LLVM  6.0.0svn
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AMDGPUBaseInfo.cpp File Reference
#include "AMDGPUBaseInfo.h"
#include "AMDGPU.h"
#include "SIDefines.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstring>
#include <utility>
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "AMDGPUGenInstrInfo.inc"
Include dependency graph for AMDGPUBaseInfo.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::AMDGPU
 
 llvm::AMDGPU::IsaInfo
 

Macros

#define GET_INSTRINFO_NAMED_OPS
 
#define MAP_REG2REG
 
#define CASE_CI_VI(node)
 
#define CASE_VI_GFX9(node)   case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
 
#define CASE_CI_VI(node)   case node##_ci: case node##_vi: return node;
 
#define CASE_VI_GFX9(node)   case node##_vi: case node##_gfx9: return node;
 

Functions

IsaVersion llvm::AMDGPU::IsaInfo::getIsaVersion (const FeatureBitset &Features)
 
void llvm::AMDGPU::IsaInfo::streamIsaVersion (const MCSubtargetInfo *STI, raw_ostream &Stream)
 Streams isa version string for given subtarget STI into Stream. More...
 
bool llvm::AMDGPU::IsaInfo::hasCodeObjectV3 (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerCU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerCU (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const FeatureBitset &Features, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const FeatureBitset &Features, unsigned WavesPerEU, bool Addressable)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const FeatureBitset &Features, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const FeatureBitset &Features, unsigned WavesPerEU)
 
void llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features)
 
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
 
int llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned llvm::AMDGPU::getVmcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::getExpcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::getLgkmcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::getWaitcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::decodeVmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeExpcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeLgkmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
void llvm::AMDGPU::decodeWaitcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
unsigned llvm::AMDGPU::encodeVmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned llvm::AMDGPU::encodeExpcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned llvm::AMDGPU::encodeLgkmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaInfo::IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
 
bool llvm::AMDGPU::isShader (CallingConv::ID cc)
 
bool llvm::AMDGPU::isCompute (CallingConv::ID cc)
 
bool llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)
 
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool llvm::AMDGPU::isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned llvm::AMDGPU::mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)
 
bool llvm::AMDGPU::isUniformMMO (const MachineMemOperand *MMO)
 
int64_t llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool llvm::AMDGPU::isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
AMDGPUAS llvm::AMDGPU::getAMDGPUAS (Triple T)
 
AMDGPUAS llvm::AMDGPU::getAMDGPUAS (const TargetMachine &TM)
 
AMDGPUAS llvm::AMDGPU::getAMDGPUAS (const Module &M)
 

Variables

static cl::opt< boolllvm::EnablePackedInlinableLiterals ("enable-packed-inlinable-literals", cl::desc("Enable packed inlinable literals (v2f16, v2i16)"), cl::init(false))
 

Macro Definition Documentation

◆ CASE_CI_VI [1/2]

#define CASE_CI_VI (   node)
Value:
assert(!isSI(STI)); \
case node: return isCI(STI) ? node##_ci : node##_vi;
bool isSI(const MCSubtargetInfo &STI)
bool isCI(const MCSubtargetInfo &STI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Definition at line 623 of file AMDGPUBaseInfo.cpp.

◆ CASE_CI_VI [2/2]

#define CASE_CI_VI (   node)    case node##_ci: case node##_vi: return node;

Definition at line 623 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9 [1/2]

#define CASE_VI_GFX9 (   node)    case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;

Definition at line 624 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9 [2/2]

#define CASE_VI_GFX9 (   node)    case node##_vi: case node##_gfx9: return node;

Definition at line 624 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 41 of file AMDGPUBaseInfo.cpp.

◆ MAP_REG2REG

#define MAP_REG2REG

Definition at line 572 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::getMCReg(), and llvm::AMDGPU::mc2PseudoReg().