LLVM  7.0.0svn
MCSubtargetInfo.h
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1 //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCSchedule.h"
23 #include <algorithm>
24 #include <cassert>
25 #include <cstdint>
26 #include <string>
27 
28 namespace llvm {
29 
30 class MCInst;
31 
32 //===----------------------------------------------------------------------===//
33 ///
34 /// Generic base class for all target subtargets.
35 ///
37  Triple TargetTriple;
38  std::string CPU; // CPU being targeted.
39  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
40  ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
41 
42  // Scheduler machine model
43  const SubtargetInfoKV *ProcSchedModels;
44  const MCWriteProcResEntry *WriteProcResTable;
45  const MCWriteLatencyEntry *WriteLatencyTable;
46  const MCReadAdvanceEntry *ReadAdvanceTable;
47  const MCSchedModel *CPUSchedModel;
48 
49  const InstrStage *Stages; // Instruction itinerary stages
50  const unsigned *OperandCycles; // Itinerary operand cycles
51  const unsigned *ForwardingPaths;
52  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
53 
54 public:
55  MCSubtargetInfo(const MCSubtargetInfo &) = default;
56  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
59  const SubtargetInfoKV *ProcSched,
60  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
61  const MCReadAdvanceEntry *RA, const InstrStage *IS,
62  const unsigned *OC, const unsigned *FP);
63  MCSubtargetInfo() = delete;
64  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
66  virtual ~MCSubtargetInfo() = default;
67 
68  const Triple &getTargetTriple() const { return TargetTriple; }
69  StringRef getCPU() const { return CPU; }
70 
71  const FeatureBitset& getFeatureBits() const { return FeatureBits; }
72  void setFeatureBits(const FeatureBitset &FeatureBits_) {
73  FeatureBits = FeatureBits_;
74  }
75 
76  bool hasFeature(unsigned Feature) const {
77  return FeatureBits[Feature];
78  }
79 
80 protected:
81  /// Initialize the scheduling model and feature bits.
82  ///
83  /// FIXME: Find a way to stick this in the constructor, since it should only
84  /// be called during initialization.
86 
87 public:
88  /// Set the features to the default for the given CPU with an appended feature
89  /// string.
91 
92  /// Toggle a feature and return the re-computed feature bits.
93  /// This version does not change the implied bits.
94  FeatureBitset ToggleFeature(uint64_t FB);
95 
96  /// Toggle a feature and return the re-computed feature bits.
97  /// This version does not change the implied bits.
99 
100  /// Toggle a set of features and return the re-computed feature bits.
101  /// This version will also change all implied bits.
103 
104  /// Apply a feature flag and return the re-computed feature bits, including
105  /// all feature bits implied by the flag.
107 
108  /// Check whether the subtarget features are enabled/disabled as per
109  /// the provided string, ignoring all other features.
110  bool checkFeatures(StringRef FS) const;
111 
112  /// Get the machine model of a CPU.
113  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
114 
115  /// Get the machine model for this subtarget's CPU.
116  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
117 
118  /// Return an iterator at the first process resource consumed by the given
119  /// scheduling class.
121  const MCSchedClassDesc *SC) const {
122  return &WriteProcResTable[SC->WriteProcResIdx];
123  }
125  const MCSchedClassDesc *SC) const {
127  }
128 
130  unsigned DefIdx) const {
131  assert(DefIdx < SC->NumWriteLatencyEntries &&
132  "MachineModel does not specify a WriteResource for DefIdx");
133 
134  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
135  }
136 
137  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
138  unsigned WriteResID) const {
139  // TODO: The number of read advance entries in a class can be significant
140  // (~50). Consider compressing the WriteID into a dense ID of those that are
141  // used by ReadAdvance and representing them as a bitset.
142  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
143  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
144  if (I->UseIdx < UseIdx)
145  continue;
146  if (I->UseIdx > UseIdx)
147  break;
148  // Find the first WriteResIdx match, which has the highest cycle count.
149  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
150  return I->Cycles;
151  }
152  }
153  return 0;
154  }
155 
156  /// Get scheduling itinerary of a CPU.
158 
159  /// Initialize an InstrItineraryData instance.
160  void initInstrItins(InstrItineraryData &InstrItins) const;
161 
162  /// Resolve a variant scheduling class for the given MCInst and CPU.
163  virtual unsigned
164  resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
165  unsigned CPUID) const {
166  return 0;
167  }
168 
169  /// Check whether the CPU string is valid.
170  bool isCPUStringValid(StringRef CPU) const {
171  auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
172  return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
173  }
174 
175  /// Returns string representation of scheduler comment
176  virtual std::string getSchedInfoStr(MCInst const &MCI) const {
177  return {};
178  }
179 };
180 
181 } // end namespace llvm
182 
183 #endif // LLVM_MC_MCSUBTARGETINFO_H
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void setFeatureBits(const FeatureBitset &FeatureBits_)
iterator begin() const
Definition: ArrayRef.h:137
uint16_t NumReadAdvanceEntries
Definition: MCSchedule.h:125
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Used to provide key value pairs for CPU and arbitrary pointers.
const Triple & getTargetTriple() const
SI optimize exec mask operations pre RA
virtual std::string getSchedInfoStr(MCInst const &MCI) const
Returns string representation of scheduler comment.
const FeatureBitset & getFeatureBits() const
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
uint16_t NumWriteProcResEntries
Definition: MCSchedule.h:121
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1004
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
virtual ~MCSubtargetInfo()=default
Container class for subtarget features.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:64
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:110
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
iterator end() const
Definition: ArrayRef.h:138
CHAIN = SC CHAIN, Imm128 - System call.
StringRef getCPU() const
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:95
These values represent a non-pipelined step in the execution of an instruction.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasFeature(unsigned Feature) const
Generic base class for all target subtargets.
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:247
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
void setDefaultFeatures(StringRef CPU, StringRef FS)
Set the features to the default for the given CPU with an appended feature string.