LLVM  9.0.0svn
MCSubtargetInfo.h
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1 //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the subtarget options of a Target machine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_MC_MCSUBTARGETINFO_H
14 #define LLVM_MC_MCSUBTARGETINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCSchedule.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 #include <string>
26 
27 namespace llvm {
28 
29 class MCInst;
30 
31 //===----------------------------------------------------------------------===//
32 ///
33 /// Generic base class for all target subtargets.
34 ///
36  Triple TargetTriple;
37  std::string CPU; // CPU being targeted.
38  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
39  ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
40 
41  // Scheduler machine model
42  const SubtargetInfoKV *ProcSchedModels;
43  const MCWriteProcResEntry *WriteProcResTable;
44  const MCWriteLatencyEntry *WriteLatencyTable;
45  const MCReadAdvanceEntry *ReadAdvanceTable;
46  const MCSchedModel *CPUSchedModel;
47 
48  const InstrStage *Stages; // Instruction itinerary stages
49  const unsigned *OperandCycles; // Itinerary operand cycles
50  const unsigned *ForwardingPaths;
51  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
52 
53 public:
54  MCSubtargetInfo(const MCSubtargetInfo &) = default;
55  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
58  const SubtargetInfoKV *ProcSched,
59  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
60  const MCReadAdvanceEntry *RA, const InstrStage *IS,
61  const unsigned *OC, const unsigned *FP);
62  MCSubtargetInfo() = delete;
63  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
65  virtual ~MCSubtargetInfo() = default;
66 
67  const Triple &getTargetTriple() const { return TargetTriple; }
68  StringRef getCPU() const { return CPU; }
69 
70  const FeatureBitset& getFeatureBits() const { return FeatureBits; }
71  void setFeatureBits(const FeatureBitset &FeatureBits_) {
72  FeatureBits = FeatureBits_;
73  }
74 
75  bool hasFeature(unsigned Feature) const {
76  return FeatureBits[Feature];
77  }
78 
79 protected:
80  /// Initialize the scheduling model and feature bits.
81  ///
82  /// FIXME: Find a way to stick this in the constructor, since it should only
83  /// be called during initialization.
85 
86 public:
87  /// Set the features to the default for the given CPU with an appended feature
88  /// string.
90 
91  /// Toggle a feature and return the re-computed feature bits.
92  /// This version does not change the implied bits.
93  FeatureBitset ToggleFeature(uint64_t FB);
94 
95  /// Toggle a feature and return the re-computed feature bits.
96  /// This version does not change the implied bits.
98 
99  /// Toggle a set of features and return the re-computed feature bits.
100  /// This version will also change all implied bits.
102 
103  /// Apply a feature flag and return the re-computed feature bits, including
104  /// all feature bits implied by the flag.
106 
107  /// Check whether the subtarget features are enabled/disabled as per
108  /// the provided string, ignoring all other features.
109  bool checkFeatures(StringRef FS) const;
110 
111  /// Get the machine model of a CPU.
112  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
113 
114  /// Get the machine model for this subtarget's CPU.
115  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
116 
117  /// Return an iterator at the first process resource consumed by the given
118  /// scheduling class.
120  const MCSchedClassDesc *SC) const {
121  return &WriteProcResTable[SC->WriteProcResIdx];
122  }
124  const MCSchedClassDesc *SC) const {
126  }
127 
129  unsigned DefIdx) const {
130  assert(DefIdx < SC->NumWriteLatencyEntries &&
131  "MachineModel does not specify a WriteResource for DefIdx");
132 
133  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
134  }
135 
136  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
137  unsigned WriteResID) const {
138  // TODO: The number of read advance entries in a class can be significant
139  // (~50). Consider compressing the WriteID into a dense ID of those that are
140  // used by ReadAdvance and representing them as a bitset.
141  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
142  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
143  if (I->UseIdx < UseIdx)
144  continue;
145  if (I->UseIdx > UseIdx)
146  break;
147  // Find the first WriteResIdx match, which has the highest cycle count.
148  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
149  return I->Cycles;
150  }
151  }
152  return 0;
153  }
154 
155  /// Get scheduling itinerary of a CPU.
157 
158  /// Initialize an InstrItineraryData instance.
159  void initInstrItins(InstrItineraryData &InstrItins) const;
160 
161  /// Resolve a variant scheduling class for the given MCInst and CPU.
162  virtual unsigned
163  resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
164  unsigned CPUID) const {
165  return 0;
166  }
167 
168  /// Check whether the CPU string is valid.
169  bool isCPUStringValid(StringRef CPU) const {
170  auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
171  return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
172  }
173 
174  /// Returns string representation of scheduler comment
175  virtual std::string getSchedInfoStr(MCInst const &MCI) const {
176  return {};
177  }
178 };
179 
180 } // end namespace llvm
181 
182 #endif // LLVM_MC_MCSUBTARGETINFO_H
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void setFeatureBits(const FeatureBitset &FeatureBits_)
iterator begin() const
Definition: ArrayRef.h:136
uint16_t NumReadAdvanceEntries
Definition: MCSchedule.h:124
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Used to provide key value pairs for CPU and arbitrary pointers.
const Triple & getTargetTriple() const
SI optimize exec mask operations pre RA
virtual std::string getSchedInfoStr(MCInst const &MCI) const
Returns string representation of scheduler comment.
const FeatureBitset & getFeatureBits() const
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
uint16_t NumWriteProcResEntries
Definition: MCSchedule.h:120
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1281
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
virtual ~MCSubtargetInfo()=default
Container class for subtarget features.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:109
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
iterator end() const
Definition: ArrayRef.h:137
CHAIN = SC CHAIN, Imm128 - System call.
StringRef getCPU() const
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
These values represent a non-pipelined step in the execution of an instruction.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasFeature(unsigned Feature) const
Generic base class for all target subtargets.
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:243
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
void setDefaultFeatures(StringRef CPU, StringRef FS)
Set the features to the default for the given CPU with an appended feature string.