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MCSubtargetInfo.h
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1 //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCSchedule.h"
23 #include <algorithm>
24 #include <cassert>
25 #include <cstdint>
26 #include <string>
27 
28 namespace llvm {
29 
30 class MachineInstr;
31 class MCInst;
32 
33 //===----------------------------------------------------------------------===//
34 ///
35 /// MCSubtargetInfo - Generic base class for all target subtargets.
36 ///
38  Triple TargetTriple; // Target triple
39  std::string CPU; // CPU being targeted.
40  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
41  ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
42 
43  // Scheduler machine model
44  const SubtargetInfoKV *ProcSchedModels;
45  const MCWriteProcResEntry *WriteProcResTable;
46  const MCWriteLatencyEntry *WriteLatencyTable;
47  const MCReadAdvanceEntry *ReadAdvanceTable;
48  const MCSchedModel *CPUSchedModel;
49 
50  const InstrStage *Stages; // Instruction itinerary stages
51  const unsigned *OperandCycles; // Itinerary operand cycles
52  const unsigned *ForwardingPaths; // Forwarding paths
53  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
54 
55 public:
56  MCSubtargetInfo(const MCSubtargetInfo &) = default;
57  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
60  const SubtargetInfoKV *ProcSched,
61  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
62  const MCReadAdvanceEntry *RA, const InstrStage *IS,
63  const unsigned *OC, const unsigned *FP);
64  MCSubtargetInfo() = delete;
65  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
67  virtual ~MCSubtargetInfo() = default;
68 
69  /// getTargetTriple - Return the target triple string.
70  const Triple &getTargetTriple() const { return TargetTriple; }
71 
72  /// getCPU - Return the CPU string.
73  StringRef getCPU() const {
74  return CPU;
75  }
76 
77  /// getFeatureBits - Return the feature bits.
78  ///
79  const FeatureBitset& getFeatureBits() const {
80  return FeatureBits;
81  }
82 
83  /// setFeatureBits - Set the feature bits.
84  ///
85  void setFeatureBits(const FeatureBitset &FeatureBits_) {
86  FeatureBits = FeatureBits_;
87  }
88 
89  bool hasFeature(unsigned Feature) const {
90  return FeatureBits[Feature];
91  }
92 
93 protected:
94  /// Initialize the scheduling model and feature bits.
95  ///
96  /// FIXME: Find a way to stick this in the constructor, since it should only
97  /// be called during initialization.
99 
100 public:
101  /// Set the features to the default for the given CPU with an appended feature
102  /// string.
103  void setDefaultFeatures(StringRef CPU, StringRef FS);
104 
105  /// ToggleFeature - Toggle a feature and returns the re-computed feature
106  /// bits. This version does not change the implied bits.
107  FeatureBitset ToggleFeature(uint64_t FB);
108 
109  /// ToggleFeature - Toggle a feature and returns the re-computed feature
110  /// bits. This version does not change the implied bits.
112 
113  /// ToggleFeature - Toggle a set of features and returns the re-computed
114  /// feature bits. This version will also change all implied bits.
116 
117  /// Apply a feature flag and return the re-computed feature bits, including
118  /// all feature bits implied by the flag.
120 
121  /// Check whether the subtarget features are enabled/disabled as per
122  /// the provided string, ignoring all other features.
123  bool checkFeatures(StringRef FS) const;
124 
125  /// getSchedModelForCPU - Get the machine model of a CPU.
126  ///
127  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
128 
129  /// Get the machine model for this subtarget's CPU.
130  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
131 
132  /// Return an iterator at the first process resource consumed by the given
133  /// scheduling class.
135  const MCSchedClassDesc *SC) const {
136  return &WriteProcResTable[SC->WriteProcResIdx];
137  }
139  const MCSchedClassDesc *SC) const {
141  }
142 
144  unsigned DefIdx) const {
145  assert(DefIdx < SC->NumWriteLatencyEntries &&
146  "MachineModel does not specify a WriteResource for DefIdx");
147 
148  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
149  }
150 
151  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
152  unsigned WriteResID) const {
153  // TODO: The number of read advance entries in a class can be significant
154  // (~50). Consider compressing the WriteID into a dense ID of those that are
155  // used by ReadAdvance and representing them as a bitset.
156  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
157  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
158  if (I->UseIdx < UseIdx)
159  continue;
160  if (I->UseIdx > UseIdx)
161  break;
162  // Find the first WriteResIdx match, which has the highest cycle count.
163  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
164  return I->Cycles;
165  }
166  }
167  return 0;
168  }
169 
170  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
171  ///
173 
174  /// Initialize an InstrItineraryData instance.
175  void initInstrItins(InstrItineraryData &InstrItins) const;
176 
177  /// Check whether the CPU string is valid.
178  bool isCPUStringValid(StringRef CPU) const {
179  auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
180  return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
181  }
182 
183  /// Returns string representation of scheduler comment
184  virtual std::string getSchedInfoStr(const MachineInstr &MI) const {
185  return {};
186  }
187 
188  virtual std::string getSchedInfoStr(MCInst const &MCI) const {
189  return {};
190  }
191 };
192 
193 } // end namespace llvm
194 
195 #endif // LLVM_MC_MCSUBTARGETINFO_H
unsigned NumWriteProcResEntries
Definition: MCSchedule.h:112
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void setFeatureBits(const FeatureBitset &FeatureBits_)
setFeatureBits - Set the feature bits.
iterator begin() const
Definition: ArrayRef.h:137
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Used to provide key value pairs for CPU and arbitrary pointers.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
SI optimize exec mask operations pre RA
virtual std::string getSchedInfoStr(MCInst const &MCI) const
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
getSchedModelForCPU - Get the machine model of a CPU.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:904
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
unsigned NumReadAdvanceEntries
Definition: MCSchedule.h:116
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
FeatureBitset ToggleFeature(uint64_t FB)
ToggleFeature - Toggle a feature and returns the re-computed feature bits.
virtual ~MCSubtargetInfo()=default
Container class for subtarget features.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
iterator end() const
Definition: ArrayRef.h:138
CHAIN = SC CHAIN, Imm128 - System call.
StringRef getCPU() const
getCPU - Return the CPU string.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:86
Representation of each machine instruction.
Definition: MachineInstr.h:60
These values represent a non-pipelined step in the execution of an instruction.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasFeature(unsigned Feature) const
MCSubtargetInfo - Generic base class for all target subtargets.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
virtual std::string getSchedInfoStr(const MachineInstr &MI) const
Returns string representation of scheduler comment.
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
void setDefaultFeatures(StringRef CPU, StringRef FS)
Set the features to the default for the given CPU with an appended feature string.