LLVM  7.0.0svn
SIOptimizeExecMaskingPreRA.cpp
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1 //===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This pass removes redundant S_OR_B64 instructions enabling lanes in
12 /// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
13 /// vector instructions between them we can only keep outer SI_END_CF, given
14 /// that CFG is structured and exec bits of the outer end statement are always
15 /// not less than exec bit of the inner one.
16 ///
17 /// This needs to be done before the RA to eliminate saved exec bits registers
18 /// but after register coalescer to have no vector registers copies in between
19 /// of different end cf statements.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #include "AMDGPU.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
32 
33 namespace {
34 
35 class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
36 public:
37  static char ID;
38 
39 public:
40  SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
42  }
43 
44  bool runOnMachineFunction(MachineFunction &MF) override;
45 
46  StringRef getPassName() const override {
47  return "SI optimize exec mask operations pre-RA";
48  }
49 
50  void getAnalysisUsage(AnalysisUsage &AU) const override {
52  AU.setPreservesAll();
54  }
55 };
56 
57 } // End anonymous namespace.
58 
59 INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
60  "SI optimize exec mask operations pre-RA", false, false)
62 INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
63  "SI optimize exec mask operations pre-RA", false, false)
64 
65 char SIOptimizeExecMaskingPreRA::ID = 0;
66 
67 char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
68 
70  return new SIOptimizeExecMaskingPreRA();
71 }
72 
73 static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
74  return MI.getOpcode() == AMDGPU::S_OR_B64 &&
75  MI.modifiesRegister(AMDGPU::EXEC, TRI);
76 }
77 
78 static bool isFullExecCopy(const MachineInstr& MI) {
79  return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
80 }
81 
82 static unsigned getOrNonExecReg(const MachineInstr &MI,
83  const SIInstrInfo &TII) {
84  auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
85  if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
86  return Op->getReg();
87  Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
88  if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
89  return Op->getReg();
90  return AMDGPU::NoRegister;
91 }
92 
94  const SIInstrInfo &TII,
95  const MachineRegisterInfo &MRI) {
96  auto SavedExec = getOrNonExecReg(MI, TII);
97  if (SavedExec == AMDGPU::NoRegister)
98  return nullptr;
99  auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);
100  if (!SaveExecInst || !isFullExecCopy(*SaveExecInst))
101  return nullptr;
102  return SaveExecInst;
103 }
104 
105 bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
106  if (skipFunction(MF.getFunction()))
107  return false;
108 
109  const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
110  const SIRegisterInfo *TRI = ST.getRegisterInfo();
111  const SIInstrInfo *TII = ST.getInstrInfo();
113  LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
114  DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
115  bool Changed = false;
116 
117  for (MachineBasicBlock &MBB : MF) {
118 
119  // Try to remove unneeded instructions before s_endpgm.
120  if (MBB.succ_empty()) {
121  if (MBB.empty() || MBB.back().getOpcode() != AMDGPU::S_ENDPGM)
122  continue;
123 
124  SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
125 
126  while (!Blocks.empty()) {
127  auto CurBB = Blocks.pop_back_val();
128  auto I = CurBB->rbegin(), E = CurBB->rend();
129  if (I != E) {
130  if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
131  ++I;
132  else if (I->isBranch())
133  continue;
134  }
135 
136  while (I != E) {
137  if (I->isDebugValue()) {
138  I = std::next(I);
139  continue;
140  }
141 
142  if (I->mayStore() || I->isBarrier() || I->isCall() ||
143  I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
144  break;
145 
146  DEBUG(dbgs() << "Removing no effect instruction: " << *I << '\n');
147 
148  for (auto &Op : I->operands()) {
149  if (Op.isReg())
150  RecalcRegs.insert(Op.getReg());
151  }
152 
153  auto Next = std::next(I);
155  I->eraseFromParent();
156  I = Next;
157 
158  Changed = true;
159  }
160 
161  if (I != E)
162  continue;
163 
164  // Try to ascend predecessors.
165  for (auto *Pred : CurBB->predecessors()) {
166  if (Pred->succ_size() == 1)
167  Blocks.push_back(Pred);
168  }
169  }
170  continue;
171  }
172 
173  // Try to collapse adjacent endifs.
174  auto Lead = MBB.begin(), E = MBB.end();
175  if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI))
176  continue;
177 
178  const MachineBasicBlock* Succ = *MBB.succ_begin();
179  if (!MBB.isLayoutSuccessor(Succ))
180  continue;
181 
182  auto I = std::next(Lead);
183 
184  for ( ; I != E; ++I)
185  if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))
186  break;
187 
188  if (I != E)
189  continue;
190 
191  const auto NextLead = Succ->begin();
192  if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) ||
193  !getOrExecSource(*NextLead, *TII, MRI))
194  continue;
195 
196  DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
197 
198  auto SaveExec = getOrExecSource(*Lead, *TII, MRI);
199  unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII);
200  for (auto &Op : Lead->operands()) {
201  if (Op.isReg())
202  RecalcRegs.insert(Op.getReg());
203  }
204 
205  LIS->RemoveMachineInstrFromMaps(*Lead);
206  Lead->eraseFromParent();
207  if (SaveExecReg) {
208  LIS->removeInterval(SaveExecReg);
209  LIS->createAndComputeVirtRegInterval(SaveExecReg);
210  }
211 
212  Changed = true;
213 
214  // If the only use of saved exec in the removed instruction is S_AND_B64
215  // fold the copy now.
216  if (!SaveExec || !SaveExec->isFullCopy())
217  continue;
218 
219  unsigned SavedExec = SaveExec->getOperand(0).getReg();
220  bool SafeToReplace = true;
221  for (auto& U : MRI.use_nodbg_instructions(SavedExec)) {
222  if (U.getParent() != SaveExec->getParent()) {
223  SafeToReplace = false;
224  break;
225  }
226 
227  DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n');
228  }
229 
230  if (SafeToReplace) {
231  LIS->RemoveMachineInstrFromMaps(*SaveExec);
232  SaveExec->eraseFromParent();
233  MRI.replaceRegWith(SavedExec, AMDGPU::EXEC);
234  LIS->removeInterval(SavedExec);
235  }
236  }
237 
238  if (Changed) {
239  for (auto Reg : RecalcRegs) {
241  LIS->removeInterval(Reg);
242  if (!MRI.reg_empty(Reg))
244  } else {
245  for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U)
246  LIS->removeRegUnit(*U);
247  }
248  }
249  }
250 
251  return Changed;
252 }
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:968
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
AMDGPU specific subclass of TargetSubtarget.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const SIInstrInfo * getInstrInfo() const override
static bool isFullExecCopy(const MachineInstr &MI)
SI optimize exec mask operations pre RA
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
char & SIOptimizeExecMaskingPreRAID
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE, "SI optimize exec mask operations pre-RA", false, false) INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA
bool isFullCopy() const
Definition: MachineInstr.h:864
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
static MachineInstr * getOrExecSource(const MachineInstr &MI, const SIInstrInfo &TII, const MachineRegisterInfo &MRI)
SI optimize exec mask operations
static unsigned getOrNonExecReg(const MachineInstr &MI, const SIInstrInfo &TII)
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void removeInterval(unsigned Reg)
Interval removal.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
void removeRegUnit(unsigned Unit)
Remove computed live range for register unit Unit.
const SIRegisterInfo * getRegisterInfo() const override
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:294
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:383
static bool isEndCF(const MachineInstr &MI, const SIRegisterInfo *TRI)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void setPreservesAll()
Set by analyses that do not transform their input at all.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
#define DEBUG_TYPE
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)