LLVM  8.0.0svn
SIOptimizeExecMaskingPreRA.cpp
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1 //===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This pass removes redundant S_OR_B64 instructions enabling lanes in
12 /// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
13 /// vector instructions between them we can only keep outer SI_END_CF, given
14 /// that CFG is structured and exec bits of the outer end statement are always
15 /// not less than exec bit of the inner one.
16 ///
17 /// This needs to be done before the RA to eliminate saved exec bits registers
18 /// but after register coalescer to have no vector registers copies in between
19 /// of different end cf statements.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #include "AMDGPU.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
33 
34 namespace {
35 
36 class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
37 public:
38  static char ID;
39 
40 public:
41  SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
43  }
44 
45  bool runOnMachineFunction(MachineFunction &MF) override;
46 
47  StringRef getPassName() const override {
48  return "SI optimize exec mask operations pre-RA";
49  }
50 
51  void getAnalysisUsage(AnalysisUsage &AU) const override {
53  AU.setPreservesAll();
55  }
56 };
57 
58 } // End anonymous namespace.
59 
60 INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
61  "SI optimize exec mask operations pre-RA", false, false)
63 INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
64  "SI optimize exec mask operations pre-RA", false, false)
65 
66 char SIOptimizeExecMaskingPreRA::ID = 0;
67 
68 char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
69 
71  return new SIOptimizeExecMaskingPreRA();
72 }
73 
74 static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
75  return MI.getOpcode() == AMDGPU::S_OR_B64 &&
76  MI.modifiesRegister(AMDGPU::EXEC, TRI);
77 }
78 
79 static bool isFullExecCopy(const MachineInstr& MI) {
80  return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
81 }
82 
83 static unsigned getOrNonExecReg(const MachineInstr &MI,
84  const SIInstrInfo &TII) {
85  auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
86  if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
87  return Op->getReg();
88  Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
89  if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
90  return Op->getReg();
91  return AMDGPU::NoRegister;
92 }
93 
95  const SIInstrInfo &TII,
96  const MachineRegisterInfo &MRI) {
97  auto SavedExec = getOrNonExecReg(MI, TII);
98  if (SavedExec == AMDGPU::NoRegister)
99  return nullptr;
100  auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);
101  if (!SaveExecInst || !isFullExecCopy(*SaveExecInst))
102  return nullptr;
103  return SaveExecInst;
104 }
105 
106 bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
107  if (skipFunction(MF.getFunction()))
108  return false;
109 
110  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
111  const SIRegisterInfo *TRI = ST.getRegisterInfo();
112  const SIInstrInfo *TII = ST.getInstrInfo();
114  LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
115  DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
116  bool Changed = false;
117 
118  for (MachineBasicBlock &MBB : MF) {
119 
120  // Try to remove unneeded instructions before s_endpgm.
121  if (MBB.succ_empty()) {
122  if (MBB.empty())
123  continue;
124 
125  // Skip this if the endpgm has any implicit uses, otherwise we would need
126  // to be careful to update / remove them.
127  MachineInstr &Term = MBB.back();
128  if (Term.getOpcode() != AMDGPU::S_ENDPGM ||
129  Term.getNumOperands() != 0)
130  continue;
131 
132  SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
133 
134  while (!Blocks.empty()) {
135  auto CurBB = Blocks.pop_back_val();
136  auto I = CurBB->rbegin(), E = CurBB->rend();
137  if (I != E) {
138  if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
139  ++I;
140  else if (I->isBranch())
141  continue;
142  }
143 
144  while (I != E) {
145  if (I->isDebugInstr()) {
146  I = std::next(I);
147  continue;
148  }
149 
150  if (I->mayStore() || I->isBarrier() || I->isCall() ||
151  I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
152  break;
153 
154  LLVM_DEBUG(dbgs()
155  << "Removing no effect instruction: " << *I << '\n');
156 
157  for (auto &Op : I->operands()) {
158  if (Op.isReg())
159  RecalcRegs.insert(Op.getReg());
160  }
161 
162  auto Next = std::next(I);
164  I->eraseFromParent();
165  I = Next;
166 
167  Changed = true;
168  }
169 
170  if (I != E)
171  continue;
172 
173  // Try to ascend predecessors.
174  for (auto *Pred : CurBB->predecessors()) {
175  if (Pred->succ_size() == 1)
176  Blocks.push_back(Pred);
177  }
178  }
179  continue;
180  }
181 
182  // Try to collapse adjacent endifs.
183  auto Lead = MBB.begin(), E = MBB.end();
184  if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI))
185  continue;
186 
187  const MachineBasicBlock* Succ = *MBB.succ_begin();
188  if (!MBB.isLayoutSuccessor(Succ))
189  continue;
190 
191  auto I = std::next(Lead);
192 
193  for ( ; I != E; ++I)
194  if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))
195  break;
196 
197  if (I != E)
198  continue;
199 
200  const auto NextLead = Succ->begin();
201  if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) ||
202  !getOrExecSource(*NextLead, *TII, MRI))
203  continue;
204 
205  LLVM_DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
206 
207  auto SaveExec = getOrExecSource(*Lead, *TII, MRI);
208  unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII);
209  for (auto &Op : Lead->operands()) {
210  if (Op.isReg())
211  RecalcRegs.insert(Op.getReg());
212  }
213 
214  LIS->RemoveMachineInstrFromMaps(*Lead);
215  Lead->eraseFromParent();
216  if (SaveExecReg) {
217  LIS->removeInterval(SaveExecReg);
218  LIS->createAndComputeVirtRegInterval(SaveExecReg);
219  }
220 
221  Changed = true;
222 
223  // If the only use of saved exec in the removed instruction is S_AND_B64
224  // fold the copy now.
225  if (!SaveExec || !SaveExec->isFullCopy())
226  continue;
227 
228  unsigned SavedExec = SaveExec->getOperand(0).getReg();
229  bool SafeToReplace = true;
230  for (auto& U : MRI.use_nodbg_instructions(SavedExec)) {
231  if (U.getParent() != SaveExec->getParent()) {
232  SafeToReplace = false;
233  break;
234  }
235 
236  LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n');
237  }
238 
239  if (SafeToReplace) {
240  LIS->RemoveMachineInstrFromMaps(*SaveExec);
241  SaveExec->eraseFromParent();
242  MRI.replaceRegWith(SavedExec, AMDGPU::EXEC);
243  LIS->removeInterval(SavedExec);
244  }
245  }
246 
247  if (Changed) {
248  for (auto Reg : RecalcRegs) {
250  LIS->removeInterval(Reg);
251  if (!MRI.reg_empty(Reg))
253  } else {
254  for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U)
255  LIS->removeRegUnit(*U);
256  }
257  }
258  }
259 
260  return Changed;
261 }
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
AMDGPU specific subclass of TargetSubtarget.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
const SIInstrInfo * getInstrInfo() const override
unsigned const TargetRegisterInfo * TRI
static bool isFullExecCopy(const MachineInstr &MI)
SI optimize exec mask operations pre RA
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:412
char & SIOptimizeExecMaskingPreRAID
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE, "SI optimize exec mask operations pre-RA", false, false) INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA
bool isFullCopy() const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
static MachineInstr * getOrExecSource(const MachineInstr &MI, const SIInstrInfo &TII, const MachineRegisterInfo &MRI)
SI optimize exec mask operations
static unsigned getOrNonExecReg(const MachineInstr &MI, const SIInstrInfo &TII)
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void removeInterval(unsigned Reg)
Interval removal.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
void removeRegUnit(unsigned Unit)
Remove computed live range for register unit Unit.
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:305
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:381
static bool isEndCF(const MachineInstr &MI, const SIRegisterInfo *TRI)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void setPreservesAll()
Set by analyses that do not transform their input at all.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
#define DEBUG_TYPE
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
const SIRegisterInfo * getRegisterInfo() const override