LLVM  9.0.0svn
AMDGPUMCTargetDesc.h
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1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Provides AMDGPU specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
17 
18 #include "llvm/Support/DataTypes.h"
19 
20 #include <memory>
21 
22 namespace llvm {
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInstrInfo;
27 class MCObjectTargetWriter;
28 class MCRegisterInfo;
29 class MCSubtargetInfo;
30 class MCTargetOptions;
31 class StringRef;
32 class Target;
33 class Triple;
34 class raw_pwrite_stream;
35 
36 Target &getTheAMDGPUTarget();
37 Target &getTheGCNTarget();
38 
39 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
40  const MCRegisterInfo &MRI,
41  MCContext &Ctx);
42 MCInstrInfo *createR600MCInstrInfo();
43 
44 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
45  const MCRegisterInfo &MRI,
46  MCContext &Ctx);
47 
48 MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
49  const MCSubtargetInfo &STI,
50  const MCRegisterInfo &MRI,
51  const MCTargetOptions &Options);
52 
53 std::unique_ptr<MCObjectTargetWriter>
54 createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
55  bool HasRelocationAddend, uint8_t ABIVersion);
56 } // End llvm namespace
57 
58 #define GET_REGINFO_ENUM
59 #include "AMDGPUGenRegisterInfo.inc"
60 #undef GET_REGINFO_ENUM
61 
62 #define GET_REGINFO_ENUM
63 #include "R600GenRegisterInfo.inc"
64 #undef GET_REGINFO_ENUM
65 
66 #define GET_INSTRINFO_ENUM
67 #define GET_INSTRINFO_OPERAND_ENUM
68 #define GET_INSTRINFO_SCHED_ENUM
69 #include "AMDGPUGenInstrInfo.inc"
70 #undef GET_INSTRINFO_SCHED_ENUM
71 #undef GET_INSTRINFO_OPERAND_ENUM
72 #undef GET_INSTRINFO_ENUM
73 
74 #define GET_INSTRINFO_ENUM
75 #define GET_INSTRINFO_OPERAND_ENUM
76 #define GET_INSTRINFO_SCHED_ENUM
77 #include "R600GenInstrInfo.inc"
78 #undef GET_INSTRINFO_SCHED_ENUM
79 #undef GET_INSTRINFO_OPERAND_ENUM
80 #undef GET_INSTRINFO_ENUM
81 
82 #define GET_SUBTARGETINFO_ENUM
83 #include "AMDGPUGenSubtargetInfo.inc"
84 #undef GET_SUBTARGETINFO_ENUM
85 
86 #define GET_SUBTARGETINFO_ENUM
87 #include "R600GenSubtargetInfo.inc"
88 #undef GET_SUBTARGETINFO_ENUM
89 
90 #endif
Target & getTheGCNTarget()
The target for GCN GPUs.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCInstrInfo * createR600MCInstrInfo()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned const MachineRegisterInfo * MRI
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)