LLVM  10.0.0svn
AMDGPUMCTargetDesc.cpp
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1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file provides AMDGPU specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUMCTargetDesc.h"
15 #include "AMDGPUELFStreamer.h"
16 #include "AMDGPUInstPrinter.h"
17 #include "AMDGPUMCAsmInfo.h"
18 #include "AMDGPUTargetStreamer.h"
19 #include "SIDefines.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
33 
34 using namespace llvm;
35 
36 #define GET_INSTRINFO_MC_DESC
37 #include "AMDGPUGenInstrInfo.inc"
38 
39 #define GET_SUBTARGETINFO_MC_DESC
40 #include "AMDGPUGenSubtargetInfo.inc"
41 
42 #define NoSchedModel NoSchedModelR600
43 #define GET_SUBTARGETINFO_MC_DESC
44 #include "R600GenSubtargetInfo.inc"
45 #undef NoSchedModelR600
46 
47 #define GET_REGINFO_MC_DESC
48 #include "AMDGPUGenRegisterInfo.inc"
49 
50 #define GET_REGINFO_MC_DESC
51 #include "R600GenRegisterInfo.inc"
52 
54  MCInstrInfo *X = new MCInstrInfo();
55  InitAMDGPUMCInstrInfo(X);
56  return X;
57 }
58 
61  if (TT.getArch() == Triple::r600)
62  InitR600MCRegisterInfo(X, 0);
63  else
64  InitAMDGPUMCRegisterInfo(X, 0);
65  return X;
66 }
67 
68 static MCSubtargetInfo *
70  if (TT.getArch() == Triple::r600)
71  return createR600MCSubtargetInfoImpl(TT, CPU, FS);
72  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
73 }
74 
76  unsigned SyntaxVariant,
77  const MCAsmInfo &MAI,
78  const MCInstrInfo &MII,
79  const MCRegisterInfo &MRI) {
80  if (T.getArch() == Triple::r600)
81  return new R600InstPrinter(MAI, MII, MRI);
82  else
83  return new AMDGPUInstPrinter(MAI, MII, MRI);
84 }
85 
88  MCInstPrinter *InstPrint,
89  bool isVerboseAsm) {
90  return new AMDGPUTargetAsmStreamer(S, OS);
91 }
92 
94  MCStreamer &S,
95  const MCSubtargetInfo &STI) {
96  return new AMDGPUTargetELFStreamer(S, STI);
97 }
98 
100  std::unique_ptr<MCAsmBackend> &&MAB,
101  std::unique_ptr<MCObjectWriter> &&OW,
102  std::unique_ptr<MCCodeEmitter> &&Emitter,
103  bool RelaxAll) {
104  return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
105  std::move(Emitter), RelaxAll);
106 }
107 
108 namespace {
109 
110 class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
111 public:
112  explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
113  : MCInstrAnalysis(Info) {}
114 
115  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
116  uint64_t &Target) const override {
117  if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
118  Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
120  return false;
121 
122  int64_t Imm = Inst.getOperand(0).getImm();
123  // Our branches take a simm16, but we need two extra bits to account for
124  // the factor of 4.
125  APInt SignedOffset(18, Imm * 4, true);
126  Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
127  return true;
128  }
129 };
130 
131 } // end anonymous namespace
132 
134  return new AMDGPUMCInstrAnalysis(Info);
135 }
136 
137 extern "C" void LLVMInitializeAMDGPUTargetMC() {
138 
141  for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
143 
150  }
151 
152  // R600 specific registration
157 
158  // GCN specific registration
161 
166 }
bool isImm() const
Definition: MCInst.h:58
Target & getTheGCNTarget()
The target for GCN GPUs.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:836
LLVMContext & Context
MCInstrInfo * createR600MCInstrInfo()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Target specific streamer interface.
Definition: MCStreamer.h:84
static MCInstrInfo * createAMDGPUMCInstrInfo()
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
static MCSubtargetInfo * createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
static MCRegisterInfo * createAMDGPUMCRegisterInfo(const Triple &TT)
Context object for machine code objects.
Definition: MCContext.h:65
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
static MCInstrAnalysis * createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
void LLVMInitializeAMDGPUTargetMC()
static MCStreamer * createMCStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
static MCInstPrinter * createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:75
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Streaming machine code generation interface.
Definition: MCStreamer.h:189
unsigned const MachineRegisterInfo * MRI
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getNumOperands() const
Definition: MCInst.h:181
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static MCTargetStreamer * createAMDGPUAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
static MCTargetStreamer * createAMDGPUObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Provides AMDGPU specific target descriptions.
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
MCELFStreamer * createAMDGPUELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
RegisterMCAsmInfo - Helper template for registering a target assembly info implementation.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171