LLVM  9.0.0svn
R600MCCodeEmitter.cpp
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1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The R600 code emitter produces machine code that can be executed
12 /// directly on the GPU device.
13 //
14 //===----------------------------------------------------------------------===//
15 
18 #include "R600Defines.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCFixup.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Endian.h"
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 namespace {
36 
37 class R600MCCodeEmitter : public MCCodeEmitter {
38  const MCRegisterInfo &MRI;
39  const MCInstrInfo &MCII;
40 
41 public:
42  R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
43  : MRI(mri), MCII(mcii) {}
44  R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
45  R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;
46 
47  /// Encode the instruction and write it to the OS.
48  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
50  const MCSubtargetInfo &STI) const;
51 
52  /// \returns the encoding for an MCOperand.
53  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
55  const MCSubtargetInfo &STI) const;
56 
57 private:
58 
59  void Emit(uint32_t value, raw_ostream &OS) const;
60  void Emit(uint64_t value, raw_ostream &OS) const;
61 
62  unsigned getHWReg(unsigned regNo) const;
63 
64  uint64_t getBinaryCodeForInstr(const MCInst &MI,
66  const MCSubtargetInfo &STI) const;
67  uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
68  void verifyInstructionPredicates(const MCInst &MI,
69  uint64_t AvailableFeatures) const;
70 
71 };
72 
73 } // end anonymous namespace
74 
75 enum RegElement {
76  ELEMENT_X = 0,
80 };
81 
82 enum FCInstr {
90 };
91 
93  const MCRegisterInfo &MRI,
94  MCContext &Ctx) {
95  return new R600MCCodeEmitter(MCII, MRI);
96 }
97 
98 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
100  const MCSubtargetInfo &STI) const {
101  verifyInstructionPredicates(MI,
102  computeAvailableFeatures(STI.getFeatureBits()));
103 
104  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
105  if (MI.getOpcode() == R600::RETURN ||
106  MI.getOpcode() == R600::FETCH_CLAUSE ||
107  MI.getOpcode() == R600::ALU_CLAUSE ||
108  MI.getOpcode() == R600::BUNDLE ||
109  MI.getOpcode() == R600::KILL) {
110  return;
111  } else if (IS_VTX(Desc)) {
112  uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
113  uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
114  if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) {
115  InstWord2 |= 1 << 19; // Mega-Fetch bit
116  }
117 
118  Emit(InstWord01, OS);
119  Emit(InstWord2, OS);
120  Emit((uint32_t) 0, OS);
121  } else if (IS_TEX(Desc)) {
122  int64_t Sampler = MI.getOperand(14).getImm();
123 
124  int64_t SrcSelect[4] = {
125  MI.getOperand(2).getImm(),
126  MI.getOperand(3).getImm(),
127  MI.getOperand(4).getImm(),
128  MI.getOperand(5).getImm()
129  };
130  int64_t Offsets[3] = {
131  MI.getOperand(6).getImm() & 0x1F,
132  MI.getOperand(7).getImm() & 0x1F,
133  MI.getOperand(8).getImm() & 0x1F
134  };
135 
136  uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
137  uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
138  SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
139  SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
140  Offsets[2] << 10;
141 
142  Emit(Word01, OS);
143  Emit(Word2, OS);
144  Emit((uint32_t) 0, OS);
145  } else {
146  uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
147  if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) &&
148  ((Desc.TSFlags & R600_InstFlag::OP1) ||
149  Desc.TSFlags & R600_InstFlag::OP2)) {
150  uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
151  Inst &= ~(0x3FFULL << 39);
152  Inst |= ISAOpCode << 1;
153  }
154  Emit(Inst, OS);
155  }
156 }
157 
158 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
160 }
161 
162 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
164 }
165 
166 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
167  return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
168 }
169 
170 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
171  const MCOperand &MO,
172  SmallVectorImpl<MCFixup> &Fixups,
173  const MCSubtargetInfo &STI) const {
174  if (MO.isReg()) {
175  if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
176  return MRI.getEncodingValue(MO.getReg());
177  return getHWReg(MO.getReg());
178  }
179 
180  if (MO.isExpr()) {
181  // We put rodata at the end of code section, then map the entire
182  // code secetion as vtx buf. Thus the section relative address is the
183  // correct one.
184  // Each R600 literal instruction has two operands
185  // We can't easily get the order of the current one, so compare against
186  // the first one and adjust offset.
187  const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
188  Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
189  return 0;
190  }
191 
192  assert(MO.isImm());
193  return MO.getImm();
194 }
195 
196 #define ENABLE_INSTR_PREDICATE_VERIFIER
197 #include "R600GenMCCodeEmitter.inc"
bool isImm() const
Definition: MCInst.h:58
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isReg() const
Definition: MCInst.h:57
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1026
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
A four-byte section relative fixup.
Definition: MCFixup.h:41
#define HAS_NATIVE_OPERANDS(Flags)
Definition: R600Defines.h:52
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
#define HW_REG_MASK
Defines for extracting register information from register encoding.
Definition: R600Defines.h:55
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:99
int64_t getImm() const
Definition: MCInst.h:75
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
bool isExpr() const
Definition: MCInst.h:60
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:89
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
#define IS_TEX(desc)
Definition: R600Defines.h:62
SMLoc getLoc() const
Definition: MCInst.h:177
Provides AMDGPU specific target descriptions.
Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
#define IS_VTX(desc)
Definition: R600Defines.h:61
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr)
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34