LLVM  10.0.0svn
R600Defines.h
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1 //===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
12 
13 #include "llvm/MC/MCRegisterInfo.h"
14 
15 // Operand Flags
16 #define MO_FLAG_CLAMP (1 << 0)
17 #define MO_FLAG_NEG (1 << 1)
18 #define MO_FLAG_ABS (1 << 2)
19 #define MO_FLAG_MASK (1 << 3)
20 #define MO_FLAG_PUSH (1 << 4)
21 #define MO_FLAG_NOT_LAST (1 << 5)
22 #define MO_FLAG_LAST (1 << 6)
23 #define NUM_MO_FLAGS 7
24 
25 /// Helper for getting the operand index for the instruction flags
26 /// operand.
27 #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
28 
29 namespace R600_InstFlag {
30  enum TIF {
31  TRANS_ONLY = (1 << 0),
32  TEX = (1 << 1),
33  REDUCTION = (1 << 2),
34  FC = (1 << 3),
35  TRIG = (1 << 4),
36  OP3 = (1 << 5),
37  VECTOR = (1 << 6),
38  //FlagOperand bits 7, 8
39  NATIVE_OPERANDS = (1 << 9),
40  OP1 = (1 << 10),
41  OP2 = (1 << 11),
42  VTX_INST = (1 << 12),
43  TEX_INST = (1 << 13),
44  ALU_INST = (1 << 14),
45  LDS_1A = (1 << 15),
46  LDS_1A1D = (1 << 16),
47  IS_EXPORT = (1 << 17),
48  LDS_1A2D = (1 << 18)
49  };
50 }
51 
52 #define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
53 
54 /// Defines for extracting register information from register encoding
55 #define HW_REG_MASK 0x1ff
56 #define HW_CHAN_SHIFT 9
57 
58 #define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
59 #define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
60 
61 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
62 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
63 
64 namespace OpName {
65 
66  enum VecOps {
138  };
139 
140 }
141 
142 //===----------------------------------------------------------------------===//
143 // Config register definitions
144 //===----------------------------------------------------------------------===//
145 
146 #define R_02880C_DB_SHADER_CONTROL 0x02880C
147 #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
148 
149 // These fields are the same for all shader types and families.
150 #define S_NUM_GPRS(x) (((x) & 0xFF) << 0)
151 #define S_STACK_SIZE(x) (((x) & 0xFF) << 8)
152 //===----------------------------------------------------------------------===//
153 // R600, R700 Registers
154 //===----------------------------------------------------------------------===//
155 
156 #define R_028850_SQ_PGM_RESOURCES_PS 0x028850
157 #define R_028868_SQ_PGM_RESOURCES_VS 0x028868
158 
159 //===----------------------------------------------------------------------===//
160 // Evergreen, Northern Islands Registers
161 //===----------------------------------------------------------------------===//
162 
163 #define R_028844_SQ_PGM_RESOURCES_PS 0x028844
164 #define R_028860_SQ_PGM_RESOURCES_VS 0x028860
165 #define R_028878_SQ_PGM_RESOURCES_GS 0x028878
166 #define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
167 
168 #define R_0288E8_SQ_LDS_ALLOC 0x0288E8
169 
170 #endif