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MCRegisterInfo.h
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1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCREGISTERINFO_H
16 #define LLVM_MC_MCREGISTERINFO_H
17 
18 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/MC/LaneBitmask.h"
21 #include <cassert>
22 #include <cstdint>
23 #include <utility>
24 
25 namespace llvm {
26 
27 /// An unsigned integer type large enough to represent all physical registers,
28 /// but not necessarily virtual registers.
29 using MCPhysReg = uint16_t;
30 
31 /// MCRegisterClass - Base class of TargetRegisterClass.
33 public:
34  using iterator = const MCPhysReg*;
35  using const_iterator = const MCPhysReg*;
36 
38  const uint8_t *const RegSet;
40  const uint16_t RegsSize;
41  const uint16_t RegSetSize;
42  const uint16_t ID;
43  const int8_t CopyCost;
44  const bool Allocatable;
45 
46  /// getID() - Return the register class ID number.
47  ///
48  unsigned getID() const { return ID; }
49 
50  /// begin/end - Return all of the registers in this class.
51  ///
52  iterator begin() const { return RegsBegin; }
53  iterator end() const { return RegsBegin + RegsSize; }
54 
55  /// getNumRegs - Return the number of registers in this class.
56  ///
57  unsigned getNumRegs() const { return RegsSize; }
58 
59  /// getRegister - Return the specified register in the class.
60  ///
61  unsigned getRegister(unsigned i) const {
62  assert(i < getNumRegs() && "Register number out of range!");
63  return RegsBegin[i];
64  }
65 
66  /// contains - Return true if the specified register is included in this
67  /// register class. This does not include virtual registers.
68  bool contains(unsigned Reg) const {
69  unsigned InByte = Reg % 8;
70  unsigned Byte = Reg / 8;
71  if (Byte >= RegSetSize)
72  return false;
73  return (RegSet[Byte] & (1 << InByte)) != 0;
74  }
75 
76  /// contains - Return true if both registers are in this class.
77  bool contains(unsigned Reg1, unsigned Reg2) const {
78  return contains(Reg1) && contains(Reg2);
79  }
80 
81  /// getCopyCost - Return the cost of copying a value between two registers in
82  /// this class. A negative number means the register class is very expensive
83  /// to copy e.g. status flag register classes.
84  int getCopyCost() const { return CopyCost; }
85 
86  /// isAllocatable - Return true if this register class may be used to create
87  /// virtual registers.
88  bool isAllocatable() const { return Allocatable; }
89 };
90 
91 /// MCRegisterDesc - This record contains information about a particular
92 /// register. The SubRegs field is a zero terminated array of registers that
93 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
94 /// of AX. The SuperRegs field is a zero terminated array of registers that are
95 /// super-registers of the specific register, e.g. RAX, EAX, are
96 /// super-registers of AX.
97 ///
99  uint32_t Name; // Printable name for the reg (for debugging)
100  uint32_t SubRegs; // Sub-register set, described above
101  uint32_t SuperRegs; // Super-register set, described above
102 
103  // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
104  // sub-register in SubRegs.
106 
107  // RegUnits - Points to the list of register units. The low 4 bits holds the
108  // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
110 
111  /// Index into list with lane mask sequences. The sequence contains a lanemask
112  /// for every register unit.
114 };
115 
116 /// MCRegisterInfo base class - We assume that the target defines a static
117 /// array of MCRegisterDesc objects that represent all of the machine
118 /// registers that the target has. As such, we simply have to track a pointer
119 /// to this array so that we can turn register number into a register
120 /// descriptor.
121 ///
122 /// Note this class is designed to be a base class of TargetRegisterInfo, which
123 /// is the interface used by codegen. However, specific targets *should never*
124 /// specialize this class. MCRegisterInfo should only contain getters to access
125 /// TableGen generated physical register data. It must not be extended with
126 /// virtual methods.
127 ///
129 public:
131 
132  /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
133  /// performed with a binary search.
135  unsigned FromReg;
136  unsigned ToReg;
137 
138  bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
139  };
140 
141  /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
142  /// index, -1 in any being invalid.
144  uint16_t Offset;
145  uint16_t Size;
146  };
147 
148 private:
149  const MCRegisterDesc *Desc; // Pointer to the descriptor array
150  unsigned NumRegs; // Number of entries in the array
151  unsigned RAReg; // Return address register
152  unsigned PCReg; // Program counter register
153  const MCRegisterClass *Classes; // Pointer to the regclass array
154  unsigned NumClasses; // Number of entries in the array
155  unsigned NumRegUnits; // Number of regunits.
156  const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
157  const MCPhysReg *DiffLists; // Pointer to the difflists array
158  const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
159  // for register units.
160  const char *RegStrings; // Pointer to the string table.
161  const char *RegClassStrings; // Pointer to the class strings.
162  const uint16_t *SubRegIndices; // Pointer to the subreg lookup
163  // array.
164  const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
165  // bit ranges array.
166  unsigned NumSubRegIndices; // Number of subreg indices.
167  const uint16_t *RegEncodingTable; // Pointer to array of register
168  // encodings.
169 
170  unsigned L2DwarfRegsSize;
171  unsigned EHL2DwarfRegsSize;
172  unsigned Dwarf2LRegsSize;
173  unsigned EHDwarf2LRegsSize;
174  const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
175  const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
176  const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
177  const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
178  DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
179  DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping
180 
181 public:
182  /// DiffListIterator - Base iterator class that can traverse the
183  /// differentially encoded register and regunit lists in DiffLists.
184  /// Don't use this class directly, use one of the specialized sub-classes
185  /// defined below.
187  uint16_t Val = 0;
188  const MCPhysReg *List = nullptr;
189 
190  protected:
191  /// Create an invalid iterator. Call init() to point to something useful.
192  DiffListIterator() = default;
193 
194  /// init - Point the iterator to InitVal, decoding subsequent values from
195  /// DiffList. The iterator will initially point to InitVal, sub-classes are
196  /// responsible for skipping the seed value if it is not part of the list.
197  void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
198  Val = InitVal;
199  List = DiffList;
200  }
201 
202  /// advance - Move to the next list position, return the applied
203  /// differential. This function does not detect the end of the list, that
204  /// is the caller's responsibility (by checking for a 0 return value).
205  unsigned advance() {
206  assert(isValid() && "Cannot move off the end of the list.");
207  MCPhysReg D = *List++;
208  Val += D;
209  return D;
210  }
211 
212  public:
213  /// isValid - returns true if this iterator is not yet at the end.
214  bool isValid() const { return List; }
215 
216  /// Dereference the iterator to get the value at the current position.
217  unsigned operator*() const { return Val; }
218 
219  /// Pre-increment to move to the next position.
220  void operator++() {
221  // The end of the list is encoded as a 0 differential.
222  if (!advance())
223  List = nullptr;
224  }
225  };
226 
227  // These iterators are allowed to sub-class DiffListIterator and access
228  // internal list pointers.
229  friend class MCSubRegIterator;
230  friend class MCSubRegIndexIterator;
231  friend class MCSuperRegIterator;
232  friend class MCRegUnitIterator;
233  friend class MCRegUnitMaskIterator;
234  friend class MCRegUnitRootIterator;
235 
236  /// Initialize MCRegisterInfo, called by TableGen
237  /// auto-generated routines. *DO NOT USE*.
238  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
239  unsigned PC,
240  const MCRegisterClass *C, unsigned NC,
241  const MCPhysReg (*RURoots)[2],
242  unsigned NRU,
243  const MCPhysReg *DL,
244  const LaneBitmask *RUMS,
245  const char *Strings,
246  const char *ClassStrings,
247  const uint16_t *SubIndices,
248  unsigned NumIndices,
249  const SubRegCoveredBits *SubIdxRanges,
250  const uint16_t *RET) {
251  Desc = D;
252  NumRegs = NR;
253  RAReg = RA;
254  PCReg = PC;
255  Classes = C;
256  DiffLists = DL;
257  RegUnitMaskSequences = RUMS;
258  RegStrings = Strings;
259  RegClassStrings = ClassStrings;
260  NumClasses = NC;
261  RegUnitRoots = RURoots;
262  NumRegUnits = NRU;
263  SubRegIndices = SubIndices;
264  NumSubRegIndices = NumIndices;
265  SubRegIdxRanges = SubIdxRanges;
266  RegEncodingTable = RET;
267 
268  // Initialize DWARF register mapping variables
269  EHL2DwarfRegs = nullptr;
270  EHL2DwarfRegsSize = 0;
271  L2DwarfRegs = nullptr;
272  L2DwarfRegsSize = 0;
273  EHDwarf2LRegs = nullptr;
274  EHDwarf2LRegsSize = 0;
275  Dwarf2LRegs = nullptr;
276  Dwarf2LRegsSize = 0;
277  }
278 
279  /// Used to initialize LLVM register to Dwarf
280  /// register number mapping. Called by TableGen auto-generated routines.
281  /// *DO NOT USE*.
282  void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
283  bool isEH) {
284  if (isEH) {
285  EHL2DwarfRegs = Map;
286  EHL2DwarfRegsSize = Size;
287  } else {
288  L2DwarfRegs = Map;
289  L2DwarfRegsSize = Size;
290  }
291  }
292 
293  /// Used to initialize Dwarf register to LLVM
294  /// register number mapping. Called by TableGen auto-generated routines.
295  /// *DO NOT USE*.
296  void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
297  bool isEH) {
298  if (isEH) {
299  EHDwarf2LRegs = Map;
300  EHDwarf2LRegsSize = Size;
301  } else {
302  Dwarf2LRegs = Map;
303  Dwarf2LRegsSize = Size;
304  }
305  }
306 
307  /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
308  /// number mapping. By default the SEH register number is just the same
309  /// as the LLVM register number.
310  /// FIXME: TableGen these numbers. Currently this requires target specific
311  /// initialization code.
312  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
313  L2SEHRegs[LLVMReg] = SEHReg;
314  }
315 
316  void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
317  L2CVRegs[LLVMReg] = CVReg;
318  }
319 
320  /// This method should return the register where the return
321  /// address can be found.
322  unsigned getRARegister() const {
323  return RAReg;
324  }
325 
326  /// Return the register which is the program counter.
327  unsigned getProgramCounter() const {
328  return PCReg;
329  }
330 
331  const MCRegisterDesc &operator[](unsigned RegNo) const {
332  assert(RegNo < NumRegs &&
333  "Attempting to access record for invalid register number!");
334  return Desc[RegNo];
335  }
336 
337  /// Provide a get method, equivalent to [], but more useful with a
338  /// pointer to this object.
339  const MCRegisterDesc &get(unsigned RegNo) const {
340  return operator[](RegNo);
341  }
342 
343  /// Returns the physical register number of sub-register "Index"
344  /// for physical register RegNo. Return zero if the sub-register does not
345  /// exist.
346  unsigned getSubReg(unsigned Reg, unsigned Idx) const;
347 
348  /// Return a super-register of the specified register
349  /// Reg so its sub-register of index SubIdx is Reg.
350  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
351  const MCRegisterClass *RC) const;
352 
353  /// For a given register pair, return the sub-register index
354  /// if the second register is a sub-register of the first. Return zero
355  /// otherwise.
356  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
357 
358  /// Get the size of the bit range covered by a sub-register index.
359  /// If the index isn't continuous, return the sum of the sizes of its parts.
360  /// If the index is used to access subregisters of different sizes, return -1.
361  unsigned getSubRegIdxSize(unsigned Idx) const;
362 
363  /// Get the offset of the bit range covered by a sub-register index.
364  /// If an Offset doesn't make sense (the index isn't continuous, or is used to
365  /// access sub-registers at different offsets), return -1.
366  unsigned getSubRegIdxOffset(unsigned Idx) const;
367 
368  /// Return the human-readable symbolic target-specific name for the
369  /// specified physical register.
370  const char *getName(unsigned RegNo) const {
371  return RegStrings + get(RegNo).Name;
372  }
373 
374  /// Return the number of registers this target has (useful for
375  /// sizing arrays holding per register information)
376  unsigned getNumRegs() const {
377  return NumRegs;
378  }
379 
380  /// Return the number of sub-register indices
381  /// understood by the target. Index 0 is reserved for the no-op sub-register,
382  /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
383  unsigned getNumSubRegIndices() const {
384  return NumSubRegIndices;
385  }
386 
387  /// Return the number of (native) register units in the
388  /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
389  /// can be accessed through MCRegUnitIterator defined below.
390  unsigned getNumRegUnits() const {
391  return NumRegUnits;
392  }
393 
394  /// Map a target register to an equivalent dwarf register
395  /// number. Returns -1 if there is no equivalent value. The second
396  /// parameter allows targets to use different numberings for EH info and
397  /// debugging info.
398  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
399 
400  /// Map a dwarf register back to a target register.
401  int getLLVMRegNum(unsigned RegNum, bool isEH) const;
402 
403  /// Map a DWARF EH register back to a target register (same as
404  /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
405  /// rather than asserting that there must be one.
406  int getLLVMRegNumFromEH(unsigned RegNum) const;
407 
408  /// Map a target EH register number to an equivalent DWARF register
409  /// number.
410  int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
411 
412  /// Map a target register to an equivalent SEH register
413  /// number. Returns LLVM register number if there is no equivalent value.
414  int getSEHRegNum(unsigned RegNum) const;
415 
416  /// Map a target register to an equivalent CodeView register
417  /// number.
418  int getCodeViewRegNum(unsigned RegNum) const;
419 
420  regclass_iterator regclass_begin() const { return Classes; }
421  regclass_iterator regclass_end() const { return Classes+NumClasses; }
423  return make_range(regclass_begin(), regclass_end());
424  }
425 
426  unsigned getNumRegClasses() const {
427  return (unsigned)(regclass_end()-regclass_begin());
428  }
429 
430  /// Returns the register class associated with the enumeration
431  /// value. See class MCOperandInfo.
432  const MCRegisterClass& getRegClass(unsigned i) const {
433  assert(i < getNumRegClasses() && "Register Class ID out of range");
434  return Classes[i];
435  }
436 
437  const char *getRegClassName(const MCRegisterClass *Class) const {
438  return RegClassStrings + Class->NameIdx;
439  }
440 
441  /// Returns the encoding for RegNo
442  uint16_t getEncodingValue(unsigned RegNo) const {
443  assert(RegNo < NumRegs &&
444  "Attempting to get encoding for invalid register number!");
445  return RegEncodingTable[RegNo];
446  }
447 
448  /// Returns true if RegB is a sub-register of RegA.
449  bool isSubRegister(unsigned RegA, unsigned RegB) const {
450  return isSuperRegister(RegB, RegA);
451  }
452 
453  /// Returns true if RegB is a super-register of RegA.
454  bool isSuperRegister(unsigned RegA, unsigned RegB) const;
455 
456  /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
457  bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
458  return isSuperRegisterEq(RegB, RegA);
459  }
460 
461  /// Returns true if RegB is a super-register of RegA or if
462  /// RegB == RegA.
463  bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
464  return RegA == RegB || isSuperRegister(RegA, RegB);
465  }
466 
467  /// Returns true if RegB is a super-register or sub-register of RegA
468  /// or if RegB == RegA.
469  bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
470  return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
471  }
472 };
473 
474 //===----------------------------------------------------------------------===//
475 // Register List Iterators
476 //===----------------------------------------------------------------------===//
477 
478 // MCRegisterInfo provides lists of super-registers, sub-registers, and
479 // aliasing registers. Use these iterator classes to traverse the lists.
480 
481 /// MCSubRegIterator enumerates all sub-registers of Reg.
482 /// If IncludeSelf is set, Reg itself is included in the list.
484 public:
485  MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
486  bool IncludeSelf = false) {
487  init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
488  // Initially, the iterator points to Reg itself.
489  if (!IncludeSelf)
490  ++*this;
491  }
492 };
493 
494 /// Iterator that enumerates the sub-registers of a Reg and the associated
495 /// sub-register indices.
497  MCSubRegIterator SRIter;
498  const uint16_t *SRIndex;
499 
500 public:
501  /// Constructs an iterator that traverses subregisters and their
502  /// associated subregister indices.
503  MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
504  : SRIter(Reg, MCRI) {
505  SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
506  }
507 
508  /// Returns current sub-register.
509  unsigned getSubReg() const {
510  return *SRIter;
511  }
512 
513  /// Returns sub-register index of the current sub-register.
514  unsigned getSubRegIndex() const {
515  return *SRIndex;
516  }
517 
518  /// Returns true if this iterator is not yet at the end.
519  bool isValid() const { return SRIter.isValid(); }
520 
521  /// Moves to the next position.
522  void operator++() {
523  ++SRIter;
524  ++SRIndex;
525  }
526 };
527 
528 /// MCSuperRegIterator enumerates all super-registers of Reg.
529 /// If IncludeSelf is set, Reg itself is included in the list.
531 public:
532  MCSuperRegIterator() = default;
533 
534  MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
535  bool IncludeSelf = false) {
536  init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
537  // Initially, the iterator points to Reg itself.
538  if (!IncludeSelf)
539  ++*this;
540  }
541 };
542 
543 // Definition for isSuperRegister. Put it down here since it needs the
544 // iterator defined above in addition to the MCRegisterInfo class itself.
545 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
546  for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
547  if (*I == RegB)
548  return true;
549  return false;
550 }
551 
552 //===----------------------------------------------------------------------===//
553 // Register Units
554 //===----------------------------------------------------------------------===//
555 
556 // Register units are used to compute register aliasing. Every register has at
557 // least one register unit, but it can have more. Two registers overlap if and
558 // only if they have a common register unit.
559 //
560 // A target with a complicated sub-register structure will typically have many
561 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
562 // the number of register units in the target.
563 
564 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
565 // in ascending numerical order.
567 public:
568  /// MCRegUnitIterator - Create an iterator that traverses the register units
569  /// in Reg.
570  MCRegUnitIterator() = default;
571 
572  MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
573  assert(Reg && "Null register has no regunits");
574  // Decode the RegUnits MCRegisterDesc field.
575  unsigned RU = MCRI->get(Reg).RegUnits;
576  unsigned Scale = RU & 15;
577  unsigned Offset = RU >> 4;
578 
579  // Initialize the iterator to Reg * Scale, and the List pointer to
580  // DiffLists + Offset.
581  init(Reg * Scale, MCRI->DiffLists + Offset);
582 
583  // That may not be a valid unit, we need to advance by one to get the real
584  // unit number. The first differential can be 0 which would normally
585  // terminate the list, but since we know every register has at least one
586  // unit, we can allow a 0 differential here.
587  advance();
588  }
589 };
590 
591 /// MCRegUnitMaskIterator enumerates a list of register units and their
592 /// associated lane masks for Reg. The register units are in ascending
593 /// numerical order.
595  MCRegUnitIterator RUIter;
596  const LaneBitmask *MaskListIter;
597 
598 public:
599  MCRegUnitMaskIterator() = default;
600 
601  /// Constructs an iterator that traverses the register units and their
602  /// associated LaneMasks in Reg.
603  MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
604  : RUIter(Reg, MCRI) {
605  uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
606  MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
607  }
608 
609  /// Returns a (RegUnit, LaneMask) pair.
610  std::pair<unsigned,LaneBitmask> operator*() const {
611  return std::make_pair(*RUIter, *MaskListIter);
612  }
613 
614  /// Returns true if this iterator is not yet at the end.
615  bool isValid() const { return RUIter.isValid(); }
616 
617  /// Moves to the next position.
618  void operator++() {
619  ++MaskListIter;
620  ++RUIter;
621  }
622 };
623 
624 // Each register unit has one or two root registers. The complete set of
625 // registers containing a register unit is the union of the roots and their
626 // super-registers. All registers aliasing Unit can be visited like this:
627 //
628 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
629 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
630 // visit(*SI);
631 // }
632 
633 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
635  uint16_t Reg0 = 0;
636  uint16_t Reg1 = 0;
637 
638 public:
639  MCRegUnitRootIterator() = default;
640 
641  MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
642  assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
643  Reg0 = MCRI->RegUnitRoots[RegUnit][0];
644  Reg1 = MCRI->RegUnitRoots[RegUnit][1];
645  }
646 
647  /// Dereference to get the current root register.
648  unsigned operator*() const {
649  return Reg0;
650  }
651 
652  /// Check if the iterator is at the end of the list.
653  bool isValid() const {
654  return Reg0;
655  }
656 
657  /// Preincrement to move to the next root register.
658  void operator++() {
659  assert(isValid() && "Cannot move off the end of the list.");
660  Reg0 = Reg1;
661  Reg1 = 0;
662  }
663 };
664 
665 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
666 /// set, Reg itself is included in the list. This iterator does not guarantee
667 /// any ordering or that entries are unique.
669 private:
670  unsigned Reg;
671  const MCRegisterInfo *MCRI;
672  bool IncludeSelf;
673 
677 
678 public:
679  MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
680  bool IncludeSelf)
681  : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
682  // Initialize the iterators.
683  for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
684  for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
685  for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
686  if (!(!IncludeSelf && Reg == *SI))
687  return;
688  }
689  }
690  }
691  }
692 
693  bool isValid() const { return RI.isValid(); }
694 
695  unsigned operator*() const {
696  assert(SI.isValid() && "Cannot dereference an invalid iterator.");
697  return *SI;
698  }
699 
700  void advance() {
701  // Assuming SI is valid.
702  ++SI;
703  if (SI.isValid()) return;
704 
705  ++RRI;
706  if (RRI.isValid()) {
707  SI = MCSuperRegIterator(*RRI, MCRI, true);
708  return;
709  }
710 
711  ++RI;
712  if (RI.isValid()) {
713  RRI = MCRegUnitRootIterator(*RI, MCRI);
714  SI = MCSuperRegIterator(*RRI, MCRI, true);
715  }
716  }
717 
718  void operator++() {
719  assert(isValid() && "Cannot move off the end of the list.");
720  do advance();
721  while (!IncludeSelf && isValid() && *SI == Reg);
722  }
723 };
724 
725 } // end namespace llvm
726 
727 #endif // LLVM_MC_MCREGISTERINFO_H
bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
uint64_t CallInst * C
A common definition of LaneBitmask for use in TableGen and CodeGen.
const uint8_t *const RegSet
void operator++()
Pre-increment to move to the next position.
iterator begin() const
begin/end - Return all of the registers in this class.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const uint32_t NameIdx
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned Reg
bool contains(unsigned Reg1, unsigned Reg2) const
contains - Return true if both registers are in this class.
const MCRegisterDesc & operator[](unsigned RegNo) const
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned getID() const
getID() - Return the register class ID number.
SI optimize exec mask operations pre RA
MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
bool isValid() const
Returns true if this iterator is not yet at the end.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MCSuperRegIterator enumerates all super-registers of Reg.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
regclass_iterator regclass_begin() const
const iterator RegsBegin
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI)
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
Initialize MCRegisterInfo, called by TableGen auto-generated routines.
MCRegUnitRootIterator enumerates the root registers of a register unit.
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
DiffListIterator - Base iterator class that can traverse the differentially encoded register and regu...
MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses the register units and their associated LaneMasks in Reg...
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
void operator++()
Moves to the next position.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
unsigned operator*() const
Dereference to get the current root register.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...
unsigned getSubReg() const
Returns current sub-register.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize LLVM register to Dwarf register number mapping.
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize Dwarf register to LLVM register number mapping.
const MCPhysReg * const_iterator
MCRegAliasIterator enumerates all registers aliasing Reg.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
iterator end() const
iterator_range< regclass_iterator > regclasses() const
std::pair< unsigned, LaneBitmask > operator*() const
Returns a (RegUnit, LaneMask) pair.
MCSubRegIterator enumerates all sub-registers of Reg.
unsigned getNumRegClasses() const
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MCRegisterDesc - This record contains information about a particular register.
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
const char * getRegClassName(const MCRegisterClass *Class) const
MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses subregisters and their associated subregister indices...
bool isSubRegisterEq(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
const MCRegisterDesc & get(unsigned RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
bool isValid() const
Returns true if this iterator is not yet at the end.
MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define NC
Definition: regutils.h:42
unsigned operator*() const
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI)
A range adaptor for a pair of iterators.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool operator<(DwarfLLVMRegPair RHS) const
uint16_t RegUnitLaneMasks
Index into list with lane mask sequences.
regclass_iterator regclass_end() const
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
const uint16_t RegSetSize
const NodeList & List
Definition: RDFGraph.cpp:209
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
uint32_t Size
Definition: Profile.cpp:46
unsigned advance()
advance - Move to the next list position, return the applied differential.
void operator++()
Moves to the next position.
unsigned getRARegister() const
This method should return the register where the return address can be found.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getProgramCounter() const
Return the register which is the program counter.
void operator++()
Preincrement to move to the next root register.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:92
unsigned operator*() const
Dereference the iterator to get the value at the current position.
bool isValid() const
Check if the iterator is at the end of the list.
const MCPhysReg * iterator
const uint16_t RegsSize
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
void init(MCPhysReg InitVal, const MCPhysReg *DiffList)
init - Point the iterator to InitVal, decoding subsequent values from DiffList.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.