15 #ifndef LLVM_MC_MCREGISTERINFO_H 16 #define LLVM_MC_MCREGISTERINFO_H 67 unsigned InByte = RegNo % 8;
68 unsigned Byte = RegNo / 8;
69 if (Byte >= RegSetSize)
71 return (RegSet[Byte] & (1 << InByte)) != 0;
153 unsigned NumRegUnits;
158 const char *RegStrings;
159 const char *RegClassStrings;
160 const uint16_t *SubRegIndices;
164 unsigned NumSubRegIndices;
165 const uint16_t *RegEncodingTable;
168 unsigned L2DwarfRegsSize;
169 unsigned EHL2DwarfRegsSize;
170 unsigned Dwarf2LRegsSize;
171 unsigned EHDwarf2LRegsSize;
204 assert(isValid() &&
"Cannot move off the end of the list.");
244 const char *ClassStrings,
245 const uint16_t *SubIndices,
248 const uint16_t *
RET) {
255 RegUnitMaskSequences = RUMS;
256 RegStrings = Strings;
257 RegClassStrings = ClassStrings;
259 RegUnitRoots = RURoots;
261 SubRegIndices = SubIndices;
262 NumSubRegIndices = NumIndices;
263 SubRegIdxRanges = SubIdxRanges;
264 RegEncodingTable =
RET;
267 EHL2DwarfRegs =
nullptr;
268 EHL2DwarfRegsSize = 0;
269 L2DwarfRegs =
nullptr;
271 EHDwarf2LRegs =
nullptr;
272 EHDwarf2LRegsSize = 0;
273 Dwarf2LRegs =
nullptr;
284 EHL2DwarfRegsSize =
Size;
287 L2DwarfRegsSize =
Size;
298 EHDwarf2LRegsSize =
Size;
301 Dwarf2LRegsSize =
Size;
311 L2SEHRegs[LLVMReg] = SEHReg;
315 L2CVRegs[LLVMReg] = CVReg;
331 "Attempting to access record for invalid register number!");
338 return operator[](RegNo);
359 unsigned getSubRegIdxSize(
unsigned Idx)
const;
364 unsigned getSubRegIdxOffset(
unsigned Idx)
const;
369 return RegStrings +
get(RegNo).
Name;
382 return NumSubRegIndices;
404 int getDwarfRegNumFromDwarfEHRegNum(
unsigned RegNum)
const;
412 int getCodeViewRegNum(
MCRegister RegNum)
const;
417 return make_range(regclass_begin(), regclass_end());
421 return (
unsigned)(regclass_end()-regclass_begin());
427 assert(i < getNumRegClasses() &&
"Register Class ID out of range");
432 return RegClassStrings + Class->
NameIdx;
438 "Attempting to get encoding for invalid register number!");
439 return RegEncodingTable[RegNo];
444 return isSuperRegister(RegB, RegA);
452 return isSuperRegisterEq(RegB, RegA);
458 return RegA == RegB || isSuperRegister(RegA, RegB);
464 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
480 bool IncludeSelf =
false) {
492 const uint16_t *SRIndex;
498 : SRIter(Reg, MCRI) {
529 bool IncludeSelf =
false) {
567 assert(Reg &&
"Null register has no regunits");
570 unsigned Scale = RU & 15;
571 unsigned Offset = RU >> 4;
575 init(Reg * Scale, MCRI->DiffLists + Offset);
598 : RUIter(Reg, MCRI) {
600 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
605 return std::make_pair(*RUIter, *MaskListIter);
636 assert(RegUnit < MCRI->getNumRegUnits() &&
"Invalid register unit");
637 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
638 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
653 assert(isValid() &&
"Cannot move off the end of the list.");
675 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
680 if (!(!IncludeSelf && Reg == *SI))
690 assert(SI.
isValid() &&
"Cannot dereference an invalid iterator.");
713 assert(isValid() &&
"Cannot move off the end of the list.");
715 while (!IncludeSelf && isValid() && *SI == Reg);
721 #endif // LLVM_MC_MCREGISTERINFO_H
A common definition of LaneBitmask for use in TableGen and CodeGen.
const uint8_t *const RegSet
Wrapper class representing physical registers. Should be passed by value.
void operator++()
Pre-increment to move to the next position.
iterator begin() const
begin/end - Return all of the registers in this class.
This class represents lattice values for constants.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
const MCRegisterDesc & operator[](MCRegister RegNo) const
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
MCRegister operator*() const
MCRegister operator*() const
Dereference the iterator to get the value at the current position.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned getID() const
getID() - Return the register class ID number.
SI optimize exec mask operations pre RA
bool isValid() const
Returns true if this iterator is not yet at the end.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MCSuperRegIterator enumerates all super-registers of Reg.
regclass_iterator regclass_begin() const
MCRegister advance()
advance - Move to the next list position, return the applied differential.
void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
Initialize MCRegisterInfo, called by TableGen auto-generated routines.
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
DiffListIterator - Base iterator class that can traverse the differentially encoded register and regu...
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
void operator++()
Moves to the next position.
initializer< Ty > init(const Ty &Val)
unsigned operator*() const
Dereference to get the current root register.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...
MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize LLVM register to Dwarf register number mapping.
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize Dwarf register to LLVM register number mapping.
const MCPhysReg * const_iterator
MCRegAliasIterator enumerates all registers aliasing Reg.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
bool contains(MCRegister Reg1, MCRegister Reg2) const
contains - Return true if both registers are in this class.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
iterator_range< regclass_iterator > regclasses() const
std::pair< unsigned, LaneBitmask > operator*() const
Returns a (RegUnit, LaneMask) pair.
bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
MCSubRegIterator enumerates all sub-registers of Reg.
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
unsigned getNumRegClasses() const
MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses subregisters and their associated subregister indices...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MCRegisterDesc - This record contains information about a particular register.
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
const char * getRegClassName(const MCRegisterClass *Class) const
bool isValid() const
Returns true if this iterator is not yet at the end.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI)
MCRegister getProgramCounter() const
Return the register which is the program counter.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
A range adaptor for a pair of iterators.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
bool operator<(DwarfLLVMRegPair RHS) const
uint16_t RegUnitLaneMasks
Index into list with lane mask sequences.
regclass_iterator regclass_end() const
const uint16_t RegSetSize
MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
void operator++()
Moves to the next position.
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void operator++()
Preincrement to move to the next root register.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
MCRegister getSubReg() const
Returns current sub-register.
bool isValid() const
Check if the iterator is at the end of the list.
const MCPhysReg * iterator
MCRegister getRARegister() const
This method should return the register where the return address can be found.
MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses the register units and their associated LaneMasks in Reg...
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
void init(MCPhysReg InitVal, const MCPhysReg *DiffList)
init - Point the iterator to InitVal, decoding subsequent values from DiffList.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.