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MCRegisterInfo.h
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1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCREGISTERINFO_H
16 #define LLVM_MC_MCREGISTERINFO_H
17 
18 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/MC/LaneBitmask.h"
21 #include "llvm/MC/MCRegister.h"
22 #include <cassert>
23 #include <cstdint>
24 #include <utility>
25 
26 namespace llvm {
27 
28 /// MCRegisterClass - Base class of TargetRegisterClass.
30 public:
31  using iterator = const MCPhysReg*;
32  using const_iterator = const MCPhysReg*;
33 
35  const uint8_t *const RegSet;
37  const uint16_t RegsSize;
38  const uint16_t RegSetSize;
39  const uint16_t ID;
40  const int8_t CopyCost;
41  const bool Allocatable;
42 
43  /// getID() - Return the register class ID number.
44  ///
45  unsigned getID() const { return ID; }
46 
47  /// begin/end - Return all of the registers in this class.
48  ///
49  iterator begin() const { return RegsBegin; }
50  iterator end() const { return RegsBegin + RegsSize; }
51 
52  /// getNumRegs - Return the number of registers in this class.
53  ///
54  unsigned getNumRegs() const { return RegsSize; }
55 
56  /// getRegister - Return the specified register in the class.
57  ///
58  unsigned getRegister(unsigned i) const {
59  assert(i < getNumRegs() && "Register number out of range!");
60  return RegsBegin[i];
61  }
62 
63  /// contains - Return true if the specified register is included in this
64  /// register class. This does not include virtual registers.
65  bool contains(MCRegister Reg) const {
66  unsigned RegNo = unsigned(Reg);
67  unsigned InByte = RegNo % 8;
68  unsigned Byte = RegNo / 8;
69  if (Byte >= RegSetSize)
70  return false;
71  return (RegSet[Byte] & (1 << InByte)) != 0;
72  }
73 
74  /// contains - Return true if both registers are in this class.
75  bool contains(MCRegister Reg1, MCRegister Reg2) const {
76  return contains(Reg1) && contains(Reg2);
77  }
78 
79  /// getCopyCost - Return the cost of copying a value between two registers in
80  /// this class. A negative number means the register class is very expensive
81  /// to copy e.g. status flag register classes.
82  int getCopyCost() const { return CopyCost; }
83 
84  /// isAllocatable - Return true if this register class may be used to create
85  /// virtual registers.
86  bool isAllocatable() const { return Allocatable; }
87 };
88 
89 /// MCRegisterDesc - This record contains information about a particular
90 /// register. The SubRegs field is a zero terminated array of registers that
91 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
92 /// of AX. The SuperRegs field is a zero terminated array of registers that are
93 /// super-registers of the specific register, e.g. RAX, EAX, are
94 /// super-registers of AX.
95 ///
97  uint32_t Name; // Printable name for the reg (for debugging)
98  uint32_t SubRegs; // Sub-register set, described above
99  uint32_t SuperRegs; // Super-register set, described above
100 
101  // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
102  // sub-register in SubRegs.
104 
105  // RegUnits - Points to the list of register units. The low 4 bits holds the
106  // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
108 
109  /// Index into list with lane mask sequences. The sequence contains a lanemask
110  /// for every register unit.
112 };
113 
114 /// MCRegisterInfo base class - We assume that the target defines a static
115 /// array of MCRegisterDesc objects that represent all of the machine
116 /// registers that the target has. As such, we simply have to track a pointer
117 /// to this array so that we can turn register number into a register
118 /// descriptor.
119 ///
120 /// Note this class is designed to be a base class of TargetRegisterInfo, which
121 /// is the interface used by codegen. However, specific targets *should never*
122 /// specialize this class. MCRegisterInfo should only contain getters to access
123 /// TableGen generated physical register data. It must not be extended with
124 /// virtual methods.
125 ///
127 public:
129 
130  /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
131  /// performed with a binary search.
133  unsigned FromReg;
134  unsigned ToReg;
135 
136  bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
137  };
138 
139  /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
140  /// index, -1 in any being invalid.
142  uint16_t Offset;
143  uint16_t Size;
144  };
145 
146 private:
147  const MCRegisterDesc *Desc; // Pointer to the descriptor array
148  unsigned NumRegs; // Number of entries in the array
149  MCRegister RAReg; // Return address register
150  MCRegister PCReg; // Program counter register
151  const MCRegisterClass *Classes; // Pointer to the regclass array
152  unsigned NumClasses; // Number of entries in the array
153  unsigned NumRegUnits; // Number of regunits.
154  const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
155  const MCPhysReg *DiffLists; // Pointer to the difflists array
156  const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
157  // for register units.
158  const char *RegStrings; // Pointer to the string table.
159  const char *RegClassStrings; // Pointer to the class strings.
160  const uint16_t *SubRegIndices; // Pointer to the subreg lookup
161  // array.
162  const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
163  // bit ranges array.
164  unsigned NumSubRegIndices; // Number of subreg indices.
165  const uint16_t *RegEncodingTable; // Pointer to array of register
166  // encodings.
167 
168  unsigned L2DwarfRegsSize;
169  unsigned EHL2DwarfRegsSize;
170  unsigned Dwarf2LRegsSize;
171  unsigned EHDwarf2LRegsSize;
172  const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
173  const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
174  const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
175  const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
176  DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
177  DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
178 
179 public:
180  /// DiffListIterator - Base iterator class that can traverse the
181  /// differentially encoded register and regunit lists in DiffLists.
182  /// Don't use this class directly, use one of the specialized sub-classes
183  /// defined below.
185  uint16_t Val = 0;
186  const MCPhysReg *List = nullptr;
187 
188  protected:
189  /// Create an invalid iterator. Call init() to point to something useful.
190  DiffListIterator() = default;
191 
192  /// init - Point the iterator to InitVal, decoding subsequent values from
193  /// DiffList. The iterator will initially point to InitVal, sub-classes are
194  /// responsible for skipping the seed value if it is not part of the list.
195  void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
196  Val = InitVal;
197  List = DiffList;
198  }
199 
200  /// advance - Move to the next list position, return the applied
201  /// differential. This function does not detect the end of the list, that
202  /// is the caller's responsibility (by checking for a 0 return value).
204  assert(isValid() && "Cannot move off the end of the list.");
205  MCPhysReg D = *List++;
206  Val += D;
207  return D;
208  }
209 
210  public:
211  /// isValid - returns true if this iterator is not yet at the end.
212  bool isValid() const { return List; }
213 
214  /// Dereference the iterator to get the value at the current position.
215  MCRegister operator*() const { return Val; }
216 
217  /// Pre-increment to move to the next position.
218  void operator++() {
219  // The end of the list is encoded as a 0 differential.
220  if (!advance())
221  List = nullptr;
222  }
223  };
224 
225  // These iterators are allowed to sub-class DiffListIterator and access
226  // internal list pointers.
227  friend class MCSubRegIterator;
228  friend class MCSubRegIndexIterator;
229  friend class MCSuperRegIterator;
230  friend class MCRegUnitIterator;
231  friend class MCRegUnitMaskIterator;
232  friend class MCRegUnitRootIterator;
233 
234  /// Initialize MCRegisterInfo, called by TableGen
235  /// auto-generated routines. *DO NOT USE*.
236  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
237  unsigned PC,
238  const MCRegisterClass *C, unsigned NC,
239  const MCPhysReg (*RURoots)[2],
240  unsigned NRU,
241  const MCPhysReg *DL,
242  const LaneBitmask *RUMS,
243  const char *Strings,
244  const char *ClassStrings,
245  const uint16_t *SubIndices,
246  unsigned NumIndices,
247  const SubRegCoveredBits *SubIdxRanges,
248  const uint16_t *RET) {
249  Desc = D;
250  NumRegs = NR;
251  RAReg = RA;
252  PCReg = PC;
253  Classes = C;
254  DiffLists = DL;
255  RegUnitMaskSequences = RUMS;
256  RegStrings = Strings;
257  RegClassStrings = ClassStrings;
258  NumClasses = NC;
259  RegUnitRoots = RURoots;
260  NumRegUnits = NRU;
261  SubRegIndices = SubIndices;
262  NumSubRegIndices = NumIndices;
263  SubRegIdxRanges = SubIdxRanges;
264  RegEncodingTable = RET;
265 
266  // Initialize DWARF register mapping variables
267  EHL2DwarfRegs = nullptr;
268  EHL2DwarfRegsSize = 0;
269  L2DwarfRegs = nullptr;
270  L2DwarfRegsSize = 0;
271  EHDwarf2LRegs = nullptr;
272  EHDwarf2LRegsSize = 0;
273  Dwarf2LRegs = nullptr;
274  Dwarf2LRegsSize = 0;
275  }
276 
277  /// Used to initialize LLVM register to Dwarf
278  /// register number mapping. Called by TableGen auto-generated routines.
279  /// *DO NOT USE*.
280  void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
281  bool isEH) {
282  if (isEH) {
283  EHL2DwarfRegs = Map;
284  EHL2DwarfRegsSize = Size;
285  } else {
286  L2DwarfRegs = Map;
287  L2DwarfRegsSize = Size;
288  }
289  }
290 
291  /// Used to initialize Dwarf register to LLVM
292  /// register number mapping. Called by TableGen auto-generated routines.
293  /// *DO NOT USE*.
294  void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
295  bool isEH) {
296  if (isEH) {
297  EHDwarf2LRegs = Map;
298  EHDwarf2LRegsSize = Size;
299  } else {
300  Dwarf2LRegs = Map;
301  Dwarf2LRegsSize = Size;
302  }
303  }
304 
305  /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
306  /// number mapping. By default the SEH register number is just the same
307  /// as the LLVM register number.
308  /// FIXME: TableGen these numbers. Currently this requires target specific
309  /// initialization code.
310  void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
311  L2SEHRegs[LLVMReg] = SEHReg;
312  }
313 
314  void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
315  L2CVRegs[LLVMReg] = CVReg;
316  }
317 
318  /// This method should return the register where the return
319  /// address can be found.
321  return RAReg;
322  }
323 
324  /// Return the register which is the program counter.
326  return PCReg;
327  }
328 
329  const MCRegisterDesc &operator[](MCRegister RegNo) const {
330  assert(RegNo < NumRegs &&
331  "Attempting to access record for invalid register number!");
332  return Desc[RegNo];
333  }
334 
335  /// Provide a get method, equivalent to [], but more useful with a
336  /// pointer to this object.
337  const MCRegisterDesc &get(MCRegister RegNo) const {
338  return operator[](RegNo);
339  }
340 
341  /// Returns the physical register number of sub-register "Index"
342  /// for physical register RegNo. Return zero if the sub-register does not
343  /// exist.
344  MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
345 
346  /// Return a super-register of the specified register
347  /// Reg so its sub-register of index SubIdx is Reg.
348  MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
349  const MCRegisterClass *RC) const;
350 
351  /// For a given register pair, return the sub-register index
352  /// if the second register is a sub-register of the first. Return zero
353  /// otherwise.
354  unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
355 
356  /// Get the size of the bit range covered by a sub-register index.
357  /// If the index isn't continuous, return the sum of the sizes of its parts.
358  /// If the index is used to access subregisters of different sizes, return -1.
359  unsigned getSubRegIdxSize(unsigned Idx) const;
360 
361  /// Get the offset of the bit range covered by a sub-register index.
362  /// If an Offset doesn't make sense (the index isn't continuous, or is used to
363  /// access sub-registers at different offsets), return -1.
364  unsigned getSubRegIdxOffset(unsigned Idx) const;
365 
366  /// Return the human-readable symbolic target-specific name for the
367  /// specified physical register.
368  const char *getName(MCRegister RegNo) const {
369  return RegStrings + get(RegNo).Name;
370  }
371 
372  /// Return the number of registers this target has (useful for
373  /// sizing arrays holding per register information)
374  unsigned getNumRegs() const {
375  return NumRegs;
376  }
377 
378  /// Return the number of sub-register indices
379  /// understood by the target. Index 0 is reserved for the no-op sub-register,
380  /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
381  unsigned getNumSubRegIndices() const {
382  return NumSubRegIndices;
383  }
384 
385  /// Return the number of (native) register units in the
386  /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
387  /// can be accessed through MCRegUnitIterator defined below.
388  unsigned getNumRegUnits() const {
389  return NumRegUnits;
390  }
391 
392  /// Map a target register to an equivalent dwarf register
393  /// number. Returns -1 if there is no equivalent value. The second
394  /// parameter allows targets to use different numberings for EH info and
395  /// debugging info.
396  int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
397 
398  /// Map a dwarf register back to a target register.
399  int getLLVMRegNum(unsigned RegNum, bool isEH) const;
400 
401  /// Map a DWARF EH register back to a target register (same as
402  /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
403  /// rather than asserting that there must be one.
404  int getLLVMRegNumFromEH(unsigned RegNum) const;
405 
406  /// Map a target EH register number to an equivalent DWARF register
407  /// number.
408  int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
409 
410  /// Map a target register to an equivalent SEH register
411  /// number. Returns LLVM register number if there is no equivalent value.
412  int getSEHRegNum(MCRegister RegNum) const;
413 
414  /// Map a target register to an equivalent CodeView register
415  /// number.
416  int getCodeViewRegNum(MCRegister RegNum) const;
417 
418  regclass_iterator regclass_begin() const { return Classes; }
419  regclass_iterator regclass_end() const { return Classes+NumClasses; }
421  return make_range(regclass_begin(), regclass_end());
422  }
423 
424  unsigned getNumRegClasses() const {
425  return (unsigned)(regclass_end()-regclass_begin());
426  }
427 
428  /// Returns the register class associated with the enumeration
429  /// value. See class MCOperandInfo.
430  const MCRegisterClass& getRegClass(unsigned i) const {
431  assert(i < getNumRegClasses() && "Register Class ID out of range");
432  return Classes[i];
433  }
434 
435  const char *getRegClassName(const MCRegisterClass *Class) const {
436  return RegClassStrings + Class->NameIdx;
437  }
438 
439  /// Returns the encoding for RegNo
440  uint16_t getEncodingValue(MCRegister RegNo) const {
441  assert(RegNo < NumRegs &&
442  "Attempting to get encoding for invalid register number!");
443  return RegEncodingTable[RegNo];
444  }
445 
446  /// Returns true if RegB is a sub-register of RegA.
447  bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
448  return isSuperRegister(RegB, RegA);
449  }
450 
451  /// Returns true if RegB is a super-register of RegA.
452  bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
453 
454  /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
455  bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
456  return isSuperRegisterEq(RegB, RegA);
457  }
458 
459  /// Returns true if RegB is a super-register of RegA or if
460  /// RegB == RegA.
461  bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
462  return RegA == RegB || isSuperRegister(RegA, RegB);
463  }
464 
465  /// Returns true if RegB is a super-register or sub-register of RegA
466  /// or if RegB == RegA.
468  return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
469  }
470 };
471 
472 //===----------------------------------------------------------------------===//
473 // Register List Iterators
474 //===----------------------------------------------------------------------===//
475 
476 // MCRegisterInfo provides lists of super-registers, sub-registers, and
477 // aliasing registers. Use these iterator classes to traverse the lists.
478 
479 /// MCSubRegIterator enumerates all sub-registers of Reg.
480 /// If IncludeSelf is set, Reg itself is included in the list.
482 public:
484  bool IncludeSelf = false) {
485  init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
486  // Initially, the iterator points to Reg itself.
487  if (!IncludeSelf)
488  ++*this;
489  }
490 };
491 
492 /// Iterator that enumerates the sub-registers of a Reg and the associated
493 /// sub-register indices.
495  MCSubRegIterator SRIter;
496  const uint16_t *SRIndex;
497 
498 public:
499  /// Constructs an iterator that traverses subregisters and their
500  /// associated subregister indices.
502  : SRIter(Reg, MCRI) {
503  SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
504  }
505 
506  /// Returns current sub-register.
508  return *SRIter;
509  }
510 
511  /// Returns sub-register index of the current sub-register.
512  unsigned getSubRegIndex() const {
513  return *SRIndex;
514  }
515 
516  /// Returns true if this iterator is not yet at the end.
517  bool isValid() const { return SRIter.isValid(); }
518 
519  /// Moves to the next position.
520  void operator++() {
521  ++SRIter;
522  ++SRIndex;
523  }
524 };
525 
526 /// MCSuperRegIterator enumerates all super-registers of Reg.
527 /// If IncludeSelf is set, Reg itself is included in the list.
529 public:
530  MCSuperRegIterator() = default;
531 
533  bool IncludeSelf = false) {
534  init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
535  // Initially, the iterator points to Reg itself.
536  if (!IncludeSelf)
537  ++*this;
538  }
539 };
540 
541 // Definition for isSuperRegister. Put it down here since it needs the
542 // iterator defined above in addition to the MCRegisterInfo class itself.
544  for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
545  if (*I == RegB)
546  return true;
547  return false;
548 }
549 
550 //===----------------------------------------------------------------------===//
551 // Register Units
552 //===----------------------------------------------------------------------===//
553 
554 // Register units are used to compute register aliasing. Every register has at
555 // least one register unit, but it can have more. Two registers overlap if and
556 // only if they have a common register unit.
557 //
558 // A target with a complicated sub-register structure will typically have many
559 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
560 // the number of register units in the target.
561 
562 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
563 // in ascending numerical order.
565 public:
566  /// MCRegUnitIterator - Create an iterator that traverses the register units
567  /// in Reg.
568  MCRegUnitIterator() = default;
569 
571  assert(Reg && "Null register has no regunits");
572  // Decode the RegUnits MCRegisterDesc field.
573  unsigned RU = MCRI->get(Reg).RegUnits;
574  unsigned Scale = RU & 15;
575  unsigned Offset = RU >> 4;
576 
577  // Initialize the iterator to Reg * Scale, and the List pointer to
578  // DiffLists + Offset.
579  init(Reg * Scale, MCRI->DiffLists + Offset);
580 
581  // That may not be a valid unit, we need to advance by one to get the real
582  // unit number. The first differential can be 0 which would normally
583  // terminate the list, but since we know every register has at least one
584  // unit, we can allow a 0 differential here.
585  advance();
586  }
587 };
588 
589 /// MCRegUnitMaskIterator enumerates a list of register units and their
590 /// associated lane masks for Reg. The register units are in ascending
591 /// numerical order.
593  MCRegUnitIterator RUIter;
594  const LaneBitmask *MaskListIter;
595 
596 public:
597  MCRegUnitMaskIterator() = default;
598 
599  /// Constructs an iterator that traverses the register units and their
600  /// associated LaneMasks in Reg.
602  : RUIter(Reg, MCRI) {
603  uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
604  MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
605  }
606 
607  /// Returns a (RegUnit, LaneMask) pair.
608  std::pair<unsigned,LaneBitmask> operator*() const {
609  return std::make_pair(*RUIter, *MaskListIter);
610  }
611 
612  /// Returns true if this iterator is not yet at the end.
613  bool isValid() const { return RUIter.isValid(); }
614 
615  /// Moves to the next position.
616  void operator++() {
617  ++MaskListIter;
618  ++RUIter;
619  }
620 };
621 
622 // Each register unit has one or two root registers. The complete set of
623 // registers containing a register unit is the union of the roots and their
624 // super-registers. All registers aliasing Unit can be visited like this:
625 //
626 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
627 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
628 // visit(*SI);
629 // }
630 
631 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
633  uint16_t Reg0 = 0;
634  uint16_t Reg1 = 0;
635 
636 public:
637  MCRegUnitRootIterator() = default;
638 
639  MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
640  assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
641  Reg0 = MCRI->RegUnitRoots[RegUnit][0];
642  Reg1 = MCRI->RegUnitRoots[RegUnit][1];
643  }
644 
645  /// Dereference to get the current root register.
646  unsigned operator*() const {
647  return Reg0;
648  }
649 
650  /// Check if the iterator is at the end of the list.
651  bool isValid() const {
652  return Reg0;
653  }
654 
655  /// Preincrement to move to the next root register.
656  void operator++() {
657  assert(isValid() && "Cannot move off the end of the list.");
658  Reg0 = Reg1;
659  Reg1 = 0;
660  }
661 };
662 
663 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
664 /// set, Reg itself is included in the list. This iterator does not guarantee
665 /// any ordering or that entries are unique.
667 private:
668  MCRegister Reg;
669  const MCRegisterInfo *MCRI;
670  bool IncludeSelf;
671 
675 
676 public:
678  bool IncludeSelf)
679  : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
680  // Initialize the iterators.
681  for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
682  for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
683  for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
684  if (!(!IncludeSelf && Reg == *SI))
685  return;
686  }
687  }
688  }
689  }
690 
691  bool isValid() const { return RI.isValid(); }
692 
694  assert(SI.isValid() && "Cannot dereference an invalid iterator.");
695  return *SI;
696  }
697 
698  void advance() {
699  // Assuming SI is valid.
700  ++SI;
701  if (SI.isValid()) return;
702 
703  ++RRI;
704  if (RRI.isValid()) {
705  SI = MCSuperRegIterator(*RRI, MCRI, true);
706  return;
707  }
708 
709  ++RI;
710  if (RI.isValid()) {
711  RRI = MCRegUnitRootIterator(*RI, MCRI);
712  SI = MCSuperRegIterator(*RRI, MCRI, true);
713  }
714  }
715 
716  void operator++() {
717  assert(isValid() && "Cannot move off the end of the list.");
718  do advance();
719  while (!IncludeSelf && isValid() && *SI == Reg);
720  }
721 };
722 
723 } // end namespace llvm
724 
725 #endif // LLVM_MC_MCREGISTERINFO_H
uint64_t CallInst * C
A common definition of LaneBitmask for use in TableGen and CodeGen.
const uint8_t *const RegSet
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
void operator++()
Pre-increment to move to the next position.
iterator begin() const
begin/end - Return all of the registers in this class.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const uint32_t NameIdx
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
const MCRegisterDesc & operator[](MCRegister RegNo) const
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
MCRegister operator*() const
unsigned Reg
MCRegister operator*() const
Dereference the iterator to get the value at the current position.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned getID() const
getID() - Return the register class ID number.
SI optimize exec mask operations pre RA
bool isValid() const
Returns true if this iterator is not yet at the end.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MCSuperRegIterator enumerates all super-registers of Reg.
regclass_iterator regclass_begin() const
const iterator RegsBegin
MCRegister advance()
advance - Move to the next list position, return the applied differential.
void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
Initialize MCRegisterInfo, called by TableGen auto-generated routines.
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
DiffListIterator - Base iterator class that can traverse the differentially encoded register and regu...
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
void operator++()
Moves to the next position.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
unsigned operator*() const
Dereference to get the current root register.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...
MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize LLVM register to Dwarf register number mapping.
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize Dwarf register to LLVM register number mapping.
const MCPhysReg * const_iterator
MCRegAliasIterator enumerates all registers aliasing Reg.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
bool contains(MCRegister Reg1, MCRegister Reg2) const
contains - Return true if both registers are in this class.
iterator end() const
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
iterator_range< regclass_iterator > regclasses() const
std::pair< unsigned, LaneBitmask > operator*() const
Returns a (RegUnit, LaneMask) pair.
bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
MCSubRegIterator enumerates all sub-registers of Reg.
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
unsigned getNumRegClasses() const
MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses subregisters and their associated subregister indices...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MCRegisterDesc - This record contains information about a particular register.
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
const char * getRegClassName(const MCRegisterClass *Class) const
bool isValid() const
Returns true if this iterator is not yet at the end.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define NC
Definition: regutils.h:42
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI)
MCRegister getProgramCounter() const
Return the register which is the program counter.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
A range adaptor for a pair of iterators.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
bool operator<(DwarfLLVMRegPair RHS) const
uint16_t RegUnitLaneMasks
Index into list with lane mask sequences.
regclass_iterator regclass_end() const
const uint16_t RegSetSize
MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
const NodeList & List
Definition: RDFGraph.cpp:201
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
uint32_t Size
Definition: Profile.cpp:46
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
void operator++()
Moves to the next position.
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void operator++()
Preincrement to move to the next root register.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:92
MCRegister getSubReg() const
Returns current sub-register.
bool isValid() const
Check if the iterator is at the end of the list.
const MCPhysReg * iterator
const uint16_t RegsSize
MCRegister getRARegister() const
This method should return the register where the return address can be found.
MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses the register units and their associated LaneMasks in Reg...
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
void init(MCPhysReg InitVal, const MCPhysReg *DiffList)
init - Point the iterator to InitVal, decoding subsequent values from DiffList.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.