LLVM  8.0.0svn
MCInstrAnalysis.h
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1 //===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MCInstrAnalysis class which the MCTargetDescs can
11 // derive from to give additional information to MC.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCINSTRANALYSIS_H
16 #define LLVM_MC_MCINSTRANALYSIS_H
17 
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include <cstdint>
22 
23 namespace llvm {
24 
25 class MCRegisterInfo;
26 
28 protected:
29  friend class Target;
30 
31  const MCInstrInfo *Info;
32 
33 public:
34  MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
35  virtual ~MCInstrAnalysis() = default;
36 
37  virtual bool isBranch(const MCInst &Inst) const {
38  return Info->get(Inst.getOpcode()).isBranch();
39  }
40 
41  virtual bool isConditionalBranch(const MCInst &Inst) const {
42  return Info->get(Inst.getOpcode()).isConditionalBranch();
43  }
44 
45  virtual bool isUnconditionalBranch(const MCInst &Inst) const {
46  return Info->get(Inst.getOpcode()).isUnconditionalBranch();
47  }
48 
49  virtual bool isIndirectBranch(const MCInst &Inst) const {
50  return Info->get(Inst.getOpcode()).isIndirectBranch();
51  }
52 
53  virtual bool isCall(const MCInst &Inst) const {
54  return Info->get(Inst.getOpcode()).isCall();
55  }
56 
57  virtual bool isReturn(const MCInst &Inst) const {
58  return Info->get(Inst.getOpcode()).isReturn();
59  }
60 
61  virtual bool isTerminator(const MCInst &Inst) const {
62  return Info->get(Inst.getOpcode()).isTerminator();
63  }
64 
65  /// Returns true if at least one of the register writes performed by
66  /// \param Inst implicitly clears the upper portion of all super-registers.
67  ///
68  /// Example: on X86-64, a write to EAX implicitly clears the upper half of
69  /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
70  /// instruction implicitly clears the upper portion of the correspondent
71  /// YMM register.
72  ///
73  /// This method also updates an APInt which is used as mask of register
74  /// writes. There is one bit for every explicit/implicit write performed by
75  /// the instruction. If a write implicitly clears its super-registers, then
76  /// the corresponding bit is set (vic. the corresponding bit is cleared).
77  ///
78  /// The first bits in the APint are related to explicit writes. The remaining
79  /// bits are related to implicit writes. The sequence of writes follows the
80  /// machine operand sequence. For implicit writes, the sequence is defined by
81  /// the MCInstrDesc.
82  ///
83  /// The assumption is that the bit-width of the APInt is correctly set by
84  /// the caller. The default implementation conservatively assumes that none of
85  /// the writes clears the upper portion of a super-register.
86  virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
87  const MCInst &Inst,
88  APInt &Writes) const;
89 
90  /// Returns true if \param Inst is a dependency breaking instruction for the
91  /// given subtarget.
92  ///
93  /// The value computed by a dependency breaking instruction is not dependent
94  /// on the inputs. An example of dependency breaking instruction on X86 is
95  /// `XOR %eax, %eax`.
96  /// TODO: In future, we could implement an alternative approach where this
97  /// method returns `true` if the input instruction is not dependent on
98  /// some/all of its input operands. An APInt mask could then be used to
99  /// identify independent operands.
100  virtual bool isDependencyBreaking(const MCSubtargetInfo &STI,
101  const MCInst &Inst) const;
102 
103  /// Given a branch instruction try to get the address the branch
104  /// targets. Return true on success, and the address in Target.
105  virtual bool
106  evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
107  uint64_t &Target) const;
108 };
109 
110 } // end namespace llvm
111 
112 #endif // LLVM_MC_MCINSTRANALYSIS_H
virtual bool isReturn(const MCInst &Inst) const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
virtual bool isBranch(const MCInst &Inst) const
virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Writes) const
Returns true if at least one of the register writes performed by.
unsigned const MachineRegisterInfo * MRI
const MCInstrInfo * Info
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
virtual bool isIndirectBranch(const MCInst &Inst) const
virtual ~MCInstrAnalysis()=default
virtual bool isTerminator(const MCInst &Inst) const
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:70
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
Generic base class for all target subtargets.
virtual bool isDependencyBreaking(const MCSubtargetInfo &STI, const MCInst &Inst) const
Returns true if.
MCInstrAnalysis(const MCInstrInfo *Info)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual bool isCall(const MCInst &Inst) const
unsigned getOpcode() const
Definition: MCInst.h:174