LLVM  8.0.0svn
Namespaces | Macros | Functions | Variables
HexagonCopyToCombine.cpp File Reference
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/PassSupport.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
Include dependency graph for HexagonCopyToCombine.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define DEBUG_TYPE   "hexagon-copy-combine"
 

Functions

FunctionPassllvm::createHexagonCopyToCombine ()
 
void llvm::initializeHexagonCopyToCombinePass (PassRegistry &)
 
 INITIALIZE_PASS (HexagonCopyToCombine, "hexagon-copy-combine", "Hexagon Copy-To-Combine Pass", false, false) static bool isCombinableInstType(MachineInstr &MI
 
template<unsigned N>
static bool isGreaterThanNBitTFRI (const MachineInstr &I)
 
static bool areCombinableOperations (const TargetRegisterInfo *TRI, MachineInstr &HighRegInst, MachineInstr &LowRegInst, bool AllowC64)
 areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring register constraints). More...
 
static bool isEvenReg (unsigned Reg)
 
static void removeKillInfo (MachineInstr &MI, unsigned RegNotKilled)
 
static bool isUnsafeToMoveAcross (MachineInstr &MI, unsigned UseReg, unsigned DestReg, const TargetRegisterInfo *TRI)
 Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction MI. More...
 
static unsigned UseReg (const MachineOperand &MO)
 

Variables

static cl::opt< boolIsCombinesDisabled ("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable merging into combines"))
 
static cl::opt< boolIsConst64Disabled ("disable-const64", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable generation of const64"))
 
static cl::opt< unsignedMaxNumOfInstsBetweenNewValueStoreAndTFR ("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we " "consider the store still to be newifiable"))
 
const HexagonInstrInfoTII
 
const HexagonInstrInfo bool ShouldCombineAggressively
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "hexagon-copy-combine"

Definition at line 33 of file HexagonCopyToCombine.cpp.

Function Documentation

◆ areCombinableOperations()

static bool areCombinableOperations ( const TargetRegisterInfo TRI,
MachineInstr HighRegInst,
MachineInstr LowRegInst,
bool  AllowC64 
)
static

areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring register constraints).

Definition at line 184 of file HexagonCopyToCombine.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and llvm_unreachable.

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( HexagonCopyToCombine  ,
"hexagon-copy-combine"  ,
"Hexagon Copy-To-Combine Pass ,
false  ,
false   
) &

◆ isEvenReg()

static bool isEvenReg ( unsigned  Reg)
static

◆ isGreaterThanNBitTFRI()

template<unsigned N>
static bool isGreaterThanNBitTFRI ( const MachineInstr I)
static

◆ isUnsafeToMoveAcross()

static bool isUnsafeToMoveAcross ( MachineInstr MI,
unsigned  UseReg,
unsigned  DestReg,
const TargetRegisterInfo TRI 
)
static

Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction MI.

Definition at line 249 of file HexagonCopyToCombine.cpp.

References llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isMetaInstruction(), llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().

◆ removeKillInfo()

static void removeKillInfo ( MachineInstr MI,
unsigned  RegNotKilled 
)
static

◆ UseReg()

static unsigned UseReg ( const MachineOperand MO)
static

Variable Documentation

◆ IsCombinesDisabled

cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable merging into combines"))
static

◆ IsConst64Disabled

cl::opt<bool> IsConst64Disabled("disable-const64", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable generation of const64"))
static

◆ MaxNumOfInstsBetweenNewValueStoreAndTFR

cl::opt<unsigned> MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we " "consider the store still to be newifiable"))
static

◆ ShouldCombineAggressively

const HexagonInstrInfo bool ShouldCombineAggressively

Definition at line 129 of file HexagonCopyToCombine.cpp.

◆ TII

Definition at line 128 of file HexagonCopyToCombine.cpp.

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