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RISCVFrameLowering.cpp
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1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVFrameLowering.h"
15 #include "RISCVSubtarget.h"
21 #include "llvm/MC/MCDwarf.h"
22 
23 using namespace llvm;
24 
26  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
27 
28  const MachineFrameInfo &MFI = MF.getFrameInfo();
29  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
30  RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
31  MFI.isFrameAddressTaken();
32 }
33 
34 // Determines the size of the frame and maximum call frame size.
35 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
36  MachineFrameInfo &MFI = MF.getFrameInfo();
38 
39  // Get the number of bytes to allocate from the FrameInfo.
40  uint64_t FrameSize = MFI.getStackSize();
41 
42  // Get the alignment.
43  unsigned StackAlign = getStackAlignment();
44  if (RI->needsStackRealignment(MF)) {
45  unsigned MaxStackAlign = std::max(StackAlign, MFI.getMaxAlignment());
46  FrameSize += (MaxStackAlign - StackAlign);
47  StackAlign = MaxStackAlign;
48  }
49 
50  // Set Max Call Frame Size
51  uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign);
52  MFI.setMaxCallFrameSize(MaxCallSize);
53 
54  // Make sure the frame is aligned.
55  FrameSize = alignTo(FrameSize, StackAlign);
56 
57  // Update frame info.
58  MFI.setStackSize(FrameSize);
59 }
60 
61 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
63  const DebugLoc &DL, Register DestReg,
64  Register SrcReg, int64_t Val,
65  MachineInstr::MIFlag Flag) const {
68 
69  if (DestReg == SrcReg && Val == 0)
70  return;
71 
72  if (isInt<12>(Val)) {
73  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
74  .addReg(SrcReg)
75  .addImm(Val)
76  .setMIFlag(Flag);
77  } else {
78  unsigned Opc = RISCV::ADD;
79  bool isSub = Val < 0;
80  if (isSub) {
81  Val = -Val;
82  Opc = RISCV::SUB;
83  }
84 
85  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
86  TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
87  BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
88  .addReg(SrcReg)
89  .addReg(ScratchReg, RegState::Kill)
90  .setMIFlag(Flag);
91  }
92 }
93 
94 // Returns the register used to hold the frame pointer.
95 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
96 
97 // Returns the register used to hold the stack pointer.
98 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
99 
101  MachineBasicBlock &MBB) const {
102  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
103 
104  MachineFrameInfo &MFI = MF.getFrameInfo();
105  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
106  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
107  const RISCVInstrInfo *TII = STI.getInstrInfo();
108  MachineBasicBlock::iterator MBBI = MBB.begin();
109 
110  if (RI->needsStackRealignment(MF) && MFI.hasVarSizedObjects()) {
112  "RISC-V backend can't currently handle functions that need stack "
113  "realignment and have variable sized objects");
114  }
115 
116  Register FPReg = getFPReg(STI);
117  Register SPReg = getSPReg(STI);
118 
119  // Debug location must be unknown since the first debug location is used
120  // to determine the end of the prologue.
121  DebugLoc DL;
122 
123  // Determine the correct frame layout
124  determineFrameLayout(MF);
125 
126  // FIXME (note copied from Lanai): This appears to be overallocating. Needs
127  // investigation. Get the number of bytes to allocate from the FrameInfo.
128  uint64_t StackSize = MFI.getStackSize();
129 
130  // Early exit if there is no need to allocate on the stack
131  if (StackSize == 0 && !MFI.adjustsStack())
132  return;
133 
134  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
135  // Split the SP adjustment to reduce the offsets of callee saved spill.
136  if (FirstSPAdjustAmount)
137  StackSize = FirstSPAdjustAmount;
138 
139  // Allocate space on the stack if necessary.
140  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
141 
142  // Emit ".cfi_def_cfa_offset StackSize"
143  unsigned CFIIndex = MF.addFrameInst(
144  MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
145  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
146  .addCFIIndex(CFIIndex);
147 
148  // The frame pointer is callee-saved, and code has been generated for us to
149  // save it to the stack. We need to skip over the storing of callee-saved
150  // registers as the frame pointer must be modified after it has been saved
151  // to the stack, not before.
152  // FIXME: assumes exactly one instruction is used to save each callee-saved
153  // register.
154  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
155  std::advance(MBBI, CSI.size());
156 
157  // Iterate over list of callee-saved registers and emit .cfi_offset
158  // directives.
159  for (const auto &Entry : CSI) {
160  int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());
161  Register Reg = Entry.getReg();
162  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
163  nullptr, RI->getDwarfRegNum(Reg, true), Offset));
164  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
165  .addCFIIndex(CFIIndex);
166  }
167 
168  // Generate new FP.
169  if (hasFP(MF)) {
170  adjustReg(MBB, MBBI, DL, FPReg, SPReg,
171  StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
172 
173  // Emit ".cfi_def_cfa $fp, 0"
174  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
175  nullptr, RI->getDwarfRegNum(FPReg, true), 0));
176  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
177  .addCFIIndex(CFIIndex);
178  }
179 
180  // Emit the second SP adjustment after saving callee saved registers.
181  if (FirstSPAdjustAmount) {
182  uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
183  assert(SecondSPAdjustAmount > 0 &&
184  "SecondSPAdjustAmount should be greater than zero");
185  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount,
187  // Emit ".cfi_def_cfa_offset StackSize"
188  unsigned CFIIndex = MF.addFrameInst(
189  MCCFIInstruction::createDefCfaOffset(nullptr, -MFI.getStackSize()));
190  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
191  .addCFIIndex(CFIIndex);
192  }
193 
194  if (hasFP(MF)) {
195  // Realign Stack
196  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
197  if (RI->needsStackRealignment(MF)) {
198  unsigned MaxAlignment = MFI.getMaxAlignment();
199 
200  const RISCVInstrInfo *TII = STI.getInstrInfo();
201  if (isInt<12>(-(int)MaxAlignment)) {
202  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
203  .addReg(SPReg)
204  .addImm(-(int)MaxAlignment);
205  } else {
206  unsigned ShiftAmount = countTrailingZeros(MaxAlignment);
207  Register VR =
208  MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
209  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
210  .addReg(SPReg)
211  .addImm(ShiftAmount);
212  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
213  .addReg(VR)
214  .addImm(ShiftAmount);
215  }
216  }
217  }
218 }
219 
221  MachineBasicBlock &MBB) const {
223  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
224  MachineFrameInfo &MFI = MF.getFrameInfo();
225  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
226  DebugLoc DL = MBBI->getDebugLoc();
227  const RISCVInstrInfo *TII = STI.getInstrInfo();
228  Register FPReg = getFPReg(STI);
229  Register SPReg = getSPReg(STI);
230 
231  // Skip to before the restores of callee-saved registers
232  // FIXME: assumes exactly one instruction is used to restore each
233  // callee-saved register.
234  auto LastFrameDestroy = std::prev(MBBI, MFI.getCalleeSavedInfo().size());
235 
236  uint64_t StackSize = MFI.getStackSize();
237  uint64_t FPOffset = StackSize - RVFI->getVarArgsSaveSize();
238 
239  // Restore the stack pointer using the value of the frame pointer. Only
240  // necessary if the stack pointer was modified, meaning the stack size is
241  // unknown.
242  if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) {
243  assert(hasFP(MF) && "frame pointer should not have been eliminated");
244  adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
246  }
247 
248  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
249  if (FirstSPAdjustAmount) {
250  uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
251  assert(SecondSPAdjustAmount > 0 &&
252  "SecondSPAdjustAmount should be greater than zero");
253 
254  adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
256 
257  // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount"
258  unsigned CFIIndex =
259  MF.addFrameInst(
261  -FirstSPAdjustAmount));
262  BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
263  .addCFIIndex(CFIIndex);
264  }
265 
266  if (hasFP(MF)) {
267  // To find the instruction restoring FP from stack.
268  for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
269  if (I->mayLoad() && I->getOperand(0).isReg()) {
270  Register DestReg = I->getOperand(0).getReg();
271  if (DestReg == FPReg) {
272  // If there is frame pointer, after restoring $fp registers, we
273  // need adjust CFA to ($sp - FPOffset).
274  // Emit ".cfi_def_cfa $sp, -FPOffset"
275  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
276  nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));
277  BuildMI(MBB, std::next(I), DL,
278  TII->get(TargetOpcode::CFI_INSTRUCTION))
279  .addCFIIndex(CFIIndex);
280  break;
281  }
282  }
283  }
284  }
285 
286  // Add CFI directives for callee-saved registers.
287  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
288  // Iterate over list of callee-saved registers and emit .cfi_restore
289  // directives.
290  for (const auto &Entry : CSI) {
291  Register Reg = Entry.getReg();
292  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
293  nullptr, RI->getDwarfRegNum(Reg, true)));
294  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
295  .addCFIIndex(CFIIndex);
296  }
297 
298  if (FirstSPAdjustAmount)
299  StackSize = FirstSPAdjustAmount;
300 
301  // Deallocate stack
302  adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
303 
304  // After restoring $sp, we need to adjust CFA to $(sp + 0)
305  // Emit ".cfi_def_cfa_offset 0"
306  unsigned CFIIndex =
308  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
309  .addCFIIndex(CFIIndex);
310 }
311 
313  int FI,
314  unsigned &FrameReg) const {
315  const MachineFrameInfo &MFI = MF.getFrameInfo();
317  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
318 
319  // Callee-saved registers should be referenced relative to the stack
320  // pointer (positive offset), otherwise use the frame pointer (negative
321  // offset).
322  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
323  int MinCSFI = 0;
324  int MaxCSFI = -1;
325 
326  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea() +
327  MFI.getOffsetAdjustment();
328 
329  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
330 
331  if (CSI.size()) {
332  MinCSFI = CSI[0].getFrameIdx();
333  MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
334  }
335 
336  if (FI >= MinCSFI && FI <= MaxCSFI) {
337  FrameReg = RISCV::X2;
338 
339  if (FirstSPAdjustAmount)
340  Offset += FirstSPAdjustAmount;
341  else
342  Offset += MF.getFrameInfo().getStackSize();
343  } else if (RI->needsStackRealignment(MF)) {
344  assert(!MFI.hasVarSizedObjects() &&
345  "Unexpected combination of stack realignment and varsized objects");
346  // If the stack was realigned, the frame pointer is set in order to allow
347  // SP to be restored, but we still access stack objects using SP.
348  FrameReg = RISCV::X2;
349  Offset += MF.getFrameInfo().getStackSize();
350  } else {
351  FrameReg = RI->getFrameRegister(MF);
352  if (hasFP(MF))
353  Offset += RVFI->getVarArgsSaveSize();
354  else
355  Offset += MF.getFrameInfo().getStackSize();
356  }
357  return Offset;
358 }
359 
361  BitVector &SavedRegs,
362  RegScavenger *RS) const {
364  // Unconditionally spill RA and FP only if the function uses a frame
365  // pointer.
366  if (hasFP(MF)) {
367  SavedRegs.set(RISCV::X1);
368  SavedRegs.set(RISCV::X8);
369  }
370 
371  // If interrupt is enabled and there are calls in the handler,
372  // unconditionally save all Caller-saved registers and
373  // all FP registers, regardless whether they are used.
374  MachineFrameInfo &MFI = MF.getFrameInfo();
375 
376  if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
377 
378  static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
379  RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
380  RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
381  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
382  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
383  };
384 
385  for (unsigned i = 0; CSRegs[i]; ++i)
386  SavedRegs.set(CSRegs[i]);
387 
388  if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
389  MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
390 
391  // If interrupt is enabled, this list contains all FP registers.
392  const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
393 
394  for (unsigned i = 0; Regs[i]; ++i)
395  if (RISCV::FPR32RegClass.contains(Regs[i]) ||
396  RISCV::FPR64RegClass.contains(Regs[i]))
397  SavedRegs.set(Regs[i]);
398  }
399  }
400 }
401 
403  MachineFunction &MF, RegScavenger *RS) const {
404  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
405  MachineFrameInfo &MFI = MF.getFrameInfo();
406  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
407  // estimateStackSize has been observed to under-estimate the final stack
408  // size, so give ourselves wiggle-room by checking for stack size
409  // representable an 11-bit signed field rather than 12-bits.
410  // FIXME: It may be possible to craft a function with a small stack that
411  // still needs an emergency spill slot for branch relaxation. This case
412  // would currently be missed.
413  if (!isInt<11>(MFI.estimateStackSize(MF))) {
414  int RegScavFI = MFI.CreateStackObject(
415  RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);
416  RS->addScavengingFrameIndex(RegScavFI);
417  }
418 }
419 
420 // Not preserve stack space within prologue for outgoing variables when the
421 // function contains variable size objects and let eliminateCallFramePseudoInstr
422 // preserve stack space for it.
424  return !MF.getFrameInfo().hasVarSizedObjects();
425 }
426 
427 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
431  Register SPReg = RISCV::X2;
432  DebugLoc DL = MI->getDebugLoc();
433 
434  if (!hasReservedCallFrame(MF)) {
435  // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
436  // ADJCALLSTACKUP must be converted to instructions manipulating the stack
437  // pointer. This is necessary when there is a variable length stack
438  // allocation (e.g. alloca), which means it's not possible to allocate
439  // space for outgoing arguments from within the function prologue.
440  int64_t Amount = MI->getOperand(0).getImm();
441 
442  if (Amount != 0) {
443  // Ensure the stack remains aligned after adjustment.
444  Amount = alignSPAdjust(Amount);
445 
446  if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
447  Amount = -Amount;
448 
449  adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
450  }
451  }
452 
453  return MBB.erase(MI);
454 }
455 
456 // We would like to split the SP adjustment to reduce prologue/epilogue
457 // as following instructions. In this way, the offset of the callee saved
458 // register could fit in a single store.
459 // add sp,sp,-2032
460 // sw ra,2028(sp)
461 // sw s0,2024(sp)
462 // sw s1,2020(sp)
463 // sw s3,2012(sp)
464 // sw s4,2008(sp)
465 // add sp,sp,-64
466 uint64_t
468  const MachineFrameInfo &MFI = MF.getFrameInfo();
469  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
470  uint64_t StackSize = MFI.getStackSize();
471  uint64_t StackAlign = getStackAlignment();
472 
473  // FIXME: Disable SplitSPAdjust if save-restore libcall enabled when the patch
474  // landing. The callee saved registers will be pushed by the
475  // save-restore libcalls, so we don't have to split the SP adjustment
476  // in this case.
477  //
478  // Return the FirstSPAdjustAmount if the StackSize can not fit in signed
479  // 12-bit and there exists a callee saved register need to be pushed.
480  if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
481  // FirstSPAdjustAmount is choosed as (2048 - StackAlign)
482  // because 2048 will cause sp = sp + 2048 in epilogue split into
483  // multi-instructions. The offset smaller than 2048 can fit in signle
484  // load/store instruction and we have to stick with the stack alignment.
485  // 2048 is 16-byte alignment. The stack alignment for RV32 and RV64 is 16,
486  // for RV32E is 4. So (2048 - StackAlign) will satisfy the stack alignment.
487  return 2048 - StackAlign;
488  }
489  return 0;
490 }
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
static Register getSPReg(const RISCVSubtarget &STI)
BitVector & set()
Definition: BitVector.h:397
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:507
unsigned Reg
const RISCVRegisterInfo * getRegisterInfo() const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
A debug info location.
Definition: DebugLoc.h:33
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:494
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:156
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment. ...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:480
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void setStackSize(uint64_t Size)
Set the size of the stack.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register)
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
Definition: MCDwarf.h:540
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
bool hasStdExtD() const
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
static Register getFPReg(const RISCVSubtarget &STI)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:163
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetOptions Options
#define I(x, y, z)
Definition: MD5.cpp:58
void setMaxCallFrameSize(unsigned S)
int getOffsetAdjustment() const
Return the correction for frame offsets.
const RISCVSubtarget & STI
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const RISCVInstrInfo * getInstrInfo() const override
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool hasCalls() const
Return true if the current function has any function calls.