LLVM  10.0.0svn
RISCVFrameLowering.cpp
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1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVFrameLowering.h"
15 #include "RISCVSubtarget.h"
21 #include "llvm/MC/MCDwarf.h"
22 
23 using namespace llvm;
24 
26  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
27 
28  const MachineFrameInfo &MFI = MF.getFrameInfo();
29  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
30  RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
31  MFI.isFrameAddressTaken();
32 }
33 
34 // Determines the size of the frame and maximum call frame size.
35 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
36  MachineFrameInfo &MFI = MF.getFrameInfo();
38 
39  // Get the number of bytes to allocate from the FrameInfo.
40  uint64_t FrameSize = MFI.getStackSize();
41 
42  // Get the alignment.
43  unsigned StackAlign = getStackAlignment();
44  if (RI->needsStackRealignment(MF)) {
45  unsigned MaxStackAlign = std::max(StackAlign, MFI.getMaxAlignment());
46  FrameSize += (MaxStackAlign - StackAlign);
47  StackAlign = MaxStackAlign;
48  }
49 
50  // Set Max Call Frame Size
51  uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign);
52  MFI.setMaxCallFrameSize(MaxCallSize);
53 
54  // Make sure the frame is aligned.
55  FrameSize = alignTo(FrameSize, StackAlign);
56 
57  // Update frame info.
58  MFI.setStackSize(FrameSize);
59 }
60 
61 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
63  const DebugLoc &DL, Register DestReg,
64  Register SrcReg, int64_t Val,
65  MachineInstr::MIFlag Flag) const {
68 
69  if (DestReg == SrcReg && Val == 0)
70  return;
71 
72  if (isInt<12>(Val)) {
73  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
74  .addReg(SrcReg)
75  .addImm(Val)
76  .setMIFlag(Flag);
77  } else if (isInt<32>(Val)) {
78  unsigned Opc = RISCV::ADD;
79  bool isSub = Val < 0;
80  if (isSub) {
81  Val = -Val;
82  Opc = RISCV::SUB;
83  }
84 
85  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
86  TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
87  BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
88  .addReg(SrcReg)
89  .addReg(ScratchReg, RegState::Kill)
90  .setMIFlag(Flag);
91  } else {
92  report_fatal_error("adjustReg cannot yet handle adjustments >32 bits");
93  }
94 }
95 
96 // Returns the register used to hold the frame pointer.
97 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
98 
99 // Returns the register used to hold the stack pointer.
100 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
101 
103  MachineBasicBlock &MBB) const {
104  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
105 
106  MachineFrameInfo &MFI = MF.getFrameInfo();
107  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
108  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
109  const RISCVInstrInfo *TII = STI.getInstrInfo();
110  MachineBasicBlock::iterator MBBI = MBB.begin();
111 
112  if (RI->needsStackRealignment(MF) && MFI.hasVarSizedObjects()) {
114  "RISC-V backend can't currently handle functions that need stack "
115  "realignment and have variable sized objects");
116  }
117 
118  Register FPReg = getFPReg(STI);
119  Register SPReg = getSPReg(STI);
120 
121  // Debug location must be unknown since the first debug location is used
122  // to determine the end of the prologue.
123  DebugLoc DL;
124 
125  // Determine the correct frame layout
126  determineFrameLayout(MF);
127 
128  // FIXME (note copied from Lanai): This appears to be overallocating. Needs
129  // investigation. Get the number of bytes to allocate from the FrameInfo.
130  uint64_t StackSize = MFI.getStackSize();
131 
132  // Early exit if there is no need to allocate on the stack
133  if (StackSize == 0 && !MFI.adjustsStack())
134  return;
135 
136  // Allocate space on the stack if necessary.
137  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
138 
139  // Emit ".cfi_def_cfa_offset StackSize"
140  unsigned CFIIndex = MF.addFrameInst(
141  MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
142  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
143  .addCFIIndex(CFIIndex);
144 
145  // The frame pointer is callee-saved, and code has been generated for us to
146  // save it to the stack. We need to skip over the storing of callee-saved
147  // registers as the frame pointer must be modified after it has been saved
148  // to the stack, not before.
149  // FIXME: assumes exactly one instruction is used to save each callee-saved
150  // register.
151  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
152  std::advance(MBBI, CSI.size());
153 
154  // Iterate over list of callee-saved registers and emit .cfi_offset
155  // directives.
156  for (const auto &Entry : CSI) {
157  int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());
158  Register Reg = Entry.getReg();
159  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
160  nullptr, RI->getDwarfRegNum(Reg, true), Offset));
161  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
162  .addCFIIndex(CFIIndex);
163  }
164 
165  // Generate new FP.
166  if (hasFP(MF)) {
167  adjustReg(MBB, MBBI, DL, FPReg, SPReg,
168  StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
169 
170  // Emit ".cfi_def_cfa $fp, 0"
171  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
172  nullptr, RI->getDwarfRegNum(FPReg, true), 0));
173  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
174  .addCFIIndex(CFIIndex);
175 
176  // Realign Stack
177  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
178  if (RI->needsStackRealignment(MF)) {
179  unsigned MaxAlignment = MFI.getMaxAlignment();
180 
181  const RISCVInstrInfo *TII = STI.getInstrInfo();
182  if (isInt<12>(-(int)MaxAlignment)) {
183  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
184  .addReg(SPReg)
185  .addImm(-(int)MaxAlignment);
186  } else {
187  unsigned ShiftAmount = countTrailingZeros(MaxAlignment);
188  Register VR =
189  MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
190  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
191  .addReg(SPReg)
192  .addImm(ShiftAmount);
193  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
194  .addReg(VR)
195  .addImm(ShiftAmount);
196  }
197  }
198  }
199 }
200 
202  MachineBasicBlock &MBB) const {
204  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
205  MachineFrameInfo &MFI = MF.getFrameInfo();
206  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
207  DebugLoc DL = MBBI->getDebugLoc();
208  const RISCVInstrInfo *TII = STI.getInstrInfo();
209  Register FPReg = getFPReg(STI);
210  Register SPReg = getSPReg(STI);
211 
212  // Skip to before the restores of callee-saved registers
213  // FIXME: assumes exactly one instruction is used to restore each
214  // callee-saved register.
215  auto LastFrameDestroy = std::prev(MBBI, MFI.getCalleeSavedInfo().size());
216 
217  uint64_t StackSize = MFI.getStackSize();
218  uint64_t FPOffset = StackSize - RVFI->getVarArgsSaveSize();
219 
220  // Restore the stack pointer using the value of the frame pointer. Only
221  // necessary if the stack pointer was modified, meaning the stack size is
222  // unknown.
223  if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) {
224  assert(hasFP(MF) && "frame pointer should not have been eliminated");
225  adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
227  }
228 
229  if (hasFP(MF)) {
230  // To find the instruction restoring FP from stack.
231  for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
232  if (I->mayLoad() && I->getOperand(0).isReg()) {
233  Register DestReg = I->getOperand(0).getReg();
234  if (DestReg == FPReg) {
235  // If there is frame pointer, after restoring $fp registers, we
236  // need adjust CFA to ($sp - FPOffset).
237  // Emit ".cfi_def_cfa $sp, -FPOffset"
238  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
239  nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));
240  BuildMI(MBB, std::next(I), DL,
241  TII->get(TargetOpcode::CFI_INSTRUCTION))
242  .addCFIIndex(CFIIndex);
243  break;
244  }
245  }
246  }
247  }
248 
249  // Add CFI directives for callee-saved registers.
250  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
251  // Iterate over list of callee-saved registers and emit .cfi_restore
252  // directives.
253  for (const auto &Entry : CSI) {
254  Register Reg = Entry.getReg();
255  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
256  nullptr, RI->getDwarfRegNum(Reg, true)));
257  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
258  .addCFIIndex(CFIIndex);
259  }
260 
261  // Deallocate stack
262  adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
263 
264  // After restoring $sp, we need to adjust CFA to $(sp + 0)
265  // Emit ".cfi_def_cfa_offset 0"
266  unsigned CFIIndex =
268  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
269  .addCFIIndex(CFIIndex);
270 }
271 
273  int FI,
274  unsigned &FrameReg) const {
275  const MachineFrameInfo &MFI = MF.getFrameInfo();
277  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
278 
279  // Callee-saved registers should be referenced relative to the stack
280  // pointer (positive offset), otherwise use the frame pointer (negative
281  // offset).
282  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
283  int MinCSFI = 0;
284  int MaxCSFI = -1;
285 
286  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea() +
287  MFI.getOffsetAdjustment();
288 
289  if (CSI.size()) {
290  MinCSFI = CSI[0].getFrameIdx();
291  MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
292  }
293 
294  if (FI >= MinCSFI && FI <= MaxCSFI) {
295  FrameReg = RISCV::X2;
296  Offset += MF.getFrameInfo().getStackSize();
297  } else if (RI->needsStackRealignment(MF)) {
298  assert(!MFI.hasVarSizedObjects() &&
299  "Unexpected combination of stack realignment and varsized objects");
300  // If the stack was realigned, the frame pointer is set in order to allow
301  // SP to be restored, but we still access stack objects using SP.
302  FrameReg = RISCV::X2;
303  Offset += MF.getFrameInfo().getStackSize();
304  } else {
305  FrameReg = RI->getFrameRegister(MF);
306  if (hasFP(MF))
307  Offset += RVFI->getVarArgsSaveSize();
308  else
309  Offset += MF.getFrameInfo().getStackSize();
310  }
311  return Offset;
312 }
313 
315  BitVector &SavedRegs,
316  RegScavenger *RS) const {
318  // Unconditionally spill RA and FP only if the function uses a frame
319  // pointer.
320  if (hasFP(MF)) {
321  SavedRegs.set(RISCV::X1);
322  SavedRegs.set(RISCV::X8);
323  }
324 
325  // If interrupt is enabled and there are calls in the handler,
326  // unconditionally save all Caller-saved registers and
327  // all FP registers, regardless whether they are used.
328  MachineFrameInfo &MFI = MF.getFrameInfo();
329 
330  if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
331 
332  static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
333  RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
334  RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
335  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
336  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
337  };
338 
339  for (unsigned i = 0; CSRegs[i]; ++i)
340  SavedRegs.set(CSRegs[i]);
341 
342  if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
343  MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
344 
345  // If interrupt is enabled, this list contains all FP registers.
346  const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
347 
348  for (unsigned i = 0; Regs[i]; ++i)
349  if (RISCV::FPR32RegClass.contains(Regs[i]) ||
350  RISCV::FPR64RegClass.contains(Regs[i]))
351  SavedRegs.set(Regs[i]);
352  }
353  }
354 }
355 
357  MachineFunction &MF, RegScavenger *RS) const {
358  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
359  MachineFrameInfo &MFI = MF.getFrameInfo();
360  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
361  // estimateStackSize has been observed to under-estimate the final stack
362  // size, so give ourselves wiggle-room by checking for stack size
363  // representable an 11-bit signed field rather than 12-bits.
364  // FIXME: It may be possible to craft a function with a small stack that
365  // still needs an emergency spill slot for branch relaxation. This case
366  // would currently be missed.
367  if (!isInt<11>(MFI.estimateStackSize(MF))) {
368  int RegScavFI = MFI.CreateStackObject(
369  RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);
370  RS->addScavengingFrameIndex(RegScavFI);
371  }
372 }
373 
374 // Not preserve stack space within prologue for outgoing variables when the
375 // function contains variable size objects and let eliminateCallFramePseudoInstr
376 // preserve stack space for it.
378  return !MF.getFrameInfo().hasVarSizedObjects();
379 }
380 
381 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
385  Register SPReg = RISCV::X2;
386  DebugLoc DL = MI->getDebugLoc();
387 
388  if (!hasReservedCallFrame(MF)) {
389  // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
390  // ADJCALLSTACKUP must be converted to instructions manipulating the stack
391  // pointer. This is necessary when there is a variable length stack
392  // allocation (e.g. alloca), which means it's not possible to allocate
393  // space for outgoing arguments from within the function prologue.
394  int64_t Amount = MI->getOperand(0).getImm();
395 
396  if (Amount != 0) {
397  // Ensure the stack remains aligned after adjustment.
398  Amount = alignSPAdjust(Amount);
399 
400  if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
401  Amount = -Amount;
402 
403  adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
404  }
405  }
406 
407  return MBB.erase(MI);
408 }
static Register getSPReg(const RISCVSubtarget &STI)
BitVector & set()
Definition: BitVector.h:397
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:507
unsigned Reg
const RISCVRegisterInfo * getRegisterInfo() const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
A debug info location.
Definition: DebugLoc.h:33
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:494
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment. ...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:480
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void setStackSize(uint64_t Size)
Set the size of the stack.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register)
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
Definition: MCDwarf.h:540
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
bool hasStdExtD() const
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
static Register getFPReg(const RISCVSubtarget &STI)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:126
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetOptions Options
#define I(x, y, z)
Definition: MD5.cpp:58
void setMaxCallFrameSize(unsigned S)
int getOffsetAdjustment() const
Return the correction for frame offsets.
const RISCVSubtarget & STI
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const RISCVInstrInfo * getInstrInfo() const override
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool hasCalls() const
Return true if the current function has any function calls.