LLVM  7.0.0svn
TargetRegisterInfo.cpp
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1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetRegisterInfo interface.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/Printable.h"
34 #include <cassert>
35 #include <utility>
36 
37 #define DEBUG_TYPE "target-reg-info"
38 
39 using namespace llvm;
40 
43  const char *const *SRINames,
44  const LaneBitmask *SRILaneMasks,
45  LaneBitmask SRICoveringLanes,
46  const RegClassInfo *const RCIs,
47  unsigned Mode)
48  : InfoDesc(ID), SubRegIndexNames(SRINames),
49  SubRegIndexLaneMasks(SRILaneMasks),
50  RegClassBegin(RCB), RegClassEnd(RCE),
51  CoveringLanes(SRICoveringLanes),
52  RCInfos(RCIs), HwMode(Mode) {
53 }
54 
56 
58  const {
59  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
60  RegisterSet.set(*AI);
61 }
62 
64  ArrayRef<MCPhysReg> Exceptions) const {
65  // Check that all super registers of reserved regs are reserved as well.
66  BitVector Checked(getNumRegs());
67  for (unsigned Reg : RegisterSet.set_bits()) {
68  if (Checked[Reg])
69  continue;
70  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
71  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
72  dbgs() << "Error: Super register " << printReg(*SR, this)
73  << " of reserved register " << printReg(Reg, this)
74  << " is not reserved.\n";
75  return false;
76  }
77 
78  // We transitively check superregs. So we can remember this for later
79  // to avoid compiletime explosion in deep register hierarchies.
80  Checked.set(*SR);
81  }
82  }
83  return true;
84 }
85 
86 namespace llvm {
87 
89  unsigned SubIdx, const MachineRegisterInfo *MRI) {
90  return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
91  if (!Reg)
92  OS << "$noreg";
93  else if (TargetRegisterInfo::isStackSlot(Reg))
94  OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
96  StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
97  if (Name != "") {
98  OS << '%' << Name;
99  } else {
100  OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
101  }
102  }
103  else if (!TRI)
104  OS << '$' << "physreg" << Reg;
105  else if (Reg < TRI->getNumRegs()) {
106  OS << '$';
107  printLowerCase(TRI->getName(Reg), OS);
108  } else
109  llvm_unreachable("Register kind is unsupported.");
110 
111  if (SubIdx) {
112  if (TRI)
113  OS << ':' << TRI->getSubRegIndexName(SubIdx);
114  else
115  OS << ":sub(" << SubIdx << ')';
116  }
117  });
118 }
119 
120 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
121  return Printable([Unit, TRI](raw_ostream &OS) {
122  // Generic printout when TRI is missing.
123  if (!TRI) {
124  OS << "Unit~" << Unit;
125  return;
126  }
127 
128  // Check for invalid register units.
129  if (Unit >= TRI->getNumRegUnits()) {
130  OS << "BadUnit~" << Unit;
131  return;
132  }
133 
134  // Normal units have at least one root.
135  MCRegUnitRootIterator Roots(Unit, TRI);
136  assert(Roots.isValid() && "Unit has no roots.");
137  OS << TRI->getName(*Roots);
138  for (++Roots; Roots.isValid(); ++Roots)
139  OS << '~' << TRI->getName(*Roots);
140  });
141 }
142 
143 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
144  return Printable([Unit, TRI](raw_ostream &OS) {
145  if (TRI && TRI->isVirtualRegister(Unit)) {
146  OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
147  } else {
148  OS << printRegUnit(Unit, TRI);
149  }
150  });
151 }
152 
154  const TargetRegisterInfo *TRI) {
155  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
156  if (RegInfo.getRegClassOrNull(Reg))
157  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
158  else if (RegInfo.getRegBankOrNull(Reg))
159  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
160  else {
161  OS << "_";
162  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
163  "Generic registers must have a valid type");
164  }
165  });
166 }
167 
168 } // end namespace llvm
169 
170 /// getAllocatableClass - Return the maximal subclass of the given register
171 /// class that is alloctable, or NULL.
172 const TargetRegisterClass *
174  if (!RC || RC->isAllocatable())
175  return RC;
176 
177  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
178  ++It) {
179  const TargetRegisterClass *SubRC = getRegClass(It.getID());
180  if (SubRC->isAllocatable())
181  return SubRC;
182  }
183  return nullptr;
184 }
185 
186 /// getMinimalPhysRegClass - Returns the Register Class of a physical
187 /// register of the given type, picking the most sub register class of
188 /// the right type that contains this physreg.
189 const TargetRegisterClass *
191  assert(isPhysicalRegister(reg) && "reg must be a physical register");
192 
193  // Pick the most sub register class of the right type that contains
194  // this physreg.
195  const TargetRegisterClass* BestRC = nullptr;
196  for (const TargetRegisterClass* RC : regclasses()) {
197  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
198  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
199  BestRC = RC;
200  }
201 
202  assert(BestRC && "Couldn't find the register class");
203  return BestRC;
204 }
205 
206 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
207 /// registers for the specific register class.
209  const TargetRegisterClass *RC, BitVector &R){
210  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
212  for (unsigned i = 0; i != Order.size(); ++i)
213  R.set(Order[i]);
214 }
215 
217  const TargetRegisterClass *RC) const {
218  BitVector Allocatable(getNumRegs());
219  if (RC) {
220  // A register class with no allocatable subclass returns an empty set.
221  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
222  if (SubClass)
223  getAllocatableSetForRC(MF, SubClass, Allocatable);
224  } else {
225  for (const TargetRegisterClass *C : regclasses())
226  if (C->isAllocatable())
227  getAllocatableSetForRC(MF, C, Allocatable);
228  }
229 
230  // Mask out the reserved registers
231  BitVector Reserved = getReservedRegs(MF);
232  Allocatable &= Reserved.flip();
233 
234  return Allocatable;
235 }
236 
237 static inline
239  const uint32_t *B,
240  const TargetRegisterInfo *TRI,
241  const MVT::SimpleValueType SVT =
243  const MVT VT(SVT);
244  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
245  if (unsigned Common = *A++ & *B++) {
246  const TargetRegisterClass *RC =
247  TRI->getRegClass(I + countTrailingZeros(Common));
248  if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT))
249  return RC;
250  }
251  return nullptr;
252 }
253 
254 const TargetRegisterClass *
256  const TargetRegisterClass *B,
257  const MVT::SimpleValueType SVT) const {
258  // First take care of the trivial cases.
259  if (A == B)
260  return A;
261  if (!A || !B)
262  return nullptr;
263 
264  // Register classes are ordered topologically, so the largest common
265  // sub-class it the common sub-class with the smallest ID.
266  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
267 }
268 
269 const TargetRegisterClass *
271  const TargetRegisterClass *B,
272  unsigned Idx) const {
273  assert(A && B && "Missing register class");
274  assert(Idx && "Bad sub-register index");
275 
276  // Find Idx in the list of super-register indices.
277  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
278  if (RCI.getSubReg() == Idx)
279  // The bit mask contains all register classes that are projected into B
280  // by Idx. Find a class that is also a sub-class of A.
281  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
282  return nullptr;
283 }
284 
286 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
287  const TargetRegisterClass *RCB, unsigned SubB,
288  unsigned &PreA, unsigned &PreB) const {
289  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
290 
291  // Search all pairs of sub-register indices that project into RCA and RCB
292  // respectively. This is quadratic, but usually the sets are very small. On
293  // most targets like X86, there will only be a single sub-register index
294  // (e.g., sub_16bit projecting into GR16).
295  //
296  // The worst case is a register class like DPR on ARM.
297  // We have indices dsub_0..dsub_7 projecting into that class.
298  //
299  // It is very common that one register class is a sub-register of the other.
300  // Arrange for RCA to be the larger register so the answer will be found in
301  // the first iteration. This makes the search linear for the most common
302  // case.
303  const TargetRegisterClass *BestRC = nullptr;
304  unsigned *BestPreA = &PreA;
305  unsigned *BestPreB = &PreB;
306  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
307  std::swap(RCA, RCB);
308  std::swap(SubA, SubB);
309  std::swap(BestPreA, BestPreB);
310  }
311 
312  // Also terminate the search one we have found a register class as small as
313  // RCA.
314  unsigned MinSize = getRegSizeInBits(*RCA);
315 
316  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
317  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
318  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
319  // Check if a common super-register class exists for this index pair.
320  const TargetRegisterClass *RC =
321  firstCommonClass(IA.getMask(), IB.getMask(), this);
322  if (!RC || getRegSizeInBits(*RC) < MinSize)
323  continue;
324 
325  // The indexes must compose identically: PreA+SubA == PreB+SubB.
326  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
327  if (FinalA != FinalB)
328  continue;
329 
330  // Is RC a better candidate than BestRC?
331  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
332  continue;
333 
334  // Yes, RC is the smallest super-register seen so far.
335  BestRC = RC;
336  *BestPreA = IA.getSubReg();
337  *BestPreB = IB.getSubReg();
338 
339  // Bail early if we reached MinSize. We won't find a better candidate.
340  if (getRegSizeInBits(*BestRC) == MinSize)
341  return BestRC;
342  }
343  }
344  return BestRC;
345 }
346 
347 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
348 /// share the same register file.
350  const TargetRegisterClass *DefRC,
351  unsigned DefSubReg,
352  const TargetRegisterClass *SrcRC,
353  unsigned SrcSubReg) {
354  // Same register class.
355  if (DefRC == SrcRC)
356  return true;
357 
358  // Both operands are sub registers. Check if they share a register class.
359  unsigned SrcIdx, DefIdx;
360  if (SrcSubReg && DefSubReg) {
361  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
362  SrcIdx, DefIdx) != nullptr;
363  }
364 
365  // At most one of the register is a sub register, make it Src to avoid
366  // duplicating the test.
367  if (!SrcSubReg) {
368  std::swap(DefSubReg, SrcSubReg);
369  std::swap(DefRC, SrcRC);
370  }
371 
372  // One of the register is a sub register, check if we can get a superclass.
373  if (SrcSubReg)
374  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
375 
376  // Plain copy.
377  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
378 }
379 
381  unsigned DefSubReg,
382  const TargetRegisterClass *SrcRC,
383  unsigned SrcSubReg) const {
384  // If this source does not incur a cross register bank copy, use it.
385  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
386 }
387 
388 // Compute target-independent register allocator hints to help eliminate copies.
389 bool
391  ArrayRef<MCPhysReg> Order,
393  const MachineFunction &MF,
394  const VirtRegMap *VRM,
395  const LiveRegMatrix *Matrix) const {
396  const MachineRegisterInfo &MRI = MF.getRegInfo();
397  const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
398  MRI.getRegAllocationHints(VirtReg);
399 
400  // First hint may be a target hint.
401  bool Skip = (Hints_MRI.first != 0);
402  for (auto Reg : Hints_MRI.second) {
403  if (Skip) {
404  Skip = false;
405  continue;
406  }
407 
408  // Target-independent hints are either a physical or a virtual register.
409  unsigned Phys = Reg;
410  if (VRM && isVirtualRegister(Phys))
411  Phys = VRM->getPhys(Phys);
412 
413  // Check that Phys is a valid hint in VirtReg's register class.
414  if (!isPhysicalRegister(Phys))
415  continue;
416  if (MRI.isReserved(Phys))
417  continue;
418  // Check that Phys is in the allocation order. We shouldn't heed hints
419  // from VirtReg's register class if they aren't in the allocation order. The
420  // target probably has a reason for removing the register.
421  if (!is_contained(Order, Phys))
422  continue;
423 
424  // All clear, tell the register allocator to prefer this register.
425  Hints.push_back(Phys);
426  }
427  return false;
428 }
429 
431  return !MF.getFunction().hasFnAttribute("no-realign-stack");
432 }
433 
435  const MachineFunction &MF) const {
436  const MachineFrameInfo &MFI = MF.getFrameInfo();
438  const Function &F = MF.getFunction();
439  unsigned StackAlign = TFI->getStackAlignment();
440  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
441  F.hasFnAttribute(Attribute::StackAlignment));
442  if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
443  if (canRealignStack(MF))
444  return true;
445  DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() << "\n");
446  }
447  return false;
448 }
449 
451  const uint32_t *mask1) const {
452  unsigned N = (getNumRegs()+31) / 32;
453  for (unsigned I = 0; I < N; ++I)
454  if ((mask0[I] & mask1[I]) != mask0[I])
455  return false;
456  return true;
457 }
458 
460  const MachineRegisterInfo &MRI) const {
461  const TargetRegisterClass *RC{};
462  if (isPhysicalRegister(Reg)) {
463  // The size is not directly available for physical registers.
464  // Instead, we need to access a register class that contains Reg and
465  // get the size of that register class.
466  RC = getMinimalPhysRegClass(Reg);
467  } else {
468  LLT Ty = MRI.getType(Reg);
469  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
470  // If Reg is not a generic register, query the register class to
471  // get its size.
472  if (RegSize)
473  return RegSize;
474  // Since Reg is not a generic register, it must have a register class.
475  RC = MRI.getRegClass(Reg);
476  }
477  assert(RC && "Unable to deduce the register class");
478  return getRegSizeInBits(*RC);
479 }
480 
481 unsigned
483  const MachineRegisterInfo *MRI) const {
484  while (true) {
485  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
486  if (!MI->isCopyLike())
487  return SrcReg;
488 
489  unsigned CopySrcReg;
490  if (MI->isCopy())
491  CopySrcReg = MI->getOperand(1).getReg();
492  else {
493  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
494  CopySrcReg = MI->getOperand(2).getReg();
495  }
496 
497  if (!isVirtualRegister(CopySrcReg))
498  return CopySrcReg;
499 
500  SrcReg = CopySrcReg;
501  }
502 }
503 
504 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
506 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
507  const TargetRegisterInfo *TRI) {
508  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
509 }
510 #endif
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
void push_back(const T &Elt)
Definition: SmallVector.h:212
BitVector & set()
Definition: BitVector.h:398
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SI Whole Quad Mode
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
bool isSubregToReg() const
Definition: MachineInstr.h:848
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
F(f)
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:874
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Live Register Matrix
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
MCSuperRegIterator enumerates all super-registers of Reg.
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:413
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
iterator_range< regclass_iterator > regclasses() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getNumRegClasses() const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
MCRegUnitRootIterator enumerates the root registers of a register unit.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Machine Value Type.
const TargetRegisterClass *const * regclass_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isValid() const
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Extra information, not in MCRegisterDesc, about registers.
bool isCopy() const
Definition: MachineInstr.h:860
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Information about stack frame layout on the target.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
BitVector & flip()
Definition: BitVector.h:478
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:224
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual const TargetFrameLowering * getFrameLowering() const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:108
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printLowerCase(StringRef String, raw_ostream &Out)
printLowerCase - Print each character as lowercase if it is uppercase.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RSI, unsigned Mode=0)
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const std::pair< unsigned, SmallVector< unsigned, 4 > > & getRegAllocationHints(unsigned VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isValid() const
Check if the iterator is at the end of the list.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
StringRef getVRegName(unsigned Reg) const
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:905