LLVM  6.0.0svn
TargetRegisterInfo.cpp
Go to the documentation of this file.
1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetRegisterInfo interface.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/Printable.h"
33 #include <cassert>
34 #include <utility>
35 
36 #define DEBUG_TYPE "target-reg-info"
37 
38 using namespace llvm;
39 
42  const char *const *SRINames,
43  const LaneBitmask *SRILaneMasks,
44  LaneBitmask SRICoveringLanes,
45  const RegClassInfo *const RCIs,
46  unsigned Mode)
47  : InfoDesc(ID), SubRegIndexNames(SRINames),
48  SubRegIndexLaneMasks(SRILaneMasks),
49  RegClassBegin(RCB), RegClassEnd(RCE),
50  CoveringLanes(SRICoveringLanes),
51  RCInfos(RCIs), HwMode(Mode) {
52 }
53 
55 
57  const {
58  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
59  RegisterSet.set(*AI);
60 }
61 
63  ArrayRef<MCPhysReg> Exceptions) const {
64  // Check that all super registers of reserved regs are reserved as well.
65  BitVector Checked(getNumRegs());
66  for (unsigned Reg : RegisterSet.set_bits()) {
67  if (Checked[Reg])
68  continue;
69  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
70  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
71  dbgs() << "Error: Super register " << PrintReg(*SR, this)
72  << " of reserved register " << PrintReg(Reg, this)
73  << " is not reserved.\n";
74  return false;
75  }
76 
77  // We transitively check superregs. So we can remember this for later
78  // to avoid compiletime explosion in deep register hierarchies.
79  Checked.set(*SR);
80  }
81  }
82  return true;
83 }
84 
85 namespace llvm {
86 
88  unsigned SubIdx) {
89  return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
90  if (!Reg)
91  OS << "%noreg";
92  else if (TargetRegisterInfo::isStackSlot(Reg))
93  OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
95  OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
96  else if (TRI && Reg < TRI->getNumRegs())
97  OS << '%' << TRI->getName(Reg);
98  else
99  OS << "%physreg" << Reg;
100  if (SubIdx) {
101  if (TRI)
102  OS << ':' << TRI->getSubRegIndexName(SubIdx);
103  else
104  OS << ":sub(" << SubIdx << ')';
105  }
106  });
107 }
108 
110  return Printable([Unit, TRI](raw_ostream &OS) {
111  // Generic printout when TRI is missing.
112  if (!TRI) {
113  OS << "Unit~" << Unit;
114  return;
115  }
116 
117  // Check for invalid register units.
118  if (Unit >= TRI->getNumRegUnits()) {
119  OS << "BadUnit~" << Unit;
120  return;
121  }
122 
123  // Normal units have at least one root.
124  MCRegUnitRootIterator Roots(Unit, TRI);
125  assert(Roots.isValid() && "Unit has no roots.");
126  OS << TRI->getName(*Roots);
127  for (++Roots; Roots.isValid(); ++Roots)
128  OS << '~' << TRI->getName(*Roots);
129  });
130 }
131 
133  return Printable([Unit, TRI](raw_ostream &OS) {
134  if (TRI && TRI->isVirtualRegister(Unit)) {
135  OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
136  } else {
137  OS << PrintRegUnit(Unit, TRI);
138  }
139  });
140 }
141 
142 } // end namespace llvm
143 
144 /// getAllocatableClass - Return the maximal subclass of the given register
145 /// class that is alloctable, or NULL.
146 const TargetRegisterClass *
148  if (!RC || RC->isAllocatable())
149  return RC;
150 
151  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
152  ++It) {
153  const TargetRegisterClass *SubRC = getRegClass(It.getID());
154  if (SubRC->isAllocatable())
155  return SubRC;
156  }
157  return nullptr;
158 }
159 
160 /// getMinimalPhysRegClass - Returns the Register Class of a physical
161 /// register of the given type, picking the most sub register class of
162 /// the right type that contains this physreg.
163 const TargetRegisterClass *
165  assert(isPhysicalRegister(reg) && "reg must be a physical register");
166 
167  // Pick the most sub register class of the right type that contains
168  // this physreg.
169  const TargetRegisterClass* BestRC = nullptr;
170  for (const TargetRegisterClass* RC : regclasses()) {
171  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
172  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
173  BestRC = RC;
174  }
175 
176  assert(BestRC && "Couldn't find the register class");
177  return BestRC;
178 }
179 
180 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
181 /// registers for the specific register class.
183  const TargetRegisterClass *RC, BitVector &R){
184  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
186  for (unsigned i = 0; i != Order.size(); ++i)
187  R.set(Order[i]);
188 }
189 
191  const TargetRegisterClass *RC) const {
192  BitVector Allocatable(getNumRegs());
193  if (RC) {
194  // A register class with no allocatable subclass returns an empty set.
195  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
196  if (SubClass)
197  getAllocatableSetForRC(MF, SubClass, Allocatable);
198  } else {
199  for (const TargetRegisterClass *C : regclasses())
200  if (C->isAllocatable())
201  getAllocatableSetForRC(MF, C, Allocatable);
202  }
203 
204  // Mask out the reserved registers
205  BitVector Reserved = getReservedRegs(MF);
206  Allocatable &= Reserved.flip();
207 
208  return Allocatable;
209 }
210 
211 static inline
213  const uint32_t *B,
214  const TargetRegisterInfo *TRI,
215  const MVT::SimpleValueType SVT =
217  const MVT VT(SVT);
218  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
219  if (unsigned Common = *A++ & *B++) {
220  const TargetRegisterClass *RC =
221  TRI->getRegClass(I + countTrailingZeros(Common));
222  if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT))
223  return RC;
224  }
225  return nullptr;
226 }
227 
228 const TargetRegisterClass *
230  const TargetRegisterClass *B,
231  const MVT::SimpleValueType SVT) const {
232  // First take care of the trivial cases.
233  if (A == B)
234  return A;
235  if (!A || !B)
236  return nullptr;
237 
238  // Register classes are ordered topologically, so the largest common
239  // sub-class it the common sub-class with the smallest ID.
240  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
241 }
242 
243 const TargetRegisterClass *
245  const TargetRegisterClass *B,
246  unsigned Idx) const {
247  assert(A && B && "Missing register class");
248  assert(Idx && "Bad sub-register index");
249 
250  // Find Idx in the list of super-register indices.
251  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
252  if (RCI.getSubReg() == Idx)
253  // The bit mask contains all register classes that are projected into B
254  // by Idx. Find a class that is also a sub-class of A.
255  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
256  return nullptr;
257 }
258 
260 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
261  const TargetRegisterClass *RCB, unsigned SubB,
262  unsigned &PreA, unsigned &PreB) const {
263  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
264 
265  // Search all pairs of sub-register indices that project into RCA and RCB
266  // respectively. This is quadratic, but usually the sets are very small. On
267  // most targets like X86, there will only be a single sub-register index
268  // (e.g., sub_16bit projecting into GR16).
269  //
270  // The worst case is a register class like DPR on ARM.
271  // We have indices dsub_0..dsub_7 projecting into that class.
272  //
273  // It is very common that one register class is a sub-register of the other.
274  // Arrange for RCA to be the larger register so the answer will be found in
275  // the first iteration. This makes the search linear for the most common
276  // case.
277  const TargetRegisterClass *BestRC = nullptr;
278  unsigned *BestPreA = &PreA;
279  unsigned *BestPreB = &PreB;
280  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
281  std::swap(RCA, RCB);
282  std::swap(SubA, SubB);
283  std::swap(BestPreA, BestPreB);
284  }
285 
286  // Also terminate the search one we have found a register class as small as
287  // RCA.
288  unsigned MinSize = getRegSizeInBits(*RCA);
289 
290  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
291  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
292  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
293  // Check if a common super-register class exists for this index pair.
294  const TargetRegisterClass *RC =
295  firstCommonClass(IA.getMask(), IB.getMask(), this);
296  if (!RC || getRegSizeInBits(*RC) < MinSize)
297  continue;
298 
299  // The indexes must compose identically: PreA+SubA == PreB+SubB.
300  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
301  if (FinalA != FinalB)
302  continue;
303 
304  // Is RC a better candidate than BestRC?
305  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
306  continue;
307 
308  // Yes, RC is the smallest super-register seen so far.
309  BestRC = RC;
310  *BestPreA = IA.getSubReg();
311  *BestPreB = IB.getSubReg();
312 
313  // Bail early if we reached MinSize. We won't find a better candidate.
314  if (getRegSizeInBits(*BestRC) == MinSize)
315  return BestRC;
316  }
317  }
318  return BestRC;
319 }
320 
321 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
322 /// share the same register file.
324  const TargetRegisterClass *DefRC,
325  unsigned DefSubReg,
326  const TargetRegisterClass *SrcRC,
327  unsigned SrcSubReg) {
328  // Same register class.
329  if (DefRC == SrcRC)
330  return true;
331 
332  // Both operands are sub registers. Check if they share a register class.
333  unsigned SrcIdx, DefIdx;
334  if (SrcSubReg && DefSubReg) {
335  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
336  SrcIdx, DefIdx) != nullptr;
337  }
338 
339  // At most one of the register is a sub register, make it Src to avoid
340  // duplicating the test.
341  if (!SrcSubReg) {
342  std::swap(DefSubReg, SrcSubReg);
343  std::swap(DefRC, SrcRC);
344  }
345 
346  // One of the register is a sub register, check if we can get a superclass.
347  if (SrcSubReg)
348  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
349 
350  // Plain copy.
351  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
352 }
353 
355  unsigned DefSubReg,
356  const TargetRegisterClass *SrcRC,
357  unsigned SrcSubReg) const {
358  // If this source does not incur a cross register bank copy, use it.
359  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
360 }
361 
362 // Compute target-independent register allocator hints to help eliminate copies.
363 void
365  ArrayRef<MCPhysReg> Order,
367  const MachineFunction &MF,
368  const VirtRegMap *VRM,
369  const LiveRegMatrix *Matrix) const {
370  const MachineRegisterInfo &MRI = MF.getRegInfo();
371  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
372 
373  // Hints with HintType != 0 were set by target-dependent code.
374  // Such targets must provide their own implementation of
375  // TRI::getRegAllocationHints to interpret those hint types.
376  assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints");
377 
378  // Target-independent hints are either a physical or a virtual register.
379  unsigned Phys = Hint.second;
380  if (VRM && isVirtualRegister(Phys))
381  Phys = VRM->getPhys(Phys);
382 
383  // Check that Phys is a valid hint in VirtReg's register class.
384  if (!isPhysicalRegister(Phys))
385  return;
386  if (MRI.isReserved(Phys))
387  return;
388  // Check that Phys is in the allocation order. We shouldn't heed hints
389  // from VirtReg's register class if they aren't in the allocation order. The
390  // target probably has a reason for removing the register.
391  if (!is_contained(Order, Phys))
392  return;
393 
394  // All clear, tell the register allocator to prefer this register.
395  Hints.push_back(Phys);
396 }
397 
399  return !MF.getFunction()->hasFnAttribute("no-realign-stack");
400 }
401 
403  const MachineFunction &MF) const {
404  const MachineFrameInfo &MFI = MF.getFrameInfo();
406  const Function *F = MF.getFunction();
407  unsigned StackAlign = TFI->getStackAlignment();
408  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
409  F->hasFnAttribute(Attribute::StackAlignment));
410  if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) {
411  if (canRealignStack(MF))
412  return true;
413  DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n");
414  }
415  return false;
416 }
417 
419  const uint32_t *mask1) const {
420  unsigned N = (getNumRegs()+31) / 32;
421  for (unsigned I = 0; I < N; ++I)
422  if ((mask0[I] & mask1[I]) != mask0[I])
423  return false;
424  return true;
425 }
426 
427 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
429 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
430  const TargetRegisterInfo *TRI) {
431  dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
432 }
433 #endif
uint64_t CallInst * C
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
void push_back(const T &Elt)
Definition: SmallVector.h:212
BitVector & set()
Definition: BitVector.h:398
SI Whole Quad Mode
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
F(f)
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Live Register Matrix
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
MCSuperRegIterator enumerates all super-registers of Reg.
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:413
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
iterator_range< regclass_iterator > regclasses() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
unsigned getNumRegClasses() const
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
MCRegUnitRootIterator enumerates the root registers of a register unit.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
MCRegisterClass - Base class of TargetRegisterClass.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Extra information, not in MCRegisterDesc, about registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Information about stack frame layout on the target.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
BitVector & flip()
Definition: BitVector.h:478
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:218
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual const TargetFrameLowering * getFrameLowering() const
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
std::vector< uint8_t > Unit
Definition: FuzzerDefs.h:105
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RSI, unsigned Mode=0)
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isValid() const
Check if the iterator is at the end of the list.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:870