LLVM  7.0.0svn
TargetRegisterInfo.cpp
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1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetRegisterInfo interface.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/Printable.h"
34 #include <cassert>
35 #include <utility>
36 
37 #define DEBUG_TYPE "target-reg-info"
38 
39 using namespace llvm;
40 
43  const char *const *SRINames,
44  const LaneBitmask *SRILaneMasks,
45  LaneBitmask SRICoveringLanes,
46  const RegClassInfo *const RCIs,
47  unsigned Mode)
48  : InfoDesc(ID), SubRegIndexNames(SRINames),
49  SubRegIndexLaneMasks(SRILaneMasks),
50  RegClassBegin(RCB), RegClassEnd(RCE),
51  CoveringLanes(SRICoveringLanes),
52  RCInfos(RCIs), HwMode(Mode) {
53 }
54 
56 
58  const {
59  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
60  RegisterSet.set(*AI);
61 }
62 
64  ArrayRef<MCPhysReg> Exceptions) const {
65  // Check that all super registers of reserved regs are reserved as well.
66  BitVector Checked(getNumRegs());
67  for (unsigned Reg : RegisterSet.set_bits()) {
68  if (Checked[Reg])
69  continue;
70  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
71  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
72  dbgs() << "Error: Super register " << printReg(*SR, this)
73  << " of reserved register " << printReg(Reg, this)
74  << " is not reserved.\n";
75  return false;
76  }
77 
78  // We transitively check superregs. So we can remember this for later
79  // to avoid compiletime explosion in deep register hierarchies.
80  Checked.set(*SR);
81  }
82  }
83  return true;
84 }
85 
86 namespace llvm {
87 
89  unsigned SubIdx) {
90  return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
91  if (!Reg)
92  OS << "$noreg";
93  else if (TargetRegisterInfo::isStackSlot(Reg))
94  OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
96  OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
97  else if (!TRI)
98  OS << '$' << "physreg" << Reg;
99  else if (Reg < TRI->getNumRegs()) {
100  OS << '$';
101  printLowerCase(TRI->getName(Reg), OS);
102  } else
103  llvm_unreachable("Register kind is unsupported.");
104 
105  if (SubIdx) {
106  if (TRI)
107  OS << ':' << TRI->getSubRegIndexName(SubIdx);
108  else
109  OS << ":sub(" << SubIdx << ')';
110  }
111  });
112 }
113 
114 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
115  return Printable([Unit, TRI](raw_ostream &OS) {
116  // Generic printout when TRI is missing.
117  if (!TRI) {
118  OS << "Unit~" << Unit;
119  return;
120  }
121 
122  // Check for invalid register units.
123  if (Unit >= TRI->getNumRegUnits()) {
124  OS << "BadUnit~" << Unit;
125  return;
126  }
127 
128  // Normal units have at least one root.
129  MCRegUnitRootIterator Roots(Unit, TRI);
130  assert(Roots.isValid() && "Unit has no roots.");
131  OS << TRI->getName(*Roots);
132  for (++Roots; Roots.isValid(); ++Roots)
133  OS << '~' << TRI->getName(*Roots);
134  });
135 }
136 
137 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
138  return Printable([Unit, TRI](raw_ostream &OS) {
139  if (TRI && TRI->isVirtualRegister(Unit)) {
140  OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
141  } else {
142  OS << printRegUnit(Unit, TRI);
143  }
144  });
145 }
146 
148  const TargetRegisterInfo *TRI) {
149  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
150  if (RegInfo.getRegClassOrNull(Reg))
151  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
152  else if (RegInfo.getRegBankOrNull(Reg))
153  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
154  else {
155  OS << "_";
156  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
157  "Generic registers must have a valid type");
158  }
159  });
160 }
161 
162 } // end namespace llvm
163 
164 /// getAllocatableClass - Return the maximal subclass of the given register
165 /// class that is alloctable, or NULL.
166 const TargetRegisterClass *
168  if (!RC || RC->isAllocatable())
169  return RC;
170 
171  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
172  ++It) {
173  const TargetRegisterClass *SubRC = getRegClass(It.getID());
174  if (SubRC->isAllocatable())
175  return SubRC;
176  }
177  return nullptr;
178 }
179 
180 /// getMinimalPhysRegClass - Returns the Register Class of a physical
181 /// register of the given type, picking the most sub register class of
182 /// the right type that contains this physreg.
183 const TargetRegisterClass *
185  assert(isPhysicalRegister(reg) && "reg must be a physical register");
186 
187  // Pick the most sub register class of the right type that contains
188  // this physreg.
189  const TargetRegisterClass* BestRC = nullptr;
190  for (const TargetRegisterClass* RC : regclasses()) {
191  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
192  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
193  BestRC = RC;
194  }
195 
196  assert(BestRC && "Couldn't find the register class");
197  return BestRC;
198 }
199 
200 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
201 /// registers for the specific register class.
203  const TargetRegisterClass *RC, BitVector &R){
204  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
206  for (unsigned i = 0; i != Order.size(); ++i)
207  R.set(Order[i]);
208 }
209 
211  const TargetRegisterClass *RC) const {
212  BitVector Allocatable(getNumRegs());
213  if (RC) {
214  // A register class with no allocatable subclass returns an empty set.
215  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
216  if (SubClass)
217  getAllocatableSetForRC(MF, SubClass, Allocatable);
218  } else {
219  for (const TargetRegisterClass *C : regclasses())
220  if (C->isAllocatable())
221  getAllocatableSetForRC(MF, C, Allocatable);
222  }
223 
224  // Mask out the reserved registers
225  BitVector Reserved = getReservedRegs(MF);
226  Allocatable &= Reserved.flip();
227 
228  return Allocatable;
229 }
230 
231 static inline
233  const uint32_t *B,
234  const TargetRegisterInfo *TRI,
235  const MVT::SimpleValueType SVT =
237  const MVT VT(SVT);
238  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
239  if (unsigned Common = *A++ & *B++) {
240  const TargetRegisterClass *RC =
241  TRI->getRegClass(I + countTrailingZeros(Common));
242  if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT))
243  return RC;
244  }
245  return nullptr;
246 }
247 
248 const TargetRegisterClass *
250  const TargetRegisterClass *B,
251  const MVT::SimpleValueType SVT) const {
252  // First take care of the trivial cases.
253  if (A == B)
254  return A;
255  if (!A || !B)
256  return nullptr;
257 
258  // Register classes are ordered topologically, so the largest common
259  // sub-class it the common sub-class with the smallest ID.
260  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
261 }
262 
263 const TargetRegisterClass *
265  const TargetRegisterClass *B,
266  unsigned Idx) const {
267  assert(A && B && "Missing register class");
268  assert(Idx && "Bad sub-register index");
269 
270  // Find Idx in the list of super-register indices.
271  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
272  if (RCI.getSubReg() == Idx)
273  // The bit mask contains all register classes that are projected into B
274  // by Idx. Find a class that is also a sub-class of A.
275  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
276  return nullptr;
277 }
278 
280 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
281  const TargetRegisterClass *RCB, unsigned SubB,
282  unsigned &PreA, unsigned &PreB) const {
283  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
284 
285  // Search all pairs of sub-register indices that project into RCA and RCB
286  // respectively. This is quadratic, but usually the sets are very small. On
287  // most targets like X86, there will only be a single sub-register index
288  // (e.g., sub_16bit projecting into GR16).
289  //
290  // The worst case is a register class like DPR on ARM.
291  // We have indices dsub_0..dsub_7 projecting into that class.
292  //
293  // It is very common that one register class is a sub-register of the other.
294  // Arrange for RCA to be the larger register so the answer will be found in
295  // the first iteration. This makes the search linear for the most common
296  // case.
297  const TargetRegisterClass *BestRC = nullptr;
298  unsigned *BestPreA = &PreA;
299  unsigned *BestPreB = &PreB;
300  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
301  std::swap(RCA, RCB);
302  std::swap(SubA, SubB);
303  std::swap(BestPreA, BestPreB);
304  }
305 
306  // Also terminate the search one we have found a register class as small as
307  // RCA.
308  unsigned MinSize = getRegSizeInBits(*RCA);
309 
310  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
311  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
312  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
313  // Check if a common super-register class exists for this index pair.
314  const TargetRegisterClass *RC =
315  firstCommonClass(IA.getMask(), IB.getMask(), this);
316  if (!RC || getRegSizeInBits(*RC) < MinSize)
317  continue;
318 
319  // The indexes must compose identically: PreA+SubA == PreB+SubB.
320  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
321  if (FinalA != FinalB)
322  continue;
323 
324  // Is RC a better candidate than BestRC?
325  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
326  continue;
327 
328  // Yes, RC is the smallest super-register seen so far.
329  BestRC = RC;
330  *BestPreA = IA.getSubReg();
331  *BestPreB = IB.getSubReg();
332 
333  // Bail early if we reached MinSize. We won't find a better candidate.
334  if (getRegSizeInBits(*BestRC) == MinSize)
335  return BestRC;
336  }
337  }
338  return BestRC;
339 }
340 
341 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
342 /// share the same register file.
344  const TargetRegisterClass *DefRC,
345  unsigned DefSubReg,
346  const TargetRegisterClass *SrcRC,
347  unsigned SrcSubReg) {
348  // Same register class.
349  if (DefRC == SrcRC)
350  return true;
351 
352  // Both operands are sub registers. Check if they share a register class.
353  unsigned SrcIdx, DefIdx;
354  if (SrcSubReg && DefSubReg) {
355  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
356  SrcIdx, DefIdx) != nullptr;
357  }
358 
359  // At most one of the register is a sub register, make it Src to avoid
360  // duplicating the test.
361  if (!SrcSubReg) {
362  std::swap(DefSubReg, SrcSubReg);
363  std::swap(DefRC, SrcRC);
364  }
365 
366  // One of the register is a sub register, check if we can get a superclass.
367  if (SrcSubReg)
368  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
369 
370  // Plain copy.
371  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
372 }
373 
375  unsigned DefSubReg,
376  const TargetRegisterClass *SrcRC,
377  unsigned SrcSubReg) const {
378  // If this source does not incur a cross register bank copy, use it.
379  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
380 }
381 
382 // Compute target-independent register allocator hints to help eliminate copies.
383 bool
385  ArrayRef<MCPhysReg> Order,
387  const MachineFunction &MF,
388  const VirtRegMap *VRM,
389  const LiveRegMatrix *Matrix) const {
390  const MachineRegisterInfo &MRI = MF.getRegInfo();
391  const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
392  MRI.getRegAllocationHints(VirtReg);
393 
394  // First hint may be a target hint.
395  bool Skip = (Hints_MRI.first != 0);
396  for (auto Reg : Hints_MRI.second) {
397  if (Skip) {
398  Skip = false;
399  continue;
400  }
401 
402  // Target-independent hints are either a physical or a virtual register.
403  unsigned Phys = Reg;
404  if (VRM && isVirtualRegister(Phys))
405  Phys = VRM->getPhys(Phys);
406 
407  // Check that Phys is a valid hint in VirtReg's register class.
408  if (!isPhysicalRegister(Phys))
409  continue;
410  if (MRI.isReserved(Phys))
411  continue;
412  // Check that Phys is in the allocation order. We shouldn't heed hints
413  // from VirtReg's register class if they aren't in the allocation order. The
414  // target probably has a reason for removing the register.
415  if (!is_contained(Order, Phys))
416  continue;
417 
418  // All clear, tell the register allocator to prefer this register.
419  Hints.push_back(Phys);
420  }
421  return false;
422 }
423 
425  return !MF.getFunction().hasFnAttribute("no-realign-stack");
426 }
427 
429  const MachineFunction &MF) const {
430  const MachineFrameInfo &MFI = MF.getFrameInfo();
432  const Function &F = MF.getFunction();
433  unsigned StackAlign = TFI->getStackAlignment();
434  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
435  F.hasFnAttribute(Attribute::StackAlignment));
436  if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
437  if (canRealignStack(MF))
438  return true;
439  DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() << "\n");
440  }
441  return false;
442 }
443 
445  const uint32_t *mask1) const {
446  unsigned N = (getNumRegs()+31) / 32;
447  for (unsigned I = 0; I < N; ++I)
448  if ((mask0[I] & mask1[I]) != mask0[I])
449  return false;
450  return true;
451 }
452 
454  const MachineRegisterInfo &MRI) const {
455  const TargetRegisterClass *RC{};
456  if (isPhysicalRegister(Reg)) {
457  // The size is not directly available for physical registers.
458  // Instead, we need to access a register class that contains Reg and
459  // get the size of that register class.
460  RC = getMinimalPhysRegClass(Reg);
461  } else {
462  LLT Ty = MRI.getType(Reg);
463  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
464  // If Reg is not a generic register, query the register class to
465  // get its size.
466  if (RegSize)
467  return RegSize;
468  // Since Reg is not a generic register, it must have a register class.
469  RC = MRI.getRegClass(Reg);
470  }
471  assert(RC && "Unable to deduce the register class");
472  return getRegSizeInBits(*RC);
473 }
474 
475 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
477 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
478  const TargetRegisterInfo *TRI) {
479  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
480 }
481 #endif
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
void push_back(const T &Elt)
Definition: SmallVector.h:212
BitVector & set()
Definition: BitVector.h:398
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SI Whole Quad Mode
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
F(f)
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Live Register Matrix
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
MCSuperRegIterator enumerates all super-registers of Reg.
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:413
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
iterator_range< regclass_iterator > regclasses() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getNumRegClasses() const
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
MCRegUnitRootIterator enumerates the root registers of a register unit.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
Machine Value Type.
const TargetRegisterClass *const * regclass_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isValid() const
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Extra information, not in MCRegisterDesc, about registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Information about stack frame layout on the target.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
BitVector & flip()
Definition: BitVector.h:478
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:224
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual const TargetFrameLowering * getFrameLowering() const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:108
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printLowerCase(StringRef String, raw_ostream &Out)
printLowerCase - Print each character as lowercase if it is uppercase.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RSI, unsigned Mode=0)
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const std::pair< unsigned, SmallVector< unsigned, 4 > > & getRegAllocationHints(unsigned VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isValid() const
Check if the iterator is at the end of the list.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:873