LLVM  8.0.0svn
TargetRegisterInfo.h
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1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
17 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/MC/LaneBitmask.h"
26 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Printable.h"
31 #include <cassert>
32 #include <cstdint>
33 #include <functional>
34 
35 namespace llvm {
36 
37 class BitVector;
38 class LiveRegMatrix;
39 class MachineFunction;
40 class MachineInstr;
41 class RegScavenger;
42 class VirtRegMap;
43 class LiveIntervals;
44 
46 public:
47  using iterator = const MCPhysReg *;
48  using const_iterator = const MCPhysReg *;
49  using sc_iterator = const TargetRegisterClass* const *;
50 
51  // Instance variables filled by tablegen, do not use!
54  const uint16_t *SuperRegIndices;
56  /// Classes with a higher priority value are assigned first by register
57  /// allocators using a greedy heuristic. The value is in the range [0,63].
58  const uint8_t AllocationPriority;
59  /// Whether the class supports two (or more) disjunct subregister indices.
60  const bool HasDisjunctSubRegs;
61  /// Whether a combination of subregisters can cover every register in the
62  /// class. See also the CoveredBySubRegs description in Target.td.
63  const bool CoveredBySubRegs;
65  ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
66 
67  /// Return the register class ID number.
68  unsigned getID() const { return MC->getID(); }
69 
70  /// begin/end - Return all of the registers in this class.
71  ///
72  iterator begin() const { return MC->begin(); }
73  iterator end() const { return MC->end(); }
74 
75  /// Return the number of registers in this class.
76  unsigned getNumRegs() const { return MC->getNumRegs(); }
77 
79  getRegisters() const {
80  return make_range(MC->begin(), MC->end());
81  }
82 
83  /// Return the specified register in the class.
84  unsigned getRegister(unsigned i) const {
85  return MC->getRegister(i);
86  }
87 
88  /// Return true if the specified register is included in this register class.
89  /// This does not include virtual registers.
90  bool contains(unsigned Reg) const {
91  return MC->contains(Reg);
92  }
93 
94  /// Return true if both registers are in this class.
95  bool contains(unsigned Reg1, unsigned Reg2) const {
96  return MC->contains(Reg1, Reg2);
97  }
98 
99  /// Return the cost of copying a value between two registers in this class.
100  /// A negative number means the register class is very expensive
101  /// to copy e.g. status flag register classes.
102  int getCopyCost() const { return MC->getCopyCost(); }
103 
104  /// Return true if this register class may be used to create virtual
105  /// registers.
106  bool isAllocatable() const { return MC->isAllocatable(); }
107 
108  /// Return true if the specified TargetRegisterClass
109  /// is a proper sub-class of this TargetRegisterClass.
110  bool hasSubClass(const TargetRegisterClass *RC) const {
111  return RC != this && hasSubClassEq(RC);
112  }
113 
114  /// Returns true if RC is a sub-class of or equal to this class.
115  bool hasSubClassEq(const TargetRegisterClass *RC) const {
116  unsigned ID = RC->getID();
117  return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
118  }
119 
120  /// Return true if the specified TargetRegisterClass is a
121  /// proper super-class of this TargetRegisterClass.
122  bool hasSuperClass(const TargetRegisterClass *RC) const {
123  return RC->hasSubClass(this);
124  }
125 
126  /// Returns true if RC is a super-class of or equal to this class.
127  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
128  return RC->hasSubClassEq(this);
129  }
130 
131  /// Returns a bit vector of subclasses, including this one.
132  /// The vector is indexed by class IDs.
133  ///
134  /// To use it, consider the returned array as a chunk of memory that
135  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
136  /// contains a bitset of the ID of the subclasses in big-endian style.
137 
138  /// I.e., the representation of the memory from left to right at the
139  /// bit level looks like:
140  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
141  /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
142  /// Where the number represents the class ID and XXX bits that
143  /// should be ignored.
144  ///
145  /// See the implementation of hasSubClassEq for an example of how it
146  /// can be used.
147  const uint32_t *getSubClassMask() const {
148  return SubClassMask;
149  }
150 
151  /// Returns a 0-terminated list of sub-register indices that project some
152  /// super-register class into this register class. The list has an entry for
153  /// each Idx such that:
154  ///
155  /// There exists SuperRC where:
156  /// For all Reg in SuperRC:
157  /// this->contains(Reg:Idx)
158  const uint16_t *getSuperRegIndices() const {
159  return SuperRegIndices;
160  }
161 
162  /// Returns a NULL-terminated list of super-classes. The
163  /// classes are ordered by ID which is also a topological ordering from large
164  /// to small classes. The list does NOT include the current class.
166  return SuperClasses;
167  }
168 
169  /// Return true if this TargetRegisterClass is a subset
170  /// class of at least one other TargetRegisterClass.
171  bool isASubClass() const {
172  return SuperClasses[0] != nullptr;
173  }
174 
175  /// Returns the preferred order for allocating registers from this register
176  /// class in MF. The raw order comes directly from the .td file and may
177  /// include reserved registers that are not allocatable.
178  /// Register allocators should also make sure to allocate
179  /// callee-saved registers only after all the volatiles are used. The
180  /// RegisterClassInfo class provides filtered allocation orders with
181  /// callee-saved registers moved to the end.
182  ///
183  /// The MachineFunction argument can be used to tune the allocatable
184  /// registers based on the characteristics of the function, subtarget, or
185  /// other criteria.
186  ///
187  /// By default, this method returns all registers in the class.
189  return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
190  }
191 
192  /// Returns the combination of all lane masks of register in this class.
193  /// The lane masks of the registers are the combination of all lane masks
194  /// of their subregisters. Returns 1 if there are no subregisters.
196  return LaneMask;
197  }
198 };
199 
200 /// Extra information, not in MCRegisterDesc, about registers.
201 /// These are used by codegen, not by MC.
203  unsigned CostPerUse; // Extra cost of instructions using register.
204  bool inAllocatableClass; // Register belongs to an allocatable regclass.
205 };
206 
207 /// Each TargetRegisterClass has a per register weight, and weight
208 /// limit which must be less than the limits of its pressure sets.
210  unsigned RegWeight;
211  unsigned WeightLimit;
212 };
213 
214 /// TargetRegisterInfo base class - We assume that the target defines a static
215 /// array of TargetRegisterDesc objects that represent all of the machine
216 /// registers that the target has. As such, we simply have to track a pointer
217 /// to this array so that we can turn register number into a register
218 /// descriptor.
219 ///
221 public:
222  using regclass_iterator = const TargetRegisterClass * const *;
224  struct RegClassInfo {
225  unsigned RegSize, SpillSize, SpillAlignment;
227  };
228 private:
229  const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
230  const char *const *SubRegIndexNames; // Names of subreg indexes.
231  // Pointer to array of lane masks, one per sub-reg index.
232  const LaneBitmask *SubRegIndexLaneMasks;
233 
234  regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
235  LaneBitmask CoveringLanes;
236  const RegClassInfo *const RCInfos;
237  unsigned HwMode;
238 
239 protected:
241  regclass_iterator RCB,
242  regclass_iterator RCE,
243  const char *const *SRINames,
244  const LaneBitmask *SRILaneMasks,
245  LaneBitmask CoveringLanes,
246  const RegClassInfo *const RCIs,
247  unsigned Mode = 0);
248  virtual ~TargetRegisterInfo();
249 
250 public:
251  // Register numbers can represent physical registers, virtual registers, and
252  // sometimes stack slots. The unsigned values are divided into these ranges:
253  //
254  // 0 Not a register, can be used as a sentinel.
255  // [1;2^30) Physical registers assigned by TableGen.
256  // [2^30;2^31) Stack slots. (Rarely used.)
257  // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
258  //
259  // Further sentinels can be allocated from the small negative integers.
260  // DenseMapInfo<unsigned> uses -1u and -2u.
261 
262  /// isStackSlot - Sometimes it is useful the be able to store a non-negative
263  /// frame index in a variable that normally holds a register. isStackSlot()
264  /// returns true if Reg is in the range used for stack slots.
265  ///
266  /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
267  /// slots, so if a variable may contains a stack slot, always check
268  /// isStackSlot() first.
269  ///
270  static bool isStackSlot(unsigned Reg) {
271  return int(Reg) >= (1 << 30);
272  }
273 
274  /// Compute the frame index from a register value representing a stack slot.
275  static int stackSlot2Index(unsigned Reg) {
276  assert(isStackSlot(Reg) && "Not a stack slot");
277  return int(Reg - (1u << 30));
278  }
279 
280  /// Convert a non-negative frame index to a stack slot register value.
281  static unsigned index2StackSlot(int FI) {
282  assert(FI >= 0 && "Cannot hold a negative frame index.");
283  return FI + (1u << 30);
284  }
285 
286  /// Return true if the specified register number is in
287  /// the physical register namespace.
288  static bool isPhysicalRegister(unsigned Reg) {
289  assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
290  return int(Reg) > 0;
291  }
292 
293  /// Return true if the specified register number is in
294  /// the virtual register namespace.
295  static bool isVirtualRegister(unsigned Reg) {
296  assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
297  return int(Reg) < 0;
298  }
299 
300  /// Convert a virtual register number to a 0-based index.
301  /// The first virtual register in a function will get the index 0.
302  static unsigned virtReg2Index(unsigned Reg) {
303  assert(isVirtualRegister(Reg) && "Not a virtual register");
304  return Reg & ~(1u << 31);
305  }
306 
307  /// Convert a 0-based index to a virtual register number.
308  /// This is the inverse operation of VirtReg2IndexFunctor below.
309  static unsigned index2VirtReg(unsigned Index) {
310  return Index | (1u << 31);
311  }
312 
313  /// Return the size in bits of a register from class RC.
314  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
315  return getRegClassInfo(RC).RegSize;
316  }
317 
318  /// Return the size in bytes of the stack slot allocated to hold a spilled
319  /// copy of a register from class RC.
320  unsigned getSpillSize(const TargetRegisterClass &RC) const {
321  return getRegClassInfo(RC).SpillSize / 8;
322  }
323 
324  /// Return the minimum required alignment in bytes for a spill slot for
325  /// a register of this class.
326  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
327  return getRegClassInfo(RC).SpillAlignment / 8;
328  }
329 
330  /// Return true if the given TargetRegisterClass has the ValueType T.
331  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
332  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
333  if (MVT(*I) == T)
334  return true;
335  return false;
336  }
337 
338  /// Loop over all of the value types that can be represented by values
339  /// in the given register class.
341  return getRegClassInfo(RC).VTList;
342  }
343 
345  vt_iterator I = legalclasstypes_begin(RC);
346  while (*I != MVT::Other)
347  ++I;
348  return I;
349  }
350 
351  /// Returns the Register Class of a physical register of the given type,
352  /// picking the most sub register class of the right type that contains this
353  /// physreg.
354  const TargetRegisterClass *
355  getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
356 
357  /// Return the maximal subclass of the given register class that is
358  /// allocatable or NULL.
359  const TargetRegisterClass *
360  getAllocatableClass(const TargetRegisterClass *RC) const;
361 
362  /// Returns a bitset indexed by register number indicating if a register is
363  /// allocatable or not. If a register class is specified, returns the subset
364  /// for the class.
365  BitVector getAllocatableSet(const MachineFunction &MF,
366  const TargetRegisterClass *RC = nullptr) const;
367 
368  /// Return the additional cost of using this register instead
369  /// of other registers in its class.
370  unsigned getCostPerUse(unsigned RegNo) const {
371  return InfoDesc[RegNo].CostPerUse;
372  }
373 
374  /// Return true if the register is in the allocation of any register class.
375  bool isInAllocatableClass(unsigned RegNo) const {
376  return InfoDesc[RegNo].inAllocatableClass;
377  }
378 
379  /// Return the human-readable symbolic target-specific
380  /// name for the specified SubRegIndex.
381  const char *getSubRegIndexName(unsigned SubIdx) const {
382  assert(SubIdx && SubIdx < getNumSubRegIndices() &&
383  "This is not a subregister index");
384  return SubRegIndexNames[SubIdx-1];
385  }
386 
387  /// Return a bitmask representing the parts of a register that are covered by
388  /// SubIdx \see LaneBitmask.
389  ///
390  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
391  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
392  assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
393  return SubRegIndexLaneMasks[SubIdx];
394  }
395 
396  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
397  /// used to determine if sub-registers overlap - they can't be used to
398  /// determine if a set of sub-registers completely cover another
399  /// sub-register.
400  ///
401  /// The X86 general purpose registers have two lanes corresponding to the
402  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
403  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
404  /// sub_32bit sub-register.
405  ///
406  /// On the other hand, the ARM NEON lanes fully cover their registers: The
407  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
408  /// This is related to the CoveredBySubRegs property on register definitions.
409  ///
410  /// This function returns a bit mask of lanes that completely cover their
411  /// sub-registers. More precisely, given:
412  ///
413  /// Covering = getCoveringLanes();
414  /// MaskA = getSubRegIndexLaneMask(SubA);
415  /// MaskB = getSubRegIndexLaneMask(SubB);
416  ///
417  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
418  /// SubB.
419  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
420 
421  /// Returns true if the two registers are equal or alias each other.
422  /// The registers may be virtual registers.
423  bool regsOverlap(unsigned regA, unsigned regB) const {
424  if (regA == regB) return true;
425  if (isVirtualRegister(regA) || isVirtualRegister(regB))
426  return false;
427 
428  // Regunits are numerically ordered. Find a common unit.
429  MCRegUnitIterator RUA(regA, this);
430  MCRegUnitIterator RUB(regB, this);
431  do {
432  if (*RUA == *RUB) return true;
433  if (*RUA < *RUB) ++RUA;
434  else ++RUB;
435  } while (RUA.isValid() && RUB.isValid());
436  return false;
437  }
438 
439  /// Returns true if Reg contains RegUnit.
440  bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
441  for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
442  if (*Units == RegUnit)
443  return true;
444  return false;
445  }
446 
447  /// Returns the original SrcReg unless it is the target of a copy-like
448  /// operation, in which case we chain backwards through all such operations
449  /// to the ultimate source register. If a physical register is encountered,
450  /// we stop the search.
451  virtual unsigned lookThruCopyLike(unsigned SrcReg,
452  const MachineRegisterInfo *MRI) const;
453 
454  /// Return a null-terminated list of all of the callee-saved registers on
455  /// this target. The register should be in the order of desired callee-save
456  /// stack frame offset. The first register is closest to the incoming stack
457  /// pointer if stack grows down, and vice versa.
458  /// Notice: This function does not take into account disabled CSRs.
459  /// In most cases you will want to use instead the function
460  /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
461  virtual const MCPhysReg*
462  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
463 
464  /// Return a mask of call-preserved registers for the given calling convention
465  /// on the current function. The mask should include all call-preserved
466  /// aliases. This is used by the register allocator to determine which
467  /// registers can be live across a call.
468  ///
469  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
470  /// A set bit indicates that all bits of the corresponding register are
471  /// preserved across the function call. The bit mask is expected to be
472  /// sub-register complete, i.e. if A is preserved, so are all its
473  /// sub-registers.
474  ///
475  /// Bits are numbered from the LSB, so the bit for physical register Reg can
476  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
477  ///
478  /// A NULL pointer means that no register mask will be used, and call
479  /// instructions should use implicit-def operands to indicate call clobbered
480  /// registers.
481  ///
483  CallingConv::ID) const {
484  // The default mask clobbers everything. All targets should override.
485  return nullptr;
486  }
487 
488  /// Return a register mask that clobbers everything.
489  virtual const uint32_t *getNoPreservedMask() const {
490  llvm_unreachable("target does not provide no preserved mask");
491  }
492 
493  /// Return true if all bits that are set in mask \p mask0 are also set in
494  /// \p mask1.
495  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
496 
497  /// Return all the call-preserved register masks defined for this target.
498  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
499  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
500 
501  /// Returns a bitset indexed by physical register number indicating if a
502  /// register is a special register that has particular uses and should be
503  /// considered unavailable at all times, e.g. stack pointer, return address.
504  /// A reserved register:
505  /// - is not allocatable
506  /// - is considered always live
507  /// - is ignored by liveness tracking
508  /// It is often necessary to reserve the super registers of a reserved
509  /// register as well, to avoid them getting allocated indirectly. You may use
510  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
511  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
512 
513  /// Returns true if PhysReg is unallocatable and constant throughout the
514  /// function. Used by MachineRegisterInfo::isConstantPhysReg().
515  virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
516 
517  /// Physical registers that may be modified within a function but are
518  /// guaranteed to be restored before any uses. This is useful for targets that
519  /// have call sequences where a GOT register may be updated by the caller
520  /// prior to a call and is guaranteed to be restored (also by the caller)
521  /// after the call.
522  virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
523  const MachineFunction &MF) const {
524  return false;
525  }
526 
527  /// Prior to adding the live-out mask to a stackmap or patchpoint
528  /// instruction, provide the target the opportunity to adjust it (mainly to
529  /// remove pseudo-registers that should be ignored).
530  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
531 
532  /// Return a super-register of the specified register
533  /// Reg so its sub-register of index SubIdx is Reg.
534  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
535  const TargetRegisterClass *RC) const {
536  return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
537  }
538 
539  /// Return a subclass of the specified register
540  /// class A so that each register in it has a sub-register of the
541  /// specified sub-register index which is in the specified register class B.
542  ///
543  /// TableGen will synthesize missing A sub-classes.
544  virtual const TargetRegisterClass *
545  getMatchingSuperRegClass(const TargetRegisterClass *A,
546  const TargetRegisterClass *B, unsigned Idx) const;
547 
548  // For a copy-like instruction that defines a register of class DefRC with
549  // subreg index DefSubReg, reading from another source with class SrcRC and
550  // subregister SrcSubReg return true if this is a preferable copy
551  // instruction or an earlier use should be used.
552  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
553  unsigned DefSubReg,
554  const TargetRegisterClass *SrcRC,
555  unsigned SrcSubReg) const;
556 
557  /// Returns the largest legal sub-class of RC that
558  /// supports the sub-register index Idx.
559  /// If no such sub-class exists, return NULL.
560  /// If all registers in RC already have an Idx sub-register, return RC.
561  ///
562  /// TableGen generates a version of this function that is good enough in most
563  /// cases. Targets can override if they have constraints that TableGen
564  /// doesn't understand. For example, the x86 sub_8bit sub-register index is
565  /// supported by the full GR32 register class in 64-bit mode, but only by the
566  /// GR32_ABCD regiister class in 32-bit mode.
567  ///
568  /// TableGen will synthesize missing RC sub-classes.
569  virtual const TargetRegisterClass *
570  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
571  assert(Idx == 0 && "Target has no sub-registers");
572  return RC;
573  }
574 
575  /// Return the subregister index you get from composing
576  /// two subregister indices.
577  ///
578  /// The special null sub-register index composes as the identity.
579  ///
580  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
581  /// returns c. Note that composeSubRegIndices does not tell you about illegal
582  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
583  /// b, composeSubRegIndices doesn't tell you.
584  ///
585  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
586  /// ssub_0:S0 - ssub_3:S3 subregs.
587  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
588  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
589  if (!a) return b;
590  if (!b) return a;
591  return composeSubRegIndicesImpl(a, b);
592  }
593 
594  /// Transforms a LaneMask computed for one subregister to the lanemask that
595  /// would have been computed when composing the subsubregisters with IdxA
596  /// first. @sa composeSubRegIndices()
598  LaneBitmask Mask) const {
599  if (!IdxA)
600  return Mask;
601  return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
602  }
603 
604  /// Transform a lanemask given for a virtual register to the corresponding
605  /// lanemask before using subregister with index \p IdxA.
606  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
607  /// valie lane mask (no invalid bits set) the following holds:
608  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
609  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
610  /// => X1 == Mask
612  LaneBitmask LaneMask) const {
613  if (!IdxA)
614  return LaneMask;
615  return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
616  }
617 
618  /// Debugging helper: dump register in human readable form to dbgs() stream.
619  static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
620  const TargetRegisterInfo* TRI = nullptr);
621 
622 protected:
623  /// Overridden by TableGen in targets that have sub-registers.
624  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
625  llvm_unreachable("Target has no sub-registers");
626  }
627 
628  /// Overridden by TableGen in targets that have sub-registers.
629  virtual LaneBitmask
631  llvm_unreachable("Target has no sub-registers");
632  }
633 
635  LaneBitmask) const {
636  llvm_unreachable("Target has no sub-registers");
637  }
638 
639 public:
640  /// Find a common super-register class if it exists.
641  ///
642  /// Find a register class, SuperRC and two sub-register indices, PreA and
643  /// PreB, such that:
644  ///
645  /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
646  ///
647  /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
648  ///
649  /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
650  ///
651  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
652  /// requirements, and there is no register class with a smaller spill size
653  /// that satisfies the requirements.
654  ///
655  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
656  ///
657  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
658  /// that case, the returned register class will be a sub-class of the
659  /// corresponding argument register class.
660  ///
661  /// The function returns NULL if no register class can be found.
662  const TargetRegisterClass*
663  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
664  const TargetRegisterClass *RCB, unsigned SubB,
665  unsigned &PreA, unsigned &PreB) const;
666 
667  //===--------------------------------------------------------------------===//
668  // Register Class Information
669  //
670 protected:
672  return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
673  }
674 
675 public:
676  /// Register class iterators
677  regclass_iterator regclass_begin() const { return RegClassBegin; }
678  regclass_iterator regclass_end() const { return RegClassEnd; }
680  return make_range(regclass_begin(), regclass_end());
681  }
682 
683  unsigned getNumRegClasses() const {
684  return (unsigned)(regclass_end()-regclass_begin());
685  }
686 
687  /// Returns the register class associated with the enumeration value.
688  /// See class MCOperandInfo.
689  const TargetRegisterClass *getRegClass(unsigned i) const {
690  assert(i < getNumRegClasses() && "Register Class ID out of range");
691  return RegClassBegin[i];
692  }
693 
694  /// Returns the name of the register class.
695  const char *getRegClassName(const TargetRegisterClass *Class) const {
696  return MCRegisterInfo::getRegClassName(Class->MC);
697  }
698 
699  /// Find the largest common subclass of A and B.
700  /// Return NULL if there is no common subclass.
701  /// The common subclass should contain
702  /// simple value type SVT if it is not the Any type.
703  const TargetRegisterClass *
704  getCommonSubClass(const TargetRegisterClass *A,
705  const TargetRegisterClass *B,
706  const MVT::SimpleValueType SVT =
708 
709  /// Returns a TargetRegisterClass used for pointer values.
710  /// If a target supports multiple different pointer register classes,
711  /// kind specifies which one is indicated.
712  virtual const TargetRegisterClass *
713  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
714  llvm_unreachable("Target didn't implement getPointerRegClass!");
715  }
716 
717  /// Returns a legal register class to copy a register in the specified class
718  /// to or from. If it is possible to copy the register directly without using
719  /// a cross register class copy, return the specified RC. Returns NULL if it
720  /// is not possible to copy between two registers of the specified class.
721  virtual const TargetRegisterClass *
723  return RC;
724  }
725 
726  /// Returns the largest super class of RC that is legal to use in the current
727  /// sub-target and has the same spill size.
728  /// The returned register class can be used to create virtual registers which
729  /// means that all its registers can be copied and spilled.
730  virtual const TargetRegisterClass *
732  const MachineFunction &) const {
733  /// The default implementation is very conservative and doesn't allow the
734  /// register allocator to inflate register classes.
735  return RC;
736  }
737 
738  /// Return the register pressure "high water mark" for the specific register
739  /// class. The scheduler is in high register pressure mode (for the specific
740  /// register class) if it goes over the limit.
741  ///
742  /// Note: this is the old register pressure model that relies on a manually
743  /// specified representative register class per value type.
744  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
745  MachineFunction &MF) const {
746  return 0;
747  }
748 
749  /// Return a heuristic for the machine scheduler to compare the profitability
750  /// of increasing one register pressure set versus another. The scheduler
751  /// will prefer increasing the register pressure of the set which returns
752  /// the largest value for this function.
753  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
754  unsigned PSetID) const {
755  return PSetID;
756  }
757 
758  /// Get the weight in units of pressure for this register class.
759  virtual const RegClassWeight &getRegClassWeight(
760  const TargetRegisterClass *RC) const = 0;
761 
762  /// Returns size in bits of a phys/virtual/generic register.
763  unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
764 
765  /// Get the weight in units of pressure for this register unit.
766  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
767 
768  /// Get the number of dimensions of register pressure.
769  virtual unsigned getNumRegPressureSets() const = 0;
770 
771  /// Get the name of this register unit pressure set.
772  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
773 
774  /// Get the register unit pressure limit for this dimension.
775  /// This limit must be adjusted dynamically for reserved registers.
776  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
777  unsigned Idx) const = 0;
778 
779  /// Get the dimensions of register pressure impacted by this register class.
780  /// Returns a -1 terminated array of pressure set IDs.
781  virtual const int *getRegClassPressureSets(
782  const TargetRegisterClass *RC) const = 0;
783 
784  /// Get the dimensions of register pressure impacted by this register unit.
785  /// Returns a -1 terminated array of pressure set IDs.
786  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
787 
788  /// Get a list of 'hint' registers that the register allocator should try
789  /// first when allocating a physical register for the virtual register
790  /// VirtReg. These registers are effectively moved to the front of the
791  /// allocation order. If true is returned, regalloc will try to only use
792  /// hints to the greatest extent possible even if it means spilling.
793  ///
794  /// The Order argument is the allocation order for VirtReg's register class
795  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
796  /// come from Order, and they must not be reserved.
797  ///
798  /// The default implementation of this function will only add target
799  /// independent register allocation hints. Targets that override this
800  /// function should typically call this default implementation as well and
801  /// expect to see generic copy hints added.
802  virtual bool getRegAllocationHints(unsigned VirtReg,
803  ArrayRef<MCPhysReg> Order,
805  const MachineFunction &MF,
806  const VirtRegMap *VRM = nullptr,
807  const LiveRegMatrix *Matrix = nullptr)
808  const;
809 
810  /// A callback to allow target a chance to update register allocation hints
811  /// when a register is "changed" (e.g. coalesced) to another register.
812  /// e.g. On ARM, some virtual registers should target register pairs,
813  /// if one of pair is coalesced to another register, the allocation hint of
814  /// the other half of the pair should be changed to point to the new register.
815  virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
816  MachineFunction &MF) const {
817  // Do nothing.
818  }
819 
820  /// The creation of multiple copy hints have been implemented in
821  /// weightCalcHelper(), but since this affects so many tests for many
822  /// targets, this is temporarily disabled per default. THIS SHOULD BE
823  /// "GENERAL GOODNESS" and hopefully all targets will update their tests
824  /// and enable this soon. This hook should then be removed.
825  virtual bool enableMultipleCopyHints() const { return false; }
826 
827  /// Allow the target to reverse allocation order of local live ranges. This
828  /// will generally allocate shorter local live ranges first. For targets with
829  /// many registers, this could reduce regalloc compile time by a large
830  /// factor. It is disabled by default for three reasons:
831  /// (1) Top-down allocation is simpler and easier to debug for targets that
832  /// don't benefit from reversing the order.
833  /// (2) Bottom-up allocation could result in poor evicition decisions on some
834  /// targets affecting the performance of compiled code.
835  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
836  virtual bool reverseLocalAssignment() const { return false; }
837 
838  /// Allow the target to override the cost of using a callee-saved register for
839  /// the first time. Default value of 0 means we will use a callee-saved
840  /// register if it is available.
841  virtual unsigned getCSRFirstUseCost() const { return 0; }
842 
843  /// Returns true if the target requires (and can make use of) the register
844  /// scavenger.
845  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
846  return false;
847  }
848 
849  /// Returns true if the target wants to use frame pointer based accesses to
850  /// spill to the scavenger emergency spill slot.
851  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
852  return true;
853  }
854 
855  /// Returns true if the target requires post PEI scavenging of registers for
856  /// materializing frame index constants.
857  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
858  return false;
859  }
860 
861  /// Returns true if the target requires using the RegScavenger directly for
862  /// frame elimination despite using requiresFrameIndexScavenging.
864  const MachineFunction &MF) const {
865  return false;
866  }
867 
868  /// Returns true if the target wants the LocalStackAllocation pass to be run
869  /// and virtual base registers used for more efficient stack access.
870  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
871  return false;
872  }
873 
874  /// Return true if target has reserved a spill slot in the stack frame of
875  /// the given function for the specified register. e.g. On x86, if the frame
876  /// register is required, the first fixed stack object is reserved as its
877  /// spill slot. This tells PEI not to create a new stack frame
878  /// object for the given register. It should be called only after
879  /// determineCalleeSaves().
880  virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
881  int &FrameIdx) const {
882  return false;
883  }
884 
885  /// Returns true if the live-ins should be tracked after register allocation.
886  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
887  return false;
888  }
889 
890  /// True if the stack can be realigned for the target.
891  virtual bool canRealignStack(const MachineFunction &MF) const;
892 
893  /// True if storage within the function requires the stack pointer to be
894  /// aligned more than the normal calling convention calls for.
895  /// This cannot be overriden by the target, but canRealignStack can be
896  /// overridden.
897  bool needsStackRealignment(const MachineFunction &MF) const;
898 
899  /// Get the offset from the referenced frame index in the instruction,
900  /// if there is one.
901  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
902  int Idx) const {
903  return 0;
904  }
905 
906  /// Returns true if the instruction's frame index reference would be better
907  /// served by a base register other than FP or SP.
908  /// Used by LocalStackFrameAllocation to determine which frame index
909  /// references it should create new base registers for.
910  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
911  return false;
912  }
913 
914  /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
915  /// before insertion point I.
917  unsigned BaseReg, int FrameIdx,
918  int64_t Offset) const {
919  llvm_unreachable("materializeFrameBaseRegister does not exist on this "
920  "target");
921  }
922 
923  /// Resolve a frame index operand of an instruction
924  /// to reference the indicated base register plus offset instead.
925  virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
926  int64_t Offset) const {
927  llvm_unreachable("resolveFrameIndex does not exist on this target");
928  }
929 
930  /// Determine whether a given base register plus offset immediate is
931  /// encodable to resolve a frame index.
932  virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
933  int64_t Offset) const {
934  llvm_unreachable("isFrameOffsetLegal does not exist on this target");
935  }
936 
937  /// Spill the register so it can be used by the register scavenger.
938  /// Return true if the register was spilled, false otherwise.
939  /// If this function does not spill the register, the scavenger
940  /// will instead spill it to the emergency spill slot.
944  const TargetRegisterClass *RC,
945  unsigned Reg) const {
946  return false;
947  }
948 
949  /// This method must be overriden to eliminate abstract frame indices from
950  /// instructions which may use them. The instruction referenced by the
951  /// iterator contains an MO_FrameIndex operand which must be eliminated by
952  /// this method. This method may modify or replace the specified instruction,
953  /// as long as it keeps the iterator pointing at the finished product.
954  /// SPAdj is the SP adjustment due to call frame setup instruction.
955  /// FIOperandNum is the FI operand number.
956  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
957  int SPAdj, unsigned FIOperandNum,
958  RegScavenger *RS = nullptr) const = 0;
959 
960  /// Return the assembly name for \p Reg.
961  virtual StringRef getRegAsmName(unsigned Reg) const {
962  // FIXME: We are assuming that the assembly name is equal to the TableGen
963  // name converted to lower case
964  //
965  // The TableGen name is the name of the definition for this register in the
966  // target's tablegen files. For example, the TableGen name of
967  // def EAX : Register <...>; is "EAX"
968  return StringRef(getName(Reg));
969  }
970 
971  //===--------------------------------------------------------------------===//
972  /// Subtarget Hooks
973 
974  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
975  virtual bool shouldCoalesce(MachineInstr *MI,
976  const TargetRegisterClass *SrcRC,
977  unsigned SubReg,
978  const TargetRegisterClass *DstRC,
979  unsigned DstSubReg,
980  const TargetRegisterClass *NewRC,
981  LiveIntervals &LIS) const
982  { return true; }
983 
984  //===--------------------------------------------------------------------===//
985  /// Debug information queries.
986 
987  /// getFrameRegister - This method should return the register used as a base
988  /// for values allocated in the current stack frame.
989  virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
990 
991  /// Mark a register and all its aliases as reserved in the given set.
992  void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
993 
994  /// Returns true if for every register in the set all super registers are part
995  /// of the set as well.
996  bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
997  ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
998 
999  virtual const TargetRegisterClass *
1001  const MachineRegisterInfo &MRI) const {
1002  return nullptr;
1003  }
1004 };
1005 
1006 //===----------------------------------------------------------------------===//
1007 // SuperRegClassIterator
1008 //===----------------------------------------------------------------------===//
1009 //
1010 // Iterate over the possible super-registers for a given register class. The
1011 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
1012 // possible classes of super-registers.
1013 //
1014 // Each bit mask will have at least one set bit, and each set bit in Mask
1015 // corresponds to a SuperRC such that:
1016 //
1017 // For all Reg in SuperRC: Reg:Idx is in RC.
1018 //
1019 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
1020 // also satisfies the above requirement, assuming Reg:0 == Reg.
1021 //
1023  const unsigned RCMaskWords;
1024  unsigned SubReg = 0;
1025  const uint16_t *Idx;
1026  const uint32_t *Mask;
1027 
1028 public:
1029  /// Create a SuperRegClassIterator that visits all the super-register classes
1030  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1032  const TargetRegisterInfo *TRI,
1033  bool IncludeSelf = false)
1034  : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1035  Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1036  if (!IncludeSelf)
1037  ++*this;
1038  }
1039 
1040  /// Returns true if this iterator is still pointing at a valid entry.
1041  bool isValid() const { return Idx; }
1042 
1043  /// Returns the current sub-register index.
1044  unsigned getSubReg() const { return SubReg; }
1045 
1046  /// Returns the bit mask of register classes that getSubReg() projects into
1047  /// RC.
1048  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1049  const uint32_t *getMask() const { return Mask; }
1050 
1051  /// Advance iterator to the next entry.
1052  void operator++() {
1053  assert(isValid() && "Cannot move iterator past end.");
1054  Mask += RCMaskWords;
1055  SubReg = *Idx++;
1056  if (!SubReg)
1057  Idx = nullptr;
1058  }
1059 };
1060 
1061 //===----------------------------------------------------------------------===//
1062 // BitMaskClassIterator
1063 //===----------------------------------------------------------------------===//
1064 /// This class encapuslates the logic to iterate over bitmask returned by
1065 /// the various RegClass related APIs.
1066 /// E.g., this class can be used to iterate over the subclasses provided by
1067 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1069  /// Total number of register classes.
1070  const unsigned NumRegClasses;
1071  /// Base index of CurrentChunk.
1072  /// In other words, the number of bit we read to get at the
1073  /// beginning of that chunck.
1074  unsigned Base = 0;
1075  /// Adjust base index of CurrentChunk.
1076  /// Base index + how many bit we read within CurrentChunk.
1077  unsigned Idx = 0;
1078  /// Current register class ID.
1079  unsigned ID = 0;
1080  /// Mask we are iterating over.
1081  const uint32_t *Mask;
1082  /// Current chunk of the Mask we are traversing.
1083  uint32_t CurrentChunk;
1084 
1085  /// Move ID to the next set bit.
1086  void moveToNextID() {
1087  // If the current chunk of memory is empty, move to the next one,
1088  // while making sure we do not go pass the number of register
1089  // classes.
1090  while (!CurrentChunk) {
1091  // Move to the next chunk.
1092  Base += 32;
1093  if (Base >= NumRegClasses) {
1094  ID = NumRegClasses;
1095  return;
1096  }
1097  CurrentChunk = *++Mask;
1098  Idx = Base;
1099  }
1100  // Otherwise look for the first bit set from the right
1101  // (representation of the class ID is big endian).
1102  // See getSubClassMask for more details on the representation.
1103  unsigned Offset = countTrailingZeros(CurrentChunk);
1104  // Add the Offset to the adjusted base number of this chunk: Idx.
1105  // This is the ID of the register class.
1106  ID = Idx + Offset;
1107 
1108  // Consume the zeros, if any, and the bit we just read
1109  // so that we are at the right spot for the next call.
1110  // Do not do Offset + 1 because Offset may be 31 and 32
1111  // will be UB for the shift, though in that case we could
1112  // have make the chunk being equal to 0, but that would
1113  // have introduced a if statement.
1114  moveNBits(Offset);
1115  moveNBits(1);
1116  }
1117 
1118  /// Move \p NumBits Bits forward in CurrentChunk.
1119  void moveNBits(unsigned NumBits) {
1120  assert(NumBits < 32 && "Undefined behavior spotted!");
1121  // Consume the bit we read for the next call.
1122  CurrentChunk >>= NumBits;
1123  // Adjust the base for the chunk.
1124  Idx += NumBits;
1125  }
1126 
1127 public:
1128  /// Create a BitMaskClassIterator that visits all the register classes
1129  /// represented by \p Mask.
1130  ///
1131  /// \pre \p Mask != nullptr
1133  : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1134  // Move to the first ID.
1135  moveToNextID();
1136  }
1137 
1138  /// Returns true if this iterator is still pointing at a valid entry.
1139  bool isValid() const { return getID() != NumRegClasses; }
1140 
1141  /// Returns the current register class ID.
1142  unsigned getID() const { return ID; }
1143 
1144  /// Advance iterator to the next entry.
1145  void operator++() {
1146  assert(isValid() && "Cannot move iterator past end.");
1147  moveToNextID();
1148  }
1149 };
1150 
1151 // This is useful when building IndexedMaps keyed on virtual registers
1154  unsigned operator()(unsigned Reg) const {
1156  }
1157 };
1158 
1159 /// Prints virtual and physical registers with or without a TRI instance.
1160 ///
1161 /// The format is:
1162 /// %noreg - NoRegister
1163 /// %5 - a virtual register.
1164 /// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1165 /// %eax - a physical register
1166 /// %physreg17 - a physical register when no TRI instance given.
1167 ///
1168 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1169 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1170  unsigned SubIdx = 0,
1171  const MachineRegisterInfo *MRI = nullptr);
1172 
1173 /// Create Printable object to print register units on a \ref raw_ostream.
1174 ///
1175 /// Register units are named after their root registers:
1176 ///
1177 /// al - Single root.
1178 /// fp0~st7 - Dual roots.
1179 ///
1180 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1181 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1182 
1183 /// Create Printable object to print virtual registers and physical
1184 /// registers on a \ref raw_ostream.
1185 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1186 
1187 /// Create Printable object to print register classes or register banks
1188 /// on a \ref raw_ostream.
1189 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
1190  const TargetRegisterInfo *TRI);
1191 
1192 } // end namespace llvm
1193 
1194 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
A common definition of LaneBitmask for use in TableGen and CodeGen.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger. ...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
SI Whole Quad Mode
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
iterator begin() const
begin/end - Return all of the registers in this class.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumRegs() const
Return the number of registers in this class.
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
iterator begin() const
begin/end - Return all of the registers in this class.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
unsigned getRegister(unsigned i) const
Return the specified register in the class.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getCostPerUse(unsigned RegNo) const
Return the additional cost of using this register instead of other registers in its class...
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
unsigned const TargetRegisterInfo * TRI
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
unsigned getSubReg() const
Returns the current sub-register index.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Live Register Matrix
unsigned getID() const
getID() - Return the register class ID number.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index...
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
virtual bool enableMultipleCopyHints() const
The creation of multiple copy hints have been implemented in weightCalcHelper(), but since this affec...
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const uint16_t * SuperRegIndices
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
unsigned SubReg
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:413
static StringRef getName(Value *V)
iterator_range< regclass_iterator > regclasses() const
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getNumRegClasses() const
regclass_iterator regclass_begin() const
Register class iterators.
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
Returns true if Reg contains RegUnit.
void operator++()
Advance iterator to the next entry.
bool contains(unsigned Reg1, unsigned Reg2) const
Return true if both registers are in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
MCRegisterClass - Base class of TargetRegisterClass.
virtual StringRef getRegAsmName(unsigned Reg) const
Return the assembly name for Reg.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:120
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Machine Value Type.
const sc_iterator SuperClasses
const TargetRegisterClass *const * regclass_iterator
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
MachineInstrBuilder & UseMI
regclass_iterator regclass_end() const
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time...
iterator end() const
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Extra information, not in MCRegisterDesc, about registers.
virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
const char * getRegClassName(const MCRegisterClass *Class) const
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
MachineOperand class - Representation of each machine instruction operand.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
A range adaptor for a pair of iterators.
const MCRegisterClass * MC
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned operator()(unsigned Reg) const
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
#define I(x, y, z)
Definition: MD5.cpp:58
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getID() const
Returns the current register class ID.
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
const MCPhysReg * const_iterator
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
void operator++()
Advance iterator to the next entry.
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I...
static unsigned index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
Spill the register so it can be used by the register scavenger.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...