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TargetRegisterInfo.h
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1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
17 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/MC/LaneBitmask.h"
27 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Printable.h"
31 #include <cassert>
32 #include <cstdint>
33 #include <functional>
34 
35 namespace llvm {
36 
37 class BitVector;
38 class LiveRegMatrix;
39 class MachineFunction;
40 class MachineInstr;
41 class RegScavenger;
42 class VirtRegMap;
43 class LiveIntervals;
44 
46 public:
47  using iterator = const MCPhysReg *;
48  using const_iterator = const MCPhysReg *;
49  using sc_iterator = const TargetRegisterClass* const *;
50 
51  // Instance variables filled by tablegen, do not use!
54  const uint16_t *SuperRegIndices;
56  /// Classes with a higher priority value are assigned first by register
57  /// allocators using a greedy heuristic. The value is in the range [0,63].
58  const uint8_t AllocationPriority;
59  /// Whether the class supports two (or more) disjunct subregister indices.
60  const bool HasDisjunctSubRegs;
61  /// Whether a combination of subregisters can cover every register in the
62  /// class. See also the CoveredBySubRegs description in Target.td.
63  const bool CoveredBySubRegs;
65  ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
66 
67  /// Return the register class ID number.
68  unsigned getID() const { return MC->getID(); }
69 
70  /// begin/end - Return all of the registers in this class.
71  ///
72  iterator begin() const { return MC->begin(); }
73  iterator end() const { return MC->end(); }
74 
75  /// Return the number of registers in this class.
76  unsigned getNumRegs() const { return MC->getNumRegs(); }
77 
79  getRegisters() const {
80  return make_range(MC->begin(), MC->end());
81  }
82 
83  /// Return the specified register in the class.
84  unsigned getRegister(unsigned i) const {
85  return MC->getRegister(i);
86  }
87 
88  /// Return true if the specified register is included in this register class.
89  /// This does not include virtual registers.
90  bool contains(unsigned Reg) const {
91  return MC->contains(Reg);
92  }
93 
94  /// Return true if both registers are in this class.
95  bool contains(unsigned Reg1, unsigned Reg2) const {
96  return MC->contains(Reg1, Reg2);
97  }
98 
99  /// Return the cost of copying a value between two registers in this class.
100  /// A negative number means the register class is very expensive
101  /// to copy e.g. status flag register classes.
102  int getCopyCost() const { return MC->getCopyCost(); }
103 
104  /// Return true if this register class may be used to create virtual
105  /// registers.
106  bool isAllocatable() const { return MC->isAllocatable(); }
107 
108  /// Return true if the specified TargetRegisterClass
109  /// is a proper sub-class of this TargetRegisterClass.
110  bool hasSubClass(const TargetRegisterClass *RC) const {
111  return RC != this && hasSubClassEq(RC);
112  }
113 
114  /// Returns true if RC is a sub-class of or equal to this class.
115  bool hasSubClassEq(const TargetRegisterClass *RC) const {
116  unsigned ID = RC->getID();
117  return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
118  }
119 
120  /// Return true if the specified TargetRegisterClass is a
121  /// proper super-class of this TargetRegisterClass.
122  bool hasSuperClass(const TargetRegisterClass *RC) const {
123  return RC->hasSubClass(this);
124  }
125 
126  /// Returns true if RC is a super-class of or equal to this class.
127  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
128  return RC->hasSubClassEq(this);
129  }
130 
131  /// Returns a bit vector of subclasses, including this one.
132  /// The vector is indexed by class IDs.
133  ///
134  /// To use it, consider the returned array as a chunk of memory that
135  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
136  /// contains a bitset of the ID of the subclasses in big-endian style.
137 
138  /// I.e., the representation of the memory from left to right at the
139  /// bit level looks like:
140  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
141  /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
142  /// Where the number represents the class ID and XXX bits that
143  /// should be ignored.
144  ///
145  /// See the implementation of hasSubClassEq for an example of how it
146  /// can be used.
147  const uint32_t *getSubClassMask() const {
148  return SubClassMask;
149  }
150 
151  /// Returns a 0-terminated list of sub-register indices that project some
152  /// super-register class into this register class. The list has an entry for
153  /// each Idx such that:
154  ///
155  /// There exists SuperRC where:
156  /// For all Reg in SuperRC:
157  /// this->contains(Reg:Idx)
158  const uint16_t *getSuperRegIndices() const {
159  return SuperRegIndices;
160  }
161 
162  /// Returns a NULL-terminated list of super-classes. The
163  /// classes are ordered by ID which is also a topological ordering from large
164  /// to small classes. The list does NOT include the current class.
166  return SuperClasses;
167  }
168 
169  /// Return true if this TargetRegisterClass is a subset
170  /// class of at least one other TargetRegisterClass.
171  bool isASubClass() const {
172  return SuperClasses[0] != nullptr;
173  }
174 
175  /// Returns the preferred order for allocating registers from this register
176  /// class in MF. The raw order comes directly from the .td file and may
177  /// include reserved registers that are not allocatable.
178  /// Register allocators should also make sure to allocate
179  /// callee-saved registers only after all the volatiles are used. The
180  /// RegisterClassInfo class provides filtered allocation orders with
181  /// callee-saved registers moved to the end.
182  ///
183  /// The MachineFunction argument can be used to tune the allocatable
184  /// registers based on the characteristics of the function, subtarget, or
185  /// other criteria.
186  ///
187  /// By default, this method returns all registers in the class.
189  return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
190  }
191 
192  /// Returns the combination of all lane masks of register in this class.
193  /// The lane masks of the registers are the combination of all lane masks
194  /// of their subregisters. Returns 1 if there are no subregisters.
196  return LaneMask;
197  }
198 };
199 
200 /// Extra information, not in MCRegisterDesc, about registers.
201 /// These are used by codegen, not by MC.
203  unsigned CostPerUse; // Extra cost of instructions using register.
204  bool inAllocatableClass; // Register belongs to an allocatable regclass.
205 };
206 
207 /// Each TargetRegisterClass has a per register weight, and weight
208 /// limit which must be less than the limits of its pressure sets.
210  unsigned RegWeight;
211  unsigned WeightLimit;
212 };
213 
214 /// TargetRegisterInfo base class - We assume that the target defines a static
215 /// array of TargetRegisterDesc objects that represent all of the machine
216 /// registers that the target has. As such, we simply have to track a pointer
217 /// to this array so that we can turn register number into a register
218 /// descriptor.
219 ///
221 public:
222  using regclass_iterator = const TargetRegisterClass * const *;
224  struct RegClassInfo {
225  unsigned RegSize, SpillSize, SpillAlignment;
227  };
228 private:
229  const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
230  const char *const *SubRegIndexNames; // Names of subreg indexes.
231  // Pointer to array of lane masks, one per sub-reg index.
232  const LaneBitmask *SubRegIndexLaneMasks;
233 
234  regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
235  LaneBitmask CoveringLanes;
236  const RegClassInfo *const RCInfos;
237  unsigned HwMode;
238 
239 protected:
241  regclass_iterator RegClassBegin,
242  regclass_iterator RegClassEnd,
243  const char *const *SRINames,
244  const LaneBitmask *SRILaneMasks,
245  LaneBitmask CoveringLanes,
246  const RegClassInfo *const RSI,
247  unsigned Mode = 0);
248  virtual ~TargetRegisterInfo();
249 
250 public:
251  // Register numbers can represent physical registers, virtual registers, and
252  // sometimes stack slots. The unsigned values are divided into these ranges:
253  //
254  // 0 Not a register, can be used as a sentinel.
255  // [1;2^30) Physical registers assigned by TableGen.
256  // [2^30;2^31) Stack slots. (Rarely used.)
257  // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
258  //
259  // Further sentinels can be allocated from the small negative integers.
260  // DenseMapInfo<unsigned> uses -1u and -2u.
261 
262  /// isStackSlot - Sometimes it is useful the be able to store a non-negative
263  /// frame index in a variable that normally holds a register. isStackSlot()
264  /// returns true if Reg is in the range used for stack slots.
265  ///
266  /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
267  /// slots, so if a variable may contains a stack slot, always check
268  /// isStackSlot() first.
269  ///
270  static bool isStackSlot(unsigned Reg) {
271  return int(Reg) >= (1 << 30);
272  }
273 
274  /// Compute the frame index from a register value representing a stack slot.
275  static int stackSlot2Index(unsigned Reg) {
276  assert(isStackSlot(Reg) && "Not a stack slot");
277  return int(Reg - (1u << 30));
278  }
279 
280  /// Convert a non-negative frame index to a stack slot register value.
281  static unsigned index2StackSlot(int FI) {
282  assert(FI >= 0 && "Cannot hold a negative frame index.");
283  return FI + (1u << 30);
284  }
285 
286  /// Return true if the specified register number is in
287  /// the physical register namespace.
288  static bool isPhysicalRegister(unsigned Reg) {
289  assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
290  return int(Reg) > 0;
291  }
292 
293  /// Return true if the specified register number is in
294  /// the virtual register namespace.
295  static bool isVirtualRegister(unsigned Reg) {
296  assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
297  return int(Reg) < 0;
298  }
299 
300  /// Convert a virtual register number to a 0-based index.
301  /// The first virtual register in a function will get the index 0.
302  static unsigned virtReg2Index(unsigned Reg) {
303  assert(isVirtualRegister(Reg) && "Not a virtual register");
304  return Reg & ~(1u << 31);
305  }
306 
307  /// Convert a 0-based index to a virtual register number.
308  /// This is the inverse operation of VirtReg2IndexFunctor below.
309  static unsigned index2VirtReg(unsigned Index) {
310  return Index | (1u << 31);
311  }
312 
313  /// Return the size in bits of a register from class RC.
314  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
315  return getRegClassInfo(RC).RegSize;
316  }
317 
318  /// Return the size in bytes of the stack slot allocated to hold a spilled
319  /// copy of a register from class RC.
320  unsigned getSpillSize(const TargetRegisterClass &RC) const {
321  return getRegClassInfo(RC).SpillSize / 8;
322  }
323 
324  /// Return the minimum required alignment in bytes for a spill slot for
325  /// a register of this class.
326  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
327  return getRegClassInfo(RC).SpillAlignment / 8;
328  }
329 
330  /// Return true if the given TargetRegisterClass has the ValueType T.
331  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
332  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
333  if (MVT(*I) == T)
334  return true;
335  return false;
336  }
337 
338  /// Loop over all of the value types that can be represented by values
339  /// in the given register class.
341  return getRegClassInfo(RC).VTList;
342  }
343 
345  vt_iterator I = legalclasstypes_begin(RC);
346  while (*I != MVT::Other)
347  ++I;
348  return I;
349  }
350 
351  /// Returns the Register Class of a physical register of the given type,
352  /// picking the most sub register class of the right type that contains this
353  /// physreg.
354  const TargetRegisterClass *
355  getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
356 
357  /// Return the maximal subclass of the given register class that is
358  /// allocatable or NULL.
359  const TargetRegisterClass *
360  getAllocatableClass(const TargetRegisterClass *RC) const;
361 
362  /// Returns a bitset indexed by register number indicating if a register is
363  /// allocatable or not. If a register class is specified, returns the subset
364  /// for the class.
365  BitVector getAllocatableSet(const MachineFunction &MF,
366  const TargetRegisterClass *RC = nullptr) const;
367 
368  /// Return the additional cost of using this register instead
369  /// of other registers in its class.
370  unsigned getCostPerUse(unsigned RegNo) const {
371  return InfoDesc[RegNo].CostPerUse;
372  }
373 
374  /// Return true if the register is in the allocation of any register class.
375  bool isInAllocatableClass(unsigned RegNo) const {
376  return InfoDesc[RegNo].inAllocatableClass;
377  }
378 
379  /// Return the human-readable symbolic target-specific
380  /// name for the specified SubRegIndex.
381  const char *getSubRegIndexName(unsigned SubIdx) const {
382  assert(SubIdx && SubIdx < getNumSubRegIndices() &&
383  "This is not a subregister index");
384  return SubRegIndexNames[SubIdx-1];
385  }
386 
387  /// Return a bitmask representing the parts of a register that are covered by
388  /// SubIdx \see LaneBitmask.
389  ///
390  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
391  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
392  assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
393  return SubRegIndexLaneMasks[SubIdx];
394  }
395 
396  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
397  /// used to determine if sub-registers overlap - they can't be used to
398  /// determine if a set of sub-registers completely cover another
399  /// sub-register.
400  ///
401  /// The X86 general purpose registers have two lanes corresponding to the
402  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
403  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
404  /// sub_32bit sub-register.
405  ///
406  /// On the other hand, the ARM NEON lanes fully cover their registers: The
407  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
408  /// This is related to the CoveredBySubRegs property on register definitions.
409  ///
410  /// This function returns a bit mask of lanes that completely cover their
411  /// sub-registers. More precisely, given:
412  ///
413  /// Covering = getCoveringLanes();
414  /// MaskA = getSubRegIndexLaneMask(SubA);
415  /// MaskB = getSubRegIndexLaneMask(SubB);
416  ///
417  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
418  /// SubB.
419  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
420 
421  /// Returns true if the two registers are equal or alias each other.
422  /// The registers may be virtual registers.
423  bool regsOverlap(unsigned regA, unsigned regB) const {
424  if (regA == regB) return true;
425  if (isVirtualRegister(regA) || isVirtualRegister(regB))
426  return false;
427 
428  // Regunits are numerically ordered. Find a common unit.
429  MCRegUnitIterator RUA(regA, this);
430  MCRegUnitIterator RUB(regB, this);
431  do {
432  if (*RUA == *RUB) return true;
433  if (*RUA < *RUB) ++RUA;
434  else ++RUB;
435  } while (RUA.isValid() && RUB.isValid());
436  return false;
437  }
438 
439  /// Returns true if Reg contains RegUnit.
440  bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
441  for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
442  if (*Units == RegUnit)
443  return true;
444  return false;
445  }
446 
447  /// Return a null-terminated list of all of the callee-saved registers on
448  /// this target. The register should be in the order of desired callee-save
449  /// stack frame offset. The first register is closest to the incoming stack
450  /// pointer if stack grows down, and vice versa.
451  /// Notice: This function does not take into account disabled CSRs.
452  /// In most cases you will want to use instead the function
453  /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
454  virtual const MCPhysReg*
455  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
456 
457  /// Return a mask of call-preserved registers for the given calling convention
458  /// on the current function. The mask should include all call-preserved
459  /// aliases. This is used by the register allocator to determine which
460  /// registers can be live across a call.
461  ///
462  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
463  /// A set bit indicates that all bits of the corresponding register are
464  /// preserved across the function call. The bit mask is expected to be
465  /// sub-register complete, i.e. if A is preserved, so are all its
466  /// sub-registers.
467  ///
468  /// Bits are numbered from the LSB, so the bit for physical register Reg can
469  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
470  ///
471  /// A NULL pointer means that no register mask will be used, and call
472  /// instructions should use implicit-def operands to indicate call clobbered
473  /// registers.
474  ///
476  CallingConv::ID) const {
477  // The default mask clobbers everything. All targets should override.
478  return nullptr;
479  }
480 
481  /// Return a register mask that clobbers everything.
482  virtual const uint32_t *getNoPreservedMask() const {
483  llvm_unreachable("target does not provide no preserved mask");
484  }
485 
486  /// Return true if all bits that are set in mask \p mask0 are also set in
487  /// \p mask1.
488  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
489 
490  /// Return all the call-preserved register masks defined for this target.
491  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
492  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
493 
494  /// Returns a bitset indexed by physical register number indicating if a
495  /// register is a special register that has particular uses and should be
496  /// considered unavailable at all times, e.g. stack pointer, return address.
497  /// A reserved register:
498  /// - is not allocatable
499  /// - is considered always live
500  /// - is ignored by liveness tracking
501  /// It is often necessary to reserve the super registers of a reserved
502  /// register as well, to avoid them getting allocated indirectly. You may use
503  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
504  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
505 
506  /// Returns true if PhysReg is unallocatable and constant throughout the
507  /// function. Used by MachineRegisterInfo::isConstantPhysReg().
508  virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
509 
510  /// Physical registers that may be modified within a function but are
511  /// guaranteed to be restored before any uses. This is useful for targets that
512  /// have call sequences where a GOT register may be updated by the caller
513  /// prior to a call and is guaranteed to be restored (also by the caller)
514  /// after the call.
515  virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
516  const MachineFunction &MF) const {
517  return false;
518  }
519 
520  /// Prior to adding the live-out mask to a stackmap or patchpoint
521  /// instruction, provide the target the opportunity to adjust it (mainly to
522  /// remove pseudo-registers that should be ignored).
523  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
524 
525  /// Return a super-register of the specified register
526  /// Reg so its sub-register of index SubIdx is Reg.
527  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
528  const TargetRegisterClass *RC) const {
529  return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
530  }
531 
532  /// Return a subclass of the specified register
533  /// class A so that each register in it has a sub-register of the
534  /// specified sub-register index which is in the specified register class B.
535  ///
536  /// TableGen will synthesize missing A sub-classes.
537  virtual const TargetRegisterClass *
538  getMatchingSuperRegClass(const TargetRegisterClass *A,
539  const TargetRegisterClass *B, unsigned Idx) const;
540 
541  // For a copy-like instruction that defines a register of class DefRC with
542  // subreg index DefSubReg, reading from another source with class SrcRC and
543  // subregister SrcSubReg return true if this is a preferable copy
544  // instruction or an earlier use should be used.
545  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
546  unsigned DefSubReg,
547  const TargetRegisterClass *SrcRC,
548  unsigned SrcSubReg) const;
549 
550  /// Returns the largest legal sub-class of RC that
551  /// supports the sub-register index Idx.
552  /// If no such sub-class exists, return NULL.
553  /// If all registers in RC already have an Idx sub-register, return RC.
554  ///
555  /// TableGen generates a version of this function that is good enough in most
556  /// cases. Targets can override if they have constraints that TableGen
557  /// doesn't understand. For example, the x86 sub_8bit sub-register index is
558  /// supported by the full GR32 register class in 64-bit mode, but only by the
559  /// GR32_ABCD regiister class in 32-bit mode.
560  ///
561  /// TableGen will synthesize missing RC sub-classes.
562  virtual const TargetRegisterClass *
563  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
564  assert(Idx == 0 && "Target has no sub-registers");
565  return RC;
566  }
567 
568  /// Return the subregister index you get from composing
569  /// two subregister indices.
570  ///
571  /// The special null sub-register index composes as the identity.
572  ///
573  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
574  /// returns c. Note that composeSubRegIndices does not tell you about illegal
575  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
576  /// b, composeSubRegIndices doesn't tell you.
577  ///
578  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
579  /// ssub_0:S0 - ssub_3:S3 subregs.
580  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
581  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
582  if (!a) return b;
583  if (!b) return a;
584  return composeSubRegIndicesImpl(a, b);
585  }
586 
587  /// Transforms a LaneMask computed for one subregister to the lanemask that
588  /// would have been computed when composing the subsubregisters with IdxA
589  /// first. @sa composeSubRegIndices()
591  LaneBitmask Mask) const {
592  if (!IdxA)
593  return Mask;
594  return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
595  }
596 
597  /// Transform a lanemask given for a virtual register to the corresponding
598  /// lanemask before using subregister with index \p IdxA.
599  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
600  /// valie lane mask (no invalid bits set) the following holds:
601  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
602  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
603  /// => X1 == Mask
605  LaneBitmask LaneMask) const {
606  if (!IdxA)
607  return LaneMask;
608  return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
609  }
610 
611  /// Debugging helper: dump register in human readable form to dbgs() stream.
612  static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
613  const TargetRegisterInfo* TRI = nullptr);
614 
615 protected:
616  /// Overridden by TableGen in targets that have sub-registers.
617  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
618  llvm_unreachable("Target has no sub-registers");
619  }
620 
621  /// Overridden by TableGen in targets that have sub-registers.
622  virtual LaneBitmask
624  llvm_unreachable("Target has no sub-registers");
625  }
626 
628  LaneBitmask) const {
629  llvm_unreachable("Target has no sub-registers");
630  }
631 
632 public:
633  /// Find a common super-register class if it exists.
634  ///
635  /// Find a register class, SuperRC and two sub-register indices, PreA and
636  /// PreB, such that:
637  ///
638  /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
639  ///
640  /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
641  ///
642  /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
643  ///
644  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
645  /// requirements, and there is no register class with a smaller spill size
646  /// that satisfies the requirements.
647  ///
648  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
649  ///
650  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
651  /// that case, the returned register class will be a sub-class of the
652  /// corresponding argument register class.
653  ///
654  /// The function returns NULL if no register class can be found.
655  const TargetRegisterClass*
656  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
657  const TargetRegisterClass *RCB, unsigned SubB,
658  unsigned &PreA, unsigned &PreB) const;
659 
660  //===--------------------------------------------------------------------===//
661  // Register Class Information
662  //
663 protected:
665  return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
666  }
667 
668 public:
669  /// Register class iterators
670  regclass_iterator regclass_begin() const { return RegClassBegin; }
671  regclass_iterator regclass_end() const { return RegClassEnd; }
673  return make_range(regclass_begin(), regclass_end());
674  }
675 
676  unsigned getNumRegClasses() const {
677  return (unsigned)(regclass_end()-regclass_begin());
678  }
679 
680  /// Returns the register class associated with the enumeration value.
681  /// See class MCOperandInfo.
682  const TargetRegisterClass *getRegClass(unsigned i) const {
683  assert(i < getNumRegClasses() && "Register Class ID out of range");
684  return RegClassBegin[i];
685  }
686 
687  /// Returns the name of the register class.
688  const char *getRegClassName(const TargetRegisterClass *Class) const {
689  return MCRegisterInfo::getRegClassName(Class->MC);
690  }
691 
692  /// Find the largest common subclass of A and B.
693  /// Return NULL if there is no common subclass.
694  /// The common subclass should contain
695  /// simple value type SVT if it is not the Any type.
696  const TargetRegisterClass *
697  getCommonSubClass(const TargetRegisterClass *A,
698  const TargetRegisterClass *B,
699  const MVT::SimpleValueType SVT =
701 
702  /// Returns a TargetRegisterClass used for pointer values.
703  /// If a target supports multiple different pointer register classes,
704  /// kind specifies which one is indicated.
705  virtual const TargetRegisterClass *
706  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
707  llvm_unreachable("Target didn't implement getPointerRegClass!");
708  }
709 
710  /// Returns a legal register class to copy a register in the specified class
711  /// to or from. If it is possible to copy the register directly without using
712  /// a cross register class copy, return the specified RC. Returns NULL if it
713  /// is not possible to copy between two registers of the specified class.
714  virtual const TargetRegisterClass *
716  return RC;
717  }
718 
719  /// Returns the largest super class of RC that is legal to use in the current
720  /// sub-target and has the same spill size.
721  /// The returned register class can be used to create virtual registers which
722  /// means that all its registers can be copied and spilled.
723  virtual const TargetRegisterClass *
725  const MachineFunction &) const {
726  /// The default implementation is very conservative and doesn't allow the
727  /// register allocator to inflate register classes.
728  return RC;
729  }
730 
731  /// Return the register pressure "high water mark" for the specific register
732  /// class. The scheduler is in high register pressure mode (for the specific
733  /// register class) if it goes over the limit.
734  ///
735  /// Note: this is the old register pressure model that relies on a manually
736  /// specified representative register class per value type.
737  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
738  MachineFunction &MF) const {
739  return 0;
740  }
741 
742  /// Return a heuristic for the machine scheduler to compare the profitability
743  /// of increasing one register pressure set versus another. The scheduler
744  /// will prefer increasing the register pressure of the set which returns
745  /// the largest value for this function.
746  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
747  unsigned PSetID) const {
748  return PSetID;
749  }
750 
751  /// Get the weight in units of pressure for this register class.
752  virtual const RegClassWeight &getRegClassWeight(
753  const TargetRegisterClass *RC) const = 0;
754 
755  /// Get the weight in units of pressure for this register unit.
756  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
757 
758  /// Get the number of dimensions of register pressure.
759  virtual unsigned getNumRegPressureSets() const = 0;
760 
761  /// Get the name of this register unit pressure set.
762  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
763 
764  /// Get the register unit pressure limit for this dimension.
765  /// This limit must be adjusted dynamically for reserved registers.
766  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
767  unsigned Idx) const = 0;
768 
769  /// Get the dimensions of register pressure impacted by this register class.
770  /// Returns a -1 terminated array of pressure set IDs.
771  virtual const int *getRegClassPressureSets(
772  const TargetRegisterClass *RC) const = 0;
773 
774  /// Get the dimensions of register pressure impacted by this register unit.
775  /// Returns a -1 terminated array of pressure set IDs.
776  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
777 
778  /// Get a list of 'hint' registers that the register allocator should try
779  /// first when allocating a physical register for the virtual register
780  /// VirtReg. These registers are effectively moved to the front of the
781  /// allocation order. If true is returned, regalloc will try to only use
782  /// hints to the greatest extent possible even if it means spilling.
783  ///
784  /// The Order argument is the allocation order for VirtReg's register class
785  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
786  /// come from Order, and they must not be reserved.
787  ///
788  /// The default implementation of this function will only add target
789  /// independent register allocation hints. Targets that override this
790  /// function should typically call this default implementation as well and
791  /// expect to see generic copy hints added.
792  virtual bool getRegAllocationHints(unsigned VirtReg,
793  ArrayRef<MCPhysReg> Order,
795  const MachineFunction &MF,
796  const VirtRegMap *VRM = nullptr,
797  const LiveRegMatrix *Matrix = nullptr)
798  const;
799 
800  /// A callback to allow target a chance to update register allocation hints
801  /// when a register is "changed" (e.g. coalesced) to another register.
802  /// e.g. On ARM, some virtual registers should target register pairs,
803  /// if one of pair is coalesced to another register, the allocation hint of
804  /// the other half of the pair should be changed to point to the new register.
805  virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
806  MachineFunction &MF) const {
807  // Do nothing.
808  }
809 
810  /// The creation of multiple copy hints have been implemented in
811  /// weightCalcHelper(), but since this affects so many tests for many
812  /// targets, this is temporarily disabled per default. THIS SHOULD BE
813  /// "GENERAL GOODNESS" and hopefully all targets will update their tests
814  /// and enable this soon. This hook should then be removed.
815  virtual bool enableMultipleCopyHints() const { return false; }
816 
817  /// Allow the target to reverse allocation order of local live ranges. This
818  /// will generally allocate shorter local live ranges first. For targets with
819  /// many registers, this could reduce regalloc compile time by a large
820  /// factor. It is disabled by default for three reasons:
821  /// (1) Top-down allocation is simpler and easier to debug for targets that
822  /// don't benefit from reversing the order.
823  /// (2) Bottom-up allocation could result in poor evicition decisions on some
824  /// targets affecting the performance of compiled code.
825  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
826  virtual bool reverseLocalAssignment() const { return false; }
827 
828  /// Allow the target to override the cost of using a callee-saved register for
829  /// the first time. Default value of 0 means we will use a callee-saved
830  /// register if it is available.
831  virtual unsigned getCSRFirstUseCost() const { return 0; }
832 
833  /// Returns true if the target requires (and can make use of) the register
834  /// scavenger.
835  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
836  return false;
837  }
838 
839  /// Returns true if the target wants to use frame pointer based accesses to
840  /// spill to the scavenger emergency spill slot.
841  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
842  return true;
843  }
844 
845  /// Returns true if the target requires post PEI scavenging of registers for
846  /// materializing frame index constants.
847  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
848  return false;
849  }
850 
851  /// Returns true if the target requires using the RegScavenger directly for
852  /// frame elimination despite using requiresFrameIndexScavenging.
854  const MachineFunction &MF) const {
855  return false;
856  }
857 
858  /// Returns true if the target wants the LocalStackAllocation pass to be run
859  /// and virtual base registers used for more efficient stack access.
860  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
861  return false;
862  }
863 
864  /// Return true if target has reserved a spill slot in the stack frame of
865  /// the given function for the specified register. e.g. On x86, if the frame
866  /// register is required, the first fixed stack object is reserved as its
867  /// spill slot. This tells PEI not to create a new stack frame
868  /// object for the given register. It should be called only after
869  /// determineCalleeSaves().
870  virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
871  int &FrameIdx) const {
872  return false;
873  }
874 
875  /// Returns true if the live-ins should be tracked after register allocation.
876  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
877  return false;
878  }
879 
880  /// True if the stack can be realigned for the target.
881  virtual bool canRealignStack(const MachineFunction &MF) const;
882 
883  /// True if storage within the function requires the stack pointer to be
884  /// aligned more than the normal calling convention calls for.
885  /// This cannot be overriden by the target, but canRealignStack can be
886  /// overridden.
887  bool needsStackRealignment(const MachineFunction &MF) const;
888 
889  /// Get the offset from the referenced frame index in the instruction,
890  /// if there is one.
891  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
892  int Idx) const {
893  return 0;
894  }
895 
896  /// Returns true if the instruction's frame index reference would be better
897  /// served by a base register other than FP or SP.
898  /// Used by LocalStackFrameAllocation to determine which frame index
899  /// references it should create new base registers for.
900  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
901  return false;
902  }
903 
904  /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
905  /// before insertion point I.
907  unsigned BaseReg, int FrameIdx,
908  int64_t Offset) const {
909  llvm_unreachable("materializeFrameBaseRegister does not exist on this "
910  "target");
911  }
912 
913  /// Resolve a frame index operand of an instruction
914  /// to reference the indicated base register plus offset instead.
915  virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
916  int64_t Offset) const {
917  llvm_unreachable("resolveFrameIndex does not exist on this target");
918  }
919 
920  /// Determine whether a given base register plus offset immediate is
921  /// encodable to resolve a frame index.
922  virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
923  int64_t Offset) const {
924  llvm_unreachable("isFrameOffsetLegal does not exist on this target");
925  }
926 
927  /// Spill the register so it can be used by the register scavenger.
928  /// Return true if the register was spilled, false otherwise.
929  /// If this function does not spill the register, the scavenger
930  /// will instead spill it to the emergency spill slot.
934  const TargetRegisterClass *RC,
935  unsigned Reg) const {
936  return false;
937  }
938 
939  /// This method must be overriden to eliminate abstract frame indices from
940  /// instructions which may use them. The instruction referenced by the
941  /// iterator contains an MO_FrameIndex operand which must be eliminated by
942  /// this method. This method may modify or replace the specified instruction,
943  /// as long as it keeps the iterator pointing at the finished product.
944  /// SPAdj is the SP adjustment due to call frame setup instruction.
945  /// FIOperandNum is the FI operand number.
946  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
947  int SPAdj, unsigned FIOperandNum,
948  RegScavenger *RS = nullptr) const = 0;
949 
950  /// Return the assembly name for \p Reg.
951  virtual StringRef getRegAsmName(unsigned Reg) const {
952  // FIXME: We are assuming that the assembly name is equal to the TableGen
953  // name converted to lower case
954  //
955  // The TableGen name is the name of the definition for this register in the
956  // target's tablegen files. For example, the TableGen name of
957  // def EAX : Register <...>; is "EAX"
958  return StringRef(getName(Reg));
959  }
960 
961  //===--------------------------------------------------------------------===//
962  /// Subtarget Hooks
963 
964  /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
965  virtual bool shouldCoalesce(MachineInstr *MI,
966  const TargetRegisterClass *SrcRC,
967  unsigned SubReg,
968  const TargetRegisterClass *DstRC,
969  unsigned DstSubReg,
970  const TargetRegisterClass *NewRC,
971  LiveIntervals &LIS) const
972  { return true; }
973 
974  //===--------------------------------------------------------------------===//
975  /// Debug information queries.
976 
977  /// getFrameRegister - This method should return the register used as a base
978  /// for values allocated in the current stack frame.
979  virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
980 
981  /// Mark a register and all its aliases as reserved in the given set.
982  void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
983 
984  /// Returns true if for every register in the set all super registers are part
985  /// of the set as well.
986  bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
987  ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
988 };
989 
990 //===----------------------------------------------------------------------===//
991 // SuperRegClassIterator
992 //===----------------------------------------------------------------------===//
993 //
994 // Iterate over the possible super-registers for a given register class. The
995 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
996 // possible classes of super-registers.
997 //
998 // Each bit mask will have at least one set bit, and each set bit in Mask
999 // corresponds to a SuperRC such that:
1000 //
1001 // For all Reg in SuperRC: Reg:Idx is in RC.
1002 //
1003 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
1004 // also satisfies the above requirement, assuming Reg:0 == Reg.
1005 //
1007  const unsigned RCMaskWords;
1008  unsigned SubReg = 0;
1009  const uint16_t *Idx;
1010  const uint32_t *Mask;
1011 
1012 public:
1013  /// Create a SuperRegClassIterator that visits all the super-register classes
1014  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1016  const TargetRegisterInfo *TRI,
1017  bool IncludeSelf = false)
1018  : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1019  Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1020  if (!IncludeSelf)
1021  ++*this;
1022  }
1023 
1024  /// Returns true if this iterator is still pointing at a valid entry.
1025  bool isValid() const { return Idx; }
1026 
1027  /// Returns the current sub-register index.
1028  unsigned getSubReg() const { return SubReg; }
1029 
1030  /// Returns the bit mask of register classes that getSubReg() projects into
1031  /// RC.
1032  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1033  const uint32_t *getMask() const { return Mask; }
1034 
1035  /// Advance iterator to the next entry.
1036  void operator++() {
1037  assert(isValid() && "Cannot move iterator past end.");
1038  Mask += RCMaskWords;
1039  SubReg = *Idx++;
1040  if (!SubReg)
1041  Idx = nullptr;
1042  }
1043 };
1044 
1045 //===----------------------------------------------------------------------===//
1046 // BitMaskClassIterator
1047 //===----------------------------------------------------------------------===//
1048 /// This class encapuslates the logic to iterate over bitmask returned by
1049 /// the various RegClass related APIs.
1050 /// E.g., this class can be used to iterate over the subclasses provided by
1051 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1053  /// Total number of register classes.
1054  const unsigned NumRegClasses;
1055  /// Base index of CurrentChunk.
1056  /// In other words, the number of bit we read to get at the
1057  /// beginning of that chunck.
1058  unsigned Base = 0;
1059  /// Adjust base index of CurrentChunk.
1060  /// Base index + how many bit we read within CurrentChunk.
1061  unsigned Idx = 0;
1062  /// Current register class ID.
1063  unsigned ID = 0;
1064  /// Mask we are iterating over.
1065  const uint32_t *Mask;
1066  /// Current chunk of the Mask we are traversing.
1067  uint32_t CurrentChunk;
1068 
1069  /// Move ID to the next set bit.
1070  void moveToNextID() {
1071  // If the current chunk of memory is empty, move to the next one,
1072  // while making sure we do not go pass the number of register
1073  // classes.
1074  while (!CurrentChunk) {
1075  // Move to the next chunk.
1076  Base += 32;
1077  if (Base >= NumRegClasses) {
1078  ID = NumRegClasses;
1079  return;
1080  }
1081  CurrentChunk = *++Mask;
1082  Idx = Base;
1083  }
1084  // Otherwise look for the first bit set from the right
1085  // (representation of the class ID is big endian).
1086  // See getSubClassMask for more details on the representation.
1087  unsigned Offset = countTrailingZeros(CurrentChunk);
1088  // Add the Offset to the adjusted base number of this chunk: Idx.
1089  // This is the ID of the register class.
1090  ID = Idx + Offset;
1091 
1092  // Consume the zeros, if any, and the bit we just read
1093  // so that we are at the right spot for the next call.
1094  // Do not do Offset + 1 because Offset may be 31 and 32
1095  // will be UB for the shift, though in that case we could
1096  // have make the chunk being equal to 0, but that would
1097  // have introduced a if statement.
1098  moveNBits(Offset);
1099  moveNBits(1);
1100  }
1101 
1102  /// Move \p NumBits Bits forward in CurrentChunk.
1103  void moveNBits(unsigned NumBits) {
1104  assert(NumBits < 32 && "Undefined behavior spotted!");
1105  // Consume the bit we read for the next call.
1106  CurrentChunk >>= NumBits;
1107  // Adjust the base for the chunk.
1108  Idx += NumBits;
1109  }
1110 
1111 public:
1112  /// Create a BitMaskClassIterator that visits all the register classes
1113  /// represented by \p Mask.
1114  ///
1115  /// \pre \p Mask != nullptr
1117  : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1118  // Move to the first ID.
1119  moveToNextID();
1120  }
1121 
1122  /// Returns true if this iterator is still pointing at a valid entry.
1123  bool isValid() const { return getID() != NumRegClasses; }
1124 
1125  /// Returns the current register class ID.
1126  unsigned getID() const { return ID; }
1127 
1128  /// Advance iterator to the next entry.
1129  void operator++() {
1130  assert(isValid() && "Cannot move iterator past end.");
1131  moveToNextID();
1132  }
1133 };
1134 
1135 // This is useful when building IndexedMaps keyed on virtual registers
1138  unsigned operator()(unsigned Reg) const {
1140  }
1141 };
1142 
1143 /// Prints virtual and physical registers with or without a TRI instance.
1144 ///
1145 /// The format is:
1146 /// %noreg - NoRegister
1147 /// %5 - a virtual register.
1148 /// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1149 /// %eax - a physical register
1150 /// %physreg17 - a physical register when no TRI instance given.
1151 ///
1152 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1153 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1154  unsigned SubRegIdx = 0);
1155 
1156 /// Create Printable object to print register units on a \ref raw_ostream.
1157 ///
1158 /// Register units are named after their root registers:
1159 ///
1160 /// al - Single root.
1161 /// fp0~st7 - Dual roots.
1162 ///
1163 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1164 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1165 
1166 /// \brief Create Printable object to print virtual registers and physical
1167 /// registers on a \ref raw_ostream.
1168 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1169 
1170 /// \brief Create Printable object to print register classes or register banks
1171 /// on a \ref raw_ostream.
1172 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
1173  const TargetRegisterInfo *TRI);
1174 
1175 } // end namespace llvm
1176 
1177 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
A common definition of LaneBitmask for use in TableGen and CodeGen.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger. ...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
SI Whole Quad Mode
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
iterator begin() const
begin/end - Return all of the registers in this class.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumRegs() const
Return the number of registers in this class.
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
iterator begin() const
begin/end - Return all of the registers in this class.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
unsigned getRegister(unsigned i) const
Return the specified register in the class.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getCostPerUse(unsigned RegNo) const
Return the additional cost of using this register instead of other registers in its class...
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
unsigned getSubReg() const
Returns the current sub-register index.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Live Register Matrix
unsigned getID() const
getID() - Return the register class ID number.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index...
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
virtual bool enableMultipleCopyHints() const
The creation of multiple copy hints have been implemented in weightCalcHelper(), but since this affec...
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const uint16_t * SuperRegIndices
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
unsigned SubReg
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:413
Reg
All possible values of the reg field in the ModR/M byte.
static StringRef getName(Value *V)
iterator_range< regclass_iterator > regclasses() const
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getNumRegClasses() const
regclass_iterator regclass_begin() const
Register class iterators.
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
Returns true if Reg contains RegUnit.
void operator++()
Advance iterator to the next entry.
bool contains(unsigned Reg1, unsigned Reg2) const
Return true if both registers are in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
MCRegisterClass - Base class of TargetRegisterClass.
virtual StringRef getRegAsmName(unsigned Reg) const
Return the assembly name for Reg.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Machine Value Type.
const sc_iterator SuperClasses
const TargetRegisterClass *const * regclass_iterator
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
MachineInstrBuilder & UseMI
regclass_iterator regclass_end() const
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time...
iterator end() const
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Extra information, not in MCRegisterDesc, about registers.
virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
const char * getRegClassName(const MCRegisterClass *Class) const
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
A range adaptor for a pair of iterators.
const MCRegisterClass * MC
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned operator()(unsigned Reg) const
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
#define I(x, y, z)
Definition: MD5.cpp:58
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getID() const
Returns the current register class ID.
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
const MCPhysReg * const_iterator
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
void operator++()
Advance iterator to the next entry.
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I...
static unsigned index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
Spill the register so it can be used by the register scavenger.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...