LLVM  6.0.0svn
RegisterBankInfo.h
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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file declares the API for the register bank info.
11 /// This API is responsible for handling the register banks.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
16 #define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/Hashing.h"
20 #include "llvm/ADT/SmallVector.h"
23 #include <cassert>
24 #include <initializer_list>
25 #include <memory>
26 
27 namespace llvm {
28 
29 class MachineInstr;
30 class MachineRegisterInfo;
31 class raw_ostream;
32 class RegisterBank;
33 class TargetInstrInfo;
34 class TargetRegisterClass;
35 class TargetRegisterInfo;
36 
37 /// Holds all the information related to register banks.
39 public:
40  /// Helper struct that represents how a value is partially mapped
41  /// into a register.
42  /// The StartIdx and Length represent what region of the orginal
43  /// value this partial mapping covers.
44  /// This can be represented as a Mask of contiguous bit starting
45  /// at StartIdx bit and spanning Length bits.
46  /// StartIdx is the number of bits from the less significant bits.
47  struct PartialMapping {
48  /// Number of bits at which this partial mapping starts in the
49  /// original value. The bits are counted from less significant
50  /// bits to most significant bits.
51  unsigned StartIdx;
52 
53  /// Length of this mapping in bits. This is how many bits this
54  /// partial mapping covers in the original value:
55  /// from StartIdx to StartIdx + Length -1.
56  unsigned Length;
57 
58  /// Register bank where the partial value lives.
60 
61  PartialMapping() = default;
62 
63  /// Provide a shortcut for quickly building PartialMapping.
64  PartialMapping(unsigned StartIdx, unsigned Length,
65  const RegisterBank &RegBank)
66  : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
67 
68  /// \return the index of in the original value of the most
69  /// significant bit that this partial mapping covers.
70  unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
71 
72  /// Print this partial mapping on dbgs() stream.
73  void dump() const;
74 
75  /// Print this partial mapping on \p OS;
76  void print(raw_ostream &OS) const;
77 
78  /// Check that the Mask is compatible with the RegBank.
79  /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
80  /// there is no way this mapping is valid.
81  ///
82  /// \note This method does not check anything when assertions are disabled.
83  ///
84  /// \return True is the check was successful.
85  bool verify() const;
86  };
87 
88  /// Helper struct that represents how a value is mapped through
89  /// different register banks.
90  ///
91  /// \note: So far we do not have any users of the complex mappings
92  /// (mappings with more than one partial mapping), but when we do,
93  /// we would have needed to duplicate partial mappings.
94  /// The alternative could be to use an array of pointers of partial
95  /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
96  /// pointers instead.
97  ///
98  /// E.g.,
99  /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
100  /// can expand the
101  /// <2 x 32-bit> add into 2 x 32-bit add.
102  ///
103  /// Currently the TableGen-like file would look like:
104  /// \code
105  /// PartialMapping[] = {
106  /// /*32-bit add*/ {0, 32, GPR},
107  /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
108  /// /*<2x32-bit> vadd {0, 64, VPR}
109  /// }; // PartialMapping duplicated.
110  ///
111  /// ValueMapping[] {
112  /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
113  /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
114  /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
115  /// };
116  /// \endcode
117  ///
118  /// With the array of pointer, we would have:
119  /// \code
120  /// PartialMapping[] = {
121  /// /*32-bit add*/ {0, 32, GPR},
122  /// /*<2x32-bit> vadd {0, 64, VPR}
123  /// }; // No more duplication.
124  ///
125  /// BreakDowns[] = {
126  /// /*AddBreakDown*/ &PartialMapping[0],
127  /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0],
128  /// /*VAddBreakDown*/ &PartialMapping[1]
129  /// }; // Addresses of PartialMapping duplicated (smaller).
130  ///
131  /// ValueMapping[] {
132  /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
133  /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
134  /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
135  /// };
136  /// \endcode
137  ///
138  /// Given that a PartialMapping is actually small, the code size
139  /// impact is actually a degradation. Moreover the compile time will
140  /// be hit by the additional indirection.
141  /// If PartialMapping gets bigger we may reconsider.
142  struct ValueMapping {
143  /// How the value is broken down between the different register banks.
145 
146  /// Number of partial mapping to break down this value.
147  unsigned NumBreakDowns;
148 
149  /// The default constructor creates an invalid (isValid() == false)
150  /// instance.
151  ValueMapping() : ValueMapping(nullptr, 0) {}
152 
153  /// Initialize a ValueMapping with the given parameter.
154  /// \p BreakDown needs to have a life time at least as long
155  /// as this instance.
156  ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
157  : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
158 
159  /// Iterators through the PartialMappings.
160  const PartialMapping *begin() const { return BreakDown; }
161  const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
162 
163  /// Check if this ValueMapping is valid.
164  bool isValid() const { return BreakDown && NumBreakDowns; }
165 
166  /// Verify that this mapping makes sense for a value of
167  /// \p MeaningfulBitWidth.
168  /// \note This method does not check anything when assertions are disabled.
169  ///
170  /// \return True is the check was successful.
171  bool verify(unsigned MeaningfulBitWidth) const;
172 
173  /// Print this on dbgs() stream.
174  void dump() const;
175 
176  /// Print this on \p OS;
177  void print(raw_ostream &OS) const;
178  };
179 
180  /// Helper class that represents how the value of an instruction may be
181  /// mapped and what is the related cost of such mapping.
183  /// Identifier of the mapping.
184  /// This is used to communicate between the target and the optimizers
185  /// which mapping should be realized.
186  unsigned ID = InvalidMappingID;
187 
188  /// Cost of this mapping.
189  unsigned Cost = 0;
190 
191  /// Mapping of all the operands.
192  const ValueMapping *OperandsMapping;
193 
194  /// Number of operands.
195  unsigned NumOperands = 0;
196 
197  const ValueMapping &getOperandMapping(unsigned i) {
198  assert(i < getNumOperands() && "Out of bound operand");
199  return OperandsMapping[i];
200  }
201 
202  public:
203  /// Constructor for the mapping of an instruction.
204  /// \p NumOperands must be equal to number of all the operands of
205  /// the related instruction.
206  /// The rationale is that it is more efficient for the optimizers
207  /// to be able to assume that the mapping of the ith operand is
208  /// at the index i.
209  ///
210  /// \pre ID != InvalidMappingID
211  InstructionMapping(unsigned ID, unsigned Cost,
212  const ValueMapping *OperandsMapping,
213  unsigned NumOperands)
214  : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
215  NumOperands(NumOperands) {
217  "Use the default constructor for invalid mapping");
218  }
219 
220  /// Default constructor.
221  /// Use this constructor to express that the mapping is invalid.
222  InstructionMapping() = default;
223 
224  /// Get the cost.
225  unsigned getCost() const { return Cost; }
226 
227  /// Get the ID.
228  unsigned getID() const { return ID; }
229 
230  /// Get the number of operands.
231  unsigned getNumOperands() const { return NumOperands; }
232 
233  /// Get the value mapping of the ith operand.
234  /// \pre The mapping for the ith operand has been set.
235  /// \pre The ith operand is a register.
236  const ValueMapping &getOperandMapping(unsigned i) const {
237  const ValueMapping &ValMapping =
238  const_cast<InstructionMapping *>(this)->getOperandMapping(i);
239  return ValMapping;
240  }
241 
242  /// Set the mapping for all the operands.
243  /// In other words, OpdsMapping should hold at least getNumOperands
244  /// ValueMapping.
245  void setOperandsMapping(const ValueMapping *OpdsMapping) {
246  OperandsMapping = OpdsMapping;
247  }
248 
249  /// Check whether this object is valid.
250  /// This is a lightweight check for obvious wrong instance.
251  bool isValid() const {
252  return getID() != InvalidMappingID && OperandsMapping;
253  }
254 
255  /// Verifiy that this mapping makes sense for \p MI.
256  /// \pre \p MI must be connected to a MachineFunction.
257  ///
258  /// \note This method does not check anything when assertions are disabled.
259  ///
260  /// \return True is the check was successful.
261  bool verify(const MachineInstr &MI) const;
262 
263  /// Print this on dbgs() stream.
264  void dump() const;
265 
266  /// Print this on \p OS;
267  void print(raw_ostream &OS) const;
268  };
269 
270  /// Convenient type to represent the alternatives for mapping an
271  /// instruction.
272  /// \todo When we move to TableGen this should be an array ref.
274 
275  /// Helper class used to get/create the virtual registers that will be used
276  /// to replace the MachineOperand when applying a mapping.
278  /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
279  /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
280  /// Note: We use a SmallVector to avoid heap allocation for most cases.
281  SmallVector<int, 8> OpToNewVRegIdx;
282 
283  /// Hold the registers that will be used to map MI with InstrMapping.
284  SmallVector<unsigned, 8> NewVRegs;
285 
286  /// Current MachineRegisterInfo, used to create new virtual registers.
288 
289  /// Instruction being remapped.
290  MachineInstr &MI;
291 
292  /// New mapping of the instruction.
293  const InstructionMapping &InstrMapping;
294 
295  /// Constant value identifying that the index in OpToNewVRegIdx
296  /// for an operand has not been set yet.
297  static const int DontKnowIdx;
298 
299  /// Get the range in NewVRegs to store all the partial
300  /// values for the \p OpIdx-th operand.
301  ///
302  /// \return The iterator range for the space created.
303  //
304  /// \pre getMI().getOperand(OpIdx).isReg()
306  getVRegsMem(unsigned OpIdx);
307 
308  /// Get the end iterator for a range starting at \p StartIdx and
309  /// spannig \p NumVal in NewVRegs.
310  /// \pre StartIdx + NumVal <= NewVRegs.size()
312  getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
313  SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx,
314  unsigned NumVal);
315 
316  public:
317  /// Create an OperandsMapper that will hold the information to apply \p
318  /// InstrMapping to \p MI.
319  /// \pre InstrMapping.verify(MI)
320  OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
321  MachineRegisterInfo &MRI);
322 
323  /// \name Getters.
324  /// @{
325  /// The MachineInstr being remapped.
326  MachineInstr &getMI() const { return MI; }
327 
328  /// The final mapping of the instruction.
329  const InstructionMapping &getInstrMapping() const { return InstrMapping; }
330 
331  /// The MachineRegisterInfo we used to realize the mapping.
332  MachineRegisterInfo &getMRI() const { return MRI; }
333  /// @}
334 
335  /// Create as many new virtual registers as needed for the mapping of the \p
336  /// OpIdx-th operand.
337  /// The number of registers is determined by the number of breakdown for the
338  /// related operand in the instruction mapping.
339  /// The type of the new registers is a plain scalar of the right size.
340  /// The proper type is expected to be set when the mapping is applied to
341  /// the instruction(s) that realizes the mapping.
342  ///
343  /// \pre getMI().getOperand(OpIdx).isReg()
344  ///
345  /// \post All the partial mapping of the \p OpIdx-th operand have been
346  /// assigned a new virtual register.
347  void createVRegs(unsigned OpIdx);
348 
349  /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
350  /// the OpIdx-th operand to \p NewVReg.
351  ///
352  /// \pre getMI().getOperand(OpIdx).isReg()
353  /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
354  /// PartialMapIdx
355  /// \pre NewReg != 0
356  ///
357  /// \post the \p PartialMapIdx-th register of the value mapping of the \p
358  /// OpIdx-th operand has been set.
359  void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
360 
361  /// Get all the virtual registers required to map the \p OpIdx-th operand of
362  /// the instruction.
363  ///
364  /// This return an empty range when createVRegs or setVRegs has not been
365  /// called.
366  /// The iterator may be invalidated by a call to setVRegs or createVRegs.
367  ///
368  /// When \p ForDebug is true, we will not check that the list of new virtual
369  /// registers does not contain uninitialized values.
370  ///
371  /// \pre getMI().getOperand(OpIdx).isReg()
372  /// \pre ForDebug || All partial mappings have been set a register
374  getVRegs(unsigned OpIdx, bool ForDebug = false) const;
375 
376  /// Print this operands mapper on dbgs() stream.
377  void dump() const;
378 
379  /// Print this operands mapper on \p OS stream.
380  void print(raw_ostream &OS, bool ForDebug = false) const;
381  };
382 
383 protected:
384  /// Hold the set of supported register banks.
386 
387  /// Total number of register banks.
388  unsigned NumRegBanks;
389 
390  /// Keep dynamically allocated PartialMapping in a separate map.
391  /// This shouldn't be needed when everything gets TableGen'ed.
394 
395  /// Keep dynamically allocated ValueMapping in a separate map.
396  /// This shouldn't be needed when everything gets TableGen'ed.
399 
400  /// Keep dynamically allocated array of ValueMapping in a separate map.
401  /// This shouldn't be needed when everything gets TableGen'ed.
404 
405  /// Keep dynamically allocated InstructionMapping in a separate map.
406  /// This shouldn't be needed when everything gets TableGen'ed.
409 
410  /// Getting the minimal register class of a physreg is expensive.
411  /// Cache this information as we get it.
413 
414  /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
415  /// RegisterBank instances.
416  RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
417 
418  /// This constructor is meaningless.
419  /// It just provides a default constructor that can be used at link time
420  /// when GlobalISel is not built.
421  /// That way, targets can still inherit from this class without doing
422  /// crazy gymnastic to avoid link time failures.
423  /// \note That works because the constructor is inlined.
425  llvm_unreachable("This constructor should not be executed");
426  }
427 
428  /// Get the register bank identified by \p ID.
430  assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
431  return *RegBanks[ID];
432  }
433 
434  /// Get the MinimalPhysRegClass for Reg.
435  /// \pre Reg is a physical register.
436  const TargetRegisterClass &
437  getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const;
438 
439  /// Try to get the mapping of \p MI.
440  /// See getInstrMapping for more details on what a mapping represents.
441  ///
442  /// Unlike getInstrMapping the returned InstructionMapping may be invalid
443  /// (isValid() == false).
444  /// This means that the target independent code is not smart enough
445  /// to get the mapping of \p MI and thus, the target has to provide the
446  /// information for \p MI.
447  ///
448  /// This implementation is able to get the mapping of:
449  /// - Target specific instructions by looking at the encoding constraints.
450  /// - Any instruction if all the register operands have already been assigned
451  /// a register, a register class, or a register bank.
452  /// - Copies and phis if at least one of the operands has been assigned a
453  /// register, a register class, or a register bank.
454  /// In other words, this method will likely fail to find a mapping for
455  /// any generic opcode that has not been lowered by target specific code.
457 
458  /// Get the uniquely generated PartialMapping for the
459  /// given arguments.
460  const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
461  const RegisterBank &RegBank) const;
462 
463  /// \name Methods to get a uniquely generated ValueMapping.
464  /// @{
465 
466  /// The most common ValueMapping consists of a single PartialMapping.
467  /// Feature a method for that.
468  const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
469  const RegisterBank &RegBank) const;
470 
471  /// Get the ValueMapping for the given arguments.
472  const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
473  unsigned NumBreakDowns) const;
474  /// @}
475 
476  /// \name Methods to get a uniquely generated array of ValueMapping.
477  /// @{
478 
479  /// Get the uniquely generated array of ValueMapping for the
480  /// elements of between \p Begin and \p End.
481  ///
482  /// Elements that are nullptr will be replaced by
483  /// invalid ValueMapping (ValueMapping::isValid == false).
484  ///
485  /// \pre The pointers on ValueMapping between \p Begin and \p End
486  /// must uniquely identify a ValueMapping. Otherwise, there is no
487  /// guarantee that the return instance will be unique, i.e., another
488  /// OperandsMapping could have the same content.
489  template <typename Iterator>
490  const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
491 
492  /// Get the uniquely generated array of ValueMapping for the
493  /// elements of \p OpdsMapping.
494  ///
495  /// Elements of \p OpdsMapping that are nullptr will be replaced by
496  /// invalid ValueMapping (ValueMapping::isValid == false).
498  const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
499 
500  /// Get the uniquely generated array of ValueMapping for the
501  /// given arguments.
502  ///
503  /// Arguments that are nullptr will be replaced by invalid
504  /// ValueMapping (ValueMapping::isValid == false).
506  std::initializer_list<const ValueMapping *> OpdsMapping) const;
507  /// @}
508 
509  /// \name Methods to get a uniquely generated InstructionMapping.
510  /// @{
511 
512 private:
513  /// Method to get a uniquely generated InstructionMapping.
514  const InstructionMapping &
515  getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
516  unsigned Cost = 0,
517  const ValueMapping *OperandsMapping = nullptr,
518  unsigned NumOperands = 0) const;
519 
520 public:
521  /// Method to get a uniquely generated InstructionMapping.
522  const InstructionMapping &
523  getInstructionMapping(unsigned ID, unsigned Cost,
524  const ValueMapping *OperandsMapping,
525  unsigned NumOperands) const {
526  return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
527  OperandsMapping, NumOperands);
528  }
529 
530  /// Method to get a uniquely generated invalid InstructionMapping.
532  return getInstructionMappingImpl(/*IsInvalid*/ true);
533  }
534  /// @}
535 
536  /// Get the register bank for the \p OpIdx-th operand of \p MI form
537  /// the encoding constraints, if any.
538  ///
539  /// \return A register bank that covers the register class of the
540  /// related encoding constraints or nullptr if \p MI did not provide
541  /// enough information to deduce it.
542  const RegisterBank *
543  getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
544  const TargetInstrInfo &TII,
545  const TargetRegisterInfo &TRI) const;
546 
547  /// Helper method to apply something that is like the default mapping.
548  /// Basically, that means that \p OpdMapper.getMI() is left untouched
549  /// aside from the reassignment of the register operand that have been
550  /// remapped.
551  ///
552  /// The type of all the new registers that have been created by the
553  /// mapper are properly remapped to the type of the original registers
554  /// they replace. In other words, the semantic of the instruction does
555  /// not change, only the register banks.
556  ///
557  /// If the mapping of one of the operand spans several registers, this
558  /// method will abort as this is not like a default mapping anymore.
559  ///
560  /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
561  /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
562  static void applyDefaultMapping(const OperandsMapper &OpdMapper);
563 
564  /// See ::applyMapping.
565  virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
566  llvm_unreachable("The target has to implement that part");
567  }
568 
569 public:
570  virtual ~RegisterBankInfo() = default;
571 
572  /// Get the register bank identified by \p ID.
573  const RegisterBank &getRegBank(unsigned ID) const {
574  return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
575  }
576 
577  /// Get the register bank of \p Reg.
578  /// If Reg has not been assigned a register, a register class,
579  /// or a register bank, then this returns nullptr.
580  ///
581  /// \pre Reg != 0 (NoRegister)
582  const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
583  const TargetRegisterInfo &TRI) const;
584 
585  /// Get the total number of register banks.
586  unsigned getNumRegBanks() const { return NumRegBanks; }
587 
588  /// Get a register bank that covers \p RC.
589  ///
590  /// \pre \p RC is a user-defined register class (as opposed as one
591  /// generated by TableGen).
592  ///
593  /// \note The mapping RC -> RegBank could be built while adding the
594  /// coverage for the register banks. However, we do not do it, because,
595  /// at least for now, we only need this information for register classes
596  /// that are used in the description of instruction. In other words,
597  /// there are just a handful of them and we do not want to waste space.
598  ///
599  /// \todo This should be TableGen'ed.
600  virtual const RegisterBank &
602  llvm_unreachable("The target must override this method");
603  }
604 
605  /// Get the cost of a copy from \p B to \p A, or put differently,
606  /// get the cost of A = COPY B. Since register banks may cover
607  /// different size, \p Size specifies what will be the size in bits
608  /// that will be copied around.
609  ///
610  /// \note Since this is a copy, both registers have the same size.
611  virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
612  unsigned Size) const {
613  // Optimistically assume that copies are coalesced. I.e., when
614  // they are on the same bank, they are free.
615  // Otherwise assume a non-zero cost of 1. The targets are supposed
616  // to override that properly anyway if they care.
617  return &A != &B;
618  }
619 
620  /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
621  ///
622  /// \pre \p Reg is a virtual register that either has a bank or a class.
623  /// \returns The constrained register class, or nullptr if there is none.
624  /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
625  static const TargetRegisterClass *
626  constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC,
627  MachineRegisterInfo &MRI);
628 
629  /// Identifier used when the related instruction mapping instance
630  /// is generated by target independent code.
631  /// Make sure not to use that identifier to avoid possible collision.
632  static const unsigned DefaultMappingID;
633 
634  /// Identifier used when the related instruction mapping instance
635  /// is generated by the default constructor.
636  /// Make sure not to use that identifier.
637  static const unsigned InvalidMappingID;
638 
639  /// Get the mapping of the different operands of \p MI
640  /// on the register bank.
641  /// This mapping should be the direct translation of \p MI.
642  /// In other words, when \p MI is mapped with the returned mapping,
643  /// only the register banks of the operands of \p MI need to be updated.
644  /// In particular, neither the opcode nor the type of \p MI needs to be
645  /// updated for this direct mapping.
646  ///
647  /// The target independent implementation gives a mapping based on
648  /// the register classes for the target specific opcode.
649  /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
650  /// Make sure you do not use that ID for the alternative mapping
651  /// for MI. See getInstrAlternativeMappings for the alternative
652  /// mappings.
653  ///
654  /// For instance, if \p MI is a vector add, the mapping should
655  /// not be a scalarization of the add.
656  ///
657  /// \post returnedVal.verify(MI).
658  ///
659  /// \note If returnedVal does not verify MI, this would probably mean
660  /// that the target does not support that instruction.
661  virtual const InstructionMapping &
662  getInstrMapping(const MachineInstr &MI) const;
663 
664  /// Get the alternative mappings for \p MI.
665  /// Alternative in the sense different from getInstrMapping.
666  virtual InstructionMappings
667  getInstrAlternativeMappings(const MachineInstr &MI) const;
668 
669  /// Get the possible mapping for \p MI.
670  /// A mapping defines where the different operands may live and at what cost.
671  /// For instance, let us consider:
672  /// v0(16) = G_ADD <2 x i8> v1, v2
673  /// The possible mapping could be:
674  ///
675  /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
676  /// /*v2*/{(0xFFFF, VPR)}}
677  /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
678  /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
679  /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
680  ///
681  /// \note The first alternative of the returned mapping should be the
682  /// direct translation of \p MI current form.
683  ///
684  /// \post !returnedVal.empty().
685  InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
686 
687  /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
688  /// After this call \p OpdMapper.getMI() may not be valid anymore.
689  /// \p OpdMapper.getInstrMapping().getID() carries the information of
690  /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
691  /// by the various getInstrXXXMapping method.
692  ///
693  /// Therefore, getting the mapping and applying it should be kept in
694  /// sync.
695  void applyMapping(const OperandsMapper &OpdMapper) const {
696  // The only mapping we know how to handle is the default mapping.
697  if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
698  return applyDefaultMapping(OpdMapper);
699  // For other mapping, the target needs to do the right thing.
700  // If that means calling applyDefaultMapping, fine, but this
701  // must be explicitly stated.
702  applyMappingImpl(OpdMapper);
703  }
704 
705  /// Get the size in bits of \p Reg.
706  /// Utility method to get the size of any registers. Unlike
707  /// MachineRegisterInfo::getSize, the register does not need to be a
708  /// virtual register.
709  ///
710  /// \pre \p Reg != 0 (NoRegister).
711  unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
712  const TargetRegisterInfo &TRI) const;
713 
714  /// Check that information hold by this instance make sense for the
715  /// given \p TRI.
716  ///
717  /// \note This method does not check anything when assertions are disabled.
718  ///
719  /// \return True is the check was successful.
720  bool verify(const TargetRegisterInfo &TRI) const;
721 };
722 
723 inline raw_ostream &
724 operator<<(raw_ostream &OS,
725  const RegisterBankInfo::PartialMapping &PartMapping) {
726  PartMapping.print(OS);
727  return OS;
728 }
729 
730 inline raw_ostream &
731 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
732  ValMapping.print(OS);
733  return OS;
734 }
735 
736 inline raw_ostream &
737 operator<<(raw_ostream &OS,
738  const RegisterBankInfo::InstructionMapping &InstrMapping) {
739  InstrMapping.print(OS);
740  return OS;
741 }
742 
743 inline raw_ostream &
744 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
745  OpdMapper.print(OS, /*ForDebug*/ false);
746  return OS;
747 }
748 
749 /// Hashing function for PartialMapping.
750 /// It is required for the hashing of ValueMapping.
751 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
752 
753 } // end namespace llvm
754 
755 #endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
class llvm::RegisterBankInfo *void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getCost() const
Get the cost.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getNumRegBanks() const
Get the total number of register banks.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
bool isValid() const
Check if this ValueMapping is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
virtual ~RegisterBankInfo()=default
unsigned getID() const
Get the ID.
void dump() const
Print this partial mapping on dbgs() stream.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4428
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
unsigned NumRegBanks
Total number of register banks.
static const unsigned End
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const PartialMapping * end() const
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
A range adaptor for a pair of iterators.
const PartialMapping * begin() const
Iterators through the PartialMappings.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2018
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned NumBreakDowns
Number of partial mapping to break down this value.
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
IRTranslator LLVM IR MI
RegisterBankInfo()
This constructor is meaningless.
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
unsigned getNumOperands() const
Get the number of operands.
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
RegisterBank ** RegBanks
Hold the set of supported register banks.
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.