LLVM  6.0.0svn
Classes | Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::TargetRegisterInfo Class Referenceabstract

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. More...

#include "llvm/CodeGen/TargetRegisterInfo.h"

Inheritance diagram for llvm::TargetRegisterInfo:
Inheritance graph
[legend]
Collaboration diagram for llvm::TargetRegisterInfo:
Collaboration graph
[legend]

Classes

struct  RegClassInfo
 

Public Types

using regclass_iterator = const TargetRegisterClass *const *
 
using vt_iterator = const MVT::SimpleValueType *
 
- Public Types inherited from llvm::MCRegisterInfo
using regclass_iterator = const MCRegisterClass *
 

Public Member Functions

unsigned getRegSizeInBits (const TargetRegisterClass &RC) const
 Return the size in bits of a register from class RC. More...
 
unsigned getSpillSize (const TargetRegisterClass &RC) const
 Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC. More...
 
unsigned getSpillAlignment (const TargetRegisterClass &RC) const
 Return the minimum required alignment in bytes for a spill slot for a register of this class. More...
 
bool isTypeLegalForClass (const TargetRegisterClass &RC, MVT T) const
 Return true if the given TargetRegisterClass has the ValueType T. More...
 
vt_iterator legalclasstypes_begin (const TargetRegisterClass &RC) const
 Loop over all of the value types that can be represented by values in the given register class. More...
 
vt_iterator legalclasstypes_end (const TargetRegisterClass &RC) const
 
const TargetRegisterClassgetMinimalPhysRegClass (unsigned Reg, MVT VT=MVT::Other) const
 Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. More...
 
const TargetRegisterClassgetAllocatableClass (const TargetRegisterClass *RC) const
 Return the maximal subclass of the given register class that is allocatable or NULL. More...
 
BitVector getAllocatableSet (const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
 Returns a bitset indexed by register number indicating if a register is allocatable or not. More...
 
unsigned getCostPerUse (unsigned RegNo) const
 Return the additional cost of using this register instead of other registers in its class. More...
 
bool isInAllocatableClass (unsigned RegNo) const
 Return true if the register is in the allocation of any register class. More...
 
const chargetSubRegIndexName (unsigned SubIdx) const
 Return the human-readable symbolic target-specific name for the specified SubRegIndex. More...
 
LaneBitmask getSubRegIndexLaneMask (unsigned SubIdx) const
 Return a bitmask representing the parts of a register that are covered by SubIdx. More...
 
LaneBitmask getCoveringLanes () const
 The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register. More...
 
bool regsOverlap (unsigned regA, unsigned regB) const
 Returns true if the two registers are equal or alias each other. More...
 
bool hasRegUnit (unsigned Reg, unsigned RegUnit) const
 Returns true if Reg contains RegUnit. More...
 
virtual const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const =0
 Return a null-terminated list of all of the callee-saved registers on this target. More...
 
virtual const uint32_tgetCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const
 Return a mask of call-preserved registers for the given calling convention on the current function. More...
 
virtual const uint32_tgetNoPreservedMask () const
 Return a register mask that clobbers everything. More...
 
bool regmaskSubsetEqual (const uint32_t *mask0, const uint32_t *mask1) const
 Return true if all bits that are set in mask mask0 are also set in mask1. More...
 
virtual ArrayRef< const uint32_t * > getRegMasks () const =0
 Return all the call-preserved register masks defined for this target. More...
 
virtual ArrayRef< const char * > getRegMaskNames () const =0
 
virtual BitVector getReservedRegs (const MachineFunction &MF) const =0
 Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. More...
 
virtual bool isConstantPhysReg (unsigned PhysReg) const
 Returns true if PhysReg is unallocatable and constant throughout the function. More...
 
virtual bool isCallerPreservedPhysReg (unsigned PhysReg, const MachineFunction &MF) const
 Physical registers that may be modified within a function but are guaranteed to be restored before any uses. More...
 
virtual void adjustStackMapLiveOutMask (uint32_t *Mask) const
 Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored). More...
 
unsigned getMatchingSuperReg (unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
 Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More...
 
virtual const TargetRegisterClassgetMatchingSuperRegClass (const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
 Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B. More...
 
virtual bool shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
 
virtual const TargetRegisterClassgetSubClassWithSubReg (const TargetRegisterClass *RC, unsigned Idx) const
 Returns the largest legal sub-class of RC that supports the sub-register index Idx. More...
 
unsigned composeSubRegIndices (unsigned a, unsigned b) const
 Return the subregister index you get from composing two subregister indices. More...
 
LaneBitmask composeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask Mask) const
 Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first. More...
 
LaneBitmask reverseComposeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask LaneMask) const
 Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA. More...
 
const TargetRegisterClassgetCommonSuperRegClass (const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
 Find a common super-register class if it exists. More...
 
regclass_iterator regclass_begin () const
 Register class iterators. More...
 
regclass_iterator regclass_end () const
 
iterator_range< regclass_iteratorregclasses () const
 
unsigned getNumRegClasses () const
 
const TargetRegisterClassgetRegClass (unsigned i) const
 Returns the register class associated with the enumeration value. More...
 
const chargetRegClassName (const TargetRegisterClass *Class) const
 Returns the name of the register class. More...
 
const TargetRegisterClassgetCommonSubClass (const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
 Find the largest common subclass of A and B. More...
 
virtual const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const
 Returns a TargetRegisterClass used for pointer values. More...
 
virtual const TargetRegisterClassgetCrossCopyRegClass (const TargetRegisterClass *RC) const
 Returns a legal register class to copy a register in the specified class to or from. More...
 
virtual const TargetRegisterClassgetLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &) const
 Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. More...
 
virtual unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const
 Return the register pressure "high water mark" for the specific register class. More...
 
virtual unsigned getRegPressureSetScore (const MachineFunction &MF, unsigned PSetID) const
 Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another. More...
 
virtual const RegClassWeightgetRegClassWeight (const TargetRegisterClass *RC) const =0
 Get the weight in units of pressure for this register class. More...
 
virtual unsigned getRegUnitWeight (unsigned RegUnit) const =0
 Get the weight in units of pressure for this register unit. More...
 
virtual unsigned getNumRegPressureSets () const =0
 Get the number of dimensions of register pressure. More...
 
virtual const chargetRegPressureSetName (unsigned Idx) const =0
 Get the name of this register unit pressure set. More...
 
virtual unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const =0
 Get the register unit pressure limit for this dimension. More...
 
virtual const int * getRegClassPressureSets (const TargetRegisterClass *RC) const =0
 Get the dimensions of register pressure impacted by this register class. More...
 
virtual const int * getRegUnitPressureSets (unsigned RegUnit) const =0
 Get the dimensions of register pressure impacted by this register unit. More...
 
virtual bool getRegAllocationHints (unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
 Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. More...
 
virtual void updateRegAllocHint (unsigned Reg, unsigned NewReg, MachineFunction &MF) const
 A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. More...
 
virtual bool reverseLocalAssignment () const
 Allow the target to reverse allocation order of local live ranges. More...
 
virtual unsigned getCSRFirstUseCost () const
 Allow the target to override the cost of using a callee-saved register for the first time. More...
 
virtual bool requiresRegisterScavenging (const MachineFunction &MF) const
 Returns true if the target requires (and can make use of) the register scavenger. More...
 
virtual bool useFPForScavengingIndex (const MachineFunction &MF) const
 Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot. More...
 
virtual bool requiresFrameIndexScavenging (const MachineFunction &MF) const
 Returns true if the target requires post PEI scavenging of registers for materializing frame index constants. More...
 
virtual bool requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const
 Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging. More...
 
virtual bool requiresVirtualBaseRegisters (const MachineFunction &MF) const
 Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access. More...
 
virtual bool hasReservedSpillSlot (const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
 Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. More...
 
virtual bool trackLivenessAfterRegAlloc (const MachineFunction &MF) const
 Returns true if the live-ins should be tracked after register allocation. More...
 
virtual bool canRealignStack (const MachineFunction &MF) const
 True if the stack can be realigned for the target. More...
 
bool needsStackRealignment (const MachineFunction &MF) const
 True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for. More...
 
virtual int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const
 Get the offset from the referenced frame index in the instruction, if there is one. More...
 
virtual bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const
 Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. More...
 
virtual void materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const
 Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I. More...
 
virtual void resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
 Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead. More...
 
virtual bool isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const
 Determine whether a given base register plus offset immediate is encodable to resolve a frame index. More...
 
virtual bool saveScavengerRegister (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
 Spill the register so it can be used by the register scavenger. More...
 
virtual void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
 This method must be overriden to eliminate abstract frame indices from instructions which may use them. More...
 
virtual StringRef getRegAsmName (unsigned Reg) const
 Return the assembly name for Reg. More...
 
virtual bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
 Subtarget Hooks. More...
 
virtual unsigned getFrameRegister (const MachineFunction &MF) const =0
 Debug information queries. More...
 
void markSuperRegs (BitVector &RegisterSet, unsigned Reg) const
 Mark a register and all its aliases as reserved in the given set. More...
 
bool checkAllSuperRegsMarked (const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
 Returns true if for every register in the set all super registers are part of the set as well. More...
 
- Public Member Functions inherited from llvm::MCRegisterInfo
void InitMCRegisterInfo (const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
 Initialize MCRegisterInfo, called by TableGen auto-generated routines. More...
 
void mapLLVMRegsToDwarfRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
 Used to initialize LLVM register to Dwarf register number mapping. More...
 
void mapDwarfRegsToLLVMRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
 Used to initialize Dwarf register to LLVM register number mapping. More...
 
void mapLLVMRegToSEHReg (unsigned LLVMReg, int SEHReg)
 mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping. More...
 
void mapLLVMRegToCVReg (unsigned LLVMReg, int CVReg)
 
unsigned getRARegister () const
 This method should return the register where the return address can be found. More...
 
unsigned getProgramCounter () const
 Return the register which is the program counter. More...
 
const MCRegisterDescoperator[] (unsigned RegNo) const
 
const MCRegisterDescget (unsigned RegNo) const
 Provide a get method, equivalent to [], but more useful with a pointer to this object. More...
 
unsigned getSubReg (unsigned Reg, unsigned Idx) const
 Returns the physical register number of sub-register "Index" for physical register RegNo. More...
 
unsigned getMatchingSuperReg (unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
 Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More...
 
unsigned getSubRegIndex (unsigned RegNo, unsigned SubRegNo) const
 For a given register pair, return the sub-register index if the second register is a sub-register of the first. More...
 
unsigned getSubRegIdxSize (unsigned Idx) const
 Get the size of the bit range covered by a sub-register index. More...
 
unsigned getSubRegIdxOffset (unsigned Idx) const
 Get the offset of the bit range covered by a sub-register index. More...
 
const chargetName (unsigned RegNo) const
 Return the human-readable symbolic target-specific name for the specified physical register. More...
 
unsigned getNumRegs () const
 Return the number of registers this target has (useful for sizing arrays holding per register information) More...
 
unsigned getNumSubRegIndices () const
 Return the number of sub-register indices understood by the target. More...
 
unsigned getNumRegUnits () const
 Return the number of (native) register units in the target. More...
 
int getDwarfRegNum (unsigned RegNum, bool isEH) const
 Map a target register to an equivalent dwarf register number. More...
 
int getLLVMRegNum (unsigned RegNum, bool isEH) const
 Map a dwarf register back to a target register. More...
 
int getSEHRegNum (unsigned RegNum) const
 Map a target register to an equivalent SEH register number. More...
 
int getCodeViewRegNum (unsigned RegNum) const
 Map a target register to an equivalent CodeView register number. More...
 
regclass_iterator regclass_begin () const
 
regclass_iterator regclass_end () const
 
iterator_range< regclass_iteratorregclasses () const
 
unsigned getNumRegClasses () const
 
const MCRegisterClassgetRegClass (unsigned i) const
 Returns the register class associated with the enumeration value. More...
 
const chargetRegClassName (const MCRegisterClass *Class) const
 
uint16_t getEncodingValue (unsigned RegNo) const
 Returns the encoding for RegNo. More...
 
bool isSubRegister (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a sub-register of RegA. More...
 
bool isSuperRegister (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a super-register of RegA. More...
 
bool isSubRegisterEq (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a sub-register of RegA or if RegB == RegA. More...
 
bool isSuperRegisterEq (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a super-register of RegA or if RegB == RegA. More...
 
bool isSuperOrSubRegisterEq (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA. More...
 

Static Public Member Functions

static bool isStackSlot (unsigned Reg)
 isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register. More...
 
static int stackSlot2Index (unsigned Reg)
 Compute the frame index from a register value representing a stack slot. More...
 
static unsigned index2StackSlot (int FI)
 Convert a non-negative frame index to a stack slot register value. More...
 
static bool isPhysicalRegister (unsigned Reg)
 Return true if the specified register number is in the physical register namespace. More...
 
static bool isVirtualRegister (unsigned Reg)
 Return true if the specified register number is in the virtual register namespace. More...
 
static unsigned virtReg2Index (unsigned Reg)
 Convert a virtual register number to a 0-based index. More...
 
static unsigned index2VirtReg (unsigned Index)
 Convert a 0-based index to a virtual register number. More...
 
static void dumpReg (unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
 Debugging helper: dump register in human readable form to dbgs() stream. More...
 

Protected Member Functions

 TargetRegisterInfo (const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RSI, unsigned Mode=0)
 
virtual ~TargetRegisterInfo ()
 
virtual unsigned composeSubRegIndicesImpl (unsigned, unsigned) const
 Overridden by TableGen in targets that have sub-registers. More...
 
virtual LaneBitmask composeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const
 Overridden by TableGen in targets that have sub-registers. More...
 
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const
 
const RegClassInfogetRegClassInfo (const TargetRegisterClass &RC) const
 

Detailed Description

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has.

As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.

Definition at line 220 of file TargetRegisterInfo.h.

Member Typedef Documentation

◆ regclass_iterator

Definition at line 222 of file TargetRegisterInfo.h.

◆ vt_iterator

Definition at line 223 of file TargetRegisterInfo.h.

Constructor & Destructor Documentation

◆ TargetRegisterInfo()

TargetRegisterInfo::TargetRegisterInfo ( const TargetRegisterInfoDesc ID,
regclass_iterator  RegClassBegin,
regclass_iterator  RegClassEnd,
const char *const SRINames,
const LaneBitmask SRILaneMasks,
LaneBitmask  CoveringLanes,
const RegClassInfo *const  RSI,
unsigned  Mode = 0 
)
protected

Definition at line 40 of file TargetRegisterInfo.cpp.

References ~TargetRegisterInfo().

◆ ~TargetRegisterInfo()

TargetRegisterInfo::~TargetRegisterInfo ( )
protectedvirtualdefault

Referenced by TargetRegisterInfo().

Member Function Documentation

◆ adjustStackMapLiveOutMask()

virtual void llvm::TargetRegisterInfo::adjustStackMapLiveOutMask ( uint32_t Mask) const
inlinevirtual

Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).

Definition at line 523 of file TargetRegisterInfo.h.

◆ canRealignStack()

bool TargetRegisterInfo::canRealignStack ( const MachineFunction MF) const
virtual

◆ checkAllSuperRegsMarked()

bool TargetRegisterInfo::checkAllSuperRegsMarked ( const BitVector RegisterSet,
ArrayRef< MCPhysReg Exceptions = ArrayRef<MCPhysReg>() 
) const

Returns true if for every register in the set all super registers are part of the set as well.

Definition at line 62 of file TargetRegisterInfo.cpp.

References llvm::dbgs(), llvm::MCRegisterInfo::getNumRegs(), llvm::is_contained(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::PrintReg(), llvm::BitVector::set(), and llvm::BitVector::set_bits().

◆ composeSubRegIndexLaneMask()

LaneBitmask llvm::TargetRegisterInfo::composeSubRegIndexLaneMask ( unsigned  IdxA,
LaneBitmask  Mask 
) const
inline

Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first.

See also
composeSubRegIndices()

Definition at line 590 of file TargetRegisterInfo.h.

References llvm::BitmaskEnumDetail::Mask().

Referenced by definesFullReg(), and llvm::rdf::PhysicalRegisterInfo::mapTo().

◆ composeSubRegIndexLaneMaskImpl()

virtual LaneBitmask llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl ( unsigned  ,
LaneBitmask   
) const
inlineprotectedvirtual

Overridden by TableGen in targets that have sub-registers.

Definition at line 623 of file TargetRegisterInfo.h.

References llvm_unreachable.

◆ composeSubRegIndices()

unsigned llvm::TargetRegisterInfo::composeSubRegIndices ( unsigned  a,
unsigned  b 
) const
inline

Return the subregister index you get from composing two subregister indices.

The special null sub-register index composes as the identity.

If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you.

The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.

Definition at line 581 of file TargetRegisterInfo.h.

Referenced by definesFullReg(), getCommonSuperRegClass(), getRegsUsedByPHIs(), llvm::CoalescerPair::isCoalescable(), isCrossCopy(), and llvm::MachineOperand::substVirtReg().

◆ composeSubRegIndicesImpl()

virtual unsigned llvm::TargetRegisterInfo::composeSubRegIndicesImpl ( unsigned  ,
unsigned   
) const
inlineprotectedvirtual

Overridden by TableGen in targets that have sub-registers.

Definition at line 617 of file TargetRegisterInfo.h.

References llvm_unreachable.

◆ dumpReg()

LLVM_DUMP_METHOD void TargetRegisterInfo::dumpReg ( unsigned  Reg,
unsigned  SubRegIndex = 0,
const TargetRegisterInfo TRI = nullptr 
)
static

Debugging helper: dump register in human readable form to dbgs() stream.

Definition at line 430 of file TargetRegisterInfo.cpp.

References llvm::dbgs(), and llvm::PrintReg().

◆ eliminateFrameIndex()

virtual void llvm::TargetRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS = nullptr 
) const
pure virtual

This method must be overriden to eliminate abstract frame indices from instructions which may use them.

The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.

Referenced by AssignProtectedObjSet(), llvm::createNVPTXPrologEpilogPass(), and getFrameIndexOperandNum().

◆ getAllocatableClass()

const TargetRegisterClass * TargetRegisterInfo::getAllocatableClass ( const TargetRegisterClass RC) const

Return the maximal subclass of the given register class that is allocatable or NULL.

getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL.

Definition at line 147 of file TargetRegisterInfo.cpp.

References getRegClass(), llvm::TargetRegisterClass::getSubClassMask(), llvm::TargetRegisterClass::isAllocatable(), and llvm::BitMaskClassIterator::isValid().

Referenced by countOperands(), getAllocatableSet(), and regOverlapsSet().

◆ getAllocatableSet()

BitVector TargetRegisterInfo::getAllocatableSet ( const MachineFunction MF,
const TargetRegisterClass RC = nullptr 
) const

Returns a bitset indexed by register number indicating if a register is allocatable or not.

If a register class is specified, returns the subset for the class.

Definition at line 190 of file TargetRegisterInfo.cpp.

References C, llvm::BitVector::flip(), getAllocatableClass(), getAllocatableSetForRC(), llvm::MCRegisterInfo::getNumRegs(), getReservedRegs(), and regclasses().

Referenced by addLiveInRegs(), llvm::AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(), CriticalPathStep(), findTemporariesForLR(), and llvm::RegScavenger::scavengeRegister().

◆ getCalleeSavedRegs()

virtual const MCPhysReg* llvm::TargetRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
pure virtual

Return a null-terminated list of all of the callee-saved registers on this target.

The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa. Notice: This function does not take into account disabled CSRs. In most cases you will want to use instead the function getCalleeSavedRegs that is implemented in MachineRegisterInfo.

Referenced by addLiveInRegs(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::MachineRegisterInfo::disableCalleeSavedRegister(), doesModifyCalleeSavedReg(), llvm::MipsFrameLowering::estimateStackSize(), findTemporariesForLR(), llvm::MachineRegisterInfo::getCalleeSavedRegs(), and llvm::tryFoldSPUpdateIntoPushPop().

◆ getCallPreservedMask()

virtual const uint32_t* llvm::TargetRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID   
) const
inlinevirtual

Return a mask of call-preserved registers for the given calling convention on the current function.

The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call.

The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers.

Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1.

A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.

Definition at line 475 of file TargetRegisterInfo.h.

Referenced by llvm::analyzeArguments(), llvm::createRegUsageInfoCollector(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), getAbsolute(), llvm::MipsTargetLowering::getOpndList(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::LowerCall(), PrepareCall(), and llvm::FastISel::selectPatchpoint().

◆ getCommonSubClass()

const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass ( const TargetRegisterClass A,
const TargetRegisterClass B,
const MVT::SimpleValueType  SVT = MVT::SimpleValueType::Any 
) const

◆ getCommonSuperRegClass()

const TargetRegisterClass * TargetRegisterInfo::getCommonSuperRegClass ( const TargetRegisterClass RCA,
unsigned  SubA,
const TargetRegisterClass RCB,
unsigned  SubB,
unsigned PreA,
unsigned PreB 
) const

Find a common super-register class if it exists.

Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that:

  1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
  2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
  3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).

SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements.

SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.

Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class.

The function returns NULL if no register class can be found.

Definition at line 260 of file TargetRegisterInfo.cpp.

References assert(), composeSubRegIndices(), firstCommonClass(), getRegSizeInBits(), llvm::SuperRegClassIterator::isValid(), and std::swap().

Referenced by getMatchingSuperRegClass(), isCrossCopy(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().

◆ getCostPerUse()

unsigned llvm::TargetRegisterInfo::getCostPerUse ( unsigned  RegNo) const
inline

Return the additional cost of using this register instead of other registers in its class.

Definition at line 370 of file TargetRegisterInfo.h.

References llvm::TargetRegisterInfoDesc::CostPerUse.

Referenced by llvm::createGreedyRegisterAllocator(), and llvm::RegisterClassInfo::runOnMachineFunction().

◆ getCoveringLanes()

LaneBitmask llvm::TargetRegisterInfo::getCoveringLanes ( ) const
inline

The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register.

The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register.

On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions.

This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given:

Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB);

If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.

Definition at line 419 of file TargetRegisterInfo.h.

◆ getCrossCopyRegClass()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass RC) const
inlinevirtual

Returns a legal register class to copy a register in the specified class to or from.

If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.

Definition at line 715 of file TargetRegisterInfo.h.

◆ getCSRFirstUseCost()

virtual unsigned llvm::TargetRegisterInfo::getCSRFirstUseCost ( ) const
inlinevirtual

Allow the target to override the cost of using a callee-saved register for the first time.

Default value of 0 means we will use a callee-saved register if it is available.

Definition at line 825 of file TargetRegisterInfo.h.

Referenced by hasTiedDef().

◆ getFrameIndexInstrOffset()

virtual int64_t llvm::TargetRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
inlinevirtual

Get the offset from the referenced frame index in the instruction, if there is one.

Definition at line 885 of file TargetRegisterInfo.h.

Referenced by lookupCandidateBaseReg().

◆ getFrameRegister()

virtual unsigned llvm::TargetRegisterInfo::getFrameRegister ( const MachineFunction MF) const
pure virtual

◆ getLargestLegalSuperClass()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass RC,
const MachineFunction  
) const
inlinevirtual

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size.

The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.

The default implementation is very conservative and doesn't allow the register allocator to inflate register classes.

Definition at line 724 of file TargetRegisterInfo.h.

Referenced by llvm::PPCRegisterInfo::getLargestLegalSuperClass(), getNumAllocatableRegsForConstraints(), matchPair(), llvm::MachineRegisterInfo::recomputeRegClass(), and llvm::RegisterClassInfo::runOnMachineFunction().

◆ getMatchingSuperReg()

unsigned llvm::TargetRegisterInfo::getMatchingSuperReg ( unsigned  Reg,
unsigned  SubIdx,
const TargetRegisterClass RC 
) const
inline

◆ getMatchingSuperRegClass()

const TargetRegisterClass * TargetRegisterInfo::getMatchingSuperRegClass ( const TargetRegisterClass A,
const TargetRegisterClass B,
unsigned  Idx 
) const
virtual

Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.

TableGen will synthesize missing A sub-classes.

Definition at line 244 of file TargetRegisterInfo.cpp.

References assert(), firstCommonClass(), getCommonSuperRegClass(), llvm::TargetRegisterClass::getSubClassMask(), and llvm::SuperRegClassIterator::isValid().

Referenced by countOperands(), definesFullReg(), llvm::MachineInstr::getRegClassConstraintEffect(), getRegsUsedByPHIs(), isCrossCopy(), matchPair(), regOverlapsSet(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().

◆ getMinimalPhysRegClass()

const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass ( unsigned  reg,
MVT  VT = MVT::Other 
) const

Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.

getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.

Definition at line 164 of file TargetRegisterInfo.cpp.

References assert(), llvm::TargetRegisterClass::hasSubClass(), isPhysicalRegister(), isTypeLegalForClass(), llvm::MVT::Other, and regclasses().

Referenced by llvm::DwarfExpression::addMachineReg(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), CheckForPhysRegDependency(), countOperands(), CriticalPathStep(), llvm::MipsFrameLowering::estimateStackSize(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), getDwarfRegNum(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), insertCSRRestores(), insertCSRSaves(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::rdf::CopyPropagation::run(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), and llvm::PPCFrameLowering::spillCalleeSavedRegisters().

◆ getNoPreservedMask()

virtual const uint32_t* llvm::TargetRegisterInfo::getNoPreservedMask ( ) const
inlinevirtual

Return a register mask that clobbers everything.

Definition at line 482 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by llvm::MachineBasicBlock::getBeginClobberMask(), and llvm::MachineBasicBlock::getEndClobberMask().

◆ getNumRegClasses()

unsigned llvm::TargetRegisterInfo::getNumRegClasses ( ) const
inline

◆ getNumRegPressureSets()

virtual unsigned llvm::TargetRegisterInfo::getNumRegPressureSets ( ) const
pure virtual

◆ getPointerRegClass()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
inlinevirtual

Returns a TargetRegisterClass used for pointer values.

If a target supports multiple different pointer register classes, kind specifies which one is indicated.

Definition at line 706 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::IRTranslator::getAnalysisUsage(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), isOpcWithIntImmediate(), lookupCandidateBaseReg(), and writeSPToMemory().

◆ getRegAllocationHints()

bool TargetRegisterInfo::getRegAllocationHints ( unsigned  VirtReg,
ArrayRef< MCPhysReg Order,
SmallVectorImpl< MCPhysReg > &  Hints,
const MachineFunction MF,
const VirtRegMap VRM = nullptr,
const LiveRegMatrix Matrix = nullptr 
) const
virtual

Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg.

These registers are effectively moved to the front of the allocation order. If true is returned, regalloc will try to only use hints to the greatest extent possible even if it means spilling.

The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved.

The default implementation of this function can resolve target-independent hints provided to MRI::setRegAllocationHint with HintType == 0. Targets that override this function should defer to the default implementation if they have no reason to change the allocation order for VirtReg. There may be target-independent hints.

Definition at line 364 of file TargetRegisterInfo.cpp.

References assert(), llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::MachineFunction::getRegInfo(), llvm::is_contained(), isPhysicalRegister(), llvm::MachineRegisterInfo::isReserved(), isVirtualRegister(), MRI, and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

Referenced by llvm::AllocationOrder::AllocationOrder(), llvm::SystemZRegisterInfo::getRegAllocationHints(), and llvm::ARMBaseRegisterInfo::getRegAllocationHints().

◆ getRegAsmName()

virtual StringRef llvm::TargetRegisterInfo::getRegAsmName ( unsigned  Reg) const
inlinevirtual

Return the assembly name for Reg.

Definition at line 945 of file TargetRegisterInfo.h.

References getName().

Referenced by llvm::SIRegisterInfo::getRegAsmName(), and llvm::TargetLowering::getRegForInlineAsmConstraint().

◆ getRegClass()

const TargetRegisterClass* llvm::TargetRegisterInfo::getRegClass ( unsigned  i) const
inline

◆ getRegClassInfo()

const RegClassInfo& llvm::TargetRegisterInfo::getRegClassInfo ( const TargetRegisterClass RC) const
inlineprotected

Definition at line 664 of file TargetRegisterInfo.h.

References llvm::TargetRegisterClass::getID().

◆ getRegClassName()

const char* llvm::TargetRegisterInfo::getRegClassName ( const TargetRegisterClass Class) const
inline

◆ getRegClassPressureSets()

virtual const int* llvm::TargetRegisterInfo::getRegClassPressureSets ( const TargetRegisterClass RC) const
pure virtual

Get the dimensions of register pressure impacted by this register class.

Returns a -1 terminated array of pressure set IDs.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), isOperandKill(), and llvm::PSetIterator::PSetIterator().

◆ getRegClassWeight()

virtual const RegClassWeight& llvm::TargetRegisterInfo::getRegClassWeight ( const TargetRegisterClass RC) const
pure virtual

◆ getRegMaskNames()

virtual ArrayRef<const char *> llvm::TargetRegisterInfo::getRegMaskNames ( ) const
pure virtual

Referenced by llvm::MIPrinter::print().

◆ getRegMasks()

virtual ArrayRef<const uint32_t *> llvm::TargetRegisterInfo::getRegMasks ( ) const
pure virtual

Return all the call-preserved register masks defined for this target.

Referenced by llvm::rdf::PhysicalRegisterInfo::PhysicalRegisterInfo().

◆ getRegPressureLimit()

virtual unsigned llvm::TargetRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
inlinevirtual

Return the register pressure "high water mark" for the specific register class.

The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit.

Note: this is the old register pressure model that relies on a manually specified representative register class per value type.

Definition at line 737 of file TargetRegisterInfo.h.

Referenced by getNodeRegMask(), and llvm::ResourcePriorityQueue::ResourcePriorityQueue().

◆ getRegPressureSetLimit()

virtual unsigned llvm::TargetRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
pure virtual

Get the register unit pressure limit for this dimension.

This limit must be adjusted dynamically for reserved registers.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), and LoopIsOuterMostWithPredecessor().

◆ getRegPressureSetName()

virtual const char* llvm::TargetRegisterInfo::getRegPressureSetName ( unsigned  Idx) const
pure virtual

Get the name of this register unit pressure set.

Referenced by llvm::PressureDiff::dump(), and llvm::dumpRegSetPressure().

◆ getRegPressureSetScore()

virtual unsigned llvm::TargetRegisterInfo::getRegPressureSetScore ( const MachineFunction MF,
unsigned  PSetID 
) const
inlinevirtual

Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another.

The scheduler will prefer increasing the register pressure of the set which returns the largest value for this function.

Definition at line 746 of file TargetRegisterInfo.h.

References Matrix.

Referenced by tryPressure().

◆ getRegSizeInBits()

unsigned llvm::TargetRegisterInfo::getRegSizeInBits ( const TargetRegisterClass RC) const
inline

◆ getRegUnitPressureSets()

virtual const int* llvm::TargetRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit) const
pure virtual

Get the dimensions of register pressure impacted by this register unit.

Returns a -1 terminated array of pressure set IDs.

Referenced by llvm::PSetIterator::PSetIterator().

◆ getRegUnitWeight()

virtual unsigned llvm::TargetRegisterInfo::getRegUnitWeight ( unsigned  RegUnit) const
pure virtual

Get the weight in units of pressure for this register unit.

Referenced by llvm::PSetIterator::PSetIterator().

◆ getReservedRegs()

virtual BitVector llvm::TargetRegisterInfo::getReservedRegs ( const MachineFunction MF) const
pure virtual

Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g.

stack pointer, return address. A reserved register:

  • is not allocatable
  • is considered always live
  • is ignored by liveness tracking It is often necessary to reserve the super registers of a reserved register as well, to avoid them getting allocated indirectly. You may use markSuperRegs() and checkAllSuperRegsMarked() in this case.

Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::MachineRegisterInfo::freezeReservedRegs(), getAllocatableSet(), and llvm::MachineFunction::verify().

◆ getSpillAlignment()

unsigned llvm::TargetRegisterInfo::getSpillAlignment ( const TargetRegisterClass RC) const
inline

◆ getSpillSize()

unsigned llvm::TargetRegisterInfo::getSpillSize ( const TargetRegisterClass RC) const
inline

Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC.

Definition at line 320 of file TargetRegisterInfo.h.

Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), llvm::VirtRegMap::assignVirt2Phys(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), getDwarfRegNum(), getFrameIndexOperandNum(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::TargetInstrInfo::getStackSlotRange(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::isValidOffset(), llvm::X86InstrInfo::loadRegFromAddr(), llvm::ARCInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::X86InstrInfo::storeRegToAddr(), llvm::ARCInstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getSubClassWithSubReg()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getSubClassWithSubReg ( const TargetRegisterClass RC,
unsigned  Idx 
) const
inlinevirtual

Returns the largest legal sub-class of RC that supports the sub-register index Idx.

If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC.

TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode.

TableGen will synthesize missing RC sub-classes.

Definition at line 563 of file TargetRegisterInfo.h.

References assert().

Referenced by countOperands(), llvm::SplitEditor::dump(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::MachineInstr::getRegClassConstraintEffect(), and matchPair().

◆ getSubRegIndexLaneMask()

LaneBitmask llvm::TargetRegisterInfo::getSubRegIndexLaneMask ( unsigned  SubIdx) const
inline

◆ getSubRegIndexName()

const char* llvm::TargetRegisterInfo::getSubRegIndexName ( unsigned  SubIdx) const
inline

Return the human-readable symbolic target-specific name for the specified SubRegIndex.

Definition at line 381 of file TargetRegisterInfo.h.

References assert().

Referenced by isImplicitOperandIn(), llvm::MIPrinter::print(), llvm::MachineInstr::print(), and llvm::PrintReg().

◆ hasRegUnit()

bool llvm::TargetRegisterInfo::hasRegUnit ( unsigned  Reg,
unsigned  RegUnit 
) const
inline

Returns true if Reg contains RegUnit.

Definition at line 440 of file TargetRegisterInfo.h.

References llvm::MCRegisterInfo::DiffListIterator::isValid().

Referenced by matchPair(), and llvm::LiveIntervals::HMEditor::updateAllRanges().

◆ hasReservedSpillSlot()

virtual bool llvm::TargetRegisterInfo::hasReservedSpillSlot ( const MachineFunction MF,
unsigned  Reg,
int &  FrameIdx 
) const
inlinevirtual

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register.

e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after determineCalleeSaves().

Definition at line 864 of file TargetRegisterInfo.h.

Referenced by assignCalleeSavedSpillSlots().

◆ index2StackSlot()

static unsigned llvm::TargetRegisterInfo::index2StackSlot ( int  FI)
inlinestatic

Convert a non-negative frame index to a stack slot register value.

Definition at line 281 of file TargetRegisterInfo.h.

References assert().

Referenced by llvm::LiveStacks::getOrCreateInterval(), and llvm::rdf::PhysicalRegisterInfo::getRegMaskId().

◆ index2VirtReg()

static unsigned llvm::TargetRegisterInfo::index2VirtReg ( unsigned  Index)
inlinestatic

◆ isCallerPreservedPhysReg()

virtual bool llvm::TargetRegisterInfo::isCallerPreservedPhysReg ( unsigned  PhysReg,
const MachineFunction MF 
) const
inlinevirtual

Physical registers that may be modified within a function but are guaranteed to be restored before any uses.

This is useful for targets that have call sequences where a GOT register may be updated by the caller prior to a call and is guaranteed to be restored (also by the caller) after the call.

Definition at line 515 of file TargetRegisterInfo.h.

Referenced by llvm::MachineRegisterInfo::isCallerPreservedOrConstPhysReg(), and mayLoadFromGOTOrConstantPool().

◆ isConstantPhysReg()

virtual bool llvm::TargetRegisterInfo::isConstantPhysReg ( unsigned  PhysReg) const
inlinevirtual

Returns true if PhysReg is unallocatable and constant throughout the function.

Used by MachineRegisterInfo::isConstantPhysReg().

Definition at line 508 of file TargetRegisterInfo.h.

Referenced by llvm::MachineRegisterInfo::isConstantPhysReg().

◆ isFrameOffsetLegal()

virtual bool llvm::TargetRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
inlinevirtual

Determine whether a given base register plus offset immediate is encodable to resolve a frame index.

Definition at line 916 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by lookupCandidateBaseReg().

◆ isInAllocatableClass()

bool llvm::TargetRegisterInfo::isInAllocatableClass ( unsigned  RegNo) const
inline

Return true if the register is in the allocation of any register class.

Definition at line 375 of file TargetRegisterInfo.h.

References llvm::TargetRegisterInfoDesc::inAllocatableClass.

Referenced by llvm::MachineRegisterInfo::isAllocatable().

◆ isPhysicalRegister()

static bool llvm::TargetRegisterInfo::isPhysicalRegister ( unsigned  Reg)
inlinestatic

Return true if the specified register number is in the physical register namespace.

Definition at line 288 of file TargetRegisterInfo.h.

References assert().

Referenced by llvm::LiveRegUnits::accumulate(), llvm::ARMBaseInstrInfo::AddDReg(), llvm::MachineBasicBlock::addLiveIn(), llvm::DwarfExpression::addMachineReg(), addRegAndItsAliases(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), addSegmentsWithValNo(), AddSubReg(), llvm::LivePhysRegs::addUses(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::LiveRangeEdit::anyRematerializable(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::VirtRegMap::assignVirt2Phys(), biasPhysRegCopy(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::calculateDbgValueHistory(), llvm::LiveRangeCalc::calculateValues(), canCompareBeNewValueJump(), canFoldCopy(), canFoldIntoMOVCC(), canFoldIntoSelect(), canMoveInstsAcrossMemOp(), CheckForLiveRegDef(), llvm::X86InstrInfo::classifyLEAReg(), llvm::MachineInstr::clearRegisterKills(), collectDebugValues(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), countOperands(), createBBSelectReg(), definesFullReg(), llvm::InstrEmitter::EmitDbgValue(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::InstructionSelector::executeMatchTable(), llvm::HexagonBlockRanges::expandToSubRegs(), llvm::finalizeBundle(), findHoistingInsertPosAndDeps(), findOnlyInterestingUse(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::CoalescerPair::flip(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), llvm::RegScavenger::forward(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::rdf::PhysicalRegisterInfo::getAliasSet(), llvm::RegBankSelect::getAnalysisUsage(), llvm::BitTracker::MachineEvaluator::getCell(), getCopyRewriter(), getDataDeps(), getDef(), getDwarfRegNum(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterClassInfo::getLastCalleeSavedAlias(), getMappedReg(), getMinimalPhysRegClass(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), getNewValueJumpOpcode(), llvm::rdf::DataFlowGraph::getNextShadow(), getNodeRegMask(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), getRegAllocationHints(), llvm::RegisterBankInfo::getRegBank(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), getRegisterName(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::LiveVariables::HandleVirtRegDef(), llvm::VirtRegMap::hasKnownPreference(), hasTiedDef(), llvm::NVPTXAsmPrinter::ignoreLoc(), INITIALIZE_PASS(), insertPHI(), InstructionStoresToFI(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::PPCRegisterInfo::isCallerPreservedPhysReg(), llvm::CoalescerPair::isCoalescable(), llvm::MachineRegisterInfo::isConstantPhysReg(), isCopyToReg(), isCrossCopy(), llvm::HexagonInstrInfo::isDependent(), isEvenReg(), isIdenticalOp(), isKilled(), isLocalCopy(), IsSafeToMove(), isSubRegOf(), isTerminalReg(), llvm::isTriviallyDead(), isVirtualRegisterOperand(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::rdf::DataFlowGraph::makeRegRef(), matchPair(), mayLoadFromGOTOrConstantPool(), MIIsInTerminatorSequence(), MoveAndTeeForMultiUse(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::LiveIntervals::print(), llvm::ARMAsmPrinter::printOperand(), llvm::recomputeLivenessFlags(), regOverlapsSet(), llvm::LivePhysRegs::removeDefs(), removeExternalCFGEdges(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::rdf::Liveness::resetKills(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::CoalescerPair::setRegisters(), shrinkScalarCompare(), SinkingPreventsImplicitNullCheck(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::LiveDebugVariables::splitRegister(), llvm::LiveRegUnits::stepBackward(), llvm::LivePhysRegs::stepForward(), llvm::Thumb1InstrInfo::storeRegToStackSlot(), llvm::MachineInstr::substituteRegister(), llvm::MachineOperand::substPhysReg(), llvm::LiveIntervals::HMEditor::updateAllRanges(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::DwarfCompileUnit::updateSubprogramScopeDIE(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isStackSlot()

static bool llvm::TargetRegisterInfo::isStackSlot ( unsigned  Reg)
inlinestatic

isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register.

isStackSlot() returns true if Reg is in the range used for stack slots.

Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack slots, so if a variable may contains a stack slot, always check isStackSlot() first.

Definition at line 270 of file TargetRegisterInfo.h.

Referenced by isFullUndefDef(), llvm::rdf::PhysicalRegisterInfo::isRegMaskId(), and llvm::PrintReg().

◆ isTypeLegalForClass()

bool llvm::TargetRegisterInfo::isTypeLegalForClass ( const TargetRegisterClass RC,
MVT  T 
) const
inline

◆ isVirtualRegister()

static bool llvm::TargetRegisterInfo::isVirtualRegister ( unsigned  Reg)
inlinestatic

Return true if the specified register number is in the virtual register namespace.

Definition at line 295 of file TargetRegisterInfo.h.

References assert().

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::LiveVariables::addNewBlock(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), addSegmentsWithValNo(), llvm::RegisterOperands::adjustLaneLiveness(), llvm::GCNDownwardRPTracker::advanceToNext(), llvm::RegAllocBase::allocatePhysRegs(), llvm::VirtRegMap::assignVirt2Phys(), llvm::VirtRegMap::assignVirt2StackSlot(), BuildInstOrderMap(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::calculateDbgValueHistory(), canClobberPhysRegDefs(), canCombine(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), canFoldIntoSelect(), CheckForPhysRegDependency(), llvm::X86InstrInfo::classifyLEAReg(), llvm::VirtRegMap::clearVirt(), collectChangingRegs(), collectVirtualRegUses(), llvm::ScheduleDAGMILive::collectVRegUses(), llvm::HexagonBlockRanges::computeDeadMap(), computeLiveOuts(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::LiveInterval::computeSubRangeUndefs(), llvm::constrainOperandRegClass(), llvm::FastISel::constrainOperandRegClass(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyHint(), llvm::WebAssemblyInstrInfo::copyPhysReg(), countOperands(), createBBSelectReg(), llvm::createCopyConstrainDAGMutation(), llvm::createGreedyRegisterAllocator(), llvm::createHexagonHardwareLoops(), llvm::createR600ISelDag(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), definesFullReg(), doCandidateWalk(), dumpMachineInstrRangeWithSlotIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::HexagonBlockRanges::expandToSubRegs(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::SIScheduleDAGMI::fillVgprSgprCost(), findHoistingInsertPosAndDeps(), findSurvivorBackwards(), foldImmediates(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), getCallTargetRegOpnd(), llvm::BitTracker::MachineEvaluator::getCell(), llvm::RegsForValue::getCopyFromRegs(), getCopyRegClasses(), getCopyRewriter(), getDefRegMask(), getDepthOfOptCmov(), GetDummyVReg(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::R600InstrInfo::getIndirectIndexBegin(), getLanesWithProperty(), getLiveLanesAt(), getLiveRange(), getMappedReg(), llvm::MachineRegisterInfo::getMaxLaneMaskForVReg(), getOModValue(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), getOrExecSource(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::VirtRegMap::getPhys(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineRegisterInfo::getRegAllocationHint(), getRegAllocationHints(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::RegScavenger::getRegsAvailable(), getRegsUsedByPHIs(), llvm::MachineRegisterInfo::getSimpleHint(), llvm::VirtRegMap::getStackSlot(), getUnderlyingArgReg(), getUsedRegMask(), llvm::LiveVariables::getVarInfo(), GetVRegRenameMap(), llvm::LiveVariables::HandleVirtRegDef(), llvm::VirtRegMap::hasKnownPreference(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), llvm::VirtRegMap::hasPreferredPhys(), llvm::TargetInstrInfo::hasReassociableOperands(), hasTiedDef(), hasUseAfterLoop(), hasVGPROperands(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::RegPressureTracker::initLiveThru(), llvm::WebAssembly::isChild(), isCrossCopy(), isCVTAToLocalCombinationCandidate(), isDebug(), isDefBetween(), isDefInSubRange(), isEqual(), isFPR64(), isFullCopyOf(), llvm::MachineInstr::isIdenticalTo(), isImplicitOperandIn(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::R600InstrInfo::isLegalToSplitMBBAt(), isOperandKill(), isPhysicalRegCopy(), llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), isPlainlyKilled(), isRematerializable(), llvm::SIRegisterInfo::isSGPRReg(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleIf(), isSourceDefinedByImplicitDef(), isUseSafeToFold(), isVGPR(), isVirtualRegisterOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::Mips16InstrInfo::loadImmediate(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), MatchingStackOffset(), matchPair(), mayLoadFromGOTOrConstantPool(), llvm::BitTracker::RegisterCell::meet(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), needsStackFrame(), OneUseDominatesOtherUses(), llvm::AArch64InstrInfo::optimizeCondBranch(), populateCandidates(), llvm::MIPrinter::print(), llvm::MachineInstr::print(), printExtendedName(), printReg(), llvm::PrintReg(), llvm::PrintVRegOrUnit(), llvm::ARMBaseInstrInfo::produceSameValue(), profitImm(), llvm::PSetIterator::PSetIterator(), pushDepHeight(), llvm::BitTracker::MachineEvaluator::putCell(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::TargetInstrInfo::reassociateOps(), llvm::GCNUpwardRPTracker::recede(), llvm::RegPressureTracker::recede(), regIsPICBase(), regOverlapsSet(), llvm::WebAssemblyAsmPrinter::regToString(), llvm::R600SchedStrategy::releaseBottomNode(), removeCopies(), removePhis(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::LiveIntervals::repairIntervalsInRange(), reportFastISelFailure(), rescheduleCanonically(), runOnBasicBlock(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ThumbRegisterInfo::saveScavengerRegister(), scavengeFrameVirtualRegsInBlock(), llvm::RegScavenger::scavengeRegister(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::MachineRegisterInfo::setRegAllocationHint(), llvm::CoalescerPair::setRegisters(), llvm::MachineRegisterInfo::shouldTrackSubRegLiveness(), shrinkScalarCompare(), llvm::LiveIntervals::shrinkToUses(), llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::LiveDebugVariables::splitRegister(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::MachineOperand::substVirtReg(), tryChangeVGPRtoSGPRinCopy(), tryToElideArgumentCopy(), llvm::LiveIntervals::HMEditor::updateAllRanges(), updateOperand(), updatePhysDepsDownwards(), llvm::ARMBaseRegisterInfo::updateRegAllocHint(), usedAsAddr(), llvm::SIInstrInfo::usesConstantBus(), llvm::MachineTraceMetrics::Ensemble::verify(), llvm::MachineFunction::verify(), and llvm::SIInstrInfo::verifyInstruction().

◆ legalclasstypes_begin()

vt_iterator llvm::TargetRegisterInfo::legalclasstypes_begin ( const TargetRegisterClass RC) const
inline

Loop over all of the value types that can be represented by values in the given register class.

Definition at line 340 of file TargetRegisterInfo.h.

Referenced by GetRegistersForValue(), getRegTy(), llvm::TargetLoweringBase::isLegalRC(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ legalclasstypes_end()

vt_iterator llvm::TargetRegisterInfo::legalclasstypes_end ( const TargetRegisterClass RC) const
inline

Definition at line 344 of file TargetRegisterInfo.h.

References getMinimalPhysRegClass(), I, and llvm::MVT::Other.

Referenced by getRegTy().

◆ markSuperRegs()

void TargetRegisterInfo::markSuperRegs ( BitVector RegisterSet,
unsigned  Reg 
) const

Mark a register and all its aliases as reserved in the given set.

Definition at line 56 of file TargetRegisterInfo.cpp.

References llvm::MCRegisterInfo::DiffListIterator::isValid(), and llvm::BitVector::set().

◆ materializeFrameBaseRegister()

virtual void llvm::TargetRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
unsigned  BaseReg,
int  FrameIdx,
int64_t  Offset 
) const
inlinevirtual

Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I.

Definition at line 900 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by lookupCandidateBaseReg().

◆ needsFrameBaseReg()

virtual bool llvm::TargetRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
inlinevirtual

Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.

Definition at line 894 of file TargetRegisterInfo.h.

Referenced by lookupCandidateBaseReg().

◆ needsStackRealignment()

bool TargetRegisterInfo::needsStackRealignment ( const MachineFunction MF) const

◆ regclass_begin()

regclass_iterator llvm::TargetRegisterInfo::regclass_begin ( ) const
inline

Register class iterators.

Definition at line 670 of file TargetRegisterInfo.h.

◆ regclass_end()

regclass_iterator llvm::TargetRegisterInfo::regclass_end ( ) const
inline

Definition at line 671 of file TargetRegisterInfo.h.

◆ regclasses()

iterator_range<regclass_iterator> llvm::TargetRegisterInfo::regclasses ( ) const
inline

◆ regmaskSubsetEqual()

bool TargetRegisterInfo::regmaskSubsetEqual ( const uint32_t mask0,
const uint32_t mask1 
) const

Return true if all bits that are set in mask mask0 are also set in mask1.

Definition at line 419 of file TargetRegisterInfo.cpp.

References llvm::MCRegisterInfo::getNumRegs(), I, LLVM_DUMP_METHOD, and N.

◆ regsOverlap()

bool llvm::TargetRegisterInfo::regsOverlap ( unsigned  regA,
unsigned  regB 
) const
inline

◆ requiresFrameIndexReplacementScavenging()

virtual bool llvm::TargetRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction MF) const
inlinevirtual

Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging.

Definition at line 847 of file TargetRegisterInfo.h.

◆ requiresFrameIndexScavenging()

virtual bool llvm::TargetRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
inlinevirtual

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants.

Definition at line 841 of file TargetRegisterInfo.h.

◆ requiresRegisterScavenging()

virtual bool llvm::TargetRegisterInfo::requiresRegisterScavenging ( const MachineFunction MF) const
inlinevirtual

Returns true if the target requires (and can make use of) the register scavenger.

Definition at line 829 of file TargetRegisterInfo.h.

Referenced by isIrreducibleCFG().

◆ requiresVirtualBaseRegisters()

virtual bool llvm::TargetRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction MF) const
inlinevirtual

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.

Definition at line 854 of file TargetRegisterInfo.h.

◆ resolveFrameIndex()

virtual void llvm::TargetRegisterInfo::resolveFrameIndex ( MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
inlinevirtual

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.

Definition at line 909 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by lookupCandidateBaseReg().

◆ reverseComposeSubRegIndexLaneMask()

LaneBitmask llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMask ( unsigned  IdxA,
LaneBitmask  LaneMask 
) const
inline

Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA.

This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a valie lane mask (no invalid bits set) the following holds: X0 = composeSubRegIndexLaneMask(Idx, Mask) X1 = reverseComposeSubRegIndexLaneMask(Idx, X0) => X1 == Mask

Definition at line 604 of file TargetRegisterInfo.h.

References llvm::TargetRegisterClass::LaneMask.

Referenced by llvm::rdf::PhysicalRegisterInfo::mapTo().

◆ reverseComposeSubRegIndexLaneMaskImpl()

virtual LaneBitmask llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl ( unsigned  ,
LaneBitmask   
) const
inlineprotectedvirtual

Definition at line 627 of file TargetRegisterInfo.h.

References llvm_unreachable.

◆ reverseLocalAssignment()

virtual bool llvm::TargetRegisterInfo::reverseLocalAssignment ( ) const
inlinevirtual

Allow the target to reverse allocation order of local live ranges.

This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.

Definition at line 820 of file TargetRegisterInfo.h.

Referenced by llvm::createGreedyRegisterAllocator().

◆ saveScavengerRegister()

virtual bool llvm::TargetRegisterInfo::saveScavengerRegister ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock::iterator UseMI,
const TargetRegisterClass RC,
unsigned  Reg 
) const
inlinevirtual

Spill the register so it can be used by the register scavenger.

Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.

Definition at line 925 of file TargetRegisterInfo.h.

References MI.

Referenced by getFrameIndexOperandNum().

◆ shouldCoalesce()

virtual bool llvm::TargetRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC,
LiveIntervals LIS 
) const
inlinevirtual

Subtarget Hooks.

SrcRC and DstRC will be morphed into NewRC if this returns true.

Definition at line 959 of file TargetRegisterInfo.h.

◆ shouldRewriteCopySrc()

bool TargetRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass DefRC,
unsigned  DefSubReg,
const TargetRegisterClass SrcRC,
unsigned  SrcSubReg 
) const
virtual

Definition at line 354 of file TargetRegisterInfo.cpp.

References shareSameRegisterFile().

◆ stackSlot2Index()

static int llvm::TargetRegisterInfo::stackSlot2Index ( unsigned  Reg)
inlinestatic

Compute the frame index from a register value representing a stack slot.

Definition at line 275 of file TargetRegisterInfo.h.

References assert().

Referenced by llvm::rdf::PhysicalRegisterInfo::getMaskUnits(), llvm::rdf::PhysicalRegisterInfo::getRegMaskBits(), false::IntervalSorter::operator()(), and llvm::PrintReg().

◆ trackLivenessAfterRegAlloc()

virtual bool llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction MF) const
inlinevirtual

Returns true if the live-ins should be tracked after register allocation.

Definition at line 870 of file TargetRegisterInfo.h.

Referenced by llvm::BranchFolder::OptimizeFunction().

◆ updateRegAllocHint()

virtual void llvm::TargetRegisterInfo::updateRegAllocHint ( unsigned  Reg,
unsigned  NewReg,
MachineFunction MF 
) const
inlinevirtual

A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g.

coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.

Definition at line 806 of file TargetRegisterInfo.h.

◆ useFPForScavengingIndex()

virtual bool llvm::TargetRegisterInfo::useFPForScavengingIndex ( const MachineFunction MF) const
inlinevirtual

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.

Definition at line 835 of file TargetRegisterInfo.h.

Referenced by AssignProtectedObjSet().

◆ virtReg2Index()

static unsigned llvm::TargetRegisterInfo::virtReg2Index ( unsigned  Reg)
inlinestatic

The documentation for this class was generated from the following files: