LLVM  10.0.0svn
X86RegisterInfo.cpp
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1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
11 // on X86.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
34 
35 using namespace llvm;
36 
37 #define GET_REGINFO_TARGET_DESC
38 #include "X86GenRegisterInfo.inc"
39 
40 static cl::opt<bool>
41 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
42  cl::desc("Enable use of a base pointer for complex stack frames"));
43 
45  : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
46  X86_MC::getDwarfRegFlavour(TT, false),
47  X86_MC::getDwarfRegFlavour(TT, true),
48  (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
50 
51  // Cache some information.
52  Is64Bit = TT.isArch64Bit();
53  IsWin64 = Is64Bit && TT.isOSWindows();
54 
55  // Use a callee-saved register as the base pointer. These registers must
56  // not conflict with any ABI requirements. For example, in 32-bit mode PIC
57  // requires GOT in the EBX register before function calls via PLT GOT pointer.
58  if (Is64Bit) {
59  SlotSize = 8;
60  // This matches the simplified 32-bit pointer code in the data layout
61  // computation.
62  // FIXME: Should use the data layout?
63  bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
64  StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
65  FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
66  BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
67  } else {
68  SlotSize = 4;
69  StackPtr = X86::ESP;
70  FramePtr = X86::EBP;
71  BasePtr = X86::ESI;
72  }
73 }
74 
75 bool
77  // ExecutionDomainFix, BreakFalseDeps and PostRAScheduler require liveness.
78  return true;
79 }
80 
81 int
82 X86RegisterInfo::getSEHRegNum(unsigned i) const {
83  return getEncodingValue(i);
84 }
85 
86 const TargetRegisterClass *
88  unsigned Idx) const {
89  // The sub_8bit sub-register index is more constrained in 32-bit mode.
90  // It behaves just like the sub_8bit_hi index.
91  if (!Is64Bit && Idx == X86::sub_8bit)
92  Idx = X86::sub_8bit_hi;
93 
94  // Forward to TableGen's default version.
95  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
96 }
97 
98 const TargetRegisterClass *
100  const TargetRegisterClass *B,
101  unsigned SubIdx) const {
102  // The sub_8bit sub-register index is more constrained in 32-bit mode.
103  if (!Is64Bit && SubIdx == X86::sub_8bit) {
104  A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
105  if (!A)
106  return nullptr;
107  }
108  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
109 }
110 
111 const TargetRegisterClass *
113  const MachineFunction &MF) const {
114  // Don't allow super-classes of GR8_NOREX. This class is only used after
115  // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
116  // to the full GR8 register class in 64-bit mode, so we cannot allow the
117  // reigster class inflation.
118  //
119  // The GR8_NOREX class is always used in a way that won't be constrained to a
120  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
121  // full GR8 class.
122  if (RC == &X86::GR8_NOREXRegClass)
123  return RC;
124 
125  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
126 
127  const TargetRegisterClass *Super = RC;
129  do {
130  switch (Super->getID()) {
131  case X86::FR32RegClassID:
132  case X86::FR64RegClassID:
133  // If AVX-512 isn't supported we should only inflate to these classes.
134  if (!Subtarget.hasAVX512() &&
135  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
136  return Super;
137  break;
138  case X86::VR128RegClassID:
139  case X86::VR256RegClassID:
140  // If VLX isn't supported we should only inflate to these classes.
141  if (!Subtarget.hasVLX() &&
142  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
143  return Super;
144  break;
145  case X86::VR128XRegClassID:
146  case X86::VR256XRegClassID:
147  // If VLX isn't support we shouldn't inflate to these classes.
148  if (Subtarget.hasVLX() &&
149  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
150  return Super;
151  break;
152  case X86::FR32XRegClassID:
153  case X86::FR64XRegClassID:
154  // If AVX-512 isn't support we shouldn't inflate to these classes.
155  if (Subtarget.hasAVX512() &&
156  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
157  return Super;
158  break;
159  case X86::GR8RegClassID:
160  case X86::GR16RegClassID:
161  case X86::GR32RegClassID:
162  case X86::GR64RegClassID:
163  case X86::RFP32RegClassID:
164  case X86::RFP64RegClassID:
165  case X86::RFP80RegClassID:
166  case X86::VR512_0_15RegClassID:
167  case X86::VR512RegClassID:
168  // Don't return a super-class that would shrink the spill size.
169  // That can happen with the vector and float classes.
170  if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
171  return Super;
172  }
173  Super = *I++;
174  } while (Super);
175  return RC;
176 }
177 
178 const TargetRegisterClass *
180  unsigned Kind) const {
181  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
182  switch (Kind) {
183  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
184  case 0: // Normal GPRs.
185  if (Subtarget.isTarget64BitLP64())
186  return &X86::GR64RegClass;
187  // If the target is 64bit but we have been told to use 32bit addresses,
188  // we can still use 64-bit register as long as we know the high bits
189  // are zeros.
190  // Reflect that in the returned register class.
191  if (Is64Bit) {
192  // When the target also allows 64-bit frame pointer and we do have a
193  // frame, this is fine to use it for the address accesses as well.
194  const X86FrameLowering *TFI = getFrameLowering(MF);
195  return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
196  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
197  : &X86::LOW32_ADDR_ACCESSRegClass;
198  }
199  return &X86::GR32RegClass;
200  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
201  if (Subtarget.isTarget64BitLP64())
202  return &X86::GR64_NOSPRegClass;
203  // NOSP does not contain RIP, so no special case here.
204  return &X86::GR32_NOSPRegClass;
205  case 2: // NOREX GPRs.
206  if (Subtarget.isTarget64BitLP64())
207  return &X86::GR64_NOREXRegClass;
208  return &X86::GR32_NOREXRegClass;
209  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
210  if (Subtarget.isTarget64BitLP64())
211  return &X86::GR64_NOREX_NOSPRegClass;
212  // NOSP does not contain RIP, so no special case here.
213  return &X86::GR32_NOREX_NOSPRegClass;
214  case 4: // Available for tailcall (not callee-saved GPRs).
215  return getGPRsForTailCall(MF);
216  }
217 }
218 
220  unsigned DefSubReg,
221  const TargetRegisterClass *SrcRC,
222  unsigned SrcSubReg) const {
223  // Prevent rewriting a copy where the destination size is larger than the
224  // input size. See PR41619.
225  // FIXME: Should this be factored into the base implementation somehow.
226  if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
227  SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
228  return false;
229 
230  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
231  SrcRC, SrcSubReg);
232 }
233 
234 const TargetRegisterClass *
236  const Function &F = MF.getFunction();
237  if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
238  return &X86::GR64_TCW64RegClass;
239  else if (Is64Bit)
240  return &X86::GR64_TCRegClass;
241 
242  bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
243  if (hasHipeCC)
244  return &X86::GR32RegClass;
245  return &X86::GR32_TCRegClass;
246 }
247 
248 const TargetRegisterClass *
250  if (RC == &X86::CCRRegClass) {
251  if (Is64Bit)
252  return &X86::GR64RegClass;
253  else
254  return &X86::GR32RegClass;
255  }
256  return RC;
257 }
258 
259 unsigned
261  MachineFunction &MF) const {
262  const X86FrameLowering *TFI = getFrameLowering(MF);
263 
264  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
265  switch (RC->getID()) {
266  default:
267  return 0;
268  case X86::GR32RegClassID:
269  return 4 - FPDiff;
270  case X86::GR64RegClassID:
271  return 12 - FPDiff;
272  case X86::VR128RegClassID:
273  return Is64Bit ? 10 : 4;
274  case X86::VR64RegClassID:
275  return 4;
276  }
277 }
278 
279 const MCPhysReg *
281  assert(MF && "MachineFunction required");
282 
283  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
284  const Function &F = MF->getFunction();
285  bool HasSSE = Subtarget.hasSSE1();
286  bool HasAVX = Subtarget.hasAVX();
287  bool HasAVX512 = Subtarget.hasAVX512();
288  bool CallsEHReturn = MF->callsEHReturn();
289 
290  CallingConv::ID CC = F.getCallingConv();
291 
292  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
293  // convention because it has the CSR list.
294  if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
296 
297  switch (CC) {
298  case CallingConv::GHC:
299  case CallingConv::HiPE:
300  return CSR_NoRegs_SaveList;
301  case CallingConv::AnyReg:
302  if (HasAVX)
303  return CSR_64_AllRegs_AVX_SaveList;
304  return CSR_64_AllRegs_SaveList;
306  return CSR_64_RT_MostRegs_SaveList;
308  if (HasAVX)
309  return CSR_64_RT_AllRegs_AVX_SaveList;
310  return CSR_64_RT_AllRegs_SaveList;
312  if (Is64Bit)
313  return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
314  CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
315  break;
317  if (HasAVX512 && IsWin64)
318  return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
319  if (HasAVX512 && Is64Bit)
320  return CSR_64_Intel_OCL_BI_AVX512_SaveList;
321  if (HasAVX && IsWin64)
322  return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
323  if (HasAVX && Is64Bit)
324  return CSR_64_Intel_OCL_BI_AVX_SaveList;
325  if (!HasAVX && !IsWin64 && Is64Bit)
326  return CSR_64_Intel_OCL_BI_SaveList;
327  break;
328  }
329  case CallingConv::HHVM:
330  return CSR_64_HHVM_SaveList;
332  if (Is64Bit) {
333  if (IsWin64) {
334  return (HasSSE ? CSR_Win64_RegCall_SaveList :
335  CSR_Win64_RegCall_NoSSE_SaveList);
336  } else {
337  return (HasSSE ? CSR_SysV64_RegCall_SaveList :
338  CSR_SysV64_RegCall_NoSSE_SaveList);
339  }
340  } else {
341  return (HasSSE ? CSR_32_RegCall_SaveList :
342  CSR_32_RegCall_NoSSE_SaveList);
343  }
344  case CallingConv::Cold:
345  if (Is64Bit)
346  return CSR_64_MostRegs_SaveList;
347  break;
348  case CallingConv::Win64:
349  if (!HasSSE)
350  return CSR_Win64_NoSSE_SaveList;
351  return CSR_Win64_SaveList;
353  if (CallsEHReturn)
354  return CSR_64EHRet_SaveList;
355  return CSR_64_SaveList;
357  if (Is64Bit) {
358  if (HasAVX512)
359  return CSR_64_AllRegs_AVX512_SaveList;
360  if (HasAVX)
361  return CSR_64_AllRegs_AVX_SaveList;
362  if (HasSSE)
363  return CSR_64_AllRegs_SaveList;
364  return CSR_64_AllRegs_NoSSE_SaveList;
365  } else {
366  if (HasAVX512)
367  return CSR_32_AllRegs_AVX512_SaveList;
368  if (HasAVX)
369  return CSR_32_AllRegs_AVX_SaveList;
370  if (HasSSE)
371  return CSR_32_AllRegs_SSE_SaveList;
372  return CSR_32_AllRegs_SaveList;
373  }
374  default:
375  break;
376  }
377 
378  if (Is64Bit) {
379  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
380  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
381  if (IsSwiftCC)
382  return IsWin64 ? CSR_Win64_SwiftError_SaveList
383  : CSR_64_SwiftError_SaveList;
384 
385  if (IsWin64)
386  return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
387  if (CallsEHReturn)
388  return CSR_64EHRet_SaveList;
389  return CSR_64_SaveList;
390  }
391 
392  return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
393 }
394 
396  const MachineFunction *MF) const {
397  assert(MF && "Invalid MachineFunction pointer.");
399  MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
400  return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
401  return nullptr;
402 }
403 
404 const uint32_t *
406  CallingConv::ID CC) const {
407  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
408  bool HasSSE = Subtarget.hasSSE1();
409  bool HasAVX = Subtarget.hasAVX();
410  bool HasAVX512 = Subtarget.hasAVX512();
411 
412  switch (CC) {
413  case CallingConv::GHC:
414  case CallingConv::HiPE:
415  return CSR_NoRegs_RegMask;
416  case CallingConv::AnyReg:
417  if (HasAVX)
418  return CSR_64_AllRegs_AVX_RegMask;
419  return CSR_64_AllRegs_RegMask;
421  return CSR_64_RT_MostRegs_RegMask;
423  if (HasAVX)
424  return CSR_64_RT_AllRegs_AVX_RegMask;
425  return CSR_64_RT_AllRegs_RegMask;
427  if (Is64Bit)
428  return CSR_64_TLS_Darwin_RegMask;
429  break;
431  if (HasAVX512 && IsWin64)
432  return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
433  if (HasAVX512 && Is64Bit)
434  return CSR_64_Intel_OCL_BI_AVX512_RegMask;
435  if (HasAVX && IsWin64)
436  return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
437  if (HasAVX && Is64Bit)
438  return CSR_64_Intel_OCL_BI_AVX_RegMask;
439  if (!HasAVX && !IsWin64 && Is64Bit)
440  return CSR_64_Intel_OCL_BI_RegMask;
441  break;
442  }
443  case CallingConv::HHVM:
444  return CSR_64_HHVM_RegMask;
446  if (Is64Bit) {
447  if (IsWin64) {
448  return (HasSSE ? CSR_Win64_RegCall_RegMask :
449  CSR_Win64_RegCall_NoSSE_RegMask);
450  } else {
451  return (HasSSE ? CSR_SysV64_RegCall_RegMask :
452  CSR_SysV64_RegCall_NoSSE_RegMask);
453  }
454  } else {
455  return (HasSSE ? CSR_32_RegCall_RegMask :
456  CSR_32_RegCall_NoSSE_RegMask);
457  }
458  case CallingConv::Cold:
459  if (Is64Bit)
460  return CSR_64_MostRegs_RegMask;
461  break;
462  case CallingConv::Win64:
463  return CSR_Win64_RegMask;
465  return CSR_64_RegMask;
467  if (Is64Bit) {
468  if (HasAVX512)
469  return CSR_64_AllRegs_AVX512_RegMask;
470  if (HasAVX)
471  return CSR_64_AllRegs_AVX_RegMask;
472  if (HasSSE)
473  return CSR_64_AllRegs_RegMask;
474  return CSR_64_AllRegs_NoSSE_RegMask;
475  } else {
476  if (HasAVX512)
477  return CSR_32_AllRegs_AVX512_RegMask;
478  if (HasAVX)
479  return CSR_32_AllRegs_AVX_RegMask;
480  if (HasSSE)
481  return CSR_32_AllRegs_SSE_RegMask;
482  return CSR_32_AllRegs_RegMask;
483  }
484  default:
485  break;
486  }
487 
488  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
489  // callsEHReturn().
490  if (Is64Bit) {
491  const Function &F = MF.getFunction();
492  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
493  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
494  if (IsSwiftCC)
495  return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
496  return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
497  }
498 
499  return CSR_32_RegMask;
500 }
501 
502 const uint32_t*
504  return CSR_NoRegs_RegMask;
505 }
506 
508  return CSR_64_TLS_Darwin_RegMask;
509 }
510 
512  BitVector Reserved(getNumRegs());
513  const X86FrameLowering *TFI = getFrameLowering(MF);
514 
515  // Set the floating point control register as reserved.
516  Reserved.set(X86::FPCW);
517 
518  // Set the stack-pointer register and its aliases as reserved.
519  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
520  ++I)
521  Reserved.set(*I);
522 
523  // Set the Shadow Stack Pointer as reserved.
524  Reserved.set(X86::SSP);
525 
526  // Set the instruction pointer register and its aliases as reserved.
527  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
528  ++I)
529  Reserved.set(*I);
530 
531  // Set the frame-pointer register and its aliases as reserved if needed.
532  if (TFI->hasFP(MF)) {
533  for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
534  ++I)
535  Reserved.set(*I);
536  }
537 
538  // Set the base-pointer register and its aliases as reserved if needed.
539  if (hasBasePointer(MF)) {
541  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
544  "Stack realignment in presence of dynamic allocas is not supported with"
545  "this calling convention.");
546 
548  for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
549  I.isValid(); ++I)
550  Reserved.set(*I);
551  }
552 
553  // Mark the segment registers as reserved.
554  Reserved.set(X86::CS);
555  Reserved.set(X86::SS);
556  Reserved.set(X86::DS);
557  Reserved.set(X86::ES);
558  Reserved.set(X86::FS);
559  Reserved.set(X86::GS);
560 
561  // Mark the floating point stack registers as reserved.
562  for (unsigned n = 0; n != 8; ++n)
563  Reserved.set(X86::ST0 + n);
564 
565  // Reserve the registers that only exist in 64-bit mode.
566  if (!Is64Bit) {
567  // These 8-bit registers are part of the x86-64 extension even though their
568  // super-registers are old 32-bits.
569  Reserved.set(X86::SIL);
570  Reserved.set(X86::DIL);
571  Reserved.set(X86::BPL);
572  Reserved.set(X86::SPL);
573  Reserved.set(X86::SIH);
574  Reserved.set(X86::DIH);
575  Reserved.set(X86::BPH);
576  Reserved.set(X86::SPH);
577 
578  for (unsigned n = 0; n != 8; ++n) {
579  // R8, R9, ...
580  for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
581  Reserved.set(*AI);
582 
583  // XMM8, XMM9, ...
584  for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
585  Reserved.set(*AI);
586  }
587  }
588  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
589  for (unsigned n = 16; n != 32; ++n) {
590  for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
591  Reserved.set(*AI);
592  }
593  }
594 
595  assert(checkAllSuperRegsMarked(Reserved,
596  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
597  X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
598  return Reserved;
599 }
600 
602  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
603  // because the calling convention defines the EFLAGS register as NOT
604  // preserved.
605  //
606  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
607  // an assert to track this and clear the register afterwards to avoid
608  // unnecessary crashes during release builds.
609  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
610  "EFLAGS are not live-out from a patchpoint.");
611 
612  // Also clean other registers that don't need preserving (IP).
613  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
614  Mask[Reg / 32] &= ~(1U << (Reg % 32));
615 }
616 
617 //===----------------------------------------------------------------------===//
618 // Stack Frame Processing methods
619 //===----------------------------------------------------------------------===//
620 
621 static bool CantUseSP(const MachineFrameInfo &MFI) {
622  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
623 }
624 
626  const MachineFrameInfo &MFI = MF.getFrameInfo();
627 
628  if (!EnableBasePointer)
629  return false;
630 
631  // When we need stack realignment, we can't address the stack from the frame
632  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
633  // can't address variables from the stack pointer. MS inline asm can
634  // reference locals while also adjusting the stack pointer. When we can't
635  // use both the SP and the FP, we need a separate base pointer register.
636  bool CantUseFP = needsStackRealignment(MF);
637  return CantUseFP && CantUseSP(MFI);
638 }
639 
642  return false;
643 
644  const MachineFrameInfo &MFI = MF.getFrameInfo();
645  const MachineRegisterInfo *MRI = &MF.getRegInfo();
646 
647  // Stack realignment requires a frame pointer. If we already started
648  // register allocation with frame pointer elimination, it is too late now.
649  if (!MRI->canReserveReg(FramePtr))
650  return false;
651 
652  // If a base pointer is necessary. Check that it isn't too late to reserve
653  // it.
654  if (CantUseSP(MFI))
655  return MRI->canReserveReg(BasePtr);
656  return true;
657 }
658 
660  unsigned Reg, int &FrameIdx) const {
661  // Since X86 defines assignCalleeSavedSpillSlots which always return true
662  // this function neither used nor tested.
663  llvm_unreachable("Unused function on X86. Otherwise need a test case.");
664 }
665 
666 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
667 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
668 // TODO: In this case we should be really trying first to entirely eliminate
669 // this instruction which is a plain copy.
671  MachineInstr &MI = *II;
672  unsigned Opc = II->getOpcode();
673  // Check if this is a LEA of the form 'lea (%esp), %ebx'
674  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
675  MI.getOperand(2).getImm() != 1 ||
676  MI.getOperand(3).getReg() != X86::NoRegister ||
677  MI.getOperand(4).getImm() != 0 ||
678  MI.getOperand(5).getReg() != X86::NoRegister)
679  return false;
680  Register BasePtr = MI.getOperand(1).getReg();
681  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
682  // be replaced with a 32-bit operand MOV which will zero extend the upper
683  // 32-bits of the super register.
684  if (Opc == X86::LEA64_32r)
685  BasePtr = getX86SubSuperRegister(BasePtr, 32);
686  Register NewDestReg = MI.getOperand(0).getReg();
687  const X86InstrInfo *TII =
688  MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
689  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
690  MI.getOperand(1).isKill());
691  MI.eraseFromParent();
692  return true;
693 }
694 
695 void
697  int SPAdj, unsigned FIOperandNum,
698  RegScavenger *RS) const {
699  MachineInstr &MI = *II;
700  MachineFunction &MF = *MI.getParent()->getParent();
701  const X86FrameLowering *TFI = getFrameLowering(MF);
702  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
703 
704  // Determine base register and offset.
705  int FIOffset;
706  unsigned BasePtr;
707  if (MI.isReturn()) {
708  assert((!needsStackRealignment(MF) ||
709  MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
710  "Return instruction can only reference SP relative frame objects");
711  FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
712  } else {
713  FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
714  }
715 
716  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
717  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
718  // offset is from the traditional base pointer location. On 64-bit, the
719  // offset is from the SP at the end of the prologue, not the FP location. This
720  // matches the behavior of llvm.frameaddress.
721  unsigned Opc = MI.getOpcode();
722  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
723  MachineOperand &FI = MI.getOperand(FIOperandNum);
724  FI.ChangeToImmediate(FIOffset);
725  return;
726  }
727 
728  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
729  // register as source operand, semantic is the same and destination is
730  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
731  // Don't change BasePtr since it is used later for stack adjustment.
732  Register MachineBasePtr = BasePtr;
733  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
734  MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
735 
736  // This must be part of a four operand memory reference. Replace the
737  // FrameIndex with base register. Add an offset to the offset.
738  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
739 
740  if (BasePtr == StackPtr)
741  FIOffset += SPAdj;
742 
743  // The frame index format for stackmaps and patchpoints is different from the
744  // X86 format. It only has a FI and an offset.
745  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
746  assert(BasePtr == FramePtr && "Expected the FP as base register");
747  int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
748  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
749  return;
750  }
751 
752  if (MI.getOperand(FIOperandNum+3).isImm()) {
753  // Offset is a 32-bit integer.
754  int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
755  int Offset = FIOffset + Imm;
756  assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
757  "Requesting 64-bit offset in 32-bit immediate!");
758  if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
759  MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
760  } else {
761  // Offset is symbolic. This is extremely rare.
762  uint64_t Offset = FIOffset +
763  (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
764  MI.getOperand(FIOperandNum + 3).setOffset(Offset);
765  }
766 }
767 
769  const X86FrameLowering *TFI = getFrameLowering(MF);
770  return TFI->hasFP(MF) ? FramePtr : StackPtr;
771 }
772 
773 unsigned
775  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
776  Register FrameReg = getFrameRegister(MF);
777  if (Subtarget.isTarget64BitILP32())
778  FrameReg = getX86SubSuperRegister(FrameReg, 32);
779  return FrameReg;
780 }
781 
782 unsigned
784  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
785  Register StackReg = getStackRegister();
786  if (Subtarget.isTarget64BitILP32())
787  StackReg = getX86SubSuperRegister(StackReg, 32);
788  return StackReg;
789 }
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:143
bool hasAVX() const
Definition: X86Subtarget.h:581
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:397
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
unsigned Reg
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
F(f)
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
block Block Frequency true
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
return AArch64::GPR64RegClass contains(Reg)
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:561
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
bool hasVLX() const
Definition: X86Subtarget.h:681
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:173
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:625
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:497
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const uint32_t * getNoPreservedMask() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:139
MCRegAliasIterator enumerates all registers aliasing Reg.
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
Definition: CallingConv.h:163
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int getSEHRegNum(unsigned i) const
void setOffset(int64_t Offset)
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Register getFrameRegister(const MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:555
bool callsEHReturn() const
const uint32_t * getDarwinTLSCallPreservedMask() const
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
int64_t getOffset() const
Return the offset from the symbol in this operand.
#define I(x, y, z)
Definition: MD5.cpp:58
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
bool canRealignStack(const MachineFunction &MF) const override
static bool CantUseSP(const MachineFrameInfo &MFI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasSSE1() const
Definition: X86Subtarget.h:575
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:203
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool hasAVX512() const
Definition: X86Subtarget.h:583
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:153
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Register getStackRegister() const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Register getBaseRegister() const