41#define GET_REGINFO_TARGET_DESC
42#include "X86GenRegisterInfo.inc"
46 cl::desc(
"Enable use of a base pointer for complex stack frames"));
50 X86_MC::getDwarfRegFlavour(TT,
false),
51 X86_MC::getDwarfRegFlavour(TT,
true),
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56 Is64Bit = TT.isArch64Bit();
57 IsWin64 = Is64Bit && TT.isOSWindows();
67 bool Use64BitReg = !TT.isX32();
68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
69 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
81 return getEncodingValue(i);
89 if (!Is64Bit &&
Idx == X86::sub_8bit)
90 Idx = X86::sub_8bit_hi;
93 return X86GenRegisterInfo::getSubClassWithSubReg(RC,
Idx);
99 unsigned SubIdx)
const {
101 if (!Is64Bit && SubIdx == X86::sub_8bit) {
102 A = X86GenRegisterInfo::getSubClassWithSubReg(
A, X86::sub_8bit_hi);
106 return X86GenRegisterInfo::getMatchingSuperRegClass(
A,
B, SubIdx);
120 if (RC == &X86::GR8_NOREXRegClass)
128 switch (Super->getID()) {
129 case X86::FR32RegClassID:
130 case X86::FR64RegClassID:
133 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
136 case X86::VR128RegClassID:
137 case X86::VR256RegClassID:
139 if (!Subtarget.hasVLX() &&
140 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
143 case X86::VR128XRegClassID:
144 case X86::VR256XRegClassID:
146 if (Subtarget.hasVLX() &&
147 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
150 case X86::FR32XRegClassID:
151 case X86::FR64XRegClassID:
154 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
157 case X86::GR8RegClassID:
158 case X86::GR16RegClassID:
159 case X86::GR32RegClassID:
160 case X86::GR64RegClassID:
161 case X86::GR8_NOREX2RegClassID:
162 case X86::GR16_NOREX2RegClassID:
163 case X86::GR32_NOREX2RegClassID:
164 case X86::GR64_NOREX2RegClassID:
165 case X86::RFP32RegClassID:
166 case X86::RFP64RegClassID:
167 case X86::RFP80RegClassID:
168 case X86::VR512_0_15RegClassID:
169 case X86::VR512RegClassID:
172 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
182 unsigned Kind)
const {
188 return &X86::GR64RegClass;
198 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
199 : &X86::LOW32_ADDR_ACCESSRegClass;
201 return &X86::GR32RegClass;
204 return &X86::GR64_NOSPRegClass;
206 return &X86::GR32_NOSPRegClass;
209 return &X86::GR64_NOREXRegClass;
210 return &X86::GR32_NOREXRegClass;
213 return &X86::GR64_NOREX_NOSPRegClass;
215 return &X86::GR32_NOREX_NOSPRegClass;
224 unsigned SrcSubReg)
const {
229 SrcRC->
hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
240 return &X86::GR64_TCW64RegClass;
242 return &X86::GR64_TCRegClass;
246 return &X86::GR32RegClass;
247 return &X86::GR32_TCRegClass;
252 if (RC == &X86::CCRRegClass) {
254 return &X86::GR64RegClass;
256 return &X86::GR32RegClass;
266 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
267 switch (RC->
getID()) {
270 case X86::GR32RegClassID:
272 case X86::GR64RegClassID:
274 case X86::VR128RegClassID:
275 return Is64Bit ? 10 : 4;
276 case X86::VR64RegClassID:
283 assert(MF &&
"MachineFunction required");
287 bool HasSSE = Subtarget.
hasSSE1();
288 bool HasAVX = Subtarget.
hasAVX();
302 return CSR_NoRegs_SaveList;
307 return CSR_NoRegs_SaveList;
310 return CSR_64_AllRegs_AVX_SaveList;
311 return CSR_64_AllRegs_SaveList;
313 return IsWin64 ? CSR_Win64_RT_MostRegs_SaveList
314 : CSR_64_RT_MostRegs_SaveList;
317 return CSR_64_RT_AllRegs_AVX_SaveList;
318 return CSR_64_RT_AllRegs_SaveList;
320 return CSR_64_NoneRegs_SaveList;
324 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
327 if (HasAVX512 && IsWin64)
328 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
329 if (HasAVX512 && Is64Bit)
330 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
331 if (HasAVX && IsWin64)
332 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
333 if (HasAVX && Is64Bit)
334 return CSR_64_Intel_OCL_BI_AVX_SaveList;
335 if (!HasAVX && !IsWin64 && Is64Bit)
336 return CSR_64_Intel_OCL_BI_SaveList;
342 return (HasSSE ? CSR_Win64_RegCall_SaveList :
343 CSR_Win64_RegCall_NoSSE_SaveList);
345 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
346 CSR_SysV64_RegCall_NoSSE_SaveList);
349 return (HasSSE ? CSR_32_RegCall_SaveList :
350 CSR_32_RegCall_NoSSE_SaveList);
353 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
354 return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
355 : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
358 return CSR_64_MostRegs_SaveList;
362 return CSR_Win64_NoSSE_SaveList;
363 return CSR_Win64_SaveList;
366 return CSR_32_SaveList;
367 return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList;
370 return CSR_64EHRet_SaveList;
371 return CSR_64_SaveList;
375 return CSR_64_AllRegs_AVX512_SaveList;
377 return CSR_64_AllRegs_AVX_SaveList;
379 return CSR_64_AllRegs_SaveList;
380 return CSR_64_AllRegs_NoSSE_SaveList;
383 return CSR_32_AllRegs_AVX512_SaveList;
385 return CSR_32_AllRegs_AVX_SaveList;
387 return CSR_32_AllRegs_SSE_SaveList;
388 return CSR_32_AllRegs_SaveList;
396 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
398 return IsWin64 ? CSR_Win64_SwiftError_SaveList
399 : CSR_64_SwiftError_SaveList;
402 return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
404 return CSR_64EHRet_SaveList;
405 return CSR_64_SaveList;
408 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
413 assert(MF &&
"Invalid MachineFunction pointer.");
416 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
424 bool HasSSE = Subtarget.
hasSSE1();
425 bool HasAVX = Subtarget.
hasAVX();
431 return CSR_NoRegs_RegMask;
434 return CSR_64_AllRegs_AVX_RegMask;
435 return CSR_64_AllRegs_RegMask;
437 return IsWin64 ? CSR_Win64_RT_MostRegs_RegMask : CSR_64_RT_MostRegs_RegMask;
440 return CSR_64_RT_AllRegs_AVX_RegMask;
441 return CSR_64_RT_AllRegs_RegMask;
443 return CSR_64_NoneRegs_RegMask;
446 return CSR_64_TLS_Darwin_RegMask;
449 if (HasAVX512 && IsWin64)
450 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
451 if (HasAVX512 && Is64Bit)
452 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
453 if (HasAVX && IsWin64)
454 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
455 if (HasAVX && Is64Bit)
456 return CSR_64_Intel_OCL_BI_AVX_RegMask;
457 if (!HasAVX && !IsWin64 && Is64Bit)
458 return CSR_64_Intel_OCL_BI_RegMask;
464 return (HasSSE ? CSR_Win64_RegCall_RegMask :
465 CSR_Win64_RegCall_NoSSE_RegMask);
467 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
468 CSR_SysV64_RegCall_NoSSE_RegMask);
471 return (HasSSE ? CSR_32_RegCall_RegMask :
472 CSR_32_RegCall_NoSSE_RegMask);
475 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
476 return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
477 : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
480 return CSR_64_MostRegs_RegMask;
483 return CSR_Win64_RegMask;
486 return CSR_32_RegMask;
487 return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask;
489 return CSR_64_RegMask;
493 return CSR_64_AllRegs_AVX512_RegMask;
495 return CSR_64_AllRegs_AVX_RegMask;
497 return CSR_64_AllRegs_RegMask;
498 return CSR_64_AllRegs_NoSSE_RegMask;
501 return CSR_32_AllRegs_AVX512_RegMask;
503 return CSR_32_AllRegs_AVX_RegMask;
505 return CSR_32_AllRegs_SSE_RegMask;
506 return CSR_32_AllRegs_RegMask;
517 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
519 return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
521 return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
524 return CSR_32_RegMask;
529 return CSR_NoRegs_RegMask;
533 return CSR_64_TLS_Darwin_RegMask;
561 if (TFI->
hasFP(MF)) {
572 "Stack realignment in presence of dynamic allocas is not supported with"
573 "this calling convention.");
589 for (
unsigned n = 0; n != 8; ++n)
605 for (
unsigned n = 0; n != 8; ++n) {
616 for (
unsigned n = 0; n != 16; ++n) {
625 Reserved.set(X86::R16, X86::R31WH + 1);
635 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
636 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
652 assert((X86::R15WH + 1 == X86 ::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
653 (X86::K6_K7 + 1 == X86::TMMCFG) && (X86::TMM7 + 1 == X86::R16) &&
654 (X86::R31WH + 1 == X86::NUM_TARGET_REGS) &&
655 "Register number may be incorrect");
659 return X86::NUM_TARGET_REGS;
661 return X86::TMM7 + 1;
663 return X86::K6_K7 + 1;
665 return X86::YMM15 + 1;
666 return X86::R15WH + 1;
674 return TRI.isSuperOrSubRegisterEq(RegA, RegB);
680 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }) ||
681 (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
690 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }))
695 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }))
700 X86::XMM3, X86::XMM4, X86::XMM5,
701 X86::XMM6, X86::XMM7},
702 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }))
705 return X86GenRegisterInfo::isArgumentRegister(MF, Reg);
714 if (
TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg))
719 if (TFI.
hasFP(MF) &&
TRI.isSuperOrSubRegisterEq(X86::RBP, PhysReg))
722 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
726 return RC->
getID() == X86::TILERegClassID;
737 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
738 "EFLAGS are not live-out from a patchpoint.");
741 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
742 Mask[Reg / 32] &= ~(1U << (Reg % 32));
773 bool CantUseFP = hasStackRealignment(MF);
786 if (!
MRI->canReserveReg(FramePtr))
792 return MRI->canReserveReg(BasePtr);
809 unsigned Opc = II->getOpcode();
811 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
812 MI.getOperand(2).getImm() != 1 ||
813 MI.getOperand(3).getReg() != X86::NoRegister ||
814 MI.getOperand(4).getImm() != 0 ||
815 MI.getOperand(5).getReg() != X86::NoRegister)
821 if (Opc == X86::LEA64_32r)
823 Register NewDestReg =
MI.getOperand(0).getReg();
825 MI.getParent()->getParent()->getSubtarget<
X86Subtarget>().getInstrInfo();
827 MI.getOperand(1).isKill());
828 MI.eraseFromParent();
833 switch (
MI.getOpcode()) {
835 case X86::CLEANUPRET:
844 unsigned FIOperandNum,
846 int FIOffset)
const {
848 unsigned Opc =
MI.getOpcode();
849 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
855 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg,
false);
859 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
860 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
861 int64_t
Offset =
MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
862 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
866 if (
MI.getOperand(FIOperandNum + 3).isImm()) {
868 int Imm = (int)(
MI.getOperand(FIOperandNum + 3).getImm());
869 int Offset = FIOffset + Imm;
870 assert((!Is64Bit || isInt<32>((
long long)FIOffset + Imm)) &&
871 "Requesting 64-bit offset in 32-bit immediate!");
873 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(
Offset);
877 FIOffset + (
uint64_t)
MI.getOperand(FIOperandNum + 3).getOffset();
878 MI.getOperand(FIOperandNum + 3).setOffset(
Offset);
884 int SPAdj,
unsigned FIOperandNum,
893 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
899 assert((!hasStackRealignment(MF) ||
901 "Return instruction can only reference SP relative frame objects");
915 unsigned Opc =
MI.getOpcode();
916 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
927 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
932 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr,
false);
934 if (BasePtr == StackPtr)
939 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
940 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
941 int64_t
Offset =
MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
942 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
946 if (
MI.getOperand(FIOperandNum+3).isImm()) {
948 int Imm = (int)(
MI.getOperand(FIOperandNum + 3).getImm());
949 int Offset = FIOffset + Imm;
950 assert((!Is64Bit || isInt<32>((
long long)FIOffset + Imm)) &&
951 "Requesting 64-bit offset in 32-bit immediate!");
953 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(
Offset);
957 (
uint64_t)
MI.getOperand(FIOperandNum+3).getOffset();
958 MI.getOperand(FIOperandNum + 3).setOffset(
Offset);
974 switch (
MBBI->getOpcode()) {
977 case TargetOpcode::PATCHABLE_RET:
983 case X86::TCRETURNdi:
984 case X86::TCRETURNri:
985 case X86::TCRETURNmi:
986 case X86::TCRETURNdi64:
987 case X86::TCRETURNri64:
988 case X86::TCRETURNmi64:
990 case X86::EH_RETURN64: {
993 if (!MO.isReg() || MO.isDef())
1002 for (
auto CS : AvailableRegs)
1003 if (!
Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
1013 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
1041 unsigned OpCode =
MI->getOpcode();
1047 Register SrcReg =
MI->getOperand(1).getReg();
1053 case X86::PTILELOADDV:
1054 case X86::PTILELOADDT1V:
1055 case X86::PTDPBSSDV:
1056 case X86::PTDPBSUDV:
1057 case X86::PTDPBUSDV:
1058 case X86::PTDPBUUDV:
1059 case X86::PTILEZEROV:
1060 case X86::PTDPBF16PSV:
1061 case X86::PTDPFP16PSV:
1062 case X86::PTCMMIMFP16PSV:
1063 case X86::PTCMMRLFP16PSV:
1081 VirtReg, Order, Hints, MF, VRM,
Matrix);
1084 if (
ID != X86::TILERegClassID)
1085 return BaseImplRetVal;
1095 if (PhysShape == VirtShape)
1102 for (
auto Hint : CopyHints) {
1108 !
MRI->isReserved(PhysReg))
1112#define DEBUG_TYPE "tile-hint"
1114 dbgs() <<
"Hints for virtual register " <<
format_hex(VirtReg, 8) <<
"\n";
1115 for (
auto Hint : Hints) {
1116 dbgs() <<
"tmm" << Hint <<
",";
unsigned const MachineRegisterInfo * MRI
static bool isFuncletReturnInstr(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Rewrite Partial Register Uses
const HexagonInstrInfo * TII
static cl::opt< bool > EnableBasePointer("m68k-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
static bool CantUseSP(const MachineFrameInfo &MFI)
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, const MachineRegisterInfo *MRI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
static constexpr unsigned NoRegister
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool callsEHReturn() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static StackOffset getFixed(int64_t Fixed)
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Triple - Helper class for working with autoconf configuration names.
bool hasShape(Register virtReg) const
ShapeT getShape(Register virtReg) const
void assignVirt2Shape(Register virtReg, ShapeT shape)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool hasPreallocatedCall() const
MachineInstr * getStackPtrSaveMI() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.
bool canRealignStack(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
bool shouldRealignStack(const MachineFunction &MF) const override
unsigned getNumSupportedRegs(const MachineFunction &MF) const override
Return the number of registers for the function.
Register getFrameRegister(const MachineFunction &MF) const override
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
const uint32_t * getDarwinTLSCallPreservedMask() const
bool isTileRegisterClass(const TargetRegisterClass *RC) const
Return true if it is tile register class.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
isArgumentReg - Returns true if Reg can be used as an argument to a function.
Register getStackRegister() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
int getSEHRegNum(unsigned i) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
X86RegisterInfo(const Triple &TT)
Register getBaseRegister() const
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned FIOperandNum, Register BaseReg, int FIOffset) const
const uint32_t * getNoPreservedMask() const override
bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const override
Returns true if PhysReg is a fixed register.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const X86TargetLowering * getTargetLowering() const override
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
@ HiPE
Used by the High-Performance Erlang Compiler (HiPE).
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
@ PreserveMost
Used for runtime calls that preserves most registers.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ CXX_FAST_TLS
Used for access functions.
@ X86_INTR
x86 hardware interrupt context.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ Intel_OCL_BI
Used for Intel OpenCL built-ins.
@ PreserveNone
Used for runtime calls that preserves none general registers.
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
@ GRAAL
Used by GraalVM. Two additional registers are reserved.
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.