LLVM  7.0.0svn
X86RegisterInfo.cpp
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1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
35 
36 using namespace llvm;
37 
38 #define GET_REGINFO_TARGET_DESC
39 #include "X86GenRegisterInfo.inc"
40 
41 static cl::opt<bool>
42 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
43  cl::desc("Enable use of a base pointer for complex stack frames"));
44 
46  : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
47  X86_MC::getDwarfRegFlavour(TT, false),
48  X86_MC::getDwarfRegFlavour(TT, true),
49  (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
51 
52  // Cache some information.
53  Is64Bit = TT.isArch64Bit();
54  IsWin64 = Is64Bit && TT.isOSWindows();
55 
56  // Use a callee-saved register as the base pointer. These registers must
57  // not conflict with any ABI requirements. For example, in 32-bit mode PIC
58  // requires GOT in the EBX register before function calls via PLT GOT pointer.
59  if (Is64Bit) {
60  SlotSize = 8;
61  // This matches the simplified 32-bit pointer code in the data layout
62  // computation.
63  // FIXME: Should use the data layout?
64  bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
65  StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
66  FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
67  BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
68  } else {
69  SlotSize = 4;
70  StackPtr = X86::ESP;
71  FramePtr = X86::EBP;
72  BasePtr = X86::ESI;
73  }
74 }
75 
76 bool
78  // ExecutionDepsFixer and PostRAScheduler require liveness.
79  return true;
80 }
81 
82 int
83 X86RegisterInfo::getSEHRegNum(unsigned i) const {
84  return getEncodingValue(i);
85 }
86 
87 const TargetRegisterClass *
89  unsigned Idx) const {
90  // The sub_8bit sub-register index is more constrained in 32-bit mode.
91  // It behaves just like the sub_8bit_hi index.
92  if (!Is64Bit && Idx == X86::sub_8bit)
93  Idx = X86::sub_8bit_hi;
94 
95  // Forward to TableGen's default version.
96  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
97 }
98 
99 const TargetRegisterClass *
101  const TargetRegisterClass *B,
102  unsigned SubIdx) const {
103  // The sub_8bit sub-register index is more constrained in 32-bit mode.
104  if (!Is64Bit && SubIdx == X86::sub_8bit) {
105  A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
106  if (!A)
107  return nullptr;
108  }
109  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
110 }
111 
112 const TargetRegisterClass *
114  const MachineFunction &MF) const {
115  // Don't allow super-classes of GR8_NOREX. This class is only used after
116  // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
117  // to the full GR8 register class in 64-bit mode, so we cannot allow the
118  // reigster class inflation.
119  //
120  // The GR8_NOREX class is always used in a way that won't be constrained to a
121  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
122  // full GR8 class.
123  if (RC == &X86::GR8_NOREXRegClass)
124  return RC;
125 
126  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
127 
128  const TargetRegisterClass *Super = RC;
130  do {
131  switch (Super->getID()) {
132  case X86::FR32RegClassID:
133  case X86::FR64RegClassID:
134  // If AVX-512 isn't supported we should only inflate to these classes.
135  if (!Subtarget.hasAVX512() &&
136  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
137  return Super;
138  break;
139  case X86::VR128RegClassID:
140  case X86::VR256RegClassID:
141  // If VLX isn't supported we should only inflate to these classes.
142  if (!Subtarget.hasVLX() &&
143  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
144  return Super;
145  break;
146  case X86::VR128XRegClassID:
147  case X86::VR256XRegClassID:
148  // If VLX isn't support we shouldn't inflate to these classes.
149  if (Subtarget.hasVLX() &&
150  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
151  return Super;
152  break;
153  case X86::FR32XRegClassID:
154  case X86::FR64XRegClassID:
155  // If AVX-512 isn't support we shouldn't inflate to these classes.
156  if (Subtarget.hasAVX512() &&
157  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
158  return Super;
159  break;
160  case X86::GR8RegClassID:
161  case X86::GR16RegClassID:
162  case X86::GR32RegClassID:
163  case X86::GR64RegClassID:
164  case X86::RFP32RegClassID:
165  case X86::RFP64RegClassID:
166  case X86::RFP80RegClassID:
167  case X86::VR512RegClassID:
168  // Don't return a super-class that would shrink the spill size.
169  // That can happen with the vector and float classes.
170  if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
171  return Super;
172  }
173  Super = *I++;
174  } while (Super);
175  return RC;
176 }
177 
178 const TargetRegisterClass *
180  unsigned Kind) const {
181  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
182  switch (Kind) {
183  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
184  case 0: // Normal GPRs.
185  if (Subtarget.isTarget64BitLP64())
186  return &X86::GR64RegClass;
187  // If the target is 64bit but we have been told to use 32bit addresses,
188  // we can still use 64-bit register as long as we know the high bits
189  // are zeros.
190  // Reflect that in the returned register class.
191  if (Is64Bit) {
192  // When the target also allows 64-bit frame pointer and we do have a
193  // frame, this is fine to use it for the address accesses as well.
194  const X86FrameLowering *TFI = getFrameLowering(MF);
195  return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
196  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
197  : &X86::LOW32_ADDR_ACCESSRegClass;
198  }
199  return &X86::GR32RegClass;
200  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
201  if (Subtarget.isTarget64BitLP64())
202  return &X86::GR64_NOSPRegClass;
203  // NOSP does not contain RIP, so no special case here.
204  return &X86::GR32_NOSPRegClass;
205  case 2: // NOREX GPRs.
206  if (Subtarget.isTarget64BitLP64())
207  return &X86::GR64_NOREXRegClass;
208  return &X86::GR32_NOREXRegClass;
209  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
210  if (Subtarget.isTarget64BitLP64())
211  return &X86::GR64_NOREX_NOSPRegClass;
212  // NOSP does not contain RIP, so no special case here.
213  return &X86::GR32_NOREX_NOSPRegClass;
214  case 4: // Available for tailcall (not callee-saved GPRs).
215  return getGPRsForTailCall(MF);
216  }
217 }
218 
219 const TargetRegisterClass *
221  const Function &F = MF.getFunction();
222  if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
223  return &X86::GR64_TCW64RegClass;
224  else if (Is64Bit)
225  return &X86::GR64_TCRegClass;
226 
227  bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
228  if (hasHipeCC)
229  return &X86::GR32RegClass;
230  return &X86::GR32_TCRegClass;
231 }
232 
233 const TargetRegisterClass *
235  if (RC == &X86::CCRRegClass) {
236  if (Is64Bit)
237  return &X86::GR64RegClass;
238  else
239  return &X86::GR32RegClass;
240  }
241  return RC;
242 }
243 
244 unsigned
246  MachineFunction &MF) const {
247  const X86FrameLowering *TFI = getFrameLowering(MF);
248 
249  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
250  switch (RC->getID()) {
251  default:
252  return 0;
253  case X86::GR32RegClassID:
254  return 4 - FPDiff;
255  case X86::GR64RegClassID:
256  return 12 - FPDiff;
257  case X86::VR128RegClassID:
258  return Is64Bit ? 10 : 4;
259  case X86::VR64RegClassID:
260  return 4;
261  }
262 }
263 
264 const MCPhysReg *
266  assert(MF && "MachineFunction required");
267 
268  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
269  const Function &F = MF->getFunction();
270  bool HasSSE = Subtarget.hasSSE1();
271  bool HasAVX = Subtarget.hasAVX();
272  bool HasAVX512 = Subtarget.hasAVX512();
273  bool CallsEHReturn = MF->callsEHReturn();
274 
275  CallingConv::ID CC = F.getCallingConv();
276 
277  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
278  // convention because it has the CSR list.
279  if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
281 
282  switch (CC) {
283  case CallingConv::GHC:
284  case CallingConv::HiPE:
285  return CSR_NoRegs_SaveList;
286  case CallingConv::AnyReg:
287  if (HasAVX)
288  return CSR_64_AllRegs_AVX_SaveList;
289  return CSR_64_AllRegs_SaveList;
291  return CSR_64_RT_MostRegs_SaveList;
293  if (HasAVX)
294  return CSR_64_RT_AllRegs_AVX_SaveList;
295  return CSR_64_RT_AllRegs_SaveList;
297  if (Is64Bit)
298  return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
299  CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
300  break;
302  if (HasAVX512 && IsWin64)
303  return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
304  if (HasAVX512 && Is64Bit)
305  return CSR_64_Intel_OCL_BI_AVX512_SaveList;
306  if (HasAVX && IsWin64)
307  return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
308  if (HasAVX && Is64Bit)
309  return CSR_64_Intel_OCL_BI_AVX_SaveList;
310  if (!HasAVX && !IsWin64 && Is64Bit)
311  return CSR_64_Intel_OCL_BI_SaveList;
312  break;
313  }
314  case CallingConv::HHVM:
315  return CSR_64_HHVM_SaveList;
317  if (Is64Bit) {
318  if (IsWin64) {
319  return (HasSSE ? CSR_Win64_RegCall_SaveList :
320  CSR_Win64_RegCall_NoSSE_SaveList);
321  } else {
322  return (HasSSE ? CSR_SysV64_RegCall_SaveList :
323  CSR_SysV64_RegCall_NoSSE_SaveList);
324  }
325  } else {
326  return (HasSSE ? CSR_32_RegCall_SaveList :
327  CSR_32_RegCall_NoSSE_SaveList);
328  }
329  case CallingConv::Cold:
330  if (Is64Bit)
331  return CSR_64_MostRegs_SaveList;
332  break;
333  case CallingConv::Win64:
334  if (!HasSSE)
335  return CSR_Win64_NoSSE_SaveList;
336  return CSR_Win64_SaveList;
338  if (CallsEHReturn)
339  return CSR_64EHRet_SaveList;
340  return CSR_64_SaveList;
342  if (Is64Bit) {
343  if (HasAVX512)
344  return CSR_64_AllRegs_AVX512_SaveList;
345  if (HasAVX)
346  return CSR_64_AllRegs_AVX_SaveList;
347  if (HasSSE)
348  return CSR_64_AllRegs_SaveList;
349  return CSR_64_AllRegs_NoSSE_SaveList;
350  } else {
351  if (HasAVX512)
352  return CSR_32_AllRegs_AVX512_SaveList;
353  if (HasAVX)
354  return CSR_32_AllRegs_AVX_SaveList;
355  if (HasSSE)
356  return CSR_32_AllRegs_SSE_SaveList;
357  return CSR_32_AllRegs_SaveList;
358  }
359  default:
360  break;
361  }
362 
363  if (Is64Bit) {
364  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
365  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
366  if (IsSwiftCC)
367  return IsWin64 ? CSR_Win64_SwiftError_SaveList
368  : CSR_64_SwiftError_SaveList;
369 
370  if (IsWin64)
371  return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
372  if (CallsEHReturn)
373  return CSR_64EHRet_SaveList;
374  return CSR_64_SaveList;
375  }
376 
377  return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
378 }
379 
381  const MachineFunction *MF) const {
382  assert(MF && "Invalid MachineFunction pointer.");
384  MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
385  return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
386  return nullptr;
387 }
388 
389 const uint32_t *
391  CallingConv::ID CC) const {
392  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
393  bool HasSSE = Subtarget.hasSSE1();
394  bool HasAVX = Subtarget.hasAVX();
395  bool HasAVX512 = Subtarget.hasAVX512();
396 
397  switch (CC) {
398  case CallingConv::GHC:
399  case CallingConv::HiPE:
400  return CSR_NoRegs_RegMask;
401  case CallingConv::AnyReg:
402  if (HasAVX)
403  return CSR_64_AllRegs_AVX_RegMask;
404  return CSR_64_AllRegs_RegMask;
406  return CSR_64_RT_MostRegs_RegMask;
408  if (HasAVX)
409  return CSR_64_RT_AllRegs_AVX_RegMask;
410  return CSR_64_RT_AllRegs_RegMask;
412  if (Is64Bit)
413  return CSR_64_TLS_Darwin_RegMask;
414  break;
416  if (HasAVX512 && IsWin64)
417  return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
418  if (HasAVX512 && Is64Bit)
419  return CSR_64_Intel_OCL_BI_AVX512_RegMask;
420  if (HasAVX && IsWin64)
421  return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
422  if (HasAVX && Is64Bit)
423  return CSR_64_Intel_OCL_BI_AVX_RegMask;
424  if (!HasAVX && !IsWin64 && Is64Bit)
425  return CSR_64_Intel_OCL_BI_RegMask;
426  break;
427  }
428  case CallingConv::HHVM:
429  return CSR_64_HHVM_RegMask;
431  if (Is64Bit) {
432  if (IsWin64) {
433  return (HasSSE ? CSR_Win64_RegCall_RegMask :
434  CSR_Win64_RegCall_NoSSE_RegMask);
435  } else {
436  return (HasSSE ? CSR_SysV64_RegCall_RegMask :
437  CSR_SysV64_RegCall_NoSSE_RegMask);
438  }
439  } else {
440  return (HasSSE ? CSR_32_RegCall_RegMask :
441  CSR_32_RegCall_NoSSE_RegMask);
442  }
443  case CallingConv::Cold:
444  if (Is64Bit)
445  return CSR_64_MostRegs_RegMask;
446  break;
447  case CallingConv::Win64:
448  return CSR_Win64_RegMask;
450  return CSR_64_RegMask;
452  if (Is64Bit) {
453  if (HasAVX512)
454  return CSR_64_AllRegs_AVX512_RegMask;
455  if (HasAVX)
456  return CSR_64_AllRegs_AVX_RegMask;
457  if (HasSSE)
458  return CSR_64_AllRegs_RegMask;
459  return CSR_64_AllRegs_NoSSE_RegMask;
460  } else {
461  if (HasAVX512)
462  return CSR_32_AllRegs_AVX512_RegMask;
463  if (HasAVX)
464  return CSR_32_AllRegs_AVX_RegMask;
465  if (HasSSE)
466  return CSR_32_AllRegs_SSE_RegMask;
467  return CSR_32_AllRegs_RegMask;
468  }
469  default:
470  break;
471  }
472 
473  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
474  // callsEHReturn().
475  if (Is64Bit) {
476  const Function &F = MF.getFunction();
477  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
478  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
479  if (IsSwiftCC)
480  return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
481  return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
482  }
483 
484  return CSR_32_RegMask;
485 }
486 
487 const uint32_t*
489  return CSR_NoRegs_RegMask;
490 }
491 
493  return CSR_64_TLS_Darwin_RegMask;
494 }
495 
497  BitVector Reserved(getNumRegs());
498  const X86FrameLowering *TFI = getFrameLowering(MF);
499 
500  // Set the stack-pointer register and its aliases as reserved.
501  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
502  ++I)
503  Reserved.set(*I);
504 
505  // Set the Shadow Stack Pointer as reserved.
506  Reserved.set(X86::SSP);
507 
508  // Set the instruction pointer register and its aliases as reserved.
509  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
510  ++I)
511  Reserved.set(*I);
512 
513  // Set the frame-pointer register and its aliases as reserved if needed.
514  if (TFI->hasFP(MF)) {
515  for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
516  ++I)
517  Reserved.set(*I);
518  }
519 
520  // Set the base-pointer register and its aliases as reserved if needed.
521  if (hasBasePointer(MF)) {
523  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
526  "Stack realignment in presence of dynamic allocas is not supported with"
527  "this calling convention.");
528 
529  unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
530  for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
531  I.isValid(); ++I)
532  Reserved.set(*I);
533  }
534 
535  // Mark the segment registers as reserved.
536  Reserved.set(X86::CS);
537  Reserved.set(X86::SS);
538  Reserved.set(X86::DS);
539  Reserved.set(X86::ES);
540  Reserved.set(X86::FS);
541  Reserved.set(X86::GS);
542 
543  // Mark the floating point stack registers as reserved.
544  for (unsigned n = 0; n != 8; ++n)
545  Reserved.set(X86::ST0 + n);
546 
547  // Reserve the registers that only exist in 64-bit mode.
548  if (!Is64Bit) {
549  // These 8-bit registers are part of the x86-64 extension even though their
550  // super-registers are old 32-bits.
551  Reserved.set(X86::SIL);
552  Reserved.set(X86::DIL);
553  Reserved.set(X86::BPL);
554  Reserved.set(X86::SPL);
555 
556  for (unsigned n = 0; n != 8; ++n) {
557  // R8, R9, ...
558  for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
559  Reserved.set(*AI);
560 
561  // XMM8, XMM9, ...
562  for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
563  Reserved.set(*AI);
564  }
565  }
566  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
567  for (unsigned n = 16; n != 32; ++n) {
568  for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
569  Reserved.set(*AI);
570  }
571  }
572 
573  assert(checkAllSuperRegsMarked(Reserved,
574  {X86::SIL, X86::DIL, X86::BPL, X86::SPL}));
575  return Reserved;
576 }
577 
579  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
580  // because the calling convention defines the EFLAGS register as NOT
581  // preserved.
582  //
583  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
584  // an assert to track this and clear the register afterwards to avoid
585  // unnecessary crashes during release builds.
586  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
587  "EFLAGS are not live-out from a patchpoint.");
588 
589  // Also clean other registers that don't need preserving (IP).
590  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
591  Mask[Reg / 32] &= ~(1U << (Reg % 32));
592 }
593 
594 //===----------------------------------------------------------------------===//
595 // Stack Frame Processing methods
596 //===----------------------------------------------------------------------===//
597 
598 static bool CantUseSP(const MachineFrameInfo &MFI) {
599  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
600 }
601 
603  const MachineFrameInfo &MFI = MF.getFrameInfo();
604 
605  if (!EnableBasePointer)
606  return false;
607 
608  // When we need stack realignment, we can't address the stack from the frame
609  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
610  // can't address variables from the stack pointer. MS inline asm can
611  // reference locals while also adjusting the stack pointer. When we can't
612  // use both the SP and the FP, we need a separate base pointer register.
613  bool CantUseFP = needsStackRealignment(MF);
614  return CantUseFP && CantUseSP(MFI);
615 }
616 
619  return false;
620 
621  const MachineFrameInfo &MFI = MF.getFrameInfo();
622  const MachineRegisterInfo *MRI = &MF.getRegInfo();
623 
624  // Stack realignment requires a frame pointer. If we already started
625  // register allocation with frame pointer elimination, it is too late now.
626  if (!MRI->canReserveReg(FramePtr))
627  return false;
628 
629  // If a base pointer is necessary. Check that it isn't too late to reserve
630  // it.
631  if (CantUseSP(MFI))
632  return MRI->canReserveReg(BasePtr);
633  return true;
634 }
635 
637  unsigned Reg, int &FrameIdx) const {
638  // Since X86 defines assignCalleeSavedSpillSlots which always return true
639  // this function neither used nor tested.
640  llvm_unreachable("Unused function on X86. Otherwise need a test case.");
641 }
642 
643 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
644 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
645 // TODO: In this case we should be really trying first to entirely eliminate
646 // this instruction which is a plain copy.
648  MachineInstr &MI = *II;
649  unsigned Opc = II->getOpcode();
650  // Check if this is a LEA of the form 'lea (%esp), %ebx'
651  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
652  MI.getOperand(2).getImm() != 1 ||
653  MI.getOperand(3).getReg() != X86::NoRegister ||
654  MI.getOperand(4).getImm() != 0 ||
655  MI.getOperand(5).getReg() != X86::NoRegister)
656  return false;
657  unsigned BasePtr = MI.getOperand(1).getReg();
658  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
659  // be replaced with a 32-bit operand MOV which will zero extend the upper
660  // 32-bits of the super register.
661  if (Opc == X86::LEA64_32r)
662  BasePtr = getX86SubSuperRegister(BasePtr, 32);
663  unsigned NewDestReg = MI.getOperand(0).getReg();
664  const X86InstrInfo *TII =
665  MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
666  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
667  MI.getOperand(1).isKill());
668  MI.eraseFromParent();
669  return true;
670 }
671 
672 void
674  int SPAdj, unsigned FIOperandNum,
675  RegScavenger *RS) const {
676  MachineInstr &MI = *II;
677  MachineFunction &MF = *MI.getParent()->getParent();
678  const X86FrameLowering *TFI = getFrameLowering(MF);
679  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
680 
681  // Determine base register and offset.
682  int FIOffset;
683  unsigned BasePtr;
684  if (MI.isReturn()) {
685  assert((!needsStackRealignment(MF) ||
686  MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
687  "Return instruction can only reference SP relative frame objects");
688  FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
689  } else {
690  FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
691  }
692 
693  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
694  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
695  // offset is from the traditional base pointer location. On 64-bit, the
696  // offset is from the SP at the end of the prologue, not the FP location. This
697  // matches the behavior of llvm.frameaddress.
698  unsigned Opc = MI.getOpcode();
699  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
700  MachineOperand &FI = MI.getOperand(FIOperandNum);
701  FI.ChangeToImmediate(FIOffset);
702  return;
703  }
704 
705  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
706  // register as source operand, semantic is the same and destination is
707  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
708  // Don't change BasePtr since it is used later for stack adjustment.
709  unsigned MachineBasePtr = BasePtr;
710  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
711  MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
712 
713  // This must be part of a four operand memory reference. Replace the
714  // FrameIndex with base register. Add an offset to the offset.
715  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
716 
717  if (BasePtr == StackPtr)
718  FIOffset += SPAdj;
719 
720  // The frame index format for stackmaps and patchpoints is different from the
721  // X86 format. It only has a FI and an offset.
722  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
723  assert(BasePtr == FramePtr && "Expected the FP as base register");
724  int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
725  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
726  return;
727  }
728 
729  if (MI.getOperand(FIOperandNum+3).isImm()) {
730  // Offset is a 32-bit integer.
731  int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
732  int Offset = FIOffset + Imm;
733  assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
734  "Requesting 64-bit offset in 32-bit immediate!");
735  if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
736  MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
737  } else {
738  // Offset is symbolic. This is extremely rare.
739  uint64_t Offset = FIOffset +
740  (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
741  MI.getOperand(FIOperandNum + 3).setOffset(Offset);
742  }
743 }
744 
746  const X86FrameLowering *TFI = getFrameLowering(MF);
747  return TFI->hasFP(MF) ? FramePtr : StackPtr;
748 }
749 
750 unsigned
752  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
753  unsigned FrameReg = getFrameRegister(MF);
754  if (Subtarget.isTarget64BitILP32())
755  FrameReg = getX86SubSuperRegister(FrameReg, 32);
756  return FrameReg;
757 }
bool hasAVX() const
Definition: X86Subtarget.h:487
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:398
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
Definition: CallingConv.h:164
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:140
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
unsigned getReg() const
getReg - Returns the register number.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
F(f)
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
return AArch64::GPR64RegClass contains(Reg)
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:470
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
unsigned getBaseRegister() const
bool hasVLX() const
Definition: X86Subtarget.h:576
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:457
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:405
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const uint32_t * getNoPreservedMask() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MCRegAliasIterator enumerates all registers aliasing Reg.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int getSEHRegNum(unsigned i) const
void setOffset(int64_t Offset)
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:204
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
MachineOperand class - Representation of each machine instruction operand.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:464
bool callsEHReturn() const
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
const uint32_t * getDarwinTLSCallPreservedMask() const
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
Basic Alias true
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1243
int64_t getOffset() const
Return the offset from the symbol in this operand.
#define I(x, y, z)
Definition: MD5.cpp:58
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
bool canRealignStack(const MachineFunction &MF) const override
static bool CantUseSP(const MachineFrameInfo &MFI)
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasSSE1() const
Definition: X86Subtarget.h:481
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool hasAVX512() const
Definition: X86Subtarget.h:489
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
IRTranslator LLVM IR MI
unsigned getFrameRegister(const MachineFunction &MF) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:174