LLVM  6.0.0svn
X86RegisterInfo.cpp
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1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
40 
41 using namespace llvm;
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
45 
46 static cl::opt<bool>
47 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
48  cl::desc("Enable use of a base pointer for complex stack frames"));
49 
51  : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
52  X86_MC::getDwarfRegFlavour(TT, false),
53  X86_MC::getDwarfRegFlavour(TT, true),
54  (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56 
57  // Cache some information.
58  Is64Bit = TT.isArch64Bit();
59  IsWin64 = Is64Bit && TT.isOSWindows();
60 
61  // Use a callee-saved register as the base pointer. These registers must
62  // not conflict with any ABI requirements. For example, in 32-bit mode PIC
63  // requires GOT in the EBX register before function calls via PLT GOT pointer.
64  if (Is64Bit) {
65  SlotSize = 8;
66  // This matches the simplified 32-bit pointer code in the data layout
67  // computation.
68  // FIXME: Should use the data layout?
69  bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
70  StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
71  FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
72  BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
73  } else {
74  SlotSize = 4;
75  StackPtr = X86::ESP;
76  FramePtr = X86::EBP;
77  BasePtr = X86::ESI;
78  }
79 }
80 
81 bool
83  // ExecutionDepsFixer and PostRAScheduler require liveness.
84  return true;
85 }
86 
87 int
88 X86RegisterInfo::getSEHRegNum(unsigned i) const {
89  return getEncodingValue(i);
90 }
91 
92 const TargetRegisterClass *
94  unsigned Idx) const {
95  // The sub_8bit sub-register index is more constrained in 32-bit mode.
96  // It behaves just like the sub_8bit_hi index.
97  if (!Is64Bit && Idx == X86::sub_8bit)
98  Idx = X86::sub_8bit_hi;
99 
100  // Forward to TableGen's default version.
101  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
102 }
103 
104 const TargetRegisterClass *
106  const TargetRegisterClass *B,
107  unsigned SubIdx) const {
108  // The sub_8bit sub-register index is more constrained in 32-bit mode.
109  if (!Is64Bit && SubIdx == X86::sub_8bit) {
110  A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
111  if (!A)
112  return nullptr;
113  }
114  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
115 }
116 
117 const TargetRegisterClass *
119  const MachineFunction &MF) const {
120  // Don't allow super-classes of GR8_NOREX. This class is only used after
121  // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
122  // to the full GR8 register class in 64-bit mode, so we cannot allow the
123  // reigster class inflation.
124  //
125  // The GR8_NOREX class is always used in a way that won't be constrained to a
126  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
127  // full GR8 class.
128  if (RC == &X86::GR8_NOREXRegClass)
129  return RC;
130 
131  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
132 
133  const TargetRegisterClass *Super = RC;
135  do {
136  switch (Super->getID()) {
137  case X86::FR32RegClassID:
138  case X86::FR64RegClassID:
139  // If AVX-512 isn't supported we should only inflate to these classes.
140  if (!Subtarget.hasAVX512() &&
141  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
142  return Super;
143  break;
144  case X86::VR128RegClassID:
145  case X86::VR256RegClassID:
146  // If VLX isn't supported we should only inflate to these classes.
147  if (!Subtarget.hasVLX() &&
148  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
149  return Super;
150  break;
151  case X86::VR128XRegClassID:
152  case X86::VR256XRegClassID:
153  // If VLX isn't support we shouldn't inflate to these classes.
154  if (Subtarget.hasVLX() &&
155  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
156  return Super;
157  break;
158  case X86::FR32XRegClassID:
159  case X86::FR64XRegClassID:
160  // If AVX-512 isn't support we shouldn't inflate to these classes.
161  if (Subtarget.hasAVX512() &&
162  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
163  return Super;
164  break;
165  case X86::GR8RegClassID:
166  case X86::GR16RegClassID:
167  case X86::GR32RegClassID:
168  case X86::GR64RegClassID:
169  case X86::RFP32RegClassID:
170  case X86::RFP64RegClassID:
171  case X86::RFP80RegClassID:
172  case X86::VR512RegClassID:
173  // Don't return a super-class that would shrink the spill size.
174  // That can happen with the vector and float classes.
175  if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
176  return Super;
177  }
178  Super = *I++;
179  } while (Super);
180  return RC;
181 }
182 
183 const TargetRegisterClass *
185  unsigned Kind) const {
186  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
187  switch (Kind) {
188  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
189  case 0: // Normal GPRs.
190  if (Subtarget.isTarget64BitLP64())
191  return &X86::GR64RegClass;
192  // If the target is 64bit but we have been told to use 32bit addresses,
193  // we can still use 64-bit register as long as we know the high bits
194  // are zeros.
195  // Reflect that in the returned register class.
196  if (Is64Bit) {
197  // When the target also allows 64-bit frame pointer and we do have a
198  // frame, this is fine to use it for the address accesses as well.
199  const X86FrameLowering *TFI = getFrameLowering(MF);
200  return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
201  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
202  : &X86::LOW32_ADDR_ACCESSRegClass;
203  }
204  return &X86::GR32RegClass;
205  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
206  if (Subtarget.isTarget64BitLP64())
207  return &X86::GR64_NOSPRegClass;
208  // NOSP does not contain RIP, so no special case here.
209  return &X86::GR32_NOSPRegClass;
210  case 2: // NOREX GPRs.
211  if (Subtarget.isTarget64BitLP64())
212  return &X86::GR64_NOREXRegClass;
213  return &X86::GR32_NOREXRegClass;
214  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
215  if (Subtarget.isTarget64BitLP64())
216  return &X86::GR64_NOREX_NOSPRegClass;
217  // NOSP does not contain RIP, so no special case here.
218  return &X86::GR32_NOREX_NOSPRegClass;
219  case 4: // Available for tailcall (not callee-saved GPRs).
220  return getGPRsForTailCall(MF);
221  }
222 }
223 
224 const TargetRegisterClass *
226  const Function *F = MF.getFunction();
227  if (IsWin64 || (F && F->getCallingConv() == CallingConv::Win64))
228  return &X86::GR64_TCW64RegClass;
229  else if (Is64Bit)
230  return &X86::GR64_TCRegClass;
231 
232  bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
233  if (hasHipeCC)
234  return &X86::GR32RegClass;
235  return &X86::GR32_TCRegClass;
236 }
237 
238 const TargetRegisterClass *
240  if (RC == &X86::CCRRegClass) {
241  if (Is64Bit)
242  return &X86::GR64RegClass;
243  else
244  return &X86::GR32RegClass;
245  }
246  return RC;
247 }
248 
249 unsigned
251  MachineFunction &MF) const {
252  const X86FrameLowering *TFI = getFrameLowering(MF);
253 
254  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
255  switch (RC->getID()) {
256  default:
257  return 0;
258  case X86::GR32RegClassID:
259  return 4 - FPDiff;
260  case X86::GR64RegClassID:
261  return 12 - FPDiff;
262  case X86::VR128RegClassID:
263  return Is64Bit ? 10 : 4;
264  case X86::VR64RegClassID:
265  return 4;
266  }
267 }
268 
269 const MCPhysReg *
271  assert(MF && "MachineFunction required");
272 
273  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
274  const Function *F = MF->getFunction();
275  bool HasSSE = Subtarget.hasSSE1();
276  bool HasAVX = Subtarget.hasAVX();
277  bool HasAVX512 = Subtarget.hasAVX512();
278  bool CallsEHReturn = MF->callsEHReturn();
279 
280  CallingConv::ID CC = F->getCallingConv();
281 
282  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
283  // convention because it has the CSR list.
284  if (MF->getFunction()->hasFnAttribute("no_caller_saved_registers"))
286 
287  switch (CC) {
288  case CallingConv::GHC:
289  case CallingConv::HiPE:
290  return CSR_NoRegs_SaveList;
291  case CallingConv::AnyReg:
292  if (HasAVX)
293  return CSR_64_AllRegs_AVX_SaveList;
294  return CSR_64_AllRegs_SaveList;
296  return CSR_64_RT_MostRegs_SaveList;
298  if (HasAVX)
299  return CSR_64_RT_AllRegs_AVX_SaveList;
300  return CSR_64_RT_AllRegs_SaveList;
302  if (Is64Bit)
303  return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
304  CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
305  break;
307  if (HasAVX512 && IsWin64)
308  return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
309  if (HasAVX512 && Is64Bit)
310  return CSR_64_Intel_OCL_BI_AVX512_SaveList;
311  if (HasAVX && IsWin64)
312  return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
313  if (HasAVX && Is64Bit)
314  return CSR_64_Intel_OCL_BI_AVX_SaveList;
315  if (!HasAVX && !IsWin64 && Is64Bit)
316  return CSR_64_Intel_OCL_BI_SaveList;
317  break;
318  }
319  case CallingConv::HHVM:
320  return CSR_64_HHVM_SaveList;
322  if (Is64Bit) {
323  if (IsWin64) {
324  return (HasSSE ? CSR_Win64_RegCall_SaveList :
325  CSR_Win64_RegCall_NoSSE_SaveList);
326  } else {
327  return (HasSSE ? CSR_SysV64_RegCall_SaveList :
328  CSR_SysV64_RegCall_NoSSE_SaveList);
329  }
330  } else {
331  return (HasSSE ? CSR_32_RegCall_SaveList :
332  CSR_32_RegCall_NoSSE_SaveList);
333  }
334  case CallingConv::Cold:
335  if (Is64Bit)
336  return CSR_64_MostRegs_SaveList;
337  break;
338  case CallingConv::Win64:
339  if (!HasSSE)
340  return CSR_Win64_NoSSE_SaveList;
341  return CSR_Win64_SaveList;
343  if (CallsEHReturn)
344  return CSR_64EHRet_SaveList;
345  return CSR_64_SaveList;
347  if (Is64Bit) {
348  if (HasAVX512)
349  return CSR_64_AllRegs_AVX512_SaveList;
350  if (HasAVX)
351  return CSR_64_AllRegs_AVX_SaveList;
352  if (HasSSE)
353  return CSR_64_AllRegs_SaveList;
354  return CSR_64_AllRegs_NoSSE_SaveList;
355  } else {
356  if (HasAVX512)
357  return CSR_32_AllRegs_AVX512_SaveList;
358  if (HasAVX)
359  return CSR_32_AllRegs_AVX_SaveList;
360  if (HasSSE)
361  return CSR_32_AllRegs_SSE_SaveList;
362  return CSR_32_AllRegs_SaveList;
363  }
364  default:
365  break;
366  }
367 
368  if (Is64Bit) {
369  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
370  F->getAttributes().hasAttrSomewhere(Attribute::SwiftError);
371  if (IsSwiftCC)
372  return IsWin64 ? CSR_Win64_SwiftError_SaveList
373  : CSR_64_SwiftError_SaveList;
374 
375  if (IsWin64)
376  return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
377  if (CallsEHReturn)
378  return CSR_64EHRet_SaveList;
379  return CSR_64_SaveList;
380  }
381 
382  return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
383 }
384 
386  const MachineFunction *MF) const {
387  assert(MF && "Invalid MachineFunction pointer.");
389  MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
390  return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
391  return nullptr;
392 }
393 
394 const uint32_t *
396  CallingConv::ID CC) const {
397  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
398  bool HasSSE = Subtarget.hasSSE1();
399  bool HasAVX = Subtarget.hasAVX();
400  bool HasAVX512 = Subtarget.hasAVX512();
401 
402  switch (CC) {
403  case CallingConv::GHC:
404  case CallingConv::HiPE:
405  return CSR_NoRegs_RegMask;
406  case CallingConv::AnyReg:
407  if (HasAVX)
408  return CSR_64_AllRegs_AVX_RegMask;
409  return CSR_64_AllRegs_RegMask;
411  return CSR_64_RT_MostRegs_RegMask;
413  if (HasAVX)
414  return CSR_64_RT_AllRegs_AVX_RegMask;
415  return CSR_64_RT_AllRegs_RegMask;
417  if (Is64Bit)
418  return CSR_64_TLS_Darwin_RegMask;
419  break;
421  if (HasAVX512 && IsWin64)
422  return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
423  if (HasAVX512 && Is64Bit)
424  return CSR_64_Intel_OCL_BI_AVX512_RegMask;
425  if (HasAVX && IsWin64)
426  return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
427  if (HasAVX && Is64Bit)
428  return CSR_64_Intel_OCL_BI_AVX_RegMask;
429  if (!HasAVX && !IsWin64 && Is64Bit)
430  return CSR_64_Intel_OCL_BI_RegMask;
431  break;
432  }
433  case CallingConv::HHVM:
434  return CSR_64_HHVM_RegMask;
436  if (Is64Bit) {
437  if (IsWin64) {
438  return (HasSSE ? CSR_Win64_RegCall_RegMask :
439  CSR_Win64_RegCall_NoSSE_RegMask);
440  } else {
441  return (HasSSE ? CSR_SysV64_RegCall_RegMask :
442  CSR_SysV64_RegCall_NoSSE_RegMask);
443  }
444  } else {
445  return (HasSSE ? CSR_32_RegCall_RegMask :
446  CSR_32_RegCall_NoSSE_RegMask);
447  }
448  case CallingConv::Cold:
449  if (Is64Bit)
450  return CSR_64_MostRegs_RegMask;
451  break;
452  case CallingConv::Win64:
453  return CSR_Win64_RegMask;
455  return CSR_64_RegMask;
457  if (Is64Bit) {
458  if (HasAVX512)
459  return CSR_64_AllRegs_AVX512_RegMask;
460  if (HasAVX)
461  return CSR_64_AllRegs_AVX_RegMask;
462  if (HasSSE)
463  return CSR_64_AllRegs_RegMask;
464  return CSR_64_AllRegs_NoSSE_RegMask;
465  } else {
466  if (HasAVX512)
467  return CSR_32_AllRegs_AVX512_RegMask;
468  if (HasAVX)
469  return CSR_32_AllRegs_AVX_RegMask;
470  if (HasSSE)
471  return CSR_32_AllRegs_SSE_RegMask;
472  return CSR_32_AllRegs_RegMask;
473  }
474  default:
475  break;
476  }
477 
478  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
479  // callsEHReturn().
480  if (Is64Bit) {
481  const Function *F = MF.getFunction();
482  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
483  F->getAttributes().hasAttrSomewhere(Attribute::SwiftError);
484  if (IsSwiftCC)
485  return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
486  return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
487  }
488 
489  return CSR_32_RegMask;
490 }
491 
492 const uint32_t*
494  return CSR_NoRegs_RegMask;
495 }
496 
498  return CSR_64_TLS_Darwin_RegMask;
499 }
500 
502  BitVector Reserved(getNumRegs());
503  const X86FrameLowering *TFI = getFrameLowering(MF);
504 
505  // Set the stack-pointer register and its aliases as reserved.
506  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
507  ++I)
508  Reserved.set(*I);
509 
510  // Set the instruction pointer register and its aliases as reserved.
511  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
512  ++I)
513  Reserved.set(*I);
514 
515  // Set the frame-pointer register and its aliases as reserved if needed.
516  if (TFI->hasFP(MF)) {
517  for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
518  ++I)
519  Reserved.set(*I);
520  }
521 
522  // Set the base-pointer register and its aliases as reserved if needed.
523  if (hasBasePointer(MF)) {
525  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
528  "Stack realignment in presence of dynamic allocas is not supported with"
529  "this calling convention.");
530 
531  unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
532  for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
533  I.isValid(); ++I)
534  Reserved.set(*I);
535  }
536 
537  // Mark the segment registers as reserved.
538  Reserved.set(X86::CS);
539  Reserved.set(X86::SS);
540  Reserved.set(X86::DS);
541  Reserved.set(X86::ES);
542  Reserved.set(X86::FS);
543  Reserved.set(X86::GS);
544 
545  // Mark the floating point stack registers as reserved.
546  for (unsigned n = 0; n != 8; ++n)
547  Reserved.set(X86::ST0 + n);
548 
549  // Reserve the registers that only exist in 64-bit mode.
550  if (!Is64Bit) {
551  // These 8-bit registers are part of the x86-64 extension even though their
552  // super-registers are old 32-bits.
553  Reserved.set(X86::SIL);
554  Reserved.set(X86::DIL);
555  Reserved.set(X86::BPL);
556  Reserved.set(X86::SPL);
557 
558  for (unsigned n = 0; n != 8; ++n) {
559  // R8, R9, ...
560  for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
561  Reserved.set(*AI);
562 
563  // XMM8, XMM9, ...
564  for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
565  Reserved.set(*AI);
566  }
567  }
568  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
569  for (unsigned n = 16; n != 32; ++n) {
570  for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
571  Reserved.set(*AI);
572  }
573  }
574 
575  assert(checkAllSuperRegsMarked(Reserved,
576  {X86::SIL, X86::DIL, X86::BPL, X86::SPL}));
577  return Reserved;
578 }
579 
581  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
582  // because the calling convention defines the EFLAGS register as NOT
583  // preserved.
584  //
585  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
586  // an assert to track this and clear the register afterwards to avoid
587  // unnecessary crashes during release builds.
588  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
589  "EFLAGS are not live-out from a patchpoint.");
590 
591  // Also clean other registers that don't need preserving (IP).
592  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
593  Mask[Reg / 32] &= ~(1U << (Reg % 32));
594 }
595 
596 //===----------------------------------------------------------------------===//
597 // Stack Frame Processing methods
598 //===----------------------------------------------------------------------===//
599 
600 static bool CantUseSP(const MachineFrameInfo &MFI) {
601  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
602 }
603 
605  const MachineFrameInfo &MFI = MF.getFrameInfo();
606 
607  if (!EnableBasePointer)
608  return false;
609 
610  // When we need stack realignment, we can't address the stack from the frame
611  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
612  // can't address variables from the stack pointer. MS inline asm can
613  // reference locals while also adjusting the stack pointer. When we can't
614  // use both the SP and the FP, we need a separate base pointer register.
615  bool CantUseFP = needsStackRealignment(MF);
616  return CantUseFP && CantUseSP(MFI);
617 }
618 
621  return false;
622 
623  const MachineFrameInfo &MFI = MF.getFrameInfo();
624  const MachineRegisterInfo *MRI = &MF.getRegInfo();
625 
626  // Stack realignment requires a frame pointer. If we already started
627  // register allocation with frame pointer elimination, it is too late now.
628  if (!MRI->canReserveReg(FramePtr))
629  return false;
630 
631  // If a base pointer is necessary. Check that it isn't too late to reserve
632  // it.
633  if (CantUseSP(MFI))
634  return MRI->canReserveReg(BasePtr);
635  return true;
636 }
637 
639  unsigned Reg, int &FrameIdx) const {
640  // Since X86 defines assignCalleeSavedSpillSlots which always return true
641  // this function neither used nor tested.
642  llvm_unreachable("Unused function on X86. Otherwise need a test case.");
643 }
644 
645 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
646 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
647 // TODO: In this case we should be really trying first to entirely eliminate
648 // this instruction which is a plain copy.
650  MachineInstr &MI = *II;
651  unsigned Opc = II->getOpcode();
652  // Check if this is a LEA of the form 'lea (%esp), %ebx'
653  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
654  MI.getOperand(2).getImm() != 1 ||
655  MI.getOperand(3).getReg() != X86::NoRegister ||
656  MI.getOperand(4).getImm() != 0 ||
657  MI.getOperand(5).getReg() != X86::NoRegister)
658  return false;
659  unsigned BasePtr = MI.getOperand(1).getReg();
660  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
661  // be replaced with a 32-bit operand MOV which will zero extend the upper
662  // 32-bits of the super register.
663  if (Opc == X86::LEA64_32r)
664  BasePtr = getX86SubSuperRegister(BasePtr, 32);
665  unsigned NewDestReg = MI.getOperand(0).getReg();
666  const X86InstrInfo *TII =
667  MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
668  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
669  MI.getOperand(1).isKill());
670  MI.eraseFromParent();
671  return true;
672 }
673 
674 void
676  int SPAdj, unsigned FIOperandNum,
677  RegScavenger *RS) const {
678  MachineInstr &MI = *II;
679  MachineFunction &MF = *MI.getParent()->getParent();
680  const X86FrameLowering *TFI = getFrameLowering(MF);
681  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
682 
683  // Determine base register and offset.
684  int FIOffset;
685  unsigned BasePtr;
686  if (MI.isReturn()) {
687  assert((!needsStackRealignment(MF) ||
688  MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
689  "Return instruction can only reference SP relative frame objects");
690  FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
691  } else {
692  FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
693  }
694 
695  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
696  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
697  // offset is from the traditional base pointer location. On 64-bit, the
698  // offset is from the SP at the end of the prologue, not the FP location. This
699  // matches the behavior of llvm.frameaddress.
700  unsigned Opc = MI.getOpcode();
701  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
702  MachineOperand &FI = MI.getOperand(FIOperandNum);
703  FI.ChangeToImmediate(FIOffset);
704  return;
705  }
706 
707  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
708  // register as source operand, semantic is the same and destination is
709  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
710  // Don't change BasePtr since it is used later for stack adjustment.
711  unsigned MachineBasePtr = BasePtr;
712  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
713  MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
714 
715  // This must be part of a four operand memory reference. Replace the
716  // FrameIndex with base register. Add an offset to the offset.
717  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
718 
719  if (BasePtr == StackPtr)
720  FIOffset += SPAdj;
721 
722  // The frame index format for stackmaps and patchpoints is different from the
723  // X86 format. It only has a FI and an offset.
724  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
725  assert(BasePtr == FramePtr && "Expected the FP as base register");
726  int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
727  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
728  return;
729  }
730 
731  if (MI.getOperand(FIOperandNum+3).isImm()) {
732  // Offset is a 32-bit integer.
733  int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
734  int Offset = FIOffset + Imm;
735  assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
736  "Requesting 64-bit offset in 32-bit immediate!");
737  if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
738  MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
739  } else {
740  // Offset is symbolic. This is extremely rare.
741  uint64_t Offset = FIOffset +
742  (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
743  MI.getOperand(FIOperandNum + 3).setOffset(Offset);
744  }
745 }
746 
748  const X86FrameLowering *TFI = getFrameLowering(MF);
749  return TFI->hasFP(MF) ? FramePtr : StackPtr;
750 }
751 
752 unsigned
754  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
755  unsigned FrameReg = getFrameRegister(MF);
756  if (Subtarget.isTarget64BitILP32())
757  FrameReg = getX86SubSuperRegister(FrameReg, 32);
758  return FrameReg;
759 }
bool hasAVX() const
Definition: X86Subtarget.h:449
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:398
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
Definition: CallingConv.h:164
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:204
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
unsigned getReg() const
getReg - Returns the register number.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
F(f)
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
return AArch64::GPR64RegClass contains(Reg)
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const HexagonInstrInfo * TII
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:433
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
unsigned getBaseRegister() const
bool hasVLX() const
Definition: X86Subtarget.h:523
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:454
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:368
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const uint32_t * getNoPreservedMask() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MCRegAliasIterator enumerates all registers aliasing Reg.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int getSEHRegNum(unsigned i) const
void setOffset(int64_t Offset)
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:174
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
MachineOperand class - Representation of each machine instruction operand.
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:140
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
int64_t getImm() const
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:427
bool callsEHReturn() const
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
const uint32_t * getDarwinTLSCallPreservedMask() const
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
Basic Alias true
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1243
int64_t getOffset() const
Return the offset from the symbol in this operand.
#define I(x, y, z)
Definition: MD5.cpp:58
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
bool canRealignStack(const MachineFunction &MF) const override
static bool CantUseSP(const MachineFrameInfo &MFI)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasSSE1() const
Definition: X86Subtarget.h:443
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool hasAVX512() const
Definition: X86Subtarget.h:451
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
IRTranslator LLVM IR MI
unsigned getFrameRegister(const MachineFunction &MF) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295