LLVM  10.0.0svn
X86ISelLowering.cpp
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1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
15 #include "Utils/X86ShuffleDecode.h"
16 #include "X86CallingConv.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86IntrinsicsInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
38 #include "llvm/IR/CallSite.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/DiagnosticInfo.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalAlias.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/MC/MCAsmInfo.h"
49 #include "llvm/MC/MCContext.h"
50 #include "llvm/MC/MCExpr.h"
51 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/KnownBits.h"
58 #include <algorithm>
59 #include <bitset>
60 #include <cctype>
61 #include <numeric>
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "x86-isel"
65 
66 STATISTIC(NumTailCalls, "Number of tail calls");
67 
69  "x86-experimental-vector-widening-legalization", cl::init(true),
70  cl::desc("Enable an experimental vector type legalization through widening "
71  "rather than promotion."),
72  cl::Hidden);
73 
75  "x86-experimental-pref-loop-alignment", cl::init(4),
76  cl::desc(
77  "Sets the preferable loop alignment for experiments (as log2 bytes)"
78  "(the last x86-experimental-pref-loop-alignment bits"
79  " of the loop header PC will be 0)."),
80  cl::Hidden);
81 
82 // Added in 10.0.
84  "x86-enable-old-knl-abi", cl::init(false),
85  cl::desc("Enables passing v32i16 and v64i8 in 2 YMM registers instead of "
86  "one ZMM register on AVX512F, but not AVX512BW targets."),
87  cl::Hidden);
88 
90  "mul-constant-optimization", cl::init(true),
91  cl::desc("Replace 'mul x, Const' with more effective instructions like "
92  "SHIFT, LEA, etc."),
93  cl::Hidden);
94 
96  "x86-experimental-unordered-atomic-isel", cl::init(false),
97  cl::desc("Use LoadSDNode and StoreSDNode instead of "
98  "AtomicSDNode for unordered atomic loads and "
99  "stores respectively."),
100  cl::Hidden);
101 
102 /// Call this when the user attempts to do something unsupported, like
103 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
104 /// report_fatal_error, so calling code should attempt to recover without
105 /// crashing.
106 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
107  const char *Msg) {
109  DAG.getContext()->diagnose(
111 }
112 
114  const X86Subtarget &STI)
115  : TargetLowering(TM), Subtarget(STI) {
116  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
117  X86ScalarSSEf64 = Subtarget.hasSSE2();
118  X86ScalarSSEf32 = Subtarget.hasSSE1();
120 
121  // Set up the TargetLowering object.
122 
123  // X86 is weird. It always uses i8 for shift amounts and setcc results.
125  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
127 
128  // For 64-bit, since we have so many registers, use the ILP scheduler.
129  // For 32-bit, use the register pressure specific scheduling.
130  // For Atom, always use ILP scheduling.
131  if (Subtarget.isAtom())
133  else if (Subtarget.is64Bit())
135  else
137  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
139 
140  // Bypass expensive divides and use cheaper ones.
141  if (TM.getOptLevel() >= CodeGenOpt::Default) {
142  if (Subtarget.hasSlowDivide32())
143  addBypassSlowDiv(32, 8);
144  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
145  addBypassSlowDiv(64, 32);
146  }
147 
148  if (Subtarget.isTargetWindowsMSVC() ||
149  Subtarget.isTargetWindowsItanium()) {
150  // Setup Windows compiler runtime calls.
151  setLibcallName(RTLIB::SDIV_I64, "_alldiv");
152  setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
153  setLibcallName(RTLIB::SREM_I64, "_allrem");
154  setLibcallName(RTLIB::UREM_I64, "_aullrem");
155  setLibcallName(RTLIB::MUL_I64, "_allmul");
161  }
162 
163  if (Subtarget.isTargetDarwin()) {
164  // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
165  setUseUnderscoreSetJmp(false);
167  } else if (Subtarget.isTargetWindowsGNU()) {
168  // MS runtime is weird: it exports _setjmp, but longjmp!
171  } else {
174  }
175 
176  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
177  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
178  // FIXME: Should we be limitting the atomic size on other configs? Default is
179  // 1024.
180  if (!Subtarget.hasCmpxchg8b())
182 
183  // Set up the register classes.
184  addRegisterClass(MVT::i8, &X86::GR8RegClass);
185  addRegisterClass(MVT::i16, &X86::GR16RegClass);
186  addRegisterClass(MVT::i32, &X86::GR32RegClass);
187  if (Subtarget.is64Bit())
188  addRegisterClass(MVT::i64, &X86::GR64RegClass);
189 
190  for (MVT VT : MVT::integer_valuetypes())
192 
193  // We don't accept any truncstore of integer registers.
200 
202 
203  // SETOEQ and SETUNE require checking two conditions.
210 
211  // Integer absolute.
212  if (Subtarget.hasCMov()) {
215  }
217 
218  // Funnel shifts.
219  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
220  setOperationAction(ShiftOp , MVT::i16 , Custom);
221  setOperationAction(ShiftOp , MVT::i32 , Custom);
222  if (Subtarget.is64Bit())
223  setOperationAction(ShiftOp , MVT::i64 , Custom);
224  }
225 
226  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
227  // operation.
231 
232  if (!Subtarget.useSoftFloat()) {
233  // We have an algorithm for SSE2->double, and we turn this into a
234  // 64-bit FILD followed by conditional FADD for other targets.
236  // We have an algorithm for SSE2, and we turn this into a 64-bit
237  // FILD or VCVTUSI2SS/SD for other targets.
239  } else {
241  }
242 
243  // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
244  // this operation.
247 
248  if (!Subtarget.useSoftFloat()) {
249  // SSE has no i16 to fp conversion, only i32.
250  if (X86ScalarSSEf32) {
252  // f32 and f64 cases are Legal, f80 case is not
254  } else {
257  }
258  } else {
261  }
262 
263  // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
264  // this operation.
267 
268  if (!Subtarget.useSoftFloat()) {
269  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
270  // are Legal, f80 is custom lowered.
273 
276  } else {
280  }
281 
282  // Handle FP_TO_UINT by promoting the destination to a larger signed
283  // conversion.
287 
288  if (!Subtarget.useSoftFloat()) {
291  }
292 
293  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
294  if (!X86ScalarSSEf64) {
297  if (Subtarget.is64Bit()) {
299  // Without SSE, i64->f64 goes through memory.
301  }
302  } else if (!Subtarget.is64Bit())
304 
305  // Scalar integer divide and remainder are lowered to use operations that
306  // produce two results, to match the available instructions. This exposes
307  // the two-result form to trivial CSE, which is able to combine x/y and x%y
308  // into a single instruction.
309  //
310  // Scalar integer multiply-high is also lowered to use two-result
311  // operations, to match the available instructions. However, plain multiply
312  // (low) operations are left as Legal, as there are single-result
313  // instructions for this in x86. Using the two-result multiply instructions
314  // when both high and low results are needed must be arranged by dagcombine.
315  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
322  }
323 
326  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
330  }
331  if (Subtarget.is64Bit())
336 
342 
343  // Promote the i8 variants and force them on up to i32 which has a shorter
344  // encoding.
347  if (!Subtarget.hasBMI()) {
352  if (Subtarget.is64Bit()) {
355  }
356  }
357 
358  if (Subtarget.hasLZCNT()) {
359  // When promoting the i8 variants, force them to i32 for a shorter
360  // encoding.
363  } else {
370  if (Subtarget.is64Bit()) {
373  }
374  }
375 
376  // Special handling for half-precision floating point conversions.
377  // If we don't have F16C support, then lower half float conversions
378  // into library calls.
379  if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {
382  }
383 
384  // There's never any support for operations beyond MVT::f32.
391 
400 
401  if (Subtarget.hasPOPCNT()) {
403  } else {
407  if (Subtarget.is64Bit())
409  else
411  }
412 
414 
415  if (!Subtarget.hasMOVBE())
417 
418  // These should be promoted to a larger select which is supported.
420  // X86 wants to expand cmov itself.
421  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
424  }
425  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
426  if (VT == MVT::i64 && !Subtarget.is64Bit())
427  continue;
430  }
431 
432  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
435 
437  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
438  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
443  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
444 
445  // Darwin ABI issue.
446  for (auto VT : { MVT::i32, MVT::i64 }) {
447  if (VT == MVT::i64 && !Subtarget.is64Bit())
448  continue;
455  }
456 
457  // 64-bit shl, sra, srl (iff 32-bit x86)
458  for (auto VT : { MVT::i32, MVT::i64 }) {
459  if (VT == MVT::i64 && !Subtarget.is64Bit())
460  continue;
464  }
465 
466  if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
468 
470 
471  // Expand certain atomics
472  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
480  }
481 
482  if (!Subtarget.is64Bit())
484 
485  if (Subtarget.hasCmpxchg16b()) {
487  }
488 
489  // FIXME - use subtarget debug flags
490  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
491  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
494  }
495 
498 
501 
504 
505  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
508  bool Is64Bit = Subtarget.is64Bit();
510  setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
511 
514 
516 
517  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
520 
521  if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
522  // f32 and f64 use SSE.
523  // Set up the FP register classes.
524  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
525  : &X86::FR32RegClass);
526  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
527  : &X86::FR64RegClass);
528 
529  // Disable f32->f64 extload as we can only generate this in one instruction
530  // under optsize. So its easier to pattern match (fpext (load)) for that
531  // case instead of needing to emit 2 instructions for extload in the
532  // non-optsize case.
534 
535  for (auto VT : { MVT::f32, MVT::f64 }) {
536  // Use ANDPD to simulate FABS.
538 
539  // Use XORP to simulate FNEG.
541 
542  // Use ANDPD and ORPD to simulate FCOPYSIGN.
544 
545  // These might be better off as horizontal vector ops.
548 
549  // We don't support sin/cos/fmod
550  setOperationAction(ISD::FSIN , VT, Expand);
551  setOperationAction(ISD::FCOS , VT, Expand);
552  setOperationAction(ISD::FSINCOS, VT, Expand);
553  }
554 
555  // Lower this to MOVMSK plus an AND.
558 
559  } else if (!useSoftFloat() && X86ScalarSSEf32 && (UseX87 || Is64Bit)) {
560  // Use SSE for f32, x87 for f64.
561  // Set up the FP register classes.
562  addRegisterClass(MVT::f32, &X86::FR32RegClass);
563  if (UseX87)
564  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
565 
566  // Use ANDPS to simulate FABS.
568 
569  // Use XORP to simulate FNEG.
571 
572  if (UseX87)
574 
575  // Use ANDPS and ORPS to simulate FCOPYSIGN.
576  if (UseX87)
579 
580  // We don't support sin/cos/fmod
584 
585  if (UseX87) {
586  // Always expand sin/cos functions even though x87 has an instruction.
590  }
591  } else if (UseX87) {
592  // f32 and f64 in x87.
593  // Set up the FP register classes.
594  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
595  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
596 
597  for (auto VT : { MVT::f32, MVT::f64 }) {
598  setOperationAction(ISD::UNDEF, VT, Expand);
599  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
600 
601  // Always expand sin/cos functions even though x87 has an instruction.
602  setOperationAction(ISD::FSIN , VT, Expand);
603  setOperationAction(ISD::FCOS , VT, Expand);
604  setOperationAction(ISD::FSINCOS, VT, Expand);
605  }
606  }
607 
608  // Expand FP32 immediates into loads from the stack, save special cases.
609  if (isTypeLegal(MVT::f32)) {
610  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
611  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
615  } else // SSE immediates.
616  addLegalFPImmediate(APFloat(+0.0f)); // xorps
617  }
618  // Expand FP64 immediates into loads from the stack, save special cases.
619  if (isTypeLegal(MVT::f64)) {
620  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
621  addLegalFPImmediate(APFloat(+0.0)); // FLD0
622  addLegalFPImmediate(APFloat(+1.0)); // FLD1
623  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
624  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
625  } else // SSE immediates.
626  addLegalFPImmediate(APFloat(+0.0)); // xorpd
627  }
628 
629  // We don't support FMA.
632 
633  // f80 always uses X87.
634  if (UseX87) {
635  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
638  {
640  addLegalFPImmediate(TmpFlt); // FLD0
641  TmpFlt.changeSign();
642  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
643 
644  bool ignored;
645  APFloat TmpFlt2(+1.0);
647  &ignored);
648  addLegalFPImmediate(TmpFlt2); // FLD1
649  TmpFlt2.changeSign();
650  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
651  }
652 
653  // Always expand sin/cos functions even though x87 has an instruction.
657 
668  }
669 
670  // f128 uses xmm registers, but most operations require libcalls.
671  if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
672  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
673  : &X86::VR128RegClass);
674 
675  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
676 
682 
686 
691 
693  // We need to custom handle any FP_ROUND with an f128 input, but
694  // LegalizeDAG uses the result type to know when to run a custom handler.
695  // So we have to list all legal floating point result types here.
696  if (isTypeLegal(MVT::f32)) {
699  }
700  if (isTypeLegal(MVT::f64)) {
703  }
704  if (isTypeLegal(MVT::f80)) {
707  }
708 
710 
717  }
718 
719  // Always use a library call for pow.
724 
732 
733  // Some FP actions are always expanded for vector types.
734  for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
736  setOperationAction(ISD::FSIN, VT, Expand);
737  setOperationAction(ISD::FSINCOS, VT, Expand);
738  setOperationAction(ISD::FCOS, VT, Expand);
739  setOperationAction(ISD::FREM, VT, Expand);
740  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
741  setOperationAction(ISD::FPOW, VT, Expand);
742  setOperationAction(ISD::FLOG, VT, Expand);
743  setOperationAction(ISD::FLOG2, VT, Expand);
744  setOperationAction(ISD::FLOG10, VT, Expand);
745  setOperationAction(ISD::FEXP, VT, Expand);
746  setOperationAction(ISD::FEXP2, VT, Expand);
747  }
748 
749  // First set operation action for all vector types to either promote
750  // (for widening) or expand (for scalarization). Then we will selectively
751  // turn on ones that can be effectively codegen'd.
752  for (MVT VT : MVT::vector_valuetypes()) {
753  setOperationAction(ISD::SDIV, VT, Expand);
754  setOperationAction(ISD::UDIV, VT, Expand);
755  setOperationAction(ISD::SREM, VT, Expand);
756  setOperationAction(ISD::UREM, VT, Expand);
761  setOperationAction(ISD::FMA, VT, Expand);
762  setOperationAction(ISD::FFLOOR, VT, Expand);
763  setOperationAction(ISD::FCEIL, VT, Expand);
764  setOperationAction(ISD::FTRUNC, VT, Expand);
765  setOperationAction(ISD::FRINT, VT, Expand);
766  setOperationAction(ISD::FNEARBYINT, VT, Expand);
767  setOperationAction(ISD::SMUL_LOHI, VT, Expand);
768  setOperationAction(ISD::MULHS, VT, Expand);
769  setOperationAction(ISD::UMUL_LOHI, VT, Expand);
770  setOperationAction(ISD::MULHU, VT, Expand);
771  setOperationAction(ISD::SDIVREM, VT, Expand);
772  setOperationAction(ISD::UDIVREM, VT, Expand);
773  setOperationAction(ISD::CTPOP, VT, Expand);
774  setOperationAction(ISD::CTTZ, VT, Expand);
775  setOperationAction(ISD::CTLZ, VT, Expand);
776  setOperationAction(ISD::ROTL, VT, Expand);
777  setOperationAction(ISD::ROTR, VT, Expand);
778  setOperationAction(ISD::BSWAP, VT, Expand);
779  setOperationAction(ISD::SETCC, VT, Expand);
780  setOperationAction(ISD::FP_TO_UINT, VT, Expand);
781  setOperationAction(ISD::FP_TO_SINT, VT, Expand);
782  setOperationAction(ISD::UINT_TO_FP, VT, Expand);
783  setOperationAction(ISD::SINT_TO_FP, VT, Expand);
785  setOperationAction(ISD::TRUNCATE, VT, Expand);
788  setOperationAction(ISD::ANY_EXTEND, VT, Expand);
789  setOperationAction(ISD::SELECT_CC, VT, Expand);
790  for (MVT InnerVT : MVT::vector_valuetypes()) {
791  setTruncStoreAction(InnerVT, VT, Expand);
792 
793  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
794  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
795 
796  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
797  // types, we have to deal with them whether we ask for Expansion or not.
798  // Setting Expand causes its own optimisation problems though, so leave
799  // them legal.
800  if (VT.getVectorElementType() == MVT::i1)
801  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
802 
803  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
804  // split/scalarized right now.
805  if (VT.getVectorElementType() == MVT::f16)
806  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
807  }
808  }
809 
810  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
811  // with -msoft-float, disable use of MMX as well.
812  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
813  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
814  // No operations on x86mmx supported, everything uses intrinsics.
815  }
816 
817  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
818  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
819  : &X86::VR128RegClass);
820 
830 
833 
835  }
836 
837  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
838  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
839  : &X86::VR128RegClass);
840 
841  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
842  // registers cannot be used even for integer operations.
843  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
844  : &X86::VR128RegClass);
845  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
846  : &X86::VR128RegClass);
847  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
848  : &X86::VR128RegClass);
849  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
850  : &X86::VR128RegClass);
851 
852  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
858  }
859 
864  }
865 
869 
883 
884  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
886  setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
887  setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
888  setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
889  }
890 
903 
905  // Use widening instead of promotion.
906  for (auto VT : { MVT::v8i8, MVT::v4i8, MVT::v2i8,
907  MVT::v4i16, MVT::v2i16 }) {
912  }
913  }
914 
918 
919  // Provide custom widening for v2f32 setcc. This is really for VLX when
920  // setcc result type returns v2i1/v4i1 vector for v2f32/v4f32 leading to
921  // type legalization changing the result type to v4i1 during widening.
922  // It works fine for SSE2 and is probably faster so no need to qualify with
923  // VLX support.
926 
927  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
931 
932  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
933  // setcc all the way to isel and prefer SETGT in some isel patterns.
936  }
937 
938  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
944  }
945 
946  // We support custom legalizing of sext and anyext loads for specific
947  // memory vector types which we can load as a scalar (or sequence of
948  // scalars) and extend in-register to a legal 128-bit vector type. For sext
949  // loads these must work with a single scalar load.
951  for (MVT VT : MVT::integer_vector_valuetypes()) {
958  }
959  }
960 
961  for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
965 
966  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
967  continue;
968 
971  }
972 
973  // Custom lower v2i64 and v2f64 selects.
979 
982 
983  // Custom legalize these to avoid over promotion or custom promotion.
994 
995  // By marking FP_TO_SINT v8i16 as Custom, will trick type legalization into
996  // promoting v8i8 FP_TO_UINT into FP_TO_SINT. When the v8i16 FP_TO_SINT is
997  // split again based on the input type, this will cause an AssertSExt i16 to
998  // be emitted instead of an AssertZExt. This will allow packssdw followed by
999  // packuswb to be used to truncate to v8i8. This is necessary since packusdw
1000  // isn't available until sse4.1.
1002 
1005 
1007 
1008  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1010 
1013 
1014  // We want to legalize this to an f64 load rather than an i64 load on
1015  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1016  // store.
1023 
1027  if (!Subtarget.hasAVX512())
1029 
1033 
1036 
1043  } else {
1045  }
1046 
1047  // In the customized shift lowering, the legal v4i32/v2i64 cases
1048  // in AVX2 will be recognized.
1049  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1053  }
1054 
1057 
1058  // With AVX512, expanding (and promoting the shifts) is better.
1059  if (!Subtarget.hasAVX512())
1061  }
1062 
1063  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1072 
1073  // These might be better off as horizontal vector ops.
1078  }
1079 
1080  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1081  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1082  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1083  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1084  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1085  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1087  }
1088 
1097 
1098  // FIXME: Do we need to handle scalar-to-vector here?
1100 
1101  // We directly match byte blends in the backend as they match the VSELECT
1102  // condition form.
1104 
1105  // SSE41 brings specific instructions for doing vector sign extend even in
1106  // cases where we don't have SRA.
1107  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1110  }
1111 
1113  // Avoid narrow result types when widening. The legal types are listed
1114  // in the next loop.
1115  for (MVT VT : MVT::integer_vector_valuetypes()) {
1119  }
1120  }
1121 
1122  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1123  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1132  }
1133 
1134  // i8 vectors are custom because the source register and source
1135  // source memory operand types are not the same width.
1137  }
1138 
1139  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1140  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1143 
1144  // XOP can efficiently perform BITREVERSE with VPPERM.
1145  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1147 
1148  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1151  }
1152 
1153  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1154  bool HasInt256 = Subtarget.hasInt256();
1155 
1156  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1157  : &X86::VR256RegClass);
1158  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1159  : &X86::VR256RegClass);
1160  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1161  : &X86::VR256RegClass);
1162  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1163  : &X86::VR256RegClass);
1164  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1165  : &X86::VR256RegClass);
1166  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1167  : &X86::VR256RegClass);
1168 
1169  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1178  }
1179 
1180  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1181  // even though v8i16 is a legal type.
1185 
1187 
1189 
1190  if (!Subtarget.hasAVX512())
1192 
1193  // In the customized shift lowering, the legal v8i32/v4i64 cases
1194  // in AVX2 will be recognized.
1195  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1199  }
1200 
1201  // These types need custom splitting if their input is a 128-bit vector.
1206 
1209 
1210  // With BWI, expanding (and promoting the shifts) is the better.
1211  if (!Subtarget.hasBWI())
1213 
1220 
1221  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1225  }
1226 
1231 
1232  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1236 
1237  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1238  // setcc all the way to isel and prefer SETGT in some isel patterns.
1241  }
1242 
1243  if (Subtarget.hasAnyFMA()) {
1244  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1247  }
1248 
1249  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1250  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1251  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1252  }
1253 
1256  setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1258 
1261  setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1262  setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1265 
1271 
1272  setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1273  setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1274  setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1275  setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1276  setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1277  setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1278  setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1279  setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1280 
1281  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1282  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1283  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1284  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1285  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1286  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1287  }
1288 
1289  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1292  }
1293 
1294  if (HasInt256) {
1295  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1296  // when we have a 256bit-wide blend with immediate.
1298 
1299  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1300  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1307  }
1308  }
1309 
1310  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1312  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1314  }
1315 
1316  // Extract subvector is special because the value type
1317  // (result) is 128-bit but the source is 256-bit wide.
1318  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1319  MVT::v4f32, MVT::v2f64 }) {
1321  }
1322 
1323  // Custom lower several nodes for 256-bit types.
1325  MVT::v8f32, MVT::v4f64 }) {
1328  setOperationAction(ISD::VSELECT, VT, Custom);
1334  setOperationAction(ISD::STORE, VT, Custom);
1335  }
1336 
1337  if (HasInt256) {
1339 
1340  // Custom legalize 2x32 to get a little better code.
1343 
1344  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1346  setOperationAction(ISD::MGATHER, VT, Custom);
1347  }
1348  }
1349 
1350  // This block controls legalization of the mask vector sizes that are
1351  // available with AVX512. 512-bit vectors are in a separate block controlled
1352  // by useAVX512Regs.
1353  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1354  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1355  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1356  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1357  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1358  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1359 
1363 
1370 
1371  // There is no byte sized k-register load or store without AVX512DQ.
1372  if (!Subtarget.hasDQI()) {
1377 
1382  }
1383 
1384  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1385  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1389  }
1390 
1391  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1402 
1409  setOperationAction(ISD::VSELECT, VT, Expand);
1410  }
1411 
1412  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1414  }
1415 
1416  // This block controls legalization for 512-bit operations with 32/64 bit
1417  // elements. 512-bits can be disabled based on prefer-vector-width and
1418  // required-vector-width function attributes.
1419  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1420  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1421  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1422  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1423  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1424 
1425  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1431  }
1432 
1433  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1438  }
1439 
1450 
1452 
1458 
1459  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1460  // to 512-bit rather than use the AVX2 instructions so that we can use
1461  // k-masks.
1462  if (!Subtarget.hasVLX()) {
1463  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1467  }
1468  }
1469 
1478 
1480  // Need to custom widen this if we don't have AVX512BW.
1484  }
1485 
1486  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1492 
1494  }
1495 
1496  // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1497  for (auto VT : {MVT::v16i32, MVT::v8i64, MVT::v64i8}) {
1500  }
1501 
1506 
1509 
1512 
1513  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1527 
1528  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1529  // setcc all the way to isel and prefer SETGT in some isel patterns.
1532  }
1533 
1534  if (Subtarget.hasDQI()) {
1539 
1541  }
1542 
1543  if (Subtarget.hasCDI()) {
1544  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1545  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1547  }
1548  } // Subtarget.hasCDI()
1549 
1550  if (Subtarget.hasVPOPCNTDQ()) {
1551  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1553  }
1554 
1555  // Extract subvector is special because the value type
1556  // (result) is 256-bit but the source is 512-bit wide.
1557  // 128-bit was made Legal under AVX1.
1558  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1561 
1562  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1574  }
1575  // Need to custom split v32i16/v64i8 bitcasts.
1576  if (!Subtarget.hasBWI()) {
1579  }
1580 
1581  if (Subtarget.hasVBMI2()) {
1582  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1585  }
1586  }
1587  }// has AVX-512
1588 
1589  // This block controls legalization for operations that don't have
1590  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1591  // narrower widths.
1592  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1593  // These operations are handled on non-VLX by artificially widening in
1594  // isel patterns.
1595  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1596 
1602 
1603  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1609  }
1610 
1611  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1614  }
1615 
1616  // Custom legalize 2x32 to get a little better code.
1619 
1620  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1623 
1624  if (Subtarget.hasDQI()) {
1625  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1630 
1632  }
1633  }
1634 
1635  if (Subtarget.hasCDI()) {
1636  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1638  }
1639  } // Subtarget.hasCDI()
1640 
1641  if (Subtarget.hasVPOPCNTDQ()) {
1642  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1644  }
1645  }
1646 
1647  // This block control legalization of v32i1/v64i1 which are available with
1648  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1649  // useBWIRegs.
1650  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1651  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1652  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1653 
1654  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1658  setOperationAction(ISD::VSELECT, VT, Expand);
1663 
1671  }
1672 
1677  for (auto VT : { MVT::v16i1, MVT::v32i1 })
1679 
1680  // Extends from v32i1 masks to 256-bit vectors.
1684  }
1685 
1686  // This block controls legalization for v32i16 and v64i8. 512-bits can be
1687  // disabled based on prefer-vector-width and required-vector-width function
1688  // attributes.
1689  if (!Subtarget.useSoftFloat() && Subtarget.useBWIRegs()) {
1690  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1691  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1692 
1693  // Extends from v64i1 masks to 512-bit vectors.
1697 
1721 
1724 
1726 
1727  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1748 
1749  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1750  // setcc all the way to isel and prefer SETGT in some isel patterns.
1753  }
1754 
1755  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1757  }
1758 
1759  if (Subtarget.hasBITALG()) {
1760  for (auto VT : { MVT::v64i8, MVT::v32i16 })
1762  }
1763 
1764  if (Subtarget.hasVBMI2()) {
1767  }
1768  }
1769 
1770  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1771  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1772  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1773  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1774  }
1775 
1776  // These operations are handled on non-VLX by artificially widening in
1777  // isel patterns.
1778  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1779 
1780  if (Subtarget.hasBITALG()) {
1781  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1783  }
1784  }
1785 
1786  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1792 
1798 
1799  if (Subtarget.hasDQI()) {
1800  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1801  // v2f32 UINT_TO_FP is already custom under SSE2.
1804  "Unexpected operation action!");
1805  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1808  }
1809 
1810  if (Subtarget.hasBWI()) {
1813  }
1814 
1815  if (Subtarget.hasVBMI2()) {
1816  // TODO: Make these legal even without VLX?
1817  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1821  }
1822  }
1823 
1826  }
1827 
1828  // We want to custom lower some of our intrinsics.
1832  if (!Subtarget.is64Bit()) {
1834  }
1835 
1836  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1837  // handle type legalization for these operations here.
1838  //
1839  // FIXME: We really should do custom legalization for addition and
1840  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1841  // than generic legalization for 64-bit multiplication-with-overflow, though.
1842  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1843  if (VT == MVT::i64 && !Subtarget.is64Bit())
1844  continue;
1845  // Add/Sub/Mul with overflow operations are custom lowered.
1852 
1853  // Support carry in as value rather than glue.
1857  }
1858 
1859  if (!Subtarget.is64Bit()) {
1860  // These libcalls are not available in 32-bit.
1861  setLibcallName(RTLIB::SHL_I128, nullptr);
1862  setLibcallName(RTLIB::SRL_I128, nullptr);
1863  setLibcallName(RTLIB::SRA_I128, nullptr);
1864  setLibcallName(RTLIB::MUL_I128, nullptr);
1865  }
1866 
1867  // Combine sin / cos into _sincos_stret if it is available.
1868  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1869  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1872  }
1873 
1874  if (Subtarget.isTargetWin64()) {
1881  }
1882 
1883  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1884  // is. We should promote the value to 64-bits to solve this.
1885  // This is what the CRT headers do - `fmodf` is an inline header
1886  // function casting to f64 and calling `fmod`.
1887  if (Subtarget.is32Bit() &&
1888  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
1889  for (ISD::NodeType Op :
1894 
1895  // We have target-specific dag combine patterns for the following nodes:
1937 
1939 
1940  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1942  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1944  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1946 
1947  // TODO: These control memcmp expansion in CGP and could be raised higher, but
1948  // that needs to benchmarked and balanced with the potential use of vector
1949  // load/store types (PR33329, PR33914).
1950  MaxLoadsPerMemcmp = 2;
1952 
1953  // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
1955 
1956  // An out-of-order CPU can speculatively execute past a predictable branch,
1957  // but a conditional move could be stalled by an expensive earlier operation.
1958  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
1959  EnableExtLdPromotion = true;
1961 
1963 }
1964 
1965 // This has so far only been implemented for 64-bit MachO.
1967  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
1968 }
1969 
1971  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
1972  return Subtarget.getTargetTriple().isOSMSVCRT();
1973 }
1974 
1976  const SDLoc &DL) const {
1977  EVT PtrTy = getPointerTy(DAG.getDataLayout());
1978  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
1979  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
1980  return SDValue(Node, 0);
1981 }
1982 
1985  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1986  return TypeSplitVector;
1987 
1989  VT.getVectorNumElements() != 1 &&
1990  VT.getVectorElementType() != MVT::i1)
1991  return TypeWidenVector;
1992 
1994 }
1995 
1997  CallingConv::ID CC,
1998  EVT VT) const {
1999  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
2000  return MVT::v32i8;
2001  // FIXME: Should we just make these types legal and custom split operations?
2002  if ((VT == MVT::v32i16 || VT == MVT::v64i8) &&
2003  Subtarget.hasAVX512() && !Subtarget.hasBWI() && !EnableOldKNLABI)
2004  return MVT::v16i32;
2005  return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
2006 }
2007 
2009  CallingConv::ID CC,
2010  EVT VT) const {
2011  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
2012  return 1;
2013  // FIXME: Should we just make these types legal and custom split operations?
2014  if ((VT == MVT::v32i16 || VT == MVT::v64i8) &&
2015  Subtarget.hasAVX512() && !Subtarget.hasBWI() && !EnableOldKNLABI)
2016  return 1;
2017  return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
2018 }
2019 
2022  EVT VT) const {
2023  if (!VT.isVector())
2024  return MVT::i8;
2025 
2026  if (Subtarget.hasAVX512()) {
2027  const unsigned NumElts = VT.getVectorNumElements();
2028 
2029  // Figure out what this type will be legalized to.
2030  EVT LegalVT = VT;
2031  while (getTypeAction(Context, LegalVT) != TypeLegal)
2032  LegalVT = getTypeToTransformTo(Context, LegalVT);
2033 
2034  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2035  if (LegalVT.getSimpleVT().is512BitVector())
2036  return EVT::getVectorVT(Context, MVT::i1, NumElts);
2037 
2038  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2039  // If we legalized to less than a 512-bit vector, then we will use a vXi1
2040  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2041  // vXi16/vXi8.
2042  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2043  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2044  return EVT::getVectorVT(Context, MVT::i1, NumElts);
2045  }
2046  }
2047 
2049 }
2050 
2051 /// Helper for getByValTypeAlignment to determine
2052 /// the desired ByVal argument alignment.
2053 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
2054  if (MaxAlign == 16)
2055  return;
2056  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2057  if (VTy->getBitWidth() == 128)
2058  MaxAlign = 16;
2059  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2060  unsigned EltAlign = 0;
2061  getMaxByValAlign(ATy->getElementType(), EltAlign);
2062  if (EltAlign > MaxAlign)
2063  MaxAlign = EltAlign;
2064  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2065  for (auto *EltTy : STy->elements()) {
2066  unsigned EltAlign = 0;
2067  getMaxByValAlign(EltTy, EltAlign);
2068  if (EltAlign > MaxAlign)
2069  MaxAlign = EltAlign;
2070  if (MaxAlign == 16)
2071  break;
2072  }
2073  }
2074 }
2075 
2076 /// Return the desired alignment for ByVal aggregate
2077 /// function arguments in the caller parameter area. For X86, aggregates
2078 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2079 /// are at 4-byte boundaries.
2081  const DataLayout &DL) const {
2082  if (Subtarget.is64Bit()) {
2083  // Max of 8 and alignment of type.
2084  unsigned TyAlign = DL.getABITypeAlignment(Ty);
2085  if (TyAlign > 8)
2086  return TyAlign;
2087  return 8;
2088  }
2089 
2090  unsigned Align = 4;
2091  if (Subtarget.hasSSE1())
2092  getMaxByValAlign(Ty, Align);
2093  return Align;
2094 }
2095 
2096 /// Returns the target specific optimal type for load
2097 /// and store operations as a result of memset, memcpy, and memmove
2098 /// lowering. If DstAlign is zero that means it's safe to destination
2099 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
2100 /// means there isn't a need to check it against alignment requirement,
2101 /// probably because the source does not need to be loaded. If 'IsMemset' is
2102 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
2103 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
2104 /// source is constant so it does not need to be loaded.
2105 /// It returns EVT::Other if the type should be determined using generic
2106 /// target-independent logic.
2107 /// For vector ops we check that the overall size isn't larger than our
2108 /// preferred vector width.
2110  uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
2111  bool ZeroMemset, bool MemcpyStrSrc,
2112  const AttributeList &FuncAttributes) const {
2113  if (!FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat)) {
2114  if (Size >= 16 && (!Subtarget.isUnalignedMem16Slow() ||
2115  ((DstAlign == 0 || DstAlign >= 16) &&
2116  (SrcAlign == 0 || SrcAlign >= 16)))) {
2117  // FIXME: Check if unaligned 32-byte accesses are slow.
2118  if (Size >= 32 && Subtarget.hasAVX() &&
2119  (Subtarget.getPreferVectorWidth() >= 256)) {
2120  // Although this isn't a well-supported type for AVX1, we'll let
2121  // legalization and shuffle lowering produce the optimal codegen. If we
2122  // choose an optimal type with a vector element larger than a byte,
2123  // getMemsetStores() may create an intermediate splat (using an integer
2124  // multiply) before we splat as a vector.
2125  return MVT::v32i8;
2126  }
2127  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2128  return MVT::v16i8;
2129  // TODO: Can SSE1 handle a byte vector?
2130  // If we have SSE1 registers we should be able to use them.
2131  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2132  (Subtarget.getPreferVectorWidth() >= 128))
2133  return MVT::v4f32;
2134  } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
2135  !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2136  // Do not use f64 to lower memcpy if source is string constant. It's
2137  // better to use i32 to avoid the loads.
2138  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2139  // The gymnastics of splatting a byte value into an XMM register and then
2140  // only using 8-byte stores (because this is a CPU with slow unaligned
2141  // 16-byte accesses) makes that a loser.
2142  return MVT::f64;
2143  }
2144  }
2145  // This is a compromise. If we reach here, unaligned accesses may be slow on
2146  // this target. However, creating smaller, aligned accesses could be even
2147  // slower and would certainly be a lot more code.
2148  if (Subtarget.is64Bit() && Size >= 8)
2149  return MVT::i64;
2150  return MVT::i32;
2151 }
2152 
2154  if (VT == MVT::f32)
2155  return X86ScalarSSEf32;
2156  else if (VT == MVT::f64)
2157  return X86ScalarSSEf64;
2158  return true;
2159 }
2160 
2162  EVT VT, unsigned, unsigned Align, MachineMemOperand::Flags Flags,
2163  bool *Fast) const {
2164  if (Fast) {
2165  switch (VT.getSizeInBits()) {
2166  default:
2167  // 8-byte and under are always assumed to be fast.
2168  *Fast = true;
2169  break;
2170  case 128:
2171  *Fast = !Subtarget.isUnalignedMem16Slow();
2172  break;
2173  case 256:
2174  *Fast = !Subtarget.isUnalignedMem32Slow();
2175  break;
2176  // TODO: What about AVX-512 (512-bit) accesses?
2177  }
2178  }
2179  // NonTemporal vector memory ops must be aligned.
2180  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2181  // NT loads can only be vector aligned, so if its less aligned than the
2182  // minimum vector size (which we can split the vector down to), we might as
2183  // well use a regular unaligned vector load.
2184  // We don't have any NT loads pre-SSE41.
2185  if (!!(Flags & MachineMemOperand::MOLoad))
2186  return (Align < 16 || !Subtarget.hasSSE41());
2187  return false;
2188  }
2189  // Misaligned accesses of any size are always allowed.
2190  return true;
2191 }
2192 
2193 /// Return the entry encoding for a jump table in the
2194 /// current function. The returned value is a member of the
2195 /// MachineJumpTableInfo::JTEntryKind enum.
2197  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2198  // symbol.
2199  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2201 
2202  // Otherwise, use the normal jump table encoding heuristics.
2204 }
2205 
2207  return Subtarget.useSoftFloat();
2208 }
2209 
2211  ArgListTy &Args) const {
2212 
2213  // Only relabel X86-32 for C / Stdcall CCs.
2214  if (Subtarget.is64Bit())
2215  return;
2216  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2217  return;
2218  unsigned ParamRegs = 0;
2219  if (auto *M = MF->getFunction().getParent())
2220  ParamRegs = M->getNumberRegisterParameters();
2221 
2222  // Mark the first N int arguments as having reg
2223  for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
2224  Type *T = Args[Idx].Ty;
2225  if (T->isIntOrPtrTy())
2226  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2227  unsigned numRegs = 1;
2228  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2229  numRegs = 2;
2230  if (ParamRegs < numRegs)
2231  return;
2232  ParamRegs -= numRegs;
2233  Args[Idx].IsInReg = true;
2234  }
2235  }
2236 }
2237 
2238 const MCExpr *
2240  const MachineBasicBlock *MBB,
2241  unsigned uid,MCContext &Ctx) const{
2242  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2243  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2244  // entries.
2245  return MCSymbolRefExpr::create(MBB->getSymbol(),
2247 }
2248 
2249 /// Returns relocation base for the given PIC jumptable.
2251  SelectionDAG &DAG) const {
2252  if (!Subtarget.is64Bit())
2253  // This doesn't have SDLoc associated with it, but is not really the
2254  // same as a Register.
2255  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2256  getPointerTy(DAG.getDataLayout()));
2257  return Table;
2258 }
2259 
2260 /// This returns the relocation base for the given PIC jumptable,
2261 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2264  MCContext &Ctx) const {
2265  // X86-64 uses RIP relative addressing based on the jump table label.
2266  if (Subtarget.isPICStyleRIPRel())
2267  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2268 
2269  // Otherwise, the reference is relative to the PIC base.
2270  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2271 }
2272 
2273 std::pair<const TargetRegisterClass *, uint8_t>
2275  MVT VT) const {
2276  const TargetRegisterClass *RRC = nullptr;
2277  uint8_t Cost = 1;
2278  switch (VT.SimpleTy) {
2279  default:
2281  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2282  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2283  break;
2284  case MVT::x86mmx:
2285  RRC = &X86::VR64RegClass;
2286  break;
2287  case MVT::f32: case MVT::f64:
2288  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2289  case MVT::v4f32: case MVT::v2f64:
2290  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2291  case MVT::v8f32: case MVT::v4f64:
2292  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2293  case MVT::v16f32: case MVT::v8f64:
2294  RRC = &X86::VR128XRegClass;
2295  break;
2296  }
2297  return std::make_pair(RRC, Cost);
2298 }
2299 
2300 unsigned X86TargetLowering::getAddressSpace() const {
2301  if (Subtarget.is64Bit())
2302  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2303  return 256;
2304 }
2305 
2306 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2307  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2308  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2309 }
2310 
2312  unsigned Offset, unsigned AddressSpace) {
2315  Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2316 }
2317 
2319  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2320  // tcbhead_t; use it instead of the usual global variable (see
2321  // sysdeps/{i386,x86_64}/nptl/tls.h)
2322  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2323  if (Subtarget.isTargetFuchsia()) {
2324  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2325  return SegmentOffset(IRB, 0x10, getAddressSpace());
2326  } else {
2327  // %fs:0x28, unless we're using a Kernel code model, in which case
2328  // it's %gs:0x28. gs:0x14 on i386.
2329  unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2330  return SegmentOffset(IRB, Offset, getAddressSpace());
2331  }
2332  }
2333 
2334  return TargetLowering::getIRStackGuard(IRB);
2335 }
2336 
2338  // MSVC CRT provides functionalities for stack protection.
2339  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2341  // MSVC CRT has a global variable holding security cookie.
2342  M.getOrInsertGlobal("__security_cookie",
2344 
2345  // MSVC CRT has a function to validate security cookie.
2346  FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2347  "__security_check_cookie", Type::getVoidTy(M.getContext()),
2349  if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2350  F->setCallingConv(CallingConv::X86_FastCall);
2351  F->addAttribute(1, Attribute::AttrKind::InReg);
2352  }
2353  return;
2354  }
2355  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2356  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2357  return;
2359 }
2360 
2362  // MSVC CRT has a global variable holding security cookie.
2363  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2365  return M.getGlobalVariable("__security_cookie");
2366  }
2368 }
2369 
2371  // MSVC CRT has a function to validate security cookie.
2372  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2374  return M.getFunction("__security_check_cookie");
2375  }
2377 }
2378 
2380  if (Subtarget.getTargetTriple().isOSContiki())
2381  return getDefaultSafeStackPointerLocation(IRB, false);
2382 
2383  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2384  // definition of TLS_SLOT_SAFESTACK in
2385  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2386  if (Subtarget.isTargetAndroid()) {
2387  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2388  // %gs:0x24 on i386
2389  unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2390  return SegmentOffset(IRB, Offset, getAddressSpace());
2391  }
2392 
2393  // Fuchsia is similar.
2394  if (Subtarget.isTargetFuchsia()) {
2395  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2396  return SegmentOffset(IRB, 0x18, getAddressSpace());
2397  }
2398 
2400 }
2401 
2403  unsigned DestAS) const {
2404  assert(SrcAS != DestAS && "Expected different address spaces!");
2405 
2406  return SrcAS < 256 && DestAS < 256;
2407 }
2408 
2409 //===----------------------------------------------------------------------===//
2410 // Return Value Calling Convention Implementation
2411 //===----------------------------------------------------------------------===//
2412 
2413 bool X86TargetLowering::CanLowerReturn(
2414  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2415  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2417  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2418  return CCInfo.CheckReturn(Outs, RetCC_X86);
2419 }
2420 
2421 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2422  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2423  return ScratchRegs;
2424 }
2425 
2426 /// Lowers masks values (v*i1) to the local register values
2427 /// \returns DAG node after lowering to register type
2428 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2429  const SDLoc &Dl, SelectionDAG &DAG) {
2430  EVT ValVT = ValArg.getValueType();
2431 
2432  if (ValVT == MVT::v1i1)
2433  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2434  DAG.getIntPtrConstant(0, Dl));
2435 
2436  if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2437  (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2438  // Two stage lowering might be required
2439  // bitcast: v8i1 -> i8 / v16i1 -> i16
2440  // anyextend: i8 -> i32 / i16 -> i32
2441  EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2442  SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2443  if (ValLoc == MVT::i32)
2444  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2445  return ValToCopy;
2446  }
2447 
2448  if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2449  (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2450  // One stage lowering is required
2451  // bitcast: v32i1 -> i32 / v64i1 -> i64
2452  return DAG.getBitcast(ValLoc, ValArg);
2453  }
2454 
2455  return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2456 }
2457 
2458 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2460  const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
2461  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
2462  CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2463  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
2464  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2465  assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
2466  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2467  "The value should reside in two registers");
2468 
2469  // Before splitting the value we cast it to i64
2470  Arg = DAG.getBitcast(MVT::i64, Arg);
2471 
2472  // Splitting the value into two i32 types
2473  SDValue Lo, Hi;
2474  Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2475  DAG.getConstant(0, Dl, MVT::i32));
2476  Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2477  DAG.getConstant(1, Dl, MVT::i32));
2478 
2479  // Attach the two i32 types into corresponding registers
2480  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2481  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2482 }
2483 
2484 SDValue
2485 X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2486  bool isVarArg,
2487  const SmallVectorImpl<ISD::OutputArg> &Outs,
2488  const SmallVectorImpl<SDValue> &OutVals,
2489  const SDLoc &dl, SelectionDAG &DAG) const {
2490  MachineFunction &MF = DAG.getMachineFunction();
2492 
2493  // In some cases we need to disable registers from the default CSR list.
2494  // For example, when they are used for argument passing.
2495  bool ShouldDisableCalleeSavedRegister =
2496  CallConv == CallingConv::X86_RegCall ||
2497  MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2498 
2499  if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2500  report_fatal_error("X86 interrupts may not return any value");
2501 
2503  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2504  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2505 
2506  SDValue Flag;
2507  SmallVector<SDValue, 6> RetOps;
2508  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2509  // Operand #1 = Bytes To Pop
2510  RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2511  MVT::i32));
2512 
2513  // Copy the result values into the output registers.
2514  for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2515  ++I, ++OutsIndex) {
2516  CCValAssign &VA = RVLocs[I];
2517  assert(VA.isRegLoc() && "Can only return in registers!");
2518 
2519  // Add the register to the CalleeSaveDisableRegs list.
2520  if (ShouldDisableCalleeSavedRegister)
2522 
2523  SDValue ValToCopy = OutVals[OutsIndex];
2524  EVT ValVT = ValToCopy.getValueType();
2525 
2526  // Promote values to the appropriate types.
2527  if (VA.getLocInfo() == CCValAssign::SExt)
2528  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2529  else if (VA.getLocInfo() == CCValAssign::ZExt)
2530  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2531  else if (VA.getLocInfo() == CCValAssign::AExt) {
2532  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2533  ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2534  else
2535  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2536  }
2537  else if (VA.getLocInfo() == CCValAssign::BCvt)
2538  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2539 
2541  "Unexpected FP-extend for return value.");
2542 
2543  // If this is x86-64, and we disabled SSE, we can't return FP values,
2544  // or SSE or MMX vectors.
2545  if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2546  VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2547  (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {
2548  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2549  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2550  } else if (ValVT == MVT::f64 &&
2551  (Subtarget.is64Bit() && !Subtarget.hasSSE2())) {
2552  // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2553  // llvm-gcc has never done it right and no one has noticed, so this
2554  // should be OK for now.
2555  errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2556  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2557  }
2558 
2559  // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2560  // the RET instruction and handled by the FP Stackifier.
2561  if (VA.getLocReg() == X86::FP0 ||
2562  VA.getLocReg() == X86::FP1) {
2563  // If this is a copy from an xmm register to ST(0), use an FPExtend to
2564  // change the value to the FP stack register class.
2565  if (isScalarFPTypeInSSEReg(VA.getValVT()))
2566  ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2567  RetOps.push_back(ValToCopy);
2568  // Don't emit a copytoreg.
2569  continue;
2570  }
2571 
2572  // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2573  // which is returned in RAX / RDX.
2574  if (Subtarget.is64Bit()) {
2575  if (ValVT == MVT::x86mmx) {
2576  if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2577  ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2578  ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2579  ValToCopy);
2580  // If we don't have SSE2 available, convert to v4f32 so the generated
2581  // register is legal.
2582  if (!Subtarget.hasSSE2())
2583  ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2584  }
2585  }
2586  }
2587 
2589 
2590  if (VA.needsCustom()) {
2591  assert(VA.getValVT() == MVT::v64i1 &&
2592  "Currently the only custom case is when we split v64i1 to 2 regs");
2593 
2594  Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
2595  Subtarget);
2596 
2597  assert(2 == RegsToPass.size() &&
2598  "Expecting two registers after Pass64BitArgInRegs");
2599 
2600  // Add the second register to the CalleeSaveDisableRegs list.
2601  if (ShouldDisableCalleeSavedRegister)
2602  MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2603  } else {
2604  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2605  }
2606 
2607  // Add nodes to the DAG and add the values into the RetOps list
2608  for (auto &Reg : RegsToPass) {
2609  Chain = DAG.getCopyToReg(Chain, dl, Reg.first, Reg.second, Flag);
2610  Flag = Chain.getValue(1);
2611  RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2612  }
2613  }
2614 
2615  // Swift calling convention does not require we copy the sret argument
2616  // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2617 
2618  // All x86 ABIs require that for returning structs by value we copy
2619  // the sret argument into %rax/%eax (depending on ABI) for the return.
2620  // We saved the argument into a virtual register in the entry block,
2621  // so now we copy the value out and into %rax/%eax.
2622  //
2623  // Checking Function.hasStructRetAttr() here is insufficient because the IR
2624  // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2625  // false, then an sret argument may be implicitly inserted in the SelDAG. In
2626  // either case FuncInfo->setSRetReturnReg() will have been called.
2627  if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2628  // When we have both sret and another return value, we should use the
2629  // original Chain stored in RetOps[0], instead of the current Chain updated
2630  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2631 
2632  // For the case of sret and another return value, we have
2633  // Chain_0 at the function entry
2634  // Chain_1 = getCopyToReg(Chain_0) in the above loop
2635  // If we use Chain_1 in getCopyFromReg, we will have
2636  // Val = getCopyFromReg(Chain_1)
2637  // Chain_2 = getCopyToReg(Chain_1, Val) from below
2638 
2639  // getCopyToReg(Chain_0) will be glued together with
2640  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2641  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2642  // Data dependency from Unit B to Unit A due to usage of Val in
2643  // getCopyToReg(Chain_1, Val)
2644  // Chain dependency from Unit A to Unit B
2645 
2646  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2647  SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2648  getPointerTy(MF.getDataLayout()));
2649 
2650  unsigned RetValReg
2651  = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2652  X86::RAX : X86::EAX;
2653  Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2654  Flag = Chain.getValue(1);
2655 
2656  // RAX/EAX now acts like a return value.
2657  RetOps.push_back(
2658  DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2659 
2660  // Add the returned register to the CalleeSaveDisableRegs list.
2661  if (ShouldDisableCalleeSavedRegister)
2662  MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2663  }
2664 
2665  const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2666  const MCPhysReg *I =
2668  if (I) {
2669  for (; *I; ++I) {
2670  if (X86::GR64RegClass.contains(*I))
2671  RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2672  else
2673  llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2674  }
2675  }
2676 
2677  RetOps[0] = Chain; // Update chain.
2678 
2679  // Add the flag if we have it.
2680  if (Flag.getNode())
2681  RetOps.push_back(Flag);
2682 
2684  if (CallConv == CallingConv::X86_INTR)
2685  opcode = X86ISD::IRET;
2686  return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2687 }
2688 
2689 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2690  if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2691  return false;
2692 
2693  SDValue TCChain = Chain;
2694  SDNode *Copy = *N->use_begin();
2695  if (Copy->getOpcode() == ISD::CopyToReg) {
2696  // If the copy has a glue operand, we conservatively assume it isn't safe to
2697  // perform a tail call.
2698  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2699  return false;
2700  TCChain = Copy->getOperand(0);
2701  } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2702  return false;
2703 
2704  bool HasRet = false;
2705  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2706  UI != UE; ++UI) {
2707  if (UI->getOpcode() != X86ISD::RET_FLAG)
2708  return false;
2709  // If we are returning more than one value, we can definitely
2710  // not make a tail call see PR19530
2711  if (UI->getNumOperands() > 4)
2712  return false;
2713  if (UI->getNumOperands() == 4 &&
2714  UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2715  return false;
2716  HasRet = true;
2717  }
2718 
2719  if (!HasRet)
2720  return false;
2721 
2722  Chain = TCChain;
2723  return true;
2724 }
2725 
2726 EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2727  ISD::NodeType ExtendKind) const {
2728  MVT ReturnMVT = MVT::i32;
2729 
2730  bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2731  if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2732  // The ABI does not require i1, i8 or i16 to be extended.
2733  //
2734  // On Darwin, there is code in the wild relying on Clang's old behaviour of
2735  // always extending i8/i16 return values, so keep doing that for now.
2736  // (PR26665).
2737  ReturnMVT = MVT::i8;
2738  }
2739 
2740  EVT MinVT = getRegisterType(Context, ReturnMVT);
2741  return VT.bitsLT(MinVT) ? MinVT : VT;
2742 }
2743 
2744 /// Reads two 32 bit registers and creates a 64 bit mask value.
2745 /// \param VA The current 32 bit value that need to be assigned.
2746 /// \param NextVA The next 32 bit value that need to be assigned.
2747 /// \param Root The parent DAG node.
2748 /// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2749 /// glue purposes. In the case the DAG is already using
2750 /// physical register instead of virtual, we should glue
2751 /// our new SDValue to InFlag SDvalue.
2752 /// \return a new SDvalue of size 64bit.
2754  SDValue &Root, SelectionDAG &DAG,
2755  const SDLoc &Dl, const X86Subtarget &Subtarget,
2756  SDValue *InFlag = nullptr) {
2757  assert((Subtarget.hasBWI()) && "Expected AVX512BW target!");
2758  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2759  assert(VA.getValVT() == MVT::v64i1 &&
2760  "Expecting first location of 64 bit width type");
2761  assert(NextVA.getValVT() == VA.getValVT() &&
2762  "The locations should have the same type");
2763  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2764  "The values should reside in two registers");
2765 
2766  SDValue Lo, Hi;
2767  SDValue ArgValueLo, ArgValueHi;
2768 
2769  MachineFunction &MF = DAG.getMachineFunction();
2770  const TargetRegisterClass *RC = &X86::GR32RegClass;
2771 
2772  // Read a 32 bit value from the registers.
2773  if (nullptr == InFlag) {
2774  // When no physical register is present,
2775  // create an intermediate virtual register.
2776  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2777  ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2778  Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2779  ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2780  } else {
2781  // When a physical register is available read the value from it and glue
2782  // the reads together.
2783  ArgValueLo =
2784  DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2785  *InFlag = ArgValueLo.getValue(2);
2786  ArgValueHi =
2787  DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2788  *InFlag = ArgValueHi.getValue(2);
2789  }
2790 
2791  // Convert the i32 type into v32i1 type.
2792  Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2793 
2794  // Convert the i32 type into v32i1 type.
2795  Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2796 
2797  // Concatenate the two values together.
2798  return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2799 }
2800 
2801 /// The function will lower a register of various sizes (8/16/32/64)
2802 /// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2803 /// \returns a DAG node contains the operand after lowering to mask type.
2804 static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2805  const EVT &ValLoc, const SDLoc &Dl,
2806  SelectionDAG &DAG) {
2807  SDValue ValReturned = ValArg;
2808 
2809  if (ValVT == MVT::v1i1)
2810  return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2811 
2812  if (ValVT == MVT::v64i1) {
2813  // In 32 bit machine, this case is handled by getv64i1Argument
2814  assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
2815  // In 64 bit machine, There is no need to truncate the value only bitcast
2816  } else {
2817  MVT maskLen;
2818  switch (ValVT.getSimpleVT().SimpleTy) {
2819  case MVT::v8i1:
2820  maskLen = MVT::i8;
2821  break;
2822  case MVT::v16i1:
2823  maskLen = MVT::i16;
2824  break;
2825  case MVT::v32i1:
2826  maskLen = MVT::i32;
2827  break;
2828  default:
2829  llvm_unreachable("Expecting a vector of i1 types");
2830  }
2831 
2832  ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
2833  }
2834  return DAG.getBitcast(ValVT, ValReturned);
2835 }
2836 
2837 /// Lower the result values of a call into the
2838 /// appropriate copies out of appropriate physical registers.
2839 ///
2840 SDValue X86TargetLowering::LowerCallResult(
2841  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2842  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2843  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2844  uint32_t *RegMask) const {
2845 
2846  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2847  // Assign locations to each value returned by this call.
2849  bool Is64Bit = Subtarget.is64Bit();
2850  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2851  *DAG.getContext());
2852  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2853 
2854  // Copy all of the result registers out of their specified physreg.
2855  for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
2856  ++I, ++InsIndex) {
2857  CCValAssign &VA = RVLocs[I];
2858  EVT CopyVT = VA.getLocVT();
2859 
2860  // In some calling conventions we need to remove the used registers
2861  // from the register mask.
2862  if (RegMask) {
2863  for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
2864  SubRegs.isValid(); ++SubRegs)
2865  RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2866  }
2867 
2868  // If this is x86-64, and we disabled SSE, we can't return FP values
2869  if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2870  ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
2871  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2872  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2873  }
2874 
2875  // If we prefer to use the value in xmm registers, copy it out as f80 and
2876  // use a truncate to move it from fp stack reg to xmm reg.
2877  bool RoundAfterCopy = false;
2878  if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2880  if (!Subtarget.hasX87())
2881  report_fatal_error("X87 register return with X87 disabled");
2882  CopyVT = MVT::f80;
2883  RoundAfterCopy = (CopyVT != VA.getLocVT());
2884  }
2885 
2886  SDValue Val;
2887  if (VA.needsCustom()) {
2888  assert(VA.getValVT() == MVT::v64i1 &&
2889  "Currently the only custom case is when we split v64i1 to 2 regs");
2890  Val =
2891  getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
2892  } else {
2893  Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
2894  .getValue(1);
2895  Val = Chain.getValue(0);
2896  InFlag = Chain.getValue(2);
2897  }
2898 
2899  if (RoundAfterCopy)
2900  Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2901  // This truncation won't change the value.
2902  DAG.getIntPtrConstant(1, dl));
2903 
2904  if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2905  if (VA.getValVT().isVector() &&
2906  ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2907  (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2908  // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
2909  Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2910  } else
2911  Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2912  }
2913 
2914  InVals.push_back(Val);
2915  }
2916 
2917  return Chain;
2918 }
2919 
2920 //===----------------------------------------------------------------------===//
2921 // C & StdCall & Fast Calling Convention implementation
2922 //===----------------------------------------------------------------------===//
2923 // StdCall calling convention seems to be standard for many Windows' API
2924 // routines and around. It differs from C calling convention just a little:
2925 // callee should clean up the stack, not caller. Symbols should be also
2926 // decorated in some fancy way :) It doesn't support any vector arguments.
2927 // For info on fast calling convention see Fast Calling Convention (tail call)
2928 // implementation LowerX86_32FastCCCallTo.
2929 
2930 /// CallIsStructReturn - Determines whether a call uses struct return
2931 /// semantics.
2936 };
2937 static StructReturnType
2939  if (Outs.empty())
2940  return NotStructReturn;
2941 
2942  const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2943  if (!Flags.isSRet())
2944  return NotStructReturn;
2945  if (Flags.isInReg() || IsMCU)
2946  return RegStructReturn;
2947  return StackStructReturn;
2948 }
2949 
2950 /// Determines whether a function uses struct return semantics.
2951 static StructReturnType
2953  if (Ins.empty())
2954  return NotStructReturn;
2955 
2956  const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2957  if (!Flags.isSRet())
2958  return NotStructReturn;
2959  if (Flags.isInReg() || IsMCU)
2960  return RegStructReturn;
2961  return StackStructReturn;
2962 }
2963 
2964 /// Make a copy of an aggregate at address specified by "Src" to address
2965 /// "Dst" with size and alignment information specified by the specific
2966 /// parameter attribute. The copy will be passed as a byval function parameter.
2968  SDValue Chain, ISD::ArgFlagsTy Flags,
2969  SelectionDAG &DAG, const SDLoc &dl) {
2970  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2971 
2972  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2973  /*isVolatile*/false, /*AlwaysInline=*/true,
2974  /*isTailCall*/false,
2976 }
2977 
2978 /// Return true if the calling convention is one that we can guarantee TCO for.
2980  return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2982  CC == CallingConv::HHVM);
2983 }
2984 
2985 /// Return true if we might ever do TCO for calls with this calling convention.
2987  switch (CC) {
2988  // C calling conventions:
2989  case CallingConv::C:
2990  case CallingConv::Win64:
2992  // Callee pop conventions:
2997  // Swift:
2998  case CallingConv::Swift:
2999  return true;
3000  default:
3001  return canGuaranteeTCO(CC);
3002  }
3003 }
3004 
3005 /// Return true if the function is being made into a tailcall target by
3006 /// changing its ABI.
3007 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
3008  return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
3009 }
3010 
3011 bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3012  auto Attr =
3013  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
3014  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
3015  return false;
3016 
3017  ImmutableCallSite CS(CI);
3018  CallingConv::ID CalleeCC = CS.getCallingConv();
3019  if (!mayTailCallThisCC(CalleeCC))
3020  return false;
3021 
3022  return true;
3023 }
3024 
3025 SDValue
3026 X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
3027  const SmallVectorImpl<ISD::InputArg> &Ins,
3028  const SDLoc &dl, SelectionDAG &DAG,
3029  const CCValAssign &VA,
3030  MachineFrameInfo &MFI, unsigned i) const {
3031  // Create the nodes corresponding to a load from this parameter slot.
3032  ISD::ArgFlagsTy Flags = Ins[i].Flags;
3033  bool AlwaysUseMutable = shouldGuaranteeTCO(
3034  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
3035  bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
3036  EVT ValVT;
3037  MVT PtrVT = getPointerTy(DAG.getDataLayout());
3038 
3039  // If value is passed by pointer we have address passed instead of the value
3040  // itself. No need to extend if the mask value and location share the same
3041  // absolute size.
3042  bool ExtendedInMem =
3043  VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3044  VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
3045 
3046  if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
3047  ValVT = VA.getLocVT();
3048  else
3049  ValVT = VA.getValVT();
3050 
3051  // FIXME: For now, all byval parameter objects are marked mutable. This can be
3052  // changed with more analysis.
3053  // In case of tail call optimization mark all arguments mutable. Since they
3054  // could be overwritten by lowering of arguments in case of a tail call.
3055  if (Flags.isByVal()) {
3056  unsigned Bytes = Flags.getByValSize();
3057  if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3058 
3059  // FIXME: For now, all byval parameter objects are marked as aliasing. This
3060  // can be improved with deeper analysis.
3061  int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3062  /*isAliased=*/true);
3063  return DAG.getFrameIndex(FI, PtrVT);
3064  }
3065 
3066  // This is an argument in memory. We might be able to perform copy elision.
3067  // If the argument is passed directly in memory without any extension, then we
3068  // can perform copy elision. Large vector types, for example, may be passed
3069  // indirectly by pointer.
3070  if (Flags.isCopyElisionCandidate() &&
3071  VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem) {
3072  EVT ArgVT = Ins[i].ArgVT;
3073  SDValue PartAddr;
3074  if (Ins[i].PartOffset == 0) {
3075  // If this is a one-part value or the first part of a multi-part value,
3076  // create a stack object for the entire argument value type and return a
3077  // load from our portion of it. This assumes that if the first part of an
3078  // argument is in memory, the rest will also be in memory.
3079  int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3080  /*IsImmutable=*/false);
3081  PartAddr = DAG.getFrameIndex(FI, PtrVT);
3082  return DAG.getLoad(
3083  ValVT, dl, Chain, PartAddr,
3085  } else {
3086  // This is not the first piece of an argument in memory. See if there is
3087  // already a fixed stack object including this offset. If so, assume it
3088  // was created by the PartOffset == 0 branch above and create a load from
3089  // the appropriate offset into it.
3090  int64_t PartBegin = VA.getLocMemOffset();
3091  int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3092  int FI = MFI.getObjectIndexBegin();
3093  for (; MFI.isFixedObjectIndex(FI); ++FI) {
3094  int64_t ObjBegin = MFI.getObjectOffset(FI);
3095  int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3096  if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3097  break;
3098  }
3099  if (MFI.isFixedObjectIndex(FI)) {
3100  SDValue Addr =
3101  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3102  DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3103  return DAG.getLoad(
3104  ValVT, dl, Chain, Addr,
3106  Ins[i].PartOffset));
3107  }
3108  }
3109  }
3110 
3111  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3112  VA.getLocMemOffset(), isImmutable);
3113 
3114  // Set SExt or ZExt flag.
3115  if (VA.getLocInfo() == CCValAssign::ZExt) {
3116  MFI.setObjectZExt(FI, true);
3117  } else if (VA.getLocInfo() == CCValAssign::SExt) {
3118  MFI.setObjectSExt(FI, true);
3119  }
3120 
3121  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3122  SDValue Val = DAG.getLoad(
3123  ValVT, dl, Chain, FIN,
3125  return ExtendedInMem
3126  ? (VA.getValVT().isVector()
3127  ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3128  : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3129  : Val;
3130 }
3131 
3132 // FIXME: Get this from tablegen.
3134  const X86Subtarget &Subtarget) {
3135  assert(Subtarget.is64Bit());
3136 
3137  if (Subtarget.isCallingConvWin64(CallConv)) {
3138  static const MCPhysReg GPR64ArgRegsWin64[] = {
3139  X86::RCX, X86::RDX, X86::R8, X86::R9
3140  };
3141  return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3142  }
3143 
3144  static const MCPhysReg GPR64ArgRegs64Bit[] = {
3145  X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3146  };
3147  return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3148 }
3149 
3150 // FIXME: Get this from tablegen.
3152  CallingConv::ID CallConv,
3153  const X86Subtarget &Subtarget) {
3154  assert(Subtarget.is64Bit());
3155  if (Subtarget.isCallingConvWin64(CallConv)) {
3156  // The XMM registers which might contain var arg parameters are shadowed
3157  // in their paired GPR. So we only need to save the GPR to their home
3158  // slots.
3159  // TODO: __vectorcall will change this.
3160  return None;
3161  }
3162 
3163  const Function &F = MF.getFunction();
3164  bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
3165  bool isSoftFloat = Subtarget.useSoftFloat();
3166  assert(!(isSoftFloat && NoImplicitFloatOps) &&
3167  "SSE register cannot be used when SSE is disabled!");
3168  if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
3169  // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3170  // registers.
3171  return None;
3172 
3173  static const MCPhysReg XMMArgRegs64Bit[] = {
3174  X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3175  X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3176  };
3177  return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3178 }
3179 
3180 #ifndef NDEBUG
3182  return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
3183  [](const CCValAssign &A, const CCValAssign &B) -> bool {
3184  return A.getValNo() < B.getValNo();
3185  });
3186 }
3187 #endif
3188 
3189 SDValue X86TargetLowering::LowerFormalArguments(
3190  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3191  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3192  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3193  MachineFunction &MF = DAG.getMachineFunction();
3195  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3196 
3197  const Function &F = MF.getFunction();
3198  if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3199  F.getName() == "main")
3200  FuncInfo->setForceFramePointer(true);
3201 
3202  MachineFrameInfo &MFI = MF.getFrameInfo();
3203  bool Is64Bit = Subtarget.is64Bit();
3204  bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3205 
3206  assert(
3207  !(isVarArg && canGuaranteeTCO(CallConv)) &&
3208  "Var args not supported with calling conv' regcall, fastcc, ghc or hipe");
3209 
3210  // Assign locations to all of the incoming arguments.
3212  CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3213 
3214  // Allocate shadow area for Win64.
3215  if (IsWin64)
3216  CCInfo.AllocateStack(32, 8);
3217 
3218  CCInfo.AnalyzeArguments(Ins, CC_X86);
3219 
3220  // In vectorcall calling convention a second pass is required for the HVA
3221  // types.
3222  if (CallingConv::X86_VectorCall == CallConv) {
3223  CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3224  }
3225 
3226  // The next loop assumes that the locations are in the same order of the
3227  // input arguments.
3228  assert(isSortedByValueNo(ArgLocs) &&
3229  "Argument Location list must be sorted before lowering");
3230 
3231  SDValue ArgValue;
3232  for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3233  ++I, ++InsIndex) {
3234  assert(InsIndex < Ins.size() && "Invalid Ins index");
3235  CCValAssign &VA = ArgLocs[I];
3236 
3237  if (VA.isRegLoc()) {
3238  EVT RegVT = VA.getLocVT();
3239  if (VA.needsCustom()) {
3240  assert(
3241  VA.getValVT() == MVT::v64i1 &&
3242  "Currently the only custom case is when we split v64i1 to 2 regs");
3243 
3244  // v64i1 values, in regcall calling convention, that are
3245  // compiled to 32 bit arch, are split up into two registers.
3246  ArgValue =
3247  getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3248  } else {
3249  const TargetRegisterClass *RC;
3250  if (RegVT == MVT::i8)
3251  RC = &X86::GR8RegClass;
3252  else if (RegVT == MVT::i16)
3253  RC = &X86::GR16RegClass;
3254  else if (RegVT == MVT::i32)
3255  RC = &X86::GR32RegClass;
3256  else if (Is64Bit && RegVT == MVT::i64)
3257  RC = &X86::GR64RegClass;
3258  else if (RegVT == MVT::f32)
3259  RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3260  else if (RegVT == MVT::f64)
3261  RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3262  else if (RegVT == MVT::f80)
3263  RC = &X86::RFP80RegClass;
3264  else if (RegVT == MVT::f128)
3265  RC = &X86::VR128RegClass;
3266  else if (RegVT.is512BitVector())
3267  RC = &X86::VR512RegClass;
3268  else if (RegVT.is256BitVector())
3269  RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3270  else if (RegVT.is128BitVector())
3271  RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3272  else if (RegVT == MVT::x86mmx)
3273  RC = &X86::VR64RegClass;
3274  else if (RegVT == MVT::v1i1)
3275  RC = &X86::VK1RegClass;
3276  else if (RegVT == MVT::v8i1)
3277  RC = &X86::VK8RegClass;
3278  else if (RegVT == MVT::v16i1)
3279  RC = &X86::VK16RegClass;
3280  else if (RegVT == MVT::v32i1)
3281  RC = &X86::VK32RegClass;
3282  else if (RegVT == MVT::v64i1)
3283  RC = &X86::VK64RegClass;
3284  else
3285  llvm_unreachable("Unknown argument type!");
3286 
3287  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3288  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3289  }
3290 
3291  // If this is an 8 or 16-bit value, it is really passed promoted to 32
3292  // bits. Insert an assert[sz]ext to capture this, then truncate to the
3293  // right size.
3294  if (VA.getLocInfo() == CCValAssign::SExt)
3295  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3296  DAG.getValueType(VA.getValVT()));
3297  else if (VA.getLocInfo() == CCValAssign::ZExt)
3298  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3299  DAG.getValueType(VA.getValVT()));
3300  else if (VA.getLocInfo() == CCValAssign::BCvt)
3301  ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3302 
3303  if (VA.isExtInLoc()) {
3304  // Handle MMX values passed in XMM regs.
3305  if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3306  ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3307  else if (VA.getValVT().isVector() &&
3308  VA.getValVT().getScalarType() == MVT::i1 &&
3309  ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3310  (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3311  // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3312  ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3313  } else
3314  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3315  }
3316  } else {
3317  assert(VA.isMemLoc());
3318  ArgValue =
3319  LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3320  }
3321 
3322  // If value is passed via pointer - do a load.
3323  if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3324  ArgValue =
3325  DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3326 
3327  InVals.push_back(ArgValue);
3328  }
3329 
3330  for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3331  // Swift calling convention does not require we copy the sret argument
3332  // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3333  if (CallConv == CallingConv::Swift)
3334  continue;
3335 
3336  // All x86 ABIs require that for returning structs by value we copy the
3337  // sret argument into %rax/%eax (depending on ABI) for the return. Save
3338  // the argument into a virtual register so that we can access it from the
3339  // return points.
3340  if (Ins[I].Flags.isSRet()) {
3341  unsigned Reg = FuncInfo->getSRetReturnReg();
3342  if (!Reg) {
3343  MVT PtrTy = getPointerTy(DAG.getDataLayout());
3344  Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3345  FuncInfo->setSRetReturnReg(Reg);
3346  }
3347  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3348  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3349  break;
3350  }
3351  }
3352 
3353  unsigned StackSize = CCInfo.getNextStackOffset();
3354  // Align stack specially for tail calls.
3355  if (shouldGuaranteeTCO(CallConv,
3357  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3358 
3359  // If the function takes variable number of arguments, make a frame index for
3360  // the start of the first vararg value... for expansion of llvm.va_start. We
3361  // can skip this if there are no va_start calls.
3362  if (MFI.hasVAStart() &&
3363  (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3364  CallConv != CallingConv::X86_ThisCall))) {
3365  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3366  }
3367 
3368  // Figure out if XMM registers are in use.
3369  assert(!(Subtarget.useSoftFloat() &&
3370  F.hasFnAttribute(Attribute::NoImplicitFloat)) &&
3371  "SSE register cannot be used when SSE is disabled!");
3372 
3373  // 64-bit calling conventions support varargs and register parameters, so we
3374  // have to do extra work to spill them in the prologue.
3375  if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3376  // Find the first unallocated argument registers.
3377  ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3378  ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3379  unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3380  unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3381  assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&
3382  "SSE register cannot be used when SSE is disabled!");
3383 
3384  // Gather all the live in physical registers.
3385  SmallVector<SDValue, 6> LiveGPRs;
3386  SmallVector<SDValue, 8> LiveXMMRegs;
3387  SDValue ALVal;
3388  for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3389  unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3390  LiveGPRs.push_back(
3391  DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3392  }
3393  if (!ArgXMMs.empty()) {
3394  unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3395  ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3396  for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3397  unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3398  LiveXMMRegs.push_back(
3399  DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3400  }
3401  }
3402 
3403  if (IsWin64) {
3404  // Get to the caller-allocated home save location. Add 8 to account
3405  // for the return address.
3406  int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3407  FuncInfo->setRegSaveFrameIndex(
3408  MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3409  // Fixup to set vararg frame on shadow area (4 x i64).
3410  if (NumIntRegs < 4)
3411  FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3412  } else {
3413  // For X86-64, if there are vararg parameters that are passed via
3414  // registers, then we must store them to their spots on the stack so
3415  // they may be loaded by dereferencing the result of va_next.
3416  FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3417  FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3419  ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3420  }
3421 
3422  // Store the integer parameter registers.
3423  SmallVector<SDValue, 8> MemOps;
3424  SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3425  getPointerTy(DAG.getDataLayout()));
3426  unsigned Offset = FuncInfo->getVarArgsGPOffset();
3427  for (SDValue Val : LiveGPRs) {
3428  SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3429  RSFIN, DAG.getIntPtrConstant(Offset, dl));
3430  SDValue Store =
3431  DAG.getStore(Val.getValue(1), dl, Val, FIN,
3433  DAG.getMachineFunction(),
3434  FuncInfo->getRegSaveFrameIndex(), Offset));
3435  MemOps.push_back(Store);
3436  Offset += 8;
3437  }
3438 
3439  if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3440  // Now store the XMM (fp + vector) parameter registers.
3441  SmallVector<SDValue, 12> SaveXMMOps;
3442  SaveXMMOps.push_back(Chain);
3443  SaveXMMOps.push_back(ALVal);
3444  SaveXMMOps.push_back(DAG.getIntPtrConstant(
3445  FuncInfo->getRegSaveFrameIndex(), dl));
3446  SaveXMMOps.push_back(DAG.getIntPtrConstant(
3447  FuncInfo->getVarArgsFPOffset(), dl));
3448  SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3449  LiveXMMRegs.end());
3451  MVT::Other, SaveXMMOps));
3452  }
3453 
3454  if (!MemOps.empty())
3455  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3456  }
3457 
3458  if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3459  // Find the largest legal vector type.
3460  MVT VecVT = MVT::Other;
3461  // FIXME: Only some x86_32 calling conventions support AVX512.
3462  if (Subtarget.useAVX512Regs() &&
3463  (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3464  CallConv == CallingConv::Intel_OCL_BI)))
3465  VecVT = MVT::v16f32;
3466  else if (Subtarget.hasAVX())
3467  VecVT = MVT::v8f32;
3468  else if (Subtarget.hasSSE2())
3469  VecVT = MVT::v4f32;
3470 
3471  // We forward some GPRs and some vector types.
3472  SmallVector<MVT, 2> RegParmTypes;
3473  MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3474  RegParmTypes.push_back(IntVT);
3475  if (VecVT != MVT::Other)
3476  RegParmTypes.push_back(VecVT);
3477 
3478  // Compute the set of forwarded registers. The rest are scratch.
3480  FuncInfo->getForwardedMustTailRegParms();
3481  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3482 
3483  // Conservatively forward AL on x86_64, since it might be used for varargs.
3484  if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3485  unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3486  Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3487  }
3488 
3489  // Copy all forwards from physical to virtual registers.
3490  for (ForwardedRegister &FR : Forwards) {
3491  // FIXME: Can we use a less constrained schedule?
3492  SDValue RegVal = DAG.getCopyFromReg(Chain, dl, FR.VReg, FR.VT);
3493  FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
3494  Chain = DAG.getCopyToReg(Chain, dl, FR.VReg, RegVal);
3495  }
3496  }
3497 
3498  // Some CCs need callee pop.
3499  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3501  FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3502  } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3503  // X86 interrupts must pop the error code (and the alignment padding) if
3504  // present.
3505  FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3506  } else {
3507  FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3508  // If this is an sret function, the return should pop the hidden pointer.
3509  if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3510  !Subtarget.getTargetTriple().isOSMSVCRT() &&
3511  argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3512  FuncInfo->setBytesToPopOnReturn(4);
3513  }
3514 
3515  if (!Is64Bit) {
3516  // RegSaveFrameIndex is X86-64 only.
3517  FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3518  if (CallConv == CallingConv::X86_FastCall ||
3519  CallConv == CallingConv::X86_ThisCall)
3520  // fastcc functions can't have varargs.
3521  FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3522  }
3523 
3524  FuncInfo->setArgumentStackSize(StackSize);
3525 
3526  if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3528  if (Personality == EHPersonality::CoreCLR) {
3529  assert(Is64Bit);
3530  // TODO: Add a mechanism to frame lowering that will allow us to indicate
3531  // that we'd prefer this slot be allocated towards the bottom of the frame
3532  // (i.e. near the stack pointer after allocating the frame). Every
3533  // funclet needs a copy of this slot in its (mostly empty) frame, and the
3534  // offset from the bottom of this and each funclet's frame must be the
3535  // same, so the size of funclets' (mostly empty) frames is dictated by
3536  // how far this slot is from the bottom (since they allocate just enough
3537  // space to accommodate holding this slot at the correct offset).
3538  int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3539  EHInfo->PSPSymFrameIdx = PSPSymFI;
3540  }
3541  }
3542 
3543  if (CallConv == CallingConv::X86_RegCall ||
3544  F.hasFnAttribute("no_caller_saved_registers")) {
3546  for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3547  MRI.disableCalleeSavedRegister(Pair.first);
3548  }
3549 
3550  return Chain;
3551 }
3552 
3553 SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3554  SDValue