LLVM  9.0.0svn
X86ISelLowering.cpp
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1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
15 #include "Utils/X86ShuffleDecode.h"
16 #include "X86CallingConv.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86IntrinsicsInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
38 #include "llvm/IR/CallSite.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/DiagnosticInfo.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalAlias.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/MC/MCAsmInfo.h"
49 #include "llvm/MC/MCContext.h"
50 #include "llvm/MC/MCExpr.h"
51 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/KnownBits.h"
58 #include <algorithm>
59 #include <bitset>
60 #include <cctype>
61 #include <numeric>
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "x86-isel"
65 
66 STATISTIC(NumTailCalls, "Number of tail calls");
67 
69  "x86-experimental-vector-widening-legalization", cl::init(false),
70  cl::desc("Enable an experimental vector type legalization through widening "
71  "rather than promotion."),
72  cl::Hidden);
73 
75  "x86-experimental-pref-loop-alignment", cl::init(4),
76  cl::desc("Sets the preferable loop alignment for experiments "
77  "(the last x86-experimental-pref-loop-alignment bits"
78  " of the loop header PC will be 0)."),
79  cl::Hidden);
80 
82  "mul-constant-optimization", cl::init(true),
83  cl::desc("Replace 'mul x, Const' with more effective instructions like "
84  "SHIFT, LEA, etc."),
85  cl::Hidden);
86 
87 /// Call this when the user attempts to do something unsupported, like
88 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
89 /// report_fatal_error, so calling code should attempt to recover without
90 /// crashing.
91 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
92  const char *Msg) {
94  DAG.getContext()->diagnose(
96 }
97 
99  const X86Subtarget &STI)
100  : TargetLowering(TM), Subtarget(STI) {
101  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
102  X86ScalarSSEf64 = Subtarget.hasSSE2();
103  X86ScalarSSEf32 = Subtarget.hasSSE1();
105 
106  // Set up the TargetLowering object.
107 
108  // X86 is weird. It always uses i8 for shift amounts and setcc results.
110  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
112 
113  // For 64-bit, since we have so many registers, use the ILP scheduler.
114  // For 32-bit, use the register pressure specific scheduling.
115  // For Atom, always use ILP scheduling.
116  if (Subtarget.isAtom())
118  else if (Subtarget.is64Bit())
120  else
122  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
124 
125  // Bypass expensive divides and use cheaper ones.
126  if (TM.getOptLevel() >= CodeGenOpt::Default) {
127  if (Subtarget.hasSlowDivide32())
128  addBypassSlowDiv(32, 8);
129  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
130  addBypassSlowDiv(64, 32);
131  }
132 
133  if (Subtarget.isTargetWindowsMSVC() ||
134  Subtarget.isTargetWindowsItanium()) {
135  // Setup Windows compiler runtime calls.
136  setLibcallName(RTLIB::SDIV_I64, "_alldiv");
137  setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
138  setLibcallName(RTLIB::SREM_I64, "_allrem");
139  setLibcallName(RTLIB::UREM_I64, "_aullrem");
140  setLibcallName(RTLIB::MUL_I64, "_allmul");
146  }
147 
148  if (Subtarget.isTargetDarwin()) {
149  // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
150  setUseUnderscoreSetJmp(false);
152  } else if (Subtarget.isTargetWindowsGNU()) {
153  // MS runtime is weird: it exports _setjmp, but longjmp!
156  } else {
159  }
160 
161  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
162  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
163  // FIXME: Should we be limitting the atomic size on other configs? Default is
164  // 1024.
165  if (!Subtarget.hasCmpxchg8b())
167 
168  // Set up the register classes.
169  addRegisterClass(MVT::i8, &X86::GR8RegClass);
170  addRegisterClass(MVT::i16, &X86::GR16RegClass);
171  addRegisterClass(MVT::i32, &X86::GR32RegClass);
172  if (Subtarget.is64Bit())
173  addRegisterClass(MVT::i64, &X86::GR64RegClass);
174 
175  for (MVT VT : MVT::integer_valuetypes())
177 
178  // We don't accept any truncstore of integer registers.
185 
187 
188  // SETOEQ and SETUNE require checking two conditions.
195 
196  // Integer absolute.
197  if (Subtarget.hasCMov()) {
200  }
202 
203  // Funnel shifts.
204  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
205  setOperationAction(ShiftOp , MVT::i16 , Custom);
206  setOperationAction(ShiftOp , MVT::i32 , Custom);
207  if (Subtarget.is64Bit())
208  setOperationAction(ShiftOp , MVT::i64 , Custom);
209  }
210 
211  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
212  // operation.
216 
217  if (Subtarget.is64Bit()) {
218  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
219  // f32/f64 are legal, f80 is custom.
221  else
224  } else if (!Subtarget.useSoftFloat()) {
225  // We have an algorithm for SSE2->double, and we turn this into a
226  // 64-bit FILD followed by conditional FADD for other targets.
228  // We have an algorithm for SSE2, and we turn this into a 64-bit
229  // FILD or VCVTUSI2SS/SD for other targets.
231  } else {
233  }
234 
235  // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
236  // this operation.
239 
240  if (!Subtarget.useSoftFloat()) {
241  // SSE has no i16 to fp conversion, only i32.
242  if (X86ScalarSSEf32) {
244  // f32 and f64 cases are Legal, f80 case is not
246  } else {
249  }
250  } else {
253  }
254 
255  // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
256  // this operation.
259 
260  if (!Subtarget.useSoftFloat()) {
261  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
262  // are Legal, f80 is custom lowered.
265 
268  } else {
272  }
273 
274  // Handle FP_TO_UINT by promoting the destination to a larger signed
275  // conversion.
279 
280  if (Subtarget.is64Bit()) {
281  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
282  // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
285  } else {
288  }
289  } else if (!Subtarget.useSoftFloat()) {
290  // Since AVX is a superset of SSE3, only check for SSE here.
291  if (Subtarget.hasSSE1() && !Subtarget.hasSSE3())
292  // Expand FP_TO_UINT into a select.
293  // FIXME: We would like to use a Custom expander here eventually to do
294  // the optimal thing for SSE vs. the default expansion in the legalizer.
296  else
297  // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
298  // With SSE3 we can use fisttpll to convert to a signed i64; without
299  // SSE, we're stuck with a fistpll.
301 
303  }
304 
305  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
306  if (!X86ScalarSSEf64) {
309  if (Subtarget.is64Bit()) {
311  // Without SSE, i64->f64 goes through memory.
313  }
314  } else if (!Subtarget.is64Bit())
316 
317  // Scalar integer divide and remainder are lowered to use operations that
318  // produce two results, to match the available instructions. This exposes
319  // the two-result form to trivial CSE, which is able to combine x/y and x%y
320  // into a single instruction.
321  //
322  // Scalar integer multiply-high is also lowered to use two-result
323  // operations, to match the available instructions. However, plain multiply
324  // (low) operations are left as Legal, as there are single-result
325  // instructions for this in x86. Using the two-result multiply instructions
326  // when both high and low results are needed must be arranged by dagcombine.
327  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
334  }
335 
338  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
342  }
343  if (Subtarget.is64Bit())
349 
354 
355  // Promote the i8 variants and force them on up to i32 which has a shorter
356  // encoding.
359  if (!Subtarget.hasBMI()) {
364  if (Subtarget.is64Bit()) {
367  }
368  }
369 
370  if (Subtarget.hasLZCNT()) {
371  // When promoting the i8 variants, force them to i32 for a shorter
372  // encoding.
375  } else {
382  if (Subtarget.is64Bit()) {
385  }
386  }
387 
388  // Special handling for half-precision floating point conversions.
389  // If we don't have F16C support, then lower half float conversions
390  // into library calls.
391  if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {
394  }
395 
396  // There's never any support for operations beyond MVT::f32.
401 
408 
409  if (Subtarget.hasPOPCNT()) {
411  } else {
415  if (Subtarget.is64Bit())
417  else
419  }
420 
422 
423  if (!Subtarget.hasMOVBE())
425 
426  // These should be promoted to a larger select which is supported.
428  // X86 wants to expand cmov itself.
429  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
432  }
433  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
434  if (VT == MVT::i64 && !Subtarget.is64Bit())
435  continue;
438  }
439 
440  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
443 
445  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
446  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
451  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
452 
453  // Darwin ABI issue.
454  for (auto VT : { MVT::i32, MVT::i64 }) {
455  if (VT == MVT::i64 && !Subtarget.is64Bit())
456  continue;
463  }
464 
465  // 64-bit shl, sra, srl (iff 32-bit x86)
466  for (auto VT : { MVT::i32, MVT::i64 }) {
467  if (VT == MVT::i64 && !Subtarget.is64Bit())
468  continue;
472  }
473 
474  if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
476 
478 
479  // Expand certain atomics
480  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
488  }
489 
490  if (!Subtarget.is64Bit())
492 
493  if (Subtarget.hasCmpxchg16b()) {
495  }
496 
497  // FIXME - use subtarget debug flags
498  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
499  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
502  }
503 
506 
509 
512 
513  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
516  bool Is64Bit = Subtarget.is64Bit();
518  setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
519 
522 
524 
525  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
528 
529  if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
530  // f32 and f64 use SSE.
531  // Set up the FP register classes.
532  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
533  : &X86::FR32RegClass);
534  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
535  : &X86::FR64RegClass);
536 
537  // Disable f32->f64 extload as we can only generate this in one instruction
538  // under optsize. So its easier to pattern match (fpext (load)) for that
539  // case instead of needing to emit 2 instructions for extload in the
540  // non-optsize case.
542 
543  for (auto VT : { MVT::f32, MVT::f64 }) {
544  // Use ANDPD to simulate FABS.
546 
547  // Use XORP to simulate FNEG.
549 
550  // Use ANDPD and ORPD to simulate FCOPYSIGN.
552 
553  // These might be better off as horizontal vector ops.
556 
557  // We don't support sin/cos/fmod
558  setOperationAction(ISD::FSIN , VT, Expand);
559  setOperationAction(ISD::FCOS , VT, Expand);
560  setOperationAction(ISD::FSINCOS, VT, Expand);
561  }
562 
563  // Lower this to MOVMSK plus an AND.
566 
567  } else if (!useSoftFloat() && X86ScalarSSEf32 && (UseX87 || Is64Bit)) {
568  // Use SSE for f32, x87 for f64.
569  // Set up the FP register classes.
570  addRegisterClass(MVT::f32, &X86::FR32RegClass);
571  if (UseX87)
572  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
573 
574  // Use ANDPS to simulate FABS.
576 
577  // Use XORP to simulate FNEG.
579 
580  if (UseX87)
582 
583  // Use ANDPS and ORPS to simulate FCOPYSIGN.
584  if (UseX87)
587 
588  // We don't support sin/cos/fmod
592 
593  if (UseX87) {
594  // Always expand sin/cos functions even though x87 has an instruction.
598  }
599  } else if (UseX87) {
600  // f32 and f64 in x87.
601  // Set up the FP register classes.
602  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
603  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
604 
605  for (auto VT : { MVT::f32, MVT::f64 }) {
606  setOperationAction(ISD::UNDEF, VT, Expand);
607  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
608 
609  // Always expand sin/cos functions even though x87 has an instruction.
610  setOperationAction(ISD::FSIN , VT, Expand);
611  setOperationAction(ISD::FCOS , VT, Expand);
612  setOperationAction(ISD::FSINCOS, VT, Expand);
613  }
614  }
615 
616  // Expand FP32 immediates into loads from the stack, save special cases.
617  if (isTypeLegal(MVT::f32)) {
618  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
619  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
620  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
621  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
622  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
623  } else // SSE immediates.
624  addLegalFPImmediate(APFloat(+0.0f)); // xorps
625  }
626  // Expand FP64 immediates into loads from the stack, save special cases.
627  if (isTypeLegal(MVT::f64)) {
628  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
629  addLegalFPImmediate(APFloat(+0.0)); // FLD0
630  addLegalFPImmediate(APFloat(+1.0)); // FLD1
631  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
632  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
633  } else // SSE immediates.
634  addLegalFPImmediate(APFloat(+0.0)); // xorpd
635  }
636 
637  // We don't support FMA.
640 
641  // Long double always uses X87, except f128 in MMX.
642  if (UseX87) {
643  if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
644  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
645  : &X86::VR128RegClass);
650  }
651 
652  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
655  {
657  addLegalFPImmediate(TmpFlt); // FLD0
658  TmpFlt.changeSign();
659  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
660 
661  bool ignored;
662  APFloat TmpFlt2(+1.0);
664  &ignored);
665  addLegalFPImmediate(TmpFlt2); // FLD1
666  TmpFlt2.changeSign();
667  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
668  }
669 
670  // Always expand sin/cos functions even though x87 has an instruction.
674 
685  }
686 
687  // Always use a library call for pow.
691 
699 
700  // Some FP actions are always expanded for vector types.
701  for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
703  setOperationAction(ISD::FSIN, VT, Expand);
704  setOperationAction(ISD::FSINCOS, VT, Expand);
705  setOperationAction(ISD::FCOS, VT, Expand);
706  setOperationAction(ISD::FREM, VT, Expand);
707  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
708  setOperationAction(ISD::FPOW, VT, Expand);
709  setOperationAction(ISD::FLOG, VT, Expand);
710  setOperationAction(ISD::FLOG2, VT, Expand);
711  setOperationAction(ISD::FLOG10, VT, Expand);
712  setOperationAction(ISD::FEXP, VT, Expand);
713  setOperationAction(ISD::FEXP2, VT, Expand);
714  }
715 
716  // First set operation action for all vector types to either promote
717  // (for widening) or expand (for scalarization). Then we will selectively
718  // turn on ones that can be effectively codegen'd.
719  for (MVT VT : MVT::vector_valuetypes()) {
720  setOperationAction(ISD::SDIV, VT, Expand);
721  setOperationAction(ISD::UDIV, VT, Expand);
722  setOperationAction(ISD::SREM, VT, Expand);
723  setOperationAction(ISD::UREM, VT, Expand);
728  setOperationAction(ISD::FMA, VT, Expand);
729  setOperationAction(ISD::FFLOOR, VT, Expand);
730  setOperationAction(ISD::FCEIL, VT, Expand);
731  setOperationAction(ISD::FTRUNC, VT, Expand);
732  setOperationAction(ISD::FRINT, VT, Expand);
733  setOperationAction(ISD::FNEARBYINT, VT, Expand);
734  setOperationAction(ISD::SMUL_LOHI, VT, Expand);
735  setOperationAction(ISD::MULHS, VT, Expand);
736  setOperationAction(ISD::UMUL_LOHI, VT, Expand);
737  setOperationAction(ISD::MULHU, VT, Expand);
738  setOperationAction(ISD::SDIVREM, VT, Expand);
739  setOperationAction(ISD::UDIVREM, VT, Expand);
740  setOperationAction(ISD::CTPOP, VT, Expand);
741  setOperationAction(ISD::CTTZ, VT, Expand);
742  setOperationAction(ISD::CTLZ, VT, Expand);
743  setOperationAction(ISD::ROTL, VT, Expand);
744  setOperationAction(ISD::ROTR, VT, Expand);
745  setOperationAction(ISD::BSWAP, VT, Expand);
746  setOperationAction(ISD::SETCC, VT, Expand);
747  setOperationAction(ISD::FP_TO_UINT, VT, Expand);
748  setOperationAction(ISD::FP_TO_SINT, VT, Expand);
749  setOperationAction(ISD::UINT_TO_FP, VT, Expand);
750  setOperationAction(ISD::SINT_TO_FP, VT, Expand);
752  setOperationAction(ISD::TRUNCATE, VT, Expand);
755  setOperationAction(ISD::ANY_EXTEND, VT, Expand);
756  setOperationAction(ISD::SELECT_CC, VT, Expand);
757  for (MVT InnerVT : MVT::vector_valuetypes()) {
758  setTruncStoreAction(InnerVT, VT, Expand);
759 
760  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
761  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
762 
763  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
764  // types, we have to deal with them whether we ask for Expansion or not.
765  // Setting Expand causes its own optimisation problems though, so leave
766  // them legal.
767  if (VT.getVectorElementType() == MVT::i1)
768  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
769 
770  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
771  // split/scalarized right now.
772  if (VT.getVectorElementType() == MVT::f16)
773  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
774  }
775  }
776 
777  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
778  // with -msoft-float, disable use of MMX as well.
779  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
780  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
781  // No operations on x86mmx supported, everything uses intrinsics.
782  }
783 
784  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
785  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
786  : &X86::VR128RegClass);
787 
797 
800  }
801 
802  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
803  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
804  : &X86::VR128RegClass);
805 
806  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
807  // registers cannot be used even for integer operations.
808  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
809  : &X86::VR128RegClass);
810  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
811  : &X86::VR128RegClass);
812  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
813  : &X86::VR128RegClass);
814  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
815  : &X86::VR128RegClass);
816 
817  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
823  }
824 
831 
845 
846  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
848  setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
849  setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
850  setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
851  }
852 
865 
867  // Use widening instead of promotion.
868  for (auto VT : { MVT::v8i8, MVT::v4i8, MVT::v2i8,
869  MVT::v4i16, MVT::v2i16 }) {
874  }
875  }
876 
880 
881  // Provide custom widening for v2f32 setcc. This is really for VLX when
882  // setcc result type returns v2i1/v4i1 vector for v2f32/v4f32 leading to
883  // type legalization changing the result type to v4i1 during widening.
884  // It works fine for SSE2 and is probably faster so no need to qualify with
885  // VLX support.
887 
888  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
892 
893  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
894  // setcc all the way to isel and prefer SETGT in some isel patterns.
897  }
898 
899  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
905  }
906 
907  // We support custom legalizing of sext and anyext loads for specific
908  // memory vector types which we can load as a scalar (or sequence of
909  // scalars) and extend in-register to a legal 128-bit vector type. For sext
910  // loads these must work with a single scalar load.
911  for (MVT VT : MVT::integer_vector_valuetypes()) {
918  }
919 
920  for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
924 
925  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
926  continue;
927 
930  }
931 
932  // Custom lower v2i64 and v2f64 selects.
938 
942 
943  // Custom legalize these to avoid over promotion or custom promotion.
954 
955  // By marking FP_TO_SINT v8i16 as Custom, will trick type legalization into
956  // promoting v8i8 FP_TO_UINT into FP_TO_SINT. When the v8i16 FP_TO_SINT is
957  // split again based on the input type, this will cause an AssertSExt i16 to
958  // be emitted instead of an AssertZExt. This will allow packssdw followed by
959  // packuswb to be used to truncate to v8i8. This is necessary since packusdw
960  // isn't available until sse4.1.
962 
965 
967 
968  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
970 
973 
974  // We want to legalize this to an f64 load rather than an i64 load on
975  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
976  // store.
983 
987  if (!Subtarget.hasAVX512())
989 
993 
996 
1003  } else {
1005  }
1006 
1007  // In the customized shift lowering, the legal v4i32/v2i64 cases
1008  // in AVX2 will be recognized.
1009  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1013  }
1014 
1017 
1018  // With AVX512, expanding (and promoting the shifts) is better.
1019  if (!Subtarget.hasAVX512())
1021  }
1022 
1023  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1032 
1033  // These might be better off as horizontal vector ops.
1038  }
1039 
1040  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1041  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1042  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1043  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1044  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1045  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1047  }
1048 
1057 
1058  // FIXME: Do we need to handle scalar-to-vector here?
1060 
1061  // We directly match byte blends in the backend as they match the VSELECT
1062  // condition form.
1064 
1065  // SSE41 brings specific instructions for doing vector sign extend even in
1066  // cases where we don't have SRA.
1067  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1070  }
1071 
1073  // Avoid narrow result types when widening. The legal types are listed
1074  // in the next loop.
1075  for (MVT VT : MVT::integer_vector_valuetypes()) {
1079  }
1080  }
1081 
1082  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1083  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1092  }
1093 
1094  // i8 vectors are custom because the source register and source
1095  // source memory operand types are not the same width.
1097  }
1098 
1099  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1100  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1103 
1104  // XOP can efficiently perform BITREVERSE with VPPERM.
1105  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1107 
1108  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1111  }
1112 
1113  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1114  bool HasInt256 = Subtarget.hasInt256();
1115 
1116  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1117  : &X86::VR256RegClass);
1118  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1119  : &X86::VR256RegClass);
1120  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1121  : &X86::VR256RegClass);
1122  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1123  : &X86::VR256RegClass);
1124  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1125  : &X86::VR256RegClass);
1126  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1127  : &X86::VR256RegClass);
1128 
1129  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1138  }
1139 
1140  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1141  // even though v8i16 is a legal type.
1145 
1147 
1148  if (!Subtarget.hasAVX512())
1150 
1151  // In the customized shift lowering, the legal v8i32/v4i64 cases
1152  // in AVX2 will be recognized.
1153  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1157  }
1158 
1159  // These types need custom splitting if their input is a 128-bit vector.
1164 
1167 
1168  // With BWI, expanding (and promoting the shifts) is the better.
1169  if (!Subtarget.hasBWI())
1171 
1178 
1179  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1183  }
1184 
1189 
1190  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1194 
1195  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1196  // setcc all the way to isel and prefer SETGT in some isel patterns.
1199  }
1200 
1201  if (Subtarget.hasAnyFMA()) {
1202  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1205  }
1206 
1207  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1208  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1209  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1210  }
1211 
1214  setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1216 
1219  setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1220  setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1223 
1229 
1230  setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1231  setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1232  setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1233  setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1234  setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1235  setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1236  setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1237  setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1238 
1239  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1240  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1241  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1242  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1243  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1244  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1245  }
1246 
1247  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1250  }
1251 
1252  if (HasInt256) {
1253  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1254  // when we have a 256bit-wide blend with immediate.
1256 
1257  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1258  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1265  }
1266  }
1267 
1268  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1270  setOperationAction(ISD::MLOAD, VT, Custom);
1272  }
1273 
1274  // Extract subvector is special because the value type
1275  // (result) is 128-bit but the source is 256-bit wide.
1276  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1277  MVT::v4f32, MVT::v2f64 }) {
1279  }
1280 
1281  // Custom lower several nodes for 256-bit types.
1283  MVT::v8f32, MVT::v4f64 }) {
1286  setOperationAction(ISD::VSELECT, VT, Custom);
1292  setOperationAction(ISD::STORE, VT, Custom);
1293  }
1294 
1295  if (HasInt256)
1297 
1298  if (HasInt256) {
1299  // Custom legalize 2x32 to get a little better code.
1302 
1303  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1305  setOperationAction(ISD::MGATHER, VT, Custom);
1306  }
1307  }
1308 
1309  // This block controls legalization of the mask vector sizes that are
1310  // available with AVX512. 512-bit vectors are in a separate block controlled
1311  // by useAVX512Regs.
1312  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1313  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1314  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1315  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1316  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1317  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1318 
1322 
1329 
1330  // There is no byte sized k-register load or store without AVX512DQ.
1331  if (!Subtarget.hasDQI()) {
1336 
1341  }
1342 
1343  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1344  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1348  }
1349 
1350  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1361 
1368  setOperationAction(ISD::VSELECT, VT, Expand);
1369  }
1370 
1371  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1373  }
1374 
1375  // This block controls legalization for 512-bit operations with 32/64 bit
1376  // elements. 512-bits can be disabled based on prefer-vector-width and
1377  // required-vector-width function attributes.
1378  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1379  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1383 
1384  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1390  }
1391 
1392  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1397  }
1398 
1409 
1415 
1416  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1417  // to 512-bit rather than use the AVX2 instructions so that we can use
1418  // k-masks.
1419  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1421  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1422  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1423  }
1424 
1433 
1435  // Need to custom widen this if we don't have AVX512BW.
1439  }
1440 
1441  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1447 
1449  }
1450 
1451  // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1452  for (auto VT : {MVT::v16i32, MVT::v8i64, MVT::v64i8}) {
1455  }
1456 
1461 
1464 
1467 
1468  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1482 
1483  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1484  // setcc all the way to isel and prefer SETGT in some isel patterns.
1487  }
1488 
1489  if (Subtarget.hasDQI()) {
1494 
1496  }
1497 
1498  if (Subtarget.hasCDI()) {
1499  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1500  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1502  }
1503  } // Subtarget.hasCDI()
1504 
1505  if (Subtarget.hasVPOPCNTDQ()) {
1506  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1508  }
1509 
1510  // Extract subvector is special because the value type
1511  // (result) is 256-bit but the source is 512-bit wide.
1512  // 128-bit was made Legal under AVX1.
1513  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1516 
1517  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1529  }
1530  // Need to custom split v32i16/v64i8 bitcasts.
1531  if (!Subtarget.hasBWI()) {
1534  }
1535 
1536  if (Subtarget.hasVBMI2()) {
1537  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1540  }
1541  }
1542  }// has AVX-512
1543 
1544  // This block controls legalization for operations that don't have
1545  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1546  // narrower widths.
1547  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1548  // These operations are handled on non-VLX by artificially widening in
1549  // isel patterns.
1550  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1551 
1557 
1558  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1564  }
1565 
1566  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1569  }
1570 
1571  // Custom legalize 2x32 to get a little better code.
1574 
1575  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1578 
1579  if (Subtarget.hasDQI()) {
1580  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1585 
1587  }
1588  }
1589 
1590  if (Subtarget.hasCDI()) {
1591  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1593  }
1594  } // Subtarget.hasCDI()
1595 
1596  if (Subtarget.hasVPOPCNTDQ()) {
1597  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1599  }
1600  }
1601 
1602  // This block control legalization of v32i1/v64i1 which are available with
1603  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1604  // useBWIRegs.
1605  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1606  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1607  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1608 
1609  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1613  setOperationAction(ISD::VSELECT, VT, Expand);
1618 
1626  }
1627 
1632  for (auto VT : { MVT::v16i1, MVT::v32i1 })
1634 
1635  // Extends from v32i1 masks to 256-bit vectors.
1639  }
1640 
1641  // This block controls legalization for v32i16 and v64i8. 512-bits can be
1642  // disabled based on prefer-vector-width and required-vector-width function
1643  // attributes.
1644  if (!Subtarget.useSoftFloat() && Subtarget.useBWIRegs()) {
1645  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1646  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1647 
1648  // Extends from v64i1 masks to 512-bit vectors.
1652 
1676 
1679 
1681 
1682  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1703 
1704  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1705  // setcc all the way to isel and prefer SETGT in some isel patterns.
1708  }
1709 
1710  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1712  }
1713 
1714  if (Subtarget.hasBITALG()) {
1715  for (auto VT : { MVT::v64i8, MVT::v32i16 })
1717  }
1718 
1719  if (Subtarget.hasVBMI2()) {
1722  }
1723  }
1724 
1725  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1726  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1727  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1728  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1729  }
1730 
1731  // These operations are handled on non-VLX by artificially widening in
1732  // isel patterns.
1733  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1734 
1735  if (Subtarget.hasBITALG()) {
1736  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1738  }
1739  }
1740 
1741  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1747 
1753 
1754  if (Subtarget.hasDQI()) {
1755  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1756  // v2f32 UINT_TO_FP is already custom under SSE2.
1759  "Unexpected operation action!");
1760  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1763  }
1764 
1765  if (Subtarget.hasBWI()) {
1768  }
1769 
1770  if (Subtarget.hasVBMI2()) {
1771  // TODO: Make these legal even without VLX?
1772  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1776  }
1777  }
1778  }
1779 
1780  // We want to custom lower some of our intrinsics.
1784  if (!Subtarget.is64Bit()) {
1786  }
1787 
1788  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1789  // handle type legalization for these operations here.
1790  //
1791  // FIXME: We really should do custom legalization for addition and
1792  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1793  // than generic legalization for 64-bit multiplication-with-overflow, though.
1794  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1795  if (VT == MVT::i64 && !Subtarget.is64Bit())
1796  continue;
1797  // Add/Sub/Mul with overflow operations are custom lowered.
1804 
1805  // Support carry in as value rather than glue.
1809  }
1810 
1811  if (!Subtarget.is64Bit()) {
1812  // These libcalls are not available in 32-bit.
1813  setLibcallName(RTLIB::SHL_I128, nullptr);
1814  setLibcallName(RTLIB::SRL_I128, nullptr);
1815  setLibcallName(RTLIB::SRA_I128, nullptr);
1816  setLibcallName(RTLIB::MUL_I128, nullptr);
1817  }
1818 
1819  // Combine sin / cos into _sincos_stret if it is available.
1820  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1821  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1824  }
1825 
1826  if (Subtarget.isTargetWin64()) {
1833  }
1834 
1835  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1836  // is. We should promote the value to 64-bits to solve this.
1837  // This is what the CRT headers do - `fmodf` is an inline header
1838  // function casting to f64 and calling `fmod`.
1839  if (Subtarget.is32Bit() &&
1840  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
1841  for (ISD::NodeType Op :
1846 
1847  // We have target-specific dag combine patterns for the following nodes:
1889 
1891 
1892  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1894  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1896  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1898 
1899  // TODO: These control memcmp expansion in CGP and could be raised higher, but
1900  // that needs to benchmarked and balanced with the potential use of vector
1901  // load/store types (PR33329, PR33914).
1902  MaxLoadsPerMemcmp = 2;
1904 
1905  // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
1907 
1908  // An out-of-order CPU can speculatively execute past a predictable branch,
1909  // but a conditional move could be stalled by an expensive earlier operation.
1910  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
1911  EnableExtLdPromotion = true;
1912  setPrefFunctionAlignment(4); // 2^4 bytes.
1913 
1915 }
1916 
1917 // This has so far only been implemented for 64-bit MachO.
1919  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
1920 }
1921 
1923  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
1924  return Subtarget.getTargetTriple().isOSMSVCRT();
1925 }
1926 
1928  const SDLoc &DL) const {
1929  EVT PtrTy = getPointerTy(DAG.getDataLayout());
1930  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
1931  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
1932  return SDValue(Node, 0);
1933 }
1934 
1937  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1938  return TypeSplitVector;
1939 
1941  VT.getVectorNumElements() != 1 &&
1942  VT.getVectorElementType() != MVT::i1)
1943  return TypeWidenVector;
1944 
1946 }
1947 
1949  CallingConv::ID CC,
1950  EVT VT) const {
1951  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1952  return MVT::v32i8;
1953  return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
1954 }
1955 
1957  CallingConv::ID CC,
1958  EVT VT) const {
1959  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1960  return 1;
1961  return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
1962 }
1963 
1966  EVT VT) const {
1967  if (!VT.isVector())
1968  return MVT::i8;
1969 
1970  if (Subtarget.hasAVX512()) {
1971  const unsigned NumElts = VT.getVectorNumElements();
1972 
1973  // Figure out what this type will be legalized to.
1974  EVT LegalVT = VT;
1975  while (getTypeAction(Context, LegalVT) != TypeLegal)
1976  LegalVT = getTypeToTransformTo(Context, LegalVT);
1977 
1978  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
1979  if (LegalVT.getSimpleVT().is512BitVector())
1980  return EVT::getVectorVT(Context, MVT::i1, NumElts);
1981 
1982  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
1983  // If we legalized to less than a 512-bit vector, then we will use a vXi1
1984  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
1985  // vXi16/vXi8.
1986  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
1987  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
1988  return EVT::getVectorVT(Context, MVT::i1, NumElts);
1989  }
1990  }
1991 
1993 }
1994 
1995 /// Helper for getByValTypeAlignment to determine
1996 /// the desired ByVal argument alignment.
1997 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1998  if (MaxAlign == 16)
1999  return;
2000  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2001  if (VTy->getBitWidth() == 128)
2002  MaxAlign = 16;
2003  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2004  unsigned EltAlign = 0;
2005  getMaxByValAlign(ATy->getElementType(), EltAlign);
2006  if (EltAlign > MaxAlign)
2007  MaxAlign = EltAlign;
2008  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2009  for (auto *EltTy : STy->elements()) {
2010  unsigned EltAlign = 0;
2011  getMaxByValAlign(EltTy, EltAlign);
2012  if (EltAlign > MaxAlign)
2013  MaxAlign = EltAlign;
2014  if (MaxAlign == 16)
2015  break;
2016  }
2017  }
2018 }
2019 
2020 /// Return the desired alignment for ByVal aggregate
2021 /// function arguments in the caller parameter area. For X86, aggregates
2022 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2023 /// are at 4-byte boundaries.
2025  const DataLayout &DL) const {
2026  if (Subtarget.is64Bit()) {
2027  // Max of 8 and alignment of type.
2028  unsigned TyAlign = DL.getABITypeAlignment(Ty);
2029  if (TyAlign > 8)
2030  return TyAlign;
2031  return 8;
2032  }
2033 
2034  unsigned Align = 4;
2035  if (Subtarget.hasSSE1())
2036  getMaxByValAlign(Ty, Align);
2037  return Align;
2038 }
2039 
2040 /// Returns the target specific optimal type for load
2041 /// and store operations as a result of memset, memcpy, and memmove
2042 /// lowering. If DstAlign is zero that means it's safe to destination
2043 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
2044 /// means there isn't a need to check it against alignment requirement,
2045 /// probably because the source does not need to be loaded. If 'IsMemset' is
2046 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
2047 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
2048 /// source is constant so it does not need to be loaded.
2049 /// It returns EVT::Other if the type should be determined using generic
2050 /// target-independent logic.
2051 /// For vector ops we check that the overall size isn't larger than our
2052 /// preferred vector width.
2054  uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
2055  bool ZeroMemset, bool MemcpyStrSrc,
2056  const AttributeList &FuncAttributes) const {
2057  if (!FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat)) {
2058  if (Size >= 16 && (!Subtarget.isUnalignedMem16Slow() ||
2059  ((DstAlign == 0 || DstAlign >= 16) &&
2060  (SrcAlign == 0 || SrcAlign >= 16)))) {
2061  // FIXME: Check if unaligned 32-byte accesses are slow.
2062  if (Size >= 32 && Subtarget.hasAVX() &&
2063  (Subtarget.getPreferVectorWidth() >= 256)) {
2064  // Although this isn't a well-supported type for AVX1, we'll let
2065  // legalization and shuffle lowering produce the optimal codegen. If we
2066  // choose an optimal type with a vector element larger than a byte,
2067  // getMemsetStores() may create an intermediate splat (using an integer
2068  // multiply) before we splat as a vector.
2069  return MVT::v32i8;
2070  }
2071  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2072  return MVT::v16i8;
2073  // TODO: Can SSE1 handle a byte vector?
2074  // If we have SSE1 registers we should be able to use them.
2075  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2076  (Subtarget.getPreferVectorWidth() >= 128))
2077  return MVT::v4f32;
2078  } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
2079  !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2080  // Do not use f64 to lower memcpy if source is string constant. It's
2081  // better to use i32 to avoid the loads.
2082  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2083  // The gymnastics of splatting a byte value into an XMM register and then
2084  // only using 8-byte stores (because this is a CPU with slow unaligned
2085  // 16-byte accesses) makes that a loser.
2086  return MVT::f64;
2087  }
2088  }
2089  // This is a compromise. If we reach here, unaligned accesses may be slow on
2090  // this target. However, creating smaller, aligned accesses could be even
2091  // slower and would certainly be a lot more code.
2092  if (Subtarget.is64Bit() && Size >= 8)
2093  return MVT::i64;
2094  return MVT::i32;
2095 }
2096 
2098  if (VT == MVT::f32)
2099  return X86ScalarSSEf32;
2100  else if (VT == MVT::f64)
2101  return X86ScalarSSEf64;
2102  return true;
2103 }
2104 
2106  EVT VT, unsigned, unsigned Align, MachineMemOperand::Flags Flags,
2107  bool *Fast) const {
2108  if (Fast) {
2109  switch (VT.getSizeInBits()) {
2110  default:
2111  // 8-byte and under are always assumed to be fast.
2112  *Fast = true;
2113  break;
2114  case 128:
2115  *Fast = !Subtarget.isUnalignedMem16Slow();
2116  break;
2117  case 256:
2118  *Fast = !Subtarget.isUnalignedMem32Slow();
2119  break;
2120  // TODO: What about AVX-512 (512-bit) accesses?
2121  }
2122  }
2123  // NonTemporal vector memory ops must be aligned.
2124  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2125  // NT loads can only be vector aligned, so if its less aligned than the
2126  // minimum vector size (which we can split the vector down to), we might as
2127  // well use a regular unaligned vector load.
2128  // We don't have any NT loads pre-SSE41.
2129  if (!!(Flags & MachineMemOperand::MOLoad))
2130  return (Align < 16 || !Subtarget.hasSSE41());
2131  return false;
2132  }
2133  // Misaligned accesses of any size are always allowed.
2134  return true;
2135 }
2136 
2137 /// Return the entry encoding for a jump table in the
2138 /// current function. The returned value is a member of the
2139 /// MachineJumpTableInfo::JTEntryKind enum.
2141  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2142  // symbol.
2143  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2145 
2146  // Otherwise, use the normal jump table encoding heuristics.
2148 }
2149 
2151  return Subtarget.useSoftFloat();
2152 }
2153 
2155  ArgListTy &Args) const {
2156 
2157  // Only relabel X86-32 for C / Stdcall CCs.
2158  if (Subtarget.is64Bit())
2159  return;
2160  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2161  return;
2162  unsigned ParamRegs = 0;
2163  if (auto *M = MF->getFunction().getParent())
2164  ParamRegs = M->getNumberRegisterParameters();
2165 
2166  // Mark the first N int arguments as having reg
2167  for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
2168  Type *T = Args[Idx].Ty;
2169  if (T->isIntOrPtrTy())
2170  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2171  unsigned numRegs = 1;
2172  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2173  numRegs = 2;
2174  if (ParamRegs < numRegs)
2175  return;
2176  ParamRegs -= numRegs;
2177  Args[Idx].IsInReg = true;
2178  }
2179  }
2180 }
2181 
2182 const MCExpr *
2184  const MachineBasicBlock *MBB,
2185  unsigned uid,MCContext &Ctx) const{
2186  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2187  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2188  // entries.
2189  return MCSymbolRefExpr::create(MBB->getSymbol(),
2191 }
2192 
2193 /// Returns relocation base for the given PIC jumptable.
2195  SelectionDAG &DAG) const {
2196  if (!Subtarget.is64Bit())
2197  // This doesn't have SDLoc associated with it, but is not really the
2198  // same as a Register.
2199  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2200  getPointerTy(DAG.getDataLayout()));
2201  return Table;
2202 }
2203 
2204 /// This returns the relocation base for the given PIC jumptable,
2205 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2208  MCContext &Ctx) const {
2209  // X86-64 uses RIP relative addressing based on the jump table label.
2210  if (Subtarget.isPICStyleRIPRel())
2211  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2212 
2213  // Otherwise, the reference is relative to the PIC base.
2214  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2215 }
2216 
2217 std::pair<const TargetRegisterClass *, uint8_t>
2219  MVT VT) const {
2220  const TargetRegisterClass *RRC = nullptr;
2221  uint8_t Cost = 1;
2222  switch (VT.SimpleTy) {
2223  default:
2225  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2226  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2227  break;
2228  case MVT::x86mmx:
2229  RRC = &X86::VR64RegClass;
2230  break;
2231  case MVT::f32: case MVT::f64:
2232  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2233  case MVT::v4f32: case MVT::v2f64:
2234  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2235  case MVT::v8f32: case MVT::v4f64:
2236  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2237  case MVT::v16f32: case MVT::v8f64:
2238  RRC = &X86::VR128XRegClass;
2239  break;
2240  }
2241  return std::make_pair(RRC, Cost);
2242 }
2243 
2244 unsigned X86TargetLowering::getAddressSpace() const {
2245  if (Subtarget.is64Bit())
2246  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2247  return 256;
2248 }
2249 
2250 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2251  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2252  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2253 }
2254 
2256  unsigned Offset, unsigned AddressSpace) {
2259  Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2260 }
2261 
2263  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2264  // tcbhead_t; use it instead of the usual global variable (see
2265  // sysdeps/{i386,x86_64}/nptl/tls.h)
2266  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2267  if (Subtarget.isTargetFuchsia()) {
2268  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2269  return SegmentOffset(IRB, 0x10, getAddressSpace());
2270  } else {
2271  // %fs:0x28, unless we're using a Kernel code model, in which case
2272  // it's %gs:0x28. gs:0x14 on i386.
2273  unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2274  return SegmentOffset(IRB, Offset, getAddressSpace());
2275  }
2276  }
2277 
2278  return TargetLowering::getIRStackGuard(IRB);
2279 }
2280 
2282  // MSVC CRT provides functionalities for stack protection.
2283  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2285  // MSVC CRT has a global variable holding security cookie.
2286  M.getOrInsertGlobal("__security_cookie",
2288 
2289  // MSVC CRT has a function to validate security cookie.
2290  FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2291  "__security_check_cookie", Type::getVoidTy(M.getContext()),
2293  if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2294  F->setCallingConv(CallingConv::X86_FastCall);
2295  F->addAttribute(1, Attribute::AttrKind::InReg);
2296  }
2297  return;
2298  }
2299  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2300  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2301  return;
2303 }
2304 
2306  // MSVC CRT has a global variable holding security cookie.
2307  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2309  return M.getGlobalVariable("__security_cookie");
2310  }
2312 }
2313 
2315  // MSVC CRT has a function to validate security cookie.
2316  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2318  return M.getFunction("__security_check_cookie");
2319  }
2321 }
2322 
2324  if (Subtarget.getTargetTriple().isOSContiki())
2325  return getDefaultSafeStackPointerLocation(IRB, false);
2326 
2327  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2328  // definition of TLS_SLOT_SAFESTACK in
2329  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2330  if (Subtarget.isTargetAndroid()) {
2331  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2332  // %gs:0x24 on i386
2333  unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2334  return SegmentOffset(IRB, Offset, getAddressSpace());
2335  }
2336 
2337  // Fuchsia is similar.
2338  if (Subtarget.isTargetFuchsia()) {
2339  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2340  return SegmentOffset(IRB, 0x18, getAddressSpace());
2341  }
2342 
2344 }
2345 
2347  unsigned DestAS) const {
2348  assert(SrcAS != DestAS && "Expected different address spaces!");
2349 
2350  return SrcAS < 256 && DestAS < 256;
2351 }
2352 
2353 //===----------------------------------------------------------------------===//
2354 // Return Value Calling Convention Implementation
2355 //===----------------------------------------------------------------------===//
2356 
2357 bool X86TargetLowering::CanLowerReturn(
2358  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2359  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2361  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2362  return CCInfo.CheckReturn(Outs, RetCC_X86);
2363 }
2364 
2365 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2366  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2367  return ScratchRegs;
2368 }
2369 
2370 /// Lowers masks values (v*i1) to the local register values
2371 /// \returns DAG node after lowering to register type
2372 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2373  const SDLoc &Dl, SelectionDAG &DAG) {
2374  EVT ValVT = ValArg.getValueType();
2375 
2376  if (ValVT == MVT::v1i1)
2377  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2378  DAG.getIntPtrConstant(0, Dl));
2379 
2380  if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2381  (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2382  // Two stage lowering might be required
2383  // bitcast: v8i1 -> i8 / v16i1 -> i16
2384  // anyextend: i8 -> i32 / i16 -> i32
2385  EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2386  SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2387  if (ValLoc == MVT::i32)
2388  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2389  return ValToCopy;
2390  }
2391 
2392  if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2393  (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2394  // One stage lowering is required
2395  // bitcast: v32i1 -> i32 / v64i1 -> i64
2396  return DAG.getBitcast(ValLoc, ValArg);
2397  }
2398 
2399  return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2400 }
2401 
2402 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2404  const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
2405  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
2406  CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2407  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
2408  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2409  assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
2410  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2411  "The value should reside in two registers");
2412 
2413  // Before splitting the value we cast it to i64
2414  Arg = DAG.getBitcast(MVT::i64, Arg);
2415 
2416  // Splitting the value into two i32 types
2417  SDValue Lo, Hi;
2418  Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2419  DAG.getConstant(0, Dl, MVT::i32));
2420  Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2421  DAG.getConstant(1, Dl, MVT::i32));
2422 
2423  // Attach the two i32 types into corresponding registers
2424  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2425  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2426 }
2427 
2428 SDValue
2429 X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2430  bool isVarArg,
2431  const SmallVectorImpl<ISD::OutputArg> &Outs,
2432  const SmallVectorImpl<SDValue> &OutVals,
2433  const SDLoc &dl, SelectionDAG &DAG) const {
2434  MachineFunction &MF = DAG.getMachineFunction();
2436 
2437  // In some cases we need to disable registers from the default CSR list.
2438  // For example, when they are used for argument passing.
2439  bool ShouldDisableCalleeSavedRegister =
2440  CallConv == CallingConv::X86_RegCall ||
2441  MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2442 
2443  if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2444  report_fatal_error("X86 interrupts may not return any value");
2445 
2447  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2448  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2449 
2450  SDValue Flag;
2451  SmallVector<SDValue, 6> RetOps;
2452  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2453  // Operand #1 = Bytes To Pop
2454  RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2455  MVT::i32));
2456 
2457  // Copy the result values into the output registers.
2458  for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2459  ++I, ++OutsIndex) {
2460  CCValAssign &VA = RVLocs[I];
2461  assert(VA.isRegLoc() && "Can only return in registers!");
2462 
2463  // Add the register to the CalleeSaveDisableRegs list.
2464  if (ShouldDisableCalleeSavedRegister)
2466 
2467  SDValue ValToCopy = OutVals[OutsIndex];
2468  EVT ValVT = ValToCopy.getValueType();
2469 
2470  // Promote values to the appropriate types.
2471  if (VA.getLocInfo() == CCValAssign::SExt)
2472  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2473  else if (VA.getLocInfo() == CCValAssign::ZExt)
2474  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2475  else if (VA.getLocInfo() == CCValAssign::AExt) {
2476  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2477  ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2478  else
2479  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2480  }
2481  else if (VA.getLocInfo() == CCValAssign::BCvt)
2482  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2483 
2485  "Unexpected FP-extend for return value.");
2486 
2487  // If this is x86-64, and we disabled SSE, we can't return FP values,
2488  // or SSE or MMX vectors.
2489  if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2490  VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2491  (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {
2492  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2493  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2494  } else if (ValVT == MVT::f64 &&
2495  (Subtarget.is64Bit() && !Subtarget.hasSSE2())) {
2496  // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2497  // llvm-gcc has never done it right and no one has noticed, so this
2498  // should be OK for now.
2499  errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2500  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2501  }
2502 
2503  // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2504  // the RET instruction and handled by the FP Stackifier.
2505  if (VA.getLocReg() == X86::FP0 ||
2506  VA.getLocReg() == X86::FP1) {
2507  // If this is a copy from an xmm register to ST(0), use an FPExtend to
2508  // change the value to the FP stack register class.
2509  if (isScalarFPTypeInSSEReg(VA.getValVT()))
2510  ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2511  RetOps.push_back(ValToCopy);
2512  // Don't emit a copytoreg.
2513  continue;
2514  }
2515 
2516  // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2517  // which is returned in RAX / RDX.
2518  if (Subtarget.is64Bit()) {
2519  if (ValVT == MVT::x86mmx) {
2520  if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2521  ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2522  ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2523  ValToCopy);
2524  // If we don't have SSE2 available, convert to v4f32 so the generated
2525  // register is legal.
2526  if (!Subtarget.hasSSE2())
2527  ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2528  }
2529  }
2530  }
2531 
2533 
2534  if (VA.needsCustom()) {
2535  assert(VA.getValVT() == MVT::v64i1 &&
2536  "Currently the only custom case is when we split v64i1 to 2 regs");
2537 
2538  Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
2539  Subtarget);
2540 
2541  assert(2 == RegsToPass.size() &&
2542  "Expecting two registers after Pass64BitArgInRegs");
2543 
2544  // Add the second register to the CalleeSaveDisableRegs list.
2545  if (ShouldDisableCalleeSavedRegister)
2546  MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2547  } else {
2548  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2549  }
2550 
2551  // Add nodes to the DAG and add the values into the RetOps list
2552  for (auto &Reg : RegsToPass) {
2553  Chain = DAG.getCopyToReg(Chain, dl, Reg.first, Reg.second, Flag);
2554  Flag = Chain.getValue(1);
2555  RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2556  }
2557  }
2558 
2559  // Swift calling convention does not require we copy the sret argument
2560  // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2561 
2562  // All x86 ABIs require that for returning structs by value we copy
2563  // the sret argument into %rax/%eax (depending on ABI) for the return.
2564  // We saved the argument into a virtual register in the entry block,
2565  // so now we copy the value out and into %rax/%eax.
2566  //
2567  // Checking Function.hasStructRetAttr() here is insufficient because the IR
2568  // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2569  // false, then an sret argument may be implicitly inserted in the SelDAG. In
2570  // either case FuncInfo->setSRetReturnReg() will have been called.
2571  if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2572  // When we have both sret and another return value, we should use the
2573  // original Chain stored in RetOps[0], instead of the current Chain updated
2574  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2575 
2576  // For the case of sret and another return value, we have
2577  // Chain_0 at the function entry
2578  // Chain_1 = getCopyToReg(Chain_0) in the above loop
2579  // If we use Chain_1 in getCopyFromReg, we will have
2580  // Val = getCopyFromReg(Chain_1)
2581  // Chain_2 = getCopyToReg(Chain_1, Val) from below
2582 
2583  // getCopyToReg(Chain_0) will be glued together with
2584  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2585  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2586  // Data dependency from Unit B to Unit A due to usage of Val in
2587  // getCopyToReg(Chain_1, Val)
2588  // Chain dependency from Unit A to Unit B
2589 
2590  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2591  SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2592  getPointerTy(MF.getDataLayout()));
2593 
2594  unsigned RetValReg
2595  = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2596  X86::RAX : X86::EAX;
2597  Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2598  Flag = Chain.getValue(1);
2599 
2600  // RAX/EAX now acts like a return value.
2601  RetOps.push_back(
2602  DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2603 
2604  // Add the returned register to the CalleeSaveDisableRegs list.
2605  if (ShouldDisableCalleeSavedRegister)
2606  MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2607  }
2608 
2609  const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2610  const MCPhysReg *I =
2612  if (I) {
2613  for (; *I; ++I) {
2614  if (X86::GR64RegClass.contains(*I))
2615  RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2616  else
2617  llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2618  }
2619  }
2620 
2621  RetOps[0] = Chain; // Update chain.
2622 
2623  // Add the flag if we have it.
2624  if (Flag.getNode())
2625  RetOps.push_back(Flag);
2626 
2628  if (CallConv == CallingConv::X86_INTR)
2629  opcode = X86ISD::IRET;
2630  return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2631 }
2632 
2633 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2634  if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2635  return false;
2636 
2637  SDValue TCChain = Chain;
2638  SDNode *Copy = *N->use_begin();
2639  if (Copy->getOpcode() == ISD::CopyToReg) {
2640  // If the copy has a glue operand, we conservatively assume it isn't safe to
2641  // perform a tail call.
2642  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2643  return false;
2644  TCChain = Copy->getOperand(0);
2645  } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2646  return false;
2647 
2648  bool HasRet = false;
2649  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2650  UI != UE; ++UI) {
2651  if (UI->getOpcode() != X86ISD::RET_FLAG)
2652  return false;
2653  // If we are returning more than one value, we can definitely
2654  // not make a tail call see PR19530
2655  if (UI->getNumOperands() > 4)
2656  return false;
2657  if (UI->getNumOperands() == 4 &&
2658  UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2659  return false;
2660  HasRet = true;
2661  }
2662 
2663  if (!HasRet)
2664  return false;
2665 
2666  Chain = TCChain;
2667  return true;
2668 }
2669 
2670 EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2671  ISD::NodeType ExtendKind) const {
2672  MVT ReturnMVT = MVT::i32;
2673 
2674  bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2675  if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2676  // The ABI does not require i1, i8 or i16 to be extended.
2677  //
2678  // On Darwin, there is code in the wild relying on Clang's old behaviour of
2679  // always extending i8/i16 return values, so keep doing that for now.
2680  // (PR26665).
2681  ReturnMVT = MVT::i8;
2682  }
2683 
2684  EVT MinVT = getRegisterType(Context, ReturnMVT);
2685  return VT.bitsLT(MinVT) ? MinVT : VT;
2686 }
2687 
2688 /// Reads two 32 bit registers and creates a 64 bit mask value.
2689 /// \param VA The current 32 bit value that need to be assigned.
2690 /// \param NextVA The next 32 bit value that need to be assigned.
2691 /// \param Root The parent DAG node.
2692 /// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2693 /// glue purposes. In the case the DAG is already using
2694 /// physical register instead of virtual, we should glue
2695 /// our new SDValue to InFlag SDvalue.
2696 /// \return a new SDvalue of size 64bit.
2698  SDValue &Root, SelectionDAG &DAG,
2699  const SDLoc &Dl, const X86Subtarget &Subtarget,
2700  SDValue *InFlag = nullptr) {
2701  assert((Subtarget.hasBWI()) && "Expected AVX512BW target!");
2702  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2703  assert(VA.getValVT() == MVT::v64i1 &&
2704  "Expecting first location of 64 bit width type");
2705  assert(NextVA.getValVT() == VA.getValVT() &&
2706  "The locations should have the same type");
2707  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2708  "The values should reside in two registers");
2709 
2710  SDValue Lo, Hi;
2711  SDValue ArgValueLo, ArgValueHi;
2712 
2713  MachineFunction &MF = DAG.getMachineFunction();
2714  const TargetRegisterClass *RC = &X86::GR32RegClass;
2715 
2716  // Read a 32 bit value from the registers.
2717  if (nullptr == InFlag) {
2718  // When no physical register is present,
2719  // create an intermediate virtual register.
2720  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2721  ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2722  Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2723  ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2724  } else {
2725  // When a physical register is available read the value from it and glue
2726  // the reads together.
2727  ArgValueLo =
2728  DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2729  *InFlag = ArgValueLo.getValue(2);
2730  ArgValueHi =
2731  DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2732  *InFlag = ArgValueHi.getValue(2);
2733  }
2734 
2735  // Convert the i32 type into v32i1 type.
2736  Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2737 
2738  // Convert the i32 type into v32i1 type.
2739  Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2740 
2741  // Concatenate the two values together.
2742  return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2743 }
2744 
2745 /// The function will lower a register of various sizes (8/16/32/64)
2746 /// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2747 /// \returns a DAG node contains the operand after lowering to mask type.
2748 static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2749  const EVT &ValLoc, const SDLoc &Dl,
2750  SelectionDAG &DAG) {
2751  SDValue ValReturned = ValArg;
2752 
2753  if (ValVT == MVT::v1i1)
2754  return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2755 
2756  if (ValVT == MVT::v64i1) {
2757  // In 32 bit machine, this case is handled by getv64i1Argument
2758  assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
2759  // In 64 bit machine, There is no need to truncate the value only bitcast
2760  } else {
2761  MVT maskLen;
2762  switch (ValVT.getSimpleVT().SimpleTy) {
2763  case MVT::v8i1:
2764  maskLen = MVT::i8;
2765  break;
2766  case MVT::v16i1:
2767  maskLen = MVT::i16;
2768  break;
2769  case MVT::v32i1:
2770  maskLen = MVT::i32;
2771  break;
2772  default:
2773  llvm_unreachable("Expecting a vector of i1 types");
2774  }
2775 
2776  ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
2777  }
2778  return DAG.getBitcast(ValVT, ValReturned);
2779 }
2780 
2781 /// Lower the result values of a call into the
2782 /// appropriate copies out of appropriate physical registers.
2783 ///
2784 SDValue X86TargetLowering::LowerCallResult(
2785  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2786  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2787  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2788  uint32_t *RegMask) const {
2789 
2790  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2791  // Assign locations to each value returned by this call.
2793  bool Is64Bit = Subtarget.is64Bit();
2794  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2795  *DAG.getContext());
2796  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2797 
2798  // Copy all of the result registers out of their specified physreg.
2799  for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
2800  ++I, ++InsIndex) {
2801  CCValAssign &VA = RVLocs[I];
2802  EVT CopyVT = VA.getLocVT();
2803 
2804  // In some calling conventions we need to remove the used registers
2805  // from the register mask.
2806  if (RegMask) {
2807  for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
2808  SubRegs.isValid(); ++SubRegs)
2809  RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2810  }
2811 
2812  // If this is x86-64, and we disabled SSE, we can't return FP values
2813  if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2814  ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
2815  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2816  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2817  }
2818 
2819  // If we prefer to use the value in xmm registers, copy it out as f80 and
2820  // use a truncate to move it from fp stack reg to xmm reg.
2821  bool RoundAfterCopy = false;
2822  if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2824  if (!Subtarget.hasX87())
2825  report_fatal_error("X87 register return with X87 disabled");
2826  CopyVT = MVT::f80;
2827  RoundAfterCopy = (CopyVT != VA.getLocVT());
2828  }
2829 
2830  SDValue Val;
2831  if (VA.needsCustom()) {
2832  assert(VA.getValVT() == MVT::v64i1 &&
2833  "Currently the only custom case is when we split v64i1 to 2 regs");
2834  Val =
2835  getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
2836  } else {
2837  Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
2838  .getValue(1);
2839  Val = Chain.getValue(0);
2840  InFlag = Chain.getValue(2);
2841  }
2842 
2843  if (RoundAfterCopy)
2844  Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2845  // This truncation won't change the value.
2846  DAG.getIntPtrConstant(1, dl));
2847 
2848  if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2849  if (VA.getValVT().isVector() &&
2850  ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2851  (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2852  // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
2853  Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2854  } else
2855  Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2856  }
2857 
2858  InVals.push_back(Val);
2859  }
2860 
2861  return Chain;
2862 }
2863 
2864 //===----------------------------------------------------------------------===//
2865 // C & StdCall & Fast Calling Convention implementation
2866 //===----------------------------------------------------------------------===//
2867 // StdCall calling convention seems to be standard for many Windows' API
2868 // routines and around. It differs from C calling convention just a little:
2869 // callee should clean up the stack, not caller. Symbols should be also
2870 // decorated in some fancy way :) It doesn't support any vector arguments.
2871 // For info on fast calling convention see Fast Calling Convention (tail call)
2872 // implementation LowerX86_32FastCCCallTo.
2873 
2874 /// CallIsStructReturn - Determines whether a call uses struct return
2875 /// semantics.
2880 };
2881 static StructReturnType
2883  if (Outs.empty())
2884  return NotStructReturn;
2885 
2886  const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2887  if (!Flags.isSRet())
2888  return NotStructReturn;
2889  if (Flags.isInReg() || IsMCU)
2890  return RegStructReturn;
2891  return StackStructReturn;
2892 }
2893 
2894 /// Determines whether a function uses struct return semantics.
2895 static StructReturnType
2897  if (Ins.empty())
2898  return NotStructReturn;
2899 
2900  const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2901  if (!Flags.isSRet())
2902  return NotStructReturn;
2903  if (Flags.isInReg() || IsMCU)
2904  return RegStructReturn;
2905  return StackStructReturn;
2906 }
2907 
2908 /// Make a copy of an aggregate at address specified by "Src" to address
2909 /// "Dst" with size and alignment information specified by the specific
2910 /// parameter attribute. The copy will be passed as a byval function parameter.
2912  SDValue Chain, ISD::ArgFlagsTy Flags,
2913  SelectionDAG &DAG, const SDLoc &dl) {
2914  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2915 
2916  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2917  /*isVolatile*/false, /*AlwaysInline=*/true,
2918  /*isTailCall*/false,
2920 }
2921 
2922 /// Return true if the calling convention is one that we can guarantee TCO for.
2924  return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2926  CC == CallingConv::HHVM);
2927 }
2928 
2929 /// Return true if we might ever do TCO for calls with this calling convention.
2931  switch (CC) {
2932  // C calling conventions:
2933  case CallingConv::C:
2934  case CallingConv::Win64:
2936  // Callee pop conventions:
2941  // Swift:
2942  case CallingConv::Swift:
2943  return true;
2944  default:
2945  return canGuaranteeTCO(CC);
2946  }
2947 }
2948 
2949 /// Return true if the function is being made into a tailcall target by
2950 /// changing its ABI.
2951 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2952  return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2953 }
2954 
2955 bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2956  auto Attr =
2957  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2958  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2959  return false;
2960 
2961  ImmutableCallSite CS(CI);
2962  CallingConv::ID CalleeCC = CS.getCallingConv();
2963  if (!mayTailCallThisCC(CalleeCC))
2964  return false;
2965 
2966  return true;
2967 }
2968 
2969 SDValue
2970 X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
2971  const SmallVectorImpl<ISD::InputArg> &Ins,
2972  const SDLoc &dl, SelectionDAG &DAG,
2973  const CCValAssign &VA,
2974  MachineFrameInfo &MFI, unsigned i) const {
2975  // Create the nodes corresponding to a load from this parameter slot.
2976  ISD::ArgFlagsTy Flags = Ins[i].Flags;
2977  bool AlwaysUseMutable = shouldGuaranteeTCO(
2978  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2979  bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2980  EVT ValVT;
2981  MVT PtrVT = getPointerTy(DAG.getDataLayout());
2982 
2983  // If value is passed by pointer we have address passed instead of the value
2984  // itself. No need to extend if the mask value and location share the same
2985  // absolute size.
2986  bool ExtendedInMem =
2987  VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
2988  VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
2989 
2990  if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2991  ValVT = VA.getLocVT();
2992  else
2993  ValVT = VA.getValVT();
2994 
2995  // FIXME: For now, all byval parameter objects are marked mutable. This can be
2996  // changed with more analysis.
2997  // In case of tail call optimization mark all arguments mutable. Since they
2998  // could be overwritten by lowering of arguments in case of a tail call.
2999  if (Flags.isByVal()) {
3000  unsigned Bytes = Flags.getByValSize();
3001  if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3002 
3003  // FIXME: For now, all byval parameter objects are marked as aliasing. This
3004  // can be improved with deeper analysis.
3005  int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3006  /*isAliased=*/true);
3007  return DAG.getFrameIndex(FI, PtrVT);
3008  }
3009 
3010  // This is an argument in memory. We might be able to perform copy elision.
3011  // If the argument is passed directly in memory without any extension, then we
3012  // can perform copy elision. Large vector types, for example, may be passed
3013  // indirectly by pointer.
3014  if (Flags.isCopyElisionCandidate() &&
3015  VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem) {
3016  EVT ArgVT = Ins[i].ArgVT;
3017  SDValue PartAddr;
3018  if (Ins[i].PartOffset == 0) {
3019  // If this is a one-part value or the first part of a multi-part value,
3020  // create a stack object for the entire argument value type and return a
3021  // load from our portion of it. This assumes that if the first part of an
3022  // argument is in memory, the rest will also be in memory.
3023  int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3024  /*IsImmutable=*/false);
3025  PartAddr = DAG.getFrameIndex(FI, PtrVT);
3026  return DAG.getLoad(
3027  ValVT, dl, Chain, PartAddr,
3029  } else {
3030  // This is not the first piece of an argument in memory. See if there is
3031  // already a fixed stack object including this offset. If so, assume it
3032  // was created by the PartOffset == 0 branch above and create a load from
3033  // the appropriate offset into it.
3034  int64_t PartBegin = VA.getLocMemOffset();
3035  int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3036  int FI = MFI.getObjectIndexBegin();
3037  for (; MFI.isFixedObjectIndex(FI); ++FI) {
3038  int64_t ObjBegin = MFI.getObjectOffset(FI);
3039  int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3040  if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3041  break;
3042  }
3043  if (MFI.isFixedObjectIndex(FI)) {
3044  SDValue Addr =
3045  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3046  DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3047  return DAG.getLoad(
3048  ValVT, dl, Chain, Addr,
3050  Ins[i].PartOffset));
3051  }
3052  }
3053  }
3054 
3055  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3056  VA.getLocMemOffset(), isImmutable);
3057 
3058  // Set SExt or ZExt flag.
3059  if (VA.getLocInfo() == CCValAssign::ZExt) {
3060  MFI.setObjectZExt(FI, true);
3061  } else if (VA.getLocInfo() == CCValAssign::SExt) {
3062  MFI.setObjectSExt(FI, true);
3063  }
3064 
3065  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3066  SDValue Val = DAG.getLoad(
3067  ValVT, dl, Chain, FIN,
3069  return ExtendedInMem
3070  ? (VA.getValVT().isVector()
3071  ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3072  : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3073  : Val;
3074 }
3075 
3076 // FIXME: Get this from tablegen.
3078  const X86Subtarget &Subtarget) {
3079  assert(Subtarget.is64Bit());
3080 
3081  if (Subtarget.isCallingConvWin64(CallConv)) {
3082  static const MCPhysReg GPR64ArgRegsWin64[] = {
3083  X86::RCX, X86::RDX, X86::R8, X86::R9
3084  };
3085  return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3086  }
3087 
3088  static const MCPhysReg GPR64ArgRegs64Bit[] = {
3089  X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3090  };
3091  return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3092 }
3093 
3094 // FIXME: Get this from tablegen.
3096  CallingConv::ID CallConv,
3097  const X86Subtarget &Subtarget) {
3098  assert(Subtarget.is64Bit());
3099  if (Subtarget.isCallingConvWin64(CallConv)) {
3100  // The XMM registers which might contain var arg parameters are shadowed
3101  // in their paired GPR. So we only need to save the GPR to their home
3102  // slots.
3103  // TODO: __vectorcall will change this.
3104  return None;
3105  }
3106 
3107  const Function &F = MF.getFunction();
3108  bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
3109  bool isSoftFloat = Subtarget.useSoftFloat();
3110  assert(!(isSoftFloat && NoImplicitFloatOps) &&
3111  "SSE register cannot be used when SSE is disabled!");
3112  if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
3113  // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3114  // registers.
3115  return None;
3116 
3117  static const MCPhysReg XMMArgRegs64Bit[] = {
3118  X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3119  X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3120  };
3121  return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3122 }
3123 
3124 #ifndef NDEBUG
3126  return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
3127  [](const CCValAssign &A, const CCValAssign &B) -> bool {
3128  return A.getValNo() < B.getValNo();
3129  });
3130 }
3131 #endif
3132 
3133 SDValue X86TargetLowering::LowerFormalArguments(
3134  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3135  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3136  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3137  MachineFunction &MF = DAG.getMachineFunction();
3139  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3140 
3141  const Function &F = MF.getFunction();
3142  if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3143  F.getName() == "main")
3144  FuncInfo->setForceFramePointer(true);
3145 
3146  MachineFrameInfo &MFI = MF.getFrameInfo();
3147  bool Is64Bit = Subtarget.is64Bit();
3148  bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3149 
3150  assert(
3151  !(isVarArg && canGuaranteeTCO(CallConv)) &&
3152  "Var args not supported with calling conv' regcall, fastcc, ghc or hipe");
3153 
3154  // Assign locations to all of the incoming arguments.
3156  CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3157 
3158  // Allocate shadow area for Win64.
3159  if (IsWin64)
3160  CCInfo.AllocateStack(32, 8);
3161 
3162  CCInfo.AnalyzeArguments(Ins, CC_X86);
3163 
3164  // In vectorcall calling convention a second pass is required for the HVA
3165  // types.
3166  if (CallingConv::X86_VectorCall == CallConv) {
3167  CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3168  }
3169 
3170  // The next loop assumes that the locations are in the same order of the
3171  // input arguments.
3172  assert(isSortedByValueNo(ArgLocs) &&
3173  "Argument Location list must be sorted before lowering");
3174 
3175  SDValue ArgValue;
3176  for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3177  ++I, ++InsIndex) {
3178  assert(InsIndex < Ins.size() && "Invalid Ins index");
3179  CCValAssign &VA = ArgLocs[I];
3180 
3181  if (VA.isRegLoc()) {
3182  EVT RegVT = VA.getLocVT();
3183  if (VA.needsCustom()) {
3184  assert(
3185  VA.getValVT() == MVT::v64i1 &&
3186  "Currently the only custom case is when we split v64i1 to 2 regs");
3187 
3188  // v64i1 values, in regcall calling convention, that are
3189  // compiled to 32 bit arch, are split up into two registers.
3190  ArgValue =
3191  getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3192  } else {
3193  const TargetRegisterClass *RC;
3194  if (RegVT == MVT::i8)
3195  RC = &X86::GR8RegClass;
3196  else if (RegVT == MVT::i16)
3197  RC = &X86::GR16RegClass;
3198  else if (RegVT == MVT::i32)
3199  RC = &X86::GR32RegClass;
3200  else if (Is64Bit && RegVT == MVT::i64)
3201  RC = &X86::GR64RegClass;
3202  else if (RegVT == MVT::f32)
3203  RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3204  else if (RegVT == MVT::f64)
3205  RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3206  else if (RegVT == MVT::f80)
3207  RC = &X86::RFP80RegClass;
3208  else if (RegVT == MVT::f128)
3209  RC = &X86::VR128RegClass;
3210  else if (RegVT.is512BitVector())
3211  RC = &X86::VR512RegClass;
3212  else if (RegVT.is256BitVector())
3213  RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3214  else if (RegVT.is128BitVector())
3215  RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3216  else if (RegVT == MVT::x86mmx)
3217  RC = &X86::VR64RegClass;
3218  else if (RegVT == MVT::v1i1)
3219  RC = &X86::VK1RegClass;
3220  else if (RegVT == MVT::v8i1)
3221  RC = &X86::VK8RegClass;
3222  else if (RegVT == MVT::v16i1)
3223  RC = &X86::VK16RegClass;
3224  else if (RegVT == MVT::v32i1)
3225  RC = &X86::VK32RegClass;
3226  else if (RegVT == MVT::v64i1)
3227  RC = &X86::VK64RegClass;
3228  else
3229  llvm_unreachable("Unknown argument type!");
3230 
3231  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3232  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3233  }
3234 
3235  // If this is an 8 or 16-bit value, it is really passed promoted to 32
3236  // bits. Insert an assert[sz]ext to capture this, then truncate to the
3237  // right size.
3238  if (VA.getLocInfo() == CCValAssign::SExt)
3239  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3240  DAG.getValueType(VA.getValVT()));
3241  else if (VA.getLocInfo() == CCValAssign::ZExt)
3242  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3243  DAG.getValueType(VA.getValVT()));
3244  else if (VA.getLocInfo() == CCValAssign::BCvt)
3245  ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3246 
3247  if (VA.isExtInLoc()) {
3248  // Handle MMX values passed in XMM regs.
3249  if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3250  ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3251  else if (VA.getValVT().isVector() &&
3252  VA.getValVT().getScalarType() == MVT::i1 &&
3253  ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3254  (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3255  // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3256  ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3257  } else
3258  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3259  }
3260  } else {
3261  assert(VA.isMemLoc());
3262  ArgValue =
3263  LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3264  }
3265 
3266  // If value is passed via pointer - do a load.
3267  if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3268  ArgValue =
3269  DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3270 
3271  InVals.push_back(ArgValue);
3272  }
3273 
3274  for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3275  // Swift calling convention does not require we copy the sret argument
3276  // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3277  if (CallConv == CallingConv::Swift)
3278  continue;
3279 
3280  // All x86 ABIs require that for returning structs by value we copy the
3281  // sret argument into %rax/%eax (depending on ABI) for the return. Save
3282  // the argument into a virtual register so that we can access it from the
3283  // return points.
3284  if (Ins[I].Flags.isSRet()) {
3285  unsigned Reg = FuncInfo->getSRetReturnReg();
3286  if (!Reg) {
3287  MVT PtrTy = getPointerTy(DAG.getDataLayout());
3288  Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3289  FuncInfo->setSRetReturnReg(Reg);
3290  }
3291  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3292  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3293  break;
3294  }
3295  }
3296 
3297  unsigned StackSize = CCInfo.getNextStackOffset();
3298  // Align stack specially for tail calls.
3299  if (shouldGuaranteeTCO(CallConv,
3301  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3302 
3303  // If the function takes variable number of arguments, make a frame index for
3304  // the start of the first vararg value... for expansion of llvm.va_start. We
3305  // can skip this if there are no va_start calls.
3306  if (MFI.hasVAStart() &&
3307  (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3308  CallConv != CallingConv::X86_ThisCall))) {
3309  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3310  }
3311 
3312  // Figure out if XMM registers are in use.
3313  assert(!(Subtarget.useSoftFloat() &&
3314  F.hasFnAttribute(Attribute::NoImplicitFloat)) &&
3315  "SSE register cannot be used when SSE is disabled!");
3316 
3317  // 64-bit calling conventions support varargs and register parameters, so we
3318  // have to do extra work to spill them in the prologue.
3319  if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3320  // Find the first unallocated argument registers.
3321  ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3322  ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3323  unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3324  unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3325  assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&
3326  "SSE register cannot be used when SSE is disabled!");
3327 
3328  // Gather all the live in physical registers.
3329  SmallVector<SDValue, 6> LiveGPRs;
3330  SmallVector<SDValue, 8> LiveXMMRegs;
3331  SDValue ALVal;
3332  for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3333  unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3334  LiveGPRs.push_back(
3335  DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3336  }
3337  if (!ArgXMMs.empty()) {
3338  unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3339  ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3340  for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3341  unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3342  LiveXMMRegs.push_back(
3343  DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3344  }
3345  }
3346 
3347  if (IsWin64) {
3348  // Get to the caller-allocated home save location. Add 8 to account
3349  // for the return address.
3350  int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3351  FuncInfo->setRegSaveFrameIndex(
3352  MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3353  // Fixup to set vararg frame on shadow area (4 x i64).
3354  if (NumIntRegs < 4)
3355  FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3356  } else {
3357  // For X86-64, if there are vararg parameters that are passed via
3358  // registers, then we must store them to their spots on the stack so
3359  // they may be loaded by dereferencing the result of va_next.
3360  FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3361  FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3363  ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3364  }
3365 
3366  // Store the integer parameter registers.
3367  SmallVector<SDValue, 8> MemOps;
3368  SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3369  getPointerTy(DAG.getDataLayout()));
3370  unsigned Offset = FuncInfo->getVarArgsGPOffset();
3371  for (SDValue Val : LiveGPRs) {
3372  SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3373  RSFIN, DAG.getIntPtrConstant(Offset, dl));
3374  SDValue Store =
3375  DAG.getStore(Val.getValue(1), dl, Val, FIN,
3377  DAG.getMachineFunction(),
3378  FuncInfo->getRegSaveFrameIndex(), Offset));
3379  MemOps.push_back(Store);
3380  Offset += 8;
3381  }
3382 
3383  if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3384  // Now store the XMM (fp + vector) parameter registers.
3385  SmallVector<SDValue, 12> SaveXMMOps;
3386  SaveXMMOps.push_back(Chain);
3387  SaveXMMOps.push_back(ALVal);
3388  SaveXMMOps.push_back(DAG.getIntPtrConstant(
3389  FuncInfo->getRegSaveFrameIndex(), dl));
3390  SaveXMMOps.push_back(DAG.getIntPtrConstant(
3391  FuncInfo->getVarArgsFPOffset(), dl));
3392  SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3393  LiveXMMRegs.end());
3395  MVT::Other, SaveXMMOps));
3396  }
3397 
3398  if (!MemOps.empty())
3399  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3400  }
3401 
3402  if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3403  // Find the largest legal vector type.
3404  MVT VecVT = MVT::Other;
3405  // FIXME: Only some x86_32 calling conventions support AVX512.
3406  if (Subtarget.hasAVX512() &&
3407  (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3408  CallConv == CallingConv::Intel_OCL_BI)))
3409  VecVT = MVT::v16f32;
3410  else if (Subtarget.hasAVX())
3411  VecVT = MVT::v8f32;
3412  else if (Subtarget.hasSSE2())
3413  VecVT = MVT::v4f32;
3414 
3415  // We forward some GPRs and some vector types.
3416  SmallVector<MVT, 2> RegParmTypes;
3417  MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3418  RegParmTypes.push_back(IntVT);
3419  if (VecVT != MVT::Other)
3420  RegParmTypes.push_back(VecVT);
3421 
3422  // Compute the set of forwarded registers. The rest are scratch.
3424  FuncInfo->getForwardedMustTailRegParms();
3425  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3426 
3427  // Conservatively forward AL on x86_64, since it might be used for varargs.
3428  if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3429  unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3430  Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3431  }
3432 
3433  // Copy all forwards from physical to virtual registers.
3434  for (ForwardedRegister &FR : Forwards) {
3435  // FIXME: Can we use a less constrained schedule?
3436  SDValue RegVal = DAG.getCopyFromReg(Chain, dl, FR.VReg, FR.VT);
3437  FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
3438  Chain = DAG.getCopyToReg(Chain, dl, FR.VReg, RegVal);
3439  }
3440  }
3441 
3442  // Some CCs need callee pop.
3443  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3445  FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3446  } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3447  // X86 interrupts must pop the error code (and the alignment padding) if
3448  // present.
3449  FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3450  } else {
3451  FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3452  // If this is an sret function, the return should pop the hidden pointer.
3453  if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3454  !Subtarget.getTargetTriple().isOSMSVCRT() &&
3455  argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3456  FuncInfo->setBytesToPopOnReturn(4);
3457  }
3458 
3459  if (!Is64Bit) {
3460  // RegSaveFrameIndex is X86-64 only.
3461  FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3462  if (CallConv == CallingConv::X86_FastCall ||
3463  CallConv == CallingConv::X86_ThisCall)
3464  // fastcc functions can't have varargs.
3465  FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3466  }
3467 
3468  FuncInfo->setArgumentStackSize(StackSize);
3469 
3470  if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3472  if (Personality == EHPersonality::CoreCLR) {
3473  assert(Is64Bit);
3474  // TODO: Add a mechanism to frame lowering that will allow us to indicate
3475  // that we'd prefer this slot be allocated towards the bottom of the frame
3476  // (i.e. near the stack pointer after allocating the frame). Every
3477  // funclet needs a copy of this slot in its (mostly empty) frame, and the
3478  // offset from the bottom of this and each funclet's frame must be the
3479  // same, so the size of funclets' (mostly empty) frames is dictated by
3480  // how far this slot is from the bottom (since they allocate just enough
3481  // space to accommodate holding this slot at the correct offset).
3482  int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3483  EHInfo->PSPSymFrameIdx = PSPSymFI;
3484  }
3485  }
3486 
3487  if (CallConv == CallingConv::X86_RegCall ||
3488  F.hasFnAttribute("no_caller_saved_registers")) {
3490  for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3491  MRI.disableCalleeSavedRegister(Pair.first);
3492  }
3493 
3494  return Chain;
3495 }
3496 
3497 SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3498  SDValue Arg, const SDLoc &dl,
3499  SelectionDAG &DAG,
3500  const CCValAssign &VA,
3501  ISD::ArgFlagsTy Flags) const {
3502  unsigned LocMemOffset = VA.getLocMemOffset();
3503  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3504  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3505  StackPtr, PtrOff);
3506  if (Flags.isByVal())
3507  return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3508 
3509  return DAG.getStore(
3510  Chain, dl, Arg, PtrOff,
3511  MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3512 }
3513 
3514 /// Emit a load of return address if tail call
3515 /// optimization is performed and it is required.
3516 SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3517  SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3518  bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3519  // Adjust the Return address stack slot.
3520  EVT VT = getPointerTy(DAG.getDataLayout());
3521  OutRetAddr = getReturnAddressFrameIndex(DAG);
3522 
3523  // Load the "old" Return address.
3524  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3525  return SDValue(OutRetAddr.getNode(), 1);
3526 }
3527 
3528 /// Emit a store of the return address if tail call
3529 /// optimization is performed and it is required (FPDiff!=0).
3531  SDValue Chain, SDValue RetAddrFrIdx,
3532  EVT PtrVT, unsigned SlotSize,
3533  int FPDiff, const SDLoc &dl) {
3534  // Store the return address to the appropriate stack slot.
3535  if (!FPDiff) return Chain;
3536  // Calculate the new stack slot for the return address.
3537  int NewReturnAddrFI =
3538  MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3539  false);
3540  SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3541  Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3543  DAG.getMachineFunction(), NewReturnAddrFI));
3544  return Chain;
3545 }
3546 
3547 /// Returns a vector_shuffle mask for an movs{s|d}, movd
3548 /// operation of specified width.
3549 static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3550  SDValue V2) {
3551  unsigned NumElems = VT.getVectorNumElements();
3553  Mask.push_back(NumElems);
3554  for (unsigned i = 1; i != NumElems; ++i)
3555  Mask.push_back(i);
3556  return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3557 }
3558 
3559 SDValue
3560 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3561  SmallVectorImpl<SDValue> &InVals) const {
3562  SelectionDAG &DAG = CLI.DAG;
3563  SDLoc &dl = CLI.DL;
3565  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3567  SDValue Chain = CLI.Chain;
3568  SDValue Callee = CLI.Callee;
3569  CallingConv::ID CallConv = CLI.CallConv;
3570  bool &isTailCall = CLI.IsTailCall;
3571  bool isVarArg = CLI.IsVarArg;
3572 
3573  MachineFunction &MF = DAG.getMachineFunction();
3574  bool Is64Bit = Subtarget.is64Bit();
3575  bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3576  StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());
3577  bool IsSibcall = false;