LLVM  6.0.0svn
Enumerations | Functions
llvm::X86II Namespace Reference

X86II - This namespace holds all of the target specific flags that instruction info tracks. More...

Enumerations

enum  TOF {
  MO_NO_FLAG, MO_GOT_ABSOLUTE_ADDRESS, MO_PIC_BASE_OFFSET, MO_GOT,
  MO_GOTOFF, MO_GOTPCREL, MO_PLT, MO_TLSGD,
  MO_TLSLD, MO_TLSLDM, MO_GOTTPOFF, MO_INDNTPOFF,
  MO_TPOFF, MO_DTPOFF, MO_NTPOFF, MO_GOTNTPOFF,
  MO_DLLIMPORT, MO_DARWIN_NONLAZY, MO_DARWIN_NONLAZY_PIC_BASE, MO_TLVP,
  MO_TLVP_PIC_BASE, MO_SECREL, MO_ABS8
}
 Target Operand Flag enum. More...
 
enum  : uint64_t {
  Pseudo = 0, RawFrm = 1, AddRegFrm = 2, RawFrmMemOffs = 3,
  RawFrmSrc = 4, RawFrmDst = 5, RawFrmDstSrc = 6, RawFrmImm8 = 7,
  RawFrmImm16 = 8, MRMDestMem = 32, MRMSrcMem = 33, MRMSrcMem4VOp3 = 34,
  MRMSrcMemOp4 = 35, MRMXm = 39, MRM0m = 40, MRM1m = 41,
  MRM2m = 42, MRM3m = 43, MRM4m = 44, MRM5m = 45,
  MRM6m = 46, MRM7m = 47, MRMDestReg = 48, MRMSrcReg = 49,
  MRMSrcReg4VOp3 = 50, MRMSrcRegOp4 = 51, MRMXr = 55, MRM0r = 56,
  MRM1r = 57, MRM2r = 58, MRM3r = 59, MRM4r = 60,
  MRM5r = 61, MRM6r = 62, MRM7r = 63, MRM_C0 = 64,
  MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, MRM_C4 = 68,
  MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, MRM_C8 = 72,
  MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, MRM_CC = 76,
  MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, MRM_D0 = 80,
  MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, MRM_D4 = 84,
  MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, MRM_D8 = 88,
  MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, MRM_DC = 92,
  MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, MRM_E0 = 96,
  MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, MRM_E4 = 100,
  MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, MRM_E8 = 104,
  MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, MRM_EC = 108,
  MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, MRM_F0 = 112,
  MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, MRM_F4 = 116,
  MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, MRM_F8 = 120,
  MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, MRM_FC = 124,
  MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, FormMask = 127,
  OpSizeShift = 7, OpSizeMask = 0x3 << OpSizeShift, OpSizeFixed = 0 << OpSizeShift, OpSize16 = 1 << OpSizeShift,
  OpSize32 = 2 << OpSizeShift, AdSizeShift = OpSizeShift + 2, AdSizeMask = 0x3 << AdSizeShift, AdSizeX = 1 << AdSizeShift,
  AdSize16 = 1 << AdSizeShift, AdSize32 = 2 << AdSizeShift, AdSize64 = 3 << AdSizeShift, OpPrefixShift = AdSizeShift + 2,
  OpPrefixMask = 0x7 << OpPrefixShift, PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift, XS = 3 << OpPrefixShift,
  XD = 4 << OpPrefixShift, OpMapShift = OpPrefixShift + 3, OpMapMask = 0x7 << OpMapShift, OB = 0 << OpMapShift,
  TB = 1 << OpMapShift, T8 = 2 << OpMapShift, TA = 3 << OpMapShift, XOP8 = 4 << OpMapShift,
  XOP9 = 5 << OpMapShift, XOPA = 6 << OpMapShift, REXShift = OpMapShift + 3, REX_W = 1 << REXShift,
  ImmShift = REXShift + 1, ImmMask = 15 << ImmShift, Imm8 = 1 << ImmShift, Imm8PCRel = 2 << ImmShift,
  Imm8Reg = 3 << ImmShift, Imm16 = 4 << ImmShift, Imm16PCRel = 5 << ImmShift, Imm32 = 6 << ImmShift,
  Imm32PCRel = 7 << ImmShift, Imm32S = 8 << ImmShift, Imm64 = 9 << ImmShift, FPTypeShift = ImmShift + 4,
  FPTypeMask = 7 << FPTypeShift, NotFP = 0 << FPTypeShift, ZeroArgFP = 1 << FPTypeShift, OneArgFP = 2 << FPTypeShift,
  OneArgFPRW = 3 << FPTypeShift, TwoArgFP = 4 << FPTypeShift, CompareFP = 5 << FPTypeShift, CondMovFP = 6 << FPTypeShift,
  SpecialFP = 7 << FPTypeShift, LOCKShift = FPTypeShift + 3, LOCK = 1 << LOCKShift, REPShift = LOCKShift + 1,
  REP = 1 << REPShift, SSEDomainShift = REPShift + 1, EncodingShift = SSEDomainShift + 2, EncodingMask = 0x3 << EncodingShift,
  VEX = 1 << EncodingShift, XOP = 2 << EncodingShift, EVEX = 3 << EncodingShift, OpcodeShift = EncodingShift + 2,
  VEX_WShift = OpcodeShift + 8, VEX_W = 1ULL << VEX_WShift, VEX_4VShift = VEX_WShift + 1, VEX_4V = 1ULL << VEX_4VShift,
  VEX_LShift = VEX_4VShift + 1, VEX_L = 1ULL << VEX_LShift, EVEX_KShift = VEX_LShift + 1, EVEX_K = 1ULL << EVEX_KShift,
  EVEX_ZShift = EVEX_KShift + 1, EVEX_Z = 1ULL << EVEX_ZShift, EVEX_L2Shift = EVEX_ZShift + 1, EVEX_L2 = 1ULL << EVEX_L2Shift,
  EVEX_BShift = EVEX_L2Shift + 1, EVEX_B = 1ULL << EVEX_BShift, CD8_Scale_Shift = EVEX_BShift + 1, CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
  Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7, Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift, EVEX_RCShift = Has3DNow0F0FOpcodeShift + 1, EVEX_RC = 1ULL << EVEX_RCShift
}
 

Functions

unsigned char getBaseOpcodeFor (uint64_t TSFlags)
 
bool hasImm (uint64_t TSFlags)
 
unsigned getSizeOfImm (uint64_t TSFlags)
 getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instruction. More...
 
unsigned isImmPCRel (uint64_t TSFlags)
 isImmPCRel - Return true if the immediate of the specified instruction's TSFlags indicates that it is pc relative. More...
 
unsigned isImmSigned (uint64_t TSFlags)
 isImmSigned - Return true if the immediate of the specified instruction's TSFlags indicates that it is signed. More...
 
unsigned getOperandBias (const MCInstrDesc &Desc)
 getOperandBias - compute any additional adjustment needed to the offset to the start of the memory operand in this instruction. More...
 
int getMemoryOperandNo (uint64_t TSFlags)
 getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory operand. More...
 
bool isX86_64ExtendedReg (unsigned RegNo)
 isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g. More...
 
static bool is32ExtendedReg (unsigned RegNo)
 is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e.g. More...
 
bool isX86_64NonExtLowByteReg (unsigned reg)
 
bool isKMasked (uint64_t TSFlags)
 isKMasked - Is this a masked instruction. More...
 
bool isKMergeMasked (uint64_t TSFlags)
 isKMergedMasked - Is this a merge masked instruction. More...
 

Detailed Description

X86II - This namespace holds all of the target specific flags that instruction info tracks.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum : uint64_t
Enumerator
Pseudo 
RawFrm 

Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode value, like 'leave'.

AddRegFrm 

AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand added to their opcode.

RawFrmMemOffs 

RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate with a possible segment override.

RawFrmSrc 

RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possible segment override.

RawFrmDst 

RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI.

RawFrmDstSrc 

RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possible segment override, and also the destination index register DI/ESI/RDI.

RawFrmImm8 

RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is a 16-bit immediate (specified by the imm encoding) and the second is a 8-bit fixed value.

RawFrmImm16 

RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which is a 16 or 32-bit immediate (specified by the imm encoding) and the second is a 16-bit fixed value.

In the AMD manual, this operand is described as pntr16:32 and pntr16:16

MRMDestMem 

MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.

In the intel manual these are represented as /0, /1, ...MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination, which in this case is memory.

MRMSrcMem 

MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source, which in this case is memory.

MRMSrcMem4VOp3 

MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.

MRMSrcMemOp4 

MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth source, which in this case is memory.

MRMXm 

MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source, but doesn't use the middle field.

MRM0m 
MRM1m 
MRM2m 
MRM3m 
MRM4m 
MRM5m 
MRM6m 
MRM7m 
MRMDestReg 

MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination, which in this case is a register.

MRMSrcReg 

MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source, which in this case is a register.

MRMSrcReg4VOp3 

MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.

MRMSrcRegOp4 

MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth source, which in this case is a register.

MRMXr 

MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source, but doesn't use the middle field.

MRM0r 
MRM1r 
MRM2r 
MRM3r 
MRM4r 
MRM5r 
MRM6r 
MRM7r 
MRM_C0 

MRM_XX - A mod/rm byte of exactly 0xXX.

MRM_C1 
MRM_C2 
MRM_C3 
MRM_C4 
MRM_C5 
MRM_C6 
MRM_C7 
MRM_C8 
MRM_C9 
MRM_CA 
MRM_CB 
MRM_CC 
MRM_CD 
MRM_CE 
MRM_CF 
MRM_D0 
MRM_D1 
MRM_D2 
MRM_D3 
MRM_D4 
MRM_D5 
MRM_D6 
MRM_D7 
MRM_D8 
MRM_D9 
MRM_DA 
MRM_DB 
MRM_DC 
MRM_DD 
MRM_DE 
MRM_DF 
MRM_E0 
MRM_E1 
MRM_E2 
MRM_E3 
MRM_E4 
MRM_E5 
MRM_E6 
MRM_E7 
MRM_E8 
MRM_E9 
MRM_EA 
MRM_EB 
MRM_EC 
MRM_ED 
MRM_EE 
MRM_EF 
MRM_F0 
MRM_F1 
MRM_F2 
MRM_F3 
MRM_F4 
MRM_F5 
MRM_F6 
MRM_F7 
MRM_F8 
MRM_F9 
MRM_FA 
MRM_FB 
MRM_FC 
MRM_FD 
MRM_FE 
MRM_FF 
FormMask 
OpSizeShift 
OpSizeMask 
OpSizeFixed 
OpSize16 
OpSize32 
AdSizeShift 
AdSizeMask 
AdSizeX 
AdSize16 
AdSize32 
AdSize64 
OpPrefixShift 
OpPrefixMask 
PS 
PD 
XS 
XD 
OpMapShift 
OpMapMask 
OB 
TB 
T8 
TA 
XOP8 
XOP9 
XOPA 
REXShift 
REX_W 
ImmShift 
ImmMask 
Imm8 
Imm8PCRel 
Imm8Reg 
Imm16 
Imm16PCRel 
Imm32 
Imm32PCRel 
Imm32S 
Imm64 
FPTypeShift 
FPTypeMask 
NotFP 
ZeroArgFP 
OneArgFP 
OneArgFPRW 
TwoArgFP 
CompareFP 
CondMovFP 
SpecialFP 
LOCKShift 
LOCK 
REPShift 
REP 
SSEDomainShift 
EncodingShift 
EncodingMask 
VEX 
XOP 

XOP - Opcode prefix used by XOP instructions.

EVEX 
OpcodeShift 
VEX_WShift 

VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE instructions.

VEX_W 
VEX_4VShift 

VEX_4V - Used to specify an additional AVX/SSE register.

Several 2 address instructions in SSE are represented as 3 address ones in AVX and the additional register is encoded in VEX_VVVV prefix.

VEX_4V 
VEX_LShift 

VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide registers.

This is usually auto detected if a VR256 register is used, but some AVX instructions also have this field marked when using a f256 memory references.

VEX_L 
EVEX_KShift 
EVEX_K 
EVEX_ZShift 
EVEX_Z 
EVEX_L2Shift 
EVEX_L2 
EVEX_BShift 
EVEX_B 
CD8_Scale_Shift 
CD8_Scale_Mask 
Has3DNow0F0FOpcodeShift 

Has3DNow0F0FOpcode - This flag indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructions.

The manual documents this as having a 0x0F prefix with a 0x0F opcode, and each instruction storing a classifier in the imm8 field. To simplify our implementation, we handle this by storeing the classifier in the opcode field and using this flag to indicate that the encoder should do the wacky 3DNow! thing.

Has3DNow0F0FOpcode 
EVEX_RCShift 

Explicitly specified rounding control.

EVEX_RC 

Definition at line 233 of file X86BaseInfo.h.

◆ TOF

Target Operand Flag enum.

Enumerator
MO_NO_FLAG 
MO_GOT_ABSOLUTE_ADDRESS 

MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.

  • PICBASELABEL]
MO_PIC_BASE_OFFSET 

MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of the symbol minus the PIC base label: SYMBOL_LABEL - PICBASELABEL.

MO_GOT 

MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the symbol name from the base of the GOT.

See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL

MO_GOTOFF 

MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of the symbol name from the base of the GOT.

See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL

MO_GOTPCREL 

MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name from the current code location.

See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL

MO_PLT 

MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol name from the current code location.

See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL

MO_TLSGD 

MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS index structure that contains the module number and variable offset for the symbol.

Used in the general dynamic TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_TLSLD 

MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS index for the module that contains the symbol.

When this index is passed to a call to __tls_get_addr, the function will return the base address of the TLS block for the symbol. Used in the x86-64 local dynamic TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_TLSLDM 

MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS index for the module that contains the symbol.

When this index is passed to a call to ___tls_get_addr, the function will return the base address of the TLS block for the symbol. Used in the IA32 local dynamic TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_GOTTPOFF 

MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the thread-pointer offset for the symbol.

Used in the x86-64 initial exec TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_INDNTPOFF 

MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the GOT entry with the negative thread-pointer offset for the symbol.

Used in the non-PIC IA32 initial exec TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_TPOFF 

MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the symbol.

Used in the x86-64 local exec TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_DTPOFF 

MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS offset of the symbol.

Used in the local dynamic TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_NTPOFF 

MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offset for the symbol.

Used in the IA32 local exec TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_GOTNTPOFF 

MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the negative thread-pointer offset for the symbol.

Used in the PIC IA32 initial exec TLS access model.

See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL

MO_DLLIMPORT 

MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp_FOO" symbol.

This is used for dllimport linkage on windows.

MO_DARWIN_NONLAZY 

MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "FOO$non_lazy_ptr" symbol, which is a non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.

MO_DARWIN_NONLAZY_PIC_BASE 

MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.

MO_TLVP 

MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.

This is the TLS offset for the Darwin TLS mechanism.

MO_TLVP_PIC_BASE 

MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the picbase.

This is the 32-bit TLS offset for Darwin TLS in PIC mode.

MO_SECREL 

MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of section.

This is the TLS offset for the COFF/Windows TLS mechanism.

MO_ABS8 

MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in range [0,128), so we can use the symbol modifier.

Definition at line 71 of file X86BaseInfo.h.

Function Documentation

◆ getBaseOpcodeFor()

unsigned char llvm::X86II::getBaseOpcodeFor ( uint64_t  TSFlags)
inline

Definition at line 577 of file X86BaseInfo.h.

References OpcodeShift.

Referenced by HasSecRelSymbolRef().

◆ getMemoryOperandNo()

int llvm::X86II::getMemoryOperandNo ( uint64_t  TSFlags)
inline

getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory operand.

If the instruction doesn't have a memory operand, this returns -1.

Note that this ignores tied operands. If there is a tied register which is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only counted as one operand.

Definition at line 674 of file X86BaseInfo.h.

References AddRegFrm, EVEX_K, FormMask, llvm_unreachable, MRM0m, MRM0r, MRM1m, MRM1r, MRM2m, MRM2r, MRM3m, MRM3r, MRM4m, MRM4r, MRM5m, MRM5r, MRM6m, MRM6r, MRM7m, MRM7r, MRM_C0, MRM_C1, MRM_C2, MRM_C3, MRM_C4, MRM_C5, MRM_C6, MRM_C7, MRM_C8, MRM_C9, MRM_CA, MRM_CB, MRM_CC, MRM_CD, MRM_CE, MRM_CF, MRM_D0, MRM_D1, MRM_D2, MRM_D3, MRM_D4, MRM_D5, MRM_D6, MRM_D7, MRM_D8, MRM_D9, MRM_DA, MRM_DB, MRM_DC, MRM_DD, MRM_DE, MRM_DF, MRM_E0, MRM_E1, MRM_E2, MRM_E3, MRM_E4, MRM_E5, MRM_E6, MRM_E7, MRM_E8, MRM_E9, MRM_EA, MRM_EB, MRM_EC, MRM_ED, MRM_EE, MRM_EF, MRM_F0, MRM_F1, MRM_F2, MRM_F3, MRM_F4, MRM_F5, MRM_F6, MRM_F7, MRM_F8, MRM_F9, MRM_FA, MRM_FB, MRM_FC, MRM_FD, MRM_FE, MRM_FF, MRMDestMem, MRMDestReg, MRMSrcMem, MRMSrcMem4VOp3, MRMSrcMemOp4, MRMSrcReg, MRMSrcReg4VOp3, MRMSrcRegOp4, MRMXm, MRMXr, Pseudo, RawFrm, RawFrmDst, RawFrmDstSrc, RawFrmImm16, RawFrmImm8, RawFrmMemOffs, RawFrmSrc, and VEX_4V.

Referenced by llvm::createX86OptimizeLEAs(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), HasSecRelSymbolRef(), isLEASimpleIncOrDec(), and usedAsAddr().

◆ getOperandBias()

unsigned llvm::X86II::getOperandBias ( const MCInstrDesc Desc)
inline

getOperandBias - compute any additional adjustment needed to the offset to the start of the memory operand in this instruction.

If this is a two-address instruction,skip one of the register operands. FIXME: This should be handled during MCInst lowering.

Definition at line 645 of file X86BaseInfo.h.

References llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::getOperandConstraint(), and llvm::MCOI::TIED_TO.

Referenced by llvm::createX86OptimizeLEAs(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), HasSecRelSymbolRef(), isLEASimpleIncOrDec(), and usedAsAddr().

◆ getSizeOfImm()

unsigned llvm::X86II::getSizeOfImm ( uint64_t  TSFlags)
inline

getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instruction.

Definition at line 587 of file X86BaseInfo.h.

References Imm16, Imm16PCRel, Imm32, Imm32PCRel, Imm32S, Imm64, Imm8, Imm8PCRel, Imm8Reg, ImmMask, and llvm_unreachable.

Referenced by getImmFixupKind(), and HasSecRelSymbolRef().

◆ hasImm()

bool llvm::X86II::hasImm ( uint64_t  TSFlags)
inline

Definition at line 581 of file X86BaseInfo.h.

References ImmMask.

Referenced by HasSecRelSymbolRef().

◆ is32ExtendedReg()

static bool llvm::X86II::is32ExtendedReg ( unsigned  RegNo)
inlinestatic

is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e.g.

zmm21, etc.

Definition at line 774 of file X86BaseInfo.h.

Referenced by CheckBaseRegAndIndexRegAndScale().

◆ isImmPCRel()

unsigned llvm::X86II::isImmPCRel ( uint64_t  TSFlags)
inline

isImmPCRel - Return true if the immediate of the specified instruction's TSFlags indicates that it is pc relative.

Definition at line 604 of file X86BaseInfo.h.

References Imm16, Imm16PCRel, Imm32, Imm32PCRel, Imm32S, Imm64, Imm8, Imm8PCRel, Imm8Reg, ImmMask, and llvm_unreachable.

Referenced by getImmFixupKind().

◆ isImmSigned()

unsigned llvm::X86II::isImmSigned ( uint64_t  TSFlags)
inline

isImmSigned - Return true if the immediate of the specified instruction's TSFlags indicates that it is signed.

Definition at line 623 of file X86BaseInfo.h.

References Imm16, Imm16PCRel, Imm32, Imm32PCRel, Imm32S, Imm64, Imm8, Imm8PCRel, Imm8Reg, ImmMask, and llvm_unreachable.

Referenced by getImmFixupKind().

◆ isKMasked()

bool llvm::X86II::isKMasked ( uint64_t  TSFlags)
inline

isKMasked - Is this a masked instruction.

Definition at line 787 of file X86BaseInfo.h.

References EVEX_K.

Referenced by llvm::X86InstrInfo::findFMA3CommutedOpIndices(), getThreeSrcCommuteCase(), and isKMergeMasked().

◆ isKMergeMasked()

bool llvm::X86II::isKMergeMasked ( uint64_t  TSFlags)
inline

isKMergedMasked - Is this a merge masked instruction.

Definition at line 792 of file X86BaseInfo.h.

References EVEX_Z, and isKMasked().

Referenced by llvm::X86InstrInfo::findFMA3CommutedOpIndices(), and getThreeSrcCommuteCase().

◆ isX86_64ExtendedReg()

bool llvm::X86II::isX86_64ExtendedReg ( unsigned  RegNo)
inline

isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.

r8, xmm8, xmm13, etc.

Definition at line 747 of file X86BaseInfo.h.

Referenced by CheckBaseRegAndIndexRegAndScale(), EmitNops(), and getRetOpcode().

◆ isX86_64NonExtLowByteReg()

bool llvm::X86II::isX86_64NonExtLowByteReg ( unsigned  reg)
inline

Definition at line 781 of file X86BaseInfo.h.

Referenced by CheckBaseRegAndIndexRegAndScale(), and HasSecRelSymbolRef().