LLVM  8.0.0svn
X86InstrInfo.cpp
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1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86InstrFoldTables.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Sequence.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/LLVMContext.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
39 #include "llvm/Support/Debug.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "x86-instr-info"
47 
48 #define GET_INSTRINFO_CTOR_DTOR
49 #include "X86GenInstrInfo.inc"
50 
51 static cl::opt<bool>
52  NoFusing("disable-spill-fusing",
53  cl::desc("Disable fusing of spill code into instructions"),
54  cl::Hidden);
55 static cl::opt<bool>
56 PrintFailedFusing("print-failed-fuse-candidates",
57  cl::desc("Print instructions that the allocator wants to"
58  " fuse, but the X86 backend currently can't"),
59  cl::Hidden);
60 static cl::opt<bool>
61 ReMatPICStubLoad("remat-pic-stub-load",
62  cl::desc("Re-materialize load from stub in PIC mode"),
63  cl::init(false), cl::Hidden);
64 static cl::opt<unsigned>
65 PartialRegUpdateClearance("partial-reg-update-clearance",
66  cl::desc("Clearance between two register writes "
67  "for inserting XOR to avoid partial "
68  "register update"),
69  cl::init(64), cl::Hidden);
70 static cl::opt<unsigned>
71 UndefRegClearance("undef-reg-clearance",
72  cl::desc("How many idle instructions we would like before "
73  "certain undef register reads"),
74  cl::init(128), cl::Hidden);
75 
76 
77 // Pin the vtable to this file.
78 void X86InstrInfo::anchor() {}
79 
81  : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
82  : X86::ADJCALLSTACKDOWN32),
83  (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
84  : X86::ADJCALLSTACKUP32),
85  X86::CATCHRET,
86  (STI.is64Bit() ? X86::RETQ : X86::RETL)),
87  Subtarget(STI), RI(STI.getTargetTriple()) {
88 }
89 
90 bool
92  unsigned &SrcReg, unsigned &DstReg,
93  unsigned &SubIdx) const {
94  switch (MI.getOpcode()) {
95  default: break;
96  case X86::MOVSX16rr8:
97  case X86::MOVZX16rr8:
98  case X86::MOVSX32rr8:
99  case X86::MOVZX32rr8:
100  case X86::MOVSX64rr8:
101  if (!Subtarget.is64Bit())
102  // It's not always legal to reference the low 8-bit of the larger
103  // register in 32-bit mode.
104  return false;
106  case X86::MOVSX32rr16:
107  case X86::MOVZX32rr16:
108  case X86::MOVSX64rr16:
109  case X86::MOVSX64rr32: {
110  if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
111  // Be conservative.
112  return false;
113  SrcReg = MI.getOperand(1).getReg();
114  DstReg = MI.getOperand(0).getReg();
115  switch (MI.getOpcode()) {
116  default: llvm_unreachable("Unreachable!");
117  case X86::MOVSX16rr8:
118  case X86::MOVZX16rr8:
119  case X86::MOVSX32rr8:
120  case X86::MOVZX32rr8:
121  case X86::MOVSX64rr8:
122  SubIdx = X86::sub_8bit;
123  break;
124  case X86::MOVSX32rr16:
125  case X86::MOVZX32rr16:
126  case X86::MOVSX64rr16:
127  SubIdx = X86::sub_16bit;
128  break;
129  case X86::MOVSX64rr32:
130  SubIdx = X86::sub_32bit;
131  break;
132  }
133  return true;
134  }
135  }
136  return false;
137 }
138 
140  const MachineFunction *MF = MI.getParent()->getParent();
142 
143  if (isFrameInstr(MI)) {
144  unsigned StackAlign = TFI->getStackAlignment();
145  int SPAdj = alignTo(getFrameSize(MI), StackAlign);
146  SPAdj -= getFrameAdjustment(MI);
147  if (!isFrameSetup(MI))
148  SPAdj = -SPAdj;
149  return SPAdj;
150  }
151 
152  // To know whether a call adjusts the stack, we need information
153  // that is bound to the following ADJCALLSTACKUP pseudo.
154  // Look for the next ADJCALLSTACKUP that follows the call.
155  if (MI.isCall()) {
156  const MachineBasicBlock *MBB = MI.getParent();
158  for (auto E = MBB->end(); I != E; ++I) {
159  if (I->getOpcode() == getCallFrameDestroyOpcode() ||
160  I->isCall())
161  break;
162  }
163 
164  // If we could not find a frame destroy opcode, then it has already
165  // been simplified, so we don't care.
166  if (I->getOpcode() != getCallFrameDestroyOpcode())
167  return 0;
168 
169  return -(I->getOperand(1).getImm());
170  }
171 
172  // Currently handle only PUSHes we can reasonably expect to see
173  // in call sequences
174  switch (MI.getOpcode()) {
175  default:
176  return 0;
177  case X86::PUSH32i8:
178  case X86::PUSH32r:
179  case X86::PUSH32rmm:
180  case X86::PUSH32rmr:
181  case X86::PUSHi32:
182  return 4;
183  case X86::PUSH64i8:
184  case X86::PUSH64r:
185  case X86::PUSH64rmm:
186  case X86::PUSH64rmr:
187  case X86::PUSH64i32:
188  return 8;
189  }
190 }
191 
192 /// Return true and the FrameIndex if the specified
193 /// operand and follow operands form a reference to the stack frame.
194 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
195  int &FrameIndex) const {
196  if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
197  MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
198  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
199  MI.getOperand(Op + X86::AddrDisp).isImm() &&
200  MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
201  MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
202  MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
203  FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
204  return true;
205  }
206  return false;
207 }
208 
209 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
210  switch (Opcode) {
211  default:
212  return false;
213  case X86::MOV8rm:
214  case X86::KMOVBkm:
215  MemBytes = 1;
216  return true;
217  case X86::MOV16rm:
218  case X86::KMOVWkm:
219  MemBytes = 2;
220  return true;
221  case X86::MOV32rm:
222  case X86::MOVSSrm:
223  case X86::VMOVSSZrm:
224  case X86::VMOVSSrm:
225  case X86::KMOVDkm:
226  MemBytes = 4;
227  return true;
228  case X86::MOV64rm:
229  case X86::LD_Fp64m:
230  case X86::MOVSDrm:
231  case X86::VMOVSDrm:
232  case X86::VMOVSDZrm:
233  case X86::MMX_MOVD64rm:
234  case X86::MMX_MOVQ64rm:
235  case X86::KMOVQkm:
236  MemBytes = 8;
237  return true;
238  case X86::MOVAPSrm:
239  case X86::MOVUPSrm:
240  case X86::MOVAPDrm:
241  case X86::MOVUPDrm:
242  case X86::MOVDQArm:
243  case X86::MOVDQUrm:
244  case X86::VMOVAPSrm:
245  case X86::VMOVUPSrm:
246  case X86::VMOVAPDrm:
247  case X86::VMOVUPDrm:
248  case X86::VMOVDQArm:
249  case X86::VMOVDQUrm:
250  case X86::VMOVAPSZ128rm:
251  case X86::VMOVUPSZ128rm:
252  case X86::VMOVAPSZ128rm_NOVLX:
253  case X86::VMOVUPSZ128rm_NOVLX:
254  case X86::VMOVAPDZ128rm:
255  case X86::VMOVUPDZ128rm:
256  case X86::VMOVDQU8Z128rm:
257  case X86::VMOVDQU16Z128rm:
258  case X86::VMOVDQA32Z128rm:
259  case X86::VMOVDQU32Z128rm:
260  case X86::VMOVDQA64Z128rm:
261  case X86::VMOVDQU64Z128rm:
262  MemBytes = 16;
263  return true;
264  case X86::VMOVAPSYrm:
265  case X86::VMOVUPSYrm:
266  case X86::VMOVAPDYrm:
267  case X86::VMOVUPDYrm:
268  case X86::VMOVDQAYrm:
269  case X86::VMOVDQUYrm:
270  case X86::VMOVAPSZ256rm:
271  case X86::VMOVUPSZ256rm:
272  case X86::VMOVAPSZ256rm_NOVLX:
273  case X86::VMOVUPSZ256rm_NOVLX:
274  case X86::VMOVAPDZ256rm:
275  case X86::VMOVUPDZ256rm:
276  case X86::VMOVDQU8Z256rm:
277  case X86::VMOVDQU16Z256rm:
278  case X86::VMOVDQA32Z256rm:
279  case X86::VMOVDQU32Z256rm:
280  case X86::VMOVDQA64Z256rm:
281  case X86::VMOVDQU64Z256rm:
282  MemBytes = 32;
283  return true;
284  case X86::VMOVAPSZrm:
285  case X86::VMOVUPSZrm:
286  case X86::VMOVAPDZrm:
287  case X86::VMOVUPDZrm:
288  case X86::VMOVDQU8Zrm:
289  case X86::VMOVDQU16Zrm:
290  case X86::VMOVDQA32Zrm:
291  case X86::VMOVDQU32Zrm:
292  case X86::VMOVDQA64Zrm:
293  case X86::VMOVDQU64Zrm:
294  MemBytes = 64;
295  return true;
296  }
297 }
298 
299 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
300  switch (Opcode) {
301  default:
302  return false;
303  case X86::MOV8mr:
304  case X86::KMOVBmk:
305  MemBytes = 1;
306  return true;
307  case X86::MOV16mr:
308  case X86::KMOVWmk:
309  MemBytes = 2;
310  return true;
311  case X86::MOV32mr:
312  case X86::MOVSSmr:
313  case X86::VMOVSSmr:
314  case X86::VMOVSSZmr:
315  case X86::KMOVDmk:
316  MemBytes = 4;
317  return true;
318  case X86::MOV64mr:
319  case X86::ST_FpP64m:
320  case X86::MOVSDmr:
321  case X86::VMOVSDmr:
322  case X86::VMOVSDZmr:
323  case X86::MMX_MOVD64mr:
324  case X86::MMX_MOVQ64mr:
325  case X86::MMX_MOVNTQmr:
326  case X86::KMOVQmk:
327  MemBytes = 8;
328  return true;
329  case X86::MOVAPSmr:
330  case X86::MOVUPSmr:
331  case X86::MOVAPDmr:
332  case X86::MOVUPDmr:
333  case X86::MOVDQAmr:
334  case X86::MOVDQUmr:
335  case X86::VMOVAPSmr:
336  case X86::VMOVUPSmr:
337  case X86::VMOVAPDmr:
338  case X86::VMOVUPDmr:
339  case X86::VMOVDQAmr:
340  case X86::VMOVDQUmr:
341  case X86::VMOVUPSZ128mr:
342  case X86::VMOVAPSZ128mr:
343  case X86::VMOVUPSZ128mr_NOVLX:
344  case X86::VMOVAPSZ128mr_NOVLX:
345  case X86::VMOVUPDZ128mr:
346  case X86::VMOVAPDZ128mr:
347  case X86::VMOVDQA32Z128mr:
348  case X86::VMOVDQU32Z128mr:
349  case X86::VMOVDQA64Z128mr:
350  case X86::VMOVDQU64Z128mr:
351  case X86::VMOVDQU8Z128mr:
352  case X86::VMOVDQU16Z128mr:
353  MemBytes = 16;
354  return true;
355  case X86::VMOVUPSYmr:
356  case X86::VMOVAPSYmr:
357  case X86::VMOVUPDYmr:
358  case X86::VMOVAPDYmr:
359  case X86::VMOVDQUYmr:
360  case X86::VMOVDQAYmr:
361  case X86::VMOVUPSZ256mr:
362  case X86::VMOVAPSZ256mr:
363  case X86::VMOVUPSZ256mr_NOVLX:
364  case X86::VMOVAPSZ256mr_NOVLX:
365  case X86::VMOVUPDZ256mr:
366  case X86::VMOVAPDZ256mr:
367  case X86::VMOVDQU8Z256mr:
368  case X86::VMOVDQU16Z256mr:
369  case X86::VMOVDQA32Z256mr:
370  case X86::VMOVDQU32Z256mr:
371  case X86::VMOVDQA64Z256mr:
372  case X86::VMOVDQU64Z256mr:
373  MemBytes = 32;
374  return true;
375  case X86::VMOVUPSZmr:
376  case X86::VMOVAPSZmr:
377  case X86::VMOVUPDZmr:
378  case X86::VMOVAPDZmr:
379  case X86::VMOVDQU8Zmr:
380  case X86::VMOVDQU16Zmr:
381  case X86::VMOVDQA32Zmr:
382  case X86::VMOVDQU32Zmr:
383  case X86::VMOVDQA64Zmr:
384  case X86::VMOVDQU64Zmr:
385  MemBytes = 64;
386  return true;
387  }
388  return false;
389 }
390 
392  int &FrameIndex) const {
393  unsigned Dummy;
394  return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
395 }
396 
398  int &FrameIndex,
399  unsigned &MemBytes) const {
400  if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
401  if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
402  return MI.getOperand(0).getReg();
403  return 0;
404 }
405 
407  int &FrameIndex) const {
408  unsigned Dummy;
409  if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
410  unsigned Reg;
411  if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
412  return Reg;
413  // Check for post-frame index elimination operations
415  if (hasLoadFromStackSlot(MI, Accesses)) {
416  FrameIndex =
417  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
418  ->getFrameIndex();
419  return 1;
420  }
421  }
422  return 0;
423 }
424 
426  int &FrameIndex) const {
427  unsigned Dummy;
428  return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
429 }
430 
432  int &FrameIndex,
433  unsigned &MemBytes) const {
434  if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
435  if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
436  isFrameOperand(MI, 0, FrameIndex))
438  return 0;
439 }
440 
442  int &FrameIndex) const {
443  unsigned Dummy;
444  if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
445  unsigned Reg;
446  if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
447  return Reg;
448  // Check for post-frame index elimination operations
450  if (hasStoreToStackSlot(MI, Accesses)) {
451  FrameIndex =
452  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
453  ->getFrameIndex();
454  return 1;
455  }
456  }
457  return 0;
458 }
459 
460 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
461 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
462  // Don't waste compile time scanning use-def chains of physregs.
464  return false;
465  bool isPICBase = false;
467  E = MRI.def_instr_end(); I != E; ++I) {
468  MachineInstr *DefMI = &*I;
469  if (DefMI->getOpcode() != X86::MOVPC32r)
470  return false;
471  assert(!isPICBase && "More than one PIC base?");
472  isPICBase = true;
473  }
474  return isPICBase;
475 }
476 
478  AliasAnalysis *AA) const {
479  switch (MI.getOpcode()) {
480  default: break;
481  case X86::MOV8rm:
482  case X86::MOV8rm_NOREX:
483  case X86::MOV16rm:
484  case X86::MOV32rm:
485  case X86::MOV64rm:
486  case X86::LD_Fp64m:
487  case X86::MOVSSrm:
488  case X86::MOVSDrm:
489  case X86::MOVAPSrm:
490  case X86::MOVUPSrm:
491  case X86::MOVAPDrm:
492  case X86::MOVUPDrm:
493  case X86::MOVDQArm:
494  case X86::MOVDQUrm:
495  case X86::VMOVSSrm:
496  case X86::VMOVSDrm:
497  case X86::VMOVAPSrm:
498  case X86::VMOVUPSrm:
499  case X86::VMOVAPDrm:
500  case X86::VMOVUPDrm:
501  case X86::VMOVDQArm:
502  case X86::VMOVDQUrm:
503  case X86::VMOVAPSYrm:
504  case X86::VMOVUPSYrm:
505  case X86::VMOVAPDYrm:
506  case X86::VMOVUPDYrm:
507  case X86::VMOVDQAYrm:
508  case X86::VMOVDQUYrm:
509  case X86::MMX_MOVD64rm:
510  case X86::MMX_MOVQ64rm:
511  // AVX-512
512  case X86::VMOVSSZrm:
513  case X86::VMOVSDZrm:
514  case X86::VMOVAPDZ128rm:
515  case X86::VMOVAPDZ256rm:
516  case X86::VMOVAPDZrm:
517  case X86::VMOVAPSZ128rm:
518  case X86::VMOVAPSZ256rm:
519  case X86::VMOVAPSZ128rm_NOVLX:
520  case X86::VMOVAPSZ256rm_NOVLX:
521  case X86::VMOVAPSZrm:
522  case X86::VMOVDQA32Z128rm:
523  case X86::VMOVDQA32Z256rm:
524  case X86::VMOVDQA32Zrm:
525  case X86::VMOVDQA64Z128rm:
526  case X86::VMOVDQA64Z256rm:
527  case X86::VMOVDQA64Zrm:
528  case X86::VMOVDQU16Z128rm:
529  case X86::VMOVDQU16Z256rm:
530  case X86::VMOVDQU16Zrm:
531  case X86::VMOVDQU32Z128rm:
532  case X86::VMOVDQU32Z256rm:
533  case X86::VMOVDQU32Zrm:
534  case X86::VMOVDQU64Z128rm:
535  case X86::VMOVDQU64Z256rm:
536  case X86::VMOVDQU64Zrm:
537  case X86::VMOVDQU8Z128rm:
538  case X86::VMOVDQU8Z256rm:
539  case X86::VMOVDQU8Zrm:
540  case X86::VMOVUPDZ128rm:
541  case X86::VMOVUPDZ256rm:
542  case X86::VMOVUPDZrm:
543  case X86::VMOVUPSZ128rm:
544  case X86::VMOVUPSZ256rm:
545  case X86::VMOVUPSZ128rm_NOVLX:
546  case X86::VMOVUPSZ256rm_NOVLX:
547  case X86::VMOVUPSZrm: {
548  // Loads from constant pools are trivially rematerializable.
549  if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
550  MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
551  MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
552  MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
554  unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
555  if (BaseReg == 0 || BaseReg == X86::RIP)
556  return true;
557  // Allow re-materialization of PIC load.
559  return false;
560  const MachineFunction &MF = *MI.getParent()->getParent();
561  const MachineRegisterInfo &MRI = MF.getRegInfo();
562  return regIsPICBase(BaseReg, MRI);
563  }
564  return false;
565  }
566 
567  case X86::LEA32r:
568  case X86::LEA64r: {
569  if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
570  MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
571  MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
572  !MI.getOperand(1 + X86::AddrDisp).isReg()) {
573  // lea fi#, lea GV, etc. are all rematerializable.
574  if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
575  return true;
576  unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
577  if (BaseReg == 0)
578  return true;
579  // Allow re-materialization of lea PICBase + x.
580  const MachineFunction &MF = *MI.getParent()->getParent();
581  const MachineRegisterInfo &MRI = MF.getRegInfo();
582  return regIsPICBase(BaseReg, MRI);
583  }
584  return false;
585  }
586  }
587 
588  // All other instructions marked M_REMATERIALIZABLE are always trivially
589  // rematerializable.
590  return true;
591 }
592 
596 
597  // For compile time consideration, if we are not able to determine the
598  // safety after visiting 4 instructions in each direction, we will assume
599  // it's not safe.
601  for (unsigned i = 0; Iter != E && i < 4; ++i) {
602  bool SeenDef = false;
603  for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
604  MachineOperand &MO = Iter->getOperand(j);
605  if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
606  SeenDef = true;
607  if (!MO.isReg())
608  continue;
609  if (MO.getReg() == X86::EFLAGS) {
610  if (MO.isUse())
611  return false;
612  SeenDef = true;
613  }
614  }
615 
616  if (SeenDef)
617  // This instruction defines EFLAGS, no need to look any further.
618  return true;
619  ++Iter;
620  // Skip over debug instructions.
621  while (Iter != E && Iter->isDebugInstr())
622  ++Iter;
623  }
624 
625  // It is safe to clobber EFLAGS at the end of a block of no successor has it
626  // live in.
627  if (Iter == E) {
628  for (MachineBasicBlock *S : MBB.successors())
629  if (S->isLiveIn(X86::EFLAGS))
630  return false;
631  return true;
632  }
633 
635  Iter = I;
636  for (unsigned i = 0; i < 4; ++i) {
637  // If we make it to the beginning of the block, it's safe to clobber
638  // EFLAGS iff EFLAGS is not live-in.
639  if (Iter == B)
640  return !MBB.isLiveIn(X86::EFLAGS);
641 
642  --Iter;
643  // Skip over debug instructions.
644  while (Iter != B && Iter->isDebugInstr())
645  --Iter;
646 
647  bool SawKill = false;
648  for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
649  MachineOperand &MO = Iter->getOperand(j);
650  // A register mask may clobber EFLAGS, but we should still look for a
651  // live EFLAGS def.
652  if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
653  SawKill = true;
654  if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
655  if (MO.isDef()) return MO.isDead();
656  if (MO.isKill()) SawKill = true;
657  }
658  }
659 
660  if (SawKill)
661  // This instruction kills EFLAGS and doesn't redefine it, so
662  // there's no need to look further.
663  return true;
664  }
665 
666  // Conservative answer.
667  return false;
668 }
669 
672  unsigned DestReg, unsigned SubIdx,
673  const MachineInstr &Orig,
674  const TargetRegisterInfo &TRI) const {
675  bool ClobbersEFLAGS = false;
676  for (const MachineOperand &MO : Orig.operands()) {
677  if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
678  ClobbersEFLAGS = true;
679  break;
680  }
681  }
682 
683  if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
684  // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
685  // effects.
686  int Value;
687  switch (Orig.getOpcode()) {
688  case X86::MOV32r0: Value = 0; break;
689  case X86::MOV32r1: Value = 1; break;
690  case X86::MOV32r_1: Value = -1; break;
691  default:
692  llvm_unreachable("Unexpected instruction!");
693  }
694 
695  const DebugLoc &DL = Orig.getDebugLoc();
696  BuildMI(MBB, I, DL, get(X86::MOV32ri))
697  .add(Orig.getOperand(0))
698  .addImm(Value);
699  } else {
700  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
701  MBB.insert(I, MI);
702  }
703 
704  MachineInstr &NewMI = *std::prev(I);
705  NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
706 }
707 
708 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
710  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
711  MachineOperand &MO = MI.getOperand(i);
712  if (MO.isReg() && MO.isDef() &&
713  MO.getReg() == X86::EFLAGS && !MO.isDead()) {
714  return true;
715  }
716  }
717  return false;
718 }
719 
720 /// Check whether the shift count for a machine operand is non-zero.
721 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
722  unsigned ShiftAmtOperandIdx) {
723  // The shift count is six bits with the REX.W prefix and five bits without.
724  unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
725  unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
726  return Imm & ShiftCountMask;
727 }
728 
729 /// Check whether the given shift count is appropriate
730 /// can be represented by a LEA instruction.
731 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
732  // Left shift instructions can be transformed into load-effective-address
733  // instructions if we can encode them appropriately.
734  // A LEA instruction utilizes a SIB byte to encode its scale factor.
735  // The SIB.scale field is two bits wide which means that we can encode any
736  // shift amount less than 4.
737  return ShAmt < 4 && ShAmt > 0;
738 }
739 
741  unsigned Opc, bool AllowSP, unsigned &NewSrc,
742  bool &isKill, MachineOperand &ImplicitOp,
743  LiveVariables *LV) const {
744  MachineFunction &MF = *MI.getParent()->getParent();
745  const TargetRegisterClass *RC;
746  if (AllowSP) {
747  RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
748  } else {
749  RC = Opc != X86::LEA32r ?
750  &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
751  }
752  unsigned SrcReg = Src.getReg();
753 
754  // For both LEA64 and LEA32 the register already has essentially the right
755  // type (32-bit or 64-bit) we may just need to forbid SP.
756  if (Opc != X86::LEA64_32r) {
757  NewSrc = SrcReg;
758  isKill = Src.isKill();
759  assert(!Src.isUndef() && "Undef op doesn't need optimization");
760 
762  !MF.getRegInfo().constrainRegClass(NewSrc, RC))
763  return false;
764 
765  return true;
766  }
767 
768  // This is for an LEA64_32r and incoming registers are 32-bit. One way or
769  // another we need to add 64-bit registers to the final MI.
771  ImplicitOp = Src;
772  ImplicitOp.setImplicit();
773 
774  NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
775  isKill = Src.isKill();
776  assert(!Src.isUndef() && "Undef op doesn't need optimization");
777  } else {
778  // Virtual register of the wrong class, we have to create a temporary 64-bit
779  // vreg to feed into the LEA.
780  NewSrc = MF.getRegInfo().createVirtualRegister(RC);
781  MachineInstr *Copy =
782  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
783  .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
784  .add(Src);
785 
786  // Which is obviously going to be dead after we're done with it.
787  isKill = true;
788 
789  if (LV)
790  LV->replaceKillInstruction(SrcReg, MI, *Copy);
791  }
792 
793  // We've set all the parameters without issue.
794  return true;
795 }
796 
797 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
798  unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
799  LiveVariables *LV) const {
800  // We handle 8-bit adds and various 16-bit opcodes in the switch below.
801  bool Is16BitOp = !(MIOpc == X86::ADD8rr || MIOpc == X86::ADD8ri);
802  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
803  assert((!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
804  *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
805  "Unexpected type for LEA transform");
806 
807  // TODO: For a 32-bit target, we need to adjust the LEA variables with
808  // something like this:
809  // Opcode = X86::LEA32r;
810  // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
811  // OutRegLEA =
812  // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
813  // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
814  if (!Subtarget.is64Bit())
815  return nullptr;
816 
817  unsigned Opcode = X86::LEA64_32r;
818  unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
819  unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
820 
821  // Build and insert into an implicit UNDEF value. This is OK because
822  // we will be shifting and then extracting the lower 8/16-bits.
823  // This has the potential to cause partial register stall. e.g.
824  // movw (%rbp,%rcx,2), %dx
825  // leal -65(%rdx), %esi
826  // But testing has shown this *does* help performance in 64-bit mode (at
827  // least on modern x86 machines).
829  unsigned Dest = MI.getOperand(0).getReg();
830  unsigned Src = MI.getOperand(1).getReg();
831  bool IsDead = MI.getOperand(0).isDead();
832  bool IsKill = MI.getOperand(1).isKill();
833  unsigned SubReg = Is16BitOp ? X86::sub_16bit : X86::sub_8bit;
834  assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
835  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
836  MachineInstr *InsMI =
837  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
838  .addReg(InRegLEA, RegState::Define, SubReg)
839  .addReg(Src, getKillRegState(IsKill));
840 
841  MachineInstrBuilder MIB =
842  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
843  switch (MIOpc) {
844  default: llvm_unreachable("Unreachable!");
845  case X86::SHL16ri: {
846  unsigned ShAmt = MI.getOperand(2).getImm();
847  MIB.addReg(0).addImm(1ULL << ShAmt)
848  .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
849  break;
850  }
851  case X86::INC16r:
852  addRegOffset(MIB, InRegLEA, true, 1);
853  break;
854  case X86::DEC16r:
855  addRegOffset(MIB, InRegLEA, true, -1);
856  break;
857  case X86::ADD8ri:
858  case X86::ADD16ri:
859  case X86::ADD16ri8:
860  case X86::ADD16ri_DB:
861  case X86::ADD16ri8_DB:
862  addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
863  break;
864  case X86::ADD8rr:
865  case X86::ADD16rr:
866  case X86::ADD16rr_DB: {
867  unsigned Src2 = MI.getOperand(2).getReg();
868  bool IsKill2 = MI.getOperand(2).isKill();
869  assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
870  unsigned InRegLEA2 = 0;
871  MachineInstr *InsMI2 = nullptr;
872  if (Src == Src2) {
873  // ADD8rr/ADD16rr killed %reg1028, %reg1028
874  // just a single insert_subreg.
875  addRegReg(MIB, InRegLEA, true, InRegLEA, false);
876  } else {
877  if (Subtarget.is64Bit())
878  InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
879  else
880  InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
881  // Build and insert into an implicit UNDEF value. This is OK because
882  // we will be shifting and then extracting the lower 8/16-bits.
883  BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
884  InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
885  .addReg(InRegLEA2, RegState::Define, SubReg)
886  .addReg(Src2, getKillRegState(IsKill2));
887  addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
888  }
889  if (LV && IsKill2 && InsMI2)
890  LV->replaceKillInstruction(Src2, MI, *InsMI2);
891  break;
892  }
893  }
894 
895  MachineInstr *NewMI = MIB;
896  MachineInstr *ExtMI =
897  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
898  .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
899  .addReg(OutRegLEA, RegState::Kill, SubReg);
900 
901  if (LV) {
902  // Update live variables.
903  LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
904  LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
905  if (IsKill)
906  LV->replaceKillInstruction(Src, MI, *InsMI);
907  if (IsDead)
908  LV->replaceKillInstruction(Dest, MI, *ExtMI);
909  }
910 
911  return ExtMI;
912 }
913 
914 /// This method must be implemented by targets that
915 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
916 /// may be able to convert a two-address instruction into a true
917 /// three-address instruction on demand. This allows the X86 target (for
918 /// example) to convert ADD and SHL instructions into LEA instructions if they
919 /// would require register copies due to two-addressness.
920 ///
921 /// This method returns a null pointer if the transformation cannot be
922 /// performed, otherwise it returns the new instruction.
923 ///
924 MachineInstr *
926  MachineInstr &MI, LiveVariables *LV) const {
927  // The following opcodes also sets the condition code register(s). Only
928  // convert them to equivalent lea if the condition code register def's
929  // are dead!
930  if (hasLiveCondCodeDef(MI))
931  return nullptr;
932 
933  MachineFunction &MF = *MI.getParent()->getParent();
934  // All instructions input are two-addr instructions. Get the known operands.
935  const MachineOperand &Dest = MI.getOperand(0);
936  const MachineOperand &Src = MI.getOperand(1);
937 
938  // Ideally, operations with undef should be folded before we get here, but we
939  // can't guarantee it. Bail out because optimizing undefs is a waste of time.
940  // Without this, we have to forward undef state to new register operands to
941  // avoid machine verifier errors.
942  if (Src.isUndef())
943  return nullptr;
944  if (MI.getNumOperands() > 2)
945  if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
946  return nullptr;
947 
948  MachineInstr *NewMI = nullptr;
949  bool Is64Bit = Subtarget.is64Bit();
950 
951  unsigned MIOpc = MI.getOpcode();
952  switch (MIOpc) {
953  default: return nullptr;
954  case X86::SHL64ri: {
955  assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
956  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
957  if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
958 
959  // LEA can't handle RSP.
961  !MF.getRegInfo().constrainRegClass(Src.getReg(),
962  &X86::GR64_NOSPRegClass))
963  return nullptr;
964 
965  NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
966  .add(Dest)
967  .addReg(0)
968  .addImm(1ULL << ShAmt)
969  .add(Src)
970  .addImm(0)
971  .addReg(0);
972  break;
973  }
974  case X86::SHL32ri: {
975  assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
976  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
977  if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
978 
979  unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
980 
981  // LEA can't handle ESP.
982  bool isKill;
983  unsigned SrcReg;
984  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
985  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
986  SrcReg, isKill, ImplicitOp, LV))
987  return nullptr;
988 
989  MachineInstrBuilder MIB =
990  BuildMI(MF, MI.getDebugLoc(), get(Opc))
991  .add(Dest)
992  .addReg(0)
993  .addImm(1ULL << ShAmt)
994  .addReg(SrcReg, getKillRegState(isKill))
995  .addImm(0)
996  .addReg(0);
997  if (ImplicitOp.getReg() != 0)
998  MIB.add(ImplicitOp);
999  NewMI = MIB;
1000 
1001  break;
1002  }
1003  case X86::SHL16ri: {
1004  assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1005  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1006  if (!isTruncatedShiftCountForLEA(ShAmt))
1007  return nullptr;
1008  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1009  }
1010  case X86::INC64r:
1011  case X86::INC32r: {
1012  assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1013  unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1014  (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1015  bool isKill;
1016  unsigned SrcReg;
1017  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1018  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1019  ImplicitOp, LV))
1020  return nullptr;
1021 
1022  MachineInstrBuilder MIB =
1023  BuildMI(MF, MI.getDebugLoc(), get(Opc))
1024  .add(Dest)
1025  .addReg(SrcReg, getKillRegState(isKill));
1026  if (ImplicitOp.getReg() != 0)
1027  MIB.add(ImplicitOp);
1028 
1029  NewMI = addOffset(MIB, 1);
1030  break;
1031  }
1032  case X86::INC16r:
1033  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1034  case X86::DEC64r:
1035  case X86::DEC32r: {
1036  assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1037  unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1038  : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1039 
1040  bool isKill;
1041  unsigned SrcReg;
1042  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1043  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1044  ImplicitOp, LV))
1045  return nullptr;
1046 
1047  MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1048  .add(Dest)
1049  .addReg(SrcReg, getKillRegState(isKill));
1050  if (ImplicitOp.getReg() != 0)
1051  MIB.add(ImplicitOp);
1052 
1053  NewMI = addOffset(MIB, -1);
1054 
1055  break;
1056  }
1057  case X86::DEC16r:
1058  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1059  case X86::ADD64rr:
1060  case X86::ADD64rr_DB:
1061  case X86::ADD32rr:
1062  case X86::ADD32rr_DB: {
1063  assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1064  unsigned Opc;
1065  if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1066  Opc = X86::LEA64r;
1067  else
1068  Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1069 
1070  bool isKill;
1071  unsigned SrcReg;
1072  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1073  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1074  SrcReg, isKill, ImplicitOp, LV))
1075  return nullptr;
1076 
1077  const MachineOperand &Src2 = MI.getOperand(2);
1078  bool isKill2;
1079  unsigned SrcReg2;
1080  MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1081  if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1082  SrcReg2, isKill2, ImplicitOp2, LV))
1083  return nullptr;
1084 
1085  MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1086  if (ImplicitOp.getReg() != 0)
1087  MIB.add(ImplicitOp);
1088  if (ImplicitOp2.getReg() != 0)
1089  MIB.add(ImplicitOp2);
1090 
1091  NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1092  if (LV && Src2.isKill())
1093  LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1094  break;
1095  }
1096  case X86::ADD8rr:
1097  case X86::ADD16rr:
1098  case X86::ADD16rr_DB:
1099  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1100  case X86::ADD64ri32:
1101  case X86::ADD64ri8:
1102  case X86::ADD64ri32_DB:
1103  case X86::ADD64ri8_DB:
1104  assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1105  NewMI = addOffset(
1106  BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1107  MI.getOperand(2));
1108  break;
1109  case X86::ADD32ri:
1110  case X86::ADD32ri8:
1111  case X86::ADD32ri_DB:
1112  case X86::ADD32ri8_DB: {
1113  assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1114  unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1115 
1116  bool isKill;
1117  unsigned SrcReg;
1118  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1119  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1120  SrcReg, isKill, ImplicitOp, LV))
1121  return nullptr;
1122 
1123  MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1124  .add(Dest)
1125  .addReg(SrcReg, getKillRegState(isKill));
1126  if (ImplicitOp.getReg() != 0)
1127  MIB.add(ImplicitOp);
1128 
1129  NewMI = addOffset(MIB, MI.getOperand(2));
1130  break;
1131  }
1132  case X86::ADD8ri:
1133  case X86::ADD16ri:
1134  case X86::ADD16ri8:
1135  case X86::ADD16ri_DB:
1136  case X86::ADD16ri8_DB:
1137  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1138  case X86::VMOVDQU8Z128rmk:
1139  case X86::VMOVDQU8Z256rmk:
1140  case X86::VMOVDQU8Zrmk:
1141  case X86::VMOVDQU16Z128rmk:
1142  case X86::VMOVDQU16Z256rmk:
1143  case X86::VMOVDQU16Zrmk:
1144  case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1145  case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1146  case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1147  case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1148  case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1149  case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1150  case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1151  case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1152  case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1153  case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1154  case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1155  case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1156  unsigned Opc;
1157  switch (MIOpc) {
1158  default: llvm_unreachable("Unreachable!");
1159  case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1160  case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1161  case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1162  case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1163  case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1164  case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1165  case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1166  case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1167  case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1168  case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1169  case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1170  case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1171  case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1172  case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1173  case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1174  case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1175  case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1176  case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1177  case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1178  case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1179  case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1180  case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1181  case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1182  case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1183  case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1184  case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1185  case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1186  case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1187  case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1188  case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1189  }
1190 
1191  NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1192  .add(Dest)
1193  .add(MI.getOperand(2))
1194  .add(Src)
1195  .add(MI.getOperand(3))
1196  .add(MI.getOperand(4))
1197  .add(MI.getOperand(5))
1198  .add(MI.getOperand(6))
1199  .add(MI.getOperand(7));
1200  break;
1201  }
1202  case X86::VMOVDQU8Z128rrk:
1203  case X86::VMOVDQU8Z256rrk:
1204  case X86::VMOVDQU8Zrrk:
1205  case X86::VMOVDQU16Z128rrk:
1206  case X86::VMOVDQU16Z256rrk:
1207  case X86::VMOVDQU16Zrrk:
1208  case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1209  case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1210  case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1211  case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1212  case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1213  case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1214  case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1215  case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1216  case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1217  case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1218  case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1219  case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1220  unsigned Opc;
1221  switch (MIOpc) {
1222  default: llvm_unreachable("Unreachable!");
1223  case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1224  case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1225  case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1226  case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1227  case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1228  case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1229  case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1230  case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1231  case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1232  case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1233  case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1234  case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1235  case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1236  case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1237  case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1238  case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1239  case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1240  case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1241  case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1242  case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1243  case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1244  case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1245  case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1246  case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1247  case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1248  case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1249  case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1250  case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1251  case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1252  case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1253  }
1254 
1255  NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1256  .add(Dest)
1257  .add(MI.getOperand(2))
1258  .add(Src)
1259  .add(MI.getOperand(3));
1260  break;
1261  }
1262  }
1263 
1264  if (!NewMI) return nullptr;
1265 
1266  if (LV) { // Update live variables
1267  if (Src.isKill())
1268  LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1269  if (Dest.isDead())
1270  LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1271  }
1272 
1273  MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1274  return NewMI;
1275 }
1276 
1277 /// This determines which of three possible cases of a three source commute
1278 /// the source indexes correspond to taking into account any mask operands.
1279 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1280 /// possible.
1281 /// Case 0 - Possible to commute the first and second operands.
1282 /// Case 1 - Possible to commute the first and third operands.
1283 /// Case 2 - Possible to commute the second and third operands.
1284 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1285  unsigned SrcOpIdx2) {
1286  // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1287  if (SrcOpIdx1 > SrcOpIdx2)
1288  std::swap(SrcOpIdx1, SrcOpIdx2);
1289 
1290  unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1291  if (X86II::isKMasked(TSFlags)) {
1292  Op2++;
1293  Op3++;
1294  }
1295 
1296  if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1297  return 0;
1298  if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1299  return 1;
1300  if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1301  return 2;
1302  llvm_unreachable("Unknown three src commute case.");
1303 }
1304 
1306  const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1307  const X86InstrFMA3Group &FMA3Group) const {
1308 
1309  unsigned Opc = MI.getOpcode();
1310 
1311  // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1312  // analysis. The commute optimization is legal only if all users of FMA*_Int
1313  // use only the lowest element of the FMA*_Int instruction. Such analysis are
1314  // not implemented yet. So, just return 0 in that case.
1315  // When such analysis are available this place will be the right place for
1316  // calling it.
1317  assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1318  "Intrinsic instructions can't commute operand 1");
1319 
1320  // Determine which case this commute is or if it can't be done.
1321  unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1322  SrcOpIdx2);
1323  assert(Case < 3 && "Unexpected case number!");
1324 
1325  // Define the FMA forms mapping array that helps to map input FMA form
1326  // to output FMA form to preserve the operation semantics after
1327  // commuting the operands.
1328  const unsigned Form132Index = 0;
1329  const unsigned Form213Index = 1;
1330  const unsigned Form231Index = 2;
1331  static const unsigned FormMapping[][3] = {
1332  // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1333  // FMA132 A, C, b; ==> FMA231 C, A, b;
1334  // FMA213 B, A, c; ==> FMA213 A, B, c;
1335  // FMA231 C, A, b; ==> FMA132 A, C, b;
1336  { Form231Index, Form213Index, Form132Index },
1337  // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1338  // FMA132 A, c, B; ==> FMA132 B, c, A;
1339  // FMA213 B, a, C; ==> FMA231 C, a, B;
1340  // FMA231 C, a, B; ==> FMA213 B, a, C;
1341  { Form132Index, Form231Index, Form213Index },
1342  // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1343  // FMA132 a, C, B; ==> FMA213 a, B, C;
1344  // FMA213 b, A, C; ==> FMA132 b, C, A;
1345  // FMA231 c, A, B; ==> FMA231 c, B, A;
1346  { Form213Index, Form132Index, Form231Index }
1347  };
1348 
1349  unsigned FMAForms[3];
1350  FMAForms[0] = FMA3Group.get132Opcode();
1351  FMAForms[1] = FMA3Group.get213Opcode();
1352  FMAForms[2] = FMA3Group.get231Opcode();
1353  unsigned FormIndex;
1354  for (FormIndex = 0; FormIndex < 3; FormIndex++)
1355  if (Opc == FMAForms[FormIndex])
1356  break;
1357 
1358  // Everything is ready, just adjust the FMA opcode and return it.
1359  FormIndex = FormMapping[Case][FormIndex];
1360  return FMAForms[FormIndex];
1361 }
1362 
1363 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1364  unsigned SrcOpIdx2) {
1365  // Determine which case this commute is or if it can't be done.
1366  unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1367  SrcOpIdx2);
1368  assert(Case < 3 && "Unexpected case value!");
1369 
1370  // For each case we need to swap two pairs of bits in the final immediate.
1371  static const uint8_t SwapMasks[3][4] = {
1372  { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1373  { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1374  { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1375  };
1376 
1377  uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1378  // Clear out the bits we are swapping.
1379  uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1380  SwapMasks[Case][2] | SwapMasks[Case][3]);
1381  // If the immediate had a bit of the pair set, then set the opposite bit.
1382  if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1383  if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1384  if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1385  if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1386  MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1387 }
1388 
1389 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1390 // commuted.
1391 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1392 #define VPERM_CASES(Suffix) \
1393  case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1394  case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1395  case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1396  case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1397  case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1398  case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1399  case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1400  case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1401  case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1402  case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1403  case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1404  case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1405 
1406 #define VPERM_CASES_BROADCAST(Suffix) \
1407  VPERM_CASES(Suffix) \
1408  case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1409  case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1410  case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1411  case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1412  case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1413  case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1414 
1415  switch (Opcode) {
1416  default: return false;
1417  VPERM_CASES(B)
1422  VPERM_CASES(W)
1423  return true;
1424  }
1425 #undef VPERM_CASES_BROADCAST
1426 #undef VPERM_CASES
1427 }
1428 
1429 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1430 // from the I opcode to the T opcode and vice versa.
1431 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1432 #define VPERM_CASES(Orig, New) \
1433  case X86::Orig##128rr: return X86::New##128rr; \
1434  case X86::Orig##128rrkz: return X86::New##128rrkz; \
1435  case X86::Orig##128rm: return X86::New##128rm; \
1436  case X86::Orig##128rmkz: return X86::New##128rmkz; \
1437  case X86::Orig##256rr: return X86::New##256rr; \
1438  case X86::Orig##256rrkz: return X86::New##256rrkz; \
1439  case X86::Orig##256rm: return X86::New##256rm; \
1440  case X86::Orig##256rmkz: return X86::New##256rmkz; \
1441  case X86::Orig##rr: return X86::New##rr; \
1442  case X86::Orig##rrkz: return X86::New##rrkz; \
1443  case X86::Orig##rm: return X86::New##rm; \
1444  case X86::Orig##rmkz: return X86::New##rmkz;
1445 
1446 #define VPERM_CASES_BROADCAST(Orig, New) \
1447  VPERM_CASES(Orig, New) \
1448  case X86::Orig##128rmb: return X86::New##128rmb; \
1449  case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1450  case X86::Orig##256rmb: return X86::New##256rmb; \
1451  case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1452  case X86::Orig##rmb: return X86::New##rmb; \
1453  case X86::Orig##rmbkz: return X86::New##rmbkz;
1454 
1455  switch (Opcode) {
1456  VPERM_CASES(VPERMI2B, VPERMT2B)
1457  VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1458  VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1459  VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1460  VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1461  VPERM_CASES(VPERMI2W, VPERMT2W)
1462  VPERM_CASES(VPERMT2B, VPERMI2B)
1463  VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1464  VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1465  VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1466  VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1467  VPERM_CASES(VPERMT2W, VPERMI2W)
1468  }
1469 
1470  llvm_unreachable("Unreachable!");
1471 #undef VPERM_CASES_BROADCAST
1472 #undef VPERM_CASES
1473 }
1474 
1476  unsigned OpIdx1,
1477  unsigned OpIdx2) const {
1478  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1479  if (NewMI)
1480  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1481  return MI;
1482  };
1483 
1484  switch (MI.getOpcode()) {
1485  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1486  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1487  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1488  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1489  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1490  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1491  unsigned Opc;
1492  unsigned Size;
1493  switch (MI.getOpcode()) {
1494  default: llvm_unreachable("Unreachable!");
1495  case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1496  case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1497  case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1498  case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1499  case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1500  case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1501  }
1502  unsigned Amt = MI.getOperand(3).getImm();
1503  auto &WorkingMI = cloneIfNew(MI);
1504  WorkingMI.setDesc(get(Opc));
1505  WorkingMI.getOperand(3).setImm(Size - Amt);
1506  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1507  OpIdx1, OpIdx2);
1508  }
1509  case X86::PFSUBrr:
1510  case X86::PFSUBRrr: {
1511  // PFSUB x, y: x = x - y
1512  // PFSUBR x, y: x = y - x
1513  unsigned Opc =
1514  (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1515  auto &WorkingMI = cloneIfNew(MI);
1516  WorkingMI.setDesc(get(Opc));
1517  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1518  OpIdx1, OpIdx2);
1519  }
1520  case X86::BLENDPDrri:
1521  case X86::BLENDPSrri:
1522  case X86::VBLENDPDrri:
1523  case X86::VBLENDPSrri:
1524  // If we're optimizing for size, try to use MOVSD/MOVSS.
1525  if (MI.getParent()->getParent()->getFunction().optForSize()) {
1526  unsigned Mask, Opc;
1527  switch (MI.getOpcode()) {
1528  default: llvm_unreachable("Unreachable!");
1529  case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1530  case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1531  case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1532  case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1533  }
1534  if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1535  auto &WorkingMI = cloneIfNew(MI);
1536  WorkingMI.setDesc(get(Opc));
1537  WorkingMI.RemoveOperand(3);
1538  return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1539  /*NewMI=*/false,
1540  OpIdx1, OpIdx2);
1541  }
1542  }
1544  case X86::PBLENDWrri:
1545  case X86::VBLENDPDYrri:
1546  case X86::VBLENDPSYrri:
1547  case X86::VPBLENDDrri:
1548  case X86::VPBLENDWrri:
1549  case X86::VPBLENDDYrri:
1550  case X86::VPBLENDWYrri:{
1551  unsigned Mask;
1552  switch (MI.getOpcode()) {
1553  default: llvm_unreachable("Unreachable!");
1554  case X86::BLENDPDrri: Mask = 0x03; break;
1555  case X86::BLENDPSrri: Mask = 0x0F; break;
1556  case X86::PBLENDWrri: Mask = 0xFF; break;
1557  case X86::VBLENDPDrri: Mask = 0x03; break;
1558  case X86::VBLENDPSrri: Mask = 0x0F; break;
1559  case X86::VBLENDPDYrri: Mask = 0x0F; break;
1560  case X86::VBLENDPSYrri: Mask = 0xFF; break;
1561  case X86::VPBLENDDrri: Mask = 0x0F; break;
1562  case X86::VPBLENDWrri: Mask = 0xFF; break;
1563  case X86::VPBLENDDYrri: Mask = 0xFF; break;
1564  case X86::VPBLENDWYrri: Mask = 0xFF; break;
1565  }
1566  // Only the least significant bits of Imm are used.
1567  unsigned Imm = MI.getOperand(3).getImm() & Mask;
1568  auto &WorkingMI = cloneIfNew(MI);
1569  WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1570  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1571  OpIdx1, OpIdx2);
1572  }
1573  case X86::MOVSDrr:
1574  case X86::MOVSSrr:
1575  case X86::VMOVSDrr:
1576  case X86::VMOVSSrr:{
1577  // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1578  assert(Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!");
1579 
1580  unsigned Mask, Opc;
1581  switch (MI.getOpcode()) {
1582  default: llvm_unreachable("Unreachable!");
1583  case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1584  case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1585  case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1586  case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1587  }
1588 
1589  auto &WorkingMI = cloneIfNew(MI);
1590  WorkingMI.setDesc(get(Opc));
1591  WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1592  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1593  OpIdx1, OpIdx2);
1594  }
1595  case X86::PCLMULQDQrr:
1596  case X86::VPCLMULQDQrr:
1597  case X86::VPCLMULQDQYrr:
1598  case X86::VPCLMULQDQZrr:
1599  case X86::VPCLMULQDQZ128rr:
1600  case X86::VPCLMULQDQZ256rr: {
1601  // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1602  // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1603  unsigned Imm = MI.getOperand(3).getImm();
1604  unsigned Src1Hi = Imm & 0x01;
1605  unsigned Src2Hi = Imm & 0x10;
1606  auto &WorkingMI = cloneIfNew(MI);
1607  WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1608  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1609  OpIdx1, OpIdx2);
1610  }
1611  case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1612  case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1613  case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1614  case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1615  case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1616  case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1617  case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1618  case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1619  case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1620  case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1621  case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1622  case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1623  case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1624  case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1625  case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1626  case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1627  case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1628  case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1629  case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1630  case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1631  case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1632  case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1633  case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1634  case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1635  // Flip comparison mode immediate (if necessary).
1636  unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1637  Imm = X86::getSwappedVPCMPImm(Imm);
1638  auto &WorkingMI = cloneIfNew(MI);
1639  WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1640  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1641  OpIdx1, OpIdx2);
1642  }
1643  case X86::VPCOMBri: case X86::VPCOMUBri:
1644  case X86::VPCOMDri: case X86::VPCOMUDri:
1645  case X86::VPCOMQri: case X86::VPCOMUQri:
1646  case X86::VPCOMWri: case X86::VPCOMUWri: {
1647  // Flip comparison mode immediate (if necessary).
1648  unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1649  Imm = X86::getSwappedVPCOMImm(Imm);
1650  auto &WorkingMI = cloneIfNew(MI);
1651  WorkingMI.getOperand(3).setImm(Imm);
1652  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1653  OpIdx1, OpIdx2);
1654  }
1655  case X86::VPERM2F128rr:
1656  case X86::VPERM2I128rr: {
1657  // Flip permute source immediate.
1658  // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1659  // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1660  unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
1661  auto &WorkingMI = cloneIfNew(MI);
1662  WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1663  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1664  OpIdx1, OpIdx2);
1665  }
1666  case X86::MOVHLPSrr:
1667  case X86::UNPCKHPDrr:
1668  case X86::VMOVHLPSrr:
1669  case X86::VUNPCKHPDrr:
1670  case X86::VMOVHLPSZrr:
1671  case X86::VUNPCKHPDZ128rr: {
1672  assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1673 
1674  unsigned Opc = MI.getOpcode();
1675  switch (Opc) {
1676  default: llvm_unreachable("Unreachable!");
1677  case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1678  case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1679  case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1680  case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1681  case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1682  case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1683  }
1684  auto &WorkingMI = cloneIfNew(MI);
1685  WorkingMI.setDesc(get(Opc));
1686  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1687  OpIdx1, OpIdx2);
1688  }
1689  case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
1690  case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
1691  case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
1692  case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
1693  case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
1694  case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
1695  case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
1696  case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
1697  case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
1698  case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
1699  case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
1700  case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
1701  case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
1702  case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
1703  case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
1704  case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
1705  unsigned Opc;
1706  switch (MI.getOpcode()) {
1707  default: llvm_unreachable("Unreachable!");
1708  case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1709  case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1710  case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1711  case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1712  case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1713  case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1714  case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1715  case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1716  case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1717  case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1718  case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1719  case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1720  case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1721  case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1722  case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1723  case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1724  case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1725  case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1726  case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1727  case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1728  case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1729  case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1730  case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1731  case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1732  case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1733  case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1734  case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1735  case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1736  case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1737  case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1738  case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1739  case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1740  case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1741  case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1742  case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1743  case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1744  case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1745  case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1746  case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1747  case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1748  case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1749  case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1750  case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1751  case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1752  case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1753  case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1754  case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1755  case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1756  }
1757  auto &WorkingMI = cloneIfNew(MI);
1758  WorkingMI.setDesc(get(Opc));
1759  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1760  OpIdx1, OpIdx2);
1761  }
1762  case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1763  case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1764  case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1765  case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1766  case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1767  case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1768  case X86::VPTERNLOGDZrrik:
1769  case X86::VPTERNLOGDZ128rrik:
1770  case X86::VPTERNLOGDZ256rrik:
1771  case X86::VPTERNLOGQZrrik:
1772  case X86::VPTERNLOGQZ128rrik:
1773  case X86::VPTERNLOGQZ256rrik:
1774  case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1775  case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1776  case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1777  case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1778  case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1779  case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1780  case X86::VPTERNLOGDZ128rmbi:
1781  case X86::VPTERNLOGDZ256rmbi:
1782  case X86::VPTERNLOGDZrmbi:
1783  case X86::VPTERNLOGQZ128rmbi:
1784  case X86::VPTERNLOGQZ256rmbi:
1785  case X86::VPTERNLOGQZrmbi:
1786  case X86::VPTERNLOGDZ128rmbikz:
1787  case X86::VPTERNLOGDZ256rmbikz:
1788  case X86::VPTERNLOGDZrmbikz:
1789  case X86::VPTERNLOGQZ128rmbikz:
1790  case X86::VPTERNLOGQZ256rmbikz:
1791  case X86::VPTERNLOGQZrmbikz: {
1792  auto &WorkingMI = cloneIfNew(MI);
1793  commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1794  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1795  OpIdx1, OpIdx2);
1796  }
1797  default: {
1799  unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1800  auto &WorkingMI = cloneIfNew(MI);
1801  WorkingMI.setDesc(get(Opc));
1802  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1803  OpIdx1, OpIdx2);
1804  }
1805 
1806  const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1807  MI.getDesc().TSFlags);
1808  if (FMA3Group) {
1809  unsigned Opc =
1810  getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1811  auto &WorkingMI = cloneIfNew(MI);
1812  WorkingMI.setDesc(get(Opc));
1813  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1814  OpIdx1, OpIdx2);
1815  }
1816 
1817  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1818  }
1819  }
1820 }
1821 
1822 bool
1823 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1824  unsigned &SrcOpIdx1,
1825  unsigned &SrcOpIdx2,
1826  bool IsIntrinsic) const {
1827  uint64_t TSFlags = MI.getDesc().TSFlags;
1828 
1829  unsigned FirstCommutableVecOp = 1;
1830  unsigned LastCommutableVecOp = 3;
1831  unsigned KMaskOp = -1U;
1832  if (X86II::isKMasked(TSFlags)) {
1833  // For k-zero-masked operations it is Ok to commute the first vector
1834  // operand.
1835  // For regular k-masked operations a conservative choice is done as the
1836  // elements of the first vector operand, for which the corresponding bit
1837  // in the k-mask operand is set to 0, are copied to the result of the
1838  // instruction.
1839  // TODO/FIXME: The commute still may be legal if it is known that the
1840  // k-mask operand is set to either all ones or all zeroes.
1841  // It is also Ok to commute the 1st operand if all users of MI use only
1842  // the elements enabled by the k-mask operand. For example,
1843  // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1844  // : v1[i];
1845  // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1846  // // Ok, to commute v1 in FMADD213PSZrk.
1847 
1848  // The k-mask operand has index = 2 for masked and zero-masked operations.
1849  KMaskOp = 2;
1850 
1851  // The operand with index = 1 is used as a source for those elements for
1852  // which the corresponding bit in the k-mask is set to 0.
1853  if (X86II::isKMergeMasked(TSFlags))
1854  FirstCommutableVecOp = 3;
1855 
1856  LastCommutableVecOp++;
1857  } else if (IsIntrinsic) {
1858  // Commuting the first operand of an intrinsic instruction isn't possible
1859  // unless we can prove that only the lowest element of the result is used.
1860  FirstCommutableVecOp = 2;
1861  }
1862 
1863  if (isMem(MI, LastCommutableVecOp))
1864  LastCommutableVecOp--;
1865 
1866  // Only the first RegOpsNum operands are commutable.
1867  // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1868  // that the operand is not specified/fixed.
1869  if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1870  (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1871  SrcOpIdx1 == KMaskOp))
1872  return false;
1873  if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1874  (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1875  SrcOpIdx2 == KMaskOp))
1876  return false;
1877 
1878  // Look for two different register operands assumed to be commutable
1879  // regardless of the FMA opcode. The FMA opcode is adjusted later.
1880  if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1881  SrcOpIdx2 == CommuteAnyOperandIndex) {
1882  unsigned CommutableOpIdx1 = SrcOpIdx1;
1883  unsigned CommutableOpIdx2 = SrcOpIdx2;
1884 
1885  // At least one of operands to be commuted is not specified and
1886  // this method is free to choose appropriate commutable operands.
1887  if (SrcOpIdx1 == SrcOpIdx2)
1888  // Both of operands are not fixed. By default set one of commutable
1889  // operands to the last register operand of the instruction.
1890  CommutableOpIdx2 = LastCommutableVecOp;
1891  else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1892  // Only one of operands is not fixed.
1893  CommutableOpIdx2 = SrcOpIdx1;
1894 
1895  // CommutableOpIdx2 is well defined now. Let's choose another commutable
1896  // operand and assign its index to CommutableOpIdx1.
1897  unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1898  for (CommutableOpIdx1 = LastCommutableVecOp;
1899  CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1900  // Just ignore and skip the k-mask operand.
1901  if (CommutableOpIdx1 == KMaskOp)
1902  continue;
1903 
1904  // The commuted operands must have different registers.
1905  // Otherwise, the commute transformation does not change anything and
1906  // is useless then.
1907  if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1908  break;
1909  }
1910 
1911  // No appropriate commutable operands were found.
1912  if (CommutableOpIdx1 < FirstCommutableVecOp)
1913  return false;
1914 
1915  // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1916  // to return those values.
1917  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1918  CommutableOpIdx1, CommutableOpIdx2))
1919  return false;
1920  }
1921 
1922  return true;
1923 }
1924 
1926  unsigned &SrcOpIdx2) const {
1927  const MCInstrDesc &Desc = MI.getDesc();
1928  if (!Desc.isCommutable())
1929  return false;
1930 
1931  switch (MI.getOpcode()) {
1932  case X86::CMPSDrr:
1933  case X86::CMPSSrr:
1934  case X86::CMPPDrri:
1935  case X86::CMPPSrri:
1936  case X86::VCMPSDrr:
1937  case X86::VCMPSSrr:
1938  case X86::VCMPPDrri:
1939  case X86::VCMPPSrri:
1940  case X86::VCMPPDYrri:
1941  case X86::VCMPPSYrri:
1942  case X86::VCMPSDZrr:
1943  case X86::VCMPSSZrr:
1944  case X86::VCMPPDZrri:
1945  case X86::VCMPPSZrri:
1946  case X86::VCMPPDZ128rri:
1947  case X86::VCMPPSZ128rri:
1948  case X86::VCMPPDZ256rri:
1949  case X86::VCMPPSZ256rri: {
1950  // Float comparison can be safely commuted for
1951  // Ordered/Unordered/Equal/NotEqual tests
1952  unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1953  switch (Imm) {
1954  case 0x00: // EQUAL
1955  case 0x03: // UNORDERED
1956  case 0x04: // NOT EQUAL
1957  case 0x07: // ORDERED
1958  // The indices of the commutable operands are 1 and 2.
1959  // Assign them to the returned operand indices here.
1960  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
1961  }
1962  return false;
1963  }
1964  case X86::MOVSDrr:
1965  case X86::MOVSSrr:
1966  case X86::VMOVSDrr:
1967  case X86::VMOVSSrr:
1968  if (Subtarget.hasSSE41())
1969  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1970  return false;
1971  case X86::MOVHLPSrr:
1972  case X86::UNPCKHPDrr:
1973  case X86::VMOVHLPSrr:
1974  case X86::VUNPCKHPDrr:
1975  case X86::VMOVHLPSZrr:
1976  case X86::VUNPCKHPDZ128rr:
1977  if (Subtarget.hasSSE2())
1978  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1979  return false;
1980  case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1981  case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1982  case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1983  case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1984  case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1985  case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1986  case X86::VPTERNLOGDZrrik:
1987  case X86::VPTERNLOGDZ128rrik:
1988  case X86::VPTERNLOGDZ256rrik:
1989  case X86::VPTERNLOGQZrrik:
1990  case X86::VPTERNLOGQZ128rrik:
1991  case X86::VPTERNLOGQZ256rrik:
1992  case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1993  case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1994  case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1995  case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1996  case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1997  case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1998  case X86::VPTERNLOGDZ128rmbi:
1999  case X86::VPTERNLOGDZ256rmbi:
2000  case X86::VPTERNLOGDZrmbi:
2001  case X86::VPTERNLOGQZ128rmbi:
2002  case X86::VPTERNLOGQZ256rmbi:
2003  case X86::VPTERNLOGQZrmbi:
2004  case X86::VPTERNLOGDZ128rmbikz:
2005  case X86::VPTERNLOGDZ256rmbikz:
2006  case X86::VPTERNLOGDZrmbikz:
2007  case X86::VPTERNLOGQZ128rmbikz:
2008  case X86::VPTERNLOGQZ256rmbikz:
2009  case X86::VPTERNLOGQZrmbikz:
2010  return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2011  case X86::VPMADD52HUQZ128r:
2012  case X86::VPMADD52HUQZ128rk:
2013  case X86::VPMADD52HUQZ128rkz:
2014  case X86::VPMADD52HUQZ256r:
2015  case X86::VPMADD52HUQZ256rk:
2016  case X86::VPMADD52HUQZ256rkz:
2017  case X86::VPMADD52HUQZr:
2018  case X86::VPMADD52HUQZrk:
2019  case X86::VPMADD52HUQZrkz:
2020  case X86::VPMADD52LUQZ128r:
2021  case X86::VPMADD52LUQZ128rk:
2022  case X86::VPMADD52LUQZ128rkz:
2023  case X86::VPMADD52LUQZ256r:
2024  case X86::VPMADD52LUQZ256rk:
2025  case X86::VPMADD52LUQZ256rkz:
2026  case X86::VPMADD52LUQZr:
2027  case X86::VPMADD52LUQZrk:
2028  case X86::VPMADD52LUQZrkz: {
2029  unsigned CommutableOpIdx1 = 2;
2030  unsigned CommutableOpIdx2 = 3;
2031  if (X86II::isKMasked(Desc.TSFlags)) {
2032  // Skip the mask register.
2033  ++CommutableOpIdx1;
2034  ++CommutableOpIdx2;
2035  }
2036  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2037  CommutableOpIdx1, CommutableOpIdx2))
2038  return false;
2039  if (!MI.getOperand(SrcOpIdx1).isReg() ||
2040  !MI.getOperand(SrcOpIdx2).isReg())
2041  // No idea.
2042  return false;
2043  return true;
2044  }
2045 
2046  default:
2047  const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2048  MI.getDesc().TSFlags);
2049  if (FMA3Group)
2050  return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2051  FMA3Group->isIntrinsic());
2052 
2053  // Handled masked instructions since we need to skip over the mask input
2054  // and the preserved input.
2055  if (X86II::isKMasked(Desc.TSFlags)) {
2056  // First assume that the first input is the mask operand and skip past it.
2057  unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2058  unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2059  // Check if the first input is tied. If there isn't one then we only
2060  // need to skip the mask operand which we did above.
2061  if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2062  MCOI::TIED_TO) != -1)) {
2063  // If this is zero masking instruction with a tied operand, we need to
2064  // move the first index back to the first input since this must
2065  // be a 3 input instruction and we want the first two non-mask inputs.
2066  // Otherwise this is a 2 input instruction with a preserved input and
2067  // mask, so we need to move the indices to skip one more input.
2068  if (X86II::isKMergeMasked(Desc.TSFlags)) {
2069  ++CommutableOpIdx1;
2070  ++CommutableOpIdx2;
2071  } else {
2072  --CommutableOpIdx1;
2073  }
2074  }
2075 
2076  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2077  CommutableOpIdx1, CommutableOpIdx2))
2078  return false;
2079 
2080  if (!MI.getOperand(SrcOpIdx1).isReg() ||
2081  !MI.getOperand(SrcOpIdx2).isReg())
2082  // No idea.
2083  return false;
2084  return true;
2085  }
2086 
2087  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2088  }
2089  return false;
2090 }
2091 
2093  switch (BrOpc) {
2094  default: return X86::COND_INVALID;
2095  case X86::JE_1: return X86::COND_E;
2096  case X86::JNE_1: return X86::COND_NE;
2097  case X86::JL_1: return X86::COND_L;
2098  case X86::JLE_1: return X86::COND_LE;
2099  case X86::JG_1: return X86::COND_G;
2100  case X86::JGE_1: return X86::COND_GE;
2101  case X86::JB_1: return X86::COND_B;
2102  case X86::JBE_1: return X86::COND_BE;
2103  case X86::JA_1: return X86::COND_A;
2104  case X86::JAE_1: return X86::COND_AE;
2105  case X86::JS_1: return X86::COND_S;
2106  case X86::JNS_1: return X86::COND_NS;
2107  case X86::JP_1: return X86::COND_P;
2108  case X86::JNP_1: return X86::COND_NP;
2109  case X86::JO_1: return X86::COND_O;
2110  case X86::JNO_1: return X86::COND_NO;
2111  }
2112 }
2113 
2114 /// Return condition code of a SET opcode.
2116  switch (Opc) {
2117  default: return X86::COND_INVALID;
2118  case X86::SETAr: case X86::SETAm: return X86::COND_A;
2119  case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2120  case X86::SETBr: case X86::SETBm: return X86::COND_B;
2121  case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2122  case X86::SETEr: case X86::SETEm: return X86::COND_E;
2123  case X86::SETGr: case X86::SETGm: return X86::COND_G;
2124  case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2125  case X86::SETLr: case X86::SETLm: return X86::COND_L;
2126  case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2127  case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2128  case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2129  case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2130  case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2131  case X86::SETOr: case X86::SETOm: return X86::COND_O;
2132  case X86::SETPr: case X86::SETPm: return X86::COND_P;
2133  case X86::SETSr: case X86::SETSm: return X86::COND_S;
2134  }
2135 }
2136 
2137 /// Return condition code of a CMov opcode.
2139  switch (Opc) {
2140  default: return X86::COND_INVALID;
2141  case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2142  case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2143  return X86::COND_A;
2144  case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2145  case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2146  return X86::COND_AE;
2147  case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2148  case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2149  return X86::COND_B;
2150  case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2151  case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2152  return X86::COND_BE;
2153  case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2154  case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2155  return X86::COND_E;
2156  case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2157  case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2158  return X86::COND_G;
2159  case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2160  case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2161  return X86::COND_GE;
2162  case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2163  case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2164  return X86::COND_L;
2165  case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2166  case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2167  return X86::COND_LE;
2168  case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2169  case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2170  return X86::COND_NE;
2171  case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2172  case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2173  return X86::COND_NO;
2174  case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2175  case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2176  return X86::COND_NP;
2177  case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2178  case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2179  return X86::COND_NS;
2180  case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2181  case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2182  return X86::COND_O;
2183  case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2184  case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2185  return X86::COND_P;
2186  case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2187  case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2188  return X86::COND_S;
2189  }
2190 }
2191 
2193  switch (CC) {
2194  default: llvm_unreachable("Illegal condition code!");
2195  case X86::COND_E: return X86::JE_1;
2196  case X86::COND_NE: return X86::JNE_1;
2197  case X86::COND_L: return X86::JL_1;
2198  case X86::COND_LE: return X86::JLE_1;
2199  case X86::COND_G: return X86::JG_1;
2200  case X86::COND_GE: return X86::JGE_1;
2201  case X86::COND_B: return X86::JB_1;
2202  case X86::COND_BE: return X86::JBE_1;
2203  case X86::COND_A: return X86::JA_1;
2204  case X86::COND_AE: return X86::JAE_1;
2205  case X86::COND_S: return X86::JS_1;
2206  case X86::COND_NS: return X86::JNS_1;
2207  case X86::COND_P: return X86::JP_1;
2208  case X86::COND_NP: return X86::JNP_1;
2209  case X86::COND_O: return X86::JO_1;
2210  case X86::COND_NO: return X86::JNO_1;
2211  }
2212 }
2213 
2214 /// Return the inverse of the specified condition,
2215 /// e.g. turning COND_E to COND_NE.
2217  switch (CC) {
2218  default: llvm_unreachable("Illegal condition code!");
2219  case X86::COND_E: return X86::COND_NE;
2220  case X86::COND_NE: return X86::COND_E;
2221  case X86::COND_L: return X86::COND_GE;
2222  case X86::COND_LE: return X86::COND_G;
2223  case X86::COND_G: return X86::COND_LE;
2224  case X86::COND_GE: return X86::COND_L;
2225  case X86::COND_B: return X86::COND_AE;
2226  case X86::COND_BE: return X86::COND_A;
2227  case X86::COND_A: return X86::COND_BE;
2228  case X86::COND_AE: return X86::COND_B;
2229  case X86::COND_S: return X86::COND_NS;
2230  case X86::COND_NS: return X86::COND_S;
2231  case X86::COND_P: return X86::COND_NP;
2232  case X86::COND_NP: return X86::COND_P;
2233  case X86::COND_O: return X86::COND_NO;
2234  case X86::COND_NO: return X86::COND_O;
2237  }
2238 }
2239 
2240 /// Assuming the flags are set by MI(a,b), return the condition code if we
2241 /// modify the instructions such that flags are set by MI(b,a).
2243  switch (CC) {
2244  default: return X86::COND_INVALID;
2245  case X86::COND_E: return X86::COND_E;
2246  case X86::COND_NE: return X86::COND_NE;
2247  case X86::COND_L: return X86::COND_G;
2248  case X86::COND_LE: return X86::COND_GE;
2249  case X86::COND_G: return X86::COND_L;
2250  case X86::COND_GE: return X86::COND_LE;
2251  case X86::COND_B: return X86::COND_A;
2252  case X86::COND_BE: return X86::COND_AE;
2253  case X86::COND_A: return X86::COND_B;
2254  case X86::COND_AE: return X86::COND_BE;
2255  }
2256 }
2257 
2258 std::pair<X86::CondCode, bool>
2261  bool NeedSwap = false;
2262  switch (Predicate) {
2263  default: break;
2264  // Floating-point Predicates
2265  case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2266  case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
2267  case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2268  case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
2269  case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2270  case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
2271  case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2272  case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
2273  case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2274  case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2275  case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2276  case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2278  case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2279 
2280  // Integer Predicates
2281  case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2282  case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2283  case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2284  case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2285  case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2286  case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2287  case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2288  case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2289  case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2290  case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2291  }
2292 
2293  return std::make_pair(CC, NeedSwap);
2294 }
2295 
2296 /// Return a set opcode for the given condition and
2297 /// whether it has memory operand.
2298 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2299  static const uint16_t Opc[16][2] = {
2300  { X86::SETAr, X86::SETAm },
2301  { X86::SETAEr, X86::SETAEm },
2302  { X86::SETBr, X86::SETBm },
2303  { X86::SETBEr, X86::SETBEm },
2304  { X86::SETEr, X86::SETEm },
2305  { X86::SETGr, X86::SETGm },
2306  { X86::SETGEr, X86::SETGEm },
2307  { X86::SETLr, X86::SETLm },
2308  { X86::SETLEr, X86::SETLEm },
2309  { X86::SETNEr, X86::SETNEm },
2310  { X86::SETNOr, X86::SETNOm },
2311  { X86::SETNPr, X86::SETNPm },
2312  { X86::SETNSr, X86::SETNSm },
2313  { X86::SETOr, X86::SETOm },
2314  { X86::SETPr, X86::SETPm },
2315  { X86::SETSr, X86::SETSm }
2316  };
2317 
2318  assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2319  return Opc[CC][HasMemoryOperand ? 1 : 0];
2320 }
2321 
2322 /// Return a cmov opcode for the given condition,
2323 /// register size in bytes, and operand type.
2324 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2325  bool HasMemoryOperand) {
2326  static const uint16_t Opc[32][3] = {
2327  { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2328  { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2329  { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2330  { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2331  { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2332  { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2333  { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2334  { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2335  { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2336  { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2337  { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2338  { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2339  { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2340  { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2341  { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2342  { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2343  { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2344  { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2345  { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2346  { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2347  { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2348  { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2349  { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2350  { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2351  { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2352  { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2353  { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2354  { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2355  { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2356  { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2357  { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2358  { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2359  };
2360 
2361  assert(CC < 16 && "Can only handle standard cond codes");
2362  unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2363  switch(RegBytes) {
2364  default: llvm_unreachable("Illegal register size!");
2365  case 2: return Opc[Idx][0];
2366  case 4: return Opc[Idx][1];
2367  case 8: return Opc[Idx][2];
2368  }
2369 }
2370 
2371 /// Get the VPCMP immediate for the given condition.
2373  switch (CC) {
2374  default: llvm_unreachable("Unexpected SETCC condition");
2375  case ISD::SETNE: return 4;
2376  case ISD::SETEQ: return 0;
2377  case ISD::SETULT:
2378  case ISD::SETLT: return 1;
2379  case ISD::SETUGT:
2380  case ISD::SETGT: return 6;
2381  case ISD::SETUGE:
2382  case ISD::SETGE: return 5;
2383  case ISD::SETULE:
2384  case ISD::SETLE: return 2;
2385  }
2386 }
2387 
2388 /// Get the VPCMP immediate if the opcodes are swapped.
2389 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2390  switch (Imm) {
2391  default: llvm_unreachable("Unreachable!");
2392  case 0x01: Imm = 0x06; break; // LT -> NLE
2393  case 0x02: Imm = 0x05; break; // LE -> NLT
2394  case 0x05: Imm = 0x02; break; // NLT -> LE
2395  case 0x06: Imm = 0x01; break; // NLE -> LT
2396  case 0x00: // EQ
2397  case 0x03: // FALSE
2398  case 0x04: // NE
2399  case 0x07: // TRUE
2400  break;
2401  }
2402 
2403  return Imm;
2404 }
2405 
2406 /// Get the VPCOM immediate if the opcodes are swapped.
2407 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2408  switch (Imm) {
2409  default: llvm_unreachable("Unreachable!");
2410  case 0x00: Imm = 0x02; break; // LT -> GT
2411  case 0x01: Imm = 0x03; break; // LE -> GE
2412  case 0x02: Imm = 0x00; break; // GT -> LT
2413  case 0x03: Imm = 0x01; break; // GE -> LE
2414  case 0x04: // EQ
2415  case 0x05: // NE
2416  case 0x06: // FALSE
2417  case 0x07: // TRUE
2418  break;
2419  }
2420 
2421  return Imm;
2422 }
2423 
2425  if (!MI.isTerminator()) return false;
2426 
2427  // Conditional branch is a special case.
2428  if (MI.isBranch() && !MI.isBarrier())
2429  return true;
2430  if (!MI.isPredicable())
2431  return true;
2432  return !isPredicated(MI);
2433 }
2434 
2436  switch (MI.getOpcode()) {
2437  case X86::TCRETURNdi:
2438  case X86::TCRETURNri:
2439  case X86::TCRETURNmi:
2440  case X86::TCRETURNdi64:
2441  case X86::TCRETURNri64:
2442  case X86::TCRETURNmi64:
2443  return true;
2444  default:
2445  return false;
2446  }
2447 }
2448 
2450  SmallVectorImpl<MachineOperand> &BranchCond,
2451  const MachineInstr &TailCall) const {
2452  if (TailCall.getOpcode() != X86::TCRETURNdi &&
2453  TailCall.getOpcode() != X86::TCRETURNdi64) {
2454  // Only direct calls can be done with a conditional branch.
2455  return false;
2456  }
2457 
2458  const MachineFunction *MF = TailCall.getParent()->getParent();
2459  if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2460  // Conditional tail calls confuse the Win64 unwinder.
2461  return false;
2462  }
2463 
2464  assert(BranchCond.size() == 1);
2465  if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2466  // Can't make a conditional tail call with this condition.
2467  return false;
2468  }
2469 
2471  if (X86FI->getTCReturnAddrDelta() != 0 ||
2472  TailCall.getOperand(1).getImm() != 0) {
2473  // A conditional tail call cannot do any stack adjustment.
2474  return false;
2475  }
2476 
2477  return true;
2478 }
2479 
2482  const MachineInstr &TailCall) const {
2483  assert(canMakeTailCallConditional(BranchCond, TailCall));
2484 
2486  while (I != MBB.begin()) {
2487  --I;
2488  if (I->isDebugInstr())
2489  continue;
2490  if (!I->isBranch())
2491  assert(0 && "Can't find the branch to replace!");
2492 
2493  X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
2494  assert(BranchCond.size() == 1);
2495  if (CC != BranchCond[0].getImm())
2496  continue;
2497 
2498  break;
2499  }
2500 
2501  unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2502  : X86::TCRETURNdi64cc;
2503 
2504  auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2505  MIB->addOperand(TailCall.getOperand(0)); // Destination.
2506  MIB.addImm(0); // Stack offset (not used).
2507  MIB->addOperand(BranchCond[0]); // Condition.
2508  MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2509 
2510  // Add implicit uses and defs of all live regs potentially clobbered by the
2511  // call. This way they still appear live across the call.
2512  LivePhysRegs LiveRegs(getRegisterInfo());
2513  LiveRegs.addLiveOuts(MBB);
2515  LiveRegs.stepForward(*MIB, Clobbers);
2516  for (const auto &C : Clobbers) {
2517  MIB.addReg(C.first, RegState::Implicit);
2518  MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2519  }
2520 
2521  I->eraseFromParent();
2522 }
2523 
2524 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2525 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2526 // fallthrough MBB cannot be identified.
2528  MachineBasicBlock *TBB) {
2529  // Look for non-EHPad successors other than TBB. If we find exactly one, it
2530  // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2531  // and fallthrough MBB. If we find more than one, we cannot identify the
2532  // fallthrough MBB and should return nullptr.
2533  MachineBasicBlock *FallthroughBB = nullptr;
2534  for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2535  if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2536  continue;
2537  // Return a nullptr if we found more than one fallthrough successor.
2538  if (FallthroughBB && FallthroughBB != TBB)
2539  return nullptr;
2540  FallthroughBB = *SI;
2541  }
2542  return FallthroughBB;
2543 }
2544 
2545 bool X86InstrInfo::AnalyzeBranchImpl(
2548  SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2549 
2550  // Start from the bottom of the block and work up, examining the
2551  // terminator instructions.
2553  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2554  while (I != MBB.begin()) {
2555  --I;
2556  if (I->isDebugInstr())
2557  continue;
2558 
2559  // Working from the bottom, when we see a non-terminator instruction, we're
2560  // done.
2561  if (!isUnpredicatedTerminator(*I))
2562  break;
2563 
2564  // A terminator that isn't a branch can't easily be handled by this
2565  // analysis.
2566  if (!I->isBranch())
2567  return true;
2568 
2569  // Handle unconditional branches.
2570  if (I->getOpcode() == X86::JMP_1) {
2571  UnCondBrIter = I;
2572 
2573  if (!AllowModify) {
2574  TBB = I->getOperand(0).getMBB();
2575  continue;
2576  }
2577 
2578  // If the block has any instructions after a JMP, delete them.
2579  while (std::next(I) != MBB.end())
2580  std::next(I)->eraseFromParent();
2581 
2582  Cond.clear();
2583  FBB = nullptr;
2584 
2585  // Delete the JMP if it's equivalent to a fall-through.
2586  if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2587  TBB = nullptr;
2588  I->eraseFromParent();
2589  I = MBB.end();
2590  UnCondBrIter = MBB.end();
2591  continue;
2592  }
2593 
2594  // TBB is used to indicate the unconditional destination.
2595  TBB = I->getOperand(0).getMBB();
2596  continue;
2597  }
2598 
2599  // Handle conditional branches.
2600  X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
2601  if (BranchCode == X86::COND_INVALID)
2602  return true; // Can't handle indirect branch.
2603 
2604  // In practice we should never have an undef eflags operand, if we do
2605  // abort here as we are not prepared to preserve the flag.
2606  if (I->getOperand(1).isUndef())
2607  return true;
2608 
2609  // Working from the bottom, handle the first conditional branch.
2610  if (Cond.empty()) {
2611  MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2612  if (AllowModify && UnCondBrIter != MBB.end() &&
2613  MBB.isLayoutSuccessor(TargetBB)) {
2614  // If we can modify the code and it ends in something like:
2615  //
2616  // jCC L1
2617  // jmp L2
2618  // L1:
2619  // ...
2620  // L2:
2621  //
2622  // Then we can change this to:
2623  //
2624  // jnCC L2
2625  // L1:
2626  // ...
2627  // L2:
2628  //
2629  // Which is a bit more efficient.
2630  // We conditionally jump to the fall-through block.
2631  BranchCode = GetOppositeBranchCondition(BranchCode);
2632  unsigned JNCC = GetCondBranchFromCond(BranchCode);
2633  MachineBasicBlock::iterator OldInst = I;
2634 
2635  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2636  .addMBB(UnCondBrIter->getOperand(0).getMBB());
2637  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2638  .addMBB(TargetBB);
2639 
2640  OldInst->eraseFromParent();
2641  UnCondBrIter->eraseFromParent();
2642 
2643  // Restart the analysis.
2644  UnCondBrIter = MBB.end();
2645  I = MBB.end();
2646  continue;
2647  }
2648 
2649  FBB = TBB;
2650  TBB = I->getOperand(0).getMBB();
2651  Cond.push_back(MachineOperand::CreateImm(BranchCode));
2652  CondBranches.push_back(&*I);
2653  continue;
2654  }
2655 
2656  // Handle subsequent conditional branches. Only handle the case where all
2657  // conditional branches branch to the same destination and their condition
2658  // opcodes fit one of the special multi-branch idioms.
2659  assert(Cond.size() == 1);
2660  assert(TBB);
2661 
2662  // If the conditions are the same, we can leave them alone.
2663  X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2664  auto NewTBB = I->getOperand(0).getMBB();
2665  if (OldBranchCode == BranchCode && TBB == NewTBB)
2666  continue;
2667 
2668  // If they differ, see if they fit one of the known patterns. Theoretically,
2669  // we could handle more patterns here, but we shouldn't expect to see them
2670  // if instruction selection has done a reasonable job.
2671  if (TBB == NewTBB &&
2672  ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2673  (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2674  BranchCode = X86::COND_NE_OR_P;
2675  } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2676  (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2677  if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2678  return true;
2679 
2680  // X86::COND_E_AND_NP usually has two different branch destinations.
2681  //
2682  // JP B1
2683  // JE B2
2684  // JMP B1
2685  // B1:
2686  // B2:
2687  //
2688  // Here this condition branches to B2 only if NP && E. It has another
2689  // equivalent form:
2690  //
2691  // JNE B1
2692  // JNP B2
2693  // JMP B1
2694  // B1:
2695  // B2:
2696  //
2697  // Similarly it branches to B2 only if E && NP. That is why this condition
2698  // is named with COND_E_AND_NP.
2699  BranchCode = X86::COND_E_AND_NP;
2700  } else
2701  return true;
2702 
2703  // Update the MachineOperand.
2704  Cond[0].setImm(BranchCode);
2705  CondBranches.push_back(&*I);
2706  }
2707 
2708  return false;
2709 }
2710 
2712  MachineBasicBlock *&TBB,
2713  MachineBasicBlock *&FBB,
2715  bool AllowModify) const {
2716  SmallVector<MachineInstr *, 4> CondBranches;
2717  return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2718 }
2719 
2721  MachineBranchPredicate &MBP,
2722  bool AllowModify) const {
2723  using namespace std::placeholders;
2724 
2726  SmallVector<MachineInstr *, 4> CondBranches;
2727  if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2728  AllowModify))
2729  return true;
2730 
2731  if (Cond.size() != 1)
2732  return true;
2733 
2734  assert(MBP.TrueDest && "expected!");
2735 
2736  if (!MBP.FalseDest)
2737  MBP.FalseDest = MBB.getNextNode();
2738 
2740 
2741  MachineInstr *ConditionDef = nullptr;
2742  bool SingleUseCondition = true;
2743 
2744  for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2745  if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2746  ConditionDef = &*I;
2747  break;
2748  }
2749 
2750  if (I->readsRegister(X86::EFLAGS, TRI))
2751  SingleUseCondition = false;
2752  }
2753 
2754  if (!ConditionDef)
2755  return true;
2756 
2757  if (SingleUseCondition) {
2758  for (auto *Succ : MBB.successors())
2759  if (Succ->isLiveIn(X86::EFLAGS))
2760  SingleUseCondition = false;
2761  }
2762 
2763  MBP.ConditionDef = ConditionDef;
2764  MBP.SingleUseCondition = SingleUseCondition;
2765 
2766  // Currently we only recognize the simple pattern:
2767  //
2768  // test %reg, %reg
2769  // je %label
2770  //
2771  const unsigned TestOpcode =
2772  Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2773 
2774  if (ConditionDef->getOpcode() == TestOpcode &&
2775  ConditionDef->getNumOperands() == 3 &&
2776  ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2777  (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2778  MBP.LHS = ConditionDef->getOperand(0);
2779  MBP.RHS = MachineOperand::CreateImm(0);
2780  MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2783  return false;
2784  }
2785 
2786  return true;
2787 }
2788 
2790  int *BytesRemoved) const {
2791  assert(!BytesRemoved && "code size not handled");
2792 
2794  unsigned Count = 0;
2795 
2796  while (I != MBB.begin()) {
2797  --I;
2798  if (I->isDebugInstr())
2799  continue;
2800  if (I->getOpcode() != X86::JMP_1 &&
2801  X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2802  break;
2803  // Remove the branch.
2804  I->eraseFromParent();
2805  I = MBB.end();
2806  ++Count;
2807  }
2808 
2809  return Count;
2810 }
2811 
2813  MachineBasicBlock *TBB,
2814  MachineBasicBlock *FBB,
2816  const DebugLoc &DL,
2817  int *BytesAdded) const {
2818  // Shouldn't be a fall through.
2819  assert(TBB && "insertBranch must not be told to insert a fallthrough");
2820  assert((Cond.size() == 1 || Cond.size() == 0) &&
2821  "X86 branch conditions have one component!");
2822  assert(!BytesAdded && "code size not handled");
2823 
2824  if (Cond.empty()) {
2825  // Unconditional branch?
2826  assert(!FBB && "Unconditional branch with multiple successors!");
2827  BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2828  return 1;
2829  }
2830 
2831  // If FBB is null, it is implied to be a fall-through block.
2832  bool FallThru = FBB == nullptr;
2833 
2834  // Conditional branch.
2835  unsigned Count = 0;
2836  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2837  switch (CC) {
2838  case X86::COND_NE_OR_P:
2839  // Synthesize NE_OR_P with two branches.
2840  BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
2841  ++Count;
2842  BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
2843  ++Count;
2844  break;
2845  case X86::COND_E_AND_NP:
2846  // Use the next block of MBB as FBB if it is null.
2847  if (FBB == nullptr) {
2848  FBB = getFallThroughMBB(&MBB, TBB);
2849  assert(FBB && "MBB cannot be the last block in function when the false "
2850  "body is a fall-through.");
2851  }
2852  // Synthesize COND_E_AND_NP with two branches.
2853  BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
2854  ++Count;
2855  BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
2856  ++Count;
2857  break;
2858  default: {
2859  unsigned Opc = GetCondBranchFromCond(CC);
2860  BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2861  ++Count;
2862  }
2863  }
2864  if (!FallThru) {
2865  // Two-way Conditional branch. Insert the second branch.
2866  BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2867  ++Count;
2868  }
2869  return Count;
2870 }
2871 
2872 bool X86InstrInfo::
2875  unsigned TrueReg, unsigned FalseReg,
2876  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2877  // Not all subtargets have cmov instructions.
2878  if (!Subtarget.hasCMov())
2879  return false;
2880  if (Cond.size() != 1)
2881  return false;
2882  // We cannot do the composite conditions, at least not in SSA form.
2883  if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2884  return false;
2885 
2886  // Check register classes.
2887  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2888  const TargetRegisterClass *RC =
2889  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2890  if (!RC)
2891  return false;
2892 
2893  // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2894  if (X86::GR16RegClass.hasSubClassEq(RC) ||
2895  X86::GR32RegClass.hasSubClassEq(RC) ||
2896  X86::GR64RegClass.hasSubClassEq(RC)) {
2897  // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2898  // Bridge. Probably Ivy Bridge as well.
2899  CondCycles = 2;
2900  TrueCycles = 2;
2901  FalseCycles = 2;
2902  return true;
2903  }
2904 
2905  // Can't do vectors.
2906  return false;
2907 }
2908 
2911  const DebugLoc &DL, unsigned DstReg,
2912  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2913  unsigned FalseReg) const {
2916  const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2917  assert(Cond.size() == 1 && "Invalid Cond array");
2918  unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2919  TRI.getRegSizeInBits(RC) / 8,
2920  false /*HasMemoryOperand*/);
2921  BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2922 }
2923 
2924 /// Test if the given register is a physical h register.
2925 static bool isHReg(unsigned Reg) {
2926  return X86::GR8_ABCD_HRegClass.contains(Reg);
2927 }
2928 
2929 // Try and copy between VR128/VR64 and GR64 registers.
2930 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2931  const X86Subtarget &Subtarget) {
2932  bool HasAVX = Subtarget.hasAVX();
2933  bool HasAVX512 = Subtarget.hasAVX512();
2934 
2935  // SrcReg(MaskReg) -> DestReg(GR64)
2936  // SrcReg(MaskReg) -> DestReg(GR32)
2937 
2938  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2939  if (X86::VK16RegClass.contains(SrcReg)) {
2940  if (X86::GR64RegClass.contains(DestReg)) {
2941  assert(Subtarget.hasBWI());
2942  return X86::KMOVQrk;
2943  }
2944  if (X86::GR32RegClass.contains(DestReg))
2945  return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2946  }
2947 
2948  // SrcReg(GR64) -> DestReg(MaskReg)
2949  // SrcReg(GR32) -> DestReg(MaskReg)
2950 
2951  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2952  if (X86::VK16RegClass.contains(DestReg)) {
2953  if (X86::GR64RegClass.contains(SrcReg)) {
2954  assert(Subtarget.hasBWI());
2955  return X86::KMOVQkr;
2956  }
2957  if (X86::GR32RegClass.contains(SrcReg))
2958  return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2959  }
2960 
2961 
2962  // SrcReg(VR128) -> DestReg(GR64)
2963  // SrcReg(VR64) -> DestReg(GR64)
2964  // SrcReg(GR64) -> DestReg(VR128)
2965  // SrcReg(GR64) -> DestReg(VR64)
2966 
2967  if (X86::GR64RegClass.contains(DestReg)) {
2968  if (X86::VR128XRegClass.contains(SrcReg))
2969  // Copy from a VR128 register to a GR64 register.
2970  return HasAVX512 ? X86::VMOVPQIto64Zrr :
2971  HasAVX ? X86::VMOVPQIto64rr :
2972  X86::MOVPQIto64rr;
2973  if (X86::VR64RegClass.contains(SrcReg))
2974  // Copy from a VR64 register to a GR64 register.
2975  return X86::MMX_MOVD64from64rr;
2976  } else if (X86::GR64RegClass.contains(SrcReg)) {
2977  // Copy from a GR64 register to a VR128 register.
2978  if (X86::VR128XRegClass.contains(DestReg))
2979  return HasAVX512 ? X86::VMOV64toPQIZrr :
2980  HasAVX ? X86::VMOV64toPQIrr :
2981  X86::MOV64toPQIrr;
2982  // Copy from a GR64 register to a VR64 register.
2983  if (X86::VR64RegClass.contains(DestReg))
2984  return X86::MMX_MOVD64to64rr;
2985  }
2986 
2987  // SrcReg(FR32) -> DestReg(GR32)
2988  // SrcReg(GR32) -> DestReg(FR32)
2989 
2990  if (X86::GR32RegClass.contains(DestReg) &&
2991  X86::FR32XRegClass.contains(SrcReg))
2992  // Copy from a FR32 register to a GR32 register.
2993  return HasAVX512 ? X86::VMOVSS2DIZrr :
2994  HasAVX ? X86::VMOVSS2DIrr :
2995  X86::MOVSS2DIrr;
2996 
2997  if (X86::FR32XRegClass.contains(DestReg) &&
2998  X86::GR32RegClass.contains(SrcReg))
2999  // Copy from a GR32 register to a FR32 register.
3000  return HasAVX512 ? X86::VMOVDI2SSZrr :
3001  HasAVX ? X86::VMOVDI2SSrr :
3002  X86::MOVDI2SSrr;
3003  return 0;
3004 }
3005 
3008  const DebugLoc &DL, unsigned DestReg,
3009  unsigned SrcReg, bool KillSrc) const {
3010  // First deal with the normal symmetric copies.
3011  bool HasAVX = Subtarget.hasAVX();
3012  bool HasVLX = Subtarget.hasVLX();
3013  unsigned Opc = 0;
3014  if (X86::GR64RegClass.contains(DestReg, SrcReg))
3015  Opc = X86::MOV64rr;
3016  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3017  Opc = X86::MOV32rr;
3018  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3019  Opc = X86::MOV16rr;
3020  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3021  // Copying to or from a physical H register on x86-64 requires a NOREX
3022  // move. Otherwise use a normal move.
3023  if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3024  Subtarget.is64Bit()) {
3025  Opc = X86::MOV8rr_NOREX;
3026  // Both operands must be encodable without an REX prefix.
3027  assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3028  "8-bit H register can not be copied outside GR8_NOREX");
3029  } else
3030  Opc = X86::MOV8rr;
3031  }
3032  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3033  Opc = X86::MMX_MOVQ64rr;
3034  else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3035  if (HasVLX)
3036  Opc = X86::VMOVAPSZ128rr;
3037  else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3038  Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3039  else {
3040  // If this an extended register and we don't have VLX we need to use a
3041  // 512-bit move.
3042  Opc = X86::VMOVAPSZrr;
3044  DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3045  &X86::VR512RegClass);
3046  SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3047  &X86::VR512RegClass);
3048  }
3049  } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3050  if (HasVLX)
3051  Opc = X86::VMOVAPSZ256rr;
3052  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3053  Opc = X86::VMOVAPSYrr;
3054  else {
3055  // If this an extended register and we don't have VLX we need to use a
3056  // 512-bit move.
3057  Opc = X86::VMOVAPSZrr;
3059  DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3060  &X86::VR512RegClass);
3061  SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3062  &X86::VR512RegClass);
3063  }
3064  } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3065  Opc = X86::VMOVAPSZrr;
3066  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3067  else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3068  Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3069  if (!Opc)
3070  Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3071 
3072  if (Opc) {
3073  BuildMI(MBB, MI, DL, get(Opc), DestReg)
3074  .addReg(SrcReg, getKillRegState(KillSrc));
3075  return;
3076  }
3077 
3078  if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3079  // FIXME: We use a fatal error here because historically LLVM has tried
3080  // lower some of these physreg copies and we want to ensure we get
3081  // reasonable bug reports if someone encounters a case no other testing
3082  // found. This path should be removed after the LLVM 7 release.
3083  report_fatal_error("Unable to copy EFLAGS physical register!");
3084  }
3085 
3086  LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3087  << RI.getName(DestReg) << '\n');
3088  report_fatal_error("Cannot emit physreg copy instruction");
3089 }
3090 
3092  const MachineOperand *&Src,
3093  const MachineOperand *&Dest) const {
3094  if (MI.isMoveReg()) {
3095  Dest = &MI.getOperand(0);
3096  Src = &MI.getOperand(1);
3097  return true;
3098  }
3099  return false;
3100 }
3101 
3102 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3103  const TargetRegisterClass *RC,
3104  bool isStackAligned,
3105  const X86Subtarget &STI,
3106  bool load) {
3107  bool HasAVX = STI.hasAVX();
3108  bool HasAVX512 = STI.hasAVX512();
3109  bool HasVLX = STI.hasVLX();
3110 
3111  switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3112  default:
3113  llvm_unreachable("Unknown spill size");
3114  case 1:
3115  assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3116  if (STI.is64Bit())
3117  // Copying to or from a physical H register on x86-64 requires a NOREX
3118  // move. Otherwise use a normal move.
3119  if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3120  return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3121  return load ? X86::MOV8rm : X86::MOV8mr;
3122  case 2:
3123  if (X86::VK16RegClass.hasSubClassEq(RC))
3124  return load ? X86::KMOVWkm : X86::KMOVWmk;
3125  assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3126  return load ? X86::MOV16rm : X86::MOV16mr;
3127  case 4:
3128  if (X86::GR32RegClass.hasSubClassEq(RC))
3129  return load ? X86::MOV32rm : X86::MOV32mr;
3130  if (X86::FR32XRegClass.hasSubClassEq(RC))
3131  return load ?
3132  (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3133  (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3134  if (X86::RFP32RegClass.hasSubClassEq(RC))
3135  return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3136  if (X86::VK32RegClass.hasSubClassEq(RC)) {
3137  assert(STI.hasBWI() && "KMOVD requires BWI");
3138  return load ? X86::KMOVDkm : X86::KMOVDmk;
3139  }
3140  llvm_unreachable("Unknown 4-byte regclass");
3141  case 8:
3142  if (X86::GR64RegClass.hasSubClassEq(RC))
3143  return load ? X86::MOV64rm : X86::MOV64mr;
3144  if (X86::FR64XRegClass.hasSubClassEq(RC))
3145  return load ?
3146  (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3147  (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3148  if (X86::VR64RegClass.hasSubClassEq(RC))
3149  return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3150  if (X86::RFP64RegClass.hasSubClassEq(RC))
3151  return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3152  if (X86::VK64RegClass.hasSubClassEq(RC)) {
3153  assert(STI.hasBWI() && "KMOVQ requires BWI");
3154  return load ? X86::KMOVQkm : X86::KMOVQmk;
3155  }
3156  llvm_unreachable("Unknown 8-byte regclass");
3157  case 10:
3158  assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3159  return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3160  case 16: {
3161  if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3162  // If stack is realigned we can use aligned stores.
3163  if (isStackAligned)
3164  return load ?
3165  (HasVLX ? X86::VMOVAPSZ128rm :
3166  HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3167  HasAVX ? X86::VMOVAPSrm :
3168  X86::MOVAPSrm):
3169  (HasVLX ? X86::VMOVAPSZ128mr :
3170  HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3171  HasAVX ? X86::VMOVAPSmr :
3172  X86::MOVAPSmr);
3173  else
3174  return load ?
3175  (HasVLX ? X86::VMOVUPSZ128rm :
3176  HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3177  HasAVX ? X86::VMOVUPSrm :
3178  X86::MOVUPSrm):
3179  (HasVLX ? X86::VMOVUPSZ128mr :
3180  HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3181  HasAVX ? X86::VMOVUPSmr :
3182  X86::MOVUPSmr);
3183  }
3184  if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3185  if (STI.is64Bit())
3186  return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3187  else
3188  return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3189  }
3190  llvm_unreachable("Unknown 16-byte regclass");
3191  }
3192  case 32:
3193  assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3194  // If stack is realigned we can use aligned stores.
3195  if (isStackAligned)
3196  return load ?
3197  (HasVLX ? X86::VMOVAPSZ256rm :
3198  HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3199  X86::VMOVAPSYrm) :
3200  (HasVLX ? X86::VMOVAPSZ256mr :
3201  HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3202  X86::VMOVAPSYmr);
3203  else
3204  return load ?
3205  (HasVLX ? X86::VMOVUPSZ256rm :
3206  HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3207  X86::VMOVUPSYrm) :
3208  (HasVLX ? X86::VMOVUPSZ256mr :
3209  HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3210  X86::VMOVUPSYmr);
3211  case 64:
3212  assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3213  assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3214  if (isStackAligned)
3215  return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3216  else
3217  return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3218  }
3219 }
3220 
3222  MachineInstr &MemOp, MachineOperand *&BaseOp, int64_t &Offset,
3223  const TargetRegisterInfo *TRI) const {
3224  const MCInstrDesc &Desc = MemOp.getDesc();
3225  int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3226  if (MemRefBegin < 0)
3227  return false;
3228 
3229  MemRefBegin += X86II::getOperandBias(Desc);
3230 
3231  BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3232  if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3233  return false;
3234 
3235  if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3236  return false;
3237 
3238  if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3239  X86::NoRegister)
3240  return false;
3241 
3242  const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3243 
3244  // Displacement can be symbolic
3245  if (!DispMO.isImm())
3246  return false;
3247 
3248  Offset = DispMO.getImm();
3249 
3250  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3251  "operands of type register.");
3252  return true;
3253 }
3254 
3255 static unsigned getStoreRegOpcode(unsigned SrcReg,
3256  const TargetRegisterClass *RC,
3257  bool isStackAligned,
3258  const X86Subtarget &STI) {
3259  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3260 }
3261 
3262 
3263 static unsigned getLoadRegOpcode(unsigned DestReg,
3264  const TargetRegisterClass *RC,
3265  bool isStackAligned,
3266  const X86Subtarget &STI) {
3267  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3268 }
3269 
3272  unsigned SrcReg, bool isKill, int FrameIdx,
3273  const TargetRegisterClass *RC,
3274  const TargetRegisterInfo *TRI) const {
3275  const MachineFunction &MF = *MBB.getParent();
3276  assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3277  "Stack slot too small for store");
3278  unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3279  bool isAligned =
3280  (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3281  RI.canRealignStack(MF);
3282  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3283  addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3284  .addReg(SrcReg, getKillRegState(isKill));
3285 }
3286 
3288  MachineFunction &MF, unsigned SrcReg, bool isKill,
3291  SmallVectorImpl<MachineInstr *> &NewMIs) const {
3293  unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3294  bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3295  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3296  DebugLoc DL;
3297  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3298  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3299  MIB.add(Addr[i]);
3300  MIB.addReg(SrcReg, getKillRegState(isKill));
3301  MIB.setMemRefs(MMOs);
3302  NewMIs.push_back(MIB);
3303 }
3304 
3305 
3308  unsigned DestReg, int FrameIdx,
3309  const TargetRegisterClass *RC,
3310  const TargetRegisterInfo *TRI) const {
3311  const MachineFunction &MF = *MBB.getParent();
3312  unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3313  bool isAligned =
3314  (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3315  RI.canRealignStack(MF);
3316  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3317  addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3318 }
3319 
3321  MachineFunction &MF, unsigned DestReg,
3324  SmallVectorImpl<MachineInstr *> &NewMIs) const {
3326  unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3327  bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3328  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3329  DebugLoc DL;
3330  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3331  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3332  MIB.add(Addr[i]);
3333  MIB.setMemRefs(MMOs);
3334  NewMIs.push_back(MIB);
3335 }
3336 
3337 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3338  unsigned &SrcReg2, int &CmpMask,
3339  int &CmpValue) const {
3340  switch (MI.getOpcode()) {
3341  default: break;
3342  case X86::CMP64ri32:
3343  case X86::CMP64ri8:
3344  case X86::CMP32ri:
3345  case X86::CMP32ri8:
3346  case X86::CMP16ri:
3347  case X86::CMP16ri8:
3348  case X86::CMP8ri:
3349  SrcReg = MI.getOperand(0).getReg();
3350  SrcReg2 = 0;
3351  if (MI.getOperand(1).isImm()) {
3352  CmpMask = ~0;
3353  CmpValue = MI.getOperand(1).getImm();
3354  } else {
3355  CmpMask = CmpValue = 0;
3356  }
3357  return true;
3358  // A SUB can be used to perform comparison.
3359  case X86::SUB64rm:
3360  case X86::SUB32rm:
3361  case X86::SUB16rm:
3362  case X86::SUB8rm:
3363  SrcReg = MI.getOperand(1).getReg();
3364  SrcReg2 = 0;
3365  CmpMask = 0;
3366  CmpValue = 0;
3367  return true;
3368  case X86::SUB64rr:
3369  case X86::SUB32rr:
3370  case X86::SUB16rr:
3371  case X86::SUB8rr:
3372  SrcReg = MI.getOperand(1).getReg();
3373  SrcReg2 = MI.getOperand(2).getReg();
3374  CmpMask = 0;
3375  CmpValue = 0;
3376  return true;
3377  case X86::SUB64ri32:
3378  case X86::SUB64ri8:
3379  case X86::SUB32ri:
3380  case X86::SUB32ri8:
3381  case X86::SUB16ri:
3382  case X86::SUB16ri8:
3383  case X86::SUB8ri:
3384  SrcReg = MI.getOperand(1).getReg();
3385  SrcReg2 = 0;
3386  if (MI.getOperand(2).isImm()) {
3387  CmpMask = ~0;
3388  CmpValue = MI.getOperand(2).getImm();
3389  } else {
3390  CmpMask = CmpValue = 0;
3391  }
3392  return true;
3393  case X86::CMP64rr:
3394  case X86::CMP32rr:
3395  case X86::CMP16rr:
3396  case X86::CMP8rr:
3397  SrcReg = MI.getOperand(0).getReg();
3398  SrcReg2 = MI.getOperand(1).getReg();
3399  CmpMask = 0;
3400  CmpValue = 0;
3401  return true;
3402  case X86::TEST8rr:
3403  case X86::TEST16rr:
3404  case X86::TEST32rr:
3405  case X86::TEST64rr:
3406  SrcReg = MI.getOperand(0).getReg();
3407  if (MI.getOperand(1).getReg() != SrcReg)
3408  return false;
3409  // Compare against zero.
3410  SrcReg2 = 0;
3411  CmpMask = ~0;
3412  CmpValue = 0;
3413  return true;
3414  }
3415  return false;
3416 }
3417 
3418 /// Check whether the first instruction, whose only
3419 /// purpose is to update flags, can be made redundant.
3420 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3421 /// This function can be extended later on.
3422 /// SrcReg, SrcRegs: register operands for FlagI.
3423 /// ImmValue: immediate for FlagI if it takes an immediate.
3424 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
3425  unsigned SrcReg2, int ImmMask,
3426  int ImmValue, MachineInstr &OI) {
3427  if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3428  (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3429  (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3430  (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3431  ((OI.getOperand(1).getReg() == SrcReg &&
3432  OI.getOperand(2).getReg() == SrcReg2) ||
3433  (OI.getOperand(1).getReg() == SrcReg2 &&
3434  OI.getOperand(2).getReg() == SrcReg)))
3435  return true;
3436 
3437  if (ImmMask != 0 &&
3438  ((FlagI.getOpcode() == X86::CMP64ri32 &&
3439  OI.getOpcode() == X86::SUB64ri32) ||
3440  (FlagI.getOpcode() == X86::CMP64ri8 &&
3441  OI.getOpcode() == X86::SUB64ri8) ||
3442  (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3443  (FlagI.getOpcode() == X86::CMP32ri8 &&
3444  OI.getOpcode() == X86::SUB32ri8) ||
3445  (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3446  (FlagI.getOpcode() == X86::CMP16ri8 &&
3447  OI.getOpcode() == X86::SUB16ri8) ||
3448  (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3449  OI.getOperand(1).getReg() == SrcReg &&
3450  OI.getOperand(2).getImm() == ImmValue)
3451  return true;
3452  return false;
3453 }
3454 
3455 /// Check whether the definition can be converted
3456 /// to remove a comparison against zero.
3457 inline static bool isDefConvertible(MachineInstr &MI) {
3458  switch (MI.getOpcode()) {
3459  default: return false;
3460 
3461  // The shift instructions only modify ZF if their shift count is non-zero.
3462  // N.B.: The processor truncates the shift count depending on the encoding.
3463  case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3464  case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3465  return getTruncatedShiftCount(MI, 2) != 0;
3466 
3467  // Some left shift instructions can be turned into LEA instructions but only
3468  // if their flags aren't used. Avoid transforming such instructions.
3469  case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3470  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3471  if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3472  return ShAmt != 0;
3473  }
3474 
3475  case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3476  case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3477  return getTruncatedShiftCount(MI, 3) != 0;
3478 
3479  case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3480  case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3481  case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3482  case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3483  case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3484  case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3485  case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3486  case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3487  case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3488  case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3489  case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3490  case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3491  case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3492  case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3493  case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3494  case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3495  case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3496  case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3497  case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3498  case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3499  case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3500  case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3501  case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3502  case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3503  case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3504  case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3505  case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3506  case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3507  case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3508  case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3509  case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3510  case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3511  case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3512  case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3513  case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3514  case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3515  case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3516  case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3517  case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3518  case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3519  case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3520  case X86::ANDN32rr: case X86::ANDN32rm:
3521  case X86::ANDN64rr: case X86::ANDN64rm:
3522  case X86::BEXTR32rr: case X86::BEXTR64rr:
3523  case X86::BEXTR32rm: case X86::BEXTR64rm:
3524  case X86::BLSI32rr: case X86::BLSI32rm:
3525  case X86::BLSI64rr: case X86::BLSI64rm:
3526  case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3527  case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3528  case X86::BLSR32rr: case X86::BLSR32rm:
3529  case X86::BLSR64rr: case X86::BLSR64rm:
3530  case X86::BZHI32rr: case X86::BZHI32rm:
3531  case X86::BZHI64rr: case X86::BZHI64rm:
3532  case X86::LZCNT16rr: case X86::LZCNT16rm:
3533  case X86::LZCNT32rr: case X86::LZCNT32rm:
3534  case X86::LZCNT64rr: case X86::LZCNT64rm:
3535  case X86::POPCNT16rr:case X86::POPCNT16rm:
3536  case X86::POPCNT32rr:case X86::POPCNT32rm:
3537  case X86::POPCNT64rr:case X86::POPCNT64rm:
3538  case X86::TZCNT16rr: case X86::TZCNT16rm:
3539  case X86::TZCNT32rr: case X86::TZCNT32rm:
3540  case X86::TZCNT64rr: case X86::TZCNT64rm:
3541  case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3542  case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3543  case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3544  case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3545  case X86::BLCI32rr: case X86::BLCI32rm:
3546  case X86::BLCI64rr: case X86::BLCI64rm:
3547  case X86::BLCIC32rr: case X86::BLCIC32rm:
3548  case X86::BLCIC64rr: case X86::BLCIC64rm:
3549  case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3550  case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3551  case X86::BLCS32rr: case X86::BLCS32rm:
3552  case X86::BLCS64rr: case X86::BLCS64rm:
3553  case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3554  case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3555  case X86::BLSIC32rr: case X86::BLSIC32rm:
3556  case X86::BLSIC64rr: case X86::BLSIC64rm:
3557  return true;
3558  }
3559 }
3560 
3561 /// Check whether the use can be converted to remove a comparison against zero.
3563  switch (MI.getOpcode()) {
3564  default: return X86::COND_INVALID;
3565  case X86::LZCNT16rr: case X86::LZCNT16rm:
3566  case X86::LZCNT32rr: case X86::LZCNT32rm:
3567  case X86::LZCNT64rr: case X86::LZCNT64rm:
3568  return X86::COND_B;
3569  case X86::POPCNT16rr:case X86::POPCNT16rm:
3570  case X86::POPCNT32rr:case X86::POPCNT32rm:
3571  case X86::POPCNT64rr:case X86::POPCNT64rm:
3572  return X86::COND_E;
3573  case X86::TZCNT16rr: case X86::TZCNT16rm:
3574  case X86::TZCNT32rr: case X86::TZCNT32rm:
3575  case X86::TZCNT64rr: case X86::TZCNT64rm:
3576  return X86::COND_B;
3577  case X86::BSF16rr:
3578  case X86::BSF16rm:
3579  case X86::BSF32rr:
3580  case X86::BSF32rm:
3581  case X86::BSF64rr:
3582  case X86::BSF64rm:
3583  return X86::COND_E;
3584  }
3585 }
3586 
3587 /// Check if there exists an earlier instruction that
3588 /// operates on the same source operands and sets flags in the same way as
3589 /// Compare; remove Compare if possible.
3590 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3591  unsigned SrcReg2, int CmpMask,
3592  int CmpValue,
3593  const MachineRegisterInfo *MRI) const {
3594  // Check whether we can replace SUB with CMP.
3595  unsigned NewOpcode = 0;
3596  switch (CmpInstr.getOpcode()) {
3597  default: break;
3598  case X86::SUB64ri32:
3599  case X86::SUB64ri8:
3600  case X86::SUB32ri:
3601  case X86::SUB32ri8:
3602  case X86::SUB16ri:
3603  case X86::SUB16ri8:
3604  case X86::SUB8ri:
3605  case X86::SUB64rm:
3606  case X86::SUB32rm:
3607  case X86::SUB16rm:
3608  case X86::SUB8rm:
3609  case X86::SUB64rr:
3610  case X86::SUB32rr:
3611  case X86::SUB16rr:
3612  case X86::SUB8rr: {
3613  if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3614  return false;
3615  // There is no use of the destination register, we can replace SUB with CMP.
3616  switch (CmpInstr.getOpcode()) {
3617  default: llvm_unreachable("Unreachable!");
3618  case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3619  case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3620  case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3621  case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3622  case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3623  case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3624  case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3625  case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3626  case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3627  case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3628  case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3629  case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3630  case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3631  case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3632  case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3633  }
3634  CmpInstr.setDesc(get(NewOpcode));
3635  CmpInstr.RemoveOperand(0);
3636  // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3637  if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3638  NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3639  return false;
3640  }
3641  }
3642 
3643  // Get the unique definition of SrcReg.
3644  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3645  if (!MI) return false;
3646 
3647  // CmpInstr is the first instruction of the BB.
3648  MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3649 
3650  // If we are comparing against zero, check whether we can use MI to update
3651  // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3652  bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3653  if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3654  return false;
3655 
3656  // If we have a use of the source register between the def and our compare
3657  // instruction we can eliminate the compare iff the use sets EFLAGS in the
3658  // right way.
3659  bool ShouldUpdateCC = false;
3661  if (IsCmpZero && !isDefConvertible(*MI)) {
3662  // Scan forward from the use until we hit the use we're looking for or the
3663  // compare instruction.
3664  for (MachineBasicBlock::iterator J = MI;; ++J) {
3665  // Do we have a convertible instruction?
3666  NewCC = isUseDefConvertible(*J);
3667  if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3668  J->getOperand(1).getReg() == SrcReg) {
3669  assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3670  ShouldUpdateCC = true; // Update CC later on.
3671  // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3672  // with the new def.
3673  Def = J;
3674  MI = &*Def;
3675  break;
3676  }
3677 
3678  if (J == I)
3679  return false;
3680  }
3681  }
3682 
3683  // We are searching for an earlier instruction that can make CmpInstr
3684  // redundant and that instruction will be saved in Sub.
3685  MachineInstr *Sub = nullptr;
3687 
3688  // We iterate backward, starting from the instruction before CmpInstr and
3689  // stop when reaching the definition of a source register or done with the BB.
3690  // RI points to the instruction before CmpInstr.
3691  // If the definition is in this basic block, RE points to the definition;
3692  // otherwise, RE is the rend of the basic block.
3694  RI = ++I.getReverse(),
3695  RE = CmpInstr.getParent() == MI->getParent()
3696  ? Def.getReverse() /* points to MI */
3697  : CmpInstr.getParent()->rend();
3698  MachineInstr *Movr0Inst = nullptr;
3699  for (; RI != RE; ++RI) {
3700  MachineInstr &Instr = *RI;
3701  // Check whether CmpInstr can be made redundant by the current instruction.
3702  if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3703  CmpValue, Instr)) {
3704  Sub = &Instr;
3705  break;
3706  }
3707 
3708  if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3709  Instr.readsRegister(X86::EFLAGS, TRI)) {
3710  // This instruction modifies or uses EFLAGS.
3711 
3712  // MOV32r0 etc. are implemented with xor which clobbers condition code.
3713  // They are safe to move up, if the definition to EFLAGS is dead and
3714  // earlier instructions do not read or write EFLAGS.
3715  if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3716  Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3717  Movr0Inst = &Instr;
3718  continue;
3719  }
3720 
3721  // We can't remove CmpInstr.
3722  return false;
3723  }
3724  }
3725 
3726  // Return false if no candidates exist.
3727  if (!IsCmpZero && !Sub)
3728  return false;
3729 
3730  bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3731  Sub->getOperand(2).getReg() == SrcReg);
3732 
3733  // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3734  // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3735  // If we are done with the basic block, we need to check whether EFLAGS is
3736  // live-out.
3737  bool IsSafe = false;
3738  SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3739  MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3740  for (++I; I != E; ++I) {
3741  const MachineInstr &Instr = *I;
3742  bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3743  bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3744  // We should check the usage if this instruction uses and updates EFLAGS.
3745  if (!UseEFLAGS && ModifyEFLAGS) {
3746  // It is safe to remove CmpInstr if EFLAGS is updated again.
3747  IsSafe = true;
3748  break;
3749  }
3750  if (!UseEFLAGS && !ModifyEFLAGS)
3751  continue;
3752 
3753  // EFLAGS is used by this instruction.
3755  bool OpcIsSET = false;
3756  if (IsCmpZero || IsSwapped) {
3757  // We decode the condition code from opcode.
3758  if (Instr.isBranch())
3759  OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
3760  else {
3761  OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
3762  if (OldCC != X86::COND_INVALID)
3763  OpcIsSET = true;
3764  else
3765  OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3766  }
3767  if (OldCC == X86::COND_INVALID) return false;
3768  }
3769  X86::CondCode ReplacementCC = X86::COND_INVALID;
3770  if (IsCmpZero) {
3771  switch (OldCC) {
3772  default: break;
3773  case X86::COND_A: case X86::COND_AE:
3774  case X86::COND_B: case X86::COND_BE:
3775  case X86::COND_G: case X86::COND_GE:
3776  case X86::COND_L: case X86::COND_LE:
3777  case X86::COND_O: case X86::COND_NO:
3778  // CF and OF are used, we can't perform this optimization.
3779  return false;
3780  }
3781 
3782  // If we're updating the condition code check if we have to reverse the
3783  // condition.
3784  if (ShouldUpdateCC)
3785  switch (OldCC) {
3786  default:
3787  return false;
3788  case X86::COND_E:
3789  ReplacementCC = NewCC;
3790  break;
3791  case X86::COND_NE:
3792  ReplacementCC = GetOppositeBranchCondition(NewCC);
3793  break;
3794  }
3795  } else if (IsSwapped) {
3796  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3797  // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3798  // We swap the condition code and synthesize the new opcode.
3799  ReplacementCC = getSwappedCondition(OldCC);
3800  if (ReplacementCC == X86::COND_INVALID) return false;
3801  }
3802 
3803  if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3804  // Synthesize the new opcode.
3805  bool HasMemoryOperand = Instr.hasOneMemOperand();
3806  unsigned NewOpc;
3807  if (Instr.isBranch())
3808  NewOpc = GetCondBranchFromCond(ReplacementCC);
3809  else if(OpcIsSET)
3810  NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand);
3811  else {
3812  unsigned DstReg = Instr.getOperand(0).getReg();
3813  const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
3814  NewOpc = getCMovFromCond(ReplacementCC, TRI->getRegSizeInBits(*DstRC)/8,
3815  HasMemoryOperand);
3816  }
3817 
3818  // Push the MachineInstr to OpsToUpdate.
3819  // If it is safe to remove CmpInstr, the condition code of these
3820  // instructions will be modified.
3821  OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3822  }
3823  if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3824  // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3825  IsSafe = true;
3826  break;
3827  }
3828  }
3829 
3830  // If EFLAGS is not killed nor re-defined, we should check whether it is
3831  // live-out. If it is live-out, do not optimize.
3832  if ((IsCmpZero || IsSwapped) && !IsSafe) {
3833  MachineBasicBlock *MBB = CmpInstr.getParent();
3834  for (MachineBasicBlock *Successor : MBB->successors())
3835  if (Successor->isLiveIn(X86::EFLAGS))
3836  return false;
3837  }
3838 
3839  // The instruction to be updated is either Sub or MI.
3840  Sub = IsCmpZero ? MI : Sub;
3841  // Move Movr0Inst to the appropriate place before Sub.
3842  if (Movr0Inst) {
3843  // Look backwards until we find a def that doesn't use the current EFLAGS.
3844  Def = Sub;
3846  InsertE = Sub->getParent()->rend();
3847  for (; InsertI != InsertE; ++InsertI) {
3848  MachineInstr *Instr = &*InsertI;
3849  if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3850  Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3851  Sub->getParent()->remove(Movr0Inst);
3852  Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3853  Movr0Inst);
3854  break;
3855  }
3856  }
3857  if (InsertI == InsertE)
3858  return false;
3859  }
3860 
3861  // Make sure Sub instruction defines EFLAGS and mark the def live.
3862  unsigned i = 0, e = Sub->getNumOperands();
3863  for (; i != e; ++i) {
3864  MachineOperand &MO = Sub->getOperand(i);
3865  if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3866  MO.setIsDead(false);
3867  break;
3868  }
3869  }
3870  assert(i != e && "Unable to locate a def EFLAGS operand");
3871 
3872  CmpInstr.eraseFromParent();
3873 
3874  // Modify the condition code of instructions in OpsToUpdate.
3875  for (auto &Op : OpsToUpdate)
3876  Op.first->setDesc(get(Op.second));
3877  return true;
3878 }
3879 
3880 /// Try to remove the load by folding it to a register
3881 /// operand at the use. We fold the load instructions if load defines a virtual
3882 /// register, the virtual register is used once in the same BB, and the
3883 /// instructions in-between do not load or store, and have no side effects.
3885  const MachineRegisterInfo *MRI,
3886  unsigned &FoldAsLoadDefReg,
3887  MachineInstr *&DefMI) const {
3888  // Check whether we can move DefMI here.
3889  DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3890  assert(DefMI);
3891  bool SawStore = false;
3892  if (!DefMI->isSafeToMove(nullptr, SawStore))
3893  return nullptr;
3894 
3895  // Collect information about virtual register operands of MI.
3896  SmallVector<unsigned, 1> SrcOperandIds;
3897  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3898  MachineOperand &MO = MI.getOperand(i);
3899  if (!MO.isReg())
3900  continue;
3901  unsigned Reg = MO.getReg();
3902  if (Reg != FoldAsLoadDefReg)
3903  continue;
3904  // Do not fold if we have a subreg use or a def.
3905  if (MO.getSubReg() || MO.isDef())
3906  return nullptr;
3907  SrcOperandIds.push_back(i);
3908  }
3909  if (SrcOperandIds.empty())
3910  return nullptr;
3911 
3912  // Check whether we can fold the def into SrcOperandId.
3913  if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3914  FoldAsLoadDefReg = 0;
3915  return FoldMI;
3916  }
3917 
3918  return nullptr;
3919 }
3920 
3921 /// Expand a single-def pseudo instruction to a two-addr
3922 /// instruction with two undef reads of the register being defined.
3923 /// This is used for mapping:
3924 /// %xmm4 = V_SET0
3925 /// to:
3926 /// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3927 ///
3929  const MCInstrDesc &Desc) {
3930  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3931  unsigned Reg = MIB->getOperand(0).getReg();
3932  MIB->setDesc(Desc);
3933 
3934  // MachineInstr::addOperand() will insert explicit operands before any
3935  // implicit operands.
3936  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3937  // But we don't trust that.
3938  assert(MIB->getOperand(1).getReg() == Reg &&
3939  MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3940  return true;
3941 }
3942 
3943 /// Expand a single-def pseudo instruction to a two-addr
3944 /// instruction with two %k0 reads.
3945 /// This is used for mapping:
3946 /// %k4 = K_SET1
3947 /// to:
3948 /// %k4 = KXNORrr %k0, %k0
3950  const MCInstrDesc &Desc, unsigned Reg) {
3951  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3952  MIB->setDesc(Desc);
3953  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3954  return true;
3955 }
3956 
3958  bool MinusOne) {
3959  MachineBasicBlock &MBB = *MIB->getParent();
3960  DebugLoc DL = MIB->getDebugLoc();
3961  unsigned Reg = MIB->getOperand(0).getReg();
3962 
3963  // Insert the XOR.
3964  BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3965  .addReg(Reg, RegState::Undef)
3966  .addReg(Reg, RegState::Undef);
3967 
3968  // Turn the pseudo into an INC or DEC.
3969  MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3970  MIB.addReg(Reg);
3971 
3972  return true;
3973 }
3974 
3976  const TargetInstrInfo &TII,
3977  const X86Subtarget &Subtarget) {
3978  MachineBasicBlock &MBB = *MIB->getParent();
3979  DebugLoc DL = MIB->getDebugLoc();
3980  int64_t Imm = MIB->getOperand(1).getImm();
3981  assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3983 
3984  int StackAdjustment;
3985 
3986  if (Subtarget.is64Bit()) {
3987  assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3988  MIB->getOpcode() == X86::MOV32ImmSExti8);
3989 
3990  // Can't use push/pop lowering if the function might write to the red zone.
3991  X86MachineFunctionInfo *X86FI =
3993  if (X86FI->getUsesRedZone()) {
3994  MIB->setDesc(TII.get(MIB->getOpcode() ==
3995  X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3996  return true;
3997  }
3998 
3999  // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4000  // widen the register if necessary.
4001  StackAdjustment = 8;
4002  BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4003  MIB->setDesc(TII.get(X86::POP64r));
4004  MIB->getOperand(0)
4006  } else {
4007  assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4008  StackAdjustment = 4;
4009  BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4010  MIB->setDesc(TII.get(X86::POP32r));
4011  }
4012 
4013  // Build CFI if necessary.
4014  MachineFunction &MF = *MBB.getParent();
4015  const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4016  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4017  bool NeedsDwarfCFI =
4018  !IsWin64Prologue &&
4020  bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4021  if (EmitCFI) {
4022  TFL->BuildCFI(MBB, I, DL,
4023  MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4024  TFL->BuildCFI(MBB, std::next(I), DL,
4025  MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4026  }
4027 
4028  return true;
4029 }
4030 
4031 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4032 // code sequence is needed for other targets.
4034  const TargetInstrInfo &TII) {
4035  MachineBasicBlock &MBB = *MIB->getParent();
4036  DebugLoc DL = MIB->getDebugLoc();
4037  unsigned Reg = MIB->getOperand(0).getReg();
4038  const GlobalValue *GV =
4039  cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4040  auto Flags = MachineMemOperand::MOLoad |
4044  MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
4046 
4047  BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4049  .addMemOperand(MMO);
4050  MIB->setDebugLoc(DL);
4051  MIB->setDesc(TII.get(X86::MOV64rm));
4052  MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4053 }
4054 
4056  MachineBasicBlock &MBB = *MIB->getParent();
4057  MachineFunction &MF = *MBB.getParent();
4058  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4059  const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4060  unsigned XorOp =
4061  MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4062  MIB->setDesc(TII.get(XorOp));
4063  MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4064  return true;
4065 }
4066 
4067 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4068 // but not VLX. If it uses an extended register we need to use an instruction
4069 // that loads the lower 128/256-bit, but is available with only AVX512F.
4071  const TargetRegisterInfo *TRI,
4072  const MCInstrDesc &LoadDesc,
4073  const MCInstrDesc &BroadcastDesc,
4074  unsigned SubIdx) {
4075  unsigned DestReg = MIB->getOperand(0).getReg();
4076  // Check if DestReg is XMM16-31 or YMM16-31.
4077  if (TRI->getEncodingValue(DestReg) < 16) {
4078  // We can use a normal VEX encoded load.
4079  MIB->setDesc(LoadDesc);
4080  } else {
4081  // Use a 128/256-bit VBROADCAST instruction.
4082  MIB->setDesc(BroadcastDesc);
4083  // Change the destination to a 512-bit register.
4084  DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4085  MIB->getOperand(0).setReg(DestReg);
4086  }
4087  return true;
4088 }
4089 
4090 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4091 // but not VLX. If it uses an extended register we need to use an instruction
4092 // that stores the lower 128/256-bit, but is available with only AVX512F.
4094  const TargetRegisterInfo *TRI,
4095  const MCInstrDesc &StoreDesc,
4096  const MCInstrDesc &ExtractDesc,
4097  unsigned SubIdx) {
4098  unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4099  // Check if DestReg is XMM16-31 or YMM16-31.
4100  if (TRI->getEncodingValue(SrcReg) < 16) {
4101  // We can use a normal VEX encoded store.
4102  MIB->setDesc(StoreDesc);
4103  } else {
4104  // Use a VEXTRACTF instruction.
4105  MIB->setDesc(ExtractDesc);
4106  // Change the destination to a 512-bit register.
4107  SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4108  MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4109  MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4110  }
4111 
4112  return true;
4113 }
4115  bool HasAVX = Subtarget.hasAVX();
4116  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4117  switch (MI.getOpcode()) {
4118  case X86::MOV32r0:
4119  return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4120  case X86::MOV32r1:
4121  return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4122  case X86::MOV32r_1:
4123  return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4124  case X86::MOV32ImmSExti8:
4125  case X86::MOV64ImmSExti8:
4126  return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4127  case X86::SETB_C8r:
4128  return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4129  case X86::SETB_C16r:
4130  return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4131  case X86::SETB_C32r:
4132  return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4133  case X86::SETB_C64r:
4134  return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4135  case X86::MMX_SET0:
4136  return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4137  case X86::V_SET0:
4138  case X86::FsFLD0SS:
4139  case X86::FsFLD0SD:
4140  return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4141  case X86::AVX_SET0: {
4142  assert(HasAVX && "AVX not supported");
4144  unsigned SrcReg = MIB->getOperand(0).getReg();
4145  unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4146  MIB->getOperand(0).setReg(XReg);
4147  Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4148  MIB.addReg(SrcReg, RegState::ImplicitDefine);
4149  return true;
4150  }
4151  case X86::AVX512_128_SET0:
4152  case X86::AVX512_FsFLD0SS:
4153  case X86::AVX512_FsFLD0SD: {
4154  bool HasVLX = Subtarget.hasVLX();
4155  unsigned SrcReg = MIB->getOperand(0).getReg();
4157  if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4158  return Expand2AddrUndef(MIB,
4159  get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4160  // Extended register without VLX. Use a larger XOR.
4161  SrcReg =
4162  TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4163  MIB->getOperand(0).setReg(SrcReg);
4164  return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4165  }
4166  case X86::AVX512_256_SET0:
4167  case X86::AVX512_512_SET0: {
4168  bool HasVLX = Subtarget.hasVLX();
4169  unsigned SrcReg = MIB->getOperand(0).getReg();
4171  if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4172  unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4173  MIB->getOperand(0).setReg(XReg);
4174  Expand2AddrUndef(MIB,
4175  get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4176  MIB.addReg(SrcReg, RegState::ImplicitDefine);
4177  return true;
4178  }
4179  return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4180  }
4181  case X86::V_SETALLONES:
4182  return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4183  case X86::AVX2_SETALLONES:
4184  return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4185  case X86::AVX1_SETALLONES: {
4186  unsigned Reg = MIB->getOperand(0).getReg();
4187  // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4188  MIB->setDesc(get(X86::VCMPPSYrri));
4189  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4190  return true;
4191  }
4192  case X86::AVX512_512_SETALLONES: {
4193  unsigned Reg = MIB->getOperand(0).getReg();
4194  MIB->setDesc(get(X86::VPTERNLOGDZrri));
4195  // VPTERNLOGD needs 3 register inputs and an immediate.
4196  // 0xff will return 1s for any input.
4197  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4198  .addReg(Reg, RegState::Undef).addImm(0xff);
4199  return true;
4200  }
4201  case X86::AVX512_512_SEXT_MASK_32:
4202  case X86::AVX512_512_SEXT_MASK_64: {
4203  unsigned Reg = MIB->getOperand(0).getReg();
4204  unsigned MaskReg = MIB->getOperand(1).getReg();
4205  unsigned MaskState = getRegState(MIB->getOperand(1));
4206  unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4207  X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4208  MI.RemoveOperand(1);
4209  MIB->setDesc(get(Opc));
4210  // VPTERNLOG needs 3 register inputs and an immediate.
4211  // 0xff will return 1s for any input.
4212  MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4213  .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4214  return true;
4215  }
4216  case X86::VMOVAPSZ128rm_NOVLX:
4217  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4218  get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4219  case X86::VMOVUPSZ128rm_NOVLX:
4220  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4221  get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4222  case X86::VMOVAPSZ256rm_NOVLX:
4223  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4224  get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4225  case X86::VMOVUPSZ256rm_NOVLX:
4226  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4227  get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4228  case X86::VMOVAPSZ128mr_NOVLX:
4229  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4230  get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4231  case X86::VMOVUPSZ128mr_NOVLX:
4232  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4233  get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4234  case X86::VMOVAPSZ256mr_NOVLX:
4235  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4236  get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4237  case X86::VMOVUPSZ256mr_NOVLX:
4238  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4239  get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4240  case X86::MOV32ri64: {
4241  unsigned Reg = MIB->getOperand(0).getReg();
4242  unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4243  MI.setDesc(get(X86::MOV32ri));
4244  MIB->getOperand(0).setReg(Reg32);
4245  MIB.addReg(Reg, RegState::ImplicitDefine);
4246  return true;
4247  }
4248 
4249  // KNL does not recognize dependency-breaking idioms for mask registers,
4250  // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4251  // Using %k0 as the undef input register is a performance heuristic based
4252  // on the assumption that %k0 is used less frequently than the other mask
4253  // registers, since it is not usable as a write mask.
4254  // FIXME: A more advanced approach would be to choose the best input mask
4255  // register based on context.
4256  case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4257  case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4258  case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4259  case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4260  case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4261  case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4262  case TargetOpcode::LOAD_STACK_GUARD:
4263  expandLoadStackGuard(MIB, *this);
4264  return true;
4265  case X86::XOR64_FP:
4266  case X86::XOR32_FP:
4267  return expandXorFP(MIB, *this);
4268  }
4269  return false;
4270 }
4271 
4272 /// Return true for all instructions that only update
4273 /// the first 32 or 64-bits of the destination register and leave the rest
4274 /// unmodified. This can be used to avoid folding loads if the instructions
4275 /// only update part of the destination register, and the non-updated part is
4276 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4277 /// instructions breaks the partial register dependency and it can improve
4278 /// performance. e.g.:
4279 ///
4280 /// movss (%rdi), %xmm0
4281 /// cvtss2sd %xmm0, %xmm0
4282 ///
4283 /// Instead of
4284 /// cvtss2sd (%rdi), %xmm0
4285 ///
4286 /// FIXME: This should be turned into a TSFlags.
4287 ///
4288 static bool hasPartialRegUpdate(unsigned Opcode,
4289  const X86Subtarget &Subtarget) {
4290  switch (Opcode) {
4291  case X86::CVTSI2SSrr:
4292  case X86::CVTSI2SSrm:
4293  case X86::CVTSI642SSrr:
4294  case X86::CVTSI642SSrm:
4295  case X86::CVTSI2SDrr:
4296  case X86::CVTSI2SDrm:
4297  case X86::CVTSI642SDrr:
4298  case X86::CVTSI642SDrm:
4299  case X86::CVTSD2SSrr:
4300  case X86::CVTSD2SSrm:
4301  case X86::CVTSS2SDrr:
4302  case X86::CVTSS2SDrm:
4303  case X86::MOVHPDrm:
4304  case X86::MOVHPSrm:
4305  case X86::MOVLPDrm:
4306  case X86::MOVLPSrm:
4307  case X86::RCPSSr:
4308  case X86::RCPSSm:
4309  case X86::RCPSSr_Int:
4310  case X86::RCPSSm_Int:
4311  case X86::ROUNDSDr:
4312  case X86::ROUNDSDm:
4313  case X86::ROUNDSSr:
4314  case X86::ROUNDSSm:
4315  case X86::RSQRTSSr:
4316  case X86::RSQRTSSm:
4317  case X86::RSQRTSSr_Int:
4318  case X86::RSQRTSSm_Int:
4319  case X86::SQRTSSr:
4320  case X86::SQRTSSm:
4321  case X86::SQRTSSr_Int:
4322  case X86::SQRTSSm_Int:
4323  case X86::SQRTSDr:
4324  case X86::SQRTSDm:
4325  case X86::SQRTSDr_Int:
4326  case X86::SQRTSDm_Int:
4327  return true;
4328  // GPR
4329  case X86::POPCNT32rm:
4330  case X86::POPCNT32rr:
4331  case X86::POPCNT64rm:
4332  case X86::POPCNT64rr:
4333  return Subtarget.hasPOPCNTFalseDeps();
4334  case X86::LZCNT32rm:
4335  case X86::LZCNT32rr:
4336  case X86::LZCNT64rm:
4337  case X86::LZCNT64rr:
4338  case X86::TZCNT32rm:
4339  case X86::TZCNT32rr:
4340  case X86::TZCNT64rm:
4341  case X86::TZCNT64rr:
4342  return Subtarget.hasLZCNTFalseDeps();
4343  }
4344 
4345  return false;
4346 }
4347 
4348 /// Inform the BreakFalseDeps pass how many idle
4349 /// instructions we would like before a partial register update.
4351  const MachineInstr &MI, unsigned OpNum,
4352  const TargetRegisterInfo *TRI) const {
4353  if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4354  return 0;
4355 
4356  // If MI is marked as reading Reg, the partial register update is wanted.
4357  const MachineOperand &MO = MI.getOperand(0);
4358  unsigned Reg = MO.getReg();
4360  if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4361  return 0;
4362  } else {
4363  if (MI.readsRegister(Reg, TRI))
4364  return 0;
4365  }
4366 
4367  // If any instructions in the clearance range are reading Reg, insert a
4368  // dependency breaking instruction, which is inexpensive and is likely to
4369  // be hidden in other instruction's cycles.
4371 }
4372 
4373 // Return true for any instruction the copies the high bits of the first source
4374 // operand into the unused high bits of the destination operand.
4375 static bool hasUndefRegUpdate(unsigned Opcode) {
4376  switch (Opcode) {
4377  case X86::VCVTSI2SSrr:
4378  case X86::VCVTSI2SSrm:
4379  case X86::VCVTSI2SSrr_Int:
4380  case X86::VCVTSI2SSrm_Int:
4381  case X86::VCVTSI642SSrr:
4382  case X86::VCVTSI642SSrm:
4383  case X86::VCVTSI642SSrr_Int:
4384  case X86::VCVTSI642SSrm_Int:
4385  case X86::VCVTSI2SDrr:
4386  case X86::VCVTSI2SDrm:
4387  case X86::VCVTSI2SDrr_Int:
4388  case X86::VCVTSI2SDrm_Int:
4389  case X86::VCVTSI642SDrr:
4390  case X86::VCVTSI642SDrm:
4391  case X86::VCVTSI642SDrr_Int:
4392  case X86::VCVTSI642SDrm_Int:
4393  case X86::VCVTSD2SSrr:
4394  case X86::VCVTSD2SSrm:
4395  case X86::VCVTSD2SSrr_Int:
4396  case X86::VCVTSD2SSrm_Int:
4397  case X86::VCVTSS2SDrr:
4398  case X86::VCVTSS2SDrm:
4399  case X86::VCVTSS2SDrr_Int:
4400  case X86::VCVTSS2SDrm_Int:
4401  case X86::VRCPSSr:
4402  case X86::VRCPSSr_Int:
4403  case X86::VRCPSSm:
4404  case X86::VRCPSSm_Int:
4405  case X86::VROUNDSDr:
4406  case X86::VROUNDSDm:
4407  case X86::VROUNDSDr_Int:
4408  case X86::VROUNDSDm_Int:
4409  case X86::VROUNDSSr:
4410  case X86::VROUNDSSm:
4411  case X86::VROUNDSSr_Int:
4412  case X86::VROUNDSSm_Int:
4413  case X86::VRSQRTSSr:
4414  case X86::VRSQRTSSr_Int:
4415  case X86::VRSQRTSSm:
4416  case X86::VRSQRTSSm_Int:
4417  case X86::VSQRTSSr:
4418  case X86::VSQRTSSr_Int:
4419  case X86::VSQRTSSm:
4420  case X86::VSQRTSSm_Int:
4421  case X86::VSQRTSDr:
4422  case X86::VSQRTSDr_Int:
4423  case X86::VSQRTSDm:
4424  case X86::VSQRTSDm_Int:
4425  // AVX-512
4426  case X86::VCVTSI2SSZrr:
4427  case X86::VCVTSI2SSZrm:
4428  case X86::VCVTSI2SSZrr_Int:
4429  case X86::VCVTSI2SSZrrb_Int:
4430  case X86::VCVTSI2SSZrm_Int:
4431  case X86::VCVTSI642SSZrr:
4432  case X86::VCVTSI642SSZrm:
4433  case X86::VCVTSI642SSZrr_Int:
4434  case X86::VCVTSI642SSZrrb_Int:
4435  case X86::VCVTSI642SSZrm_Int:
4436  case X86::VCVTSI2SDZrr:
4437  case X86::VCVTSI2SDZrm:
4438  case X86::VCVTSI2SDZrr_Int:
4439  case X86::VCVTSI2SDZrrb_Int:
4440  case X86::VCVTSI2SDZrm_Int:
4441  case X86::VCVTSI642SDZrr:
4442  case X86::VCVTSI642SDZrm:
4443  case X86::VCVTSI642SDZrr_Int:
4444  case X86::VCVTSI642SDZrrb_Int:
4445  case X86::VCVTSI642SDZrm_Int:
4446  case X86::VCVTUSI2SSZrr:
4447  case X86::VCVTUSI2SSZrm:
4448  case X86::VCVTUSI2SSZrr_Int:
4449  case X86::VCVTUSI2SSZrrb_Int:
4450  case X86::VCVTUSI2SSZrm_Int:
4451  case X86::VCVTUSI642SSZrr:
4452  case X86::VCVTUSI642SSZrm:
4453  case X86::VCVTUSI642SSZrr_Int:
4454  case X86::VCVTUSI642SSZrrb_Int:
4455  case X86::VCVTUSI642SSZrm_Int:
4456  case X86::VCVTUSI2SDZrr:
4457  case X86::VCVTUSI2SDZrm:
4458  case X86::VCVTUSI2SDZrr_Int:
4459  case X86::VCVTUSI2SDZrm_Int:
4460  case X86::VCVTUSI642SDZrr:
4461  case X86::VCVTUSI642SDZrm:
4462  case X86::VCVTUSI642SDZrr_Int:
4463  case X86::VCVTUSI642SDZrrb_Int:
4464  case X86::VCVTUSI642SDZrm_Int:
4465  case X86::VCVTSD2SSZrr:
4466  case X86::VCVTSD2SSZrr_Int:
4467  case X86::VCVTSD2SSZrrb_Int:
4468  case X86::VCVTSD2SSZrm:
4469  case X86::VCVTSD2SSZrm_Int:
4470  case X86::VCVTSS2SDZrr:
4471  case X86::VCVTSS2SDZrr_Int:
4472  case X86::VCVTSS2SDZrrb_Int:
4473  case X86::VCVTSS2SDZrm:
4474  case X86::VCVTSS2SDZrm_Int:
4475  case X86::VGETEXPSDZr:
4476  case X86::VGETEXPSDZrb:
4477  case X86::VGETEXPSDZm:
4478  case X86::VGETEXPSSZr:
4479  case X86::VGETEXPSSZrb:
4480  case X86::VGETEXPSSZm:
4481  case X86::VGETMANTSDZrri:
4482  case X86::VGETMANTSDZrrib:
4483  case X86::VGETMANTSDZrmi:
4484  case X86::VGETMANTSSZrri:
4485  case X86::VGETMANTSSZrrib:
4486  case X86::VGETMANTSSZrmi:
4487  case X86::VRNDSCALESDZr:
4488  case X86::VRNDSCALESDZr_Int:
4489  case X86::VRNDSCALESDZrb_Int:
4490  case X86::VRNDSCALESDZm:
4491  case X86::VRNDSCALESDZm_Int:
4492  case X86::VRNDSCALESSZr:
4493  case X86::VRNDSCALESSZr_Int:
4494  case X86::VRNDSCALESSZrb_Int:
4495  case X86::VRNDSCALESSZm:
4496  case X86::VRNDSCALESSZm_Int:
4497  case X86::VRCP14SDZrr:
4498  case X86::VRCP14SDZrm:
4499  case X86::VRCP14SSZrr:
4500  case X86::VRCP14SSZrm:
4501  case X86::VRCP28SDZr:
4502  case X86::VRCP28SDZrb:
4503  case X86::VRCP28SDZm:
4504  case X86::VRCP28SSZr:
4505  case X86::VRCP28SSZrb:
4506  case X86::VRCP28SSZm:
4507  case X86::VREDUCESSZrmi:
4508  case X86::VREDUCESSZrri:
4509  case X86::VREDUCESSZrrib:
4510  case X86::VRSQRT14SDZrr:
4511  case X86::VRSQRT14SDZrm:
4512  case X86::VRSQRT14SSZrr:
4513  case X86::VRSQRT14SSZrm:
4514  case X86::VRSQRT28SDZr:
4515  case X86::VRSQRT28SDZrb:
4516  case X86::VRSQRT28SDZm:
4517  case X86::VRSQRT28SSZr:
4518  case X86::VRSQRT28SSZrb:
4519  case X86::VRSQRT28SSZm:
4520  case X86::VSQRTSSZr:
4521  case X86::VSQRTSSZr_Int:
4522  case X86::VSQRTSSZrb_Int:
4523  case X86::VSQRTSSZm:
4524  case X86::VSQRTSSZm_Int:
4525  case X86::VSQRTSDZr:
4526  case X86::VSQRTSDZr_Int:
4527  case X86::VSQRTSDZrb_Int:
4528  case X86::VSQRTSDZm:
4529  case X86::VSQRTSDZm_Int:
4530  return true;
4531  }
4532 
4533  return false;
4534 }
4535 
4536 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4537 /// before certain undef register reads.
4538 ///
4539 /// This catches the VCVTSI2SD family of instructions:
4540 ///
4541 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4542 ///
4543 /// We should to be careful *not* to catch VXOR idioms which are presumably
4544 /// handled specially in the pipeline:
4545 ///
4546 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4547 ///
4548 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4549 /// high bits that are passed-through are not live.
4550 unsigned
4552  const TargetRegisterInfo *TRI) const {
4553  if (!hasUndefRegUpdate(MI.getOpcode()))
4554  return 0;
4555 
4556  // Set the OpNum parameter to the first source operand.
4557  OpNum = 1;
4558 
4559  const MachineOperand &MO = MI.getOperand(OpNum);
4561  return UndefRegClearance;
4562  }
4563  return 0;
4564 }
4565 
4567  MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4568  unsigned Reg = MI.getOperand(OpNum).getReg();
4569  // If MI kills this register, the false dependence is already broken.
4570  if (MI.killsRegister(Reg, TRI))
4571  return;
4572 
4573  if (X86::VR128RegClass.contains(Reg)) {
4574  // These instructions are all floating point domain, so xorps is the best
4575  // choice.
4576  unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4577  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4578  .addReg(Reg, RegState::Undef)
4579  .addReg(Reg, RegState::Undef);
4580  MI.addRegisterKilled(Reg, TRI, true);
4581  } else if (X86::VR256RegClass.contains(Reg)) {
4582  // Use vxorps to clear the full ymm register.
4583  // It wants to read and write the xmm sub-register.
4584  unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4585  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4586  .addReg(XReg, RegState::Undef)
4587  .addReg(XReg, RegState::Undef)
4589  MI.addRegisterKilled(Reg, TRI, true);
4590  } else if (X86::GR64RegClass.contains(Reg)) {
4591  // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4592  // as well.
4593  unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4594  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4595  .addReg(XReg, RegState::Undef)
4596  .addReg(XReg, RegState::Undef)
4598  MI.addRegisterKilled(Reg, TRI, true);
4599  } else if (X86::GR32RegClass.contains(Reg)) {
4600  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4601  .addReg(Reg, RegState::Undef)
4602  .addReg(Reg, RegState::Undef);
4603  MI.addRegisterKilled(Reg, TRI, true);
4604  }
4605 }
4606 
4608  int PtrOffset = 0) {
4609  unsigned NumAddrOps = MOs.size();
4610 
4611  if (NumAddrOps < 4) {
4612  // FrameIndex only - add an immediate offset (whether its zero or not).
4613  for (unsigned i = 0; i != NumAddrOps; ++i)
4614  MIB.add(MOs[i]);
4615  addOffset(MIB, PtrOffset);
4616  } else {
4617  // General Memory Addressing - we need to add any offset to an existing
4618  // offset.
4619  assert(MOs.size() == 5 && "Unexpected memory operand list length");
4620  for (unsigned i = 0; i != NumAddrOps; ++i) {
4621  const MachineOperand &MO = MOs[i];
4622  if (i == 3 && PtrOffset != 0) {
4623  MIB.addDisp(MO, PtrOffset);
4624  } else {
4625  MIB.add(MO);
4626  }
4627  }
4628  }
4629 }
4630 
4632  MachineInstr &NewMI,
4633  const TargetInstrInfo &TII) {
4636 
4637  for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4638  MachineOperand &MO = NewMI.getOperand(Idx);
4639  // We only need to update constraints on virtual register operands.
4640  if (!MO.isReg())
4641  continue;
4642  unsigned Reg = MO.getReg();
4643  if (!TRI.isVirtualRegister(Reg))
4644  continue;
4645 
4646  auto *NewRC = MRI.constrainRegClass(
4647  Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4648  if (!NewRC) {
4649  LLVM_DEBUG(
4650  dbgs() << "WARNING: Unable to update register constraint for operand "
4651  << Idx << " of instruction:\n";
4652  NewMI.dump(); dbgs() << "\n");
4653  }
4654  }
4655 }
4656 
4657 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4659  MachineBasicBlock::iterator InsertPt,
4660  MachineInstr &MI,
4661  const TargetInstrInfo &TII) {
4662  // Create the base instruction with the memory operand as the first part.
4663  // Omit the implicit operands, something BuildMI can't do.
4664  MachineInstr *NewMI =
4665  MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4666  MachineInstrBuilder MIB(MF, NewMI);
4667  addOperands(MIB, MOs);
4668 
4669  // Loop over the rest of the ri operands, converting them over.
4670  unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4671  for (unsigned i = 0; i != NumOps; ++i) {
4672  MachineOperand &MO = MI.getOperand(i + 2);
4673  MIB.add(MO);
4674  }
4675  for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4676  MachineOperand &MO = MI.getOperand(i);
4677  MIB.add(MO);
4678  }
4679 
4680  updateOperandRegConstraints(MF, *NewMI, TII);
4681 
4682  MachineBasicBlock *MBB = InsertPt->getParent();
4683  MBB->insert(InsertPt, NewMI);
4684 
4685  return MIB;
4686 }
4687 
4688 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4689  unsigned OpNo, ArrayRef<MachineOperand> MOs,
4690  MachineBasicBlock::iterator InsertPt,
4691  MachineInstr &MI, const TargetInstrInfo &TII,
4692  int PtrOffset = 0) {
4693  // Omit the implicit operands, something BuildMI can't do.
4694  MachineInstr *NewMI =
4695  MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4696  MachineInstrBuilder MIB(MF, NewMI);
4697 
4698  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4699  MachineOperand &MO = MI.getOperand(i);
4700  if (i == OpNo) {
4701  assert(MO.isReg() && "Expected to fold into reg operand!");
4702  addOperands(MIB, MOs, PtrOffset);
4703  } else {
4704  MIB.add(MO);
4705  }
4706  }
4707 
4708  updateOperandRegConstraints(MF, *NewMI, TII);
4709 
4710  MachineBasicBlock *MBB = InsertPt->getParent();
4711  MBB->insert(InsertPt, NewMI);
4712 
4713  return MIB;
4714 }
4715 
4716 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4718  MachineBasicBlock::iterator InsertPt,
4719  MachineInstr &MI) {
4720  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4721  MI.getDebugLoc(), TII.get(Opcode));
4722  addOperands(MIB, MOs);
4723  return MIB.addImm(0);
4724 }
4725 
4726 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4727  MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4729  unsigned Size, unsigned Align) const {
4730  switch (MI.getOpcode()) {
4731  case X86::INSERTPSrr:
4732  case X86::VINSERTPSrr:
4733  case X86::VINSERTPSZrr:
4734  // Attempt to convert the load of inserted vector into a fold load
4735  // of a single float.
4736  if (OpNum == 2) {
4737  unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4738  unsigned ZMask = Imm & 15;
4739  unsigned DstIdx = (Imm >> 4) & 3;
4740  unsigned SrcIdx = (Imm >> 6) & 3;
4741 
4743  const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4744  unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4745  if (Size <= RCSize && 4 <= Align) {
4746  int PtrOffset = SrcIdx * 4;
4747  unsigned NewImm = (DstIdx << 4) | ZMask;
4748  unsigned NewOpCode =
4749  (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4750  (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4751  X86::INSERTPSrm;
4752  MachineInstr *NewMI =
4753  FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4754  NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4755  return NewMI;
4756  }
4757  }
4758  break;
4759  case X86::MOVHLPSrr:
4760  case X86::VMOVHLPSrr:
4761  case X86::VMOVHLPSZrr:
4762  // Move the upper 64-bits of the second operand to the lower 64-bits.
4763  // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4764  // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4765  if (OpNum == 2) {
4767  const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4768  unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4769  if (Size <= RCSize && 8 <= Align) {
4770  unsigned NewOpCode =
4771  (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4772  (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4773  X86::MOVLPSrm;
4774  MachineInstr *NewMI =
4775  FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4776  return NewMI;
4777  }
4778  }
4779  break;
4780  };
4781 
4782  return nullptr;
4783 }
4784 
4786  if (MF.getFunction().optForSize() || !hasUndefRegUpdate(MI.getOpcode()) ||
4787  !MI.getOperand(1).isReg())
4788  return false;
4789 
4790  // The are two cases we need to handle depending on where in the pipeline
4791  // the folding attempt is being made.
4792  // -Register has the undef flag set.
4793  // -Register is produced by the IMPLICIT_DEF instruction.
4794 
4795  if (MI.getOperand(1).isUndef())
4796  return true;
4797 
4798  MachineRegisterInfo &RegInfo = MF.getRegInfo();
4799  MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4800  return VRegDef && VRegDef->isImplicitDef();
4801 }
4802 
4803 
4805  MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4807  unsigned Size, unsigned Align, bool AllowCommute) const {
4808  bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4809  bool isTwoAddrFold = false;
4810 
4811  // For CPUs that favor the register form of a call or push,
4812  // do not fold loads into calls or pushes, unless optimizing for size
4813  // aggressively.
4814  if (isSlowTwoMemOps && !MF.getFunction().optForMinSize() &&
4815  (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4816  MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4817  MI.getOpcode() == X86::PUSH64r))
4818  return nullptr;
4819 
4820  // Avoid partial and undef register update stalls unless optimizing for size.
4821  if (!MF.getFunction().optForSize() &&
4822  (hasPartialRegUpdate(MI.getOpcode(), Subtarget) ||
4824  return nullptr;
4825 
4826  unsigned NumOps = MI.getDesc().getNumOperands();
4827  bool isTwoAddr =
4828  NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4829 
4830  // FIXME: AsmPrinter doesn't know how to handle
4831  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4832  if (MI.getOpcode() == X86::ADD32ri &&
4834  return nullptr;
4835 
4836  // GOTTPOFF relocation loads can only be folded into add instructions.
4837  // FIXME: Need to exclude other relocations that only support specific
4838  // instructions.
4839  if (MOs.size() == X86::AddrNumOperands &&
4840  MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4841  MI.getOpcode() != X86::ADD64rr)
4842  return nullptr;
4843 
4844  MachineInstr *NewMI = nullptr;
4845 
4846  // Attempt to fold any custom cases we have.
4847  if (MachineInstr *CustomMI =
4848  foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4849  return CustomMI;
4850 
4851  const X86MemoryFoldTableEntry *I = nullptr;
4852 
4853  // Folding a memory location into the two-address part of a two-address
4854  // instruction is different than folding it other places. It requires
4855  // replacing the *two* registers with the memory location.
4856  if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4857  MI.getOperand(1).isReg() &&
4858  MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4860  isTwoAddrFold = true;
4861  } else {
4862  if (OpNum == 0) {
4863  if (MI.getOpcode() == X86::MOV32r0) {
4864  NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4865  if (NewMI)
4866  return NewMI;
4867  }
4868  }
4869 
4870  I = lookupFoldTable(MI.getOpcode(), OpNum);
4871  }
4872 
4873  if (I != nullptr) {
4874  unsigned Opcode = I->DstOp;
4875  unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4876  if (Align < MinAlign)
4877  return nullptr;
4878  bool NarrowToMOV32rm = false;
4879  if (Size) {
4881  const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4882  &RI, MF);
4883  unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4884  if (Size < RCSize) {
4885  // Check if it's safe to fold the load. If the size of the object is
4886  // narrower than the load width, then it's not.
4887  if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4888  return nullptr;
4889  // If this is a 64-bit load, but the spill slot is 32, then we can do
4890  // a 32-bit load which is implicitly zero-extended. This likely is
4891  // due to live interval analysis remat'ing a load from stack slot.
4892  if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4893  return nullptr;
4894  Opcode = X86::MOV32rm;
4895  NarrowToMOV32rm = true;
4896  }
4897  }
4898 
4899  if (isTwoAddrFold)
4900  NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4901  else
4902  NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4903 
4904  if (NarrowToMOV32rm) {
4905  // If this is the special case where we use a MOV32rm to load a 32-bit
4906  // value and zero-extend the top bits. Change the destination register
4907  // to a 32-bit one.
4908  unsigned DstReg = NewMI->getOperand(0).getReg();
4910  NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4911  else
4912  NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4913  }
4914  return NewMI;
4915  }
4916 
4917  // If the instruction and target operand are commutable, commute the
4918  // instruction and try again.
4919  if (AllowCommute) {
4920  unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4921  if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4922  bool HasDef = MI.getDesc().getNumDefs();
4923  unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
4924  unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4925  unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4926  bool Tied1 =
4927  0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4928  bool Tied2 =
4929  0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4930 
4931  // If either of the commutable operands are tied to the destination
4932  // then we can not commute + fold.
4933  if ((HasDef && Reg0 == Reg1 && Tied1) ||
4934  (HasDef && Reg0 == Reg2 && Tied2))
4935  return nullptr;
4936 
4937  MachineInstr *CommutedMI =
4938  commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4939  if (!CommutedMI) {
4940  // Unable to commute.
4941  return nullptr;
4942  }
4943  if (CommutedMI != &MI) {
4944  // New instruction. We can't fold from this.
4945  CommutedMI->eraseFromParent();
4946  return nullptr;
4947  }
4948 
4949  // Attempt to fold with the commuted version of the instruction.
4950  NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4951  Size, Align, /*AllowCommute=*/false);
4952  if (NewMI)
4953  return NewMI;
4954 
4955  // Folding failed again - undo the commute before returning.
4956  MachineInstr *UncommutedMI =
4957  commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4958  if (!UncommutedMI) {
4959  // Unable to commute.
4960  return nullptr;
4961  }
4962  if (UncommutedMI != &MI) {
4963  // New instruction. It doesn't need to be kept.
4964  UncommutedMI->eraseFromParent();
4965  return nullptr;
4966  }
4967 
4968  // Return here to prevent duplicate fuse failure report.
4969  return nullptr;
4970  }
4971  }
4972 
4973  // No fusion
4974  if (PrintFailedFusing && !MI.isCopy())
4975  dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4976  return nullptr;
4977 }
4978 
4979 MachineInstr *
4981  ArrayRef<unsigned> Ops,
4982  MachineBasicBlock::iterator InsertPt,
4983  int FrameIndex, LiveIntervals *LIS) const {
4984  // Check switch flag
4985  if (NoFusing)
4986  return nullptr;
4987 
4988  // Avoid partial and undef register update stalls unless optimizing for size.
4989  if (!MF.getFunction().optForSize() &&
4990  (hasPartialRegUpdate(MI.getOpcode(), Subtarget) ||
4992  return nullptr;
4993 
4994  // Don't fold subreg spills, or reloads that use a high subreg.
4995  for (auto Op : Ops) {
4996  MachineOperand &MO = MI.getOperand(Op);
4997  auto SubReg = MO.getSubReg();
4998  if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
4999  return nullptr;
5000  }
5001 
5002  const MachineFrameInfo &MFI = MF.getFrameInfo();
5003  unsigned Size = MFI.getObjectSize(FrameIndex);
5004  unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
5005  // If the function stack isn't realigned we don't want to fold instructions
5006  // that need increased alignment.
5007  if (!RI.needsStackRealignment(MF))
5008  Alignment =
5009  std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5010  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5011  unsigned NewOpc = 0;
5012  unsigned RCSize = 0;
5013  switch (MI.getOpcode()) {
5014  default: return nullptr;
5015  case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5016  case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5017  case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5018  case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5019  }
5020  // Check if it's safe to fold the load. If the size of the object is
5021  // narrower than the load width, then it's not.
5022  if (Size < RCSize)
5023  return nullptr;
5024  // Change to CMPXXri r, 0 first.
5025  MI.setDesc(get(NewOpc));
5026  MI.getOperand(1).ChangeToImmediate(0);
5027  } else if (Ops.size() != 1)
5028  return nullptr;
5029 
5030  return foldMemoryOperandImpl(MF, MI, Ops[0],
5031  MachineOperand::CreateFI(FrameIndex), InsertPt,
5032  Size, Alignment, /*AllowCommute=*/true);
5033 }
5034 
5035 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5036 /// because the latter uses contents that wouldn't be defined in the folded
5037 /// version. For instance, this transformation isn't legal:
5038 /// movss (%rdi), %xmm0
5039 /// addps %xmm0, %xmm0
5040 /// ->
5041 /// addps (%rdi), %xmm0
5042 ///
5043 /// But this one is:
5044 /// movss (%rdi), %xmm0
5045 /// addss %xmm0, %xmm0
5046 /// ->
5047 /// addss (%rdi), %xmm0
5048 ///
5050  const MachineInstr &UserMI,
5051  const MachineFunction &MF) {
5052  unsigned Opc = LoadMI.getOpcode();
5053  unsigned UserOpc = UserMI.getOpcode();
5055  const TargetRegisterClass *RC =
5056  MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5057  unsigned RegSize = TRI.getRegSizeInBits(*RC);
5058 
5059  if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
5060  RegSize > 32) {
5061  // These instructions only load 32 bits, we can't fold them if the
5062  // destination register is wider than 32 bits (4 bytes), and its user
5063  // instruction isn't scalar (SS).
5064  switch (UserOpc) {
5065  case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5066  case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5067  case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5068  case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5069  case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5070  case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5071  case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5072  case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5073  case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5074  case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5075  case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5076  case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5077  case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5078  case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
5079  case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
5080  case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
5081  case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
5082  case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
5083  case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
5084  case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
5085  case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
5086  case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5087  case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5088  case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5089  case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5090  case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5091  case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5092  case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5093  case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5094  case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5095  case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5096  case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5097  case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5098  case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5099  case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5100  case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5101  case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5102  case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5103  case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5104  return false;
5105  default:
5106  return true;
5107  }
5108  }
5109 
5110  if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
5111  RegSize > 64) {
5112  // These instructions only load 64 bits, we can't fold them if the
5113  // destination register is wider than 64 bits (8 bytes), and its user
5114  // instruction isn't scalar (SD).
5115  switch (UserOpc) {
5116  case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5117  case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5118  case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5119  case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5120  case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5121  case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5122  case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5123  case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5124  case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5125  case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5126  case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5127  case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5128  case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5129  case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5130  case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5131  case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5132  case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5133  case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5134  case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5135  case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5136  case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5137  case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5138  case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5139  case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5140  case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5141  case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5142  case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5143  case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5144  case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5145  case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5146  case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5147  case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5148  case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5149  case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5150  case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5151  case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5152  case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5153  case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5154  case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5155  return false;
5156  default:
5157  return true;
5158  }
5159  }
5160 
5161  return false;
5162 }
5163 
5166  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5167  LiveIntervals *LIS) const {
5168 
5169  // TODO: Support the case where LoadMI loads a wide register, but MI
5170  // only uses a subreg.
5171  for (auto Op : Ops) {
5172  if (MI.getOperand(Op).getSubReg())
5173  return nullptr;
5174  }
5175 
5176  // If loading from a FrameIndex, fold directly from the FrameIndex.
5177  unsigned NumOps = LoadMI.getDesc().getNumOperands();
5178  int FrameIndex;
5179  if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5180  if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5181  return nullptr;
5182  return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5183  }
5184 
5185  // Check switch flag
5186  if (NoFusing) return nullptr;
5187 
5188  // Avoid partial and undef register update stalls unless optimizing for size.
5189  if (!MF.getFunction().optForSize() &&
5190  (hasPartialRegUpdate(MI.getOpcode(), Subtarget) ||
5192  return nullptr;
5193 
5194  // Determine the alignment of the load.
5195  unsigned Alignment = 0;
5196  if (LoadMI.hasOneMemOperand())
5197  Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5198  else
5199  switch (LoadMI.getOpcode()) {
5200  case X86::AVX512_512_SET0:
5201  case X86::AVX512_512_SETALLONES:
5202  Alignment = 64;
5203  break;
5204  case X86::AVX2_SETALLONES:
5205  case X86::AVX1_SETALLONES:
5206  case X86::AVX_SET0:
5207  case X86::AVX512_256_SET0:
5208  Alignment = 32;
5209  break;
5210  case X86::V_SET0:
5211  case X86::V_SETALLONES:
5212  case X86::AVX512_128_SET0:
5213  Alignment = 16;
5214  break;
5215  case X86::MMX_SET0:
5216  case X86::FsFLD0SD:
5217  case X86::AVX512_FsFLD0SD:
5218  Alignment = 8;
5219  break;
5220  case X86::FsFLD0SS:
5221  case X86::AVX512_FsFLD0SS:
5222  Alignment = 4;
5223  break;
5224  default:
5225  return nullptr;
5226  }
5227  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5228  unsigned NewOpc = 0;
5229  switch (MI.getOpcode()) {
5230  default: return nullptr;
5231  case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5232  case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5233  case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5234  case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5235  }
5236  // Change to CMPXXri r, 0 first.
5237  MI.setDesc(get(NewOpc));
5238  MI.getOperand(1).ChangeToImmediate(0);
5239  } else if (Ops.size() != 1)
5240  return nullptr;
5241 
5242  // Make sure the subregisters match.
5243  // Otherwise we risk changing the size of the load.
5244  if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5245  return nullptr;
5246 
5248  switch (LoadMI.getOpcode()) {
5249  case X86::MMX_SET0:
5250  case X86::V_SET0:
5251  case X86::V_SETALLONES:
5252  case X86::AVX2_SETALLONES:
5253  case X86::AVX1_SETALLONES:
5254  case X86::AVX_SET0:
5255  case X86::AVX512_128_SET0:
5256  case X86::AVX512_256_SET0:
5257  case X86::AVX512_512_SET0:
5258  case X86::AVX512_512_SETALLONES:
5259  case X86::FsFLD0SD:
5260  case X86::AVX512_FsFLD0SD:
5261  case X86::FsFLD0SS:
5262  case X86::AVX512_FsFLD0SS: {
5263  // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5264  // Create a constant-pool entry and operands to load from it.
5265 
5266  // Medium and large mode can't fold loads this way.
5267  if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5269  return nullptr;
5270 
5271  // x86-32 PIC requires a PIC base register for constant pools.
5272  unsigned PICBase = 0;
5273  if (MF.getTarget().isPositionIndependent()) {
5274  if (Subtarget.is64Bit())
5275  PICBase = X86::RIP;
5276  else
5277  // FIXME: PICBase = getGlobalBaseReg(&MF);
5278  // This doesn't work for several reasons.
5279  // 1. GlobalBaseReg may have been spilled.
5280  // 2. It may not be live at MI.
5281  return nullptr;
5282  }
5283 
5284  // Create a constant-pool entry.
5285  MachineConstantPool &MCP = *MF.getConstantPool();
5286  Type *Ty;
5287  unsigned Opc = LoadMI.getOpcode();
5288  if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5290  else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5292  else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5294  else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5295  Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5297  else if (Opc == X86::MMX_SET0)
5299  else
5301 
5302  bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5303  Opc == X86::AVX512_512_SETALLONES ||
5304  Opc == X86::AVX1_SETALLONES);
5305  const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5307  unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5308 
5309  // Create operands to load from the constant pool entry.
5310  MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5312  MOs.push_back(MachineOperand::CreateReg(0, false));
5313  MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5314  MOs.push_back(MachineOperand::CreateReg(0, false));
5315  break;
5316  }
5317  default: {
5318  if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5319  return nullptr;
5320 
5321  // Folding a normal load. Just copy the load's address operands.
5322  MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5323  LoadMI.operands_begin() + NumOps);
5324  break;
5325  }
5326  }
5327  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5328  /*Size=*/0, Alignment, /*AllowCommute=*/true);
5329 }
5330