LLVM  7.0.0svn
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/FoldingSet.h"
18 #include "llvm/ADT/Hashing.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Analysis/Loads.h"
40 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Metadata.h"
50 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Type.h"
53 #include "llvm/IR/Value.h"
54 #include "llvm/MC/MCInstrDesc.h"
55 #include "llvm/MC/MCRegisterInfo.h"
56 #include "llvm/MC/MCSymbol.h"
57 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/Compiler.h"
60 #include "llvm/Support/Debug.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cstddef>
70 #include <cstdint>
71 #include <cstring>
72 #include <iterator>
73 #include <utility>
74 
75 using namespace llvm;
76 
78  if (MCID->ImplicitDefs)
79  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
80  ++ImpDefs)
81  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
82  if (MCID->ImplicitUses)
83  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
84  ++ImpUses)
85  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
86 }
87 
88 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
89 /// implicit operands. It reserves space for the number of operands specified by
90 /// the MCInstrDesc.
91 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
92  DebugLoc dl, bool NoImp)
93  : MCID(&tid), debugLoc(std::move(dl)) {
94  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
95 
96  // Reserve space for the expected number of operands.
97  if (unsigned NumOps = MCID->getNumOperands() +
98  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
99  CapOperands = OperandCapacity::get(NumOps);
100  Operands = MF.allocateOperandArray(CapOperands);
101  }
102 
103  if (!NoImp)
105 }
106 
107 /// MachineInstr ctor - Copies MachineInstr arg exactly
108 ///
109 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
110  : MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
111  debugLoc(MI.getDebugLoc()) {
112  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
113 
114  CapOperands = OperandCapacity::get(MI.getNumOperands());
115  Operands = MF.allocateOperandArray(CapOperands);
116 
117  // Copy operands.
118  for (const MachineOperand &MO : MI.operands())
119  addOperand(MF, MO);
120 
121  // Copy all the sensible flags.
122  setFlags(MI.Flags);
123 }
124 
125 /// getRegInfo - If this instruction is embedded into a MachineFunction,
126 /// return the MachineRegisterInfo object for the current function, otherwise
127 /// return null.
128 MachineRegisterInfo *MachineInstr::getRegInfo() {
129  if (MachineBasicBlock *MBB = getParent())
130  return &MBB->getParent()->getRegInfo();
131  return nullptr;
132 }
133 
134 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
135 /// this instruction from their respective use lists. This requires that the
136 /// operands already be on their use lists.
137 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
138  for (MachineOperand &MO : operands())
139  if (MO.isReg())
141 }
142 
143 /// AddRegOperandsToUseLists - Add all of the register operands in
144 /// this instruction from their respective use lists. This requires that the
145 /// operands not be on their use lists yet.
146 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
147  for (MachineOperand &MO : operands())
148  if (MO.isReg())
149  MRI.addRegOperandToUseList(&MO);
150 }
151 
153  MachineBasicBlock *MBB = getParent();
154  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
155  MachineFunction *MF = MBB->getParent();
156  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
157  addOperand(*MF, Op);
158 }
159 
160 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
161 /// ranges. If MRI is non-null also update use-def chains.
163  unsigned NumOps, MachineRegisterInfo *MRI) {
164  if (MRI)
165  return MRI->moveOperands(Dst, Src, NumOps);
166 
167  // MachineOperand is a trivially copyable type so we can just use memmove.
168  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
169 }
170 
171 /// addOperand - Add the specified operand to the instruction. If it is an
172 /// implicit operand, it is added to the end of the operand list. If it is
173 /// an explicit operand it is added at the end of the explicit operand list
174 /// (before the first implicit operand).
176  assert(MCID && "Cannot add operands before providing an instr descriptor");
177 
178  // Check if we're adding one of our existing operands.
179  if (&Op >= Operands && &Op < Operands + NumOperands) {
180  // This is unusual: MI->addOperand(MI->getOperand(i)).
181  // If adding Op requires reallocating or moving existing operands around,
182  // the Op reference could go stale. Support it by copying Op.
183  MachineOperand CopyOp(Op);
184  return addOperand(MF, CopyOp);
185  }
186 
187  // Find the insert location for the new operand. Implicit registers go at
188  // the end, everything else goes before the implicit regs.
189  //
190  // FIXME: Allow mixed explicit and implicit operands on inline asm.
191  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
192  // implicit-defs, but they must not be moved around. See the FIXME in
193  // InstrEmitter.cpp.
194  unsigned OpNo = getNumOperands();
195  bool isImpReg = Op.isReg() && Op.isImplicit();
196  if (!isImpReg && !isInlineAsm()) {
197  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
198  --OpNo;
199  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
200  }
201  }
202 
203 #ifndef NDEBUG
204  bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
205  // OpNo now points as the desired insertion point. Unless this is a variadic
206  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
207  // RegMask operands go between the explicit and implicit operands.
208  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
209  OpNo < MCID->getNumOperands() || isMetaDataOp) &&
210  "Trying to add an operand to a machine instr that is already done!");
211 #endif
212 
213  MachineRegisterInfo *MRI = getRegInfo();
214 
215  // Determine if the Operands array needs to be reallocated.
216  // Save the old capacity and operand array.
217  OperandCapacity OldCap = CapOperands;
218  MachineOperand *OldOperands = Operands;
219  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
220  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
221  Operands = MF.allocateOperandArray(CapOperands);
222  // Move the operands before the insertion point.
223  if (OpNo)
224  moveOperands(Operands, OldOperands, OpNo, MRI);
225  }
226 
227  // Move the operands following the insertion point.
228  if (OpNo != NumOperands)
229  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
230  MRI);
231  ++NumOperands;
232 
233  // Deallocate the old operand array.
234  if (OldOperands != Operands && OldOperands)
235  MF.deallocateOperandArray(OldCap, OldOperands);
236 
237  // Copy Op into place. It still needs to be inserted into the MRI use lists.
238  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
239  NewMO->ParentMI = this;
240 
241  // When adding a register operand, tell MRI about it.
242  if (NewMO->isReg()) {
243  // Ensure isOnRegUseList() returns false, regardless of Op's status.
244  NewMO->Contents.Reg.Prev = nullptr;
245  // Ignore existing ties. This is not a property that can be copied.
246  NewMO->TiedTo = 0;
247  // Add the new operand to MRI, but only for instructions in an MBB.
248  if (MRI)
249  MRI->addRegOperandToUseList(NewMO);
250  // The MCID operand information isn't accurate until we start adding
251  // explicit operands. The implicit operands are added first, then the
252  // explicits are inserted before them.
253  if (!isImpReg) {
254  // Tie uses to defs as indicated in MCInstrDesc.
255  if (NewMO->isUse()) {
256  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
257  if (DefIdx != -1)
258  tieOperands(DefIdx, OpNo);
259  }
260  // If the register operand is flagged as early, mark the operand as such.
261  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
262  NewMO->setIsEarlyClobber(true);
263  }
264  }
265 }
266 
267 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
268 /// fewer operand than it started with.
269 ///
270 void MachineInstr::RemoveOperand(unsigned OpNo) {
271  assert(OpNo < getNumOperands() && "Invalid operand number");
272  untieRegOperand(OpNo);
273 
274 #ifndef NDEBUG
275  // Moving tied operands would break the ties.
276  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
277  if (Operands[i].isReg())
278  assert(!Operands[i].isTied() && "Cannot move tied operands");
279 #endif
280 
281  MachineRegisterInfo *MRI = getRegInfo();
282  if (MRI && Operands[OpNo].isReg())
283  MRI->removeRegOperandFromUseList(Operands + OpNo);
284 
285  // Don't call the MachineOperand destructor. A lot of this code depends on
286  // MachineOperand having a trivial destructor anyway, and adding a call here
287  // wouldn't make it 'destructor-correct'.
288 
289  if (unsigned N = NumOperands - 1 - OpNo)
290  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
291  --NumOperands;
292 }
293 
294 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
295 /// This function should be used only occasionally. The setMemRefs function
296 /// is the primary method for setting up a MachineInstr's MemRefs list.
298  MachineMemOperand *MO) {
299  mmo_iterator OldMemRefs = MemRefs;
300  unsigned OldNumMemRefs = NumMemRefs;
301 
302  unsigned NewNum = NumMemRefs + 1;
303  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
304 
305  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
306  NewMemRefs[NewNum - 1] = MO;
307  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
308 }
309 
310 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
311 /// identical.
312 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
313  auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
314  auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
315  if ((E1 - I1) != (E2 - I2))
316  return false;
317  for (; I1 != E1; ++I1, ++I2) {
318  if (**I1 != **I2)
319  return false;
320  }
321  return true;
322 }
323 
324 std::pair<MachineInstr::mmo_iterator, unsigned>
326 
327  // If either of the incoming memrefs are empty, we must be conservative and
328  // treat this as if we've exhausted our space for memrefs and dropped them.
329  if (memoperands_empty() || Other.memoperands_empty())
330  return std::make_pair(nullptr, 0);
331 
332  // If both instructions have identical memrefs, we don't need to merge them.
333  // Since many instructions have a single memref, and we tend to merge things
334  // like pairs of loads from the same location, this catches a large number of
335  // cases in practice.
336  if (hasIdenticalMMOs(*this, Other))
337  return std::make_pair(MemRefs, NumMemRefs);
338 
339  // TODO: consider uniquing elements within the operand lists to reduce
340  // space usage and fall back to conservative information less often.
341  size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
342 
343  // If we don't have enough room to store this many memrefs, be conservative
344  // and drop them. Otherwise, we'd fail asserts when trying to add them to
345  // the new instruction.
346  if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
347  return std::make_pair(nullptr, 0);
348 
349  MachineFunction *MF = getMF();
350  mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
352  MemBegin);
353  MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
354  MemEnd);
355  assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
356  "missing memrefs");
357 
358  return std::make_pair(MemBegin, CombinedNumMemRefs);
359 }
360 
361 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
362  assert(!isBundledWithPred() && "Must be called on bundle header");
364  if (MII->getDesc().getFlags() & Mask) {
365  if (Type == AnyInBundle)
366  return true;
367  } else {
368  if (Type == AllInBundle && !MII->isBundle())
369  return false;
370  }
371  // This was the last instruction in the bundle.
372  if (!MII->isBundledWithSucc())
373  return Type == AllInBundle;
374  }
375 }
376 
378  MICheckType Check) const {
379  // If opcodes or number of operands are not the same then the two
380  // instructions are obviously not identical.
381  if (Other.getOpcode() != getOpcode() ||
382  Other.getNumOperands() != getNumOperands())
383  return false;
384 
385  if (isBundle()) {
386  // We have passed the test above that both instructions have the same
387  // opcode, so we know that both instructions are bundles here. Let's compare
388  // MIs inside the bundle.
389  assert(Other.isBundle() && "Expected that both instructions are bundles.");
392  // Loop until we analysed the last intruction inside at least one of the
393  // bundles.
394  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
395  ++I1;
396  ++I2;
397  if (!I1->isIdenticalTo(*I2, Check))
398  return false;
399  }
400  // If we've reached the end of just one of the two bundles, but not both,
401  // the instructions are not identical.
402  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
403  return false;
404  }
405 
406  // Check operands to make sure they match.
407  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
408  const MachineOperand &MO = getOperand(i);
409  const MachineOperand &OMO = Other.getOperand(i);
410  if (!MO.isReg()) {
411  if (!MO.isIdenticalTo(OMO))
412  return false;
413  continue;
414  }
415 
416  // Clients may or may not want to ignore defs when testing for equality.
417  // For example, machine CSE pass only cares about finding common
418  // subexpressions, so it's safe to ignore virtual register defs.
419  if (MO.isDef()) {
420  if (Check == IgnoreDefs)
421  continue;
422  else if (Check == IgnoreVRegDefs) {
425  if (!MO.isIdenticalTo(OMO))
426  return false;
427  } else {
428  if (!MO.isIdenticalTo(OMO))
429  return false;
430  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
431  return false;
432  }
433  } else {
434  if (!MO.isIdenticalTo(OMO))
435  return false;
436  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
437  return false;
438  }
439  }
440  // If DebugLoc does not match then two dbg.values are not identical.
441  if (isDebugValue())
442  if (getDebugLoc() && Other.getDebugLoc() &&
443  getDebugLoc() != Other.getDebugLoc())
444  return false;
445  return true;
446 }
447 
449  return getParent()->getParent();
450 }
451 
453  assert(getParent() && "Not embedded in a basic block!");
454  return getParent()->remove(this);
455 }
456 
458  assert(getParent() && "Not embedded in a basic block!");
459  return getParent()->remove_instr(this);
460 }
461 
463  assert(getParent() && "Not embedded in a basic block!");
464  getParent()->erase(this);
465 }
466 
468  assert(getParent() && "Not embedded in a basic block!");
469  MachineBasicBlock *MBB = getParent();
470  MachineFunction *MF = MBB->getParent();
471  assert(MF && "Not embedded in a function!");
472 
473  MachineInstr *MI = (MachineInstr *)this;
474  MachineRegisterInfo &MRI = MF->getRegInfo();
475 
476  for (const MachineOperand &MO : MI->operands()) {
477  if (!MO.isReg() || !MO.isDef())
478  continue;
479  unsigned Reg = MO.getReg();
481  continue;
483  }
484  MI->eraseFromParent();
485 }
486 
488  assert(getParent() && "Not embedded in a basic block!");
489  getParent()->erase_instr(this);
490 }
491 
492 /// getNumExplicitOperands - Returns the number of non-implicit operands.
493 ///
495  unsigned NumOperands = MCID->getNumOperands();
496  if (!MCID->isVariadic())
497  return NumOperands;
498 
499  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
500  const MachineOperand &MO = getOperand(i);
501  if (!MO.isReg() || !MO.isImplicit())
502  NumOperands++;
503  }
504  return NumOperands;
505 }
506 
508  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
511  --Pred;
512  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
513  Pred->setFlag(BundledSucc);
514 }
515 
517  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
520  ++Succ;
521  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
522  Succ->setFlag(BundledPred);
523 }
524 
526  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
529  --Pred;
530  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
531  Pred->clearFlag(BundledSucc);
532 }
533 
535  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
538  ++Succ;
539  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
540  Succ->clearFlag(BundledPred);
541 }
542 
544  if (isInlineAsm()) {
545  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
546  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
547  return true;
548  }
549  return false;
550 }
551 
553  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
554  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
555  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
556 }
557 
559  unsigned *GroupNo) const {
560  assert(isInlineAsm() && "Expected an inline asm instruction");
561  assert(OpIdx < getNumOperands() && "OpIdx out of range");
562 
563  // Ignore queries about the initial operands.
564  if (OpIdx < InlineAsm::MIOp_FirstOperand)
565  return -1;
566 
567  unsigned Group = 0;
568  unsigned NumOps;
569  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
570  i += NumOps) {
571  const MachineOperand &FlagMO = getOperand(i);
572  // If we reach the implicit register operands, stop looking.
573  if (!FlagMO.isImm())
574  return -1;
575  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
576  if (i + NumOps > OpIdx) {
577  if (GroupNo)
578  *GroupNo = Group;
579  return i;
580  }
581  ++Group;
582  }
583  return -1;
584 }
585 
587  assert(isDebugValue() && "not a DBG_VALUE");
588  return cast<DILocalVariable>(getOperand(2).getMetadata());
589 }
590 
592  assert(isDebugValue() && "not a DBG_VALUE");
593  return cast<DIExpression>(getOperand(3).getMetadata());
594 }
595 
596 const TargetRegisterClass*
598  const TargetInstrInfo *TII,
599  const TargetRegisterInfo *TRI) const {
600  assert(getParent() && "Can't have an MBB reference here!");
601  assert(getMF() && "Can't have an MF reference here!");
602  const MachineFunction &MF = *getMF();
603 
604  // Most opcodes have fixed constraints in their MCInstrDesc.
605  if (!isInlineAsm())
606  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
607 
608  if (!getOperand(OpIdx).isReg())
609  return nullptr;
610 
611  // For tied uses on inline asm, get the constraint from the def.
612  unsigned DefIdx;
613  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
614  OpIdx = DefIdx;
615 
616  // Inline asm stores register class constraints in the flag word.
617  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
618  if (FlagIdx < 0)
619  return nullptr;
620 
621  unsigned Flag = getOperand(FlagIdx).getImm();
622  unsigned RCID;
627  return TRI->getRegClass(RCID);
628 
629  // Assume that all registers in a memory operand are pointers.
631  return TRI->getPointerRegClass(MF);
632 
633  return nullptr;
634 }
635 
637  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
638  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
639  // Check every operands inside the bundle if we have
640  // been asked to.
641  if (ExploreBundle)
642  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
643  ++OpndIt)
644  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
645  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
646  else
647  // Otherwise, just check the current operands.
648  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
649  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
650  return CurRC;
651 }
652 
653 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
654  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
655  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
656  assert(CurRC && "Invalid initial register class");
657  // Check if Reg is constrained by some of its use/def from MI.
658  const MachineOperand &MO = getOperand(OpIdx);
659  if (!MO.isReg() || MO.getReg() != Reg)
660  return CurRC;
661  // If yes, accumulate the constraints through the operand.
662  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
663 }
664 
666  unsigned OpIdx, const TargetRegisterClass *CurRC,
667  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
668  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
669  const MachineOperand &MO = getOperand(OpIdx);
670  assert(MO.isReg() &&
671  "Cannot get register constraints for non-register operand");
672  assert(CurRC && "Invalid initial register class");
673  if (unsigned SubIdx = MO.getSubReg()) {
674  if (OpRC)
675  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
676  else
677  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
678  } else if (OpRC)
679  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
680  return CurRC;
681 }
682 
683 /// Return the number of instructions inside the MI bundle, not counting the
684 /// header instruction.
685 unsigned MachineInstr::getBundleSize() const {
687  unsigned Size = 0;
688  while (I->isBundledWithSucc()) {
689  ++Size;
690  ++I;
691  }
692  return Size;
693 }
694 
695 /// Returns true if the MachineInstr has an implicit-use operand of exactly
696 /// the given register (not considering sub/super-registers).
698  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
699  const MachineOperand &MO = getOperand(i);
700  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
701  return true;
702  }
703  return false;
704 }
705 
706 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
707 /// the specific register or -1 if it is not found. It further tightens
708 /// the search criteria to a use that kills the register if isKill is true.
710  unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
711  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
712  const MachineOperand &MO = getOperand(i);
713  if (!MO.isReg() || !MO.isUse())
714  continue;
715  unsigned MOReg = MO.getReg();
716  if (!MOReg)
717  continue;
718  if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
720  TRI->isSubRegister(MOReg, Reg)))
721  if (!isKill || MO.isKill())
722  return i;
723  }
724  return -1;
725 }
726 
727 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
728 /// indicating if this instruction reads or writes Reg. This also considers
729 /// partial defines.
730 std::pair<bool,bool>
732  SmallVectorImpl<unsigned> *Ops) const {
733  bool PartDef = false; // Partial redefine.
734  bool FullDef = false; // Full define.
735  bool Use = false;
736 
737  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
738  const MachineOperand &MO = getOperand(i);
739  if (!MO.isReg() || MO.getReg() != Reg)
740  continue;
741  if (Ops)
742  Ops->push_back(i);
743  if (MO.isUse())
744  Use |= !MO.isUndef();
745  else if (MO.getSubReg() && !MO.isUndef())
746  // A partial def undef doesn't count as reading the register.
747  PartDef = true;
748  else
749  FullDef = true;
750  }
751  // A partial redefine uses Reg unless there is also a full define.
752  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
753 }
754 
755 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
756 /// the specified register or -1 if it is not found. If isDead is true, defs
757 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
758 /// also checks if there is a def of a super-register.
759 int
760 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
761  const TargetRegisterInfo *TRI) const {
762  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
763  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
764  const MachineOperand &MO = getOperand(i);
765  // Accept regmask operands when Overlap is set.
766  // Ignore them when looking for a specific def operand (Overlap == false).
767  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
768  return i;
769  if (!MO.isReg() || !MO.isDef())
770  continue;
771  unsigned MOReg = MO.getReg();
772  bool Found = (MOReg == Reg);
773  if (!Found && TRI && isPhys &&
775  if (Overlap)
776  Found = TRI->regsOverlap(MOReg, Reg);
777  else
778  Found = TRI->isSubRegister(MOReg, Reg);
779  }
780  if (Found && (!isDead || MO.isDead()))
781  return i;
782  }
783  return -1;
784 }
785 
786 /// findFirstPredOperandIdx() - Find the index of the first operand in the
787 /// operand list that is used to represent the predicate. It returns -1 if
788 /// none is found.
790  // Don't call MCID.findFirstPredOperandIdx() because this variant
791  // is sometimes called on an instruction that's not yet complete, and
792  // so the number of operands is less than the MCID indicates. In
793  // particular, the PTX target does this.
794  const MCInstrDesc &MCID = getDesc();
795  if (MCID.isPredicable()) {
796  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
797  if (MCID.OpInfo[i].isPredicate())
798  return i;
799  }
800 
801  return -1;
802 }
803 
804 // MachineOperand::TiedTo is 4 bits wide.
805 const unsigned TiedMax = 15;
806 
807 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
808 ///
809 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
810 /// field. TiedTo can have these values:
811 ///
812 /// 0: Operand is not tied to anything.
813 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
814 /// TiedMax: Tied to an operand >= TiedMax-1.
815 ///
816 /// The tied def must be one of the first TiedMax operands on a normal
817 /// instruction. INLINEASM instructions allow more tied defs.
818 ///
819 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
820  MachineOperand &DefMO = getOperand(DefIdx);
821  MachineOperand &UseMO = getOperand(UseIdx);
822  assert(DefMO.isDef() && "DefIdx must be a def operand");
823  assert(UseMO.isUse() && "UseIdx must be a use operand");
824  assert(!DefMO.isTied() && "Def is already tied to another use");
825  assert(!UseMO.isTied() && "Use is already tied to another def");
826 
827  if (DefIdx < TiedMax)
828  UseMO.TiedTo = DefIdx + 1;
829  else {
830  // Inline asm can use the group descriptors to find tied operands, but on
831  // normal instruction, the tied def must be within the first TiedMax
832  // operands.
833  assert(isInlineAsm() && "DefIdx out of range");
834  UseMO.TiedTo = TiedMax;
835  }
836 
837  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
838  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
839 }
840 
841 /// Given the index of a tied register operand, find the operand it is tied to.
842 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
843 /// which must exist.
844 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
845  const MachineOperand &MO = getOperand(OpIdx);
846  assert(MO.isTied() && "Operand isn't tied");
847 
848  // Normally TiedTo is in range.
849  if (MO.TiedTo < TiedMax)
850  return MO.TiedTo - 1;
851 
852  // Uses on normal instructions can be out of range.
853  if (!isInlineAsm()) {
854  // Normal tied defs must be in the 0..TiedMax-1 range.
855  if (MO.isUse())
856  return TiedMax - 1;
857  // MO is a def. Search for the tied use.
858  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
859  const MachineOperand &UseMO = getOperand(i);
860  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
861  return i;
862  }
863  llvm_unreachable("Can't find tied use");
864  }
865 
866  // Now deal with inline asm by parsing the operand group descriptor flags.
867  // Find the beginning of each operand group.
868  SmallVector<unsigned, 8> GroupIdx;
869  unsigned OpIdxGroup = ~0u;
870  unsigned NumOps;
871  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
872  i += NumOps) {
873  const MachineOperand &FlagMO = getOperand(i);
874  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
875  unsigned CurGroup = GroupIdx.size();
876  GroupIdx.push_back(i);
877  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
878  // OpIdx belongs to this operand group.
879  if (OpIdx > i && OpIdx < i + NumOps)
880  OpIdxGroup = CurGroup;
881  unsigned TiedGroup;
882  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
883  continue;
884  // Operands in this group are tied to operands in TiedGroup which must be
885  // earlier. Find the number of operands between the two groups.
886  unsigned Delta = i - GroupIdx[TiedGroup];
887 
888  // OpIdx is a use tied to TiedGroup.
889  if (OpIdxGroup == CurGroup)
890  return OpIdx - Delta;
891 
892  // OpIdx is a def tied to this use group.
893  if (OpIdxGroup == TiedGroup)
894  return OpIdx + Delta;
895  }
896  llvm_unreachable("Invalid tied operand on inline asm");
897 }
898 
899 /// clearKillInfo - Clears kill flags on all operands.
900 ///
902  for (MachineOperand &MO : operands()) {
903  if (MO.isReg() && MO.isUse())
904  MO.setIsKill(false);
905  }
906 }
907 
908 void MachineInstr::substituteRegister(unsigned FromReg,
909  unsigned ToReg,
910  unsigned SubIdx,
911  const TargetRegisterInfo &RegInfo) {
913  if (SubIdx)
914  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
915  for (MachineOperand &MO : operands()) {
916  if (!MO.isReg() || MO.getReg() != FromReg)
917  continue;
918  MO.substPhysReg(ToReg, RegInfo);
919  }
920  } else {
921  for (MachineOperand &MO : operands()) {
922  if (!MO.isReg() || MO.getReg() != FromReg)
923  continue;
924  MO.substVirtReg(ToReg, SubIdx, RegInfo);
925  }
926  }
927 }
928 
929 /// isSafeToMove - Return true if it is safe to move this instruction. If
930 /// SawStore is set to true, it means that there is a store (or call) between
931 /// the instruction's location and its intended destination.
932 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
933  // Ignore stuff that we obviously can't move.
934  //
935  // Treat volatile loads as stores. This is not strictly necessary for
936  // volatiles, but it is required for atomic loads. It is not allowed to move
937  // a load across an atomic load with Ordering > Monotonic.
938  if (mayStore() || isCall() || isPHI() ||
939  (mayLoad() && hasOrderedMemoryRef())) {
940  SawStore = true;
941  return false;
942  }
943 
944  if (isPosition() || isDebugValue() || isTerminator() ||
946  return false;
947 
948  // See if this instruction does a load. If so, we have to guarantee that the
949  // loaded value doesn't change between the load and the its intended
950  // destination. The check for isInvariantLoad gives the targe the chance to
951  // classify the load as always returning a constant, e.g. a constant pool
952  // load.
954  // Otherwise, this is a real load. If there is a store between the load and
955  // end of block, we can't move it.
956  return !SawStore;
957 
958  return true;
959 }
960 
962  bool UseTBAA) {
963  const MachineFunction *MF = getMF();
964  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
965  const MachineFrameInfo &MFI = MF->getFrameInfo();
966 
967  // If neither instruction stores to memory, they can't alias in any
968  // meaningful way, even if they read from the same address.
969  if (!mayStore() && !Other.mayStore())
970  return false;
971 
972  // Let the target decide if memory accesses cannot possibly overlap.
973  if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
974  return false;
975 
976  // FIXME: Need to handle multiple memory operands to support all targets.
977  if (!hasOneMemOperand() || !Other.hasOneMemOperand())
978  return true;
979 
981  MachineMemOperand *MMOb = *Other.memoperands_begin();
982 
983  // The following interface to AA is fashioned after DAGCombiner::isAlias
984  // and operates with MachineMemOperand offset with some important
985  // assumptions:
986  // - LLVM fundamentally assumes flat address spaces.
987  // - MachineOperand offset can *only* result from legalization and
988  // cannot affect queries other than the trivial case of overlap
989  // checking.
990  // - These offsets never wrap and never step outside
991  // of allocated objects.
992  // - There should never be any negative offsets here.
993  //
994  // FIXME: Modify API to hide this math from "user"
995  // Even before we go to AA we can reason locally about some
996  // memory objects. It can save compile time, and possibly catch some
997  // corner cases not currently covered.
998 
999  int64_t OffsetA = MMOa->getOffset();
1000  int64_t OffsetB = MMOb->getOffset();
1001 
1002  int64_t MinOffset = std::min(OffsetA, OffsetB);
1003  int64_t WidthA = MMOa->getSize();
1004  int64_t WidthB = MMOb->getSize();
1005  const Value *ValA = MMOa->getValue();
1006  const Value *ValB = MMOb->getValue();
1007  bool SameVal = (ValA && ValB && (ValA == ValB));
1008  if (!SameVal) {
1009  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1010  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1011  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1012  return false;
1013  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1014  return false;
1015  if (PSVa && PSVb && (PSVa == PSVb))
1016  SameVal = true;
1017  }
1018 
1019  if (SameVal) {
1020  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1021  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1022  return (MinOffset + LowWidth > MaxOffset);
1023  }
1024 
1025  if (!AA)
1026  return true;
1027 
1028  if (!ValA || !ValB)
1029  return true;
1030 
1031  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1032  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1033 
1034  int64_t Overlapa = WidthA + OffsetA - MinOffset;
1035  int64_t Overlapb = WidthB + OffsetB - MinOffset;
1036 
1037  AliasResult AAResult = AA->alias(
1038  MemoryLocation(ValA, Overlapa,
1039  UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1040  MemoryLocation(ValB, Overlapb,
1041  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1042 
1043  return (AAResult != NoAlias);
1044 }
1045 
1046 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1047 /// or volatile memory reference, or if the information describing the memory
1048 /// reference is not available. Return false if it is known to have no ordered
1049 /// memory references.
1051  // An instruction known never to access memory won't have a volatile access.
1052  if (!mayStore() &&
1053  !mayLoad() &&
1054  !isCall() &&
1056  return false;
1057 
1058  // Otherwise, if the instruction has no memory reference information,
1059  // conservatively assume it wasn't preserved.
1060  if (memoperands_empty())
1061  return true;
1062 
1063  // Check if any of our memory operands are ordered.
1064  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1065  return !MMO->isUnordered();
1066  });
1067 }
1068 
1069 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1070 /// trap and is loading from a location whose value is invariant across a run of
1071 /// this function.
1073  // If the instruction doesn't load at all, it isn't an invariant load.
1074  if (!mayLoad())
1075  return false;
1076 
1077  // If the instruction has lost its memoperands, conservatively assume that
1078  // it may not be an invariant load.
1079  if (memoperands_empty())
1080  return false;
1081 
1082  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1083 
1084  for (MachineMemOperand *MMO : memoperands()) {
1085  if (MMO->isVolatile()) return false;
1086  if (MMO->isStore()) return false;
1087  if (MMO->isInvariant() && MMO->isDereferenceable())
1088  continue;
1089 
1090  // A load from a constant PseudoSourceValue is invariant.
1091  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1092  if (PSV->isConstant(&MFI))
1093  continue;
1094 
1095  if (const Value *V = MMO->getValue()) {
1096  // If we have an AliasAnalysis, ask it whether the memory is constant.
1097  if (AA &&
1099  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1100  continue;
1101  }
1102 
1103  // Otherwise assume conservatively.
1104  return false;
1105  }
1106 
1107  // Everything checks out.
1108  return true;
1109 }
1110 
1111 /// isConstantValuePHI - If the specified instruction is a PHI that always
1112 /// merges together the same virtual register, return the register, otherwise
1113 /// return 0.
1115  if (!isPHI())
1116  return 0;
1117  assert(getNumOperands() >= 3 &&
1118  "It's illegal to have a PHI without source operands");
1119 
1120  unsigned Reg = getOperand(1).getReg();
1121  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1122  if (getOperand(i).getReg() != Reg)
1123  return 0;
1124  return Reg;
1125 }
1126 
1129  return true;
1130  if (isInlineAsm()) {
1131  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1132  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1133  return true;
1134  }
1135 
1136  return false;
1137 }
1138 
1140  return mayStore() || isCall() || hasUnmodeledSideEffects();
1141 }
1142 
1143 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1144 ///
1146  for (const MachineOperand &MO : operands()) {
1147  if (!MO.isReg() || MO.isUse())
1148  continue;
1149  if (!MO.isDead())
1150  return false;
1151  }
1152  return true;
1153 }
1154 
1155 /// copyImplicitOps - Copy implicit register operands from specified
1156 /// instruction to this instruction.
1158  const MachineInstr &MI) {
1159  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1160  i != e; ++i) {
1161  const MachineOperand &MO = MI.getOperand(i);
1162  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1163  addOperand(MF, MO);
1164  }
1165 }
1166 
1168  const MCInstrDesc &MCID = getDesc();
1169  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1170  const auto &Operand = getOperand(I);
1171  if (!Operand.isReg() || Operand.isDef())
1172  // Ignore the defined registers as MCID marks only the uses as tied.
1173  continue;
1174  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1175  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1176  if (ExpectedTiedIdx != TiedIdx)
1177  return true;
1178  }
1179  return false;
1180 }
1181 
1182 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1183  const MachineRegisterInfo &MRI) const {
1184  const MachineOperand &Op = getOperand(OpIdx);
1185  if (!Op.isReg())
1186  return LLT{};
1187 
1188  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1189  return MRI.getType(Op.getReg());
1190 
1191  auto &OpInfo = getDesc().OpInfo[OpIdx];
1192  if (!OpInfo.isGenericType())
1193  return MRI.getType(Op.getReg());
1194 
1195  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1196  return LLT{};
1197 
1198  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1199  return MRI.getType(Op.getReg());
1200 }
1201 
1202 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1204  dbgs() << " ";
1205  print(dbgs());
1206 }
1207 #endif
1208 
1209 void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
1210  const TargetInstrInfo *TII) const {
1211  const Module *M = nullptr;
1212  if (const MachineBasicBlock *MBB = getParent())
1213  if (const MachineFunction *MF = MBB->getParent())
1214  M = MF->getFunction().getParent();
1215 
1216  ModuleSlotTracker MST(M);
1217  print(OS, MST, SkipOpers, SkipDebugLoc, TII);
1218 }
1219 
1221  bool SkipOpers, bool SkipDebugLoc,
1222  const TargetInstrInfo *TII) const {
1223  // We can be a bit tidier if we know the MachineFunction.
1224  const MachineFunction *MF = nullptr;
1225  const TargetRegisterInfo *TRI = nullptr;
1226  const MachineRegisterInfo *MRI = nullptr;
1227  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1228 
1229  if (const MachineBasicBlock *MBB = getParent()) {
1230  MF = MBB->getParent();
1231  if (MF) {
1232  MRI = &MF->getRegInfo();
1233  TRI = MF->getSubtarget().getRegisterInfo();
1234  if (!TII)
1235  TII = MF->getSubtarget().getInstrInfo();
1236  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
1237  }
1238  }
1239 
1240 
1241  SmallBitVector PrintedTypes(8);
1242  bool ShouldPrintRegisterTies = hasComplexRegisterTies();
1243  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1244  if (!ShouldPrintRegisterTies)
1245  return 0U;
1246  const MachineOperand &MO = getOperand(OpIdx);
1247  if (MO.isReg() && MO.isTied() && !MO.isDef())
1248  return findTiedOperandIdx(OpIdx);
1249  return 0U;
1250  };
1251  // Print explicitly defined operands on the left of an assignment syntax.
1252  unsigned StartOp = 0, e = getNumOperands();
1253  for (; StartOp < e && getOperand(StartOp).isReg() &&
1254  getOperand(StartOp).isDef() && !getOperand(StartOp).isImplicit();
1255  ++StartOp) {
1256  if (StartOp != 0)
1257  OS << ", ";
1258  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1259  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1260  getOperand(StartOp).print(OS, MST, TypeToPrint, /*PrintDef=*/false,
1261  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1262  IntrinsicInfo);
1263  }
1264 
1265  if (StartOp != 0)
1266  OS << " = ";
1267 
1269  OS << "frame-setup ";
1271  OS << "frame-destroy ";
1272 
1273  // Print the opcode name.
1274  if (TII)
1275  OS << TII->getName(getOpcode());
1276  else
1277  OS << "UNKNOWN";
1278 
1279  if (SkipOpers)
1280  return;
1281 
1282  // Print the rest of the operands.
1283  bool FirstOp = true;
1284  unsigned AsmDescOp = ~0u;
1285  unsigned AsmOpCount = 0;
1286 
1287  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1288  // Print asm string.
1289  OS << " ";
1290  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1291  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1292  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1293  getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true,
1294  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1295  IntrinsicInfo);
1296 
1297  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1298  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1299  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1300  OS << " [sideeffect]";
1301  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1302  OS << " [mayload]";
1303  if (ExtraInfo & InlineAsm::Extra_MayStore)
1304  OS << " [maystore]";
1305  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1306  OS << " [isconvergent]";
1307  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1308  OS << " [alignstack]";
1310  OS << " [attdialect]";
1312  OS << " [inteldialect]";
1313 
1314  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1315  FirstOp = false;
1316  }
1317 
1318  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1319  const MachineOperand &MO = getOperand(i);
1320 
1321  if (FirstOp) FirstOp = false; else OS << ",";
1322  OS << " ";
1323 
1324  if (isDebugValue() && MO.isMetadata()) {
1325  // Pretty print DBG_VALUE instructions.
1326  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1327  if (DIV && !DIV->getName().empty())
1328  OS << "!\"" << DIV->getName() << '\"';
1329  else {
1330  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1331  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1332  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
1333  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1334  }
1335  } else if (TRI && (isInsertSubreg() || isRegSequence() ||
1336  (isSubregToReg() && i == 3)) && MO.isImm()) {
1337  OS << TRI->getSubRegIndexName(MO.getImm());
1338  } else if (i == AsmDescOp && MO.isImm()) {
1339  // Pretty print the inline asm operand descriptor.
1340  OS << '$' << AsmOpCount++;
1341  unsigned Flag = MO.getImm();
1342  switch (InlineAsm::getKind(Flag)) {
1343  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1344  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1345  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1346  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1347  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1348  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1349  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1350  }
1351 
1352  unsigned RCID = 0;
1353  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1354  InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1355  if (TRI) {
1356  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1357  } else
1358  OS << ":RC" << RCID;
1359  }
1360 
1361  if (InlineAsm::isMemKind(Flag)) {
1362  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1363  switch (MCID) {
1364  case InlineAsm::Constraint_es: OS << ":es"; break;
1365  case InlineAsm::Constraint_i: OS << ":i"; break;
1366  case InlineAsm::Constraint_m: OS << ":m"; break;
1367  case InlineAsm::Constraint_o: OS << ":o"; break;
1368  case InlineAsm::Constraint_v: OS << ":v"; break;
1369  case InlineAsm::Constraint_Q: OS << ":Q"; break;
1370  case InlineAsm::Constraint_R: OS << ":R"; break;
1371  case InlineAsm::Constraint_S: OS << ":S"; break;
1372  case InlineAsm::Constraint_T: OS << ":T"; break;
1373  case InlineAsm::Constraint_Um: OS << ":Um"; break;
1374  case InlineAsm::Constraint_Un: OS << ":Un"; break;
1375  case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1376  case InlineAsm::Constraint_Us: OS << ":Us"; break;
1377  case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1378  case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1379  case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1380  case InlineAsm::Constraint_X: OS << ":X"; break;
1381  case InlineAsm::Constraint_Z: OS << ":Z"; break;
1382  case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1383  case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1384  default: OS << ":?"; break;
1385  }
1386  }
1387 
1388  unsigned TiedTo = 0;
1389  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1390  OS << " tiedto:$" << TiedTo;
1391 
1392  OS << ']';
1393 
1394  // Compute the index of the next operand descriptor.
1395  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1396  } else {
1397  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1398  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1399  if (MO.isImm() && isOperandSubregIdx(i))
1400  MachineOperand::printSubregIdx(OS, MO.getImm(), TRI);
1401  else
1402  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
1403  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1404  }
1405  }
1406 
1407  bool HaveSemi = false;
1408  if (!memoperands_empty()) {
1409  if (!HaveSemi) {
1410  OS << ";";
1411  HaveSemi = true;
1412  }
1413 
1414  OS << " mem:";
1416  i != e; ++i) {
1417  (*i)->print(OS, MST);
1418  if (std::next(i) != e)
1419  OS << " ";
1420  }
1421  }
1422 
1423  // Print debug location information.
1424  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1425  if (!HaveSemi)
1426  OS << ";";
1427  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1428  OS << " line no:" << DV->getLine();
1429  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1430  DebugLoc InlinedAtDL(InlinedAt);
1431  if (InlinedAtDL && MF) {
1432  OS << " inlined @[ ";
1433  InlinedAtDL.print(OS);
1434  OS << " ]";
1435  }
1436  }
1437  if (isIndirectDebugValue())
1438  OS << " indirect";
1439  } else if (SkipDebugLoc) {
1440  return;
1441  } else if (debugLoc && MF) {
1442  if (!HaveSemi)
1443  OS << ";";
1444  OS << " dbg:";
1445  debugLoc.print(OS);
1446  }
1447 
1448  OS << '\n';
1449 }
1450 
1451 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1452  const TargetRegisterInfo *RegInfo,
1453  bool AddIfNotFound) {
1454  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1455  bool hasAliases = isPhysReg &&
1456  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1457  bool Found = false;
1458  SmallVector<unsigned,4> DeadOps;
1459  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1460  MachineOperand &MO = getOperand(i);
1461  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1462  continue;
1463 
1464  // DEBUG_VALUE nodes do not contribute to code generation and should
1465  // always be ignored. Failure to do so may result in trying to modify
1466  // KILL flags on DEBUG_VALUE nodes.
1467  if (MO.isDebug())
1468  continue;
1469 
1470  unsigned Reg = MO.getReg();
1471  if (!Reg)
1472  continue;
1473 
1474  if (Reg == IncomingReg) {
1475  if (!Found) {
1476  if (MO.isKill())
1477  // The register is already marked kill.
1478  return true;
1479  if (isPhysReg && isRegTiedToDefOperand(i))
1480  // Two-address uses of physregs must not be marked kill.
1481  return true;
1482  MO.setIsKill();
1483  Found = true;
1484  }
1485  } else if (hasAliases && MO.isKill() &&
1487  // A super-register kill already exists.
1488  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1489  return true;
1490  if (RegInfo->isSubRegister(IncomingReg, Reg))
1491  DeadOps.push_back(i);
1492  }
1493  }
1494 
1495  // Trim unneeded kill operands.
1496  while (!DeadOps.empty()) {
1497  unsigned OpIdx = DeadOps.back();
1498  if (getOperand(OpIdx).isImplicit())
1499  RemoveOperand(OpIdx);
1500  else
1501  getOperand(OpIdx).setIsKill(false);
1502  DeadOps.pop_back();
1503  }
1504 
1505  // If not found, this means an alias of one of the operands is killed. Add a
1506  // new implicit operand if required.
1507  if (!Found && AddIfNotFound) {
1509  false /*IsDef*/,
1510  true /*IsImp*/,
1511  true /*IsKill*/));
1512  return true;
1513  }
1514  return Found;
1515 }
1516 
1518  const TargetRegisterInfo *RegInfo) {
1520  RegInfo = nullptr;
1521  for (MachineOperand &MO : operands()) {
1522  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1523  continue;
1524  unsigned OpReg = MO.getReg();
1525  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1526  MO.setIsKill(false);
1527  }
1528 }
1529 
1531  const TargetRegisterInfo *RegInfo,
1532  bool AddIfNotFound) {
1533  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1534  bool hasAliases = isPhysReg &&
1535  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1536  bool Found = false;
1537  SmallVector<unsigned,4> DeadOps;
1538  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1539  MachineOperand &MO = getOperand(i);
1540  if (!MO.isReg() || !MO.isDef())
1541  continue;
1542  unsigned MOReg = MO.getReg();
1543  if (!MOReg)
1544  continue;
1545 
1546  if (MOReg == Reg) {
1547  MO.setIsDead();
1548  Found = true;
1549  } else if (hasAliases && MO.isDead() &&
1551  // There exists a super-register that's marked dead.
1552  if (RegInfo->isSuperRegister(Reg, MOReg))
1553  return true;
1554  if (RegInfo->isSubRegister(Reg, MOReg))
1555  DeadOps.push_back(i);
1556  }
1557  }
1558 
1559  // Trim unneeded dead operands.
1560  while (!DeadOps.empty()) {
1561  unsigned OpIdx = DeadOps.back();
1562  if (getOperand(OpIdx).isImplicit())
1563  RemoveOperand(OpIdx);
1564  else
1565  getOperand(OpIdx).setIsDead(false);
1566  DeadOps.pop_back();
1567  }
1568 
1569  // If not found, this means an alias of one of the operands is dead. Add a
1570  // new implicit operand if required.
1571  if (Found || !AddIfNotFound)
1572  return Found;
1573 
1575  true /*IsDef*/,
1576  true /*IsImp*/,
1577  false /*IsKill*/,
1578  true /*IsDead*/));
1579  return true;
1580 }
1581 
1583  for (MachineOperand &MO : operands()) {
1584  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1585  continue;
1586  MO.setIsDead(false);
1587  }
1588 }
1589 
1590 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1591  for (MachineOperand &MO : operands()) {
1592  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1593  continue;
1594  MO.setIsUndef(IsUndef);
1595  }
1596 }
1597 
1599  const TargetRegisterInfo *RegInfo) {
1601  MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1602  if (MO)
1603  return;
1604  } else {
1605  for (const MachineOperand &MO : operands()) {
1606  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1607  MO.getSubReg() == 0)
1608  return;
1609  }
1610  }
1612  true /*IsDef*/,
1613  true /*IsImp*/));
1614 }
1615 
1617  const TargetRegisterInfo &TRI) {
1618  bool HasRegMask = false;
1619  for (MachineOperand &MO : operands()) {
1620  if (MO.isRegMask()) {
1621  HasRegMask = true;
1622  continue;
1623  }
1624  if (!MO.isReg() || !MO.isDef()) continue;
1625  unsigned Reg = MO.getReg();
1626  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1627  // If there are no uses, including partial uses, the def is dead.
1628  if (llvm::none_of(UsedRegs,
1629  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1630  MO.setIsDead();
1631  }
1632 
1633  // This is a call with a register mask operand.
1634  // Mask clobbers are always dead, so add defs for the non-dead defines.
1635  if (HasRegMask)
1636  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1637  I != E; ++I)
1638  addRegisterDefined(*I, &TRI);
1639 }
1640 
1641 unsigned
1643  // Build up a buffer of hash code components.
1644  SmallVector<size_t, 8> HashComponents;
1645  HashComponents.reserve(MI->getNumOperands() + 1);
1646  HashComponents.push_back(MI->getOpcode());
1647  for (const MachineOperand &MO : MI->operands()) {
1648  if (MO.isReg() && MO.isDef() &&
1650  continue; // Skip virtual register defs.
1651 
1652  HashComponents.push_back(hash_value(MO));
1653  }
1654  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1655 }
1656 
1658  // Find the source location cookie.
1659  unsigned LocCookie = 0;
1660  const MDNode *LocMD = nullptr;
1661  for (unsigned i = getNumOperands(); i != 0; --i) {
1662  if (getOperand(i-1).isMetadata() &&
1663  (LocMD = getOperand(i-1).getMetadata()) &&
1664  LocMD->getNumOperands() != 0) {
1665  if (const ConstantInt *CI =
1666  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1667  LocCookie = CI->getZExtValue();
1668  break;
1669  }
1670  }
1671  }
1672 
1673  if (const MachineBasicBlock *MBB = getParent())
1674  if (const MachineFunction *MF = MBB->getParent())
1675  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1676  report_fatal_error(Msg);
1677 }
1678 
1680  const MCInstrDesc &MCID, bool IsIndirect,
1681  unsigned Reg, const MDNode *Variable,
1682  const MDNode *Expr) {
1683  assert(isa<DILocalVariable>(Variable) && "not a variable");
1684  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1685  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
1686  "Expected inlined-at fields to agree");
1687  if (IsIndirect)
1688  return BuildMI(MF, DL, MCID)
1689  .addReg(Reg, RegState::Debug)
1690  .addImm(0U)
1691  .addMetadata(Variable)
1692  .addMetadata(Expr);
1693  else
1694  return BuildMI(MF, DL, MCID)
1695  .addReg(Reg, RegState::Debug)
1696  .addReg(0U, RegState::Debug)
1697  .addMetadata(Variable)
1698  .addMetadata(Expr);
1699 }
1700 
1703  const DebugLoc &DL, const MCInstrDesc &MCID,
1704  bool IsIndirect, unsigned Reg,
1705  const MDNode *Variable, const MDNode *Expr) {
1706  assert(isa<DILocalVariable>(Variable) && "not a variable");
1707  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1708  MachineFunction &MF = *BB.getParent();
1709  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
1710  BB.insert(I, MI);
1711  return MachineInstrBuilder(MF, MI);
1712 }
1713 
1714 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
1715 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
1717  assert(MI.getOperand(0).isReg() && "can't spill non-register");
1719  "Expected inlined-at fields to agree");
1720 
1721  const DIExpression *Expr = MI.getDebugExpression();
1722  if (MI.isIndirectDebugValue()) {
1723  assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
1725  }
1726  return Expr;
1727 }
1728 
1731  const MachineInstr &Orig,
1732  int FrameIndex) {
1733  const DIExpression *Expr = computeExprForSpill(Orig);
1734  return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
1735  .addFrameIndex(FrameIndex)
1736  .addImm(0U)
1737  .addMetadata(Orig.getDebugVariable())
1738  .addMetadata(Expr);
1739 }
1740 
1742  const DIExpression *Expr = computeExprForSpill(Orig);
1743  Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
1744  Orig.getOperand(1).ChangeToImmediate(0U);
1745  Orig.getOperand(3).setMetadata(Expr);
1746 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool Check(DecodeStatus &Out, DecodeStatus In)
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:515
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
bool isUnordered() const
Returns true if this memory operation doesn&#39;t have any ordering constraints other than normal aliasin...
void push_back(const T &Elt)
Definition: SmallVector.h:212
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:537
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static const DIExpression * computeExprForSpill(const MachineInstr &MI)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:250
bool isSubregToReg() const
Definition: MachineInstr.h:848
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:512
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
This file contains the declarations for metadata subclasses.
unsigned getSubReg() const
bool isInlineAsm() const
Definition: MachineInstr.h:835
bool isRegSequence() const
Definition: MachineInstr.h:852
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:862
The two locations do not alias at all.
Definition: AliasAnalysis.h:85
void setIsDead(bool Val=true)
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1067
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:399
void reserve(size_type N)
Definition: SmallVector.h:378
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
bool isPHI() const
Definition: MachineInstr.h:829
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:117
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:276
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void clearKillInfo()
Clears kill flags on all operands.
AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
The main low level interface to the alias analysis implementation.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
A description of a memory reference used in the backend.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:254
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:237
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:828
Reg
All possible values of the reg field in the ModR/M byte.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:477
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
void bundleWithSucc()
Bundle this instruction with its successor.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isBundle() const
Definition: MachineInstr.h:856
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4428
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
virtual const TargetInstrInfo * getInstrInfo() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:642
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
unsigned const MachineRegisterInfo * MRI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:308
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
AliasResult
The possible results of an alias query.
Definition: AliasAnalysis.h:79
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:188
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:199
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:407
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:821
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:329
const PseudoSourceValue * getPseudoValue() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
bool isStackAligningInlineAsm() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:277
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
void setIsKill(bool Val=true)
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
Representation for a specific memory location.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
static void printSubregIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
InlineAsm::AsmDialect getInlineAsmDialect() const
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:392
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
void setFlags(unsigned flags)
Definition: MachineInstr.h:192
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:819
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
bool isInsertSubreg() const
Definition: MachineInstr.h:844
iterator end() const
Definition: ArrayRef.h:138
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:642
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:441
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
int64_t getImm() const
void setMetadata(const MDNode *MD)
DWARF expression.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:428
Special value supplied for machine level alias analysis.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:480
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
const unsigned TiedMax
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:417
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
static DIExpression * prepend(const DIExpression *DIExpr, bool DerefBefore, int64_t Offset=0, bool DerefAfter=false, bool StackValue=false)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value...
std::pair< mmo_iterator, unsigned > mergeMemRefsWith(const MachineInstr &Other)
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of b...
This file provides utility analysis objects describing memory locations.
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
Definition: MachineInstr.h:833
void print(raw_ostream &OS, bool SkipOpers=false, bool SkipDebugLoc=false, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
const Module * getModule() const
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:629
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the the memory access done by this i...
Definition: MachineInstr.h:397
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
void unbundleFromSucc()
Break bundle below this instruction.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:559
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool isPosition() const
Definition: MachineInstr.h:817
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1073
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:866
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
Definition: MachineInstr.h:823
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
struct llvm::MachineOperand::@142::@144 Reg
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr&#39;s memory reference descriptor list.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:183
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
const MDNode * getMetadata() const
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:393
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
bool isImplicit() const
Metadata reference (for debug info)
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:70
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.