LLVM  8.0.0svn
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/FoldingSet.h"
18 #include "llvm/ADT/Hashing.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Analysis/Loads.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
53 #include "llvm/IR/Type.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/MC/MCRegisterInfo.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/Compiler.h"
62 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <cassert>
71 #include <cstddef>
72 #include <cstdint>
73 #include <cstring>
74 #include <iterator>
75 #include <utility>
76 
77 using namespace llvm;
78 
80  if (const MachineBasicBlock *MBB = MI.getParent())
81  if (const MachineFunction *MF = MBB->getParent())
82  return MF;
83  return nullptr;
84 }
85 
86 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
87 // it.
88 static void tryToGetTargetInfo(const MachineInstr &MI,
89  const TargetRegisterInfo *&TRI,
90  const MachineRegisterInfo *&MRI,
91  const TargetIntrinsicInfo *&IntrinsicInfo,
92  const TargetInstrInfo *&TII) {
93 
94  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95  TRI = MF->getSubtarget().getRegisterInfo();
96  MRI = &MF->getRegInfo();
97  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98  TII = MF->getSubtarget().getInstrInfo();
99  }
100 }
101 
103  if (MCID->ImplicitDefs)
104  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
105  ++ImpDefs)
106  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107  if (MCID->ImplicitUses)
108  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
109  ++ImpUses)
110  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
111 }
112 
113 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114 /// implicit operands. It reserves space for the number of operands specified by
115 /// the MCInstrDesc.
116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117  DebugLoc dl, bool NoImp)
118  : MCID(&tid), debugLoc(std::move(dl)) {
119  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
120 
121  // Reserve space for the expected number of operands.
122  if (unsigned NumOps = MCID->getNumOperands() +
123  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124  CapOperands = OperandCapacity::get(NumOps);
125  Operands = MF.allocateOperandArray(CapOperands);
126  }
127 
128  if (!NoImp)
130 }
131 
132 /// MachineInstr ctor - Copies MachineInstr arg exactly
133 ///
134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135  : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
137 
138  CapOperands = OperandCapacity::get(MI.getNumOperands());
139  Operands = MF.allocateOperandArray(CapOperands);
140 
141  // Copy operands.
142  for (const MachineOperand &MO : MI.operands())
143  addOperand(MF, MO);
144 
145  // Copy all the sensible flags.
146  setFlags(MI.Flags);
147 }
148 
149 /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 /// return the MachineRegisterInfo object for the current function, otherwise
151 /// return null.
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
153  if (MachineBasicBlock *MBB = getParent())
154  return &MBB->getParent()->getRegInfo();
155  return nullptr;
156 }
157 
158 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 /// this instruction from their respective use lists. This requires that the
160 /// operands already be on their use lists.
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162  for (MachineOperand &MO : operands())
163  if (MO.isReg())
165 }
166 
167 /// AddRegOperandsToUseLists - Add all of the register operands in
168 /// this instruction from their respective use lists. This requires that the
169 /// operands not be on their use lists yet.
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171  for (MachineOperand &MO : operands())
172  if (MO.isReg())
173  MRI.addRegOperandToUseList(&MO);
174 }
175 
177  MachineBasicBlock *MBB = getParent();
178  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179  MachineFunction *MF = MBB->getParent();
180  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
181  addOperand(*MF, Op);
182 }
183 
184 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 /// ranges. If MRI is non-null also update use-def chains.
187  unsigned NumOps, MachineRegisterInfo *MRI) {
188  if (MRI)
189  return MRI->moveOperands(Dst, Src, NumOps);
190 
191  // MachineOperand is a trivially copyable type so we can just use memmove.
192  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193 }
194 
195 /// addOperand - Add the specified operand to the instruction. If it is an
196 /// implicit operand, it is added to the end of the operand list. If it is
197 /// an explicit operand it is added at the end of the explicit operand list
198 /// (before the first implicit operand).
200  assert(MCID && "Cannot add operands before providing an instr descriptor");
201 
202  // Check if we're adding one of our existing operands.
203  if (&Op >= Operands && &Op < Operands + NumOperands) {
204  // This is unusual: MI->addOperand(MI->getOperand(i)).
205  // If adding Op requires reallocating or moving existing operands around,
206  // the Op reference could go stale. Support it by copying Op.
207  MachineOperand CopyOp(Op);
208  return addOperand(MF, CopyOp);
209  }
210 
211  // Find the insert location for the new operand. Implicit registers go at
212  // the end, everything else goes before the implicit regs.
213  //
214  // FIXME: Allow mixed explicit and implicit operands on inline asm.
215  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216  // implicit-defs, but they must not be moved around. See the FIXME in
217  // InstrEmitter.cpp.
218  unsigned OpNo = getNumOperands();
219  bool isImpReg = Op.isReg() && Op.isImplicit();
220  if (!isImpReg && !isInlineAsm()) {
221  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
222  --OpNo;
223  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
224  }
225  }
226 
227 #ifndef NDEBUG
228  bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
229  // OpNo now points as the desired insertion point. Unless this is a variadic
230  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
231  // RegMask operands go between the explicit and implicit operands.
232  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
233  OpNo < MCID->getNumOperands() || isMetaDataOp) &&
234  "Trying to add an operand to a machine instr that is already done!");
235 #endif
236 
237  MachineRegisterInfo *MRI = getRegInfo();
238 
239  // Determine if the Operands array needs to be reallocated.
240  // Save the old capacity and operand array.
241  OperandCapacity OldCap = CapOperands;
242  MachineOperand *OldOperands = Operands;
243  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
244  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
245  Operands = MF.allocateOperandArray(CapOperands);
246  // Move the operands before the insertion point.
247  if (OpNo)
248  moveOperands(Operands, OldOperands, OpNo, MRI);
249  }
250 
251  // Move the operands following the insertion point.
252  if (OpNo != NumOperands)
253  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
254  MRI);
255  ++NumOperands;
256 
257  // Deallocate the old operand array.
258  if (OldOperands != Operands && OldOperands)
259  MF.deallocateOperandArray(OldCap, OldOperands);
260 
261  // Copy Op into place. It still needs to be inserted into the MRI use lists.
262  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
263  NewMO->ParentMI = this;
264 
265  // When adding a register operand, tell MRI about it.
266  if (NewMO->isReg()) {
267  // Ensure isOnRegUseList() returns false, regardless of Op's status.
268  NewMO->Contents.Reg.Prev = nullptr;
269  // Ignore existing ties. This is not a property that can be copied.
270  NewMO->TiedTo = 0;
271  // Add the new operand to MRI, but only for instructions in an MBB.
272  if (MRI)
273  MRI->addRegOperandToUseList(NewMO);
274  // The MCID operand information isn't accurate until we start adding
275  // explicit operands. The implicit operands are added first, then the
276  // explicits are inserted before them.
277  if (!isImpReg) {
278  // Tie uses to defs as indicated in MCInstrDesc.
279  if (NewMO->isUse()) {
280  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
281  if (DefIdx != -1)
282  tieOperands(DefIdx, OpNo);
283  }
284  // If the register operand is flagged as early, mark the operand as such.
285  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
286  NewMO->setIsEarlyClobber(true);
287  }
288  }
289 }
290 
291 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
292 /// fewer operand than it started with.
293 ///
294 void MachineInstr::RemoveOperand(unsigned OpNo) {
295  assert(OpNo < getNumOperands() && "Invalid operand number");
296  untieRegOperand(OpNo);
297 
298 #ifndef NDEBUG
299  // Moving tied operands would break the ties.
300  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
301  if (Operands[i].isReg())
302  assert(!Operands[i].isTied() && "Cannot move tied operands");
303 #endif
304 
305  MachineRegisterInfo *MRI = getRegInfo();
306  if (MRI && Operands[OpNo].isReg())
307  MRI->removeRegOperandFromUseList(Operands + OpNo);
308 
309  // Don't call the MachineOperand destructor. A lot of this code depends on
310  // MachineOperand having a trivial destructor anyway, and adding a call here
311  // wouldn't make it 'destructor-correct'.
312 
313  if (unsigned N = NumOperands - 1 - OpNo)
314  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
315  --NumOperands;
316 }
317 
319  if (memoperands_empty())
320  return;
321 
322  // See if we can just drop all of our extra info.
323  if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
324  Info.clear();
325  return;
326  }
327  if (!getPostInstrSymbol()) {
328  Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
329  return;
330  }
331  if (!getPreInstrSymbol()) {
332  Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
333  return;
334  }
335 
336  // Otherwise allocate a fresh extra info with just these symbols.
337  Info.set<EIIK_OutOfLine>(
339 }
340 
343  if (MMOs.empty()) {
344  dropMemRefs(MF);
345  return;
346  }
347 
348  // Try to store a single MMO inline.
349  if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
350  Info.set<EIIK_MMO>(MMOs[0]);
351  return;
352  }
353 
354  // Otherwise create an extra info struct with all of our info.
355  Info.set<EIIK_OutOfLine>(
357 }
358 
360  MachineMemOperand *MO) {
363  MMOs.push_back(MO);
364  setMemRefs(MF, MMOs);
365 }
366 
368  if (this == &MI)
369  // Nothing to do for a self-clone!
370  return;
371 
372  assert(&MF == MI.getMF() &&
373  "Invalid machine functions when cloning memory refrences!");
374  // See if we can just steal the extra info already allocated for the
375  // instruction. We can do this whenever the pre- and post-instruction symbols
376  // are the same (including null).
377  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
379  Info = MI.Info;
380  return;
381  }
382 
383  // Otherwise, fall back on a copy-based clone.
384  setMemRefs(MF, MI.memoperands());
385 }
386 
387 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
388 /// identical.
391  if (LHS.size() != RHS.size())
392  return false;
393 
394  auto LHSPointees = make_pointee_range(LHS);
395  auto RHSPointees = make_pointee_range(RHS);
396  return std::equal(LHSPointees.begin(), LHSPointees.end(),
397  RHSPointees.begin());
398 }
399 
402  // Try handling easy numbers of MIs with simpler mechanisms.
403  if (MIs.empty()) {
404  dropMemRefs(MF);
405  return;
406  }
407  if (MIs.size() == 1) {
408  cloneMemRefs(MF, *MIs[0]);
409  return;
410  }
411  // Because an empty memoperands list provides *no* information and must be
412  // handled conservatively (assuming the instruction can do anything), the only
413  // way to merge with it is to drop all other memoperands.
414  if (MIs[0]->memoperands_empty()) {
415  dropMemRefs(MF);
416  return;
417  }
418 
419  // Handle the general case.
421  // Start with the first instruction.
422  assert(&MF == MIs[0]->getMF() &&
423  "Invalid machine functions when cloning memory references!");
424  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
425  // Now walk all the other instructions and accumulate any different MMOs.
426  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
427  assert(&MF == MI.getMF() &&
428  "Invalid machine functions when cloning memory references!");
429 
430  // Skip MIs with identical operands to the first. This is a somewhat
431  // arbitrary hack but will catch common cases without being quadratic.
432  // TODO: We could fully implement merge semantics here if needed.
433  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
434  continue;
435 
436  // Because an empty memoperands list provides *no* information and must be
437  // handled conservatively (assuming the instruction can do anything), the
438  // only way to merge with it is to drop all other memoperands.
439  if (MI.memoperands_empty()) {
440  dropMemRefs(MF);
441  return;
442  }
443 
444  // Otherwise accumulate these into our temporary buffer of the merged state.
445  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
446  }
447 
448  setMemRefs(MF, MergedMMOs);
449 }
450 
452  MCSymbol *OldSymbol = getPreInstrSymbol();
453  if (OldSymbol == Symbol)
454  return;
455  if (OldSymbol && !Symbol) {
456  // We're removing a symbol rather than adding one. Try to clean up any
457  // extra info carried around.
458  if (Info.is<EIIK_PreInstrSymbol>()) {
459  Info.clear();
460  return;
461  }
462 
463  if (memoperands_empty()) {
465  "Should never have only a single symbol allocated out-of-line!");
466  Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
467  return;
468  }
469 
470  // Otherwise fallback on the generic update.
471  } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
472  // If we don't have any other extra info, we can store this inline.
473  Info.set<EIIK_PreInstrSymbol>(Symbol);
474  return;
475  }
476 
477  // Otherwise, allocate a full new set of extra info.
478  // FIXME: Maybe we should make the symbols in the extra info mutable?
479  Info.set<EIIK_OutOfLine>(
481 }
482 
484  MCSymbol *OldSymbol = getPostInstrSymbol();
485  if (OldSymbol == Symbol)
486  return;
487  if (OldSymbol && !Symbol) {
488  // We're removing a symbol rather than adding one. Try to clean up any
489  // extra info carried around.
490  if (Info.is<EIIK_PostInstrSymbol>()) {
491  Info.clear();
492  return;
493  }
494 
495  if (memoperands_empty()) {
497  "Should never have only a single symbol allocated out-of-line!");
498  Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
499  return;
500  }
501 
502  // Otherwise fallback on the generic update.
503  } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
504  // If we don't have any other extra info, we can store this inline.
505  Info.set<EIIK_PostInstrSymbol>(Symbol);
506  return;
507  }
508 
509  // Otherwise, allocate a full new set of extra info.
510  // FIXME: Maybe we should make the symbols in the extra info mutable?
511  Info.set<EIIK_OutOfLine>(
513 }
514 
515 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
516  // For now, the just return the union of the flags. If the flags get more
517  // complicated over time, we might need more logic here.
518  return getFlags() | Other.getFlags();
519 }
520 
522  // Copy the wrapping flags.
523  if (const OverflowingBinaryOperator *OB =
524  dyn_cast<OverflowingBinaryOperator>(&I)) {
525  if (OB->hasNoSignedWrap())
526  setFlag(MachineInstr::MIFlag::NoSWrap);
527  if (OB->hasNoUnsignedWrap())
528  setFlag(MachineInstr::MIFlag::NoUWrap);
529  }
530 
531  // Copy the exact flag.
532  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
533  if (PE->isExact())
534  setFlag(MachineInstr::MIFlag::IsExact);
535 
536  // Copy the fast-math flags.
537  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
538  const FastMathFlags Flags = FP->getFastMathFlags();
539  if (Flags.noNaNs())
540  setFlag(MachineInstr::MIFlag::FmNoNans);
541  if (Flags.noInfs())
542  setFlag(MachineInstr::MIFlag::FmNoInfs);
543  if (Flags.noSignedZeros())
544  setFlag(MachineInstr::MIFlag::FmNsz);
545  if (Flags.allowReciprocal())
546  setFlag(MachineInstr::MIFlag::FmArcp);
547  if (Flags.allowContract())
548  setFlag(MachineInstr::MIFlag::FmContract);
549  if (Flags.approxFunc())
550  setFlag(MachineInstr::MIFlag::FmAfn);
551  if (Flags.allowReassoc())
552  setFlag(MachineInstr::MIFlag::FmReassoc);
553  }
554 }
555 
556 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
557  assert(!isBundledWithPred() && "Must be called on bundle header");
559  if (MII->getDesc().getFlags() & Mask) {
560  if (Type == AnyInBundle)
561  return true;
562  } else {
563  if (Type == AllInBundle && !MII->isBundle())
564  return false;
565  }
566  // This was the last instruction in the bundle.
567  if (!MII->isBundledWithSucc())
568  return Type == AllInBundle;
569  }
570 }
571 
573  MICheckType Check) const {
574  // If opcodes or number of operands are not the same then the two
575  // instructions are obviously not identical.
576  if (Other.getOpcode() != getOpcode() ||
577  Other.getNumOperands() != getNumOperands())
578  return false;
579 
580  if (isBundle()) {
581  // We have passed the test above that both instructions have the same
582  // opcode, so we know that both instructions are bundles here. Let's compare
583  // MIs inside the bundle.
584  assert(Other.isBundle() && "Expected that both instructions are bundles.");
587  // Loop until we analysed the last intruction inside at least one of the
588  // bundles.
589  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
590  ++I1;
591  ++I2;
592  if (!I1->isIdenticalTo(*I2, Check))
593  return false;
594  }
595  // If we've reached the end of just one of the two bundles, but not both,
596  // the instructions are not identical.
597  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
598  return false;
599  }
600 
601  // Check operands to make sure they match.
602  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
603  const MachineOperand &MO = getOperand(i);
604  const MachineOperand &OMO = Other.getOperand(i);
605  if (!MO.isReg()) {
606  if (!MO.isIdenticalTo(OMO))
607  return false;
608  continue;
609  }
610 
611  // Clients may or may not want to ignore defs when testing for equality.
612  // For example, machine CSE pass only cares about finding common
613  // subexpressions, so it's safe to ignore virtual register defs.
614  if (MO.isDef()) {
615  if (Check == IgnoreDefs)
616  continue;
617  else if (Check == IgnoreVRegDefs) {
620  if (!MO.isIdenticalTo(OMO))
621  return false;
622  } else {
623  if (!MO.isIdenticalTo(OMO))
624  return false;
625  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
626  return false;
627  }
628  } else {
629  if (!MO.isIdenticalTo(OMO))
630  return false;
631  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
632  return false;
633  }
634  }
635  // If DebugLoc does not match then two debug instructions are not identical.
636  if (isDebugInstr())
637  if (getDebugLoc() && Other.getDebugLoc() &&
638  getDebugLoc() != Other.getDebugLoc())
639  return false;
640  return true;
641 }
642 
644  return getParent()->getParent();
645 }
646 
648  assert(getParent() && "Not embedded in a basic block!");
649  return getParent()->remove(this);
650 }
651 
653  assert(getParent() && "Not embedded in a basic block!");
654  return getParent()->remove_instr(this);
655 }
656 
658  assert(getParent() && "Not embedded in a basic block!");
659  getParent()->erase(this);
660 }
661 
663  assert(getParent() && "Not embedded in a basic block!");
664  MachineBasicBlock *MBB = getParent();
665  MachineFunction *MF = MBB->getParent();
666  assert(MF && "Not embedded in a function!");
667 
668  MachineInstr *MI = (MachineInstr *)this;
669  MachineRegisterInfo &MRI = MF->getRegInfo();
670 
671  for (const MachineOperand &MO : MI->operands()) {
672  if (!MO.isReg() || !MO.isDef())
673  continue;
674  unsigned Reg = MO.getReg();
676  continue;
678  }
679  MI->eraseFromParent();
680 }
681 
683  assert(getParent() && "Not embedded in a basic block!");
684  getParent()->erase_instr(this);
685 }
686 
688  unsigned NumOperands = MCID->getNumOperands();
689  if (!MCID->isVariadic())
690  return NumOperands;
691 
692  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
693  const MachineOperand &MO = getOperand(I);
694  // The operands must always be in the following order:
695  // - explicit reg defs,
696  // - other explicit operands (reg uses, immediates, etc.),
697  // - implicit reg defs
698  // - implicit reg uses
699  if (MO.isReg() && MO.isImplicit())
700  break;
701  ++NumOperands;
702  }
703  return NumOperands;
704 }
705 
707  unsigned NumDefs = MCID->getNumDefs();
708  if (!MCID->isVariadic())
709  return NumDefs;
710 
711  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
712  const MachineOperand &MO = getOperand(I);
713  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
714  break;
715  ++NumDefs;
716  }
717  return NumDefs;
718 }
719 
721  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
724  --Pred;
725  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
726  Pred->setFlag(BundledSucc);
727 }
728 
730  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
733  ++Succ;
734  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
735  Succ->setFlag(BundledPred);
736 }
737 
739  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
742  --Pred;
743  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
744  Pred->clearFlag(BundledSucc);
745 }
746 
748  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
751  ++Succ;
752  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
753  Succ->clearFlag(BundledPred);
754 }
755 
757  if (isInlineAsm()) {
758  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
759  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
760  return true;
761  }
762  return false;
763 }
764 
766  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
767  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
768  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
769 }
770 
772  unsigned *GroupNo) const {
773  assert(isInlineAsm() && "Expected an inline asm instruction");
774  assert(OpIdx < getNumOperands() && "OpIdx out of range");
775 
776  // Ignore queries about the initial operands.
777  if (OpIdx < InlineAsm::MIOp_FirstOperand)
778  return -1;
779 
780  unsigned Group = 0;
781  unsigned NumOps;
782  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
783  i += NumOps) {
784  const MachineOperand &FlagMO = getOperand(i);
785  // If we reach the implicit register operands, stop looking.
786  if (!FlagMO.isImm())
787  return -1;
788  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
789  if (i + NumOps > OpIdx) {
790  if (GroupNo)
791  *GroupNo = Group;
792  return i;
793  }
794  ++Group;
795  }
796  return -1;
797 }
798 
800  assert(isDebugLabel() && "not a DBG_LABEL");
801  return cast<DILabel>(getOperand(0).getMetadata());
802 }
803 
805  assert(isDebugValue() && "not a DBG_VALUE");
806  return cast<DILocalVariable>(getOperand(2).getMetadata());
807 }
808 
810  assert(isDebugValue() && "not a DBG_VALUE");
811  return cast<DIExpression>(getOperand(3).getMetadata());
812 }
813 
814 const TargetRegisterClass*
816  const TargetInstrInfo *TII,
817  const TargetRegisterInfo *TRI) const {
818  assert(getParent() && "Can't have an MBB reference here!");
819  assert(getMF() && "Can't have an MF reference here!");
820  const MachineFunction &MF = *getMF();
821 
822  // Most opcodes have fixed constraints in their MCInstrDesc.
823  if (!isInlineAsm())
824  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
825 
826  if (!getOperand(OpIdx).isReg())
827  return nullptr;
828 
829  // For tied uses on inline asm, get the constraint from the def.
830  unsigned DefIdx;
831  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
832  OpIdx = DefIdx;
833 
834  // Inline asm stores register class constraints in the flag word.
835  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
836  if (FlagIdx < 0)
837  return nullptr;
838 
839  unsigned Flag = getOperand(FlagIdx).getImm();
840  unsigned RCID;
845  return TRI->getRegClass(RCID);
846 
847  // Assume that all registers in a memory operand are pointers.
849  return TRI->getPointerRegClass(MF);
850 
851  return nullptr;
852 }
853 
855  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
856  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
857  // Check every operands inside the bundle if we have
858  // been asked to.
859  if (ExploreBundle)
860  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
861  ++OpndIt)
862  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
863  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
864  else
865  // Otherwise, just check the current operands.
866  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
867  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
868  return CurRC;
869 }
870 
871 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
872  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
873  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
874  assert(CurRC && "Invalid initial register class");
875  // Check if Reg is constrained by some of its use/def from MI.
876  const MachineOperand &MO = getOperand(OpIdx);
877  if (!MO.isReg() || MO.getReg() != Reg)
878  return CurRC;
879  // If yes, accumulate the constraints through the operand.
880  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
881 }
882 
884  unsigned OpIdx, const TargetRegisterClass *CurRC,
885  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
886  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
887  const MachineOperand &MO = getOperand(OpIdx);
888  assert(MO.isReg() &&
889  "Cannot get register constraints for non-register operand");
890  assert(CurRC && "Invalid initial register class");
891  if (unsigned SubIdx = MO.getSubReg()) {
892  if (OpRC)
893  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
894  else
895  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
896  } else if (OpRC)
897  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
898  return CurRC;
899 }
900 
901 /// Return the number of instructions inside the MI bundle, not counting the
902 /// header instruction.
903 unsigned MachineInstr::getBundleSize() const {
905  unsigned Size = 0;
906  while (I->isBundledWithSucc()) {
907  ++Size;
908  ++I;
909  }
910  return Size;
911 }
912 
913 /// Returns true if the MachineInstr has an implicit-use operand of exactly
914 /// the given register (not considering sub/super-registers).
916  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
917  const MachineOperand &MO = getOperand(i);
918  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
919  return true;
920  }
921  return false;
922 }
923 
924 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
925 /// the specific register or -1 if it is not found. It further tightens
926 /// the search criteria to a use that kills the register if isKill is true.
928  unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
929  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
930  const MachineOperand &MO = getOperand(i);
931  if (!MO.isReg() || !MO.isUse())
932  continue;
933  unsigned MOReg = MO.getReg();
934  if (!MOReg)
935  continue;
936  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
937  if (!isKill || MO.isKill())
938  return i;
939  }
940  return -1;
941 }
942 
943 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
944 /// indicating if this instruction reads or writes Reg. This also considers
945 /// partial defines.
946 std::pair<bool,bool>
948  SmallVectorImpl<unsigned> *Ops) const {
949  bool PartDef = false; // Partial redefine.
950  bool FullDef = false; // Full define.
951  bool Use = false;
952 
953  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
954  const MachineOperand &MO = getOperand(i);
955  if (!MO.isReg() || MO.getReg() != Reg)
956  continue;
957  if (Ops)
958  Ops->push_back(i);
959  if (MO.isUse())
960  Use |= !MO.isUndef();
961  else if (MO.getSubReg() && !MO.isUndef())
962  // A partial def undef doesn't count as reading the register.
963  PartDef = true;
964  else
965  FullDef = true;
966  }
967  // A partial redefine uses Reg unless there is also a full define.
968  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
969 }
970 
971 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
972 /// the specified register or -1 if it is not found. If isDead is true, defs
973 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
974 /// also checks if there is a def of a super-register.
975 int
976 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
977  const TargetRegisterInfo *TRI) const {
978  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
979  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
980  const MachineOperand &MO = getOperand(i);
981  // Accept regmask operands when Overlap is set.
982  // Ignore them when looking for a specific def operand (Overlap == false).
983  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
984  return i;
985  if (!MO.isReg() || !MO.isDef())
986  continue;
987  unsigned MOReg = MO.getReg();
988  bool Found = (MOReg == Reg);
989  if (!Found && TRI && isPhys &&
991  if (Overlap)
992  Found = TRI->regsOverlap(MOReg, Reg);
993  else
994  Found = TRI->isSubRegister(MOReg, Reg);
995  }
996  if (Found && (!isDead || MO.isDead()))
997  return i;
998  }
999  return -1;
1000 }
1001 
1002 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1003 /// operand list that is used to represent the predicate. It returns -1 if
1004 /// none is found.
1006  // Don't call MCID.findFirstPredOperandIdx() because this variant
1007  // is sometimes called on an instruction that's not yet complete, and
1008  // so the number of operands is less than the MCID indicates. In
1009  // particular, the PTX target does this.
1010  const MCInstrDesc &MCID = getDesc();
1011  if (MCID.isPredicable()) {
1012  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1013  if (MCID.OpInfo[i].isPredicate())
1014  return i;
1015  }
1016 
1017  return -1;
1018 }
1019 
1020 // MachineOperand::TiedTo is 4 bits wide.
1021 const unsigned TiedMax = 15;
1022 
1023 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1024 ///
1025 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1026 /// field. TiedTo can have these values:
1027 ///
1028 /// 0: Operand is not tied to anything.
1029 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1030 /// TiedMax: Tied to an operand >= TiedMax-1.
1031 ///
1032 /// The tied def must be one of the first TiedMax operands on a normal
1033 /// instruction. INLINEASM instructions allow more tied defs.
1034 ///
1035 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1036  MachineOperand &DefMO = getOperand(DefIdx);
1037  MachineOperand &UseMO = getOperand(UseIdx);
1038  assert(DefMO.isDef() && "DefIdx must be a def operand");
1039  assert(UseMO.isUse() && "UseIdx must be a use operand");
1040  assert(!DefMO.isTied() && "Def is already tied to another use");
1041  assert(!UseMO.isTied() && "Use is already tied to another def");
1042 
1043  if (DefIdx < TiedMax)
1044  UseMO.TiedTo = DefIdx + 1;
1045  else {
1046  // Inline asm can use the group descriptors to find tied operands, but on
1047  // normal instruction, the tied def must be within the first TiedMax
1048  // operands.
1049  assert(isInlineAsm() && "DefIdx out of range");
1050  UseMO.TiedTo = TiedMax;
1051  }
1052 
1053  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1054  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1055 }
1056 
1057 /// Given the index of a tied register operand, find the operand it is tied to.
1058 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1059 /// which must exist.
1060 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1061  const MachineOperand &MO = getOperand(OpIdx);
1062  assert(MO.isTied() && "Operand isn't tied");
1063 
1064  // Normally TiedTo is in range.
1065  if (MO.TiedTo < TiedMax)
1066  return MO.TiedTo - 1;
1067 
1068  // Uses on normal instructions can be out of range.
1069  if (!isInlineAsm()) {
1070  // Normal tied defs must be in the 0..TiedMax-1 range.
1071  if (MO.isUse())
1072  return TiedMax - 1;
1073  // MO is a def. Search for the tied use.
1074  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1075  const MachineOperand &UseMO = getOperand(i);
1076  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1077  return i;
1078  }
1079  llvm_unreachable("Can't find tied use");
1080  }
1081 
1082  // Now deal with inline asm by parsing the operand group descriptor flags.
1083  // Find the beginning of each operand group.
1084  SmallVector<unsigned, 8> GroupIdx;
1085  unsigned OpIdxGroup = ~0u;
1086  unsigned NumOps;
1087  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1088  i += NumOps) {
1089  const MachineOperand &FlagMO = getOperand(i);
1090  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1091  unsigned CurGroup = GroupIdx.size();
1092  GroupIdx.push_back(i);
1093  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1094  // OpIdx belongs to this operand group.
1095  if (OpIdx > i && OpIdx < i + NumOps)
1096  OpIdxGroup = CurGroup;
1097  unsigned TiedGroup;
1098  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1099  continue;
1100  // Operands in this group are tied to operands in TiedGroup which must be
1101  // earlier. Find the number of operands between the two groups.
1102  unsigned Delta = i - GroupIdx[TiedGroup];
1103 
1104  // OpIdx is a use tied to TiedGroup.
1105  if (OpIdxGroup == CurGroup)
1106  return OpIdx - Delta;
1107 
1108  // OpIdx is a def tied to this use group.
1109  if (OpIdxGroup == TiedGroup)
1110  return OpIdx + Delta;
1111  }
1112  llvm_unreachable("Invalid tied operand on inline asm");
1113 }
1114 
1115 /// clearKillInfo - Clears kill flags on all operands.
1116 ///
1118  for (MachineOperand &MO : operands()) {
1119  if (MO.isReg() && MO.isUse())
1120  MO.setIsKill(false);
1121  }
1122 }
1123 
1124 void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1125  unsigned SubIdx,
1126  const TargetRegisterInfo &RegInfo) {
1128  if (SubIdx)
1129  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1130  for (MachineOperand &MO : operands()) {
1131  if (!MO.isReg() || MO.getReg() != FromReg)
1132  continue;
1133  MO.substPhysReg(ToReg, RegInfo);
1134  }
1135  } else {
1136  for (MachineOperand &MO : operands()) {
1137  if (!MO.isReg() || MO.getReg() != FromReg)
1138  continue;
1139  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1140  }
1141  }
1142 }
1143 
1144 /// isSafeToMove - Return true if it is safe to move this instruction. If
1145 /// SawStore is set to true, it means that there is a store (or call) between
1146 /// the instruction's location and its intended destination.
1147 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1148  // Ignore stuff that we obviously can't move.
1149  //
1150  // Treat volatile loads as stores. This is not strictly necessary for
1151  // volatiles, but it is required for atomic loads. It is not allowed to move
1152  // a load across an atomic load with Ordering > Monotonic.
1153  if (mayStore() || isCall() || isPHI() ||
1154  (mayLoad() && hasOrderedMemoryRef())) {
1155  SawStore = true;
1156  return false;
1157  }
1158 
1159  if (isPosition() || isDebugInstr() || isTerminator() ||
1161  return false;
1162 
1163  // See if this instruction does a load. If so, we have to guarantee that the
1164  // loaded value doesn't change between the load and the its intended
1165  // destination. The check for isInvariantLoad gives the targe the chance to
1166  // classify the load as always returning a constant, e.g. a constant pool
1167  // load.
1169  // Otherwise, this is a real load. If there is a store between the load and
1170  // end of block, we can't move it.
1171  return !SawStore;
1172 
1173  return true;
1174 }
1175 
1177  bool UseTBAA) {
1178  const MachineFunction *MF = getMF();
1179  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1180  const MachineFrameInfo &MFI = MF->getFrameInfo();
1181 
1182  // If neither instruction stores to memory, they can't alias in any
1183  // meaningful way, even if they read from the same address.
1184  if (!mayStore() && !Other.mayStore())
1185  return false;
1186 
1187  // Let the target decide if memory accesses cannot possibly overlap.
1188  if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1189  return false;
1190 
1191  // FIXME: Need to handle multiple memory operands to support all targets.
1192  if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1193  return true;
1194 
1196  MachineMemOperand *MMOb = *Other.memoperands_begin();
1197 
1198  // The following interface to AA is fashioned after DAGCombiner::isAlias
1199  // and operates with MachineMemOperand offset with some important
1200  // assumptions:
1201  // - LLVM fundamentally assumes flat address spaces.
1202  // - MachineOperand offset can *only* result from legalization and
1203  // cannot affect queries other than the trivial case of overlap
1204  // checking.
1205  // - These offsets never wrap and never step outside
1206  // of allocated objects.
1207  // - There should never be any negative offsets here.
1208  //
1209  // FIXME: Modify API to hide this math from "user"
1210  // Even before we go to AA we can reason locally about some
1211  // memory objects. It can save compile time, and possibly catch some
1212  // corner cases not currently covered.
1213 
1214  int64_t OffsetA = MMOa->getOffset();
1215  int64_t OffsetB = MMOb->getOffset();
1216  int64_t MinOffset = std::min(OffsetA, OffsetB);
1217 
1218  uint64_t WidthA = MMOa->getSize();
1219  uint64_t WidthB = MMOb->getSize();
1220  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1221  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1222 
1223  const Value *ValA = MMOa->getValue();
1224  const Value *ValB = MMOb->getValue();
1225  bool SameVal = (ValA && ValB && (ValA == ValB));
1226  if (!SameVal) {
1227  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1228  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1229  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1230  return false;
1231  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1232  return false;
1233  if (PSVa && PSVb && (PSVa == PSVb))
1234  SameVal = true;
1235  }
1236 
1237  if (SameVal) {
1238  if (!KnownWidthA || !KnownWidthB)
1239  return true;
1240  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1241  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1242  return (MinOffset + LowWidth > MaxOffset);
1243  }
1244 
1245  if (!AA)
1246  return true;
1247 
1248  if (!ValA || !ValB)
1249  return true;
1250 
1251  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1252  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1253 
1254  int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1256  int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1258 
1259  AliasResult AAResult = AA->alias(
1260  MemoryLocation(ValA, OverlapA,
1261  UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1262  MemoryLocation(ValB, OverlapB,
1263  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1264 
1265  return (AAResult != NoAlias);
1266 }
1267 
1268 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1269 /// or volatile memory reference, or if the information describing the memory
1270 /// reference is not available. Return false if it is known to have no ordered
1271 /// memory references.
1273  // An instruction known never to access memory won't have a volatile access.
1274  if (!mayStore() &&
1275  !mayLoad() &&
1276  !isCall() &&
1278  return false;
1279 
1280  // Otherwise, if the instruction has no memory reference information,
1281  // conservatively assume it wasn't preserved.
1282  if (memoperands_empty())
1283  return true;
1284 
1285  // Check if any of our memory operands are ordered.
1286  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1287  return !MMO->isUnordered();
1288  });
1289 }
1290 
1291 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1292 /// trap and is loading from a location whose value is invariant across a run of
1293 /// this function.
1295  // If the instruction doesn't load at all, it isn't an invariant load.
1296  if (!mayLoad())
1297  return false;
1298 
1299  // If the instruction has lost its memoperands, conservatively assume that
1300  // it may not be an invariant load.
1301  if (memoperands_empty())
1302  return false;
1303 
1304  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1305 
1306  for (MachineMemOperand *MMO : memoperands()) {
1307  if (MMO->isVolatile()) return false;
1308  if (MMO->isStore()) return false;
1309  if (MMO->isInvariant() && MMO->isDereferenceable())
1310  continue;
1311 
1312  // A load from a constant PseudoSourceValue is invariant.
1313  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1314  if (PSV->isConstant(&MFI))
1315  continue;
1316 
1317  if (const Value *V = MMO->getValue()) {
1318  // If we have an AliasAnalysis, ask it whether the memory is constant.
1319  if (AA &&
1321  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1322  continue;
1323  }
1324 
1325  // Otherwise assume conservatively.
1326  return false;
1327  }
1328 
1329  // Everything checks out.
1330  return true;
1331 }
1332 
1333 /// isConstantValuePHI - If the specified instruction is a PHI that always
1334 /// merges together the same virtual register, return the register, otherwise
1335 /// return 0.
1337  if (!isPHI())
1338  return 0;
1339  assert(getNumOperands() >= 3 &&
1340  "It's illegal to have a PHI without source operands");
1341 
1342  unsigned Reg = getOperand(1).getReg();
1343  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1344  if (getOperand(i).getReg() != Reg)
1345  return 0;
1346  return Reg;
1347 }
1348 
1351  return true;
1352  if (isInlineAsm()) {
1353  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1354  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1355  return true;
1356  }
1357 
1358  return false;
1359 }
1360 
1362  return mayStore() || isCall() || hasUnmodeledSideEffects();
1363 }
1364 
1365 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1366 ///
1368  for (const MachineOperand &MO : operands()) {
1369  if (!MO.isReg() || MO.isUse())
1370  continue;
1371  if (!MO.isDead())
1372  return false;
1373  }
1374  return true;
1375 }
1376 
1377 /// copyImplicitOps - Copy implicit register operands from specified
1378 /// instruction to this instruction.
1380  const MachineInstr &MI) {
1381  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1382  i != e; ++i) {
1383  const MachineOperand &MO = MI.getOperand(i);
1384  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1385  addOperand(MF, MO);
1386  }
1387 }
1388 
1390  const MCInstrDesc &MCID = getDesc();
1391  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1392  const auto &Operand = getOperand(I);
1393  if (!Operand.isReg() || Operand.isDef())
1394  // Ignore the defined registers as MCID marks only the uses as tied.
1395  continue;
1396  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1397  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1398  if (ExpectedTiedIdx != TiedIdx)
1399  return true;
1400  }
1401  return false;
1402 }
1403 
1404 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1405  const MachineRegisterInfo &MRI) const {
1406  const MachineOperand &Op = getOperand(OpIdx);
1407  if (!Op.isReg())
1408  return LLT{};
1409 
1410  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1411  return MRI.getType(Op.getReg());
1412 
1413  auto &OpInfo = getDesc().OpInfo[OpIdx];
1414  if (!OpInfo.isGenericType())
1415  return MRI.getType(Op.getReg());
1416 
1417  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1418  return LLT{};
1419 
1420  LLT TypeToPrint = MRI.getType(Op.getReg());
1421  // Don't mark the type index printed if it wasn't actually printed: maybe
1422  // another operand with the same type index has an actual type attached:
1423  if (TypeToPrint.isValid())
1424  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1425  return TypeToPrint;
1426 }
1427 
1428 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1430  dbgs() << " ";
1431  print(dbgs());
1432 }
1433 #endif
1434 
1435 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1436  bool SkipDebugLoc, bool AddNewLine,
1437  const TargetInstrInfo *TII) const {
1438  const Module *M = nullptr;
1439  const Function *F = nullptr;
1440  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1441  F = &MF->getFunction();
1442  M = F->getParent();
1443  if (!TII)
1444  TII = MF->getSubtarget().getInstrInfo();
1445  }
1446 
1447  ModuleSlotTracker MST(M);
1448  if (F)
1449  MST.incorporateFunction(*F);
1450  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1451 }
1452 
1454  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1455  bool AddNewLine, const TargetInstrInfo *TII) const {
1456  // We can be a bit tidier if we know the MachineFunction.
1457  const MachineFunction *MF = nullptr;
1458  const TargetRegisterInfo *TRI = nullptr;
1459  const MachineRegisterInfo *MRI = nullptr;
1460  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1461  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1462 
1463  if (isCFIInstruction())
1464  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1465 
1466  SmallBitVector PrintedTypes(8);
1467  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1468  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1469  if (!ShouldPrintRegisterTies)
1470  return 0U;
1471  const MachineOperand &MO = getOperand(OpIdx);
1472  if (MO.isReg() && MO.isTied() && !MO.isDef())
1473  return findTiedOperandIdx(OpIdx);
1474  return 0U;
1475  };
1476  unsigned StartOp = 0;
1477  unsigned e = getNumOperands();
1478 
1479  // Print explicitly defined operands on the left of an assignment syntax.
1480  while (StartOp < e) {
1481  const MachineOperand &MO = getOperand(StartOp);
1482  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1483  break;
1484 
1485  if (StartOp != 0)
1486  OS << ", ";
1487 
1488  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1489  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1490  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1491  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1492  ++StartOp;
1493  }
1494 
1495  if (StartOp != 0)
1496  OS << " = ";
1497 
1499  OS << "frame-setup ";
1501  OS << "frame-destroy ";
1503  OS << "nnan ";
1505  OS << "ninf ";
1507  OS << "nsz ";
1509  OS << "arcp ";
1511  OS << "contract ";
1513  OS << "afn ";
1515  OS << "reassoc ";
1517  OS << "nuw ";
1519  OS << "nsw ";
1521  OS << "exact ";
1522 
1523  // Print the opcode name.
1524  if (TII)
1525  OS << TII->getName(getOpcode());
1526  else
1527  OS << "UNKNOWN";
1528 
1529  if (SkipOpers)
1530  return;
1531 
1532  // Print the rest of the operands.
1533  bool FirstOp = true;
1534  unsigned AsmDescOp = ~0u;
1535  unsigned AsmOpCount = 0;
1536 
1537  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1538  // Print asm string.
1539  OS << " ";
1540  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1541  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1542  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1543  getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1544  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1545  IntrinsicInfo);
1546 
1547  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1548  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1549  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1550  OS << " [sideeffect]";
1551  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1552  OS << " [mayload]";
1553  if (ExtraInfo & InlineAsm::Extra_MayStore)
1554  OS << " [maystore]";
1555  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1556  OS << " [isconvergent]";
1557  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1558  OS << " [alignstack]";
1560  OS << " [attdialect]";
1562  OS << " [inteldialect]";
1563 
1564  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1565  FirstOp = false;
1566  }
1567 
1568  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1569  const MachineOperand &MO = getOperand(i);
1570 
1571  if (FirstOp) FirstOp = false; else OS << ",";
1572  OS << " ";
1573 
1574  if (isDebugValue() && MO.isMetadata()) {
1575  // Pretty print DBG_VALUE instructions.
1576  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1577  if (DIV && !DIV->getName().empty())
1578  OS << "!\"" << DIV->getName() << '\"';
1579  else {
1580  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1581  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1582  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1583  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1584  }
1585  } else if (isDebugLabel() && MO.isMetadata()) {
1586  // Pretty print DBG_LABEL instructions.
1587  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1588  if (DIL && !DIL->getName().empty())
1589  OS << "\"" << DIL->getName() << '\"';
1590  else {
1591  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1592  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1593  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1594  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1595  }
1596  } else if (i == AsmDescOp && MO.isImm()) {
1597  // Pretty print the inline asm operand descriptor.
1598  OS << '$' << AsmOpCount++;
1599  unsigned Flag = MO.getImm();
1600  switch (InlineAsm::getKind(Flag)) {
1601  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1602  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1603  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1604  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1605  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1606  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1607  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1608  }
1609 
1610  unsigned RCID = 0;
1611  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1612  InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1613  if (TRI) {
1614  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1615  } else
1616  OS << ":RC" << RCID;
1617  }
1618 
1619  if (InlineAsm::isMemKind(Flag)) {
1620  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1621  switch (MCID) {
1622  case InlineAsm::Constraint_es: OS << ":es"; break;
1623  case InlineAsm::Constraint_i: OS << ":i"; break;
1624  case InlineAsm::Constraint_m: OS << ":m"; break;
1625  case InlineAsm::Constraint_o: OS << ":o"; break;
1626  case InlineAsm::Constraint_v: OS << ":v"; break;
1627  case InlineAsm::Constraint_Q: OS << ":Q"; break;
1628  case InlineAsm::Constraint_R: OS << ":R"; break;
1629  case InlineAsm::Constraint_S: OS << ":S"; break;
1630  case InlineAsm::Constraint_T: OS << ":T"; break;
1631  case InlineAsm::Constraint_Um: OS << ":Um"; break;
1632  case InlineAsm::Constraint_Un: OS << ":Un"; break;
1633  case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1634  case InlineAsm::Constraint_Us: OS << ":Us"; break;
1635  case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1636  case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1637  case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1638  case InlineAsm::Constraint_X: OS << ":X"; break;
1639  case InlineAsm::Constraint_Z: OS << ":Z"; break;
1640  case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1641  case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1642  default: OS << ":?"; break;
1643  }
1644  }
1645 
1646  unsigned TiedTo = 0;
1647  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1648  OS << " tiedto:$" << TiedTo;
1649 
1650  OS << ']';
1651 
1652  // Compute the index of the next operand descriptor.
1653  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1654  } else {
1655  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1656  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1657  if (MO.isImm() && isOperandSubregIdx(i))
1659  else
1660  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1661  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1662  }
1663  }
1664 
1665  // Print any optional symbols attached to this instruction as-if they were
1666  // operands.
1667  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1668  if (!FirstOp) {
1669  FirstOp = false;
1670  OS << ',';
1671  }
1672  OS << " pre-instr-symbol ";
1673  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1674  }
1675  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1676  if (!FirstOp) {
1677  FirstOp = false;
1678  OS << ',';
1679  }
1680  OS << " post-instr-symbol ";
1681  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1682  }
1683 
1684  if (!SkipDebugLoc) {
1685  if (const DebugLoc &DL = getDebugLoc()) {
1686  if (!FirstOp)
1687  OS << ',';
1688  OS << " debug-location ";
1689  DL->printAsOperand(OS, MST);
1690  }
1691  }
1692 
1693  if (!memoperands_empty()) {
1695  const LLVMContext *Context = nullptr;
1696  std::unique_ptr<LLVMContext> CtxPtr;
1697  const MachineFrameInfo *MFI = nullptr;
1698  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1699  MFI = &MF->getFrameInfo();
1700  Context = &MF->getFunction().getContext();
1701  } else {
1702  CtxPtr = llvm::make_unique<LLVMContext>();
1703  Context = CtxPtr.get();
1704  }
1705 
1706  OS << " :: ";
1707  bool NeedComma = false;
1708  for (const MachineMemOperand *Op : memoperands()) {
1709  if (NeedComma)
1710  OS << ", ";
1711  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1712  NeedComma = true;
1713  }
1714  }
1715 
1716  if (SkipDebugLoc)
1717  return;
1718 
1719  bool HaveSemi = false;
1720 
1721  // Print debug location information.
1722  if (const DebugLoc &DL = getDebugLoc()) {
1723  if (!HaveSemi) {
1724  OS << ';';
1725  HaveSemi = true;
1726  }
1727  OS << ' ';
1728  DL.print(OS);
1729  }
1730 
1731  // Print extra comments for DEBUG_VALUE.
1732  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1733  if (!HaveSemi) {
1734  OS << ";";
1735  HaveSemi = true;
1736  }
1737  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1738  OS << " line no:" << DV->getLine();
1739  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1740  DebugLoc InlinedAtDL(InlinedAt);
1741  if (InlinedAtDL && MF) {
1742  OS << " inlined @[ ";
1743  InlinedAtDL.print(OS);
1744  OS << " ]";
1745  }
1746  }
1747  if (isIndirectDebugValue())
1748  OS << " indirect";
1749  }
1750  // TODO: DBG_LABEL
1751 
1752  if (AddNewLine)
1753  OS << '\n';
1754 }
1755 
1756 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1757  const TargetRegisterInfo *RegInfo,
1758  bool AddIfNotFound) {
1759  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1760  bool hasAliases = isPhysReg &&
1761  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1762  bool Found = false;
1763  SmallVector<unsigned,4> DeadOps;
1764  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1765  MachineOperand &MO = getOperand(i);
1766  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1767  continue;
1768 
1769  // DEBUG_VALUE nodes do not contribute to code generation and should
1770  // always be ignored. Failure to do so may result in trying to modify
1771  // KILL flags on DEBUG_VALUE nodes.
1772  if (MO.isDebug())
1773  continue;
1774 
1775  unsigned Reg = MO.getReg();
1776  if (!Reg)
1777  continue;
1778 
1779  if (Reg == IncomingReg) {
1780  if (!Found) {
1781  if (MO.isKill())
1782  // The register is already marked kill.
1783  return true;
1784  if (isPhysReg && isRegTiedToDefOperand(i))
1785  // Two-address uses of physregs must not be marked kill.
1786  return true;
1787  MO.setIsKill();
1788  Found = true;
1789  }
1790  } else if (hasAliases && MO.isKill() &&
1792  // A super-register kill already exists.
1793  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1794  return true;
1795  if (RegInfo->isSubRegister(IncomingReg, Reg))
1796  DeadOps.push_back(i);
1797  }
1798  }
1799 
1800  // Trim unneeded kill operands.
1801  while (!DeadOps.empty()) {
1802  unsigned OpIdx = DeadOps.back();
1803  if (getOperand(OpIdx).isImplicit() &&
1804  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1805  RemoveOperand(OpIdx);
1806  else
1807  getOperand(OpIdx).setIsKill(false);
1808  DeadOps.pop_back();
1809  }
1810 
1811  // If not found, this means an alias of one of the operands is killed. Add a
1812  // new implicit operand if required.
1813  if (!Found && AddIfNotFound) {
1815  false /*IsDef*/,
1816  true /*IsImp*/,
1817  true /*IsKill*/));
1818  return true;
1819  }
1820  return Found;
1821 }
1822 
1824  const TargetRegisterInfo *RegInfo) {
1826  RegInfo = nullptr;
1827  for (MachineOperand &MO : operands()) {
1828  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1829  continue;
1830  unsigned OpReg = MO.getReg();
1831  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1832  MO.setIsKill(false);
1833  }
1834 }
1835 
1837  const TargetRegisterInfo *RegInfo,
1838  bool AddIfNotFound) {
1839  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1840  bool hasAliases = isPhysReg &&
1841  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1842  bool Found = false;
1843  SmallVector<unsigned,4> DeadOps;
1844  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1845  MachineOperand &MO = getOperand(i);
1846  if (!MO.isReg() || !MO.isDef())
1847  continue;
1848  unsigned MOReg = MO.getReg();
1849  if (!MOReg)
1850  continue;
1851 
1852  if (MOReg == Reg) {
1853  MO.setIsDead();
1854  Found = true;
1855  } else if (hasAliases && MO.isDead() &&
1857  // There exists a super-register that's marked dead.
1858  if (RegInfo->isSuperRegister(Reg, MOReg))
1859  return true;
1860  if (RegInfo->isSubRegister(Reg, MOReg))
1861  DeadOps.push_back(i);
1862  }
1863  }
1864 
1865  // Trim unneeded dead operands.
1866  while (!DeadOps.empty()) {
1867  unsigned OpIdx = DeadOps.back();
1868  if (getOperand(OpIdx).isImplicit() &&
1869  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1870  RemoveOperand(OpIdx);
1871  else
1872  getOperand(OpIdx).setIsDead(false);
1873  DeadOps.pop_back();
1874  }
1875 
1876  // If not found, this means an alias of one of the operands is dead. Add a
1877  // new implicit operand if required.
1878  if (Found || !AddIfNotFound)
1879  return Found;
1880 
1882  true /*IsDef*/,
1883  true /*IsImp*/,
1884  false /*IsKill*/,
1885  true /*IsDead*/));
1886  return true;
1887 }
1888 
1890  for (MachineOperand &MO : operands()) {
1891  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1892  continue;
1893  MO.setIsDead(false);
1894  }
1895 }
1896 
1897 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1898  for (MachineOperand &MO : operands()) {
1899  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1900  continue;
1901  MO.setIsUndef(IsUndef);
1902  }
1903 }
1904 
1906  const TargetRegisterInfo *RegInfo) {
1908  MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1909  if (MO)
1910  return;
1911  } else {
1912  for (const MachineOperand &MO : operands()) {
1913  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1914  MO.getSubReg() == 0)
1915  return;
1916  }
1917  }
1919  true /*IsDef*/,
1920  true /*IsImp*/));
1921 }
1922 
1924  const TargetRegisterInfo &TRI) {
1925  bool HasRegMask = false;
1926  for (MachineOperand &MO : operands()) {
1927  if (MO.isRegMask()) {
1928  HasRegMask = true;
1929  continue;
1930  }
1931  if (!MO.isReg() || !MO.isDef()) continue;
1932  unsigned Reg = MO.getReg();
1933  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1934  // If there are no uses, including partial uses, the def is dead.
1935  if (llvm::none_of(UsedRegs,
1936  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1937  MO.setIsDead();
1938  }
1939 
1940  // This is a call with a register mask operand.
1941  // Mask clobbers are always dead, so add defs for the non-dead defines.
1942  if (HasRegMask)
1943  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1944  I != E; ++I)
1945  addRegisterDefined(*I, &TRI);
1946 }
1947 
1948 unsigned
1950  // Build up a buffer of hash code components.
1951  SmallVector<size_t, 8> HashComponents;
1952  HashComponents.reserve(MI->getNumOperands() + 1);
1953  HashComponents.push_back(MI->getOpcode());
1954  for (const MachineOperand &MO : MI->operands()) {
1955  if (MO.isReg() && MO.isDef() &&
1957  continue; // Skip virtual register defs.
1958 
1959  HashComponents.push_back(hash_value(MO));
1960  }
1961  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1962 }
1963 
1965  // Find the source location cookie.
1966  unsigned LocCookie = 0;
1967  const MDNode *LocMD = nullptr;
1968  for (unsigned i = getNumOperands(); i != 0; --i) {
1969  if (getOperand(i-1).isMetadata() &&
1970  (LocMD = getOperand(i-1).getMetadata()) &&
1971  LocMD->getNumOperands() != 0) {
1972  if (const ConstantInt *CI =
1973  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1974  LocCookie = CI->getZExtValue();
1975  break;
1976  }
1977  }
1978  }
1979 
1980  if (const MachineBasicBlock *MBB = getParent())
1981  if (const MachineFunction *MF = MBB->getParent())
1982  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1983  report_fatal_error(Msg);
1984 }
1985 
1987  const MCInstrDesc &MCID, bool IsIndirect,
1988  unsigned Reg, const MDNode *Variable,
1989  const MDNode *Expr) {
1990  assert(isa<DILocalVariable>(Variable) && "not a variable");
1991  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1992  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
1993  "Expected inlined-at fields to agree");
1994  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
1995  if (IsIndirect)
1996  MIB.addImm(0U);
1997  else
1998  MIB.addReg(0U, RegState::Debug);
1999  return MIB.addMetadata(Variable).addMetadata(Expr);
2000 }
2001 
2003  const MCInstrDesc &MCID, bool IsIndirect,
2004  MachineOperand &MO, const MDNode *Variable,
2005  const MDNode *Expr) {
2006  assert(isa<DILocalVariable>(Variable) && "not a variable");
2007  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2008  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2009  "Expected inlined-at fields to agree");
2010  if (MO.isReg())
2011  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2012 
2013  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2014  if (IsIndirect)
2015  MIB.addImm(0U);
2016  else
2017  MIB.addReg(0U, RegState::Debug);
2018  return MIB.addMetadata(Variable).addMetadata(Expr);
2019  }
2020 
2023  const DebugLoc &DL, const MCInstrDesc &MCID,
2024  bool IsIndirect, unsigned Reg,
2025  const MDNode *Variable, const MDNode *Expr) {
2026  MachineFunction &MF = *BB.getParent();
2027  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2028  BB.insert(I, MI);
2029  return MachineInstrBuilder(MF, MI);
2030 }
2031 
2034  const DebugLoc &DL, const MCInstrDesc &MCID,
2035  bool IsIndirect, MachineOperand &MO,
2036  const MDNode *Variable, const MDNode *Expr) {
2037  MachineFunction &MF = *BB.getParent();
2038  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2039  BB.insert(I, MI);
2040  return MachineInstrBuilder(MF, *MI);
2041 }
2042 
2043 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2044 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2046  assert(MI.getOperand(0).isReg() && "can't spill non-register");
2048  "Expected inlined-at fields to agree");
2049 
2050  const DIExpression *Expr = MI.getDebugExpression();
2051  if (MI.isIndirectDebugValue()) {
2052  assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
2054  }
2055  return Expr;
2056 }
2057 
2060  const MachineInstr &Orig,
2061  int FrameIndex) {
2062  const DIExpression *Expr = computeExprForSpill(Orig);
2063  return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2064  .addFrameIndex(FrameIndex)
2065  .addImm(0U)
2066  .addMetadata(Orig.getDebugVariable())
2067  .addMetadata(Expr);
2068 }
2069 
2071  const DIExpression *Expr = computeExprForSpill(Orig);
2072  Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2073  Orig.getOperand(1).ChangeToImmediate(0U);
2074  Orig.getOperand(3).setMetadata(Expr);
2075 }
2076 
2078  SmallVectorImpl<MachineInstr *> &DbgValues) {
2079  MachineInstr &MI = *this;
2080  if (!MI.getOperand(0).isReg())
2081  return;
2082 
2083  MachineBasicBlock::iterator DI = MI; ++DI;
2084  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2085  DI != DE; ++DI) {
2086  if (!DI->isDebugValue())
2087  return;
2088  if (DI->getOperand(0).isReg() &&
2089  DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2090  DbgValues.push_back(&*DI);
2091  }
2092 }
2093 
2095  // Collect matching debug values.
2097  collectDebugValues(DbgValues);
2098 
2099  // Propagate Reg to debug value instructions.
2100  for (auto *DBI : DbgValues)
2101  DBI->getOperand(0).setReg(Reg);
2102 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool Check(DecodeStatus &Out, DecodeStatus In)
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:521
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
bool isUnordered() const
Returns true if this memory operation doesn&#39;t have any ordering constraints other than normal aliasin...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isDebugLabel() const
Definition: MachineInstr.h:998
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
bool noNaNs() const
Definition: Operator.h:200
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:543
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
iterator begin() const
Definition: ArrayRef.h:137
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static const DIExpression * computeExprForSpill(const MachineInstr &MI)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
bool isCFIInstruction() const
Definition: MachineInstr.h:990
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:362
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:518
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
This file contains the declarations for metadata subclasses.
unsigned getSubReg() const
bool isInlineAsm() const
The two locations do not alias at all.
Definition: AliasAnalysis.h:85
bool noInfs() const
Definition: Operator.h:201
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:864
void setIsDead(bool Val=true)
F(f)
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1069
Manage lifetime of a slot tracker for printing IR.
void reserve(size_type N)
Definition: SmallVector.h:376
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
bool isPHI() const
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:119
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:276
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DIExpression * prepend(const DIExpression *Expr, bool DerefBefore, int64_t Offset=0, bool DerefAfter=false, bool StackValue=false)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void clearKillInfo()
Clears kill flags on all operands.
AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
The main low level interface to the alias analysis implementation.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
A description of a memory reference used in the backend.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:366
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:243
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1062
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:649
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void bundleWithSucc()
Bundle this instruction with its successor.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand *> MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
bool isValid() const
isValid - Returns true until all the operands have been visited.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isBundle() const
struct llvm::MachineOperand::@159::@161 Reg
void changeDebugValuesDefReg(unsigned Reg)
Find all DBG_VALUEs immediately following this instruction that point to a register def in this instr...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4431
bool allowContract() const
Definition: Operator.h:204
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
virtual const TargetInstrInfo * getInstrInfo() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:93
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:555
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr&#39;s memory reference descriptor list.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
AliasResult
The possible results of an alias query.
Definition: AliasAnalysis.h:79
const Value * getValue() const
Return the base address of the memory access.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:540
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
unsigned const MachineRegisterInfo * MRI
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:516
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:429
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed...
Definition: Operator.h:120
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:300
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:311
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:549
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1055
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:329
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl...
Definition: Operator.h:67
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool allowReciprocal() const
Definition: Operator.h:203
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:307
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:842
bool isStackAligningInlineAsm() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:277
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
size_t size() const
Definition: SmallVector.h:53
bool isDebugInstr() const
Definition: MachineInstr.h:999
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:567
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
void setIsKill(bool Val=true)
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
Representation for a specific memory location.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s memory reference descriptor list and replace ours with it...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
InlineAsm::AsmDialect getInlineAsmDialect() const
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:534
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
void setFlags(unsigned flags)
Definition: MachineInstr.h:304
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:997
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:240
Module.h This file contains the declarations for the Module class.
iterator end() const
Definition: ArrayRef.h:138
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:644
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:607
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
int64_t getImm() const
void setMetadata(const MDNode *MD)
DWARF expression.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:592
Special value supplied for machine level alias analysis.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:479
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:179
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:394
const unsigned TiedMax
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:581
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
This file provides utility analysis objects describing memory locations.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
Clone the merge of multiple MachineInstrs&#39; memory reference descriptors list and replace ours with it...
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:303
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand *> LHS, ArrayRef< MachineMemOperand *> RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
uint32_t Size
Definition: Profile.cpp:47
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
const Module * getModule() const
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:290
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:546
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void unbundleFromSucc()
Break bundle below this instruction.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
bool isPosition() const
Definition: MachineInstr.h:995
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
bool allowReassoc() const
Flag queries.
Definition: Operator.h:199
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:160
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool approxFunc() const
Definition: Operator.h:205
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1075
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:295
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
const MDNode * getMetadata() const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool noSignedZeros() const
Definition: Operator.h:202
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:541
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
bool isImplicit() const
Metadata reference (for debug info)
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:70
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.