LLVM  7.0.0svn
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/FoldingSet.h"
18 #include "llvm/ADT/Hashing.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Analysis/Loads.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
53 #include "llvm/IR/Type.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/MC/MCInstrDesc.h"
56 #include "llvm/MC/MCRegisterInfo.h"
57 #include "llvm/MC/MCSymbol.h"
58 #include "llvm/Support/Casting.h"
60 #include "llvm/Support/Compiler.h"
61 #include "llvm/Support/Debug.h"
68 #include <algorithm>
69 #include <cassert>
70 #include <cstddef>
71 #include <cstdint>
72 #include <cstring>
73 #include <iterator>
74 #include <utility>
75 
76 using namespace llvm;
77 
79  if (const MachineBasicBlock *MBB = MI.getParent())
80  if (const MachineFunction *MF = MBB->getParent())
81  return MF;
82  return nullptr;
83 }
84 
85 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
86 // it.
87 static void tryToGetTargetInfo(const MachineInstr &MI,
88  const TargetRegisterInfo *&TRI,
89  const MachineRegisterInfo *&MRI,
90  const TargetIntrinsicInfo *&IntrinsicInfo,
91  const TargetInstrInfo *&TII) {
92 
93  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
94  TRI = MF->getSubtarget().getRegisterInfo();
95  MRI = &MF->getRegInfo();
96  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
97  TII = MF->getSubtarget().getInstrInfo();
98  }
99 }
100 
102  if (MCID->ImplicitDefs)
103  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
104  ++ImpDefs)
105  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
106  if (MCID->ImplicitUses)
107  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
108  ++ImpUses)
109  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
110 }
111 
112 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
113 /// implicit operands. It reserves space for the number of operands specified by
114 /// the MCInstrDesc.
115 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
116  DebugLoc dl, bool NoImp)
117  : MCID(&tid), debugLoc(std::move(dl)) {
118  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
119 
120  // Reserve space for the expected number of operands.
121  if (unsigned NumOps = MCID->getNumOperands() +
122  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
123  CapOperands = OperandCapacity::get(NumOps);
124  Operands = MF.allocateOperandArray(CapOperands);
125  }
126 
127  if (!NoImp)
129 }
130 
131 /// MachineInstr ctor - Copies MachineInstr arg exactly
132 ///
133 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
134  : MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
135  debugLoc(MI.getDebugLoc()) {
136  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
137 
138  CapOperands = OperandCapacity::get(MI.getNumOperands());
139  Operands = MF.allocateOperandArray(CapOperands);
140 
141  // Copy operands.
142  for (const MachineOperand &MO : MI.operands())
143  addOperand(MF, MO);
144 
145  // Copy all the sensible flags.
146  setFlags(MI.Flags);
147 }
148 
149 /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 /// return the MachineRegisterInfo object for the current function, otherwise
151 /// return null.
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
153  if (MachineBasicBlock *MBB = getParent())
154  return &MBB->getParent()->getRegInfo();
155  return nullptr;
156 }
157 
158 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 /// this instruction from their respective use lists. This requires that the
160 /// operands already be on their use lists.
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162  for (MachineOperand &MO : operands())
163  if (MO.isReg())
165 }
166 
167 /// AddRegOperandsToUseLists - Add all of the register operands in
168 /// this instruction from their respective use lists. This requires that the
169 /// operands not be on their use lists yet.
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171  for (MachineOperand &MO : operands())
172  if (MO.isReg())
173  MRI.addRegOperandToUseList(&MO);
174 }
175 
177  MachineBasicBlock *MBB = getParent();
178  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179  MachineFunction *MF = MBB->getParent();
180  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
181  addOperand(*MF, Op);
182 }
183 
184 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 /// ranges. If MRI is non-null also update use-def chains.
187  unsigned NumOps, MachineRegisterInfo *MRI) {
188  if (MRI)
189  return MRI->moveOperands(Dst, Src, NumOps);
190 
191  // MachineOperand is a trivially copyable type so we can just use memmove.
192  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193 }
194 
195 /// addOperand - Add the specified operand to the instruction. If it is an
196 /// implicit operand, it is added to the end of the operand list. If it is
197 /// an explicit operand it is added at the end of the explicit operand list
198 /// (before the first implicit operand).
200  assert(MCID && "Cannot add operands before providing an instr descriptor");
201 
202  // Check if we're adding one of our existing operands.
203  if (&Op >= Operands && &Op < Operands + NumOperands) {
204  // This is unusual: MI->addOperand(MI->getOperand(i)).
205  // If adding Op requires reallocating or moving existing operands around,
206  // the Op reference could go stale. Support it by copying Op.
207  MachineOperand CopyOp(Op);
208  return addOperand(MF, CopyOp);
209  }
210 
211  // Find the insert location for the new operand. Implicit registers go at
212  // the end, everything else goes before the implicit regs.
213  //
214  // FIXME: Allow mixed explicit and implicit operands on inline asm.
215  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216  // implicit-defs, but they must not be moved around. See the FIXME in
217  // InstrEmitter.cpp.
218  unsigned OpNo = getNumOperands();
219  bool isImpReg = Op.isReg() && Op.isImplicit();
220  if (!isImpReg && !isInlineAsm()) {
221  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
222  --OpNo;
223  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
224  }
225  }
226 
227 #ifndef NDEBUG
228  bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
229  // OpNo now points as the desired insertion point. Unless this is a variadic
230  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
231  // RegMask operands go between the explicit and implicit operands.
232  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
233  OpNo < MCID->getNumOperands() || isMetaDataOp) &&
234  "Trying to add an operand to a machine instr that is already done!");
235 #endif
236 
237  MachineRegisterInfo *MRI = getRegInfo();
238 
239  // Determine if the Operands array needs to be reallocated.
240  // Save the old capacity and operand array.
241  OperandCapacity OldCap = CapOperands;
242  MachineOperand *OldOperands = Operands;
243  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
244  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
245  Operands = MF.allocateOperandArray(CapOperands);
246  // Move the operands before the insertion point.
247  if (OpNo)
248  moveOperands(Operands, OldOperands, OpNo, MRI);
249  }
250 
251  // Move the operands following the insertion point.
252  if (OpNo != NumOperands)
253  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
254  MRI);
255  ++NumOperands;
256 
257  // Deallocate the old operand array.
258  if (OldOperands != Operands && OldOperands)
259  MF.deallocateOperandArray(OldCap, OldOperands);
260 
261  // Copy Op into place. It still needs to be inserted into the MRI use lists.
262  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
263  NewMO->ParentMI = this;
264 
265  // When adding a register operand, tell MRI about it.
266  if (NewMO->isReg()) {
267  // Ensure isOnRegUseList() returns false, regardless of Op's status.
268  NewMO->Contents.Reg.Prev = nullptr;
269  // Ignore existing ties. This is not a property that can be copied.
270  NewMO->TiedTo = 0;
271  // Add the new operand to MRI, but only for instructions in an MBB.
272  if (MRI)
273  MRI->addRegOperandToUseList(NewMO);
274  // The MCID operand information isn't accurate until we start adding
275  // explicit operands. The implicit operands are added first, then the
276  // explicits are inserted before them.
277  if (!isImpReg) {
278  // Tie uses to defs as indicated in MCInstrDesc.
279  if (NewMO->isUse()) {
280  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
281  if (DefIdx != -1)
282  tieOperands(DefIdx, OpNo);
283  }
284  // If the register operand is flagged as early, mark the operand as such.
285  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
286  NewMO->setIsEarlyClobber(true);
287  }
288  }
289 }
290 
291 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
292 /// fewer operand than it started with.
293 ///
294 void MachineInstr::RemoveOperand(unsigned OpNo) {
295  assert(OpNo < getNumOperands() && "Invalid operand number");
296  untieRegOperand(OpNo);
297 
298 #ifndef NDEBUG
299  // Moving tied operands would break the ties.
300  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
301  if (Operands[i].isReg())
302  assert(!Operands[i].isTied() && "Cannot move tied operands");
303 #endif
304 
305  MachineRegisterInfo *MRI = getRegInfo();
306  if (MRI && Operands[OpNo].isReg())
307  MRI->removeRegOperandFromUseList(Operands + OpNo);
308 
309  // Don't call the MachineOperand destructor. A lot of this code depends on
310  // MachineOperand having a trivial destructor anyway, and adding a call here
311  // wouldn't make it 'destructor-correct'.
312 
313  if (unsigned N = NumOperands - 1 - OpNo)
314  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
315  --NumOperands;
316 }
317 
318 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
319 /// This function should be used only occasionally. The setMemRefs function
320 /// is the primary method for setting up a MachineInstr's MemRefs list.
322  MachineMemOperand *MO) {
323  mmo_iterator OldMemRefs = MemRefs;
324  unsigned OldNumMemRefs = NumMemRefs;
325 
326  unsigned NewNum = NumMemRefs + 1;
327  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
328 
329  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
330  NewMemRefs[NewNum - 1] = MO;
331  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
332 }
333 
334 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
335 /// identical.
336 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
337  auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
338  auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
339  if ((E1 - I1) != (E2 - I2))
340  return false;
341  for (; I1 != E1; ++I1, ++I2) {
342  if (**I1 != **I2)
343  return false;
344  }
345  return true;
346 }
347 
348 std::pair<MachineInstr::mmo_iterator, unsigned>
350 
351  // If either of the incoming memrefs are empty, we must be conservative and
352  // treat this as if we've exhausted our space for memrefs and dropped them.
353  if (memoperands_empty() || Other.memoperands_empty())
354  return std::make_pair(nullptr, 0);
355 
356  // If both instructions have identical memrefs, we don't need to merge them.
357  // Since many instructions have a single memref, and we tend to merge things
358  // like pairs of loads from the same location, this catches a large number of
359  // cases in practice.
360  if (hasIdenticalMMOs(*this, Other))
361  return std::make_pair(MemRefs, NumMemRefs);
362 
363  // TODO: consider uniquing elements within the operand lists to reduce
364  // space usage and fall back to conservative information less often.
365  size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
366 
367  // If we don't have enough room to store this many memrefs, be conservative
368  // and drop them. Otherwise, we'd fail asserts when trying to add them to
369  // the new instruction.
370  if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
371  return std::make_pair(nullptr, 0);
372 
373  MachineFunction *MF = getMF();
374  mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
376  MemBegin);
377  MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
378  MemEnd);
379  assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
380  "missing memrefs");
381 
382  return std::make_pair(MemBegin, CombinedNumMemRefs);
383 }
384 
385 uint8_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
386  // For now, the just return the union of the flags. If the flags get more
387  // complicated over time, we might need more logic here.
388  return getFlags() | Other.getFlags();
389 }
390 
391 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
392  assert(!isBundledWithPred() && "Must be called on bundle header");
394  if (MII->getDesc().getFlags() & Mask) {
395  if (Type == AnyInBundle)
396  return true;
397  } else {
398  if (Type == AllInBundle && !MII->isBundle())
399  return false;
400  }
401  // This was the last instruction in the bundle.
402  if (!MII->isBundledWithSucc())
403  return Type == AllInBundle;
404  }
405 }
406 
408  MICheckType Check) const {
409  // If opcodes or number of operands are not the same then the two
410  // instructions are obviously not identical.
411  if (Other.getOpcode() != getOpcode() ||
412  Other.getNumOperands() != getNumOperands())
413  return false;
414 
415  if (isBundle()) {
416  // We have passed the test above that both instructions have the same
417  // opcode, so we know that both instructions are bundles here. Let's compare
418  // MIs inside the bundle.
419  assert(Other.isBundle() && "Expected that both instructions are bundles.");
422  // Loop until we analysed the last intruction inside at least one of the
423  // bundles.
424  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
425  ++I1;
426  ++I2;
427  if (!I1->isIdenticalTo(*I2, Check))
428  return false;
429  }
430  // If we've reached the end of just one of the two bundles, but not both,
431  // the instructions are not identical.
432  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
433  return false;
434  }
435 
436  // Check operands to make sure they match.
437  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
438  const MachineOperand &MO = getOperand(i);
439  const MachineOperand &OMO = Other.getOperand(i);
440  if (!MO.isReg()) {
441  if (!MO.isIdenticalTo(OMO))
442  return false;
443  continue;
444  }
445 
446  // Clients may or may not want to ignore defs when testing for equality.
447  // For example, machine CSE pass only cares about finding common
448  // subexpressions, so it's safe to ignore virtual register defs.
449  if (MO.isDef()) {
450  if (Check == IgnoreDefs)
451  continue;
452  else if (Check == IgnoreVRegDefs) {
455  if (!MO.isIdenticalTo(OMO))
456  return false;
457  } else {
458  if (!MO.isIdenticalTo(OMO))
459  return false;
460  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
461  return false;
462  }
463  } else {
464  if (!MO.isIdenticalTo(OMO))
465  return false;
466  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
467  return false;
468  }
469  }
470  // If DebugLoc does not match then two debug instructions are not identical.
471  if (isDebugInstr())
472  if (getDebugLoc() && Other.getDebugLoc() &&
473  getDebugLoc() != Other.getDebugLoc())
474  return false;
475  return true;
476 }
477 
479  return getParent()->getParent();
480 }
481 
483  assert(getParent() && "Not embedded in a basic block!");
484  return getParent()->remove(this);
485 }
486 
488  assert(getParent() && "Not embedded in a basic block!");
489  return getParent()->remove_instr(this);
490 }
491 
493  assert(getParent() && "Not embedded in a basic block!");
494  getParent()->erase(this);
495 }
496 
498  assert(getParent() && "Not embedded in a basic block!");
499  MachineBasicBlock *MBB = getParent();
500  MachineFunction *MF = MBB->getParent();
501  assert(MF && "Not embedded in a function!");
502 
503  MachineInstr *MI = (MachineInstr *)this;
504  MachineRegisterInfo &MRI = MF->getRegInfo();
505 
506  for (const MachineOperand &MO : MI->operands()) {
507  if (!MO.isReg() || !MO.isDef())
508  continue;
509  unsigned Reg = MO.getReg();
511  continue;
513  }
514  MI->eraseFromParent();
515 }
516 
518  assert(getParent() && "Not embedded in a basic block!");
519  getParent()->erase_instr(this);
520 }
521 
522 /// getNumExplicitOperands - Returns the number of non-implicit operands.
523 ///
525  unsigned NumOperands = MCID->getNumOperands();
526  if (!MCID->isVariadic())
527  return NumOperands;
528 
529  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
530  const MachineOperand &MO = getOperand(i);
531  if (!MO.isReg() || !MO.isImplicit())
532  NumOperands++;
533  }
534  return NumOperands;
535 }
536 
538  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
541  --Pred;
542  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
543  Pred->setFlag(BundledSucc);
544 }
545 
547  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
550  ++Succ;
551  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
552  Succ->setFlag(BundledPred);
553 }
554 
556  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
559  --Pred;
560  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
561  Pred->clearFlag(BundledSucc);
562 }
563 
565  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
568  ++Succ;
569  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
570  Succ->clearFlag(BundledPred);
571 }
572 
574  if (isInlineAsm()) {
575  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
576  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
577  return true;
578  }
579  return false;
580 }
581 
583  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
584  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
585  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
586 }
587 
589  unsigned *GroupNo) const {
590  assert(isInlineAsm() && "Expected an inline asm instruction");
591  assert(OpIdx < getNumOperands() && "OpIdx out of range");
592 
593  // Ignore queries about the initial operands.
594  if (OpIdx < InlineAsm::MIOp_FirstOperand)
595  return -1;
596 
597  unsigned Group = 0;
598  unsigned NumOps;
599  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
600  i += NumOps) {
601  const MachineOperand &FlagMO = getOperand(i);
602  // If we reach the implicit register operands, stop looking.
603  if (!FlagMO.isImm())
604  return -1;
605  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
606  if (i + NumOps > OpIdx) {
607  if (GroupNo)
608  *GroupNo = Group;
609  return i;
610  }
611  ++Group;
612  }
613  return -1;
614 }
615 
617  assert(isDebugLabel() && "not a DBG_LABEL");
618  return cast<DILabel>(getOperand(0).getMetadata());
619 }
620 
622  assert(isDebugValue() && "not a DBG_VALUE");
623  return cast<DILocalVariable>(getOperand(2).getMetadata());
624 }
625 
627  assert(isDebugValue() && "not a DBG_VALUE");
628  return cast<DIExpression>(getOperand(3).getMetadata());
629 }
630 
631 const TargetRegisterClass*
633  const TargetInstrInfo *TII,
634  const TargetRegisterInfo *TRI) const {
635  assert(getParent() && "Can't have an MBB reference here!");
636  assert(getMF() && "Can't have an MF reference here!");
637  const MachineFunction &MF = *getMF();
638 
639  // Most opcodes have fixed constraints in their MCInstrDesc.
640  if (!isInlineAsm())
641  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
642 
643  if (!getOperand(OpIdx).isReg())
644  return nullptr;
645 
646  // For tied uses on inline asm, get the constraint from the def.
647  unsigned DefIdx;
648  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
649  OpIdx = DefIdx;
650 
651  // Inline asm stores register class constraints in the flag word.
652  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
653  if (FlagIdx < 0)
654  return nullptr;
655 
656  unsigned Flag = getOperand(FlagIdx).getImm();
657  unsigned RCID;
662  return TRI->getRegClass(RCID);
663 
664  // Assume that all registers in a memory operand are pointers.
666  return TRI->getPointerRegClass(MF);
667 
668  return nullptr;
669 }
670 
672  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
673  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
674  // Check every operands inside the bundle if we have
675  // been asked to.
676  if (ExploreBundle)
677  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
678  ++OpndIt)
679  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
680  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
681  else
682  // Otherwise, just check the current operands.
683  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
684  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
685  return CurRC;
686 }
687 
688 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
689  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
690  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
691  assert(CurRC && "Invalid initial register class");
692  // Check if Reg is constrained by some of its use/def from MI.
693  const MachineOperand &MO = getOperand(OpIdx);
694  if (!MO.isReg() || MO.getReg() != Reg)
695  return CurRC;
696  // If yes, accumulate the constraints through the operand.
697  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
698 }
699 
701  unsigned OpIdx, const TargetRegisterClass *CurRC,
702  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
703  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
704  const MachineOperand &MO = getOperand(OpIdx);
705  assert(MO.isReg() &&
706  "Cannot get register constraints for non-register operand");
707  assert(CurRC && "Invalid initial register class");
708  if (unsigned SubIdx = MO.getSubReg()) {
709  if (OpRC)
710  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
711  else
712  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
713  } else if (OpRC)
714  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
715  return CurRC;
716 }
717 
718 /// Return the number of instructions inside the MI bundle, not counting the
719 /// header instruction.
720 unsigned MachineInstr::getBundleSize() const {
722  unsigned Size = 0;
723  while (I->isBundledWithSucc()) {
724  ++Size;
725  ++I;
726  }
727  return Size;
728 }
729 
730 /// Returns true if the MachineInstr has an implicit-use operand of exactly
731 /// the given register (not considering sub/super-registers).
733  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
734  const MachineOperand &MO = getOperand(i);
735  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
736  return true;
737  }
738  return false;
739 }
740 
741 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
742 /// the specific register or -1 if it is not found. It further tightens
743 /// the search criteria to a use that kills the register if isKill is true.
745  unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
746  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
747  const MachineOperand &MO = getOperand(i);
748  if (!MO.isReg() || !MO.isUse())
749  continue;
750  unsigned MOReg = MO.getReg();
751  if (!MOReg)
752  continue;
753  if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
755  TRI->isSubRegister(MOReg, Reg)))
756  if (!isKill || MO.isKill())
757  return i;
758  }
759  return -1;
760 }
761 
762 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
763 /// indicating if this instruction reads or writes Reg. This also considers
764 /// partial defines.
765 std::pair<bool,bool>
767  SmallVectorImpl<unsigned> *Ops) const {
768  bool PartDef = false; // Partial redefine.
769  bool FullDef = false; // Full define.
770  bool Use = false;
771 
772  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
773  const MachineOperand &MO = getOperand(i);
774  if (!MO.isReg() || MO.getReg() != Reg)
775  continue;
776  if (Ops)
777  Ops->push_back(i);
778  if (MO.isUse())
779  Use |= !MO.isUndef();
780  else if (MO.getSubReg() && !MO.isUndef())
781  // A partial def undef doesn't count as reading the register.
782  PartDef = true;
783  else
784  FullDef = true;
785  }
786  // A partial redefine uses Reg unless there is also a full define.
787  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
788 }
789 
790 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
791 /// the specified register or -1 if it is not found. If isDead is true, defs
792 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
793 /// also checks if there is a def of a super-register.
794 int
795 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
796  const TargetRegisterInfo *TRI) const {
797  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
798  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
799  const MachineOperand &MO = getOperand(i);
800  // Accept regmask operands when Overlap is set.
801  // Ignore them when looking for a specific def operand (Overlap == false).
802  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
803  return i;
804  if (!MO.isReg() || !MO.isDef())
805  continue;
806  unsigned MOReg = MO.getReg();
807  bool Found = (MOReg == Reg);
808  if (!Found && TRI && isPhys &&
810  if (Overlap)
811  Found = TRI->regsOverlap(MOReg, Reg);
812  else
813  Found = TRI->isSubRegister(MOReg, Reg);
814  }
815  if (Found && (!isDead || MO.isDead()))
816  return i;
817  }
818  return -1;
819 }
820 
821 /// findFirstPredOperandIdx() - Find the index of the first operand in the
822 /// operand list that is used to represent the predicate. It returns -1 if
823 /// none is found.
825  // Don't call MCID.findFirstPredOperandIdx() because this variant
826  // is sometimes called on an instruction that's not yet complete, and
827  // so the number of operands is less than the MCID indicates. In
828  // particular, the PTX target does this.
829  const MCInstrDesc &MCID = getDesc();
830  if (MCID.isPredicable()) {
831  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
832  if (MCID.OpInfo[i].isPredicate())
833  return i;
834  }
835 
836  return -1;
837 }
838 
839 // MachineOperand::TiedTo is 4 bits wide.
840 const unsigned TiedMax = 15;
841 
842 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
843 ///
844 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
845 /// field. TiedTo can have these values:
846 ///
847 /// 0: Operand is not tied to anything.
848 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
849 /// TiedMax: Tied to an operand >= TiedMax-1.
850 ///
851 /// The tied def must be one of the first TiedMax operands on a normal
852 /// instruction. INLINEASM instructions allow more tied defs.
853 ///
854 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
855  MachineOperand &DefMO = getOperand(DefIdx);
856  MachineOperand &UseMO = getOperand(UseIdx);
857  assert(DefMO.isDef() && "DefIdx must be a def operand");
858  assert(UseMO.isUse() && "UseIdx must be a use operand");
859  assert(!DefMO.isTied() && "Def is already tied to another use");
860  assert(!UseMO.isTied() && "Use is already tied to another def");
861 
862  if (DefIdx < TiedMax)
863  UseMO.TiedTo = DefIdx + 1;
864  else {
865  // Inline asm can use the group descriptors to find tied operands, but on
866  // normal instruction, the tied def must be within the first TiedMax
867  // operands.
868  assert(isInlineAsm() && "DefIdx out of range");
869  UseMO.TiedTo = TiedMax;
870  }
871 
872  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
873  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
874 }
875 
876 /// Given the index of a tied register operand, find the operand it is tied to.
877 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
878 /// which must exist.
879 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
880  const MachineOperand &MO = getOperand(OpIdx);
881  assert(MO.isTied() && "Operand isn't tied");
882 
883  // Normally TiedTo is in range.
884  if (MO.TiedTo < TiedMax)
885  return MO.TiedTo - 1;
886 
887  // Uses on normal instructions can be out of range.
888  if (!isInlineAsm()) {
889  // Normal tied defs must be in the 0..TiedMax-1 range.
890  if (MO.isUse())
891  return TiedMax - 1;
892  // MO is a def. Search for the tied use.
893  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
894  const MachineOperand &UseMO = getOperand(i);
895  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
896  return i;
897  }
898  llvm_unreachable("Can't find tied use");
899  }
900 
901  // Now deal with inline asm by parsing the operand group descriptor flags.
902  // Find the beginning of each operand group.
903  SmallVector<unsigned, 8> GroupIdx;
904  unsigned OpIdxGroup = ~0u;
905  unsigned NumOps;
906  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
907  i += NumOps) {
908  const MachineOperand &FlagMO = getOperand(i);
909  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
910  unsigned CurGroup = GroupIdx.size();
911  GroupIdx.push_back(i);
912  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
913  // OpIdx belongs to this operand group.
914  if (OpIdx > i && OpIdx < i + NumOps)
915  OpIdxGroup = CurGroup;
916  unsigned TiedGroup;
917  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
918  continue;
919  // Operands in this group are tied to operands in TiedGroup which must be
920  // earlier. Find the number of operands between the two groups.
921  unsigned Delta = i - GroupIdx[TiedGroup];
922 
923  // OpIdx is a use tied to TiedGroup.
924  if (OpIdxGroup == CurGroup)
925  return OpIdx - Delta;
926 
927  // OpIdx is a def tied to this use group.
928  if (OpIdxGroup == TiedGroup)
929  return OpIdx + Delta;
930  }
931  llvm_unreachable("Invalid tied operand on inline asm");
932 }
933 
934 /// clearKillInfo - Clears kill flags on all operands.
935 ///
937  for (MachineOperand &MO : operands()) {
938  if (MO.isReg() && MO.isUse())
939  MO.setIsKill(false);
940  }
941 }
942 
943 void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
944  unsigned SubIdx,
945  const TargetRegisterInfo &RegInfo) {
947  if (SubIdx)
948  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
949  for (MachineOperand &MO : operands()) {
950  if (!MO.isReg() || MO.getReg() != FromReg)
951  continue;
952  MO.substPhysReg(ToReg, RegInfo);
953  }
954  } else {
955  for (MachineOperand &MO : operands()) {
956  if (!MO.isReg() || MO.getReg() != FromReg)
957  continue;
958  MO.substVirtReg(ToReg, SubIdx, RegInfo);
959  }
960  }
961 }
962 
963 /// isSafeToMove - Return true if it is safe to move this instruction. If
964 /// SawStore is set to true, it means that there is a store (or call) between
965 /// the instruction's location and its intended destination.
966 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
967  // Ignore stuff that we obviously can't move.
968  //
969  // Treat volatile loads as stores. This is not strictly necessary for
970  // volatiles, but it is required for atomic loads. It is not allowed to move
971  // a load across an atomic load with Ordering > Monotonic.
972  if (mayStore() || isCall() || isPHI() ||
973  (mayLoad() && hasOrderedMemoryRef())) {
974  SawStore = true;
975  return false;
976  }
977 
978  if (isPosition() || isDebugInstr() || isTerminator() ||
980  return false;
981 
982  // See if this instruction does a load. If so, we have to guarantee that the
983  // loaded value doesn't change between the load and the its intended
984  // destination. The check for isInvariantLoad gives the targe the chance to
985  // classify the load as always returning a constant, e.g. a constant pool
986  // load.
988  // Otherwise, this is a real load. If there is a store between the load and
989  // end of block, we can't move it.
990  return !SawStore;
991 
992  return true;
993 }
994 
996  bool UseTBAA) {
997  const MachineFunction *MF = getMF();
998  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
999  const MachineFrameInfo &MFI = MF->getFrameInfo();
1000 
1001  // If neither instruction stores to memory, they can't alias in any
1002  // meaningful way, even if they read from the same address.
1003  if (!mayStore() && !Other.mayStore())
1004  return false;
1005 
1006  // Let the target decide if memory accesses cannot possibly overlap.
1007  if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1008  return false;
1009 
1010  // FIXME: Need to handle multiple memory operands to support all targets.
1011  if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1012  return true;
1013 
1015  MachineMemOperand *MMOb = *Other.memoperands_begin();
1016 
1017  // The following interface to AA is fashioned after DAGCombiner::isAlias
1018  // and operates with MachineMemOperand offset with some important
1019  // assumptions:
1020  // - LLVM fundamentally assumes flat address spaces.
1021  // - MachineOperand offset can *only* result from legalization and
1022  // cannot affect queries other than the trivial case of overlap
1023  // checking.
1024  // - These offsets never wrap and never step outside
1025  // of allocated objects.
1026  // - There should never be any negative offsets here.
1027  //
1028  // FIXME: Modify API to hide this math from "user"
1029  // Even before we go to AA we can reason locally about some
1030  // memory objects. It can save compile time, and possibly catch some
1031  // corner cases not currently covered.
1032 
1033  int64_t OffsetA = MMOa->getOffset();
1034  int64_t OffsetB = MMOb->getOffset();
1035 
1036  int64_t MinOffset = std::min(OffsetA, OffsetB);
1037  int64_t WidthA = MMOa->getSize();
1038  int64_t WidthB = MMOb->getSize();
1039  const Value *ValA = MMOa->getValue();
1040  const Value *ValB = MMOb->getValue();
1041  bool SameVal = (ValA && ValB && (ValA == ValB));
1042  if (!SameVal) {
1043  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1044  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1045  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1046  return false;
1047  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1048  return false;
1049  if (PSVa && PSVb && (PSVa == PSVb))
1050  SameVal = true;
1051  }
1052 
1053  if (SameVal) {
1054  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1055  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1056  return (MinOffset + LowWidth > MaxOffset);
1057  }
1058 
1059  if (!AA)
1060  return true;
1061 
1062  if (!ValA || !ValB)
1063  return true;
1064 
1065  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1066  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1067 
1068  int64_t Overlapa = WidthA + OffsetA - MinOffset;
1069  int64_t Overlapb = WidthB + OffsetB - MinOffset;
1070 
1071  AliasResult AAResult = AA->alias(
1072  MemoryLocation(ValA, Overlapa,
1073  UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1074  MemoryLocation(ValB, Overlapb,
1075  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1076 
1077  return (AAResult != NoAlias);
1078 }
1079 
1080 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1081 /// or volatile memory reference, or if the information describing the memory
1082 /// reference is not available. Return false if it is known to have no ordered
1083 /// memory references.
1085  // An instruction known never to access memory won't have a volatile access.
1086  if (!mayStore() &&
1087  !mayLoad() &&
1088  !isCall() &&
1090  return false;
1091 
1092  // Otherwise, if the instruction has no memory reference information,
1093  // conservatively assume it wasn't preserved.
1094  if (memoperands_empty())
1095  return true;
1096 
1097  // Check if any of our memory operands are ordered.
1098  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1099  return !MMO->isUnordered();
1100  });
1101 }
1102 
1103 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1104 /// trap and is loading from a location whose value is invariant across a run of
1105 /// this function.
1107  // If the instruction doesn't load at all, it isn't an invariant load.
1108  if (!mayLoad())
1109  return false;
1110 
1111  // If the instruction has lost its memoperands, conservatively assume that
1112  // it may not be an invariant load.
1113  if (memoperands_empty())
1114  return false;
1115 
1116  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1117 
1118  for (MachineMemOperand *MMO : memoperands()) {
1119  if (MMO->isVolatile()) return false;
1120  if (MMO->isStore()) return false;
1121  if (MMO->isInvariant() && MMO->isDereferenceable())
1122  continue;
1123 
1124  // A load from a constant PseudoSourceValue is invariant.
1125  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1126  if (PSV->isConstant(&MFI))
1127  continue;
1128 
1129  if (const Value *V = MMO->getValue()) {
1130  // If we have an AliasAnalysis, ask it whether the memory is constant.
1131  if (AA &&
1133  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1134  continue;
1135  }
1136 
1137  // Otherwise assume conservatively.
1138  return false;
1139  }
1140 
1141  // Everything checks out.
1142  return true;
1143 }
1144 
1145 /// isConstantValuePHI - If the specified instruction is a PHI that always
1146 /// merges together the same virtual register, return the register, otherwise
1147 /// return 0.
1149  if (!isPHI())
1150  return 0;
1151  assert(getNumOperands() >= 3 &&
1152  "It's illegal to have a PHI without source operands");
1153 
1154  unsigned Reg = getOperand(1).getReg();
1155  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1156  if (getOperand(i).getReg() != Reg)
1157  return 0;
1158  return Reg;
1159 }
1160 
1163  return true;
1164  if (isInlineAsm()) {
1165  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1166  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1167  return true;
1168  }
1169 
1170  return false;
1171 }
1172 
1174  return mayStore() || isCall() || hasUnmodeledSideEffects();
1175 }
1176 
1177 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1178 ///
1180  for (const MachineOperand &MO : operands()) {
1181  if (!MO.isReg() || MO.isUse())
1182  continue;
1183  if (!MO.isDead())
1184  return false;
1185  }
1186  return true;
1187 }
1188 
1189 /// copyImplicitOps - Copy implicit register operands from specified
1190 /// instruction to this instruction.
1192  const MachineInstr &MI) {
1193  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1194  i != e; ++i) {
1195  const MachineOperand &MO = MI.getOperand(i);
1196  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1197  addOperand(MF, MO);
1198  }
1199 }
1200 
1202  const MCInstrDesc &MCID = getDesc();
1203  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1204  const auto &Operand = getOperand(I);
1205  if (!Operand.isReg() || Operand.isDef())
1206  // Ignore the defined registers as MCID marks only the uses as tied.
1207  continue;
1208  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1209  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1210  if (ExpectedTiedIdx != TiedIdx)
1211  return true;
1212  }
1213  return false;
1214 }
1215 
1216 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1217  const MachineRegisterInfo &MRI) const {
1218  const MachineOperand &Op = getOperand(OpIdx);
1219  if (!Op.isReg())
1220  return LLT{};
1221 
1222  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1223  return MRI.getType(Op.getReg());
1224 
1225  auto &OpInfo = getDesc().OpInfo[OpIdx];
1226  if (!OpInfo.isGenericType())
1227  return MRI.getType(Op.getReg());
1228 
1229  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1230  return LLT{};
1231 
1232  LLT TypeToPrint = MRI.getType(Op.getReg());
1233  // Don't mark the type index printed if it wasn't actually printed: maybe
1234  // another operand with the same type index has an actual type attached:
1235  if (TypeToPrint.isValid())
1236  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1237  return TypeToPrint;
1238 }
1239 
1240 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1242  dbgs() << " ";
1243  print(dbgs());
1244 }
1245 #endif
1246 
1247 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1248  bool SkipDebugLoc, bool AddNewLine,
1249  const TargetInstrInfo *TII) const {
1250  const Module *M = nullptr;
1251  const Function *F = nullptr;
1252  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1253  F = &MF->getFunction();
1254  M = F->getParent();
1255  if (!TII)
1256  TII = MF->getSubtarget().getInstrInfo();
1257  }
1258 
1259  ModuleSlotTracker MST(M);
1260  if (F)
1261  MST.incorporateFunction(*F);
1262  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1263 }
1264 
1266  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1267  bool AddNewLine, const TargetInstrInfo *TII) const {
1268  // We can be a bit tidier if we know the MachineFunction.
1269  const MachineFunction *MF = nullptr;
1270  const TargetRegisterInfo *TRI = nullptr;
1271  const MachineRegisterInfo *MRI = nullptr;
1272  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1273  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1274 
1275  if (isCFIInstruction())
1276  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1277 
1278  SmallBitVector PrintedTypes(8);
1279  bool ShouldPrintRegisterTies = hasComplexRegisterTies();
1280  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1281  if (!ShouldPrintRegisterTies)
1282  return 0U;
1283  const MachineOperand &MO = getOperand(OpIdx);
1284  if (MO.isReg() && MO.isTied() && !MO.isDef())
1285  return findTiedOperandIdx(OpIdx);
1286  return 0U;
1287  };
1288  unsigned StartOp = 0;
1289  unsigned e = getNumOperands();
1290 
1291  // Print explicitly defined operands on the left of an assignment syntax.
1292  while (StartOp < e) {
1293  const MachineOperand &MO = getOperand(StartOp);
1294  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1295  break;
1296 
1297  if (StartOp != 0)
1298  OS << ", ";
1299 
1300  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1301  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1302  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1303  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1304  ++StartOp;
1305  }
1306 
1307  if (StartOp != 0)
1308  OS << " = ";
1309 
1311  OS << "frame-setup ";
1313  OS << "frame-destroy ";
1315  OS << "nnan ";
1317  OS << "ninf ";
1319  OS << "nsz ";
1321  OS << "arcp ";
1323  OS << "contract ";
1325  OS << "afn ";
1327  OS << "reassoc ";
1328 
1329  // Print the opcode name.
1330  if (TII)
1331  OS << TII->getName(getOpcode());
1332  else
1333  OS << "UNKNOWN";
1334 
1335  if (SkipOpers)
1336  return;
1337 
1338  // Print the rest of the operands.
1339  bool FirstOp = true;
1340  unsigned AsmDescOp = ~0u;
1341  unsigned AsmOpCount = 0;
1342 
1343  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1344  // Print asm string.
1345  OS << " ";
1346  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1347  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1348  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1349  getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1350  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1351  IntrinsicInfo);
1352 
1353  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1354  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1355  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1356  OS << " [sideeffect]";
1357  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1358  OS << " [mayload]";
1359  if (ExtraInfo & InlineAsm::Extra_MayStore)
1360  OS << " [maystore]";
1361  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1362  OS << " [isconvergent]";
1363  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1364  OS << " [alignstack]";
1366  OS << " [attdialect]";
1368  OS << " [inteldialect]";
1369 
1370  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1371  FirstOp = false;
1372  }
1373 
1374  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1375  const MachineOperand &MO = getOperand(i);
1376 
1377  if (FirstOp) FirstOp = false; else OS << ",";
1378  OS << " ";
1379 
1380  if (isDebugValue() && MO.isMetadata()) {
1381  // Pretty print DBG_VALUE instructions.
1382  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1383  if (DIV && !DIV->getName().empty())
1384  OS << "!\"" << DIV->getName() << '\"';
1385  else {
1386  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1387  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1388  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1389  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1390  }
1391  } else if (isDebugLabel() && MO.isMetadata()) {
1392  // Pretty print DBG_LABEL instructions.
1393  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1394  if (DIL && !DIL->getName().empty())
1395  OS << "\"" << DIL->getName() << '\"';
1396  else {
1397  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1398  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1399  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1400  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1401  }
1402  } else if (i == AsmDescOp && MO.isImm()) {
1403  // Pretty print the inline asm operand descriptor.
1404  OS << '$' << AsmOpCount++;
1405  unsigned Flag = MO.getImm();
1406  switch (InlineAsm::getKind(Flag)) {
1407  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1408  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1409  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1410  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1411  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1412  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1413  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1414  }
1415 
1416  unsigned RCID = 0;
1417  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1418  InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1419  if (TRI) {
1420  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1421  } else
1422  OS << ":RC" << RCID;
1423  }
1424 
1425  if (InlineAsm::isMemKind(Flag)) {
1426  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1427  switch (MCID) {
1428  case InlineAsm::Constraint_es: OS << ":es"; break;
1429  case InlineAsm::Constraint_i: OS << ":i"; break;
1430  case InlineAsm::Constraint_m: OS << ":m"; break;
1431  case InlineAsm::Constraint_o: OS << ":o"; break;
1432  case InlineAsm::Constraint_v: OS << ":v"; break;
1433  case InlineAsm::Constraint_Q: OS << ":Q"; break;
1434  case InlineAsm::Constraint_R: OS << ":R"; break;
1435  case InlineAsm::Constraint_S: OS << ":S"; break;
1436  case InlineAsm::Constraint_T: OS << ":T"; break;
1437  case InlineAsm::Constraint_Um: OS << ":Um"; break;
1438  case InlineAsm::Constraint_Un: OS << ":Un"; break;
1439  case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1440  case InlineAsm::Constraint_Us: OS << ":Us"; break;
1441  case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1442  case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1443  case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1444  case InlineAsm::Constraint_X: OS << ":X"; break;
1445  case InlineAsm::Constraint_Z: OS << ":Z"; break;
1446  case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1447  case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1448  default: OS << ":?"; break;
1449  }
1450  }
1451 
1452  unsigned TiedTo = 0;
1453  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1454  OS << " tiedto:$" << TiedTo;
1455 
1456  OS << ']';
1457 
1458  // Compute the index of the next operand descriptor.
1459  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1460  } else {
1461  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1462  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1463  if (MO.isImm() && isOperandSubregIdx(i))
1465  else
1466  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1467  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1468  }
1469  }
1470 
1471  if (!SkipDebugLoc) {
1472  if (const DebugLoc &DL = getDebugLoc()) {
1473  if (!FirstOp)
1474  OS << ',';
1475  OS << " debug-location ";
1476  DL->printAsOperand(OS, MST);
1477  }
1478  }
1479 
1480  if (!memoperands_empty()) {
1482  const LLVMContext *Context = nullptr;
1483  std::unique_ptr<LLVMContext> CtxPtr;
1484  const MachineFrameInfo *MFI = nullptr;
1485  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1486  MFI = &MF->getFrameInfo();
1487  Context = &MF->getFunction().getContext();
1488  } else {
1489  CtxPtr = llvm::make_unique<LLVMContext>();
1490  Context = CtxPtr.get();
1491  }
1492 
1493  OS << " :: ";
1494  bool NeedComma = false;
1495  for (const MachineMemOperand *Op : memoperands()) {
1496  if (NeedComma)
1497  OS << ", ";
1498  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1499  NeedComma = true;
1500  }
1501  }
1502 
1503  if (SkipDebugLoc)
1504  return;
1505 
1506  bool HaveSemi = false;
1507 
1508  // Print debug location information.
1509  if (const DebugLoc &DL = getDebugLoc()) {
1510  if (!HaveSemi) {
1511  OS << ';';
1512  HaveSemi = true;
1513  }
1514  OS << ' ';
1515  DL.print(OS);
1516  }
1517 
1518  // Print extra comments for DEBUG_VALUE.
1519  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1520  if (!HaveSemi) {
1521  OS << ";";
1522  HaveSemi = true;
1523  }
1524  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1525  OS << " line no:" << DV->getLine();
1526  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1527  DebugLoc InlinedAtDL(InlinedAt);
1528  if (InlinedAtDL && MF) {
1529  OS << " inlined @[ ";
1530  InlinedAtDL.print(OS);
1531  OS << " ]";
1532  }
1533  }
1534  if (isIndirectDebugValue())
1535  OS << " indirect";
1536  }
1537  // TODO: DBG_LABEL
1538 
1539  if (AddNewLine)
1540  OS << '\n';
1541 }
1542 
1543 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1544  const TargetRegisterInfo *RegInfo,
1545  bool AddIfNotFound) {
1546  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1547  bool hasAliases = isPhysReg &&
1548  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1549  bool Found = false;
1550  SmallVector<unsigned,4> DeadOps;
1551  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1552  MachineOperand &MO = getOperand(i);
1553  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1554  continue;
1555 
1556  // DEBUG_VALUE nodes do not contribute to code generation and should
1557  // always be ignored. Failure to do so may result in trying to modify
1558  // KILL flags on DEBUG_VALUE nodes.
1559  if (MO.isDebug())
1560  continue;
1561 
1562  unsigned Reg = MO.getReg();
1563  if (!Reg)
1564  continue;
1565 
1566  if (Reg == IncomingReg) {
1567  if (!Found) {
1568  if (MO.isKill())
1569  // The register is already marked kill.
1570  return true;
1571  if (isPhysReg && isRegTiedToDefOperand(i))
1572  // Two-address uses of physregs must not be marked kill.
1573  return true;
1574  MO.setIsKill();
1575  Found = true;
1576  }
1577  } else if (hasAliases && MO.isKill() &&
1579  // A super-register kill already exists.
1580  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1581  return true;
1582  if (RegInfo->isSubRegister(IncomingReg, Reg))
1583  DeadOps.push_back(i);
1584  }
1585  }
1586 
1587  // Trim unneeded kill operands.
1588  while (!DeadOps.empty()) {
1589  unsigned OpIdx = DeadOps.back();
1590  if (getOperand(OpIdx).isImplicit())
1591  RemoveOperand(OpIdx);
1592  else
1593  getOperand(OpIdx).setIsKill(false);
1594  DeadOps.pop_back();
1595  }
1596 
1597  // If not found, this means an alias of one of the operands is killed. Add a
1598  // new implicit operand if required.
1599  if (!Found && AddIfNotFound) {
1601  false /*IsDef*/,
1602  true /*IsImp*/,
1603  true /*IsKill*/));
1604  return true;
1605  }
1606  return Found;
1607 }
1608 
1610  const TargetRegisterInfo *RegInfo) {
1612  RegInfo = nullptr;
1613  for (MachineOperand &MO : operands()) {
1614  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1615  continue;
1616  unsigned OpReg = MO.getReg();
1617  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1618  MO.setIsKill(false);
1619  }
1620 }
1621 
1623  const TargetRegisterInfo *RegInfo,
1624  bool AddIfNotFound) {
1625  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1626  bool hasAliases = isPhysReg &&
1627  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1628  bool Found = false;
1629  SmallVector<unsigned,4> DeadOps;
1630  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1631  MachineOperand &MO = getOperand(i);
1632  if (!MO.isReg() || !MO.isDef())
1633  continue;
1634  unsigned MOReg = MO.getReg();
1635  if (!MOReg)
1636  continue;
1637 
1638  if (MOReg == Reg) {
1639  MO.setIsDead();
1640  Found = true;
1641  } else if (hasAliases && MO.isDead() &&
1643  // There exists a super-register that's marked dead.
1644  if (RegInfo->isSuperRegister(Reg, MOReg))
1645  return true;
1646  if (RegInfo->isSubRegister(Reg, MOReg))
1647  DeadOps.push_back(i);
1648  }
1649  }
1650 
1651  // Trim unneeded dead operands.
1652  while (!DeadOps.empty()) {
1653  unsigned OpIdx = DeadOps.back();
1654  if (getOperand(OpIdx).isImplicit())
1655  RemoveOperand(OpIdx);
1656  else
1657  getOperand(OpIdx).setIsDead(false);
1658  DeadOps.pop_back();
1659  }
1660 
1661  // If not found, this means an alias of one of the operands is dead. Add a
1662  // new implicit operand if required.
1663  if (Found || !AddIfNotFound)
1664  return Found;
1665 
1667  true /*IsDef*/,
1668  true /*IsImp*/,
1669  false /*IsKill*/,
1670  true /*IsDead*/));
1671  return true;
1672 }
1673 
1675  for (MachineOperand &MO : operands()) {
1676  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1677  continue;
1678  MO.setIsDead(false);
1679  }
1680 }
1681 
1682 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1683  for (MachineOperand &MO : operands()) {
1684  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1685  continue;
1686  MO.setIsUndef(IsUndef);
1687  }
1688 }
1689 
1691  const TargetRegisterInfo *RegInfo) {
1693  MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1694  if (MO)
1695  return;
1696  } else {
1697  for (const MachineOperand &MO : operands()) {
1698  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1699  MO.getSubReg() == 0)
1700  return;
1701  }
1702  }
1704  true /*IsDef*/,
1705  true /*IsImp*/));
1706 }
1707 
1709  const TargetRegisterInfo &TRI) {
1710  bool HasRegMask = false;
1711  for (MachineOperand &MO : operands()) {
1712  if (MO.isRegMask()) {
1713  HasRegMask = true;
1714  continue;
1715  }
1716  if (!MO.isReg() || !MO.isDef()) continue;
1717  unsigned Reg = MO.getReg();
1718  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1719  // If there are no uses, including partial uses, the def is dead.
1720  if (llvm::none_of(UsedRegs,
1721  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1722  MO.setIsDead();
1723  }
1724 
1725  // This is a call with a register mask operand.
1726  // Mask clobbers are always dead, so add defs for the non-dead defines.
1727  if (HasRegMask)
1728  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1729  I != E; ++I)
1730  addRegisterDefined(*I, &TRI);
1731 }
1732 
1733 unsigned
1735  // Build up a buffer of hash code components.
1736  SmallVector<size_t, 8> HashComponents;
1737  HashComponents.reserve(MI->getNumOperands() + 1);
1738  HashComponents.push_back(MI->getOpcode());
1739  for (const MachineOperand &MO : MI->operands()) {
1740  if (MO.isReg() && MO.isDef() &&
1742  continue; // Skip virtual register defs.
1743 
1744  HashComponents.push_back(hash_value(MO));
1745  }
1746  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1747 }
1748 
1750  // Find the source location cookie.
1751  unsigned LocCookie = 0;
1752  const MDNode *LocMD = nullptr;
1753  for (unsigned i = getNumOperands(); i != 0; --i) {
1754  if (getOperand(i-1).isMetadata() &&
1755  (LocMD = getOperand(i-1).getMetadata()) &&
1756  LocMD->getNumOperands() != 0) {
1757  if (const ConstantInt *CI =
1758  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1759  LocCookie = CI->getZExtValue();
1760  break;
1761  }
1762  }
1763  }
1764 
1765  if (const MachineBasicBlock *MBB = getParent())
1766  if (const MachineFunction *MF = MBB->getParent())
1767  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1768  report_fatal_error(Msg);
1769 }
1770 
1772  const MCInstrDesc &MCID, bool IsIndirect,
1773  unsigned Reg, const MDNode *Variable,
1774  const MDNode *Expr) {
1775  assert(isa<DILocalVariable>(Variable) && "not a variable");
1776  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1777  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
1778  "Expected inlined-at fields to agree");
1779  if (IsIndirect)
1780  return BuildMI(MF, DL, MCID)
1781  .addReg(Reg, RegState::Debug)
1782  .addImm(0U)
1783  .addMetadata(Variable)
1784  .addMetadata(Expr);
1785  else
1786  return BuildMI(MF, DL, MCID)
1787  .addReg(Reg, RegState::Debug)
1788  .addReg(0U, RegState::Debug)
1789  .addMetadata(Variable)
1790  .addMetadata(Expr);
1791 }
1792 
1795  const DebugLoc &DL, const MCInstrDesc &MCID,
1796  bool IsIndirect, unsigned Reg,
1797  const MDNode *Variable, const MDNode *Expr) {
1798  assert(isa<DILocalVariable>(Variable) && "not a variable");
1799  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1800  MachineFunction &MF = *BB.getParent();
1801  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
1802  BB.insert(I, MI);
1803  return MachineInstrBuilder(MF, MI);
1804 }
1805 
1806 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
1807 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
1809  assert(MI.getOperand(0).isReg() && "can't spill non-register");
1811  "Expected inlined-at fields to agree");
1812 
1813  const DIExpression *Expr = MI.getDebugExpression();
1814  if (MI.isIndirectDebugValue()) {
1815  assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
1817  }
1818  return Expr;
1819 }
1820 
1823  const MachineInstr &Orig,
1824  int FrameIndex) {
1825  const DIExpression *Expr = computeExprForSpill(Orig);
1826  return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
1827  .addFrameIndex(FrameIndex)
1828  .addImm(0U)
1829  .addMetadata(Orig.getDebugVariable())
1830  .addMetadata(Expr);
1831 }
1832 
1834  const DIExpression *Expr = computeExprForSpill(Orig);
1835  Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
1836  Orig.getOperand(1).ChangeToImmediate(0U);
1837  Orig.getOperand(3).setMetadata(Expr);
1838 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool Check(DecodeStatus &Out, DecodeStatus In)
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:516
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
bool isUnordered() const
Returns true if this memory operation doesn&#39;t have any ordering constraints other than normal aliasin...
void push_back(const T &Elt)
Definition: SmallVector.h:212
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isDebugLabel() const
Definition: MachineInstr.h:844
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:479
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:538
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static const DIExpression * computeExprForSpill(const MachineInstr &MI)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
bool isCFIInstruction() const
Definition: MachineInstr.h:836
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:264
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:513
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:161
unsigned getReg() const
getReg - Returns the register number.
uint8_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
This file contains the declarations for metadata subclasses.
unsigned getSubReg() const
bool isInlineAsm() const
Definition: MachineInstr.h:861
The two locations do not alias at all.
Definition: AliasAnalysis.h:85
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:862
void setIsDead(bool Val=true)
F(f)
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1067
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:417
void reserve(size_type N)
Definition: SmallVector.h:378
struct llvm::MachineOperand::@147::@149 Reg
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:353
bool isPHI() const
Definition: MachineInstr.h:855
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:106
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:276
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void clearKillInfo()
Clears kill flags on all operands.
AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
The main low level interface to the alias analysis implementation.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
A description of a memory reference used in the backend.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:208
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:268
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:242
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:922
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:495
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
void bundleWithSucc()
Bundle this instruction with its successor.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isBundle() const
Definition: MachineInstr.h:882
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4431
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
virtual const TargetInstrInfo * getInstrInfo() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:93
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
AliasResult
The possible results of an alias query.
Definition: AliasAnalysis.h:79
const Value * getValue() const
Return the base address of the memory access.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:666
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:535
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
unsigned const MachineRegisterInfo * MRI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:232
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:326
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:171
uint8_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:192
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:202
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:213
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:425
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:915
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:329
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:302
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:193
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:810
bool isStackAligningInlineAsm() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:277
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
bool isDebugInstr() const
Definition: MachineInstr.h:845
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
void setIsKill(bool Val=true)
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
Representation for a specific memory location.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:185
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
InlineAsm::AsmDialect getInlineAsmDialect() const
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:410
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
void setFlags(unsigned flags)
Definition: MachineInstr.h:206
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:843
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
iterator end() const
Definition: ArrayRef.h:138
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:642
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:459
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
int64_t getImm() const
void setMetadata(const MDNode *MD)
DWARF expression.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:446
Special value supplied for machine level alias analysis.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:480
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
const unsigned TiedMax
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:435
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
static DIExpression * prepend(const DIExpression *DIExpr, bool DerefBefore, int64_t Offset=0, bool DerefAfter=false, bool StackValue=false)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value...
std::pair< mmo_iterator, unsigned > mergeMemRefsWith(const MachineInstr &Other)
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of b...
This file provides utility analysis objects describing memory locations.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
Definition: MachineInstr.h:859
const Module * getModule() const
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:653
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:415
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
void unbundleFromSucc()
Break bundle below this instruction.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool isPosition() const
Definition: MachineInstr.h:841
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:172
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1073
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:960
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
Definition: MachineInstr.h:849
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr&#39;s memory reference descriptor list.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:197
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
const MDNode * getMetadata() const
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:170
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:411
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
bool isImplicit() const
Metadata reference (for debug info)
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:70
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.