LLVM  6.0.0svn
Public Member Functions | List of all members
llvm::HexagonInstrInfo Class Reference

#include "Target/Hexagon/HexagonInstrInfo.h"

Inheritance diagram for llvm::HexagonInstrInfo:
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Collaboration diagram for llvm::HexagonInstrInfo:
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Public Member Functions

 HexagonInstrInfo (HexagonSubtarget &ST)
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 TargetInstrInfo overrides. More...
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. More...
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 Remove the branching code at the end of the specific MBB. More...
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 Insert branch code into the end of the specified MachineBasicBlock. More...
 
bool analyzeLoop (MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
 Analyze the loop code, return true if it cannot be understood. More...
 
unsigned reduceLoopCount (MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
 Generate code to reduce the loop iteration by one and check if the loop is finished. More...
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted. More...
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override
 Second variant of isProfitableToIfCvt. More...
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion. More...
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 Emit instructions to copy a pair of physical registers. More...
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 Store the specified register of the given register class to the specified stack frame index. More...
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 Load the specified register of the given register class from the specified stack frame index. More...
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 This function is called for all pseudo instructions that remain after register allocation. More...
 
bool getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
 Get the base register and byte offset of a load/store instr. More...
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed. More...
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 Insert a noop into the instruction stream at the specified point. More...
 
bool isPredicated (const MachineInstr &MI) const override
 Returns true if the instruction is already predicated. More...
 
bool isPostIncrement (const MachineInstr &MI) const override
 Return true for post-incremented instructions. More...
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
 Convert the instruction into a predicated instruction. More...
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 Returns true if the first specified predicate subsumes the second, e.g. More...
 
bool DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
 If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference. More...
 
bool isPredicable (const MachineInstr &MI) const override
 Return true if the specified instruction can be predicated. More...
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 Test if the given instruction should be considered a scheduling boundary. More...
 
unsigned getInlineAsmLength (const char *Str, const MCAsmInfo &MAI) const override
 Measure the specified inline asm to determine an approximation of its length. More...
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation. More...
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
 For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 Compute the instruction latency of a given instruction. More...
 
DFAPacketizerCreateTargetScheduleState (const TargetSubtargetInfo &STI) const override
 Create machine specific model for scheduling. More...
 
bool areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
 
bool getBaseAndOffsetPosition (const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
 For instructions with a base and offset, return the position of the base register and offset operands. More...
 
bool getIncrementValue (const MachineInstr &MI, int &Value) const override
 If the instruction is an increment of a constant value, return the amount. More...
 
int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 getOperandLatency - Compute and return the use operand latency of a given pair of def and use. More...
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied. More...
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 Return an array that contains the direct target flag values and their names. More...
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 Return an array that contains the bitmask target flag values and their names. More...
 
bool isTailCall (const MachineInstr &MI) const override
 
unsigned createVR (MachineFunction *MF, MVT VT) const
 HexagonInstrInfo specifics. More...
 
bool isAbsoluteSet (const MachineInstr &MI) const
 
bool isAccumulator (const MachineInstr &MI) const
 
bool isComplex (const MachineInstr &MI) const
 
bool isCompoundBranchInstr (const MachineInstr &MI) const
 
bool isConstExtended (const MachineInstr &MI) const
 
bool isDeallocRet (const MachineInstr &MI) const
 
bool isDependent (const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
 
bool isDotCurInst (const MachineInstr &MI) const
 
bool isDotNewInst (const MachineInstr &MI) const
 
bool isDuplexPair (const MachineInstr &MIa, const MachineInstr &MIb) const
 Symmetrical. See if these two instructions are fit for duplex pair. More...
 
bool isEarlySourceInstr (const MachineInstr &MI) const
 
bool isEndLoopN (unsigned Opcode) const
 
bool isExpr (unsigned OpType) const
 
bool isExtendable (const MachineInstr &MI) const
 
bool isExtended (const MachineInstr &MI) const
 
bool isFloat (const MachineInstr &MI) const
 
bool isHVXMemWithAIndirect (const MachineInstr &I, const MachineInstr &J) const
 
bool isIndirectCall (const MachineInstr &MI) const
 
bool isIndirectL4Return (const MachineInstr &MI) const
 
bool isJumpR (const MachineInstr &MI) const
 
bool isJumpWithinBranchRange (const MachineInstr &MI, unsigned offset) const
 
bool isLateInstrFeedsEarlyInstr (const MachineInstr &LRMI, const MachineInstr &ESMI) const
 
bool isLateResultInstr (const MachineInstr &MI) const
 
bool isLateSourceInstr (const MachineInstr &MI) const
 
bool isLoopN (const MachineInstr &MI) const
 
bool isMemOp (const MachineInstr &MI) const
 
bool isNewValue (const MachineInstr &MI) const
 
bool isNewValue (unsigned Opcode) const
 
bool isNewValueInst (const MachineInstr &MI) const
 
bool isNewValueJump (const MachineInstr &MI) const
 
bool isNewValueJump (unsigned Opcode) const
 
bool isNewValueStore (const MachineInstr &MI) const
 
bool isNewValueStore (unsigned Opcode) const
 
bool isOperandExtended (const MachineInstr &MI, unsigned OperandNum) const
 
bool isPredicatedNew (const MachineInstr &MI) const
 
bool isPredicatedNew (unsigned Opcode) const
 
bool isPredicatedTrue (const MachineInstr &MI) const
 
bool isPredicatedTrue (unsigned Opcode) const
 
bool isPredicated (unsigned Opcode) const
 
bool isPredicateLate (unsigned Opcode) const
 
bool isPredictedTaken (unsigned Opcode) const
 
bool isSaveCalleeSavedRegsCall (const MachineInstr &MI) const
 
bool isSignExtendingLoad (const MachineInstr &MI) const
 
bool isSolo (const MachineInstr &MI) const
 
bool isSpillPredRegOp (const MachineInstr &MI) const
 
bool isTC1 (const MachineInstr &MI) const
 
bool isTC2 (const MachineInstr &MI) const
 
bool isTC2Early (const MachineInstr &MI) const
 
bool isTC4x (const MachineInstr &MI) const
 
bool isToBeScheduledASAP (const MachineInstr &MI1, const MachineInstr &MI2) const
 
bool isHVXVec (const MachineInstr &MI) const
 
bool isValidAutoIncImm (const EVT VT, const int Offset) const
 
bool isValidOffset (unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
 
bool isVecAcc (const MachineInstr &MI) const
 
bool isVecALU (const MachineInstr &MI) const
 
bool isVecUsableNextPacket (const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
 
bool isZeroExtendingLoad (const MachineInstr &MI) const
 
bool addLatencyToSchedule (const MachineInstr &MI1, const MachineInstr &MI2) const
 
bool canExecuteInBundle (const MachineInstr &First, const MachineInstr &Second) const
 Can these instructions execute at the same time in a bundle. More...
 
bool doesNotReturn (const MachineInstr &CallMI) const
 
bool hasEHLabel (const MachineBasicBlock *B) const
 
bool hasNonExtEquivalent (const MachineInstr &MI) const
 
bool hasPseudoInstrPair (const MachineInstr &MI) const
 
bool hasUncondBranch (const MachineBasicBlock *B) const
 
bool mayBeCurLoad (const MachineInstr &MI) const
 
bool mayBeNewStore (const MachineInstr &MI) const
 
bool producesStall (const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
 
bool producesStall (const MachineInstr &MI, MachineBasicBlock::const_instr_iterator MII) const
 
bool predCanBeUsedAsDotNew (const MachineInstr &MI, unsigned PredReg) const
 
bool PredOpcodeHasJMP_c (unsigned Opcode) const
 
bool predOpcodeHasNot (ArrayRef< MachineOperand > Cond) const
 
unsigned getAddrMode (const MachineInstr &MI) const
 
unsigned getBaseAndOffset (const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
 
SmallVector< MachineInstr *, 2 > getBranchingInstrs (MachineBasicBlock &MBB) const
 
unsigned getCExtOpNum (const MachineInstr &MI) const
 
HexagonII::CompoundGroup getCompoundCandidateGroup (const MachineInstr &MI) const
 
unsigned getCompoundOpcode (const MachineInstr &GA, const MachineInstr &GB) const
 
int getCondOpcode (int Opc, bool sense) const
 
int getDotCurOp (const MachineInstr &MI) const
 
int getNonDotCurOp (const MachineInstr &MI) const
 
int getDotNewOp (const MachineInstr &MI) const
 
int getDotNewPredJumpOp (const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
 
int getDotNewPredOp (const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
 
int getDotOldOp (const MachineInstr &MI) const
 
HexagonII::SubInstructionGroup getDuplexCandidateGroup (const MachineInstr &MI) const
 
short getEquivalentHWInstr (const MachineInstr &MI) const
 
MachineInstrgetFirstNonDbgInst (MachineBasicBlock *BB) const
 
unsigned getInstrTimingClassLatency (const InstrItineraryData *ItinData, const MachineInstr &MI) const
 
bool getInvertedPredSense (SmallVectorImpl< MachineOperand > &Cond) const
 
unsigned getInvertedPredicatedOpcode (const int Opc) const
 
int getMaxValue (const MachineInstr &MI) const
 
unsigned getMemAccessSize (const MachineInstr &MI) const
 
int getMinValue (const MachineInstr &MI) const
 
short getNonExtOpcode (const MachineInstr &MI) const
 
bool getPredReg (ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
 
short getPseudoInstrPair (const MachineInstr &MI) const
 
short getRegForm (const MachineInstr &MI) const
 
unsigned getSize (const MachineInstr &MI) const
 
uint64_t getType (const MachineInstr &MI) const
 
unsigned getUnits (const MachineInstr &MI) const
 
unsigned nonDbgBBSize (const MachineBasicBlock *BB) const
 getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available. More...
 
unsigned nonDbgBundleSize (MachineBasicBlock::const_iterator BundleHead) const
 
void immediateExtend (MachineInstr &MI) const
 immediateExtend - Changes the instruction in place to one using an immediate extender. More...
 
bool invertAndChangeJumpTarget (MachineInstr &MI, MachineBasicBlock *NewTarget) const
 
void genAllInsnTimingClasses (MachineFunction &MF) const
 
bool reversePredSense (MachineInstr &MI) const
 
unsigned reversePrediction (unsigned Opcode) const
 
bool validateBranchCond (const ArrayRef< MachineOperand > &Cond) const
 
short changeAddrMode_abs_io (short Opc) const
 
short changeAddrMode_io_abs (short Opc) const
 
short changeAddrMode_io_rr (short Opc) const
 
short changeAddrMode_rr_io (short Opc) const
 
short changeAddrMode_rr_ur (short Opc) const
 
short changeAddrMode_ur_rr (short Opc) const
 
short changeAddrMode_abs_io (const MachineInstr &MI) const
 
short changeAddrMode_io_abs (const MachineInstr &MI) const
 
short changeAddrMode_io_rr (const MachineInstr &MI) const
 
short changeAddrMode_rr_io (const MachineInstr &MI) const
 
short changeAddrMode_rr_ur (const MachineInstr &MI) const
 
short changeAddrMode_ur_rr (const MachineInstr &MI) const
 

Detailed Description

Definition at line 39 of file HexagonInstrInfo.h.

Constructor & Destructor Documentation

◆ HexagonInstrInfo()

HexagonInstrInfo::HexagonInstrInfo ( HexagonSubtarget ST)
explicit

Definition at line 118 of file HexagonInstrInfo.cpp.

Member Function Documentation

◆ addLatencyToSchedule()

bool HexagonInstrInfo::addLatencyToSchedule ( const MachineInstr MI1,
const MachineInstr MI2 
) const

Definition at line 2670 of file HexagonInstrInfo.cpp.

References isHVXVec(), and isVecUsableNextPacket().

◆ analyzeBranch()

bool HexagonInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

This function can analyze one/two way branching only and should (mostly) be called by target independent side.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

  1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
  2. If this block ends with only an unconditional branch, it sets TBB to be the destination block.
  3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
  4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm

Definition at line 350 of file HexagonInstrInfo.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::MachineOperand::CreateImm(), llvm::dbgs(), DEBUG, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), isEndLoopN(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), isNewValueJump(), PredOpcodeHasJMP_c(), llvm::printMBBReference(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::createHexagonHardwareLoops(), insertBranch(), isImmValidForOpcode(), parseCond(), and profitImm().

◆ analyzeCompare()

bool HexagonInstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  Mask,
int &  Value 
) const
override

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1516 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().

Referenced by llvm::createHexagonHardwareLoops(), and profitImm().

◆ analyzeLoop()

bool HexagonInstrInfo::analyzeLoop ( MachineLoop L,
MachineInstr *&  IndVarInst,
MachineInstr *&  CmpInst 
) const
override

Analyze the loop code, return true if it cannot be understood.

Analyze the loop code to find the loop induction variable and compare used to compute the number of iterations.

Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.

Currently, we analyze loop that are controlled using hardware loops. In this case, the induction variable instruction is null. For all other cases, this function returns true, which means we're unable to analyze it.

Definition at line 646 of file HexagonInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineLoop::getBottomBlock(), llvm::MachineBasicBlock::getFirstTerminator(), I, and isEndLoopN().

◆ areMemAccessesTriviallyDisjoint()

bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override

◆ canExecuteInBundle()

bool HexagonInstrInfo::canExecuteInBundle ( const MachineInstr First,
const MachineInstr Second 
) const

◆ changeAddrMode_abs_io() [1/2]

short HexagonInstrInfo::changeAddrMode_abs_io ( short  Opc) const

Definition at line 4098 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_abs_io().

◆ changeAddrMode_abs_io() [2/2]

short llvm::HexagonInstrInfo::changeAddrMode_abs_io ( const MachineInstr MI) const
inline

Definition at line 473 of file HexagonInstrInfo.h.

References changeAddrMode_abs_io(), and llvm::MachineInstr::getOpcode().

◆ changeAddrMode_io_abs() [1/2]

short HexagonInstrInfo::changeAddrMode_io_abs ( short  Opc) const

Definition at line 4102 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_io_abs().

◆ changeAddrMode_io_abs() [2/2]

short llvm::HexagonInstrInfo::changeAddrMode_io_abs ( const MachineInstr MI) const
inline

Definition at line 476 of file HexagonInstrInfo.h.

References changeAddrMode_io_abs(), and llvm::MachineInstr::getOpcode().

◆ changeAddrMode_io_rr() [1/2]

short HexagonInstrInfo::changeAddrMode_io_rr ( short  Opc) const

Definition at line 4106 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_io_rr().

◆ changeAddrMode_io_rr() [2/2]

short llvm::HexagonInstrInfo::changeAddrMode_io_rr ( const MachineInstr MI) const
inline

Definition at line 479 of file HexagonInstrInfo.h.

References changeAddrMode_io_rr(), and llvm::MachineInstr::getOpcode().

◆ changeAddrMode_rr_io() [1/2]

short HexagonInstrInfo::changeAddrMode_rr_io ( short  Opc) const

Definition at line 4110 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_rr_io().

◆ changeAddrMode_rr_io() [2/2]

short llvm::HexagonInstrInfo::changeAddrMode_rr_io ( const MachineInstr MI) const
inline

Definition at line 482 of file HexagonInstrInfo.h.

References changeAddrMode_rr_io(), and llvm::MachineInstr::getOpcode().

◆ changeAddrMode_rr_ur() [1/2]

short HexagonInstrInfo::changeAddrMode_rr_ur ( short  Opc) const

Definition at line 4114 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_rr_ur().

◆ changeAddrMode_rr_ur() [2/2]

short llvm::HexagonInstrInfo::changeAddrMode_rr_ur ( const MachineInstr MI) const
inline

Definition at line 485 of file HexagonInstrInfo.h.

References changeAddrMode_rr_ur(), and llvm::MachineInstr::getOpcode().

◆ changeAddrMode_ur_rr() [1/2]

short HexagonInstrInfo::changeAddrMode_ur_rr ( short  Opc) const

Definition at line 4118 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_ur_rr().

◆ changeAddrMode_ur_rr() [2/2]

short llvm::HexagonInstrInfo::changeAddrMode_ur_rr ( const MachineInstr MI) const
inline

Definition at line 488 of file HexagonInstrInfo.h.

References changeAddrMode_ur_rr(), and llvm::MachineInstr::getOpcode().

◆ copyPhysReg()

void HexagonInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

Emit instructions to copy a pair of physical registers.

This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.

The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.

Definition at line 741 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::dbgs(), llvm::getKillRegState(), llvm::HexagonSubtarget::getRegisterInfo(), llvm_unreachable, llvm::printMBBReference(), and llvm::printReg().

Referenced by expandPostRAPseudo(), INITIALIZE_PASS(), and isLEASimpleIncOrDec().

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * HexagonInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.

Definition at line 1505 of file HexagonInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), and UseDFAHazardRec.

◆ CreateTargetScheduleState()

DFAPacketizer * HexagonInstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo STI) const
override

Create machine specific model for scheduling.

Definition at line 1611 of file HexagonInstrInfo.cpp.

References llvm::TargetSubtargetInfo::getInstrItineraryData().

◆ createVR()

unsigned HexagonInstrInfo::createVR ( MachineFunction MF,
MVT  VT 
) const

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > HexagonInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.

Definition at line 1702 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::MO_Bitmasks.

Referenced by llvm::MIPrinter::printTargetFlags().

◆ DefinesPredicate()

bool HexagonInstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override

If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

Definition at line 1372 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), and llvm::MachineInstr::modifiesRegister().

◆ doesNotReturn()

bool HexagonInstrInfo::doesNotReturn ( const MachineInstr CallMI) const

◆ expandPostRAPseudo()

bool HexagonInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

This function is called for all pseudo instructions that remain after register allocation.

expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.

Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.

Definition at line 975 of file HexagonInstrInfo.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), copyPhysReg(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::getDebugLoc(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), getLiveRegsAt(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::getRegState(), llvm::MachineOperand::getSubReg(), llvm::RegState::Implicit, llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, MRI, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::RegState::Undef.

Referenced by INITIALIZE_PASS().

◆ genAllInsnTimingClasses()

void HexagonInstrInfo::genAllInsnTimingClasses ( MachineFunction MF) const

◆ getAddrMode()

unsigned HexagonInstrInfo::getAddrMode ( const MachineInstr MI) const

◆ getBaseAndOffset()

unsigned HexagonInstrInfo::getBaseAndOffset ( const MachineInstr MI,
int &  Offset,
unsigned AccessSize 
) const

◆ getBaseAndOffsetPosition()

bool HexagonInstrInfo::getBaseAndOffsetPosition ( const MachineInstr MI,
unsigned BasePos,
unsigned OffsetPos 
) const
override

For instructions with a base and offset, return the position of the base register and offset operands.

Return the position of the base and offset operands for this instruction.

Definition at line 2907 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), isPredicated(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().

Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), and getIncrementValue().

◆ getBranchingInstrs()

SmallVector< MachineInstr *, 2 > HexagonInstrInfo::getBranchingInstrs ( MachineBasicBlock MBB) const

◆ getCExtOpNum()

unsigned HexagonInstrInfo::getCExtOpNum ( const MachineInstr MI) const

◆ getCompoundCandidateGroup()

HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup ( const MachineInstr MI) const

◆ getCompoundOpcode()

unsigned HexagonInstrInfo::getCompoundOpcode ( const MachineInstr GA,
const MachineInstr GB 
) const

◆ getCondOpcode()

int HexagonInstrInfo::getCondOpcode ( int  Opc,
bool  sense 
) const

Definition at line 3111 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

Referenced by PredicateInstruction().

◆ getDotCurOp()

int HexagonInstrInfo::getDotCurOp ( const MachineInstr MI) const

Definition at line 3123 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and llvm_unreachable.

◆ getDotNewOp()

int HexagonInstrInfo::getDotNewOp ( const MachineInstr MI) const

◆ getDotNewPredJumpOp()

int HexagonInstrInfo::getDotNewPredJumpOp ( const MachineInstr MI,
const MachineBranchProbabilityInfo MBPI 
) const

◆ getDotNewPredOp()

int HexagonInstrInfo::getDotNewPredOp ( const MachineInstr MI,
const MachineBranchProbabilityInfo MBPI 
) const

◆ getDotOldOp()

int HexagonInstrInfo::getDotOldOp ( const MachineInstr MI) const

◆ getDuplexCandidateGroup()

HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup ( const MachineInstr MI) const

◆ getEquivalentHWInstr()

short HexagonInstrInfo::getEquivalentHWInstr ( const MachineInstr MI) const

Definition at line 3771 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ getFirstNonDbgInst()

MachineInstr* llvm::HexagonInstrInfo::getFirstNonDbgInst ( MachineBasicBlock BB) const

◆ getIncrementValue()

bool HexagonInstrInfo::getIncrementValue ( const MachineInstr MI,
int &  Value 
) const
override

If the instruction is an increment of a constant value, return the amount.

Definition at line 1679 of file HexagonInstrInfo.cpp.

References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and isPostIncrement().

◆ getInlineAsmLength()

unsigned HexagonInstrInfo::getInlineAsmLength ( const char Str,
const MCAsmInfo MAI 
) const
override

Measure the specified inline asm to determine an approximation of its length.

Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. Hexagon counts the number of ##'s and adjust for that many constant exenders.

Definition at line 1479 of file HexagonInstrInfo.cpp.

References llvm::StringRef::count(), llvm::StringRef::data(), llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), and llvm::StringRef::size().

Referenced by getSize(), and opcodeEmitsNoInsts().

◆ getInstrLatency()

unsigned HexagonInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned PredCost = nullptr 
) const
override

Compute the instruction latency of a given instruction.

If the instruction has higher cost when predicated, it's returned via PredCost.

Definition at line 1605 of file HexagonInstrInfo.cpp.

References getInstrTimingClassLatency().

Referenced by llvm::createX86PadShortFunctions(), getInstrTimingClassLatency(), and getPreviousInstr().

◆ getInstrTimingClassLatency()

unsigned HexagonInstrInfo::getInstrTimingClassLatency ( const InstrItineraryData ItinData,
const MachineInstr MI 
) const

◆ getInvertedPredicatedOpcode()

unsigned HexagonInstrInfo::getInvertedPredicatedOpcode ( const int  Opc) const

◆ getInvertedPredSense()

bool HexagonInstrInfo::getInvertedPredSense ( SmallVectorImpl< MachineOperand > &  Cond) const

◆ getMaxValue()

int HexagonInstrInfo::getMaxValue ( const MachineInstr MI) const

◆ getMemAccessSize()

unsigned HexagonInstrInfo::getMemAccessSize ( const MachineInstr MI) const

◆ getMemOpBaseRegImmOfs()

bool HexagonInstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
const TargetRegisterInfo TRI 
) const
override

Get the base register and byte offset of a load/store instr.

Definition at line 2679 of file HexagonInstrInfo.cpp.

References getBaseAndOffset().

Referenced by llvm::createStoreClusterDAGMutation(), and INITIALIZE_PASS().

◆ getMinValue()

int HexagonInstrInfo::getMinValue ( const MachineInstr MI) const

◆ getNonDotCurOp()

int HexagonInstrInfo::getNonDotCurOp ( const MachineInstr MI) const

Definition at line 3139 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and llvm_unreachable.

◆ getNonExtOpcode()

short HexagonInstrInfo::getNonExtOpcode ( const MachineInstr MI) const

◆ getOperandLatency()

int HexagonInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

getOperandLatency - Compute and return the use operand latency of a given pair of def and use.

In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.

This is a raw interface to the itinerary that may be directly overriden by a target. Use computeOperandLatency to get the best estimate of latency.

Definition at line 3795 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getOperand(), llvm::TargetInstrInfo::getOperandLatency(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), and llvm::MCRegisterInfo::DiffListIterator::isValid().

Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), and llvm::HexagonSubtarget::usePredicatedCalls().

◆ getPredReg()

bool HexagonInstrInfo::getPredReg ( ArrayRef< MachineOperand Cond,
unsigned PredReg,
unsigned PredRegPos,
unsigned PredRegFlags 
) const

◆ getPseudoInstrPair()

short HexagonInstrInfo::getPseudoInstrPair ( const MachineInstr MI) const

Definition at line 3946 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ getRegForm()

short HexagonInstrInfo::getRegForm ( const MachineInstr MI) const

Definition at line 3950 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

Return an array that contains the bitmask target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 1727 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::HMOTF_ConstExtended, and llvm::makeArrayRef().

Referenced by initSlots2Values(), and llvm::MIPrinter::printTargetFlags().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Return an array that contains the direct target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 1708 of file HexagonInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::HexagonII::MO_GDGOT, llvm::HexagonII::MO_GDPLT, llvm::AArch64II::MO_GOT, llvm::HexagonII::MO_GPREL, llvm::ARMII::MO_HI16, llvm::HexagonII::MO_IE, llvm::HexagonII::MO_IEGOT, llvm::ARMII::MO_LO16, llvm::HexagonII::MO_PCREL, and llvm::HexagonII::MO_TPREL.

Referenced by initSlots2Values().

◆ getSize()

unsigned HexagonInstrInfo::getSize ( const MachineInstr MI) const

◆ getType()

uint64_t HexagonInstrInfo::getType ( const MachineInstr MI) const

◆ getUnits()

unsigned HexagonInstrInfo::getUnits ( const MachineInstr MI) const

◆ hasEHLabel()

bool HexagonInstrInfo::hasEHLabel ( const MachineBasicBlock B) const

Definition at line 2720 of file HexagonInstrInfo.cpp.

References I.

◆ hasNonExtEquivalent()

bool HexagonInstrInfo::hasNonExtEquivalent ( const MachineInstr MI) const

◆ hasPseudoInstrPair()

bool HexagonInstrInfo::hasPseudoInstrPair ( const MachineInstr MI) const

Definition at line 2764 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ hasUncondBranch()

bool HexagonInstrInfo::hasUncondBranch ( const MachineBasicBlock B) const

◆ immediateExtend()

void HexagonInstrInfo::immediateExtend ( MachineInstr MI) const

◆ insertBranch()

unsigned HexagonInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

Insert branch code into the end of the specified MachineBasicBlock.

The operands to this method are the same as those returned by AnalyzeBranch. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions inserted.

It is also invoked by tail merging to add unconditional branches in cases where AnalyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.

Definition at line 543 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), llvm::dbgs(), DEBUG, llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getReg(), llvm::getUndefRegState(), isEndLoopN(), isNewValueJump(), isPredicated(), isReg(), llvm::MachineOperand::isUndef(), isUndef(), llvm_unreachable, llvm::printMBBReference(), removeBranch(), reverseBranchCondition(), llvm::MachineOperand::setMBB(), llvm::ArrayRef< T >::size(), and validateBranchCond().

Referenced by llvm::createHexagonHardwareLoops(), and isImmValidForOpcode().

◆ insertNoop()

void HexagonInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

Insert a noop into the instruction stream at the specified point.

Definition at line 1292 of file HexagonInstrInfo.cpp.

References llvm::BuildMI().

Referenced by INITIALIZE_PASS().

◆ invertAndChangeJumpTarget()

bool HexagonInstrInfo::invertAndChangeJumpTarget ( MachineInstr MI,
MachineBasicBlock NewTarget 
) const

◆ isAbsoluteSet()

bool HexagonInstrInfo::isAbsoluteSet ( const MachineInstr MI) const

Definition at line 1753 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::AbsoluteSet, and getAddrMode().

◆ isAccumulator()

bool HexagonInstrInfo::isAccumulator ( const MachineInstr MI) const

◆ isComplex()

bool HexagonInstrInfo::isComplex ( const MachineInstr MI) const

◆ isCompoundBranchInstr()

bool HexagonInstrInfo::isCompoundBranchInstr ( const MachineInstr MI) const

◆ isConstExtended()

bool HexagonInstrInfo::isConstExtended ( const MachineInstr MI) const

◆ isDeallocRet()

bool HexagonInstrInfo::isDeallocRet ( const MachineInstr MI) const

Definition at line 1820 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isDependent()

bool HexagonInstrInfo::isDependent ( const MachineInstr ProdMI,
const MachineInstr ConsMI 
) const

◆ isDotCurInst()

bool HexagonInstrInfo::isDotCurInst ( const MachineInstr MI) const

Definition at line 1870 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isDotNewInst()

bool HexagonInstrInfo::isDotNewInst ( const MachineInstr MI) const

Definition at line 1881 of file HexagonInstrInfo.cpp.

References isNewValueInst(), isPredicated(), and isPredicatedNew().

◆ isDuplexPair()

bool HexagonInstrInfo::isDuplexPair ( const MachineInstr MIa,
const MachineInstr MIb 
) const

Symmetrical. See if these two instructions are fit for duplex pair.

Definition at line 1889 of file HexagonInstrInfo.cpp.

References getDuplexCandidateGroup(), and isDuplexPairMatch().

◆ isEarlySourceInstr()

bool HexagonInstrInfo::isEarlySourceInstr ( const MachineInstr MI) const

◆ isEndLoopN()

bool HexagonInstrInfo::isEndLoopN ( unsigned  Opcode) const

◆ isExpr()

bool HexagonInstrInfo::isExpr ( unsigned  OpType) const

◆ isExtendable()

bool HexagonInstrInfo::isExtendable ( const MachineInstr MI) const

◆ isExtended()

bool HexagonInstrInfo::isExtended ( const MachineInstr MI) const

◆ isFloat()

bool HexagonInstrInfo::isFloat ( const MachineInstr MI) const

◆ isHVXMemWithAIndirect()

bool HexagonInstrInfo::isHVXMemWithAIndirect ( const MachineInstr I,
const MachineInstr J 
) const

◆ isHVXVec()

bool HexagonInstrInfo::isHVXVec ( const MachineInstr MI) const

◆ isIndirectCall()

bool HexagonInstrInfo::isIndirectCall ( const MachineInstr MI) const

Definition at line 1975 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by isHVXMemWithAIndirect().

◆ isIndirectL4Return()

bool HexagonInstrInfo::isIndirectL4Return ( const MachineInstr MI) const

Definition at line 1986 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by isHVXMemWithAIndirect().

◆ isJumpR()

bool HexagonInstrInfo::isJumpR ( const MachineInstr MI) const

Definition at line 2000 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isJumpWithinBranchRange()

bool HexagonInstrInfo::isJumpWithinBranchRange ( const MachineInstr MI,
unsigned  offset 
) const

Definition at line 2018 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isNewValueJump().

◆ isLateInstrFeedsEarlyInstr()

bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr ( const MachineInstr LRMI,
const MachineInstr ESMI 
) const

◆ isLateResultInstr()

bool HexagonInstrInfo::isLateResultInstr ( const MachineInstr MI) const

◆ isLateSourceInstr()

bool HexagonInstrInfo::isLateSourceInstr ( const MachineInstr MI) const

Definition at line 2095 of file HexagonInstrInfo.cpp.

References getType(), and llvm::HexagonII::TypeCVI_VX_LATE.

Referenced by isVecUsableNextPacket().

◆ isLoadFromStackSlot()

unsigned HexagonInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

TargetInstrInfo overrides.

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 240 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

Referenced by isFullCopyOf().

◆ isLoopN()

bool HexagonInstrInfo::isLoopN ( const MachineInstr MI) const

Definition at line 2101 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isMemOp()

bool HexagonInstrInfo::isMemOp ( const MachineInstr MI) const

◆ isNewValue() [1/2]

bool HexagonInstrInfo::isNewValue ( const MachineInstr MI) const

◆ isNewValue() [2/2]

bool HexagonInstrInfo::isNewValue ( unsigned  Opcode) const

◆ isNewValueInst()

bool HexagonInstrInfo::isNewValueInst ( const MachineInstr MI) const

Definition at line 2155 of file HexagonInstrInfo.cpp.

References isNewValueJump(), and isNewValueStore().

Referenced by isDotNewInst().

◆ isNewValueJump() [1/2]

bool HexagonInstrInfo::isNewValueJump ( const MachineInstr MI) const

◆ isNewValueJump() [2/2]

bool HexagonInstrInfo::isNewValueJump ( unsigned  Opcode) const

Definition at line 2163 of file HexagonInstrInfo.cpp.

References isBranch(), isNewValue(), and isPredicated().

◆ isNewValueStore() [1/2]

bool HexagonInstrInfo::isNewValueStore ( const MachineInstr MI) const

◆ isNewValueStore() [2/2]

bool HexagonInstrInfo::isNewValueStore ( unsigned  Opcode) const

◆ isOperandExtended()

bool HexagonInstrInfo::isOperandExtended ( const MachineInstr MI,
unsigned  OperandNum 
) const

◆ isPostIncrement()

bool HexagonInstrInfo::isPostIncrement ( const MachineInstr MI) const
override

Return true for post-incremented instructions.

Definition at line 1298 of file HexagonInstrInfo.cpp.

References getAddrMode(), and llvm::HexagonII::PostInc.

Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), getIncrementValue(), and getPostIncrementOperand().

◆ isPredicable()

bool HexagonInstrInfo::isPredicable ( const MachineInstr MI) const
override

Return true if the specified instruction can be predicated.

By default, this returns true for every instruction with a PredicateOperand.

Definition at line 1399 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::HexagonSubtarget::hasV62TOps(), llvm::MachineInstr::isCall(), llvm::MCInstrDesc::isPredicable(), isTailCall(), and llvm::HexagonSubtarget::usePredicatedCalls().

Referenced by PredicateInstruction().

◆ isPredicated() [1/2]

bool HexagonInstrInfo::isPredicated ( const MachineInstr MI) const
override

◆ isPredicated() [2/2]

bool HexagonInstrInfo::isPredicated ( unsigned  Opcode) const

◆ isPredicatedNew() [1/2]

bool HexagonInstrInfo::isPredicatedNew ( const MachineInstr MI) const

◆ isPredicatedNew() [2/2]

bool HexagonInstrInfo::isPredicatedNew ( unsigned  Opcode) const

◆ isPredicatedTrue() [1/2]

bool HexagonInstrInfo::isPredicatedTrue ( const MachineInstr MI) const

◆ isPredicatedTrue() [2/2]

bool HexagonInstrInfo::isPredicatedTrue ( unsigned  Opcode) const

◆ isPredicateLate()

bool HexagonInstrInfo::isPredicateLate ( unsigned  Opcode) const

◆ isPredictedTaken()

bool HexagonInstrInfo::isPredictedTaken ( unsigned  Opcode) const

◆ isProfitableToDupForIfCvt()

bool HexagonInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
override

Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.

The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 736 of file HexagonInstrInfo.cpp.

◆ isProfitableToIfCvt() [1/2]

bool HexagonInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
override

Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 723 of file HexagonInstrInfo.cpp.

References nonDbgBBSize().

◆ isProfitableToIfCvt() [2/2]

bool HexagonInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
BranchProbability  Probability 
) const
override

Second variant of isProfitableToIfCvt.

This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 729 of file HexagonInstrInfo.cpp.

References nonDbgBBSize().

◆ isSaveCalleeSavedRegsCall()

bool HexagonInstrInfo::isSaveCalleeSavedRegsCall ( const MachineInstr MI) const

Definition at line 2228 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isSchedulingBoundary()

bool HexagonInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

Test if the given instruction should be considered a scheduling boundary.

This primarily includes labels and terminators.

Definition at line 1435 of file HexagonInstrInfo.cpp.

References doesNotReturn(), llvm::MachineInstr::getDesc(), I, llvm::MachineInstr::isCall(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isPosition(), llvm::MCInstrDesc::isTerminator(), ScheduleInlineAsm, and llvm::MachineBasicBlock::successors().

Referenced by INITIALIZE_PASS().

◆ isSignExtendingLoad()

bool HexagonInstrInfo::isSignExtendingLoad ( const MachineInstr MI) const

Definition at line 2235 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isSolo()

bool HexagonInstrInfo::isSolo ( const MachineInstr MI) const

◆ isSpillPredRegOp()

bool HexagonInstrInfo::isSpillPredRegOp ( const MachineInstr MI) const

Definition at line 2318 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isStoreToStackSlot()

unsigned HexagonInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 288 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

Referenced by dumpMachineInstrRangeWithSlotIndex(), and isFullCopyOf().

◆ isTailCall()

bool HexagonInstrInfo::isTailCall ( const MachineInstr MI) const
override

Definition at line 2328 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::isBranch(), and llvm::MachineInstr::operands().

Referenced by isPredicable().

◆ isTC1()

bool HexagonInstrInfo::isTC1 ( const MachineInstr MI) const

◆ isTC2()

bool HexagonInstrInfo::isTC2 ( const MachineInstr MI) const

◆ isTC2Early()

bool HexagonInstrInfo::isTC2Early ( const MachineInstr MI) const

◆ isTC4x()

bool HexagonInstrInfo::isTC4x ( const MachineInstr MI) const

◆ isToBeScheduledASAP()

bool HexagonInstrInfo::isToBeScheduledASAP ( const MachineInstr MI1,
const MachineInstr MI2 
) const

◆ isValidAutoIncImm()

bool HexagonInstrInfo::isValidAutoIncImm ( const EVT  VT,
const int  Offset 
) const

◆ isValidOffset()

bool HexagonInstrInfo::isValidOffset ( unsigned  Opcode,
int  Offset,
const TargetRegisterInfo TRI,
bool  Extend = true 
) const

◆ isVecAcc()

bool HexagonInstrInfo::isVecAcc ( const MachineInstr MI) const

Definition at line 2565 of file HexagonInstrInfo.cpp.

References isAccumulator(), and isHVXVec().

Referenced by isVecUsableNextPacket().

◆ isVecALU()

bool HexagonInstrInfo::isVecALU ( const MachineInstr MI) const

◆ isVecUsableNextPacket()

bool HexagonInstrInfo::isVecUsableNextPacket ( const MachineInstr ProdMI,
const MachineInstr ConsMI 
) const

◆ isZeroExtendingLoad()

bool HexagonInstrInfo::isZeroExtendingLoad ( const MachineInstr MI) const

Definition at line 2591 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ loadRegFromStackSlot()

void HexagonInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ mayBeCurLoad()

bool HexagonInstrInfo::mayBeCurLoad ( const MachineInstr MI) const

◆ mayBeNewStore()

bool HexagonInstrInfo::mayBeNewStore ( const MachineInstr MI) const

◆ nonDbgBBSize()

unsigned HexagonInstrInfo::nonDbgBBSize ( const MachineBasicBlock BB) const

getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.

Definition at line 4005 of file HexagonInstrInfo.cpp.

References llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and nonDbgMICount().

Referenced by isProfitableToIfCvt().

◆ nonDbgBundleSize()

unsigned HexagonInstrInfo::nonDbgBundleSize ( MachineBasicBlock::const_iterator  BundleHead) const

◆ predCanBeUsedAsDotNew()

bool HexagonInstrInfo::predCanBeUsedAsDotNew ( const MachineInstr MI,
unsigned  PredReg 
) const

◆ PredicateInstruction()

bool HexagonInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Cond 
) const
override

◆ PredOpcodeHasJMP_c()

bool HexagonInstrInfo::PredOpcodeHasJMP_c ( unsigned  Opcode) const

Definition at line 2849 of file HexagonInstrInfo.cpp.

Referenced by analyzeBranch(), and profitImm().

◆ predOpcodeHasNot()

bool HexagonInstrInfo::predOpcodeHasNot ( ArrayRef< MachineOperand Cond) const

◆ producesStall() [1/2]

bool HexagonInstrInfo::producesStall ( const MachineInstr ProdMI,
const MachineInstr ConsMI 
) const

Definition at line 2793 of file HexagonInstrInfo.cpp.

References isDependent(), isHVXVec(), and isVecUsableNextPacket().

Referenced by producesStall().

◆ producesStall() [2/2]

bool HexagonInstrInfo::producesStall ( const MachineInstr MI,
MachineBasicBlock::const_instr_iterator  MII 
) const

Definition at line 2811 of file HexagonInstrInfo.cpp.

References isHVXVec(), and producesStall().

◆ reduceLoopCount()

unsigned HexagonInstrInfo::reduceLoopCount ( MachineBasicBlock MBB,
MachineInstr IndVar,
MachineInstr Cmp,
SmallVectorImpl< MachineOperand > &  Cond,
SmallVectorImpl< MachineInstr *> &  PrevInsts,
unsigned  Iter,
unsigned  MaxIter 
) const
override

◆ removeBranch()

unsigned HexagonInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

Remove the branching code at the end of the specific MBB.

This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.

Definition at line 520 of file HexagonInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::begin(), llvm::dbgs(), DEBUG, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), I, llvm_unreachable, and llvm::printMBBReference().

Referenced by insertBranch().

◆ reverseBranchCondition()

bool HexagonInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

Definition at line 1277 of file HexagonInstrInfo.cpp.

References assert(), llvm::SmallVectorBase::empty(), getInvertedPredicatedOpcode(), isBranch(), and isEndLoopN().

Referenced by insertBranch(), and isInRage().

◆ reversePrediction()

unsigned HexagonInstrInfo::reversePrediction ( unsigned  Opcode) const

Definition at line 4081 of file HexagonInstrInfo.cpp.

References assert(), and isPredictedTaken().

Referenced by invertAndChangeJumpTarget().

◆ reversePredSense()

bool HexagonInstrInfo::reversePredSense ( MachineInstr MI) const

◆ storeRegToStackSlot()

void HexagonInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ SubsumesPredicate()

bool HexagonInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

Returns true if the first specified predicate subsumes the second, e.g.

GE subsumes GT.

Definition at line 1366 of file HexagonInstrInfo.cpp.

◆ validateBranchCond()

bool HexagonInstrInfo::validateBranchCond ( const ArrayRef< MachineOperand > &  Cond) const

Definition at line 4092 of file HexagonInstrInfo.cpp.

References llvm::ArrayRef< T >::empty(), and llvm::ArrayRef< T >::size().

Referenced by insertBranch().


The documentation for this class was generated from the following files: