31 #define DEBUG_TYPE "framelowering" 32 STATISTIC(NumPESpillVSR,
"Number of spills to vector in prologue");
33 STATISTIC(NumPEReloadVSR,
"Number of reloads from vector in epilogue");
37 cl::desc(
"Enable spills in prologue to vector registers."),
43 PPC::V0 , PPC::V1 ,
PPC::V2 , PPC::V3 ,
PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
69 return STI.
isPPC64() ? -8U : -4U;
72 return STI.
isPPC64() ? -8U : -4U;
85 return STI.
isPPC64() ? -16U : -8U;
100 STI.getPlatformStackAlignment(), 0),
110 unsigned &NumEntries)
const {
114 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
115 return &darwin64Offsets;
117 static const SpillSlot darwinOffsets = {PPC::R31, -4};
118 return &darwinOffsets;
300 assert(MBBI != Entry->
end() && MBBI->getOpcode() == PPC::MTVRSAVE);
301 MBBI->eraseFromParent();
303 bool RemovedAllMTVRSAVEs =
true;
308 if (
I->isReturnBlock()) {
309 bool FoundIt =
false;
310 for (MBBI =
I->end(); MBBI !=
I->begin(); ) {
312 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
313 MBBI->eraseFromParent();
318 RemovedAllMTVRSAVEs &= FoundIt;
324 if (RemovedAllMTVRSAVEs) {
326 assert(MBBI != Entry->
begin() &&
"UPDATE_VRSAVE is first instr in block?");
328 assert(MBBI->getOpcode() == PPC::MFVRSAVE &&
"VRSAVE instrs wandered?");
329 MBBI->eraseFromParent();
345 unsigned UsedRegMask = 0;
346 for (
unsigned i = 0; i != 32; ++i)
348 UsedRegMask |= 1 << (31-i);
354 if (VRRegNo[RegNo] == LI.first)
355 UsedRegMask &= ~(1 << (31-RegNo));
360 UsedRegMask != 0 && BI != BE; ++BI) {
367 if (!MO.
isReg() || !PPC::VRRCRegClass.contains(MO.
getReg()))
370 UsedRegMask &= ~(1 << (31-RegNo));
375 if (UsedRegMask == 0) {
384 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
385 if (DstReg != SrcReg)
393 }
else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
394 if (DstReg != SrcReg)
397 .
addImm(UsedRegMask >> 16);
401 .
addImm(UsedRegMask >> 16);
403 if (DstReg != SrcReg)
406 .
addImm(UsedRegMask >> 16);
410 .
addImm(UsedRegMask >> 16);
414 .
addImm(UsedRegMask & 0xFFFF);
459 bool UseEstimate)
const {
460 unsigned NewMaxCallFrameSize = 0;
462 &NewMaxCallFrameSize);
473 unsigned *NewMaxCallFrameSize)
const {
484 unsigned AlignMask =
std::max(MaxAlign, TargetAlign) - 1;
488 unsigned LR = RegInfo->getRARegister();
501 if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
511 maxCallFrameSize =
std::max(maxCallFrameSize, minCallFrameSize);
516 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
519 if (NewMaxCallFrameSize)
520 *NewMaxCallFrameSize = maxCallFrameSize;
523 FrameSize += maxCallFrameSize;
526 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
560 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
561 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
566 unsigned BP8Reg = HasBP ? (
unsigned) PPC::X30 : FP8Reg;
572 for (
unsigned I = 0,
E = MBBI->getNumOperands();
I !=
E; ++
I) {
615 bool TwoUniqueRegsRequired,
617 unsigned *SR2)
const {
619 unsigned R0 = Subtarget.
isPPC64() ? PPC::X0 : PPC::R0;
620 unsigned R12 = Subtarget.
isPPC64() ? PPC::X12 : PPC::R12;
627 assert (SR1 &&
"Asking for the second scratch register but not the first?");
638 if (UseAtEnd && !MBB->
empty()) {
644 if (MBBI == MBB->
end())
645 MBBI = std::prev(MBBI);
647 if (MBBI != MBB->
begin())
670 for (
int i = 0; CSRegs[i]; ++i)
676 *SR1 = FirstScratchReg == -1 ? (
unsigned)PPC::NoRegister : FirstScratchReg;
683 int SecondScratchReg = BV.
find_next(*SR1);
684 if (SecondScratchReg != -1)
685 *SR2 = SecondScratchReg;
687 *SR2 = TwoUniqueRegsRequired ? (
unsigned)PPC::NoRegister : *SR1;
692 if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
709 int NegFrameSize = -FrameSize;
710 bool IsLargeFrame = !
isInt<16>(NegFrameSize);
715 return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
721 return findScratchRegister(TmpMBB,
false,
722 twoUniqueScratchRegsRequired(TmpMBB));
728 return findScratchRegister(TmpMBB,
true);
731 bool PPCFrameLowering::stackUpdateCanBeMoved(
MachineFunction &MF)
const {
789 bool isPPC64 = Subtarget.
isPPC64();
792 bool isAIXABI = Subtarget.
isAIXABI();
795 "Unsupported PPC ABI.");
800 for (
unsigned i = 0; MBBI != MBB.
end(); ++i, ++MBBI) {
801 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
814 int NegFrameSize = -FrameSize;
826 bool MustSaveCR = !MustSaveCRs.
empty();
828 bool HasFP =
hasFP(MF);
830 bool HasRedZone = isPPC64 || !isSVR4ABI;
832 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
834 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
835 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
836 unsigned TOCReg = isPPC64 ? PPC::X2 :
PPC::R2;
837 unsigned ScratchReg = 0;
838 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12;
840 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
844 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
846 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
848 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
850 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
852 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
854 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
856 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
863 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
864 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
867 bool SingleScratchReg =
868 findScratchRegister(&MBB,
false, twoUniqueScratchRegsRequired(&MBB),
869 &ScratchReg, &TempReg);
870 assert(SingleScratchReg &&
871 "Required number of registers not available in this block");
873 SingleScratchReg = ScratchReg == TempReg;
882 assert(FPIndex &&
"No Frame Pointer Save Slot!");
894 assert(BPIndex &&
"No Base Pointer Save Slot!");
905 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
911 if (HasBP && MaxAlign > 1)
913 "Invalid alignment!");
917 bool isLargeFrame = !
isInt<16>(NegFrameSize);
919 assert((isPPC64 || !MustSaveCR) &&
920 "Prologue CR saving supported only in 64-bit mode");
922 if (MustSaveCR && isAIXABI)
929 bool MovingStackUpdateDown =
false;
932 if (stackUpdateCanBeMoved(MF)) {
935 int FrIdx = CSI.getFrameIdx();
944 MovingStackUpdateDown =
true;
948 StackUpdateLoc = MBBI;
949 MovingStackUpdateDown =
false;
955 if (MovingStackUpdateDown) {
957 int FrIdx = CSI.getFrameIdx();
966 if (MustSaveCR && SingleScratchReg && MustSaveLR) {
971 unsigned MfcrOpcode = PPC::MFCR8;
973 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
974 MfcrOpcode = PPC::MFOCRF8;
978 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
979 for (
unsigned i = 0,
e = MustSaveCRs.
size(); i !=
e; ++i)
980 MIB.
addReg(MustSaveCRs[i], CrState);
981 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
988 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
991 !(SingleScratchReg && MustSaveLR)) {
996 unsigned MfcrOpcode = PPC::MFCR8;
998 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
999 MfcrOpcode = PPC::MFOCRF8;
1003 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
1004 for (
unsigned i = 0,
e = MustSaveCRs.
size(); i !=
e; ++i)
1005 MIB.
addReg(MustSaveCRs[i], CrState);
1010 BuildMI(MBB, MBBI, dl, StoreInst)
1015 BuildMI(MBB, MBBI, dl, StoreInst)
1020 BuildMI(MBB, MBBI, dl, StoreInst)
1027 BuildMI(MBB, StackUpdateLoc, dl, StoreInst)
1033 !(SingleScratchReg && MustSaveLR)) {
1034 assert(HasRedZone &&
"A red zone is always available on PPC64");
1035 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
1048 if (HasBP && HasRedZone) {
1050 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1057 bool HasSTUX =
false;
1060 if (HasBP && MaxAlign > 1) {
1062 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
1067 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
1072 if (!isLargeFrame) {
1073 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
1077 assert(!SingleScratchReg &&
"Only a single scratch reg available");
1078 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
1079 .
addImm(NegFrameSize >> 16);
1080 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
1082 .
addImm(NegFrameSize & 0xFFFF);
1083 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
1088 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
1094 }
else if (!isLargeFrame) {
1095 BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
1101 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1102 .
addImm(NegFrameSize >> 16);
1103 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1105 .
addImm(NegFrameSize & 0xFFFF);
1106 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
1116 assert(isELFv2ABI &&
"TOC saves in the prologue only supported on ELFv2");
1117 BuildMI(MBB, StackUpdateLoc, dl, TII.get(PPC::STD))
1119 .addImm(TOCSaveOffset)
1124 assert(!isPPC64 &&
"A red zone is always available on PPC64");
1136 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1140 if (ScratchReg == PPC::R0) {
1147 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1149 .
addImm(FPOffset-LastOffset);
1150 LastOffset = FPOffset;
1152 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1159 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1161 .
addImm(PBPOffset-LastOffset);
1162 LastOffset = PBPOffset;
1163 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1170 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1172 .
addImm(BPOffset-LastOffset);
1173 LastOffset = BPOffset;
1174 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1179 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1190 BuildMI(MBB, MBBI, dl, StoreInst)
1195 BuildMI(MBB, MBBI, dl, StoreInst)
1200 BuildMI(MBB, MBBI, dl, StoreInst)
1204 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1215 BuildMI(MBB, MBBI, dl, StoreInst)
1217 .
addImm(FrameSize + FPOffset)
1220 BuildMI(MBB, MBBI, dl, StoreInst)
1222 .
addImm(FrameSize + PBPOffset)
1225 BuildMI(MBB, MBBI, dl, StoreInst)
1227 .
addImm(FrameSize + BPOffset)
1229 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1253 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1254 .addCFIIndex(CFIIndex);
1261 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1262 .addCFIIndex(CFIIndex);
1270 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1271 .addCFIIndex(CFIIndex);
1279 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1280 .addCFIIndex(CFIIndex);
1288 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1289 .addCFIIndex(CFIIndex);
1295 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1299 if (!HasBP && needsCFI) {
1306 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1307 .addCFIIndex(CFIIndex);
1315 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
1316 unsigned Reg = CSI[
I].getReg();
1317 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg ==
PPC::RM)
continue;
1321 if (PPC::CRBITRCRegClass.
contains(Reg))
1324 if ((Reg == PPC::X2 || Reg ==
PPC::R2) && MustSaveTOC)
1329 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1335 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1339 unsigned CRReg = isELFv2ABI?
Reg : (
unsigned) PPC::CR2;
1342 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1343 .addCFIIndex(CFIIndex);
1347 if (CSI[
I].isSpilledToReg()) {
1348 unsigned SpilledReg = CSI[
I].getDstReg();
1352 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1353 .addCFIIndex(CFIRegister);
1359 if (MovingStackUpdateDown)
1360 Offset -= NegFrameSize;
1364 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1365 .addCFIIndex(CFIIndex);
1376 if (MBBI != MBB.
end())
1377 dl = MBBI->getDebugLoc();
1389 bool isPPC64 = Subtarget.
isPPC64();
1397 bool MustSaveCR = !MustSaveCRs.
empty();
1399 bool HasFP =
hasFP(MF);
1403 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1405 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1406 unsigned ScratchReg = 0;
1407 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12;
1408 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1412 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1414 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1416 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1418 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1420 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1428 bool SingleScratchReg = findScratchRegister(&MBB,
true,
false, &ScratchReg,
1430 assert(SingleScratchReg &&
1431 "Could not find an available scratch register");
1433 SingleScratchReg = ScratchReg == TempReg;
1438 assert(FPIndex &&
"No Frame Pointer Save Slot!");
1449 assert(BPIndex &&
"No Base Pointer Save Slot!");
1459 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1463 bool IsReturnBlock = (MBBI != MBB.
end() && MBBI->isReturn());
1465 if (IsReturnBlock) {
1466 unsigned RetOpcode = MBBI->getOpcode();
1467 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1468 RetOpcode == PPC::TCRETURNdi ||
1469 RetOpcode == PPC::TCRETURNai ||
1470 RetOpcode == PPC::TCRETURNri8 ||
1471 RetOpcode == PPC::TCRETURNdi8 ||
1472 RetOpcode == PPC::TCRETURNai8;
1477 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1479 int StackAdj = StackAdjust.
getImm();
1480 int Delta = StackAdj - MaxTCRetDelta;
1481 assert((Delta >= 0) &&
"Delta must be positive");
1482 if (MaxTCRetDelta>0)
1483 FrameSize += (StackAdj +Delta);
1485 FrameSize += StackAdj;
1491 bool isLargeFrame = !
isInt<16>(FrameSize);
1505 unsigned RBReg = SPReg;
1513 if (stackUpdateCanBeMoved(MF)) {
1516 int FrIdx = CSI.getFrameIdx();
1528 StackUpdateLoc = MBBI;
1544 assert(HasFP &&
"Expecting a valid frame pointer.");
1547 if (!isLargeFrame) {
1548 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1551 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1552 .
addImm(FrameSize >> 16);
1553 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1555 .
addImm(FrameSize & 0xFFFF);
1556 BuildMI(MBB, MBBI, dl, AddInst)
1563 BuildMI(MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1569 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1570 "Local offsets should be negative");
1572 FPOffset += FrameSize;
1573 BPOffset += FrameSize;
1574 PBPOffset += FrameSize;
1582 BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1587 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg)
1592 assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1597 assert((isPPC64 || !MustSaveCR) &&
1598 "Epilogue CR restoring supported only in 64-bit mode");
1602 if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1605 assert(HasRedZone &&
"Expecting red zone");
1606 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1609 for (
unsigned i = 0,
e = MustSaveCRs.
size(); i !=
e; ++i)
1610 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1618 bool LoadedLR =
false;
1619 if (MustSaveLR && RBReg == SPReg &&
isInt<16>(LROffset+SPAdd)) {
1620 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, ScratchReg)
1626 if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1628 assert(isPPC64 &&
"Expecting 64-bit mode");
1629 assert(RBReg == SPReg &&
"Should be using SP as a base register");
1630 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1638 if (HasRedZone || RBReg == SPReg)
1639 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1643 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1649 BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)
1654 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1660 if (RBReg != SPReg || SPAdd != 0) {
1661 assert(!HasRedZone &&
"This should not happen with red zone");
1664 BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1668 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1672 assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1674 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1679 if (MustSaveLR && !LoadedLR)
1680 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1686 !(SingleScratchReg && MustSaveLR))
1687 for (
unsigned i = 0,
e = MustSaveCRs.
size(); i !=
e; ++i)
1688 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1692 BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).
addReg(ScratchReg);
1696 if (IsReturnBlock) {
1697 unsigned RetOpcode = MBBI->getOpcode();
1699 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1704 if (CallerAllocatedAmt &&
isInt<16>(CallerAllocatedAmt)) {
1705 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1708 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1709 .
addImm(CallerAllocatedAmt >> 16);
1710 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1712 .
addImm(CallerAllocatedAmt & 0xFFFF);
1713 BuildMI(MBB, MBBI, dl, AddInst)
1719 createTailCallBranchInstr(MBB);
1724 void PPCFrameLowering::createTailCallBranchInstr(
MachineBasicBlock &MBB)
const {
1728 assert(MBBI != MBB.
end() &&
"Failed to find the first terminator.");
1734 unsigned RetOpcode = MBBI->getOpcode();
1735 if (RetOpcode == PPC::TCRETURNdi) {
1738 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1740 }
else if (RetOpcode == PPC::TCRETURNri) {
1742 assert(MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1743 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1744 }
else if (RetOpcode == PPC::TCRETURNai) {
1747 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.
getImm());
1748 }
else if (RetOpcode == PPC::TCRETURNdi8) {
1751 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1753 }
else if (RetOpcode == PPC::TCRETURNri8) {
1755 assert(MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1756 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1757 }
else if (RetOpcode == PPC::TCRETURNai8) {
1760 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.
getImm());
1773 unsigned LR = RegInfo->getRARegister();
1775 SavedRegs.
reset(LR);
1779 const bool isPPC64 = Subtarget.
isPPC64();
1814 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
1818 SavedRegs.
reset(PPC::R30);
1829 if (!isPPC64 && !IsDarwinABI &&
1830 (SavedRegs.
test(PPC::CR2) ||
1831 SavedRegs.
test(PPC::CR3) ||
1832 SavedRegs.
test(PPC::CR4))) {
1858 createTailCallBranchInstr(MBB);
1863 if (CSI.empty() && !
needsFP(MF)) {
1868 unsigned MinGPR = PPC::R31;
1869 unsigned MinG8R = PPC::X31;
1870 unsigned MinFPR = PPC::F31;
1871 unsigned MinVR = Subtarget.
hasSPE() ? PPC::S31 : PPC::V31;
1873 bool HasGPSaveArea =
false;
1874 bool HasG8SaveArea =
false;
1875 bool HasFPSaveArea =
false;
1876 bool HasVRSAVESaveArea =
false;
1877 bool HasVRSaveArea =
false;
1884 for (
unsigned i = 0,
e = CSI.size(); i !=
e; ++i) {
1885 unsigned Reg = CSI[i].getReg();
1887 (Reg != PPC::X2 && Reg !=
PPC::R2)) &&
1888 "Not expecting to try to spill R2 in a function that must save TOC");
1889 if (PPC::GPRCRegClass.
contains(Reg)) {
1890 HasGPSaveArea =
true;
1897 }
else if (PPC::G8RCRegClass.
contains(Reg)) {
1898 HasG8SaveArea =
true;
1905 }
else if (PPC::F8RCRegClass.
contains(Reg)) {
1906 HasFPSaveArea =
true;
1913 }
else if (PPC::CRBITRCRegClass.
contains(Reg) ||
1916 }
else if (PPC::VRSAVERCRegClass.
contains(Reg)) {
1917 HasVRSAVESaveArea =
true;
1918 }
else if (PPC::VRRCRegClass.
contains(Reg) ||
1919 PPC::SPERCRegClass.
contains(Reg)) {
1922 HasVRSaveArea =
true;
1937 int64_t LowerBound = 0;
1943 LowerBound = TCSPDelta;
1948 if (HasFPSaveArea) {
1949 for (
unsigned i = 0,
e = FPRegs.
size(); i !=
e; ++i) {
1950 int FI = FPRegs[i].getFrameIdx();
1955 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1962 assert(FI &&
"No Frame Pointer Save Slot!");
1965 HasGPSaveArea =
true;
1970 assert(FI &&
"No PIC Base Pointer Save Slot!");
1973 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
1974 HasGPSaveArea =
true;
1980 assert(FI &&
"No Base Pointer Save Slot!");
1984 if (PPC::G8RCRegClass.
contains(BP)) {
1985 MinG8R = std::min<unsigned>(MinG8R, BP);
1986 HasG8SaveArea =
true;
1987 }
else if (PPC::GPRCRegClass.
contains(BP)) {
1988 MinGPR = std::min<unsigned>(MinGPR, BP);
1989 HasGPSaveArea =
true;
1995 if (HasGPSaveArea || HasG8SaveArea) {
1998 for (
unsigned i = 0,
e = GPRegs.
size(); i !=
e; ++i) {
1999 if (!GPRegs[i].isSpilledToReg()) {
2000 int FI = GPRegs[i].getFrameIdx();
2007 for (
unsigned i = 0,
e = G8Regs.
size(); i !=
e; ++i) {
2008 if (!G8Regs[i].isSpilledToReg()) {
2009 int FI = G8Regs[i].getFrameIdx();
2015 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
2016 TRI->getEncodingValue(MinG8R));
2019 LowerBound -= (31 - MinReg + 1) * 8;
2021 LowerBound -= (31 - MinReg + 1) * 4;
2032 for (
unsigned i = 0,
e = CSI.size(); i !=
e; ++i) {
2033 unsigned Reg = CSI[i].getReg();
2035 if ((Subtarget.
isSVR4ABI() && Reg == PPC::CR2)
2038 (PPC::CRBITRCRegClass.contains(Reg) ||
2039 PPC::CRRCRegClass.contains(Reg)))) {
2040 int FI = CSI[i].getFrameIdx();
2049 if (HasVRSAVESaveArea) {
2053 for (
unsigned i = 0,
e = CSI.size(); i !=
e; ++i) {
2054 unsigned Reg = CSI[i].getReg();
2056 if (PPC::VRSAVERCRegClass.
contains(Reg)) {
2057 int FI = CSI[i].getFrameIdx();
2068 if (HasVRSaveArea) {
2074 assert(LowerBound <= 0 &&
"Expect LowerBound have a non-positive value!");
2075 LowerBound &= ~(15);
2077 for (
unsigned i = 0,
e = VRegs.
size(); i !=
e; ++i) {
2078 int FI = VRegs[i].getFrameIdx();
2133 std::vector<CalleeSavedInfo> &CSI)
const {
2148 for (
unsigned i = 0; CSRegs[i]; ++i)
2149 BVCalleeSaved.set(CSRegs[i]);
2154 if (BVCalleeSaved[
Reg] ||
2161 bool AllSpilledToReg =
true;
2162 for (
auto &CS : CSI) {
2163 if (BVAllocatable.
none())
2166 unsigned Reg = CS.getReg();
2167 if (!PPC::G8RCRegClass.
contains(Reg) && !PPC::GPRCRegClass.
contains(Reg)) {
2168 AllSpilledToReg =
false;
2172 unsigned VolatileVFReg = BVAllocatable.
find_first();
2173 if (VolatileVFReg < BVAllocatable.
size()) {
2174 CS.setDstReg(VolatileVFReg);
2175 BVAllocatable.
reset(VolatileVFReg);
2177 AllSpilledToReg =
false;
2180 return AllSpilledToReg;
2187 const std::vector<CalleeSavedInfo> &CSI,
2200 bool CRSpilled =
false;
2203 for (
unsigned i = 0,
e = CSI.size(); i !=
e; ++i) {
2204 unsigned Reg = CSI[i].getReg();
2208 if (Reg == PPC::VRSAVE && !Subtarget.
isDarwinABI())
2212 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
2224 if (CRSpilled && IsCRField) {
2230 if ((Reg == PPC::X2 || Reg ==
PPC::R2) && MustSaveTOC)
2245 CRMIB =
BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
2252 CSI[i].getFrameIdx()));
2255 if (CSI[i].isSpilledToReg()) {
2257 BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRD), CSI[i].getDstReg())
2265 CSI[i].getFrameIdx(), RC, TRI);
2274 bool CR2Spilled,
bool CR3Spilled,
bool CR4Spilled,
2276 const std::vector<CalleeSavedInfo> &CSI,
unsigned CSIIndex) {
2290 CSI[CSIIndex].getFrameIdx()));
2291 RestoreOp = PPC::MTOCRF;
2296 MBB.
insert(MI,
BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2300 MBB.
insert(MI,
BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2304 MBB.
insert(MI,
BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2313 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2315 if (
int CalleeAmt = I->getOperand(1).getImm()) {
2318 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2319 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2320 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2321 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2322 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2323 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2324 const DebugLoc &dl = I->getDebugLoc();
2327 BuildMI(MBB, I, dl, TII.
get(ADDIInstr), StackReg)
2332 BuildMI(MBB, MBBI, dl, TII.
get(LISInstr), TmpReg)
2333 .addImm(CalleeAmt >> 16);
2334 BuildMI(MBB, MBBI, dl, TII.
get(ORIInstr), TmpReg)
2336 .
addImm(CalleeAmt & 0xFFFF);
2337 BuildMI(MBB, MBBI, dl, TII.
get(ADDInstr), StackReg)
2344 return MBB.
erase(I);
2350 std::vector<CalleeSavedInfo> &CSI,
2362 bool CR2Spilled =
false;
2363 bool CR3Spilled =
false;
2364 bool CR4Spilled =
false;
2365 unsigned CSIIndex = 0;
2370 bool AtStart = I == MBB.
begin();
2375 for (
unsigned i = 0,
e = CSI.size(); i !=
e; ++i) {
2376 unsigned Reg = CSI[i].getReg();
2381 if (Reg == PPC::VRSAVE && !Subtarget.
isDarwinABI())
2384 if ((Reg == PPC::X2 || Reg ==
PPC::R2) && MustSaveTOC)
2387 if (Reg == PPC::CR2) {
2393 }
else if (Reg == PPC::CR3) {
2396 }
else if (Reg == PPC::CR4) {
2402 if ((CR2Spilled || CR3Spilled || CR4Spilled)
2403 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2406 CR2Spilled, CR3Spilled, CR4Spilled,
2407 MBB,
I, CSI, CSIIndex);
2408 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2411 if (CSI[i].isSpilledToReg()) {
2414 BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD),
Reg)
2421 "loadRegFromStackSlot didn't insert any code!");
2435 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2438 MBB,
I, CSI, CSIIndex);
2449 return TOCSaveOffset;
2455 return FramePointerSaveOffset;
2461 return BasePointerSaveOffset;
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isVRSAVESpilled() const
bool hasDebugInfo() const
Returns true if valid debug info is present.
int getFramePointerSaveIndex() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addMustSaveCR(unsigned Reg)
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void push_back(const T &Elt)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
unsigned determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool test(unsigned Idx) const
void setFramePointerSaveIndex(int Idx)
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
constexpr bool isInt< 16 >(int64_t x)
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
An instruction for reading from memory.
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned determineFrameLayoutAndUpdate(MachineFunction &MF, bool UseEstimate=false) const
Determine the frame layout and update the machine function.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
MachineBasicBlock * getRestorePoint() const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
def_iterator def_begin(unsigned RegNo) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool hasNonRISpills() const
const PPCTargetMachine & getTargetMachine() const
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool hasBasePointer(const MachineFunction &MF) const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Analysis containing CSE Info
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
int getBasePointerSaveIndex() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
int getTailCallSPDelta() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
void setBasePointerSaveIndex(int Idx)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
bool shrinkWrapDisabled() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
void setCRSpillFrameIndex(int idx)
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
const PPCRegisterInfo * getRegisterInfo() const override
Iterator for intrusive lists based on ilist_node.
constexpr bool isInt< 32 >(int64_t x)
size_type count() const
count - Returns the number of bits which are set.
Align max(MaybeAlign Lhs, Align Rhs)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const PPCInstrInfo * getInstrInfo() const override
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Information about stack frame layout on the target.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Register getBaseRegister(const MachineFunction &MF) const
static bool spillsVRSAVE(const MachineFunction &MF)
static bool hasSpills(const MachineFunction &MF)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
unsigned getMinReservedArea() const
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
static bool spillsCR(const MachineFunction &MF)
unsigned getRedZoneSize() const
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
unsigned getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only...
int getPICBasePointerSaveIndex() const
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
const MachineBasicBlock * getParent() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool none() const
none - Returns true if none of the bits are set.
void setPICBasePointerSaveIndex(int Idx)
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getCRSaveOffset() const
getCRSaveOffset - Return the previous frame offset to save the CR register.
LLVM_NODISCARD bool empty() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setMaxCallFrameSize(unsigned S)
bool needsFP(const MachineFunction &MF) const
static unsigned computeCRSaveOffset()
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
size_type size() const
size - Returns the number of bits in this bitvector.
bool isLRStoreRequired() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock * getSavePoint() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
const MCRegisterInfo * getRegisterInfo() const
iterator_range< const_set_bits_iterator > set_bits() const
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
Wrapper class representing virtual and physical registers.
void replaceFPWithRealFP(MachineFunction &MF) const
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.