LLVM  6.0.0svn
PPCFrameLowering.cpp
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1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
26 #include "llvm/IR/Function.h"
28 
29 using namespace llvm;
30 
31 /// VRRegNo - Map from a numbered VR register to its enum value.
32 ///
33 static const MCPhysReg VRRegNo[] = {
34  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 };
39 
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41  if (STI.isDarwinABI())
42  return STI.isPPC64() ? 16 : 8;
43  // SVR4 ABI:
44  return STI.isPPC64() ? 16 : 4;
45 }
46 
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48  return STI.isELFv2ABI() ? 24 : 40;
49 }
50 
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52  // For the Darwin ABI:
53  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54  // for saving the frame pointer (if needed.) While the published ABI has
55  // not used this slot since at least MacOSX 10.2, there is older code
56  // around that does use it, and that needs to continue to work.
57  if (STI.isDarwinABI())
58  return STI.isPPC64() ? -8U : -4U;
59 
60  // SVR4 ABI: First slot in the general register save area.
61  return STI.isPPC64() ? -8U : -4U;
62 }
63 
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65  if (STI.isDarwinABI() || STI.isPPC64())
66  return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
67 
68  // SVR4 ABI:
69  return 8;
70 }
71 
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73  if (STI.isDarwinABI())
74  return STI.isPPC64() ? -16U : -8U;
75 
76  // SVR4 ABI: First slot in the general register save area.
77  return STI.isPPC64()
78  ? -16U
79  : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
80 }
81 
83  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
84  STI.getPlatformStackAlignment(), 0),
85  Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
86  TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
87  FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
88  LinkageSize(computeLinkageSize(Subtarget)),
89  BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
90 
91 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
93  unsigned &NumEntries) const {
94  if (Subtarget.isDarwinABI()) {
95  NumEntries = 1;
96  if (Subtarget.isPPC64()) {
97  static const SpillSlot darwin64Offsets = {PPC::X31, -8};
98  return &darwin64Offsets;
99  } else {
100  static const SpillSlot darwinOffsets = {PPC::R31, -4};
101  return &darwinOffsets;
102  }
103  }
104 
105  // Early exit if not using the SVR4 ABI.
106  if (!Subtarget.isSVR4ABI()) {
107  NumEntries = 0;
108  return nullptr;
109  }
110 
111  // Note that the offsets here overlap, but this is fixed up in
112  // processFunctionBeforeFrameFinalized.
113 
114  static const SpillSlot Offsets[] = {
115  // Floating-point register save area offsets.
116  {PPC::F31, -8},
117  {PPC::F30, -16},
118  {PPC::F29, -24},
119  {PPC::F28, -32},
120  {PPC::F27, -40},
121  {PPC::F26, -48},
122  {PPC::F25, -56},
123  {PPC::F24, -64},
124  {PPC::F23, -72},
125  {PPC::F22, -80},
126  {PPC::F21, -88},
127  {PPC::F20, -96},
128  {PPC::F19, -104},
129  {PPC::F18, -112},
130  {PPC::F17, -120},
131  {PPC::F16, -128},
132  {PPC::F15, -136},
133  {PPC::F14, -144},
134 
135  // General register save area offsets.
136  {PPC::R31, -4},
137  {PPC::R30, -8},
138  {PPC::R29, -12},
139  {PPC::R28, -16},
140  {PPC::R27, -20},
141  {PPC::R26, -24},
142  {PPC::R25, -28},
143  {PPC::R24, -32},
144  {PPC::R23, -36},
145  {PPC::R22, -40},
146  {PPC::R21, -44},
147  {PPC::R20, -48},
148  {PPC::R19, -52},
149  {PPC::R18, -56},
150  {PPC::R17, -60},
151  {PPC::R16, -64},
152  {PPC::R15, -68},
153  {PPC::R14, -72},
154 
155  // CR save area offset. We map each of the nonvolatile CR fields
156  // to the slot for CR2, which is the first of the nonvolatile CR
157  // fields to be assigned, so that we only allocate one save slot.
158  // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
159  {PPC::CR2, -4},
160 
161  // VRSAVE save area offset.
162  {PPC::VRSAVE, -4},
163 
164  // Vector register save area
165  {PPC::V31, -16},
166  {PPC::V30, -32},
167  {PPC::V29, -48},
168  {PPC::V28, -64},
169  {PPC::V27, -80},
170  {PPC::V26, -96},
171  {PPC::V25, -112},
172  {PPC::V24, -128},
173  {PPC::V23, -144},
174  {PPC::V22, -160},
175  {PPC::V21, -176},
176  {PPC::V20, -192}};
177 
178  static const SpillSlot Offsets64[] = {
179  // Floating-point register save area offsets.
180  {PPC::F31, -8},
181  {PPC::F30, -16},
182  {PPC::F29, -24},
183  {PPC::F28, -32},
184  {PPC::F27, -40},
185  {PPC::F26, -48},
186  {PPC::F25, -56},
187  {PPC::F24, -64},
188  {PPC::F23, -72},
189  {PPC::F22, -80},
190  {PPC::F21, -88},
191  {PPC::F20, -96},
192  {PPC::F19, -104},
193  {PPC::F18, -112},
194  {PPC::F17, -120},
195  {PPC::F16, -128},
196  {PPC::F15, -136},
197  {PPC::F14, -144},
198 
199  // General register save area offsets.
200  {PPC::X31, -8},
201  {PPC::X30, -16},
202  {PPC::X29, -24},
203  {PPC::X28, -32},
204  {PPC::X27, -40},
205  {PPC::X26, -48},
206  {PPC::X25, -56},
207  {PPC::X24, -64},
208  {PPC::X23, -72},
209  {PPC::X22, -80},
210  {PPC::X21, -88},
211  {PPC::X20, -96},
212  {PPC::X19, -104},
213  {PPC::X18, -112},
214  {PPC::X17, -120},
215  {PPC::X16, -128},
216  {PPC::X15, -136},
217  {PPC::X14, -144},
218 
219  // VRSAVE save area offset.
220  {PPC::VRSAVE, -4},
221 
222  // Vector register save area
223  {PPC::V31, -16},
224  {PPC::V30, -32},
225  {PPC::V29, -48},
226  {PPC::V28, -64},
227  {PPC::V27, -80},
228  {PPC::V26, -96},
229  {PPC::V25, -112},
230  {PPC::V24, -128},
231  {PPC::V23, -144},
232  {PPC::V22, -160},
233  {PPC::V21, -176},
234  {PPC::V20, -192}};
235 
236  if (Subtarget.isPPC64()) {
237  NumEntries = array_lengthof(Offsets64);
238 
239  return Offsets64;
240  } else {
241  NumEntries = array_lengthof(Offsets);
242 
243  return Offsets;
244  }
245 }
246 
247 /// RemoveVRSaveCode - We have found that this function does not need any code
248 /// to manipulate the VRSAVE register, even though it uses vector registers.
249 /// This can happen when the only registers used are known to be live in or out
250 /// of the function. Remove all of the VRSAVE related code from the function.
251 /// FIXME: The removal of the code results in a compile failure at -O0 when the
252 /// function contains a function call, as the GPR containing original VRSAVE
253 /// contents is spilled and reloaded around the call. Without the prolog code,
254 /// the spill instruction refers to an undefined register. This code needs
255 /// to account for all uses of that GPR.
257  MachineBasicBlock *Entry = MI.getParent();
258  MachineFunction *MF = Entry->getParent();
259 
260  // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
262  ++MBBI;
263  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
264  MBBI->eraseFromParent();
265 
266  bool RemovedAllMTVRSAVEs = true;
267  // See if we can find and remove the MTVRSAVE instruction from all of the
268  // epilog blocks.
269  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
270  // If last instruction is a return instruction, add an epilogue
271  if (I->isReturnBlock()) {
272  bool FoundIt = false;
273  for (MBBI = I->end(); MBBI != I->begin(); ) {
274  --MBBI;
275  if (MBBI->getOpcode() == PPC::MTVRSAVE) {
276  MBBI->eraseFromParent(); // remove it.
277  FoundIt = true;
278  break;
279  }
280  }
281  RemovedAllMTVRSAVEs &= FoundIt;
282  }
283  }
284 
285  // If we found and removed all MTVRSAVE instructions, remove the read of
286  // VRSAVE as well.
287  if (RemovedAllMTVRSAVEs) {
288  MBBI = MI;
289  assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
290  --MBBI;
291  assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
292  MBBI->eraseFromParent();
293  }
294 
295  // Finally, nuke the UPDATE_VRSAVE.
296  MI.eraseFromParent();
297 }
298 
299 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
300 // instruction selector. Based on the vector registers that have been used,
301 // transform this into the appropriate ORI instruction.
303  MachineFunction *MF = MI.getParent()->getParent();
304  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
305  DebugLoc dl = MI.getDebugLoc();
306 
307  const MachineRegisterInfo &MRI = MF->getRegInfo();
308  unsigned UsedRegMask = 0;
309  for (unsigned i = 0; i != 32; ++i)
310  if (MRI.isPhysRegModified(VRRegNo[i]))
311  UsedRegMask |= 1 << (31-i);
312 
313  // Live in and live out values already must be in the mask, so don't bother
314  // marking them.
316  I = MF->getRegInfo().livein_begin(),
317  E = MF->getRegInfo().livein_end(); I != E; ++I) {
318  unsigned RegNo = TRI->getEncodingValue(I->first);
319  if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
320  UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
321  }
322 
323  // Live out registers appear as use operands on return instructions.
324  for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
325  UsedRegMask != 0 && BI != BE; ++BI) {
326  const MachineBasicBlock &MBB = *BI;
327  if (!MBB.isReturnBlock())
328  continue;
329  const MachineInstr &Ret = MBB.back();
330  for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
331  const MachineOperand &MO = Ret.getOperand(I);
332  if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
333  continue;
334  unsigned RegNo = TRI->getEncodingValue(MO.getReg());
335  UsedRegMask &= ~(1 << (31-RegNo));
336  }
337  }
338 
339  // If no registers are used, turn this into a copy.
340  if (UsedRegMask == 0) {
341  // Remove all VRSAVE code.
342  RemoveVRSaveCode(MI);
343  return;
344  }
345 
346  unsigned SrcReg = MI.getOperand(1).getReg();
347  unsigned DstReg = MI.getOperand(0).getReg();
348 
349  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
350  if (DstReg != SrcReg)
351  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
352  .addReg(SrcReg)
353  .addImm(UsedRegMask);
354  else
355  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
356  .addReg(SrcReg, RegState::Kill)
357  .addImm(UsedRegMask);
358  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
359  if (DstReg != SrcReg)
360  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
361  .addReg(SrcReg)
362  .addImm(UsedRegMask >> 16);
363  else
364  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
365  .addReg(SrcReg, RegState::Kill)
366  .addImm(UsedRegMask >> 16);
367  } else {
368  if (DstReg != SrcReg)
369  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
370  .addReg(SrcReg)
371  .addImm(UsedRegMask >> 16);
372  else
373  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
374  .addReg(SrcReg, RegState::Kill)
375  .addImm(UsedRegMask >> 16);
376 
377  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
378  .addReg(DstReg, RegState::Kill)
379  .addImm(UsedRegMask & 0xFFFF);
380  }
381 
382  // Remove the old UPDATE_VRSAVE instruction.
383  MI.eraseFromParent();
384 }
385 
386 static bool spillsCR(const MachineFunction &MF) {
387  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
388  return FuncInfo->isCRSpilled();
389 }
390 
391 static bool spillsVRSAVE(const MachineFunction &MF) {
392  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
393  return FuncInfo->isVRSAVESpilled();
394 }
395 
396 static bool hasSpills(const MachineFunction &MF) {
397  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
398  return FuncInfo->hasSpills();
399 }
400 
401 static bool hasNonRISpills(const MachineFunction &MF) {
402  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
403  return FuncInfo->hasNonRISpills();
404 }
405 
406 /// MustSaveLR - Return true if this function requires that we save the LR
407 /// register onto the stack in the prolog and restore it in the epilog of the
408 /// function.
409 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
410  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
411 
412  // We need a save/restore of LR if there is any def of LR (which is
413  // defined by calls, including the PIC setup sequence), or if there is
414  // some use of the LR stack slot (e.g. for builtin_return_address).
415  // (LR comes in 32 and 64 bit versions.)
417  return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
418 }
419 
420 /// determineFrameLayout - Determine the size of the frame and maximum call
421 /// frame size.
423  bool UpdateMF,
424  bool UseEstimate) const {
425  MachineFrameInfo &MFI = MF.getFrameInfo();
426 
427  // Get the number of bytes to allocate from the FrameInfo
428  unsigned FrameSize =
429  UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
430 
431  // Get stack alignments. The frame must be aligned to the greatest of these:
432  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
433  unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
434  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
435 
436  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
437 
438  unsigned LR = RegInfo->getRARegister();
439  bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
440  bool CanUseRedZone = !MFI.hasVarSizedObjects() && // No dynamic alloca.
441  !MFI.adjustsStack() && // No calls.
442  !MustSaveLR(MF, LR) && // No need to save LR.
443  !RegInfo->hasBasePointer(MF); // No special alignment.
444 
445  // Note: for PPC32 SVR4ABI (Non-DarwinABI), we can still generate stackless
446  // code if all local vars are reg-allocated.
447  bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize();
448 
449  // Check whether we can skip adjusting the stack pointer (by using red zone)
450  if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
451  // No need for frame
452  if (UpdateMF)
453  MFI.setStackSize(0);
454  return 0;
455  }
456 
457  // Get the maximum call frame size of all the calls.
458  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
459 
460  // Maximum call frame needs to be at least big enough for linkage area.
461  unsigned minCallFrameSize = getLinkageSize();
462  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
463 
464  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
465  // that allocations will be aligned.
466  if (MFI.hasVarSizedObjects())
467  maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
468 
469  // Update maximum call frame size.
470  if (UpdateMF)
471  MFI.setMaxCallFrameSize(maxCallFrameSize);
472 
473  // Include call frame size in total.
474  FrameSize += maxCallFrameSize;
475 
476  // Make sure the frame is aligned.
477  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
478 
479  // Update frame info.
480  if (UpdateMF)
481  MFI.setStackSize(FrameSize);
482 
483  return FrameSize;
484 }
485 
486 // hasFP - Return true if the specified function actually has a dedicated frame
487 // pointer register.
489  const MachineFrameInfo &MFI = MF.getFrameInfo();
490  // FIXME: This is pretty much broken by design: hasFP() might be called really
491  // early, before the stack layout was calculated and thus hasFP() might return
492  // true or false here depending on the time of call.
493  return (MFI.getStackSize()) && needsFP(MF);
494 }
495 
496 // needsFP - Return true if the specified function should have a dedicated frame
497 // pointer register. This is true if the function has variable sized allocas or
498 // if frame pointer elimination is disabled.
500  const MachineFrameInfo &MFI = MF.getFrameInfo();
501 
502  // Naked functions have no stack frame pushed, so we don't have a frame
503  // pointer.
504  if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
505  return false;
506 
507  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
508  MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint() ||
510  MF.getInfo<PPCFunctionInfo>()->hasFastCall());
511 }
512 
514  bool is31 = needsFP(MF);
515  unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
516  unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
517 
518  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
519  bool HasBP = RegInfo->hasBasePointer(MF);
520  unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
521  unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
522 
523  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
524  BI != BE; ++BI)
525  for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
526  --MBBI;
527  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
528  MachineOperand &MO = MBBI->getOperand(I);
529  if (!MO.isReg())
530  continue;
531 
532  switch (MO.getReg()) {
533  case PPC::FP:
534  MO.setReg(FPReg);
535  break;
536  case PPC::FP8:
537  MO.setReg(FP8Reg);
538  break;
539  case PPC::BP:
540  MO.setReg(BPReg);
541  break;
542  case PPC::BP8:
543  MO.setReg(BP8Reg);
544  break;
545 
546  }
547  }
548  }
549 }
550 
551 /* This function will do the following:
552  - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
553  respectively (defaults recommended by the ABI) and return true
554  - If MBB is not an entry block, initialize the register scavenger and look
555  for available registers.
556  - If the defaults (R0/R12) are available, return true
557  - If TwoUniqueRegsRequired is set to true, it looks for two unique
558  registers. Otherwise, look for a single available register.
559  - If the required registers are found, set SR1 and SR2 and return true.
560  - If the required registers are not found, set SR2 or both SR1 and SR2 to
561  PPC::NoRegister and return false.
562 
563  Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
564  is not set, this function will attempt to find two different registers, but
565  still return true if only one register is available (and set SR1 == SR2).
566 */
567 bool
568 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
569  bool UseAtEnd,
570  bool TwoUniqueRegsRequired,
571  unsigned *SR1,
572  unsigned *SR2) const {
573  RegScavenger RS;
574  unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
575  unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
576 
577  // Set the defaults for the two scratch registers.
578  if (SR1)
579  *SR1 = R0;
580 
581  if (SR2) {
582  assert (SR1 && "Asking for the second scratch register but not the first?");
583  *SR2 = R12;
584  }
585 
586  // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
587  if ((UseAtEnd && MBB->isReturnBlock()) ||
588  (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
589  return true;
590 
591  RS.enterBasicBlock(*MBB);
592 
593  if (UseAtEnd && !MBB->empty()) {
594  // The scratch register will be used at the end of the block, so must
595  // consider all registers used within the block
596 
598  // If no terminator, back iterator up to previous instruction.
599  if (MBBI == MBB->end())
600  MBBI = std::prev(MBBI);
601 
602  if (MBBI != MBB->begin())
603  RS.forward(MBBI);
604  }
605 
606  // If the two registers are available, we're all good.
607  // Note that we only return here if both R0 and R12 are available because
608  // although the function may not require two unique registers, it may benefit
609  // from having two so we should try to provide them.
610  if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
611  return true;
612 
613  // Get the list of callee-saved registers for the target.
614  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
615  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
616 
617  // Get all the available registers in the block.
618  BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
619  &PPC::GPRCRegClass);
620 
621  // We shouldn't use callee-saved registers as scratch registers as they may be
622  // available when looking for a candidate block for shrink wrapping but not
623  // available when the actual prologue/epilogue is being emitted because they
624  // were added as live-in to the prologue block by PrologueEpilogueInserter.
625  for (int i = 0; CSRegs[i]; ++i)
626  BV.reset(CSRegs[i]);
627 
628  // Set the first scratch register to the first available one.
629  if (SR1) {
630  int FirstScratchReg = BV.find_first();
631  *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
632  }
633 
634  // If there is another one available, set the second scratch register to that.
635  // Otherwise, set it to either PPC::NoRegister if this function requires two
636  // or to whatever SR1 is set to if this function doesn't require two.
637  if (SR2) {
638  int SecondScratchReg = BV.find_next(*SR1);
639  if (SecondScratchReg != -1)
640  *SR2 = SecondScratchReg;
641  else
642  *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
643  }
644 
645  // Now that we've done our best to provide both registers, double check
646  // whether we were unable to provide enough.
647  if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U))
648  return false;
649 
650  return true;
651 }
652 
653 // We need a scratch register for spilling LR and for spilling CR. By default,
654 // we use two scratch registers to hide latency. However, if only one scratch
655 // register is available, we can adjust for that by not overlapping the spill
656 // code. However, if we need to realign the stack (i.e. have a base pointer)
657 // and the stack frame is large, we need two scratch registers.
658 bool
659 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
660  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
661  MachineFunction &MF = *(MBB->getParent());
662  bool HasBP = RegInfo->hasBasePointer(MF);
663  unsigned FrameSize = determineFrameLayout(MF, false);
664  int NegFrameSize = -FrameSize;
665  bool IsLargeFrame = !isInt<16>(NegFrameSize);
666  MachineFrameInfo &MFI = MF.getFrameInfo();
667  unsigned MaxAlign = MFI.getMaxAlignment();
668  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
669 
670  return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
671 }
672 
674  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
675 
676  return findScratchRegister(TmpMBB, false,
677  twoUniqueScratchRegsRequired(TmpMBB));
678 }
679 
681  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
682 
683  return findScratchRegister(TmpMBB, true);
684 }
685 
687  MachineBasicBlock &MBB) const {
688  MachineBasicBlock::iterator MBBI = MBB.begin();
689  MachineFrameInfo &MFI = MF.getFrameInfo();
690  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
691  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
692 
693  MachineModuleInfo &MMI = MF.getMMI();
694  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
695  DebugLoc dl;
696  bool needsCFI = MMI.hasDebugInfo() ||
698 
699  // Get processor type.
700  bool isPPC64 = Subtarget.isPPC64();
701  // Get the ABI.
702  bool isSVR4ABI = Subtarget.isSVR4ABI();
703  bool isELFv2ABI = Subtarget.isELFv2ABI();
704  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
705  "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
706 
707  // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
708  // process it.
709  if (!isSVR4ABI)
710  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
711  if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
712  HandleVRSaveUpdate(*MBBI, TII);
713  break;
714  }
715  }
716 
717  // Move MBBI back to the beginning of the prologue block.
718  MBBI = MBB.begin();
719 
720  // Work out frame sizes.
721  unsigned FrameSize = determineFrameLayout(MF);
722  int NegFrameSize = -FrameSize;
723  if (!isInt<32>(NegFrameSize))
724  llvm_unreachable("Unhandled stack size!");
725 
726  if (MFI.isFrameAddressTaken())
728 
729  // Check if the link register (LR) must be saved.
731  bool MustSaveLR = FI->mustSaveLR();
732  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
733  bool MustSaveCR = !MustSaveCRs.empty();
734  // Do we have a frame pointer and/or base pointer for this function?
735  bool HasFP = hasFP(MF);
736  bool HasBP = RegInfo->hasBasePointer(MF);
737  bool HasRedZone = isPPC64 || !isSVR4ABI;
738 
739  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
740  unsigned BPReg = RegInfo->getBaseRegister(MF);
741  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
742  unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
743  unsigned ScratchReg = 0;
744  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
745  // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
746  const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
747  : PPC::MFLR );
748  const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
749  : PPC::STW );
750  const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
751  : PPC::STWU );
752  const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
753  : PPC::STWUX);
754  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
755  : PPC::LIS );
756  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
757  : PPC::ORI );
758  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
759  : PPC::OR );
760  const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
761  : PPC::SUBFC);
762  const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
763  : PPC::SUBFIC);
764 
765  // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
766  // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
767  // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
768  // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
769  assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
770  "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
771 
772  // Using the same bool variable as below to suppress compiler warnings.
773  bool SingleScratchReg =
774  findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
775  &ScratchReg, &TempReg);
776  assert(SingleScratchReg &&
777  "Required number of registers not available in this block");
778 
779  SingleScratchReg = ScratchReg == TempReg;
780 
781  int LROffset = getReturnSaveOffset();
782 
783  int FPOffset = 0;
784  if (HasFP) {
785  if (isSVR4ABI) {
786  MachineFrameInfo &MFI = MF.getFrameInfo();
787  int FPIndex = FI->getFramePointerSaveIndex();
788  assert(FPIndex && "No Frame Pointer Save Slot!");
789  FPOffset = MFI.getObjectOffset(FPIndex);
790  } else {
791  FPOffset = getFramePointerSaveOffset();
792  }
793  }
794 
795  int BPOffset = 0;
796  if (HasBP) {
797  if (isSVR4ABI) {
798  MachineFrameInfo &MFI = MF.getFrameInfo();
799  int BPIndex = FI->getBasePointerSaveIndex();
800  assert(BPIndex && "No Base Pointer Save Slot!");
801  BPOffset = MFI.getObjectOffset(BPIndex);
802  } else {
803  BPOffset = getBasePointerSaveOffset();
804  }
805  }
806 
807  int PBPOffset = 0;
808  if (FI->usesPICBase()) {
809  MachineFrameInfo &MFI = MF.getFrameInfo();
810  int PBPIndex = FI->getPICBasePointerSaveIndex();
811  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
812  PBPOffset = MFI.getObjectOffset(PBPIndex);
813  }
814 
815  // Get stack alignments.
816  unsigned MaxAlign = MFI.getMaxAlignment();
817  if (HasBP && MaxAlign > 1)
818  assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
819  "Invalid alignment!");
820 
821  // Frames of 32KB & larger require special handling because they cannot be
822  // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
823  bool isLargeFrame = !isInt<16>(NegFrameSize);
824 
825  assert((isPPC64 || !MustSaveCR) &&
826  "Prologue CR saving supported only in 64-bit mode");
827 
828  // If we need to spill the CR and the LR but we don't have two separate
829  // registers available, we must spill them one at a time
830  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
831  // In the ELFv2 ABI, we are not required to save all CR fields.
832  // If only one or two CR fields are clobbered, it is more efficient to use
833  // mfocrf to selectively save just those fields, because mfocrf has short
834  // latency compares to mfcr.
835  unsigned MfcrOpcode = PPC::MFCR8;
836  unsigned CrState = RegState::ImplicitKill;
837  if (isELFv2ABI && MustSaveCRs.size() == 1) {
838  MfcrOpcode = PPC::MFOCRF8;
839  CrState = RegState::Kill;
840  }
841  MachineInstrBuilder MIB =
842  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
843  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
844  MIB.addReg(MustSaveCRs[i], CrState);
845  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
846  .addReg(TempReg, getKillRegState(true))
847  .addImm(8)
848  .addReg(SPReg);
849  }
850 
851  if (MustSaveLR)
852  BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
853 
854  if (MustSaveCR &&
855  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
856  // In the ELFv2 ABI, we are not required to save all CR fields.
857  // If only one or two CR fields are clobbered, it is more efficient to use
858  // mfocrf to selectively save just those fields, because mfocrf has short
859  // latency compares to mfcr.
860  unsigned MfcrOpcode = PPC::MFCR8;
861  unsigned CrState = RegState::ImplicitKill;
862  if (isELFv2ABI && MustSaveCRs.size() == 1) {
863  MfcrOpcode = PPC::MFOCRF8;
864  CrState = RegState::Kill;
865  }
866  MachineInstrBuilder MIB =
867  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
868  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
869  MIB.addReg(MustSaveCRs[i], CrState);
870  }
871 
872  if (HasRedZone) {
873  if (HasFP)
874  BuildMI(MBB, MBBI, dl, StoreInst)
875  .addReg(FPReg)
876  .addImm(FPOffset)
877  .addReg(SPReg);
878  if (FI->usesPICBase())
879  BuildMI(MBB, MBBI, dl, StoreInst)
880  .addReg(PPC::R30)
881  .addImm(PBPOffset)
882  .addReg(SPReg);
883  if (HasBP)
884  BuildMI(MBB, MBBI, dl, StoreInst)
885  .addReg(BPReg)
886  .addImm(BPOffset)
887  .addReg(SPReg);
888  }
889 
890  if (MustSaveLR)
891  BuildMI(MBB, MBBI, dl, StoreInst)
892  .addReg(ScratchReg, getKillRegState(true))
893  .addImm(LROffset)
894  .addReg(SPReg);
895 
896  if (MustSaveCR &&
897  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
898  assert(HasRedZone && "A red zone is always available on PPC64");
899  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
900  .addReg(TempReg, getKillRegState(true))
901  .addImm(8)
902  .addReg(SPReg);
903  }
904 
905  // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
906  if (!FrameSize)
907  return;
908 
909  // Adjust stack pointer: r1 += NegFrameSize.
910  // If there is a preferred stack alignment, align R1 now
911 
912  if (HasBP && HasRedZone) {
913  // Save a copy of r1 as the base pointer.
914  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
915  .addReg(SPReg)
916  .addReg(SPReg);
917  }
918 
919  // Have we generated a STUX instruction to claim stack frame? If so,
920  // the negated frame size will be placed in ScratchReg.
921  bool HasSTUX = false;
922 
923  // This condition must be kept in sync with canUseAsPrologue.
924  if (HasBP && MaxAlign > 1) {
925  if (isPPC64)
926  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
927  .addReg(SPReg)
928  .addImm(0)
929  .addImm(64 - Log2_32(MaxAlign));
930  else // PPC32...
931  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
932  .addReg(SPReg)
933  .addImm(0)
934  .addImm(32 - Log2_32(MaxAlign))
935  .addImm(31);
936  if (!isLargeFrame) {
937  BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
938  .addReg(ScratchReg, RegState::Kill)
939  .addImm(NegFrameSize);
940  } else {
941  assert(!SingleScratchReg && "Only a single scratch reg available");
942  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
943  .addImm(NegFrameSize >> 16);
944  BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
945  .addReg(TempReg, RegState::Kill)
946  .addImm(NegFrameSize & 0xFFFF);
947  BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
948  .addReg(ScratchReg, RegState::Kill)
949  .addReg(TempReg, RegState::Kill);
950  }
951 
952  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
953  .addReg(SPReg, RegState::Kill)
954  .addReg(SPReg)
955  .addReg(ScratchReg);
956  HasSTUX = true;
957 
958  } else if (!isLargeFrame) {
959  BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
960  .addReg(SPReg)
961  .addImm(NegFrameSize)
962  .addReg(SPReg);
963 
964  } else {
965  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
966  .addImm(NegFrameSize >> 16);
967  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
968  .addReg(ScratchReg, RegState::Kill)
969  .addImm(NegFrameSize & 0xFFFF);
970  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
971  .addReg(SPReg, RegState::Kill)
972  .addReg(SPReg)
973  .addReg(ScratchReg);
974  HasSTUX = true;
975  }
976 
977  if (!HasRedZone) {
978  assert(!isPPC64 && "A red zone is always available on PPC64");
979  if (HasSTUX) {
980  // The negated frame size is in ScratchReg, and the SPReg has been
981  // decremented by the frame size: SPReg = old SPReg + ScratchReg.
982  // Since FPOffset, PBPOffset, etc. are relative to the beginning of
983  // the stack frame (i.e. the old SP), ideally, we would put the old
984  // SP into a register and use it as the base for the stores. The
985  // problem is that the only available register may be ScratchReg,
986  // which could be R0, and R0 cannot be used as a base address.
987 
988  // First, set ScratchReg to the old SP. This may need to be modified
989  // later.
990  BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
991  .addReg(ScratchReg, RegState::Kill)
992  .addReg(SPReg);
993 
994  if (ScratchReg == PPC::R0) {
995  // R0 cannot be used as a base register, but it can be used as an
996  // index in a store-indexed.
997  int LastOffset = 0;
998  if (HasFP) {
999  // R0 += (FPOffset-LastOffset).
1000  // Need addic, since addi treats R0 as 0.
1001  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1002  .addReg(ScratchReg)
1003  .addImm(FPOffset-LastOffset);
1004  LastOffset = FPOffset;
1005  // Store FP into *R0.
1006  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1007  .addReg(FPReg, RegState::Kill) // Save FP.
1008  .addReg(PPC::ZERO)
1009  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1010  }
1011  if (FI->usesPICBase()) {
1012  // R0 += (PBPOffset-LastOffset).
1013  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1014  .addReg(ScratchReg)
1015  .addImm(PBPOffset-LastOffset);
1016  LastOffset = PBPOffset;
1017  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1018  .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1019  .addReg(PPC::ZERO)
1020  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1021  }
1022  if (HasBP) {
1023  // R0 += (BPOffset-LastOffset).
1024  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1025  .addReg(ScratchReg)
1026  .addImm(BPOffset-LastOffset);
1027  LastOffset = BPOffset;
1028  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1029  .addReg(BPReg, RegState::Kill) // Save BP.
1030  .addReg(PPC::ZERO)
1031  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1032  // BP = R0-LastOffset
1033  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1034  .addReg(ScratchReg, RegState::Kill)
1035  .addImm(-LastOffset);
1036  }
1037  } else {
1038  // ScratchReg is not R0, so use it as the base register. It is
1039  // already set to the old SP, so we can use the offsets directly.
1040 
1041  // Now that the stack frame has been allocated, save all the necessary
1042  // registers using ScratchReg as the base address.
1043  if (HasFP)
1044  BuildMI(MBB, MBBI, dl, StoreInst)
1045  .addReg(FPReg)
1046  .addImm(FPOffset)
1047  .addReg(ScratchReg);
1048  if (FI->usesPICBase())
1049  BuildMI(MBB, MBBI, dl, StoreInst)
1050  .addReg(PPC::R30)
1051  .addImm(PBPOffset)
1052  .addReg(ScratchReg);
1053  if (HasBP) {
1054  BuildMI(MBB, MBBI, dl, StoreInst)
1055  .addReg(BPReg)
1056  .addImm(BPOffset)
1057  .addReg(ScratchReg);
1058  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1059  .addReg(ScratchReg, RegState::Kill)
1060  .addReg(ScratchReg);
1061  }
1062  }
1063  } else {
1064  // The frame size is a known 16-bit constant (fitting in the immediate
1065  // field of STWU). To be here we have to be compiling for PPC32.
1066  // Since the SPReg has been decreased by FrameSize, add it back to each
1067  // offset.
1068  if (HasFP)
1069  BuildMI(MBB, MBBI, dl, StoreInst)
1070  .addReg(FPReg)
1071  .addImm(FrameSize + FPOffset)
1072  .addReg(SPReg);
1073  if (FI->usesPICBase())
1074  BuildMI(MBB, MBBI, dl, StoreInst)
1075  .addReg(PPC::R30)
1076  .addImm(FrameSize + PBPOffset)
1077  .addReg(SPReg);
1078  if (HasBP) {
1079  BuildMI(MBB, MBBI, dl, StoreInst)
1080  .addReg(BPReg)
1081  .addImm(FrameSize + BPOffset)
1082  .addReg(SPReg);
1083  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1084  .addReg(SPReg)
1085  .addImm(FrameSize);
1086  }
1087  }
1088  }
1089 
1090  // Add Call Frame Information for the instructions we generated above.
1091  if (needsCFI) {
1092  unsigned CFIIndex;
1093 
1094  if (HasBP) {
1095  // Define CFA in terms of BP. Do this in preference to using FP/SP,
1096  // because if the stack needed aligning then CFA won't be at a fixed
1097  // offset from FP/SP.
1098  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1099  CFIIndex = MF.addFrameInst(
1101  } else {
1102  // Adjust the definition of CFA to account for the change in SP.
1103  assert(NegFrameSize);
1104  CFIIndex = MF.addFrameInst(
1105  MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
1106  }
1107  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1108  .addCFIIndex(CFIIndex);
1109 
1110  if (HasFP) {
1111  // Describe where FP was saved, at a fixed offset from CFA.
1112  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1113  CFIIndex = MF.addFrameInst(
1114  MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
1115  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1116  .addCFIIndex(CFIIndex);
1117  }
1118 
1119  if (FI->usesPICBase()) {
1120  // Describe where FP was saved, at a fixed offset from CFA.
1121  unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
1122  CFIIndex = MF.addFrameInst(
1123  MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
1124  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1125  .addCFIIndex(CFIIndex);
1126  }
1127 
1128  if (HasBP) {
1129  // Describe where BP was saved, at a fixed offset from CFA.
1130  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1131  CFIIndex = MF.addFrameInst(
1132  MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
1133  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1134  .addCFIIndex(CFIIndex);
1135  }
1136 
1137  if (MustSaveLR) {
1138  // Describe where LR was saved, at a fixed offset from CFA.
1139  unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1140  CFIIndex = MF.addFrameInst(
1141  MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
1142  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1143  .addCFIIndex(CFIIndex);
1144  }
1145  }
1146 
1147  // If there is a frame pointer, copy R1 into R31
1148  if (HasFP) {
1149  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1150  .addReg(SPReg)
1151  .addReg(SPReg);
1152 
1153  if (!HasBP && needsCFI) {
1154  // Change the definition of CFA from SP+offset to FP+offset, because SP
1155  // will change at every alloca.
1156  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1157  unsigned CFIIndex = MF.addFrameInst(
1159 
1160  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1161  .addCFIIndex(CFIIndex);
1162  }
1163  }
1164 
1165  if (needsCFI) {
1166  // Describe where callee saved registers were saved, at fixed offsets from
1167  // CFA.
1168  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1169  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1170  unsigned Reg = CSI[I].getReg();
1171  if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1172 
1173  // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
1174  // subregisters of CR2. We just need to emit a move of CR2.
1175  if (PPC::CRBITRCRegClass.contains(Reg))
1176  continue;
1177 
1178  // For SVR4, don't emit a move for the CR spill slot if we haven't
1179  // spilled CRs.
1180  if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1181  && !MustSaveCR)
1182  continue;
1183 
1184  // For 64-bit SVR4 when we have spilled CRs, the spill location
1185  // is SP+8, not a frame-relative slot.
1186  if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1187  // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1188  // the whole CR word. In the ELFv2 ABI, every CR that was
1189  // actually saved gets its own CFI record.
1190  unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1191  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1192  nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
1193  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1194  .addCFIIndex(CFIIndex);
1195  continue;
1196  }
1197 
1198  int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());
1199  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1200  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
1201  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1202  .addCFIIndex(CFIIndex);
1203  }
1204  }
1205 }
1206 
1208  MachineBasicBlock &MBB) const {
1210  DebugLoc dl;
1211 
1212  if (MBBI != MBB.end())
1213  dl = MBBI->getDebugLoc();
1214 
1215  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1216  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1217 
1218  // Get alignment info so we know how to restore the SP.
1219  const MachineFrameInfo &MFI = MF.getFrameInfo();
1220 
1221  // Get the number of bytes allocated from the FrameInfo.
1222  int FrameSize = MFI.getStackSize();
1223 
1224  // Get processor type.
1225  bool isPPC64 = Subtarget.isPPC64();
1226  // Get the ABI.
1227  bool isSVR4ABI = Subtarget.isSVR4ABI();
1228 
1229  // Check if the link register (LR) has been saved.
1231  bool MustSaveLR = FI->mustSaveLR();
1232  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1233  bool MustSaveCR = !MustSaveCRs.empty();
1234  // Do we have a frame pointer and/or base pointer for this function?
1235  bool HasFP = hasFP(MF);
1236  bool HasBP = RegInfo->hasBasePointer(MF);
1237  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1238 
1239  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1240  unsigned BPReg = RegInfo->getBaseRegister(MF);
1241  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1242  unsigned ScratchReg = 0;
1243  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1244  const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1245  : PPC::MTLR );
1246  const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1247  : PPC::LWZ );
1248  const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1249  : PPC::LIS );
1250  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1251  : PPC::OR );
1252  const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1253  : PPC::ORI );
1254  const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1255  : PPC::ADDI );
1256  const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1257  : PPC::ADD4 );
1258 
1259  int LROffset = getReturnSaveOffset();
1260 
1261  int FPOffset = 0;
1262 
1263  // Using the same bool variable as below to suppress compiler warnings.
1264  bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
1265  &TempReg);
1266  assert(SingleScratchReg &&
1267  "Could not find an available scratch register");
1268 
1269  SingleScratchReg = ScratchReg == TempReg;
1270 
1271  if (HasFP) {
1272  if (isSVR4ABI) {
1273  int FPIndex = FI->getFramePointerSaveIndex();
1274  assert(FPIndex && "No Frame Pointer Save Slot!");
1275  FPOffset = MFI.getObjectOffset(FPIndex);
1276  } else {
1277  FPOffset = getFramePointerSaveOffset();
1278  }
1279  }
1280 
1281  int BPOffset = 0;
1282  if (HasBP) {
1283  if (isSVR4ABI) {
1284  int BPIndex = FI->getBasePointerSaveIndex();
1285  assert(BPIndex && "No Base Pointer Save Slot!");
1286  BPOffset = MFI.getObjectOffset(BPIndex);
1287  } else {
1288  BPOffset = getBasePointerSaveOffset();
1289  }
1290  }
1291 
1292  int PBPOffset = 0;
1293  if (FI->usesPICBase()) {
1294  int PBPIndex = FI->getPICBasePointerSaveIndex();
1295  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1296  PBPOffset = MFI.getObjectOffset(PBPIndex);
1297  }
1298 
1299  bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1300 
1301  if (IsReturnBlock) {
1302  unsigned RetOpcode = MBBI->getOpcode();
1303  bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1304  RetOpcode == PPC::TCRETURNdi ||
1305  RetOpcode == PPC::TCRETURNai ||
1306  RetOpcode == PPC::TCRETURNri8 ||
1307  RetOpcode == PPC::TCRETURNdi8 ||
1308  RetOpcode == PPC::TCRETURNai8;
1309 
1310  if (UsesTCRet) {
1311  int MaxTCRetDelta = FI->getTailCallSPDelta();
1312  MachineOperand &StackAdjust = MBBI->getOperand(1);
1313  assert(StackAdjust.isImm() && "Expecting immediate value.");
1314  // Adjust stack pointer.
1315  int StackAdj = StackAdjust.getImm();
1316  int Delta = StackAdj - MaxTCRetDelta;
1317  assert((Delta >= 0) && "Delta must be positive");
1318  if (MaxTCRetDelta>0)
1319  FrameSize += (StackAdj +Delta);
1320  else
1321  FrameSize += StackAdj;
1322  }
1323  }
1324 
1325  // Frames of 32KB & larger require special handling because they cannot be
1326  // indexed into with a simple LD/LWZ immediate offset operand.
1327  bool isLargeFrame = !isInt<16>(FrameSize);
1328 
1329  // On targets without red zone, the SP needs to be restored last, so that
1330  // all live contents of the stack frame are upwards of the SP. This means
1331  // that we cannot restore SP just now, since there may be more registers
1332  // to restore from the stack frame (e.g. R31). If the frame size is not
1333  // a simple immediate value, we will need a spare register to hold the
1334  // restored SP. If the frame size is known and small, we can simply adjust
1335  // the offsets of the registers to be restored, and still use SP to restore
1336  // them. In such case, the final update of SP will be to add the frame
1337  // size to it.
1338  // To simplify the code, set RBReg to the base register used to restore
1339  // values from the stack, and set SPAdd to the value that needs to be added
1340  // to the SP at the end. The default values are as if red zone was present.
1341  unsigned RBReg = SPReg;
1342  unsigned SPAdd = 0;
1343 
1344  if (FrameSize) {
1345  // In the prologue, the loaded (or persistent) stack pointer value is
1346  // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
1347  // zone add this offset back now.
1348 
1349  // If this function contained a fastcc call and GuaranteedTailCallOpt is
1350  // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1351  // call which invalidates the stack pointer value in SP(0). So we use the
1352  // value of R31 in this case.
1353  if (FI->hasFastCall()) {
1354  assert(HasFP && "Expecting a valid frame pointer.");
1355  if (!HasRedZone)
1356  RBReg = FPReg;
1357  if (!isLargeFrame) {
1358  BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1359  .addReg(FPReg).addImm(FrameSize);
1360  } else {
1361  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1362  .addImm(FrameSize >> 16);
1363  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1364  .addReg(ScratchReg, RegState::Kill)
1365  .addImm(FrameSize & 0xFFFF);
1366  BuildMI(MBB, MBBI, dl, AddInst)
1367  .addReg(RBReg)
1368  .addReg(FPReg)
1369  .addReg(ScratchReg);
1370  }
1371  } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
1372  if (HasRedZone) {
1373  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1374  .addReg(SPReg)
1375  .addImm(FrameSize);
1376  } else {
1377  // Make sure that adding FrameSize will not overflow the max offset
1378  // size.
1379  assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1380  "Local offsets should be negative");
1381  SPAdd = FrameSize;
1382  FPOffset += FrameSize;
1383  BPOffset += FrameSize;
1384  PBPOffset += FrameSize;
1385  }
1386  } else {
1387  // We don't want to use ScratchReg as a base register, because it
1388  // could happen to be R0. Use FP instead, but make sure to preserve it.
1389  if (!HasRedZone) {
1390  // If FP is not saved, copy it to ScratchReg.
1391  if (!HasFP)
1392  BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1393  .addReg(FPReg)
1394  .addReg(FPReg);
1395  RBReg = FPReg;
1396  }
1397  BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
1398  .addImm(0)
1399  .addReg(SPReg);
1400  }
1401  }
1402  assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
1403  // If there is no red zone, ScratchReg may be needed for holding a useful
1404  // value (although not the base register). Make sure it is not overwritten
1405  // too early.
1406 
1407  assert((isPPC64 || !MustSaveCR) &&
1408  "Epilogue CR restoring supported only in 64-bit mode");
1409 
1410  // If we need to restore both the LR and the CR and we only have one
1411  // available scratch register, we must do them one at a time.
1412  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1413  // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
1414  // is live here.
1415  assert(HasRedZone && "Expecting red zone");
1416  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1417  .addImm(8)
1418  .addReg(SPReg);
1419  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1420  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1421  .addReg(TempReg, getKillRegState(i == e-1));
1422  }
1423 
1424  // Delay restoring of the LR if ScratchReg is needed. This is ok, since
1425  // LR is stored in the caller's stack frame. ScratchReg will be needed
1426  // if RBReg is anything other than SP. We shouldn't use ScratchReg as
1427  // a base register anyway, because it may happen to be R0.
1428  bool LoadedLR = false;
1429  if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1430  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1431  .addImm(LROffset+SPAdd)
1432  .addReg(RBReg);
1433  LoadedLR = true;
1434  }
1435 
1436  if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1437  // This will only occur for PPC64.
1438  assert(isPPC64 && "Expecting 64-bit mode");
1439  assert(RBReg == SPReg && "Should be using SP as a base register");
1440  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1441  .addImm(8)
1442  .addReg(RBReg);
1443  }
1444 
1445  if (HasFP) {
1446  // If there is red zone, restore FP directly, since SP has already been
1447  // restored. Otherwise, restore the value of FP into ScratchReg.
1448  if (HasRedZone || RBReg == SPReg)
1449  BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1450  .addImm(FPOffset)
1451  .addReg(SPReg);
1452  else
1453  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1454  .addImm(FPOffset)
1455  .addReg(RBReg);
1456  }
1457 
1458  if (FI->usesPICBase())
1459  BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)
1460  .addImm(PBPOffset)
1461  .addReg(RBReg);
1462 
1463  if (HasBP)
1464  BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1465  .addImm(BPOffset)
1466  .addReg(RBReg);
1467 
1468  // There is nothing more to be loaded from the stack, so now we can
1469  // restore SP: SP = RBReg + SPAdd.
1470  if (RBReg != SPReg || SPAdd != 0) {
1471  assert(!HasRedZone && "This should not happen with red zone");
1472  // If SPAdd is 0, generate a copy.
1473  if (SPAdd == 0)
1474  BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1475  .addReg(RBReg)
1476  .addReg(RBReg);
1477  else
1478  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1479  .addReg(RBReg)
1480  .addImm(SPAdd);
1481 
1482  assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
1483  if (RBReg == FPReg)
1484  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1485  .addReg(ScratchReg)
1486  .addReg(ScratchReg);
1487 
1488  // Now load the LR from the caller's stack frame.
1489  if (MustSaveLR && !LoadedLR)
1490  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1491  .addImm(LROffset)
1492  .addReg(SPReg);
1493  }
1494 
1495  if (MustSaveCR &&
1496  !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1497  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1498  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1499  .addReg(TempReg, getKillRegState(i == e-1));
1500 
1501  if (MustSaveLR)
1502  BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1503 
1504  // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1505  // call optimization
1506  if (IsReturnBlock) {
1507  unsigned RetOpcode = MBBI->getOpcode();
1509  (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1512  unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1513 
1514  if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1515  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1516  .addReg(SPReg).addImm(CallerAllocatedAmt);
1517  } else {
1518  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1519  .addImm(CallerAllocatedAmt >> 16);
1520  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1521  .addReg(ScratchReg, RegState::Kill)
1522  .addImm(CallerAllocatedAmt & 0xFFFF);
1523  BuildMI(MBB, MBBI, dl, AddInst)
1524  .addReg(SPReg)
1525  .addReg(FPReg)
1526  .addReg(ScratchReg);
1527  }
1528  } else {
1529  createTailCallBranchInstr(MBB);
1530  }
1531  }
1532 }
1533 
1534 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const {
1536  DebugLoc dl;
1537 
1538  if (MBBI != MBB.end())
1539  dl = MBBI->getDebugLoc();
1540 
1541  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1542 
1543  // Create branch instruction for pseudo tail call return instruction
1544  unsigned RetOpcode = MBBI->getOpcode();
1545  if (RetOpcode == PPC::TCRETURNdi) {
1546  MBBI = MBB.getLastNonDebugInstr();
1547  MachineOperand &JumpTarget = MBBI->getOperand(0);
1548  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1549  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1550  } else if (RetOpcode == PPC::TCRETURNri) {
1551  MBBI = MBB.getLastNonDebugInstr();
1552  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1553  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1554  } else if (RetOpcode == PPC::TCRETURNai) {
1555  MBBI = MBB.getLastNonDebugInstr();
1556  MachineOperand &JumpTarget = MBBI->getOperand(0);
1557  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1558  } else if (RetOpcode == PPC::TCRETURNdi8) {
1559  MBBI = MBB.getLastNonDebugInstr();
1560  MachineOperand &JumpTarget = MBBI->getOperand(0);
1561  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1562  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1563  } else if (RetOpcode == PPC::TCRETURNri8) {
1564  MBBI = MBB.getLastNonDebugInstr();
1565  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1566  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1567  } else if (RetOpcode == PPC::TCRETURNai8) {
1568  MBBI = MBB.getLastNonDebugInstr();
1569  MachineOperand &JumpTarget = MBBI->getOperand(0);
1570  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1571  }
1572 }
1573 
1575  BitVector &SavedRegs,
1576  RegScavenger *RS) const {
1577  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1578 
1579  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1580 
1581  // Save and clear the LR state.
1583  unsigned LR = RegInfo->getRARegister();
1584  FI->setMustSaveLR(MustSaveLR(MF, LR));
1585  SavedRegs.reset(LR);
1586 
1587  // Save R31 if necessary
1588  int FPSI = FI->getFramePointerSaveIndex();
1589  bool isPPC64 = Subtarget.isPPC64();
1590  bool isDarwinABI = Subtarget.isDarwinABI();
1591  MachineFrameInfo &MFI = MF.getFrameInfo();
1592 
1593  // If the frame pointer save index hasn't been defined yet.
1594  if (!FPSI && needsFP(MF)) {
1595  // Find out what the fix offset of the frame pointer save area.
1596  int FPOffset = getFramePointerSaveOffset();
1597  // Allocate the frame index for frame pointer save area.
1598  FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1599  // Save the result.
1600  FI->setFramePointerSaveIndex(FPSI);
1601  }
1602 
1603  int BPSI = FI->getBasePointerSaveIndex();
1604  if (!BPSI && RegInfo->hasBasePointer(MF)) {
1605  int BPOffset = getBasePointerSaveOffset();
1606  // Allocate the frame index for the base pointer save area.
1607  BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1608  // Save the result.
1609  FI->setBasePointerSaveIndex(BPSI);
1610  }
1611 
1612  // Reserve stack space for the PIC Base register (R30).
1613  // Only used in SVR4 32-bit.
1614  if (FI->usesPICBase()) {
1615  int PBPSI = MFI.CreateFixedObject(4, -8, true);
1616  FI->setPICBasePointerSaveIndex(PBPSI);
1617  }
1618 
1619  // Make sure we don't explicitly spill r31, because, for example, we have
1620  // some inline asm which explicity clobbers it, when we otherwise have a
1621  // frame pointer and are using r31's spill slot for the prologue/epilogue
1622  // code. Same goes for the base pointer and the PIC base register.
1623  if (needsFP(MF))
1624  SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
1625  if (RegInfo->hasBasePointer(MF))
1626  SavedRegs.reset(RegInfo->getBaseRegister(MF));
1627  if (FI->usesPICBase())
1628  SavedRegs.reset(PPC::R30);
1629 
1630  // Reserve stack space to move the linkage area to in case of a tail call.
1631  int TCSPDelta = 0;
1633  (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1634  MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1635  }
1636 
1637  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1638  // function uses CR 2, 3, or 4.
1639  if (!isPPC64 && !isDarwinABI &&
1640  (SavedRegs.test(PPC::CR2) ||
1641  SavedRegs.test(PPC::CR3) ||
1642  SavedRegs.test(PPC::CR4))) {
1643  int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1644  FI->setCRSpillFrameIndex(FrameIdx);
1645  }
1646 }
1647 
1649  RegScavenger *RS) const {
1650  // Early exit if not using the SVR4 ABI.
1651  if (!Subtarget.isSVR4ABI()) {
1652  addScavengingSpillSlot(MF, RS);
1653  return;
1654  }
1655 
1656  // Get callee saved register information.
1657  MachineFrameInfo &MFI = MF.getFrameInfo();
1658  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1659 
1660  // If the function is shrink-wrapped, and if the function has a tail call, the
1661  // tail call might not be in the new RestoreBlock, so real branch instruction
1662  // won't be generated by emitEpilogue(), because shrink-wrap has chosen new
1663  // RestoreBlock. So we handle this case here.
1664  if (MFI.getSavePoint() && MFI.hasTailCall()) {
1665  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
1666  for (MachineBasicBlock &MBB : MF) {
1667  if (MBB.isReturnBlock() && (&MBB) != RestoreBlock)
1668  createTailCallBranchInstr(MBB);
1669  }
1670  }
1671 
1672  // Early exit if no callee saved registers are modified!
1673  if (CSI.empty() && !needsFP(MF)) {
1674  addScavengingSpillSlot(MF, RS);
1675  return;
1676  }
1677 
1678  unsigned MinGPR = PPC::R31;
1679  unsigned MinG8R = PPC::X31;
1680  unsigned MinFPR = PPC::F31;
1681  unsigned MinVR = PPC::V31;
1682 
1683  bool HasGPSaveArea = false;
1684  bool HasG8SaveArea = false;
1685  bool HasFPSaveArea = false;
1686  bool HasVRSAVESaveArea = false;
1687  bool HasVRSaveArea = false;
1688 
1693 
1694  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1695  unsigned Reg = CSI[i].getReg();
1696  if (PPC::GPRCRegClass.contains(Reg)) {
1697  HasGPSaveArea = true;
1698 
1699  GPRegs.push_back(CSI[i]);
1700 
1701  if (Reg < MinGPR) {
1702  MinGPR = Reg;
1703  }
1704  } else if (PPC::G8RCRegClass.contains(Reg)) {
1705  HasG8SaveArea = true;
1706 
1707  G8Regs.push_back(CSI[i]);
1708 
1709  if (Reg < MinG8R) {
1710  MinG8R = Reg;
1711  }
1712  } else if (PPC::F8RCRegClass.contains(Reg)) {
1713  HasFPSaveArea = true;
1714 
1715  FPRegs.push_back(CSI[i]);
1716 
1717  if (Reg < MinFPR) {
1718  MinFPR = Reg;
1719  }
1720  } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1721  PPC::CRRCRegClass.contains(Reg)) {
1722  ; // do nothing, as we already know whether CRs are spilled
1723  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1724  HasVRSAVESaveArea = true;
1725  } else if (PPC::VRRCRegClass.contains(Reg)) {
1726  HasVRSaveArea = true;
1727 
1728  VRegs.push_back(CSI[i]);
1729 
1730  if (Reg < MinVR) {
1731  MinVR = Reg;
1732  }
1733  } else {
1734  llvm_unreachable("Unknown RegisterClass!");
1735  }
1736  }
1737 
1739  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1740 
1741  int64_t LowerBound = 0;
1742 
1743  // Take into account stack space reserved for tail calls.
1744  int TCSPDelta = 0;
1746  (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1747  LowerBound = TCSPDelta;
1748  }
1749 
1750  // The Floating-point register save area is right below the back chain word
1751  // of the previous stack frame.
1752  if (HasFPSaveArea) {
1753  for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1754  int FI = FPRegs[i].getFrameIdx();
1755 
1756  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1757  }
1758 
1759  LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1760  }
1761 
1762  // Check whether the frame pointer register is allocated. If so, make sure it
1763  // is spilled to the correct offset.
1764  if (needsFP(MF)) {
1765  int FI = PFI->getFramePointerSaveIndex();
1766  assert(FI && "No Frame Pointer Save Slot!");
1767  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1768  // FP is R31/X31, so no need to update MinGPR/MinG8R.
1769  HasGPSaveArea = true;
1770  }
1771 
1772  if (PFI->usesPICBase()) {
1773  int FI = PFI->getPICBasePointerSaveIndex();
1774  assert(FI && "No PIC Base Pointer Save Slot!");
1775  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1776 
1777  MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
1778  HasGPSaveArea = true;
1779  }
1780 
1781  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1782  if (RegInfo->hasBasePointer(MF)) {
1783  int FI = PFI->getBasePointerSaveIndex();
1784  assert(FI && "No Base Pointer Save Slot!");
1785  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1786 
1787  unsigned BP = RegInfo->getBaseRegister(MF);
1788  if (PPC::G8RCRegClass.contains(BP)) {
1789  MinG8R = std::min<unsigned>(MinG8R, BP);
1790  HasG8SaveArea = true;
1791  } else if (PPC::GPRCRegClass.contains(BP)) {
1792  MinGPR = std::min<unsigned>(MinGPR, BP);
1793  HasGPSaveArea = true;
1794  }
1795  }
1796 
1797  // General register save area starts right below the Floating-point
1798  // register save area.
1799  if (HasGPSaveArea || HasG8SaveArea) {
1800  // Move general register save area spill slots down, taking into account
1801  // the size of the Floating-point register save area.
1802  for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1803  int FI = GPRegs[i].getFrameIdx();
1804 
1805  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1806  }
1807 
1808  // Move general register save area spill slots down, taking into account
1809  // the size of the Floating-point register save area.
1810  for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1811  int FI = G8Regs[i].getFrameIdx();
1812 
1813  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1814  }
1815 
1816  unsigned MinReg =
1817  std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1818  TRI->getEncodingValue(MinG8R));
1819 
1820  if (Subtarget.isPPC64()) {
1821  LowerBound -= (31 - MinReg + 1) * 8;
1822  } else {
1823  LowerBound -= (31 - MinReg + 1) * 4;
1824  }
1825  }
1826 
1827  // For 32-bit only, the CR save area is below the general register
1828  // save area. For 64-bit SVR4, the CR save area is addressed relative
1829  // to the stack pointer and hence does not need an adjustment here.
1830  // Only CR2 (the first nonvolatile spilled) has an associated frame
1831  // index so that we have a single uniform save area.
1832  if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1833  // Adjust the frame index of the CR spill slot.
1834  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1835  unsigned Reg = CSI[i].getReg();
1836 
1837  if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1838  // Leave Darwin logic as-is.
1839  || (!Subtarget.isSVR4ABI() &&
1840  (PPC::CRBITRCRegClass.contains(Reg) ||
1841  PPC::CRRCRegClass.contains(Reg)))) {
1842  int FI = CSI[i].getFrameIdx();
1843 
1844  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1845  }
1846  }
1847 
1848  LowerBound -= 4; // The CR save area is always 4 bytes long.
1849  }
1850 
1851  if (HasVRSAVESaveArea) {
1852  // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1853  // which have the VRSAVE register class?
1854  // Adjust the frame index of the VRSAVE spill slot.
1855  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1856  unsigned Reg = CSI[i].getReg();
1857 
1858  if (PPC::VRSAVERCRegClass.contains(Reg)) {
1859  int FI = CSI[i].getFrameIdx();
1860 
1861  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1862  }
1863  }
1864 
1865  LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1866  }
1867 
1868  if (HasVRSaveArea) {
1869  // Insert alignment padding, we need 16-byte alignment. Note: for postive
1870  // number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since
1871  // we are using negative number here (the stack grows downward). We should
1872  // use formula : y = x & (~(n-1)). Where x is the size before aligning, n
1873  // is the alignment size ( n = 16 here) and y is the size after aligning.
1874  assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
1875  LowerBound &= ~(15);
1876 
1877  for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1878  int FI = VRegs[i].getFrameIdx();
1879 
1880  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1881  }
1882  }
1883 
1884  addScavengingSpillSlot(MF, RS);
1885 }
1886 
1887 void
1889  RegScavenger *RS) const {
1890  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1891  // a large stack, which will require scavenging a register to materialize a
1892  // large offset.
1893 
1894  // We need to have a scavenger spill slot for spills if the frame size is
1895  // large. In case there is no free register for large-offset addressing,
1896  // this slot is used for the necessary emergency spill. Also, we need the
1897  // slot for dynamic stack allocations.
1898 
1899  // The scavenger might be invoked if the frame offset does not fit into
1900  // the 16-bit immediate. We don't know the complete frame size here
1901  // because we've not yet computed callee-saved register spills or the
1902  // needed alignment padding.
1903  unsigned StackSize = determineFrameLayout(MF, false, true);
1904  MachineFrameInfo &MFI = MF.getFrameInfo();
1905  if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1906  hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1907  const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
1908  const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
1909  const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
1910  const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
1911  unsigned Size = TRI.getSpillSize(RC);
1912  unsigned Align = TRI.getSpillAlignment(RC);
1913  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1914 
1915  // Might we have over-aligned allocas?
1916  bool HasAlVars = MFI.hasVarSizedObjects() &&
1918 
1919  // These kinds of spills might need two registers.
1920  if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1921  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1922 
1923  }
1924 }
1925 
1926 bool
1929  const std::vector<CalleeSavedInfo> &CSI,
1930  const TargetRegisterInfo *TRI) const {
1931 
1932  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1933  // Return false otherwise to maintain pre-existing behavior.
1934  if (!Subtarget.isSVR4ABI())
1935  return false;
1936 
1937  MachineFunction *MF = MBB.getParent();
1938  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1939  DebugLoc DL;
1940  bool CRSpilled = false;
1941  MachineInstrBuilder CRMIB;
1942 
1943  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1944  unsigned Reg = CSI[i].getReg();
1945  // Only Darwin actually uses the VRSAVE register, but it can still appear
1946  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1947  // Darwin, ignore it.
1948  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1949  continue;
1950 
1951  // CR2 through CR4 are the nonvolatile CR fields.
1952  bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1953 
1954  // Add the callee-saved register as live-in; it's killed at the spill.
1955  MBB.addLiveIn(Reg);
1956 
1957  if (CRSpilled && IsCRField) {
1958  CRMIB.addReg(Reg, RegState::ImplicitKill);
1959  continue;
1960  }
1961 
1962  // Insert the spill to the stack frame.
1963  if (IsCRField) {
1964  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1965  if (Subtarget.isPPC64()) {
1966  // The actual spill will happen at the start of the prologue.
1967  FuncInfo->addMustSaveCR(Reg);
1968  } else {
1969  CRSpilled = true;
1970  FuncInfo->setSpillsCR();
1971 
1972  // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1973  // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1974  CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1975  .addReg(Reg, RegState::ImplicitKill);
1976 
1977  MBB.insert(MI, CRMIB);
1978  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1979  .addReg(PPC::R12,
1980  getKillRegState(true)),
1981  CSI[i].getFrameIdx()));
1982  }
1983  } else {
1984  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1985  TII.storeRegToStackSlot(MBB, MI, Reg, true,
1986  CSI[i].getFrameIdx(), RC, TRI);
1987  }
1988  }
1989  return true;
1990 }
1991 
1992 static void
1993 restoreCRs(bool isPPC64, bool is31,
1994  bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1996  const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1997 
1998  MachineFunction *MF = MBB.getParent();
1999  const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
2000  DebugLoc DL;
2001  unsigned RestoreOp, MoveReg;
2002 
2003  if (isPPC64)
2004  // This is handled during epilogue generation.
2005  return;
2006  else {
2007  // 32-bit: FP-relative
2008  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
2009  PPC::R12),
2010  CSI[CSIIndex].getFrameIdx()));
2011  RestoreOp = PPC::MTOCRF;
2012  MoveReg = PPC::R12;
2013  }
2014 
2015  if (CR2Spilled)
2016  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2017  .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2018 
2019  if (CR3Spilled)
2020  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2021  .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2022 
2023  if (CR4Spilled)
2024  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2025  .addReg(MoveReg, getKillRegState(true)));
2026 }
2027 
2031  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2033  I->getOpcode() == PPC::ADJCALLSTACKUP) {
2034  // Add (actually subtract) back the amount the callee popped on return.
2035  if (int CalleeAmt = I->getOperand(1).getImm()) {
2036  bool is64Bit = Subtarget.isPPC64();
2037  CalleeAmt *= -1;
2038  unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2039  unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2040  unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2041  unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2042  unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2043  unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2044  const DebugLoc &dl = I->getDebugLoc();
2045 
2046  if (isInt<16>(CalleeAmt)) {
2047  BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2048  .addReg(StackReg, RegState::Kill)
2049  .addImm(CalleeAmt);
2050  } else {
2052  BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2053  .addImm(CalleeAmt >> 16);
2054  BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2055  .addReg(TmpReg, RegState::Kill)
2056  .addImm(CalleeAmt & 0xFFFF);
2057  BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2058  .addReg(StackReg, RegState::Kill)
2059  .addReg(TmpReg);
2060  }
2061  }
2062  }
2063  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
2064  return MBB.erase(I);
2065 }
2066 
2067 bool
2070  const std::vector<CalleeSavedInfo> &CSI,
2071  const TargetRegisterInfo *TRI) const {
2072 
2073  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
2074  // Return false otherwise to maintain pre-existing behavior.
2075  if (!Subtarget.isSVR4ABI())
2076  return false;
2077 
2078  MachineFunction *MF = MBB.getParent();
2079  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
2080  bool CR2Spilled = false;
2081  bool CR3Spilled = false;
2082  bool CR4Spilled = false;
2083  unsigned CSIIndex = 0;
2084 
2085  // Initialize insertion-point logic; we will be restoring in reverse
2086  // order of spill.
2087  MachineBasicBlock::iterator I = MI, BeforeI = I;
2088  bool AtStart = I == MBB.begin();
2089 
2090  if (!AtStart)
2091  --BeforeI;
2092 
2093  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2094  unsigned Reg = CSI[i].getReg();
2095 
2096  // Only Darwin actually uses the VRSAVE register, but it can still appear
2097  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
2098  // Darwin, ignore it.
2099  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
2100  continue;
2101 
2102  if (Reg == PPC::CR2) {
2103  CR2Spilled = true;
2104  // The spill slot is associated only with CR2, which is the
2105  // first nonvolatile spilled. Save it here.
2106  CSIIndex = i;
2107  continue;
2108  } else if (Reg == PPC::CR3) {
2109  CR3Spilled = true;
2110  continue;
2111  } else if (Reg == PPC::CR4) {
2112  CR4Spilled = true;
2113  continue;
2114  } else {
2115  // When we first encounter a non-CR register after seeing at
2116  // least one CR register, restore all spilled CRs together.
2117  if ((CR2Spilled || CR3Spilled || CR4Spilled)
2118  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2119  bool is31 = needsFP(*MF);
2120  restoreCRs(Subtarget.isPPC64(), is31,
2121  CR2Spilled, CR3Spilled, CR4Spilled,
2122  MBB, I, CSI, CSIIndex);
2123  CR2Spilled = CR3Spilled = CR4Spilled = false;
2124  }
2125 
2126  // Default behavior for non-CR saves.
2127  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2128  TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
2129  RC, TRI);
2130  assert(I != MBB.begin() &&
2131  "loadRegFromStackSlot didn't insert any code!");
2132  }
2133 
2134  // Insert in reverse order.
2135  if (AtStart)
2136  I = MBB.begin();
2137  else {
2138  I = BeforeI;
2139  ++I;
2140  }
2141  }
2142 
2143  // If we haven't yet spilled the CRs, do so now.
2144  if (CR2Spilled || CR3Spilled || CR4Spilled) {
2145  bool is31 = needsFP(*MF);
2146  restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
2147  MBB, I, CSI, CSIIndex);
2148  }
2149 
2150  return true;
2151 }
2152 
2154  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
2155  MF.getSubtarget<PPCSubtarget>().isPPC64());
2156 }
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
static const unsigned GPRegs[]
bool hasDebugInfo() const
Returns true if valid debug info is present.
livein_iterator livein_begin() const
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addMustSaveCR(unsigned Reg)
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:257
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:404
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool test(unsigned Idx) const
Definition: BitVector.h:502
void setFramePointerSaveIndex(int Idx)
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:868
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static const MCPhysReg VRegs[32]
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:254
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
A debug info location.
Definition: DebugLoc.h:34
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
An instruction for reading from memory.
Definition: Instructions.h:164
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:391
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment for a spill slot for a register of this class.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:282
MachineBasicBlock * getRestorePoint() const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
Reg
All possible values of the reg field in the ModR/M byte.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
def_iterator def_begin(unsigned RegNo) const
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool isELFv2ABI() const
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
livein_iterator livein_end() const
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:189
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
Definition: Instructions.h:306
bool hasBasePointer(const MachineFunction &MF) const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getBaseRegister(const MachineFunction &MF) const
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
static const unsigned G8Regs[]
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:384
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
BitVector & reset()
Definition: BitVector.h:439
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:186
Iterator for intrusive lists based on ilist_node.
#define E
Definition: LargeTest.cpp:27
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:186
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:179
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:731
Information about stack frame layout on the target.
bool isDarwinABI() const
Definition: PPCSubtarget.h:304
static bool spillsVRSAVE(const MachineFunction &MF)
static bool hasSpills(const MachineFunction &MF)
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
int64_t getImm() const
unsigned getMinReservedArea() const
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:497
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:531
static bool spillsCR(const MachineFunction &MF)
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:278
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void setPICBasePointerSaveIndex(int Idx)
Representation of each machine instruction.
Definition: MachineInstr.h:59
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:95
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
void setMaxCallFrameSize(unsigned S)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool needsFP(const MachineFunction &MF) const
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock * getSavePoint() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:285
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:305
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:284
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
void replaceFPWithRealFP(MachineFunction &MF) const
This class contains meta information specific to a module.