LLVM  8.0.0svn
PPCFrameLowering.cpp
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1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
26 #include "llvm/IR/Function.h"
28 
29 using namespace llvm;
30 
31 /// VRRegNo - Map from a numbered VR register to its enum value.
32 ///
33 static const MCPhysReg VRRegNo[] = {
34  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 };
39 
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41  if (STI.isDarwinABI())
42  return STI.isPPC64() ? 16 : 8;
43  // SVR4 ABI:
44  return STI.isPPC64() ? 16 : 4;
45 }
46 
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48  return STI.isELFv2ABI() ? 24 : 40;
49 }
50 
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52  // For the Darwin ABI:
53  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54  // for saving the frame pointer (if needed.) While the published ABI has
55  // not used this slot since at least MacOSX 10.2, there is older code
56  // around that does use it, and that needs to continue to work.
57  if (STI.isDarwinABI())
58  return STI.isPPC64() ? -8U : -4U;
59 
60  // SVR4 ABI: First slot in the general register save area.
61  return STI.isPPC64() ? -8U : -4U;
62 }
63 
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65  if (STI.isDarwinABI() || STI.isPPC64())
66  return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
67 
68  // SVR4 ABI:
69  return 8;
70 }
71 
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73  if (STI.isDarwinABI())
74  return STI.isPPC64() ? -16U : -8U;
75 
76  // SVR4 ABI: First slot in the general register save area.
77  return STI.isPPC64()
78  ? -16U
79  : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
80 }
81 
83  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
84  STI.getPlatformStackAlignment(), 0),
85  Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
86  TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
87  FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
88  LinkageSize(computeLinkageSize(Subtarget)),
89  BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
90 
91 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
93  unsigned &NumEntries) const {
94  if (Subtarget.isDarwinABI()) {
95  NumEntries = 1;
96  if (Subtarget.isPPC64()) {
97  static const SpillSlot darwin64Offsets = {PPC::X31, -8};
98  return &darwin64Offsets;
99  } else {
100  static const SpillSlot darwinOffsets = {PPC::R31, -4};
101  return &darwinOffsets;
102  }
103  }
104 
105  // Early exit if not using the SVR4 ABI.
106  if (!Subtarget.isSVR4ABI()) {
107  NumEntries = 0;
108  return nullptr;
109  }
110 
111  // Note that the offsets here overlap, but this is fixed up in
112  // processFunctionBeforeFrameFinalized.
113 
114  static const SpillSlot Offsets[] = {
115  // Floating-point register save area offsets.
116  {PPC::F31, -8},
117  {PPC::F30, -16},
118  {PPC::F29, -24},
119  {PPC::F28, -32},
120  {PPC::F27, -40},
121  {PPC::F26, -48},
122  {PPC::F25, -56},
123  {PPC::F24, -64},
124  {PPC::F23, -72},
125  {PPC::F22, -80},
126  {PPC::F21, -88},
127  {PPC::F20, -96},
128  {PPC::F19, -104},
129  {PPC::F18, -112},
130  {PPC::F17, -120},
131  {PPC::F16, -128},
132  {PPC::F15, -136},
133  {PPC::F14, -144},
134 
135  // General register save area offsets.
136  {PPC::R31, -4},
137  {PPC::R30, -8},
138  {PPC::R29, -12},
139  {PPC::R28, -16},
140  {PPC::R27, -20},
141  {PPC::R26, -24},
142  {PPC::R25, -28},
143  {PPC::R24, -32},
144  {PPC::R23, -36},
145  {PPC::R22, -40},
146  {PPC::R21, -44},
147  {PPC::R20, -48},
148  {PPC::R19, -52},
149  {PPC::R18, -56},
150  {PPC::R17, -60},
151  {PPC::R16, -64},
152  {PPC::R15, -68},
153  {PPC::R14, -72},
154 
155  // CR save area offset. We map each of the nonvolatile CR fields
156  // to the slot for CR2, which is the first of the nonvolatile CR
157  // fields to be assigned, so that we only allocate one save slot.
158  // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
159  {PPC::CR2, -4},
160 
161  // VRSAVE save area offset.
162  {PPC::VRSAVE, -4},
163 
164  // Vector register save area
165  {PPC::V31, -16},
166  {PPC::V30, -32},
167  {PPC::V29, -48},
168  {PPC::V28, -64},
169  {PPC::V27, -80},
170  {PPC::V26, -96},
171  {PPC::V25, -112},
172  {PPC::V24, -128},
173  {PPC::V23, -144},
174  {PPC::V22, -160},
175  {PPC::V21, -176},
176  {PPC::V20, -192},
177 
178  // SPE register save area (overlaps Vector save area).
179  {PPC::S31, -8},
180  {PPC::S30, -16},
181  {PPC::S29, -24},
182  {PPC::S28, -32},
183  {PPC::S27, -40},
184  {PPC::S26, -48},
185  {PPC::S25, -56},
186  {PPC::S24, -64},
187  {PPC::S23, -72},
188  {PPC::S22, -80},
189  {PPC::S21, -88},
190  {PPC::S20, -96},
191  {PPC::S19, -104},
192  {PPC::S18, -112},
193  {PPC::S17, -120},
194  {PPC::S16, -128},
195  {PPC::S15, -136},
196  {PPC::S14, -144}};
197 
198  static const SpillSlot Offsets64[] = {
199  // Floating-point register save area offsets.
200  {PPC::F31, -8},
201  {PPC::F30, -16},
202  {PPC::F29, -24},
203  {PPC::F28, -32},
204  {PPC::F27, -40},
205  {PPC::F26, -48},
206  {PPC::F25, -56},
207  {PPC::F24, -64},
208  {PPC::F23, -72},
209  {PPC::F22, -80},
210  {PPC::F21, -88},
211  {PPC::F20, -96},
212  {PPC::F19, -104},
213  {PPC::F18, -112},
214  {PPC::F17, -120},
215  {PPC::F16, -128},
216  {PPC::F15, -136},
217  {PPC::F14, -144},
218 
219  // General register save area offsets.
220  {PPC::X31, -8},
221  {PPC::X30, -16},
222  {PPC::X29, -24},
223  {PPC::X28, -32},
224  {PPC::X27, -40},
225  {PPC::X26, -48},
226  {PPC::X25, -56},
227  {PPC::X24, -64},
228  {PPC::X23, -72},
229  {PPC::X22, -80},
230  {PPC::X21, -88},
231  {PPC::X20, -96},
232  {PPC::X19, -104},
233  {PPC::X18, -112},
234  {PPC::X17, -120},
235  {PPC::X16, -128},
236  {PPC::X15, -136},
237  {PPC::X14, -144},
238 
239  // VRSAVE save area offset.
240  {PPC::VRSAVE, -4},
241 
242  // Vector register save area
243  {PPC::V31, -16},
244  {PPC::V30, -32},
245  {PPC::V29, -48},
246  {PPC::V28, -64},
247  {PPC::V27, -80},
248  {PPC::V26, -96},
249  {PPC::V25, -112},
250  {PPC::V24, -128},
251  {PPC::V23, -144},
252  {PPC::V22, -160},
253  {PPC::V21, -176},
254  {PPC::V20, -192}};
255 
256  if (Subtarget.isPPC64()) {
257  NumEntries = array_lengthof(Offsets64);
258 
259  return Offsets64;
260  } else {
261  NumEntries = array_lengthof(Offsets);
262 
263  return Offsets;
264  }
265 }
266 
267 /// RemoveVRSaveCode - We have found that this function does not need any code
268 /// to manipulate the VRSAVE register, even though it uses vector registers.
269 /// This can happen when the only registers used are known to be live in or out
270 /// of the function. Remove all of the VRSAVE related code from the function.
271 /// FIXME: The removal of the code results in a compile failure at -O0 when the
272 /// function contains a function call, as the GPR containing original VRSAVE
273 /// contents is spilled and reloaded around the call. Without the prolog code,
274 /// the spill instruction refers to an undefined register. This code needs
275 /// to account for all uses of that GPR.
277  MachineBasicBlock *Entry = MI.getParent();
278  MachineFunction *MF = Entry->getParent();
279 
280  // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
282  ++MBBI;
283  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
284  MBBI->eraseFromParent();
285 
286  bool RemovedAllMTVRSAVEs = true;
287  // See if we can find and remove the MTVRSAVE instruction from all of the
288  // epilog blocks.
289  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
290  // If last instruction is a return instruction, add an epilogue
291  if (I->isReturnBlock()) {
292  bool FoundIt = false;
293  for (MBBI = I->end(); MBBI != I->begin(); ) {
294  --MBBI;
295  if (MBBI->getOpcode() == PPC::MTVRSAVE) {
296  MBBI->eraseFromParent(); // remove it.
297  FoundIt = true;
298  break;
299  }
300  }
301  RemovedAllMTVRSAVEs &= FoundIt;
302  }
303  }
304 
305  // If we found and removed all MTVRSAVE instructions, remove the read of
306  // VRSAVE as well.
307  if (RemovedAllMTVRSAVEs) {
308  MBBI = MI;
309  assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
310  --MBBI;
311  assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
312  MBBI->eraseFromParent();
313  }
314 
315  // Finally, nuke the UPDATE_VRSAVE.
316  MI.eraseFromParent();
317 }
318 
319 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
320 // instruction selector. Based on the vector registers that have been used,
321 // transform this into the appropriate ORI instruction.
323  MachineFunction *MF = MI.getParent()->getParent();
325  DebugLoc dl = MI.getDebugLoc();
326 
327  const MachineRegisterInfo &MRI = MF->getRegInfo();
328  unsigned UsedRegMask = 0;
329  for (unsigned i = 0; i != 32; ++i)
330  if (MRI.isPhysRegModified(VRRegNo[i]))
331  UsedRegMask |= 1 << (31-i);
332 
333  // Live in and live out values already must be in the mask, so don't bother
334  // marking them.
335  for (std::pair<unsigned, unsigned> LI : MF->getRegInfo().liveins()) {
336  unsigned RegNo = TRI->getEncodingValue(LI.first);
337  if (VRRegNo[RegNo] == LI.first) // If this really is a vector reg.
338  UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
339  }
340 
341  // Live out registers appear as use operands on return instructions.
342  for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
343  UsedRegMask != 0 && BI != BE; ++BI) {
344  const MachineBasicBlock &MBB = *BI;
345  if (!MBB.isReturnBlock())
346  continue;
347  const MachineInstr &Ret = MBB.back();
348  for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
349  const MachineOperand &MO = Ret.getOperand(I);
350  if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
351  continue;
352  unsigned RegNo = TRI->getEncodingValue(MO.getReg());
353  UsedRegMask &= ~(1 << (31-RegNo));
354  }
355  }
356 
357  // If no registers are used, turn this into a copy.
358  if (UsedRegMask == 0) {
359  // Remove all VRSAVE code.
360  RemoveVRSaveCode(MI);
361  return;
362  }
363 
364  unsigned SrcReg = MI.getOperand(1).getReg();
365  unsigned DstReg = MI.getOperand(0).getReg();
366 
367  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
368  if (DstReg != SrcReg)
369  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
370  .addReg(SrcReg)
371  .addImm(UsedRegMask);
372  else
373  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
374  .addReg(SrcReg, RegState::Kill)
375  .addImm(UsedRegMask);
376  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
377  if (DstReg != SrcReg)
378  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
379  .addReg(SrcReg)
380  .addImm(UsedRegMask >> 16);
381  else
382  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
383  .addReg(SrcReg, RegState::Kill)
384  .addImm(UsedRegMask >> 16);
385  } else {
386  if (DstReg != SrcReg)
387  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
388  .addReg(SrcReg)
389  .addImm(UsedRegMask >> 16);
390  else
391  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
392  .addReg(SrcReg, RegState::Kill)
393  .addImm(UsedRegMask >> 16);
394 
395  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
396  .addReg(DstReg, RegState::Kill)
397  .addImm(UsedRegMask & 0xFFFF);
398  }
399 
400  // Remove the old UPDATE_VRSAVE instruction.
401  MI.eraseFromParent();
402 }
403 
404 static bool spillsCR(const MachineFunction &MF) {
405  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
406  return FuncInfo->isCRSpilled();
407 }
408 
409 static bool spillsVRSAVE(const MachineFunction &MF) {
410  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
411  return FuncInfo->isVRSAVESpilled();
412 }
413 
414 static bool hasSpills(const MachineFunction &MF) {
415  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
416  return FuncInfo->hasSpills();
417 }
418 
419 static bool hasNonRISpills(const MachineFunction &MF) {
420  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
421  return FuncInfo->hasNonRISpills();
422 }
423 
424 /// MustSaveLR - Return true if this function requires that we save the LR
425 /// register onto the stack in the prolog and restore it in the epilog of the
426 /// function.
427 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
428  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
429 
430  // We need a save/restore of LR if there is any def of LR (which is
431  // defined by calls, including the PIC setup sequence), or if there is
432  // some use of the LR stack slot (e.g. for builtin_return_address).
433  // (LR comes in 32 and 64 bit versions.)
435  return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
436 }
437 
438 /// determineFrameLayout - Determine the size of the frame and maximum call
439 /// frame size.
441  bool UpdateMF,
442  bool UseEstimate) const {
443  MachineFrameInfo &MFI = MF.getFrameInfo();
444 
445  // Get the number of bytes to allocate from the FrameInfo
446  unsigned FrameSize =
447  UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
448 
449  // Get stack alignments. The frame must be aligned to the greatest of these:
450  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
451  unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
452  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
453 
454  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
455 
456  unsigned LR = RegInfo->getRARegister();
457  bool DisableRedZone = MF.getFunction().hasFnAttribute(Attribute::NoRedZone);
458  bool CanUseRedZone = !MFI.hasVarSizedObjects() && // No dynamic alloca.
459  !MFI.adjustsStack() && // No calls.
460  !MustSaveLR(MF, LR) && // No need to save LR.
461  !RegInfo->hasBasePointer(MF); // No special alignment.
462 
463  // Note: for PPC32 SVR4ABI (Non-DarwinABI), we can still generate stackless
464  // code if all local vars are reg-allocated.
465  bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize();
466 
467  // Check whether we can skip adjusting the stack pointer (by using red zone)
468  if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
469  // No need for frame
470  if (UpdateMF)
471  MFI.setStackSize(0);
472  return 0;
473  }
474 
475  // Get the maximum call frame size of all the calls.
476  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
477 
478  // Maximum call frame needs to be at least big enough for linkage area.
479  unsigned minCallFrameSize = getLinkageSize();
480  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
481 
482  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
483  // that allocations will be aligned.
484  if (MFI.hasVarSizedObjects())
485  maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
486 
487  // Update maximum call frame size.
488  if (UpdateMF)
489  MFI.setMaxCallFrameSize(maxCallFrameSize);
490 
491  // Include call frame size in total.
492  FrameSize += maxCallFrameSize;
493 
494  // Make sure the frame is aligned.
495  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
496 
497  // Update frame info.
498  if (UpdateMF)
499  MFI.setStackSize(FrameSize);
500 
501  return FrameSize;
502 }
503 
504 // hasFP - Return true if the specified function actually has a dedicated frame
505 // pointer register.
507  const MachineFrameInfo &MFI = MF.getFrameInfo();
508  // FIXME: This is pretty much broken by design: hasFP() might be called really
509  // early, before the stack layout was calculated and thus hasFP() might return
510  // true or false here depending on the time of call.
511  return (MFI.getStackSize()) && needsFP(MF);
512 }
513 
514 // needsFP - Return true if the specified function should have a dedicated frame
515 // pointer register. This is true if the function has variable sized allocas or
516 // if frame pointer elimination is disabled.
518  const MachineFrameInfo &MFI = MF.getFrameInfo();
519 
520  // Naked functions have no stack frame pushed, so we don't have a frame
521  // pointer.
522  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
523  return false;
524 
525  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
526  MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint() ||
528  MF.getInfo<PPCFunctionInfo>()->hasFastCall());
529 }
530 
532  bool is31 = needsFP(MF);
533  unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
534  unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
535 
536  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
537  bool HasBP = RegInfo->hasBasePointer(MF);
538  unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
539  unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
540 
541  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
542  BI != BE; ++BI)
543  for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
544  --MBBI;
545  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
546  MachineOperand &MO = MBBI->getOperand(I);
547  if (!MO.isReg())
548  continue;
549 
550  switch (MO.getReg()) {
551  case PPC::FP:
552  MO.setReg(FPReg);
553  break;
554  case PPC::FP8:
555  MO.setReg(FP8Reg);
556  break;
557  case PPC::BP:
558  MO.setReg(BPReg);
559  break;
560  case PPC::BP8:
561  MO.setReg(BP8Reg);
562  break;
563 
564  }
565  }
566  }
567 }
568 
569 /* This function will do the following:
570  - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
571  respectively (defaults recommended by the ABI) and return true
572  - If MBB is not an entry block, initialize the register scavenger and look
573  for available registers.
574  - If the defaults (R0/R12) are available, return true
575  - If TwoUniqueRegsRequired is set to true, it looks for two unique
576  registers. Otherwise, look for a single available register.
577  - If the required registers are found, set SR1 and SR2 and return true.
578  - If the required registers are not found, set SR2 or both SR1 and SR2 to
579  PPC::NoRegister and return false.
580 
581  Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
582  is not set, this function will attempt to find two different registers, but
583  still return true if only one register is available (and set SR1 == SR2).
584 */
585 bool
586 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
587  bool UseAtEnd,
588  bool TwoUniqueRegsRequired,
589  unsigned *SR1,
590  unsigned *SR2) const {
591  RegScavenger RS;
592  unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
593  unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
594 
595  // Set the defaults for the two scratch registers.
596  if (SR1)
597  *SR1 = R0;
598 
599  if (SR2) {
600  assert (SR1 && "Asking for the second scratch register but not the first?");
601  *SR2 = R12;
602  }
603 
604  // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
605  if ((UseAtEnd && MBB->isReturnBlock()) ||
606  (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
607  return true;
608 
609  RS.enterBasicBlock(*MBB);
610 
611  if (UseAtEnd && !MBB->empty()) {
612  // The scratch register will be used at the end of the block, so must
613  // consider all registers used within the block
614 
616  // If no terminator, back iterator up to previous instruction.
617  if (MBBI == MBB->end())
618  MBBI = std::prev(MBBI);
619 
620  if (MBBI != MBB->begin())
621  RS.forward(MBBI);
622  }
623 
624  // If the two registers are available, we're all good.
625  // Note that we only return here if both R0 and R12 are available because
626  // although the function may not require two unique registers, it may benefit
627  // from having two so we should try to provide them.
628  if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
629  return true;
630 
631  // Get the list of callee-saved registers for the target.
632  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
633  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
634 
635  // Get all the available registers in the block.
636  BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
637  &PPC::GPRCRegClass);
638 
639  // We shouldn't use callee-saved registers as scratch registers as they may be
640  // available when looking for a candidate block for shrink wrapping but not
641  // available when the actual prologue/epilogue is being emitted because they
642  // were added as live-in to the prologue block by PrologueEpilogueInserter.
643  for (int i = 0; CSRegs[i]; ++i)
644  BV.reset(CSRegs[i]);
645 
646  // Set the first scratch register to the first available one.
647  if (SR1) {
648  int FirstScratchReg = BV.find_first();
649  *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
650  }
651 
652  // If there is another one available, set the second scratch register to that.
653  // Otherwise, set it to either PPC::NoRegister if this function requires two
654  // or to whatever SR1 is set to if this function doesn't require two.
655  if (SR2) {
656  int SecondScratchReg = BV.find_next(*SR1);
657  if (SecondScratchReg != -1)
658  *SR2 = SecondScratchReg;
659  else
660  *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
661  }
662 
663  // Now that we've done our best to provide both registers, double check
664  // whether we were unable to provide enough.
665  if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U))
666  return false;
667 
668  return true;
669 }
670 
671 // We need a scratch register for spilling LR and for spilling CR. By default,
672 // we use two scratch registers to hide latency. However, if only one scratch
673 // register is available, we can adjust for that by not overlapping the spill
674 // code. However, if we need to realign the stack (i.e. have a base pointer)
675 // and the stack frame is large, we need two scratch registers.
676 bool
677 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
678  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
679  MachineFunction &MF = *(MBB->getParent());
680  bool HasBP = RegInfo->hasBasePointer(MF);
681  unsigned FrameSize = determineFrameLayout(MF, false);
682  int NegFrameSize = -FrameSize;
683  bool IsLargeFrame = !isInt<16>(NegFrameSize);
684  MachineFrameInfo &MFI = MF.getFrameInfo();
685  unsigned MaxAlign = MFI.getMaxAlignment();
686  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
687 
688  return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
689 }
690 
692  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
693 
694  return findScratchRegister(TmpMBB, false,
695  twoUniqueScratchRegsRequired(TmpMBB));
696 }
697 
699  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
700 
701  return findScratchRegister(TmpMBB, true);
702 }
703 
705  MachineBasicBlock &MBB) const {
706  MachineBasicBlock::iterator MBBI = MBB.begin();
707  MachineFrameInfo &MFI = MF.getFrameInfo();
708  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
709  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
710 
711  MachineModuleInfo &MMI = MF.getMMI();
712  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
713  DebugLoc dl;
714  bool needsCFI = MMI.hasDebugInfo() ||
716 
717  // Get processor type.
718  bool isPPC64 = Subtarget.isPPC64();
719  // Get the ABI.
720  bool isSVR4ABI = Subtarget.isSVR4ABI();
721  bool isELFv2ABI = Subtarget.isELFv2ABI();
722  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
723  "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
724 
725  // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
726  // process it.
727  if (!isSVR4ABI)
728  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
729  if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
730  HandleVRSaveUpdate(*MBBI, TII);
731  break;
732  }
733  }
734 
735  // Move MBBI back to the beginning of the prologue block.
736  MBBI = MBB.begin();
737 
738  // Work out frame sizes.
739  unsigned FrameSize = determineFrameLayout(MF);
740  int NegFrameSize = -FrameSize;
741  if (!isInt<32>(NegFrameSize))
742  llvm_unreachable("Unhandled stack size!");
743 
744  if (MFI.isFrameAddressTaken())
746 
747  // Check if the link register (LR) must be saved.
749  bool MustSaveLR = FI->mustSaveLR();
750  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
751  bool MustSaveCR = !MustSaveCRs.empty();
752  // Do we have a frame pointer and/or base pointer for this function?
753  bool HasFP = hasFP(MF);
754  bool HasBP = RegInfo->hasBasePointer(MF);
755  bool HasRedZone = isPPC64 || !isSVR4ABI;
756 
757  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
758  unsigned BPReg = RegInfo->getBaseRegister(MF);
759  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
760  unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
761  unsigned ScratchReg = 0;
762  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
763  // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
764  const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
765  : PPC::MFLR );
766  const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
767  : PPC::STW );
768  const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
769  : PPC::STWU );
770  const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
771  : PPC::STWUX);
772  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
773  : PPC::LIS );
774  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
775  : PPC::ORI );
776  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
777  : PPC::OR );
778  const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
779  : PPC::SUBFC);
780  const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
781  : PPC::SUBFIC);
782 
783  // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
784  // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
785  // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
786  // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
787  assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
788  "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
789 
790  // Using the same bool variable as below to suppress compiler warnings.
791  bool SingleScratchReg =
792  findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
793  &ScratchReg, &TempReg);
794  assert(SingleScratchReg &&
795  "Required number of registers not available in this block");
796 
797  SingleScratchReg = ScratchReg == TempReg;
798 
799  int LROffset = getReturnSaveOffset();
800 
801  int FPOffset = 0;
802  if (HasFP) {
803  if (isSVR4ABI) {
804  MachineFrameInfo &MFI = MF.getFrameInfo();
805  int FPIndex = FI->getFramePointerSaveIndex();
806  assert(FPIndex && "No Frame Pointer Save Slot!");
807  FPOffset = MFI.getObjectOffset(FPIndex);
808  } else {
809  FPOffset = getFramePointerSaveOffset();
810  }
811  }
812 
813  int BPOffset = 0;
814  if (HasBP) {
815  if (isSVR4ABI) {
816  MachineFrameInfo &MFI = MF.getFrameInfo();
817  int BPIndex = FI->getBasePointerSaveIndex();
818  assert(BPIndex && "No Base Pointer Save Slot!");
819  BPOffset = MFI.getObjectOffset(BPIndex);
820  } else {
821  BPOffset = getBasePointerSaveOffset();
822  }
823  }
824 
825  int PBPOffset = 0;
826  if (FI->usesPICBase()) {
827  MachineFrameInfo &MFI = MF.getFrameInfo();
828  int PBPIndex = FI->getPICBasePointerSaveIndex();
829  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
830  PBPOffset = MFI.getObjectOffset(PBPIndex);
831  }
832 
833  // Get stack alignments.
834  unsigned MaxAlign = MFI.getMaxAlignment();
835  if (HasBP && MaxAlign > 1)
836  assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
837  "Invalid alignment!");
838 
839  // Frames of 32KB & larger require special handling because they cannot be
840  // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
841  bool isLargeFrame = !isInt<16>(NegFrameSize);
842 
843  assert((isPPC64 || !MustSaveCR) &&
844  "Prologue CR saving supported only in 64-bit mode");
845 
846  // If we need to spill the CR and the LR but we don't have two separate
847  // registers available, we must spill them one at a time
848  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
849  // In the ELFv2 ABI, we are not required to save all CR fields.
850  // If only one or two CR fields are clobbered, it is more efficient to use
851  // mfocrf to selectively save just those fields, because mfocrf has short
852  // latency compares to mfcr.
853  unsigned MfcrOpcode = PPC::MFCR8;
854  unsigned CrState = RegState::ImplicitKill;
855  if (isELFv2ABI && MustSaveCRs.size() == 1) {
856  MfcrOpcode = PPC::MFOCRF8;
857  CrState = RegState::Kill;
858  }
859  MachineInstrBuilder MIB =
860  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
861  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
862  MIB.addReg(MustSaveCRs[i], CrState);
863  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
864  .addReg(TempReg, getKillRegState(true))
865  .addImm(8)
866  .addReg(SPReg);
867  }
868 
869  if (MustSaveLR)
870  BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
871 
872  if (MustSaveCR &&
873  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
874  // In the ELFv2 ABI, we are not required to save all CR fields.
875  // If only one or two CR fields are clobbered, it is more efficient to use
876  // mfocrf to selectively save just those fields, because mfocrf has short
877  // latency compares to mfcr.
878  unsigned MfcrOpcode = PPC::MFCR8;
879  unsigned CrState = RegState::ImplicitKill;
880  if (isELFv2ABI && MustSaveCRs.size() == 1) {
881  MfcrOpcode = PPC::MFOCRF8;
882  CrState = RegState::Kill;
883  }
884  MachineInstrBuilder MIB =
885  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
886  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
887  MIB.addReg(MustSaveCRs[i], CrState);
888  }
889 
890  if (HasRedZone) {
891  if (HasFP)
892  BuildMI(MBB, MBBI, dl, StoreInst)
893  .addReg(FPReg)
894  .addImm(FPOffset)
895  .addReg(SPReg);
896  if (FI->usesPICBase())
897  BuildMI(MBB, MBBI, dl, StoreInst)
898  .addReg(PPC::R30)
899  .addImm(PBPOffset)
900  .addReg(SPReg);
901  if (HasBP)
902  BuildMI(MBB, MBBI, dl, StoreInst)
903  .addReg(BPReg)
904  .addImm(BPOffset)
905  .addReg(SPReg);
906  }
907 
908  if (MustSaveLR)
909  BuildMI(MBB, MBBI, dl, StoreInst)
910  .addReg(ScratchReg, getKillRegState(true))
911  .addImm(LROffset)
912  .addReg(SPReg);
913 
914  if (MustSaveCR &&
915  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
916  assert(HasRedZone && "A red zone is always available on PPC64");
917  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
918  .addReg(TempReg, getKillRegState(true))
919  .addImm(8)
920  .addReg(SPReg);
921  }
922 
923  // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
924  if (!FrameSize)
925  return;
926 
927  // Adjust stack pointer: r1 += NegFrameSize.
928  // If there is a preferred stack alignment, align R1 now
929 
930  if (HasBP && HasRedZone) {
931  // Save a copy of r1 as the base pointer.
932  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
933  .addReg(SPReg)
934  .addReg(SPReg);
935  }
936 
937  // Have we generated a STUX instruction to claim stack frame? If so,
938  // the negated frame size will be placed in ScratchReg.
939  bool HasSTUX = false;
940 
941  // This condition must be kept in sync with canUseAsPrologue.
942  if (HasBP && MaxAlign > 1) {
943  if (isPPC64)
944  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
945  .addReg(SPReg)
946  .addImm(0)
947  .addImm(64 - Log2_32(MaxAlign));
948  else // PPC32...
949  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
950  .addReg(SPReg)
951  .addImm(0)
952  .addImm(32 - Log2_32(MaxAlign))
953  .addImm(31);
954  if (!isLargeFrame) {
955  BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
956  .addReg(ScratchReg, RegState::Kill)
957  .addImm(NegFrameSize);
958  } else {
959  assert(!SingleScratchReg && "Only a single scratch reg available");
960  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
961  .addImm(NegFrameSize >> 16);
962  BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
963  .addReg(TempReg, RegState::Kill)
964  .addImm(NegFrameSize & 0xFFFF);
965  BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
966  .addReg(ScratchReg, RegState::Kill)
967  .addReg(TempReg, RegState::Kill);
968  }
969 
970  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
971  .addReg(SPReg, RegState::Kill)
972  .addReg(SPReg)
973  .addReg(ScratchReg);
974  HasSTUX = true;
975 
976  } else if (!isLargeFrame) {
977  BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
978  .addReg(SPReg)
979  .addImm(NegFrameSize)
980  .addReg(SPReg);
981 
982  } else {
983  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
984  .addImm(NegFrameSize >> 16);
985  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
986  .addReg(ScratchReg, RegState::Kill)
987  .addImm(NegFrameSize & 0xFFFF);
988  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
989  .addReg(SPReg, RegState::Kill)
990  .addReg(SPReg)
991  .addReg(ScratchReg);
992  HasSTUX = true;
993  }
994 
995  if (!HasRedZone) {
996  assert(!isPPC64 && "A red zone is always available on PPC64");
997  if (HasSTUX) {
998  // The negated frame size is in ScratchReg, and the SPReg has been
999  // decremented by the frame size: SPReg = old SPReg + ScratchReg.
1000  // Since FPOffset, PBPOffset, etc. are relative to the beginning of
1001  // the stack frame (i.e. the old SP), ideally, we would put the old
1002  // SP into a register and use it as the base for the stores. The
1003  // problem is that the only available register may be ScratchReg,
1004  // which could be R0, and R0 cannot be used as a base address.
1005 
1006  // First, set ScratchReg to the old SP. This may need to be modified
1007  // later.
1008  BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1009  .addReg(ScratchReg, RegState::Kill)
1010  .addReg(SPReg);
1011 
1012  if (ScratchReg == PPC::R0) {
1013  // R0 cannot be used as a base register, but it can be used as an
1014  // index in a store-indexed.
1015  int LastOffset = 0;
1016  if (HasFP) {
1017  // R0 += (FPOffset-LastOffset).
1018  // Need addic, since addi treats R0 as 0.
1019  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1020  .addReg(ScratchReg)
1021  .addImm(FPOffset-LastOffset);
1022  LastOffset = FPOffset;
1023  // Store FP into *R0.
1024  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1025  .addReg(FPReg, RegState::Kill) // Save FP.
1026  .addReg(PPC::ZERO)
1027  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1028  }
1029  if (FI->usesPICBase()) {
1030  // R0 += (PBPOffset-LastOffset).
1031  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1032  .addReg(ScratchReg)
1033  .addImm(PBPOffset-LastOffset);
1034  LastOffset = PBPOffset;
1035  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1036  .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1037  .addReg(PPC::ZERO)
1038  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1039  }
1040  if (HasBP) {
1041  // R0 += (BPOffset-LastOffset).
1042  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1043  .addReg(ScratchReg)
1044  .addImm(BPOffset-LastOffset);
1045  LastOffset = BPOffset;
1046  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1047  .addReg(BPReg, RegState::Kill) // Save BP.
1048  .addReg(PPC::ZERO)
1049  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1050  // BP = R0-LastOffset
1051  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1052  .addReg(ScratchReg, RegState::Kill)
1053  .addImm(-LastOffset);
1054  }
1055  } else {
1056  // ScratchReg is not R0, so use it as the base register. It is
1057  // already set to the old SP, so we can use the offsets directly.
1058 
1059  // Now that the stack frame has been allocated, save all the necessary
1060  // registers using ScratchReg as the base address.
1061  if (HasFP)
1062  BuildMI(MBB, MBBI, dl, StoreInst)
1063  .addReg(FPReg)
1064  .addImm(FPOffset)
1065  .addReg(ScratchReg);
1066  if (FI->usesPICBase())
1067  BuildMI(MBB, MBBI, dl, StoreInst)
1068  .addReg(PPC::R30)
1069  .addImm(PBPOffset)
1070  .addReg(ScratchReg);
1071  if (HasBP) {
1072  BuildMI(MBB, MBBI, dl, StoreInst)
1073  .addReg(BPReg)
1074  .addImm(BPOffset)
1075  .addReg(ScratchReg);
1076  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1077  .addReg(ScratchReg, RegState::Kill)
1078  .addReg(ScratchReg);
1079  }
1080  }
1081  } else {
1082  // The frame size is a known 16-bit constant (fitting in the immediate
1083  // field of STWU). To be here we have to be compiling for PPC32.
1084  // Since the SPReg has been decreased by FrameSize, add it back to each
1085  // offset.
1086  if (HasFP)
1087  BuildMI(MBB, MBBI, dl, StoreInst)
1088  .addReg(FPReg)
1089  .addImm(FrameSize + FPOffset)
1090  .addReg(SPReg);
1091  if (FI->usesPICBase())
1092  BuildMI(MBB, MBBI, dl, StoreInst)
1093  .addReg(PPC::R30)
1094  .addImm(FrameSize + PBPOffset)
1095  .addReg(SPReg);
1096  if (HasBP) {
1097  BuildMI(MBB, MBBI, dl, StoreInst)
1098  .addReg(BPReg)
1099  .addImm(FrameSize + BPOffset)
1100  .addReg(SPReg);
1101  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1102  .addReg(SPReg)
1103  .addImm(FrameSize);
1104  }
1105  }
1106  }
1107 
1108  // Add Call Frame Information for the instructions we generated above.
1109  if (needsCFI) {
1110  unsigned CFIIndex;
1111 
1112  if (HasBP) {
1113  // Define CFA in terms of BP. Do this in preference to using FP/SP,
1114  // because if the stack needed aligning then CFA won't be at a fixed
1115  // offset from FP/SP.
1116  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1117  CFIIndex = MF.addFrameInst(
1119  } else {
1120  // Adjust the definition of CFA to account for the change in SP.
1121  assert(NegFrameSize);
1122  CFIIndex = MF.addFrameInst(
1123  MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
1124  }
1125  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1126  .addCFIIndex(CFIIndex);
1127 
1128  if (HasFP) {
1129  // Describe where FP was saved, at a fixed offset from CFA.
1130  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1131  CFIIndex = MF.addFrameInst(
1132  MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
1133  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1134  .addCFIIndex(CFIIndex);
1135  }
1136 
1137  if (FI->usesPICBase()) {
1138  // Describe where FP was saved, at a fixed offset from CFA.
1139  unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
1140  CFIIndex = MF.addFrameInst(
1141  MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
1142  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1143  .addCFIIndex(CFIIndex);
1144  }
1145 
1146  if (HasBP) {
1147  // Describe where BP was saved, at a fixed offset from CFA.
1148  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1149  CFIIndex = MF.addFrameInst(
1150  MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
1151  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1152  .addCFIIndex(CFIIndex);
1153  }
1154 
1155  if (MustSaveLR) {
1156  // Describe where LR was saved, at a fixed offset from CFA.
1157  unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1158  CFIIndex = MF.addFrameInst(
1159  MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
1160  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1161  .addCFIIndex(CFIIndex);
1162  }
1163  }
1164 
1165  // If there is a frame pointer, copy R1 into R31
1166  if (HasFP) {
1167  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1168  .addReg(SPReg)
1169  .addReg(SPReg);
1170 
1171  if (!HasBP && needsCFI) {
1172  // Change the definition of CFA from SP+offset to FP+offset, because SP
1173  // will change at every alloca.
1174  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1175  unsigned CFIIndex = MF.addFrameInst(
1177 
1178  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1179  .addCFIIndex(CFIIndex);
1180  }
1181  }
1182 
1183  if (needsCFI) {
1184  // Describe where callee saved registers were saved, at fixed offsets from
1185  // CFA.
1186  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1187  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1188  unsigned Reg = CSI[I].getReg();
1189  if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1190 
1191  // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
1192  // subregisters of CR2. We just need to emit a move of CR2.
1193  if (PPC::CRBITRCRegClass.contains(Reg))
1194  continue;
1195 
1196  // For SVR4, don't emit a move for the CR spill slot if we haven't
1197  // spilled CRs.
1198  if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1199  && !MustSaveCR)
1200  continue;
1201 
1202  // For 64-bit SVR4 when we have spilled CRs, the spill location
1203  // is SP+8, not a frame-relative slot.
1204  if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1205  // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1206  // the whole CR word. In the ELFv2 ABI, every CR that was
1207  // actually saved gets its own CFI record.
1208  unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1209  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1210  nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
1211  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1212  .addCFIIndex(CFIIndex);
1213  continue;
1214  }
1215 
1216  int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());
1217  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1218  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
1219  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1220  .addCFIIndex(CFIIndex);
1221  }
1222  }
1223 }
1224 
1226  MachineBasicBlock &MBB) const {
1228  DebugLoc dl;
1229 
1230  if (MBBI != MBB.end())
1231  dl = MBBI->getDebugLoc();
1232 
1233  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1234  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1235 
1236  // Get alignment info so we know how to restore the SP.
1237  const MachineFrameInfo &MFI = MF.getFrameInfo();
1238 
1239  // Get the number of bytes allocated from the FrameInfo.
1240  int FrameSize = MFI.getStackSize();
1241 
1242  // Get processor type.
1243  bool isPPC64 = Subtarget.isPPC64();
1244  // Get the ABI.
1245  bool isSVR4ABI = Subtarget.isSVR4ABI();
1246 
1247  // Check if the link register (LR) has been saved.
1249  bool MustSaveLR = FI->mustSaveLR();
1250  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1251  bool MustSaveCR = !MustSaveCRs.empty();
1252  // Do we have a frame pointer and/or base pointer for this function?
1253  bool HasFP = hasFP(MF);
1254  bool HasBP = RegInfo->hasBasePointer(MF);
1255  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1256 
1257  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1258  unsigned BPReg = RegInfo->getBaseRegister(MF);
1259  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1260  unsigned ScratchReg = 0;
1261  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1262  const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1263  : PPC::MTLR );
1264  const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1265  : PPC::LWZ );
1266  const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1267  : PPC::LIS );
1268  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1269  : PPC::OR );
1270  const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1271  : PPC::ORI );
1272  const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1273  : PPC::ADDI );
1274  const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1275  : PPC::ADD4 );
1276 
1277  int LROffset = getReturnSaveOffset();
1278 
1279  int FPOffset = 0;
1280 
1281  // Using the same bool variable as below to suppress compiler warnings.
1282  bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
1283  &TempReg);
1284  assert(SingleScratchReg &&
1285  "Could not find an available scratch register");
1286 
1287  SingleScratchReg = ScratchReg == TempReg;
1288 
1289  if (HasFP) {
1290  if (isSVR4ABI) {
1291  int FPIndex = FI->getFramePointerSaveIndex();
1292  assert(FPIndex && "No Frame Pointer Save Slot!");
1293  FPOffset = MFI.getObjectOffset(FPIndex);
1294  } else {
1295  FPOffset = getFramePointerSaveOffset();
1296  }
1297  }
1298 
1299  int BPOffset = 0;
1300  if (HasBP) {
1301  if (isSVR4ABI) {
1302  int BPIndex = FI->getBasePointerSaveIndex();
1303  assert(BPIndex && "No Base Pointer Save Slot!");
1304  BPOffset = MFI.getObjectOffset(BPIndex);
1305  } else {
1306  BPOffset = getBasePointerSaveOffset();
1307  }
1308  }
1309 
1310  int PBPOffset = 0;
1311  if (FI->usesPICBase()) {
1312  int PBPIndex = FI->getPICBasePointerSaveIndex();
1313  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1314  PBPOffset = MFI.getObjectOffset(PBPIndex);
1315  }
1316 
1317  bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1318 
1319  if (IsReturnBlock) {
1320  unsigned RetOpcode = MBBI->getOpcode();
1321  bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1322  RetOpcode == PPC::TCRETURNdi ||
1323  RetOpcode == PPC::TCRETURNai ||
1324  RetOpcode == PPC::TCRETURNri8 ||
1325  RetOpcode == PPC::TCRETURNdi8 ||
1326  RetOpcode == PPC::TCRETURNai8;
1327 
1328  if (UsesTCRet) {
1329  int MaxTCRetDelta = FI->getTailCallSPDelta();
1330  MachineOperand &StackAdjust = MBBI->getOperand(1);
1331  assert(StackAdjust.isImm() && "Expecting immediate value.");
1332  // Adjust stack pointer.
1333  int StackAdj = StackAdjust.getImm();
1334  int Delta = StackAdj - MaxTCRetDelta;
1335  assert((Delta >= 0) && "Delta must be positive");
1336  if (MaxTCRetDelta>0)
1337  FrameSize += (StackAdj +Delta);
1338  else
1339  FrameSize += StackAdj;
1340  }
1341  }
1342 
1343  // Frames of 32KB & larger require special handling because they cannot be
1344  // indexed into with a simple LD/LWZ immediate offset operand.
1345  bool isLargeFrame = !isInt<16>(FrameSize);
1346 
1347  // On targets without red zone, the SP needs to be restored last, so that
1348  // all live contents of the stack frame are upwards of the SP. This means
1349  // that we cannot restore SP just now, since there may be more registers
1350  // to restore from the stack frame (e.g. R31). If the frame size is not
1351  // a simple immediate value, we will need a spare register to hold the
1352  // restored SP. If the frame size is known and small, we can simply adjust
1353  // the offsets of the registers to be restored, and still use SP to restore
1354  // them. In such case, the final update of SP will be to add the frame
1355  // size to it.
1356  // To simplify the code, set RBReg to the base register used to restore
1357  // values from the stack, and set SPAdd to the value that needs to be added
1358  // to the SP at the end. The default values are as if red zone was present.
1359  unsigned RBReg = SPReg;
1360  unsigned SPAdd = 0;
1361 
1362  if (FrameSize) {
1363  // In the prologue, the loaded (or persistent) stack pointer value is
1364  // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
1365  // zone add this offset back now.
1366 
1367  // If this function contained a fastcc call and GuaranteedTailCallOpt is
1368  // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1369  // call which invalidates the stack pointer value in SP(0). So we use the
1370  // value of R31 in this case.
1371  if (FI->hasFastCall()) {
1372  assert(HasFP && "Expecting a valid frame pointer.");
1373  if (!HasRedZone)
1374  RBReg = FPReg;
1375  if (!isLargeFrame) {
1376  BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1377  .addReg(FPReg).addImm(FrameSize);
1378  } else {
1379  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1380  .addImm(FrameSize >> 16);
1381  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1382  .addReg(ScratchReg, RegState::Kill)
1383  .addImm(FrameSize & 0xFFFF);
1384  BuildMI(MBB, MBBI, dl, AddInst)
1385  .addReg(RBReg)
1386  .addReg(FPReg)
1387  .addReg(ScratchReg);
1388  }
1389  } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
1390  if (HasRedZone) {
1391  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1392  .addReg(SPReg)
1393  .addImm(FrameSize);
1394  } else {
1395  // Make sure that adding FrameSize will not overflow the max offset
1396  // size.
1397  assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1398  "Local offsets should be negative");
1399  SPAdd = FrameSize;
1400  FPOffset += FrameSize;
1401  BPOffset += FrameSize;
1402  PBPOffset += FrameSize;
1403  }
1404  } else {
1405  // We don't want to use ScratchReg as a base register, because it
1406  // could happen to be R0. Use FP instead, but make sure to preserve it.
1407  if (!HasRedZone) {
1408  // If FP is not saved, copy it to ScratchReg.
1409  if (!HasFP)
1410  BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1411  .addReg(FPReg)
1412  .addReg(FPReg);
1413  RBReg = FPReg;
1414  }
1415  BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
1416  .addImm(0)
1417  .addReg(SPReg);
1418  }
1419  }
1420  assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
1421  // If there is no red zone, ScratchReg may be needed for holding a useful
1422  // value (although not the base register). Make sure it is not overwritten
1423  // too early.
1424 
1425  assert((isPPC64 || !MustSaveCR) &&
1426  "Epilogue CR restoring supported only in 64-bit mode");
1427 
1428  // If we need to restore both the LR and the CR and we only have one
1429  // available scratch register, we must do them one at a time.
1430  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1431  // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
1432  // is live here.
1433  assert(HasRedZone && "Expecting red zone");
1434  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1435  .addImm(8)
1436  .addReg(SPReg);
1437  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1438  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1439  .addReg(TempReg, getKillRegState(i == e-1));
1440  }
1441 
1442  // Delay restoring of the LR if ScratchReg is needed. This is ok, since
1443  // LR is stored in the caller's stack frame. ScratchReg will be needed
1444  // if RBReg is anything other than SP. We shouldn't use ScratchReg as
1445  // a base register anyway, because it may happen to be R0.
1446  bool LoadedLR = false;
1447  if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1448  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1449  .addImm(LROffset+SPAdd)
1450  .addReg(RBReg);
1451  LoadedLR = true;
1452  }
1453 
1454  if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1455  // This will only occur for PPC64.
1456  assert(isPPC64 && "Expecting 64-bit mode");
1457  assert(RBReg == SPReg && "Should be using SP as a base register");
1458  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1459  .addImm(8)
1460  .addReg(RBReg);
1461  }
1462 
1463  if (HasFP) {
1464  // If there is red zone, restore FP directly, since SP has already been
1465  // restored. Otherwise, restore the value of FP into ScratchReg.
1466  if (HasRedZone || RBReg == SPReg)
1467  BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1468  .addImm(FPOffset)
1469  .addReg(SPReg);
1470  else
1471  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1472  .addImm(FPOffset)
1473  .addReg(RBReg);
1474  }
1475 
1476  if (FI->usesPICBase())
1477  BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)
1478  .addImm(PBPOffset)
1479  .addReg(RBReg);
1480 
1481  if (HasBP)
1482  BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1483  .addImm(BPOffset)
1484  .addReg(RBReg);
1485 
1486  // There is nothing more to be loaded from the stack, so now we can
1487  // restore SP: SP = RBReg + SPAdd.
1488  if (RBReg != SPReg || SPAdd != 0) {
1489  assert(!HasRedZone && "This should not happen with red zone");
1490  // If SPAdd is 0, generate a copy.
1491  if (SPAdd == 0)
1492  BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1493  .addReg(RBReg)
1494  .addReg(RBReg);
1495  else
1496  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1497  .addReg(RBReg)
1498  .addImm(SPAdd);
1499 
1500  assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
1501  if (RBReg == FPReg)
1502  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1503  .addReg(ScratchReg)
1504  .addReg(ScratchReg);
1505 
1506  // Now load the LR from the caller's stack frame.
1507  if (MustSaveLR && !LoadedLR)
1508  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1509  .addImm(LROffset)
1510  .addReg(SPReg);
1511  }
1512 
1513  if (MustSaveCR &&
1514  !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1515  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1516  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1517  .addReg(TempReg, getKillRegState(i == e-1));
1518 
1519  if (MustSaveLR)
1520  BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1521 
1522  // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1523  // call optimization
1524  if (IsReturnBlock) {
1525  unsigned RetOpcode = MBBI->getOpcode();
1527  (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1530  unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1531 
1532  if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1533  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1534  .addReg(SPReg).addImm(CallerAllocatedAmt);
1535  } else {
1536  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1537  .addImm(CallerAllocatedAmt >> 16);
1538  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1539  .addReg(ScratchReg, RegState::Kill)
1540  .addImm(CallerAllocatedAmt & 0xFFFF);
1541  BuildMI(MBB, MBBI, dl, AddInst)
1542  .addReg(SPReg)
1543  .addReg(FPReg)
1544  .addReg(ScratchReg);
1545  }
1546  } else {
1547  createTailCallBranchInstr(MBB);
1548  }
1549  }
1550 }
1551 
1552 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const {
1554 
1555  // If we got this far a first terminator should exist.
1556  assert(MBBI != MBB.end() && "Failed to find the first terminator.");
1557 
1558  DebugLoc dl = MBBI->getDebugLoc();
1559  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1560 
1561  // Create branch instruction for pseudo tail call return instruction
1562  unsigned RetOpcode = MBBI->getOpcode();
1563  if (RetOpcode == PPC::TCRETURNdi) {
1564  MBBI = MBB.getLastNonDebugInstr();
1565  MachineOperand &JumpTarget = MBBI->getOperand(0);
1566  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1567  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1568  } else if (RetOpcode == PPC::TCRETURNri) {
1569  MBBI = MBB.getLastNonDebugInstr();
1570  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1571  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1572  } else if (RetOpcode == PPC::TCRETURNai) {
1573  MBBI = MBB.getLastNonDebugInstr();
1574  MachineOperand &JumpTarget = MBBI->getOperand(0);
1575  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1576  } else if (RetOpcode == PPC::TCRETURNdi8) {
1577  MBBI = MBB.getLastNonDebugInstr();
1578  MachineOperand &JumpTarget = MBBI->getOperand(0);
1579  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1580  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1581  } else if (RetOpcode == PPC::TCRETURNri8) {
1582  MBBI = MBB.getLastNonDebugInstr();
1583  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1584  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1585  } else if (RetOpcode == PPC::TCRETURNai8) {
1586  MBBI = MBB.getLastNonDebugInstr();
1587  MachineOperand &JumpTarget = MBBI->getOperand(0);
1588  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1589  }
1590 }
1591 
1593  BitVector &SavedRegs,
1594  RegScavenger *RS) const {
1595  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1596 
1597  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1598 
1599  // Save and clear the LR state.
1601  unsigned LR = RegInfo->getRARegister();
1602  FI->setMustSaveLR(MustSaveLR(MF, LR));
1603  SavedRegs.reset(LR);
1604 
1605  // Save R31 if necessary
1606  int FPSI = FI->getFramePointerSaveIndex();
1607  bool isPPC64 = Subtarget.isPPC64();
1608  bool isDarwinABI = Subtarget.isDarwinABI();
1609  MachineFrameInfo &MFI = MF.getFrameInfo();
1610 
1611  // If the frame pointer save index hasn't been defined yet.
1612  if (!FPSI && needsFP(MF)) {
1613  // Find out what the fix offset of the frame pointer save area.
1614  int FPOffset = getFramePointerSaveOffset();
1615  // Allocate the frame index for frame pointer save area.
1616  FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1617  // Save the result.
1618  FI->setFramePointerSaveIndex(FPSI);
1619  }
1620 
1621  int BPSI = FI->getBasePointerSaveIndex();
1622  if (!BPSI && RegInfo->hasBasePointer(MF)) {
1623  int BPOffset = getBasePointerSaveOffset();
1624  // Allocate the frame index for the base pointer save area.
1625  BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1626  // Save the result.
1627  FI->setBasePointerSaveIndex(BPSI);
1628  }
1629 
1630  // Reserve stack space for the PIC Base register (R30).
1631  // Only used in SVR4 32-bit.
1632  if (FI->usesPICBase()) {
1633  int PBPSI = MFI.CreateFixedObject(4, -8, true);
1634  FI->setPICBasePointerSaveIndex(PBPSI);
1635  }
1636 
1637  // Make sure we don't explicitly spill r31, because, for example, we have
1638  // some inline asm which explicitly clobbers it, when we otherwise have a
1639  // frame pointer and are using r31's spill slot for the prologue/epilogue
1640  // code. Same goes for the base pointer and the PIC base register.
1641  if (needsFP(MF))
1642  SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
1643  if (RegInfo->hasBasePointer(MF))
1644  SavedRegs.reset(RegInfo->getBaseRegister(MF));
1645  if (FI->usesPICBase())
1646  SavedRegs.reset(PPC::R30);
1647 
1648  // Reserve stack space to move the linkage area to in case of a tail call.
1649  int TCSPDelta = 0;
1651  (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1652  MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1653  }
1654 
1655  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1656  // function uses CR 2, 3, or 4.
1657  if (!isPPC64 && !isDarwinABI &&
1658  (SavedRegs.test(PPC::CR2) ||
1659  SavedRegs.test(PPC::CR3) ||
1660  SavedRegs.test(PPC::CR4))) {
1661  int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1662  FI->setCRSpillFrameIndex(FrameIdx);
1663  }
1664 }
1665 
1667  RegScavenger *RS) const {
1668  // Early exit if not using the SVR4 ABI.
1669  if (!Subtarget.isSVR4ABI()) {
1670  addScavengingSpillSlot(MF, RS);
1671  return;
1672  }
1673 
1674  // Get callee saved register information.
1675  MachineFrameInfo &MFI = MF.getFrameInfo();
1676  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1677 
1678  // If the function is shrink-wrapped, and if the function has a tail call, the
1679  // tail call might not be in the new RestoreBlock, so real branch instruction
1680  // won't be generated by emitEpilogue(), because shrink-wrap has chosen new
1681  // RestoreBlock. So we handle this case here.
1682  if (MFI.getSavePoint() && MFI.hasTailCall()) {
1683  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
1684  for (MachineBasicBlock &MBB : MF) {
1685  if (MBB.isReturnBlock() && (&MBB) != RestoreBlock)
1686  createTailCallBranchInstr(MBB);
1687  }
1688  }
1689 
1690  // Early exit if no callee saved registers are modified!
1691  if (CSI.empty() && !needsFP(MF)) {
1692  addScavengingSpillSlot(MF, RS);
1693  return;
1694  }
1695 
1696  unsigned MinGPR = PPC::R31;
1697  unsigned MinG8R = PPC::X31;
1698  unsigned MinFPR = PPC::F31;
1699  unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
1700 
1701  bool HasGPSaveArea = false;
1702  bool HasG8SaveArea = false;
1703  bool HasFPSaveArea = false;
1704  bool HasVRSAVESaveArea = false;
1705  bool HasVRSaveArea = false;
1706 
1711 
1712  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1713  unsigned Reg = CSI[i].getReg();
1714  if (PPC::GPRCRegClass.contains(Reg) ||
1715  PPC::SPE4RCRegClass.contains(Reg)) {
1716  HasGPSaveArea = true;
1717 
1718  GPRegs.push_back(CSI[i]);
1719 
1720  if (Reg < MinGPR) {
1721  MinGPR = Reg;
1722  }
1723  } else if (PPC::G8RCRegClass.contains(Reg)) {
1724  HasG8SaveArea = true;
1725 
1726  G8Regs.push_back(CSI[i]);
1727 
1728  if (Reg < MinG8R) {
1729  MinG8R = Reg;
1730  }
1731  } else if (PPC::F8RCRegClass.contains(Reg)) {
1732  HasFPSaveArea = true;
1733 
1734  FPRegs.push_back(CSI[i]);
1735 
1736  if (Reg < MinFPR) {
1737  MinFPR = Reg;
1738  }
1739  } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1740  PPC::CRRCRegClass.contains(Reg)) {
1741  ; // do nothing, as we already know whether CRs are spilled
1742  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1743  HasVRSAVESaveArea = true;
1744  } else if (PPC::VRRCRegClass.contains(Reg) ||
1745  PPC::SPERCRegClass.contains(Reg)) {
1746  // Altivec and SPE are mutually exclusive, but have the same stack
1747  // alignment requirements, so overload the save area for both cases.
1748  HasVRSaveArea = true;
1749 
1750  VRegs.push_back(CSI[i]);
1751 
1752  if (Reg < MinVR) {
1753  MinVR = Reg;
1754  }
1755  } else {
1756  llvm_unreachable("Unknown RegisterClass!");
1757  }
1758  }
1759 
1761  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1762 
1763  int64_t LowerBound = 0;
1764 
1765  // Take into account stack space reserved for tail calls.
1766  int TCSPDelta = 0;
1768  (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1769  LowerBound = TCSPDelta;
1770  }
1771 
1772  // The Floating-point register save area is right below the back chain word
1773  // of the previous stack frame.
1774  if (HasFPSaveArea) {
1775  for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1776  int FI = FPRegs[i].getFrameIdx();
1777 
1778  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1779  }
1780 
1781  LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1782  }
1783 
1784  // Check whether the frame pointer register is allocated. If so, make sure it
1785  // is spilled to the correct offset.
1786  if (needsFP(MF)) {
1787  int FI = PFI->getFramePointerSaveIndex();
1788  assert(FI && "No Frame Pointer Save Slot!");
1789  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1790  // FP is R31/X31, so no need to update MinGPR/MinG8R.
1791  HasGPSaveArea = true;
1792  }
1793 
1794  if (PFI->usesPICBase()) {
1795  int FI = PFI->getPICBasePointerSaveIndex();
1796  assert(FI && "No PIC Base Pointer Save Slot!");
1797  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1798 
1799  MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
1800  HasGPSaveArea = true;
1801  }
1802 
1803  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1804  if (RegInfo->hasBasePointer(MF)) {
1805  int FI = PFI->getBasePointerSaveIndex();
1806  assert(FI && "No Base Pointer Save Slot!");
1807  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1808 
1809  unsigned BP = RegInfo->getBaseRegister(MF);
1810  if (PPC::G8RCRegClass.contains(BP)) {
1811  MinG8R = std::min<unsigned>(MinG8R, BP);
1812  HasG8SaveArea = true;
1813  } else if (PPC::GPRCRegClass.contains(BP)) {
1814  MinGPR = std::min<unsigned>(MinGPR, BP);
1815  HasGPSaveArea = true;
1816  }
1817  }
1818 
1819  // General register save area starts right below the Floating-point
1820  // register save area.
1821  if (HasGPSaveArea || HasG8SaveArea) {
1822  // Move general register save area spill slots down, taking into account
1823  // the size of the Floating-point register save area.
1824  for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1825  int FI = GPRegs[i].getFrameIdx();
1826 
1827  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1828  }
1829 
1830  // Move general register save area spill slots down, taking into account
1831  // the size of the Floating-point register save area.
1832  for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1833  int FI = G8Regs[i].getFrameIdx();
1834 
1835  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1836  }
1837 
1838  unsigned MinReg =
1839  std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1840  TRI->getEncodingValue(MinG8R));
1841 
1842  if (Subtarget.isPPC64()) {
1843  LowerBound -= (31 - MinReg + 1) * 8;
1844  } else {
1845  LowerBound -= (31 - MinReg + 1) * 4;
1846  }
1847  }
1848 
1849  // For 32-bit only, the CR save area is below the general register
1850  // save area. For 64-bit SVR4, the CR save area is addressed relative
1851  // to the stack pointer and hence does not need an adjustment here.
1852  // Only CR2 (the first nonvolatile spilled) has an associated frame
1853  // index so that we have a single uniform save area.
1854  if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1855  // Adjust the frame index of the CR spill slot.
1856  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1857  unsigned Reg = CSI[i].getReg();
1858 
1859  if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1860  // Leave Darwin logic as-is.
1861  || (!Subtarget.isSVR4ABI() &&
1862  (PPC::CRBITRCRegClass.contains(Reg) ||
1863  PPC::CRRCRegClass.contains(Reg)))) {
1864  int FI = CSI[i].getFrameIdx();
1865 
1866  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1867  }
1868  }
1869 
1870  LowerBound -= 4; // The CR save area is always 4 bytes long.
1871  }
1872 
1873  if (HasVRSAVESaveArea) {
1874  // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1875  // which have the VRSAVE register class?
1876  // Adjust the frame index of the VRSAVE spill slot.
1877  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1878  unsigned Reg = CSI[i].getReg();
1879 
1880  if (PPC::VRSAVERCRegClass.contains(Reg)) {
1881  int FI = CSI[i].getFrameIdx();
1882 
1883  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1884  }
1885  }
1886 
1887  LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1888  }
1889 
1890  // Both Altivec and SPE have the same alignment and padding requirements
1891  // within the stack frame.
1892  if (HasVRSaveArea) {
1893  // Insert alignment padding, we need 16-byte alignment. Note: for positive
1894  // number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since
1895  // we are using negative number here (the stack grows downward). We should
1896  // use formula : y = x & (~(n-1)). Where x is the size before aligning, n
1897  // is the alignment size ( n = 16 here) and y is the size after aligning.
1898  assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
1899  LowerBound &= ~(15);
1900 
1901  for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1902  int FI = VRegs[i].getFrameIdx();
1903 
1904  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1905  }
1906  }
1907 
1908  addScavengingSpillSlot(MF, RS);
1909 }
1910 
1911 void
1913  RegScavenger *RS) const {
1914  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1915  // a large stack, which will require scavenging a register to materialize a
1916  // large offset.
1917 
1918  // We need to have a scavenger spill slot for spills if the frame size is
1919  // large. In case there is no free register for large-offset addressing,
1920  // this slot is used for the necessary emergency spill. Also, we need the
1921  // slot for dynamic stack allocations.
1922 
1923  // The scavenger might be invoked if the frame offset does not fit into
1924  // the 16-bit immediate. We don't know the complete frame size here
1925  // because we've not yet computed callee-saved register spills or the
1926  // needed alignment padding.
1927  unsigned StackSize = determineFrameLayout(MF, false, true);
1928  MachineFrameInfo &MFI = MF.getFrameInfo();
1929  if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1930  hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1931  const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
1932  const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
1933  const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
1934  const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
1935  unsigned Size = TRI.getSpillSize(RC);
1936  unsigned Align = TRI.getSpillAlignment(RC);
1937  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1938 
1939  // Might we have over-aligned allocas?
1940  bool HasAlVars = MFI.hasVarSizedObjects() &&
1942 
1943  // These kinds of spills might need two registers.
1944  if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1945  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1946 
1947  }
1948 }
1949 
1950 bool
1953  const std::vector<CalleeSavedInfo> &CSI,
1954  const TargetRegisterInfo *TRI) const {
1955 
1956  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1957  // Return false otherwise to maintain pre-existing behavior.
1958  if (!Subtarget.isSVR4ABI())
1959  return false;
1960 
1961  MachineFunction *MF = MBB.getParent();
1962  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1963  DebugLoc DL;
1964  bool CRSpilled = false;
1965  MachineInstrBuilder CRMIB;
1966 
1967  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1968  unsigned Reg = CSI[i].getReg();
1969  // Only Darwin actually uses the VRSAVE register, but it can still appear
1970  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1971  // Darwin, ignore it.
1972  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1973  continue;
1974 
1975  // CR2 through CR4 are the nonvolatile CR fields.
1976  bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1977 
1978  // Add the callee-saved register as live-in; it's killed at the spill.
1979  // Do not do this for callee-saved registers that are live-in to the
1980  // function because they will already be marked live-in and this will be
1981  // adding it for a second time. It is an error to add the same register
1982  // to the set more than once.
1983  const MachineRegisterInfo &MRI = MF->getRegInfo();
1984  bool IsLiveIn = MRI.isLiveIn(Reg);
1985  if (!IsLiveIn)
1986  MBB.addLiveIn(Reg);
1987 
1988  if (CRSpilled && IsCRField) {
1989  CRMIB.addReg(Reg, RegState::ImplicitKill);
1990  continue;
1991  }
1992 
1993  // Insert the spill to the stack frame.
1994  if (IsCRField) {
1995  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1996  if (Subtarget.isPPC64()) {
1997  // The actual spill will happen at the start of the prologue.
1998  FuncInfo->addMustSaveCR(Reg);
1999  } else {
2000  CRSpilled = true;
2001  FuncInfo->setSpillsCR();
2002 
2003  // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
2004  // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
2005  CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
2006  .addReg(Reg, RegState::ImplicitKill);
2007 
2008  MBB.insert(MI, CRMIB);
2009  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
2010  .addReg(PPC::R12,
2011  getKillRegState(true)),
2012  CSI[i].getFrameIdx()));
2013  }
2014  } else {
2015  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2016  // Use !IsLiveIn for the kill flag.
2017  // We do not want to kill registers that are live in this function
2018  // before their use because they will become undefined registers.
2019  TII.storeRegToStackSlot(MBB, MI, Reg, !IsLiveIn,
2020  CSI[i].getFrameIdx(), RC, TRI);
2021  }
2022  }
2023  return true;
2024 }
2025 
2026 static void
2027 restoreCRs(bool isPPC64, bool is31,
2028  bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
2030  const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
2031 
2032  MachineFunction *MF = MBB.getParent();
2033  const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
2034  DebugLoc DL;
2035  unsigned RestoreOp, MoveReg;
2036 
2037  if (isPPC64)
2038  // This is handled during epilogue generation.
2039  return;
2040  else {
2041  // 32-bit: FP-relative
2042  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
2043  PPC::R12),
2044  CSI[CSIIndex].getFrameIdx()));
2045  RestoreOp = PPC::MTOCRF;
2046  MoveReg = PPC::R12;
2047  }
2048 
2049  if (CR2Spilled)
2050  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2051  .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2052 
2053  if (CR3Spilled)
2054  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2055  .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2056 
2057  if (CR4Spilled)
2058  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2059  .addReg(MoveReg, getKillRegState(true)));
2060 }
2061 
2065  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2067  I->getOpcode() == PPC::ADJCALLSTACKUP) {
2068  // Add (actually subtract) back the amount the callee popped on return.
2069  if (int CalleeAmt = I->getOperand(1).getImm()) {
2070  bool is64Bit = Subtarget.isPPC64();
2071  CalleeAmt *= -1;
2072  unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2073  unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2074  unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2075  unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2076  unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2077  unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2078  const DebugLoc &dl = I->getDebugLoc();
2079 
2080  if (isInt<16>(CalleeAmt)) {
2081  BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2082  .addReg(StackReg, RegState::Kill)
2083  .addImm(CalleeAmt);
2084  } else {
2086  BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2087  .addImm(CalleeAmt >> 16);
2088  BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2089  .addReg(TmpReg, RegState::Kill)
2090  .addImm(CalleeAmt & 0xFFFF);
2091  BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2092  .addReg(StackReg, RegState::Kill)
2093  .addReg(TmpReg);
2094  }
2095  }
2096  }
2097  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
2098  return MBB.erase(I);
2099 }
2100 
2101 bool
2104  std::vector<CalleeSavedInfo> &CSI,
2105  const TargetRegisterInfo *TRI) const {
2106 
2107  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
2108  // Return false otherwise to maintain pre-existing behavior.
2109  if (!Subtarget.isSVR4ABI())
2110  return false;
2111 
2112  MachineFunction *MF = MBB.getParent();
2113  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
2114  bool CR2Spilled = false;
2115  bool CR3Spilled = false;
2116  bool CR4Spilled = false;
2117  unsigned CSIIndex = 0;
2118 
2119  // Initialize insertion-point logic; we will be restoring in reverse
2120  // order of spill.
2121  MachineBasicBlock::iterator I = MI, BeforeI = I;
2122  bool AtStart = I == MBB.begin();
2123 
2124  if (!AtStart)
2125  --BeforeI;
2126 
2127  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2128  unsigned Reg = CSI[i].getReg();
2129 
2130  // Only Darwin actually uses the VRSAVE register, but it can still appear
2131  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
2132  // Darwin, ignore it.
2133  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
2134  continue;
2135 
2136  if (Reg == PPC::CR2) {
2137  CR2Spilled = true;
2138  // The spill slot is associated only with CR2, which is the
2139  // first nonvolatile spilled. Save it here.
2140  CSIIndex = i;
2141  continue;
2142  } else if (Reg == PPC::CR3) {
2143  CR3Spilled = true;
2144  continue;
2145  } else if (Reg == PPC::CR4) {
2146  CR4Spilled = true;
2147  continue;
2148  } else {
2149  // When we first encounter a non-CR register after seeing at
2150  // least one CR register, restore all spilled CRs together.
2151  if ((CR2Spilled || CR3Spilled || CR4Spilled)
2152  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2153  bool is31 = needsFP(*MF);
2154  restoreCRs(Subtarget.isPPC64(), is31,
2155  CR2Spilled, CR3Spilled, CR4Spilled,
2156  MBB, I, CSI, CSIIndex);
2157  CR2Spilled = CR3Spilled = CR4Spilled = false;
2158  }
2159 
2160  // Default behavior for non-CR saves.
2161  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2162  TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
2163  RC, TRI);
2164  assert(I != MBB.begin() &&
2165  "loadRegFromStackSlot didn't insert any code!");
2166  }
2167 
2168  // Insert in reverse order.
2169  if (AtStart)
2170  I = MBB.begin();
2171  else {
2172  I = BeforeI;
2173  ++I;
2174  }
2175  }
2176 
2177  // If we haven't yet spilled the CRs, do so now.
2178  if (CR2Spilled || CR3Spilled || CR4Spilled) {
2179  bool is31 = needsFP(*MF);
2180  restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
2181  MBB, I, CSI, CSIIndex);
2182  }
2183 
2184  return true;
2185 }
2186 
2189  return false;
2190  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
2191  MF.getSubtarget<PPCSubtarget>().isPPC64());
2192 }
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
static const unsigned GPRegs[]
bool hasDebugInfo() const
Returns true if valid debug info is present.
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addMustSaveCR(unsigned Reg)
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
unsigned Reg
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool test(unsigned Idx) const
Definition: BitVector.h:502
void setFramePointerSaveIndex(int Idx)
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:972
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static const MCPhysReg VRegs[32]
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
An instruction for reading from memory.
Definition: Instructions.h:168
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:474
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool hasSPE() const
Definition: PPCSubtarget.h:243
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
MachineBasicBlock * getRestorePoint() const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
def_iterator def_begin(unsigned RegNo) const
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool isELFv2ABI() const
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:192
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
Definition: Instructions.h:310
bool hasBasePointer(const MachineFunction &MF) const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getBaseRegister(const MachineFunction &MF) const
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
static const unsigned G8Regs[]
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:467
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
BitVector & reset()
Definition: BitVector.h:439
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
size_t size() const
Definition: SmallVector.h:53
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:189
Iterator for intrusive lists based on ilist_node.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:309
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:182
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:900
Information about stack frame layout on the target.
bool isDarwinABI() const
Definition: PPCSubtarget.h:309
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
static bool spillsVRSAVE(const MachineFunction &MF)
static bool hasSpills(const MachineFunction &MF)
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
unsigned getMinReservedArea() const
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:573
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
static bool spillsCR(const MachineFunction &MF)
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:283
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void setPICBasePointerSaveIndex(int Idx)
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:97
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
void setMaxCallFrameSize(unsigned S)
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool needsFP(const MachineFunction &MF) const
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
uint32_t Size
Definition: Profile.cpp:47
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock * getSavePoint() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:295
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:310
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
void replaceFPWithRealFP(MachineFunction &MF) const
This class contains meta information specific to a module.