LLVM  9.0.0svn
PPCFrameLowering.cpp
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1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PPC implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCFrameLowering.h"
14 #include "PPCInstrBuilder.h"
15 #include "PPCInstrInfo.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/Statistic.h"
26 #include "llvm/IR/Function.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "framelowering"
32 STATISTIC(NumNoNeedForFrame, "Number of functions without frames");
33 STATISTIC(NumPESpillVSR, "Number of spills to vector in prologue");
34 STATISTIC(NumPEReloadVSR, "Number of reloads from vector in epilogue");
35 
36 static cl::opt<bool>
37 EnablePEVectorSpills("ppc-enable-pe-vector-spills",
38  cl::desc("Enable spills in prologue to vector registers."),
39  cl::init(false), cl::Hidden);
40 
41 /// VRRegNo - Map from a numbered VR register to its enum value.
42 ///
43 static const MCPhysReg VRRegNo[] = {
44  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
45  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
46  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
47  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
48 };
49 
50 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
51  if (STI.isDarwinABI())
52  return STI.isPPC64() ? 16 : 8;
53  // SVR4 ABI:
54  return STI.isPPC64() ? 16 : 4;
55 }
56 
57 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
58  return STI.isELFv2ABI() ? 24 : 40;
59 }
60 
61 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
62  // For the Darwin ABI:
63  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
64  // for saving the frame pointer (if needed.) While the published ABI has
65  // not used this slot since at least MacOSX 10.2, there is older code
66  // around that does use it, and that needs to continue to work.
67  if (STI.isDarwinABI())
68  return STI.isPPC64() ? -8U : -4U;
69 
70  // SVR4 ABI: First slot in the general register save area.
71  return STI.isPPC64() ? -8U : -4U;
72 }
73 
74 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
75  if (STI.isDarwinABI() || STI.isPPC64())
76  return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
77 
78  // SVR4 ABI:
79  return 8;
80 }
81 
82 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
83  if (STI.isDarwinABI())
84  return STI.isPPC64() ? -16U : -8U;
85 
86  // SVR4 ABI: First slot in the general register save area.
87  return STI.isPPC64()
88  ? -16U
89  : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
90 }
91 
93  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
94  STI.getPlatformStackAlignment(), 0),
95  Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
96  TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
97  FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
98  LinkageSize(computeLinkageSize(Subtarget)),
99  BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
100 
101 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
103  unsigned &NumEntries) const {
104  if (Subtarget.isDarwinABI()) {
105  NumEntries = 1;
106  if (Subtarget.isPPC64()) {
107  static const SpillSlot darwin64Offsets = {PPC::X31, -8};
108  return &darwin64Offsets;
109  } else {
110  static const SpillSlot darwinOffsets = {PPC::R31, -4};
111  return &darwinOffsets;
112  }
113  }
114 
115  // Early exit if not using the SVR4 ABI.
116  if (!Subtarget.isSVR4ABI()) {
117  NumEntries = 0;
118  return nullptr;
119  }
120 
121  // Note that the offsets here overlap, but this is fixed up in
122  // processFunctionBeforeFrameFinalized.
123 
124  static const SpillSlot Offsets[] = {
125  // Floating-point register save area offsets.
126  {PPC::F31, -8},
127  {PPC::F30, -16},
128  {PPC::F29, -24},
129  {PPC::F28, -32},
130  {PPC::F27, -40},
131  {PPC::F26, -48},
132  {PPC::F25, -56},
133  {PPC::F24, -64},
134  {PPC::F23, -72},
135  {PPC::F22, -80},
136  {PPC::F21, -88},
137  {PPC::F20, -96},
138  {PPC::F19, -104},
139  {PPC::F18, -112},
140  {PPC::F17, -120},
141  {PPC::F16, -128},
142  {PPC::F15, -136},
143  {PPC::F14, -144},
144 
145  // General register save area offsets.
146  {PPC::R31, -4},
147  {PPC::R30, -8},
148  {PPC::R29, -12},
149  {PPC::R28, -16},
150  {PPC::R27, -20},
151  {PPC::R26, -24},
152  {PPC::R25, -28},
153  {PPC::R24, -32},
154  {PPC::R23, -36},
155  {PPC::R22, -40},
156  {PPC::R21, -44},
157  {PPC::R20, -48},
158  {PPC::R19, -52},
159  {PPC::R18, -56},
160  {PPC::R17, -60},
161  {PPC::R16, -64},
162  {PPC::R15, -68},
163  {PPC::R14, -72},
164 
165  // CR save area offset. We map each of the nonvolatile CR fields
166  // to the slot for CR2, which is the first of the nonvolatile CR
167  // fields to be assigned, so that we only allocate one save slot.
168  // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
169  {PPC::CR2, -4},
170 
171  // VRSAVE save area offset.
172  {PPC::VRSAVE, -4},
173 
174  // Vector register save area
175  {PPC::V31, -16},
176  {PPC::V30, -32},
177  {PPC::V29, -48},
178  {PPC::V28, -64},
179  {PPC::V27, -80},
180  {PPC::V26, -96},
181  {PPC::V25, -112},
182  {PPC::V24, -128},
183  {PPC::V23, -144},
184  {PPC::V22, -160},
185  {PPC::V21, -176},
186  {PPC::V20, -192},
187 
188  // SPE register save area (overlaps Vector save area).
189  {PPC::S31, -8},
190  {PPC::S30, -16},
191  {PPC::S29, -24},
192  {PPC::S28, -32},
193  {PPC::S27, -40},
194  {PPC::S26, -48},
195  {PPC::S25, -56},
196  {PPC::S24, -64},
197  {PPC::S23, -72},
198  {PPC::S22, -80},
199  {PPC::S21, -88},
200  {PPC::S20, -96},
201  {PPC::S19, -104},
202  {PPC::S18, -112},
203  {PPC::S17, -120},
204  {PPC::S16, -128},
205  {PPC::S15, -136},
206  {PPC::S14, -144}};
207 
208  static const SpillSlot Offsets64[] = {
209  // Floating-point register save area offsets.
210  {PPC::F31, -8},
211  {PPC::F30, -16},
212  {PPC::F29, -24},
213  {PPC::F28, -32},
214  {PPC::F27, -40},
215  {PPC::F26, -48},
216  {PPC::F25, -56},
217  {PPC::F24, -64},
218  {PPC::F23, -72},
219  {PPC::F22, -80},
220  {PPC::F21, -88},
221  {PPC::F20, -96},
222  {PPC::F19, -104},
223  {PPC::F18, -112},
224  {PPC::F17, -120},
225  {PPC::F16, -128},
226  {PPC::F15, -136},
227  {PPC::F14, -144},
228 
229  // General register save area offsets.
230  {PPC::X31, -8},
231  {PPC::X30, -16},
232  {PPC::X29, -24},
233  {PPC::X28, -32},
234  {PPC::X27, -40},
235  {PPC::X26, -48},
236  {PPC::X25, -56},
237  {PPC::X24, -64},
238  {PPC::X23, -72},
239  {PPC::X22, -80},
240  {PPC::X21, -88},
241  {PPC::X20, -96},
242  {PPC::X19, -104},
243  {PPC::X18, -112},
244  {PPC::X17, -120},
245  {PPC::X16, -128},
246  {PPC::X15, -136},
247  {PPC::X14, -144},
248 
249  // VRSAVE save area offset.
250  {PPC::VRSAVE, -4},
251 
252  // Vector register save area
253  {PPC::V31, -16},
254  {PPC::V30, -32},
255  {PPC::V29, -48},
256  {PPC::V28, -64},
257  {PPC::V27, -80},
258  {PPC::V26, -96},
259  {PPC::V25, -112},
260  {PPC::V24, -128},
261  {PPC::V23, -144},
262  {PPC::V22, -160},
263  {PPC::V21, -176},
264  {PPC::V20, -192}};
265 
266  if (Subtarget.isPPC64()) {
267  NumEntries = array_lengthof(Offsets64);
268 
269  return Offsets64;
270  } else {
271  NumEntries = array_lengthof(Offsets);
272 
273  return Offsets;
274  }
275 }
276 
277 /// RemoveVRSaveCode - We have found that this function does not need any code
278 /// to manipulate the VRSAVE register, even though it uses vector registers.
279 /// This can happen when the only registers used are known to be live in or out
280 /// of the function. Remove all of the VRSAVE related code from the function.
281 /// FIXME: The removal of the code results in a compile failure at -O0 when the
282 /// function contains a function call, as the GPR containing original VRSAVE
283 /// contents is spilled and reloaded around the call. Without the prolog code,
284 /// the spill instruction refers to an undefined register. This code needs
285 /// to account for all uses of that GPR.
287  MachineBasicBlock *Entry = MI.getParent();
288  MachineFunction *MF = Entry->getParent();
289 
290  // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
292  ++MBBI;
293  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
294  MBBI->eraseFromParent();
295 
296  bool RemovedAllMTVRSAVEs = true;
297  // See if we can find and remove the MTVRSAVE instruction from all of the
298  // epilog blocks.
299  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
300  // If last instruction is a return instruction, add an epilogue
301  if (I->isReturnBlock()) {
302  bool FoundIt = false;
303  for (MBBI = I->end(); MBBI != I->begin(); ) {
304  --MBBI;
305  if (MBBI->getOpcode() == PPC::MTVRSAVE) {
306  MBBI->eraseFromParent(); // remove it.
307  FoundIt = true;
308  break;
309  }
310  }
311  RemovedAllMTVRSAVEs &= FoundIt;
312  }
313  }
314 
315  // If we found and removed all MTVRSAVE instructions, remove the read of
316  // VRSAVE as well.
317  if (RemovedAllMTVRSAVEs) {
318  MBBI = MI;
319  assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
320  --MBBI;
321  assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
322  MBBI->eraseFromParent();
323  }
324 
325  // Finally, nuke the UPDATE_VRSAVE.
326  MI.eraseFromParent();
327 }
328 
329 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
330 // instruction selector. Based on the vector registers that have been used,
331 // transform this into the appropriate ORI instruction.
333  MachineFunction *MF = MI.getParent()->getParent();
335  DebugLoc dl = MI.getDebugLoc();
336 
337  const MachineRegisterInfo &MRI = MF->getRegInfo();
338  unsigned UsedRegMask = 0;
339  for (unsigned i = 0; i != 32; ++i)
340  if (MRI.isPhysRegModified(VRRegNo[i]))
341  UsedRegMask |= 1 << (31-i);
342 
343  // Live in and live out values already must be in the mask, so don't bother
344  // marking them.
345  for (std::pair<unsigned, unsigned> LI : MF->getRegInfo().liveins()) {
346  unsigned RegNo = TRI->getEncodingValue(LI.first);
347  if (VRRegNo[RegNo] == LI.first) // If this really is a vector reg.
348  UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
349  }
350 
351  // Live out registers appear as use operands on return instructions.
352  for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
353  UsedRegMask != 0 && BI != BE; ++BI) {
354  const MachineBasicBlock &MBB = *BI;
355  if (!MBB.isReturnBlock())
356  continue;
357  const MachineInstr &Ret = MBB.back();
358  for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
359  const MachineOperand &MO = Ret.getOperand(I);
360  if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
361  continue;
362  unsigned RegNo = TRI->getEncodingValue(MO.getReg());
363  UsedRegMask &= ~(1 << (31-RegNo));
364  }
365  }
366 
367  // If no registers are used, turn this into a copy.
368  if (UsedRegMask == 0) {
369  // Remove all VRSAVE code.
370  RemoveVRSaveCode(MI);
371  return;
372  }
373 
374  unsigned SrcReg = MI.getOperand(1).getReg();
375  unsigned DstReg = MI.getOperand(0).getReg();
376 
377  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
378  if (DstReg != SrcReg)
379  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
380  .addReg(SrcReg)
381  .addImm(UsedRegMask);
382  else
383  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
384  .addReg(SrcReg, RegState::Kill)
385  .addImm(UsedRegMask);
386  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
387  if (DstReg != SrcReg)
388  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
389  .addReg(SrcReg)
390  .addImm(UsedRegMask >> 16);
391  else
392  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
393  .addReg(SrcReg, RegState::Kill)
394  .addImm(UsedRegMask >> 16);
395  } else {
396  if (DstReg != SrcReg)
397  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
398  .addReg(SrcReg)
399  .addImm(UsedRegMask >> 16);
400  else
401  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
402  .addReg(SrcReg, RegState::Kill)
403  .addImm(UsedRegMask >> 16);
404 
405  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
406  .addReg(DstReg, RegState::Kill)
407  .addImm(UsedRegMask & 0xFFFF);
408  }
409 
410  // Remove the old UPDATE_VRSAVE instruction.
411  MI.eraseFromParent();
412 }
413 
414 static bool spillsCR(const MachineFunction &MF) {
415  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
416  return FuncInfo->isCRSpilled();
417 }
418 
419 static bool spillsVRSAVE(const MachineFunction &MF) {
420  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
421  return FuncInfo->isVRSAVESpilled();
422 }
423 
424 static bool hasSpills(const MachineFunction &MF) {
425  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
426  return FuncInfo->hasSpills();
427 }
428 
429 static bool hasNonRISpills(const MachineFunction &MF) {
430  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
431  return FuncInfo->hasNonRISpills();
432 }
433 
434 /// MustSaveLR - Return true if this function requires that we save the LR
435 /// register onto the stack in the prolog and restore it in the epilog of the
436 /// function.
437 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
438  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
439 
440  // We need a save/restore of LR if there is any def of LR (which is
441  // defined by calls, including the PIC setup sequence), or if there is
442  // some use of the LR stack slot (e.g. for builtin_return_address).
443  // (LR comes in 32 and 64 bit versions.)
445  return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
446 }
447 
448 /// determineFrameLayout - Determine the size of the frame and maximum call
449 /// frame size.
451  bool UpdateMF,
452  bool UseEstimate) const {
453  MachineFrameInfo &MFI = MF.getFrameInfo();
454 
455  // Get the number of bytes to allocate from the FrameInfo
456  unsigned FrameSize =
457  UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
458 
459  // Get stack alignments. The frame must be aligned to the greatest of these:
460  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
461  unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
462  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
463 
464  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
465 
466  unsigned LR = RegInfo->getRARegister();
467  bool DisableRedZone = MF.getFunction().hasFnAttribute(Attribute::NoRedZone);
468  bool CanUseRedZone = !MFI.hasVarSizedObjects() && // No dynamic alloca.
469  !MFI.adjustsStack() && // No calls.
470  !MustSaveLR(MF, LR) && // No need to save LR.
471  !RegInfo->hasBasePointer(MF); // No special alignment.
472 
473  // Note: for PPC32 SVR4ABI (Non-DarwinABI), we can still generate stackless
474  // code if all local vars are reg-allocated.
475  bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize();
476 
477  // Check whether we can skip adjusting the stack pointer (by using red zone)
478  if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
479  NumNoNeedForFrame++;
480  // No need for frame
481  if (UpdateMF)
482  MFI.setStackSize(0);
483  return 0;
484  }
485 
486  // Get the maximum call frame size of all the calls.
487  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
488 
489  // Maximum call frame needs to be at least big enough for linkage area.
490  unsigned minCallFrameSize = getLinkageSize();
491  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
492 
493  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
494  // that allocations will be aligned.
495  if (MFI.hasVarSizedObjects())
496  maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
497 
498  // Update maximum call frame size.
499  if (UpdateMF)
500  MFI.setMaxCallFrameSize(maxCallFrameSize);
501 
502  // Include call frame size in total.
503  FrameSize += maxCallFrameSize;
504 
505  // Make sure the frame is aligned.
506  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
507 
508  // Update frame info.
509  if (UpdateMF)
510  MFI.setStackSize(FrameSize);
511 
512  return FrameSize;
513 }
514 
515 // hasFP - Return true if the specified function actually has a dedicated frame
516 // pointer register.
518  const MachineFrameInfo &MFI = MF.getFrameInfo();
519  // FIXME: This is pretty much broken by design: hasFP() might be called really
520  // early, before the stack layout was calculated and thus hasFP() might return
521  // true or false here depending on the time of call.
522  return (MFI.getStackSize()) && needsFP(MF);
523 }
524 
525 // needsFP - Return true if the specified function should have a dedicated frame
526 // pointer register. This is true if the function has variable sized allocas or
527 // if frame pointer elimination is disabled.
529  const MachineFrameInfo &MFI = MF.getFrameInfo();
530 
531  // Naked functions have no stack frame pushed, so we don't have a frame
532  // pointer.
533  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
534  return false;
535 
536  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
537  MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint() ||
539  MF.getInfo<PPCFunctionInfo>()->hasFastCall());
540 }
541 
543  bool is31 = needsFP(MF);
544  unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
545  unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
546 
547  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
548  bool HasBP = RegInfo->hasBasePointer(MF);
549  unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
550  unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
551 
552  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
553  BI != BE; ++BI)
554  for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
555  --MBBI;
556  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
557  MachineOperand &MO = MBBI->getOperand(I);
558  if (!MO.isReg())
559  continue;
560 
561  switch (MO.getReg()) {
562  case PPC::FP:
563  MO.setReg(FPReg);
564  break;
565  case PPC::FP8:
566  MO.setReg(FP8Reg);
567  break;
568  case PPC::BP:
569  MO.setReg(BPReg);
570  break;
571  case PPC::BP8:
572  MO.setReg(BP8Reg);
573  break;
574 
575  }
576  }
577  }
578 }
579 
580 /* This function will do the following:
581  - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
582  respectively (defaults recommended by the ABI) and return true
583  - If MBB is not an entry block, initialize the register scavenger and look
584  for available registers.
585  - If the defaults (R0/R12) are available, return true
586  - If TwoUniqueRegsRequired is set to true, it looks for two unique
587  registers. Otherwise, look for a single available register.
588  - If the required registers are found, set SR1 and SR2 and return true.
589  - If the required registers are not found, set SR2 or both SR1 and SR2 to
590  PPC::NoRegister and return false.
591 
592  Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
593  is not set, this function will attempt to find two different registers, but
594  still return true if only one register is available (and set SR1 == SR2).
595 */
596 bool
597 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
598  bool UseAtEnd,
599  bool TwoUniqueRegsRequired,
600  unsigned *SR1,
601  unsigned *SR2) const {
602  RegScavenger RS;
603  unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
604  unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
605 
606  // Set the defaults for the two scratch registers.
607  if (SR1)
608  *SR1 = R0;
609 
610  if (SR2) {
611  assert (SR1 && "Asking for the second scratch register but not the first?");
612  *SR2 = R12;
613  }
614 
615  // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
616  if ((UseAtEnd && MBB->isReturnBlock()) ||
617  (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
618  return true;
619 
620  RS.enterBasicBlock(*MBB);
621 
622  if (UseAtEnd && !MBB->empty()) {
623  // The scratch register will be used at the end of the block, so must
624  // consider all registers used within the block
625 
627  // If no terminator, back iterator up to previous instruction.
628  if (MBBI == MBB->end())
629  MBBI = std::prev(MBBI);
630 
631  if (MBBI != MBB->begin())
632  RS.forward(MBBI);
633  }
634 
635  // If the two registers are available, we're all good.
636  // Note that we only return here if both R0 and R12 are available because
637  // although the function may not require two unique registers, it may benefit
638  // from having two so we should try to provide them.
639  if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
640  return true;
641 
642  // Get the list of callee-saved registers for the target.
643  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
644  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
645 
646  // Get all the available registers in the block.
647  BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
648  &PPC::GPRCRegClass);
649 
650  // We shouldn't use callee-saved registers as scratch registers as they may be
651  // available when looking for a candidate block for shrink wrapping but not
652  // available when the actual prologue/epilogue is being emitted because they
653  // were added as live-in to the prologue block by PrologueEpilogueInserter.
654  for (int i = 0; CSRegs[i]; ++i)
655  BV.reset(CSRegs[i]);
656 
657  // Set the first scratch register to the first available one.
658  if (SR1) {
659  int FirstScratchReg = BV.find_first();
660  *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
661  }
662 
663  // If there is another one available, set the second scratch register to that.
664  // Otherwise, set it to either PPC::NoRegister if this function requires two
665  // or to whatever SR1 is set to if this function doesn't require two.
666  if (SR2) {
667  int SecondScratchReg = BV.find_next(*SR1);
668  if (SecondScratchReg != -1)
669  *SR2 = SecondScratchReg;
670  else
671  *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
672  }
673 
674  // Now that we've done our best to provide both registers, double check
675  // whether we were unable to provide enough.
676  if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U))
677  return false;
678 
679  return true;
680 }
681 
682 // We need a scratch register for spilling LR and for spilling CR. By default,
683 // we use two scratch registers to hide latency. However, if only one scratch
684 // register is available, we can adjust for that by not overlapping the spill
685 // code. However, if we need to realign the stack (i.e. have a base pointer)
686 // and the stack frame is large, we need two scratch registers.
687 bool
688 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
689  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
690  MachineFunction &MF = *(MBB->getParent());
691  bool HasBP = RegInfo->hasBasePointer(MF);
692  unsigned FrameSize = determineFrameLayout(MF, false);
693  int NegFrameSize = -FrameSize;
694  bool IsLargeFrame = !isInt<16>(NegFrameSize);
695  MachineFrameInfo &MFI = MF.getFrameInfo();
696  unsigned MaxAlign = MFI.getMaxAlignment();
697  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
698 
699  return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
700 }
701 
703  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
704 
705  return findScratchRegister(TmpMBB, false,
706  twoUniqueScratchRegsRequired(TmpMBB));
707 }
708 
710  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
711 
712  return findScratchRegister(TmpMBB, true);
713 }
714 
716  MachineBasicBlock &MBB) const {
717  MachineBasicBlock::iterator MBBI = MBB.begin();
718  MachineFrameInfo &MFI = MF.getFrameInfo();
719  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
720  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
721 
722  MachineModuleInfo &MMI = MF.getMMI();
723  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
724  DebugLoc dl;
725  bool needsCFI = MMI.hasDebugInfo() ||
727 
728  // Get processor type.
729  bool isPPC64 = Subtarget.isPPC64();
730  // Get the ABI.
731  bool isSVR4ABI = Subtarget.isSVR4ABI();
732  bool isELFv2ABI = Subtarget.isELFv2ABI();
733  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
734  "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
735 
736  // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
737  // process it.
738  if (!isSVR4ABI)
739  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
740  if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
741  HandleVRSaveUpdate(*MBBI, TII);
742  break;
743  }
744  }
745 
746  // Move MBBI back to the beginning of the prologue block.
747  MBBI = MBB.begin();
748 
749  // Work out frame sizes.
750  unsigned FrameSize = determineFrameLayout(MF);
751  int NegFrameSize = -FrameSize;
752  if (!isInt<32>(NegFrameSize))
753  llvm_unreachable("Unhandled stack size!");
754 
755  if (MFI.isFrameAddressTaken())
757 
758  // Check if the link register (LR) must be saved.
760  bool MustSaveLR = FI->mustSaveLR();
761  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
762  bool MustSaveCR = !MustSaveCRs.empty();
763  // Do we have a frame pointer and/or base pointer for this function?
764  bool HasFP = hasFP(MF);
765  bool HasBP = RegInfo->hasBasePointer(MF);
766  bool HasRedZone = isPPC64 || !isSVR4ABI;
767 
768  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
769  unsigned BPReg = RegInfo->getBaseRegister(MF);
770  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
771  unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
772  unsigned ScratchReg = 0;
773  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
774  // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
775  const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
776  : PPC::MFLR );
777  const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
778  : PPC::STW );
779  const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
780  : PPC::STWU );
781  const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
782  : PPC::STWUX);
783  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
784  : PPC::LIS );
785  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
786  : PPC::ORI );
787  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
788  : PPC::OR );
789  const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
790  : PPC::SUBFC);
791  const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
792  : PPC::SUBFIC);
793 
794  // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
795  // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
796  // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
797  // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
798  assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
799  "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
800 
801  // Using the same bool variable as below to suppress compiler warnings.
802  bool SingleScratchReg =
803  findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
804  &ScratchReg, &TempReg);
805  assert(SingleScratchReg &&
806  "Required number of registers not available in this block");
807 
808  SingleScratchReg = ScratchReg == TempReg;
809 
810  int LROffset = getReturnSaveOffset();
811 
812  int FPOffset = 0;
813  if (HasFP) {
814  if (isSVR4ABI) {
815  MachineFrameInfo &MFI = MF.getFrameInfo();
816  int FPIndex = FI->getFramePointerSaveIndex();
817  assert(FPIndex && "No Frame Pointer Save Slot!");
818  FPOffset = MFI.getObjectOffset(FPIndex);
819  } else {
820  FPOffset = getFramePointerSaveOffset();
821  }
822  }
823 
824  int BPOffset = 0;
825  if (HasBP) {
826  if (isSVR4ABI) {
827  MachineFrameInfo &MFI = MF.getFrameInfo();
828  int BPIndex = FI->getBasePointerSaveIndex();
829  assert(BPIndex && "No Base Pointer Save Slot!");
830  BPOffset = MFI.getObjectOffset(BPIndex);
831  } else {
832  BPOffset = getBasePointerSaveOffset();
833  }
834  }
835 
836  int PBPOffset = 0;
837  if (FI->usesPICBase()) {
838  MachineFrameInfo &MFI = MF.getFrameInfo();
839  int PBPIndex = FI->getPICBasePointerSaveIndex();
840  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
841  PBPOffset = MFI.getObjectOffset(PBPIndex);
842  }
843 
844  // Get stack alignments.
845  unsigned MaxAlign = MFI.getMaxAlignment();
846  if (HasBP && MaxAlign > 1)
847  assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
848  "Invalid alignment!");
849 
850  // Frames of 32KB & larger require special handling because they cannot be
851  // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
852  bool isLargeFrame = !isInt<16>(NegFrameSize);
853 
854  assert((isPPC64 || !MustSaveCR) &&
855  "Prologue CR saving supported only in 64-bit mode");
856 
857  // If we need to spill the CR and the LR but we don't have two separate
858  // registers available, we must spill them one at a time
859  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
860  // In the ELFv2 ABI, we are not required to save all CR fields.
861  // If only one or two CR fields are clobbered, it is more efficient to use
862  // mfocrf to selectively save just those fields, because mfocrf has short
863  // latency compares to mfcr.
864  unsigned MfcrOpcode = PPC::MFCR8;
865  unsigned CrState = RegState::ImplicitKill;
866  if (isELFv2ABI && MustSaveCRs.size() == 1) {
867  MfcrOpcode = PPC::MFOCRF8;
868  CrState = RegState::Kill;
869  }
870  MachineInstrBuilder MIB =
871  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
872  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
873  MIB.addReg(MustSaveCRs[i], CrState);
874  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
875  .addReg(TempReg, getKillRegState(true))
876  .addImm(8)
877  .addReg(SPReg);
878  }
879 
880  if (MustSaveLR)
881  BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
882 
883  if (MustSaveCR &&
884  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
885  // In the ELFv2 ABI, we are not required to save all CR fields.
886  // If only one or two CR fields are clobbered, it is more efficient to use
887  // mfocrf to selectively save just those fields, because mfocrf has short
888  // latency compares to mfcr.
889  unsigned MfcrOpcode = PPC::MFCR8;
890  unsigned CrState = RegState::ImplicitKill;
891  if (isELFv2ABI && MustSaveCRs.size() == 1) {
892  MfcrOpcode = PPC::MFOCRF8;
893  CrState = RegState::Kill;
894  }
895  MachineInstrBuilder MIB =
896  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
897  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
898  MIB.addReg(MustSaveCRs[i], CrState);
899  }
900 
901  if (HasRedZone) {
902  if (HasFP)
903  BuildMI(MBB, MBBI, dl, StoreInst)
904  .addReg(FPReg)
905  .addImm(FPOffset)
906  .addReg(SPReg);
907  if (FI->usesPICBase())
908  BuildMI(MBB, MBBI, dl, StoreInst)
909  .addReg(PPC::R30)
910  .addImm(PBPOffset)
911  .addReg(SPReg);
912  if (HasBP)
913  BuildMI(MBB, MBBI, dl, StoreInst)
914  .addReg(BPReg)
915  .addImm(BPOffset)
916  .addReg(SPReg);
917  }
918 
919  if (MustSaveLR)
920  BuildMI(MBB, MBBI, dl, StoreInst)
921  .addReg(ScratchReg, getKillRegState(true))
922  .addImm(LROffset)
923  .addReg(SPReg);
924 
925  if (MustSaveCR &&
926  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
927  assert(HasRedZone && "A red zone is always available on PPC64");
928  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
929  .addReg(TempReg, getKillRegState(true))
930  .addImm(8)
931  .addReg(SPReg);
932  }
933 
934  // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
935  if (!FrameSize)
936  return;
937 
938  // Adjust stack pointer: r1 += NegFrameSize.
939  // If there is a preferred stack alignment, align R1 now
940 
941  if (HasBP && HasRedZone) {
942  // Save a copy of r1 as the base pointer.
943  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
944  .addReg(SPReg)
945  .addReg(SPReg);
946  }
947 
948  // Have we generated a STUX instruction to claim stack frame? If so,
949  // the negated frame size will be placed in ScratchReg.
950  bool HasSTUX = false;
951 
952  // This condition must be kept in sync with canUseAsPrologue.
953  if (HasBP && MaxAlign > 1) {
954  if (isPPC64)
955  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
956  .addReg(SPReg)
957  .addImm(0)
958  .addImm(64 - Log2_32(MaxAlign));
959  else // PPC32...
960  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
961  .addReg(SPReg)
962  .addImm(0)
963  .addImm(32 - Log2_32(MaxAlign))
964  .addImm(31);
965  if (!isLargeFrame) {
966  BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
967  .addReg(ScratchReg, RegState::Kill)
968  .addImm(NegFrameSize);
969  } else {
970  assert(!SingleScratchReg && "Only a single scratch reg available");
971  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
972  .addImm(NegFrameSize >> 16);
973  BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
974  .addReg(TempReg, RegState::Kill)
975  .addImm(NegFrameSize & 0xFFFF);
976  BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
977  .addReg(ScratchReg, RegState::Kill)
978  .addReg(TempReg, RegState::Kill);
979  }
980 
981  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
982  .addReg(SPReg, RegState::Kill)
983  .addReg(SPReg)
984  .addReg(ScratchReg);
985  HasSTUX = true;
986 
987  } else if (!isLargeFrame) {
988  BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
989  .addReg(SPReg)
990  .addImm(NegFrameSize)
991  .addReg(SPReg);
992 
993  } else {
994  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
995  .addImm(NegFrameSize >> 16);
996  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
997  .addReg(ScratchReg, RegState::Kill)
998  .addImm(NegFrameSize & 0xFFFF);
999  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
1000  .addReg(SPReg, RegState::Kill)
1001  .addReg(SPReg)
1002  .addReg(ScratchReg);
1003  HasSTUX = true;
1004  }
1005 
1006  if (!HasRedZone) {
1007  assert(!isPPC64 && "A red zone is always available on PPC64");
1008  if (HasSTUX) {
1009  // The negated frame size is in ScratchReg, and the SPReg has been
1010  // decremented by the frame size: SPReg = old SPReg + ScratchReg.
1011  // Since FPOffset, PBPOffset, etc. are relative to the beginning of
1012  // the stack frame (i.e. the old SP), ideally, we would put the old
1013  // SP into a register and use it as the base for the stores. The
1014  // problem is that the only available register may be ScratchReg,
1015  // which could be R0, and R0 cannot be used as a base address.
1016 
1017  // First, set ScratchReg to the old SP. This may need to be modified
1018  // later.
1019  BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1020  .addReg(ScratchReg, RegState::Kill)
1021  .addReg(SPReg);
1022 
1023  if (ScratchReg == PPC::R0) {
1024  // R0 cannot be used as a base register, but it can be used as an
1025  // index in a store-indexed.
1026  int LastOffset = 0;
1027  if (HasFP) {
1028  // R0 += (FPOffset-LastOffset).
1029  // Need addic, since addi treats R0 as 0.
1030  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1031  .addReg(ScratchReg)
1032  .addImm(FPOffset-LastOffset);
1033  LastOffset = FPOffset;
1034  // Store FP into *R0.
1035  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1036  .addReg(FPReg, RegState::Kill) // Save FP.
1037  .addReg(PPC::ZERO)
1038  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1039  }
1040  if (FI->usesPICBase()) {
1041  // R0 += (PBPOffset-LastOffset).
1042  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1043  .addReg(ScratchReg)
1044  .addImm(PBPOffset-LastOffset);
1045  LastOffset = PBPOffset;
1046  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1047  .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1048  .addReg(PPC::ZERO)
1049  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1050  }
1051  if (HasBP) {
1052  // R0 += (BPOffset-LastOffset).
1053  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1054  .addReg(ScratchReg)
1055  .addImm(BPOffset-LastOffset);
1056  LastOffset = BPOffset;
1057  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1058  .addReg(BPReg, RegState::Kill) // Save BP.
1059  .addReg(PPC::ZERO)
1060  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1061  // BP = R0-LastOffset
1062  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1063  .addReg(ScratchReg, RegState::Kill)
1064  .addImm(-LastOffset);
1065  }
1066  } else {
1067  // ScratchReg is not R0, so use it as the base register. It is
1068  // already set to the old SP, so we can use the offsets directly.
1069 
1070  // Now that the stack frame has been allocated, save all the necessary
1071  // registers using ScratchReg as the base address.
1072  if (HasFP)
1073  BuildMI(MBB, MBBI, dl, StoreInst)
1074  .addReg(FPReg)
1075  .addImm(FPOffset)
1076  .addReg(ScratchReg);
1077  if (FI->usesPICBase())
1078  BuildMI(MBB, MBBI, dl, StoreInst)
1079  .addReg(PPC::R30)
1080  .addImm(PBPOffset)
1081  .addReg(ScratchReg);
1082  if (HasBP) {
1083  BuildMI(MBB, MBBI, dl, StoreInst)
1084  .addReg(BPReg)
1085  .addImm(BPOffset)
1086  .addReg(ScratchReg);
1087  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1088  .addReg(ScratchReg, RegState::Kill)
1089  .addReg(ScratchReg);
1090  }
1091  }
1092  } else {
1093  // The frame size is a known 16-bit constant (fitting in the immediate
1094  // field of STWU). To be here we have to be compiling for PPC32.
1095  // Since the SPReg has been decreased by FrameSize, add it back to each
1096  // offset.
1097  if (HasFP)
1098  BuildMI(MBB, MBBI, dl, StoreInst)
1099  .addReg(FPReg)
1100  .addImm(FrameSize + FPOffset)
1101  .addReg(SPReg);
1102  if (FI->usesPICBase())
1103  BuildMI(MBB, MBBI, dl, StoreInst)
1104  .addReg(PPC::R30)
1105  .addImm(FrameSize + PBPOffset)
1106  .addReg(SPReg);
1107  if (HasBP) {
1108  BuildMI(MBB, MBBI, dl, StoreInst)
1109  .addReg(BPReg)
1110  .addImm(FrameSize + BPOffset)
1111  .addReg(SPReg);
1112  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1113  .addReg(SPReg)
1114  .addImm(FrameSize);
1115  }
1116  }
1117  }
1118 
1119  // Add Call Frame Information for the instructions we generated above.
1120  if (needsCFI) {
1121  unsigned CFIIndex;
1122 
1123  if (HasBP) {
1124  // Define CFA in terms of BP. Do this in preference to using FP/SP,
1125  // because if the stack needed aligning then CFA won't be at a fixed
1126  // offset from FP/SP.
1127  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1128  CFIIndex = MF.addFrameInst(
1130  } else {
1131  // Adjust the definition of CFA to account for the change in SP.
1132  assert(NegFrameSize);
1133  CFIIndex = MF.addFrameInst(
1134  MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
1135  }
1136  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1137  .addCFIIndex(CFIIndex);
1138 
1139  if (HasFP) {
1140  // Describe where FP was saved, at a fixed offset from CFA.
1141  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1142  CFIIndex = MF.addFrameInst(
1143  MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
1144  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1145  .addCFIIndex(CFIIndex);
1146  }
1147 
1148  if (FI->usesPICBase()) {
1149  // Describe where FP was saved, at a fixed offset from CFA.
1150  unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
1151  CFIIndex = MF.addFrameInst(
1152  MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
1153  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1154  .addCFIIndex(CFIIndex);
1155  }
1156 
1157  if (HasBP) {
1158  // Describe where BP was saved, at a fixed offset from CFA.
1159  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1160  CFIIndex = MF.addFrameInst(
1161  MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
1162  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1163  .addCFIIndex(CFIIndex);
1164  }
1165 
1166  if (MustSaveLR) {
1167  // Describe where LR was saved, at a fixed offset from CFA.
1168  unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1169  CFIIndex = MF.addFrameInst(
1170  MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
1171  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1172  .addCFIIndex(CFIIndex);
1173  }
1174  }
1175 
1176  // If there is a frame pointer, copy R1 into R31
1177  if (HasFP) {
1178  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1179  .addReg(SPReg)
1180  .addReg(SPReg);
1181 
1182  if (!HasBP && needsCFI) {
1183  // Change the definition of CFA from SP+offset to FP+offset, because SP
1184  // will change at every alloca.
1185  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1186  unsigned CFIIndex = MF.addFrameInst(
1188 
1189  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1190  .addCFIIndex(CFIIndex);
1191  }
1192  }
1193 
1194  if (needsCFI) {
1195  // Describe where callee saved registers were saved, at fixed offsets from
1196  // CFA.
1197  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1198  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1199  unsigned Reg = CSI[I].getReg();
1200  if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1201 
1202  // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
1203  // subregisters of CR2. We just need to emit a move of CR2.
1204  if (PPC::CRBITRCRegClass.contains(Reg))
1205  continue;
1206 
1207  // For SVR4, don't emit a move for the CR spill slot if we haven't
1208  // spilled CRs.
1209  if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1210  && !MustSaveCR)
1211  continue;
1212 
1213  // For 64-bit SVR4 when we have spilled CRs, the spill location
1214  // is SP+8, not a frame-relative slot.
1215  if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1216  // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1217  // the whole CR word. In the ELFv2 ABI, every CR that was
1218  // actually saved gets its own CFI record.
1219  unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1220  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1221  nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
1222  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1223  .addCFIIndex(CFIIndex);
1224  continue;
1225  }
1226 
1227  if (CSI[I].isSpilledToReg()) {
1228  unsigned SpilledReg = CSI[I].getDstReg();
1229  unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister(
1230  nullptr, MRI->getDwarfRegNum(Reg, true),
1231  MRI->getDwarfRegNum(SpilledReg, true)));
1232  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1233  .addCFIIndex(CFIRegister);
1234  } else {
1235  int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());
1236  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1237  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
1238  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1239  .addCFIIndex(CFIIndex);
1240  }
1241  }
1242  }
1243 }
1244 
1246  MachineBasicBlock &MBB) const {
1248  DebugLoc dl;
1249 
1250  if (MBBI != MBB.end())
1251  dl = MBBI->getDebugLoc();
1252 
1253  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1254  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1255 
1256  // Get alignment info so we know how to restore the SP.
1257  const MachineFrameInfo &MFI = MF.getFrameInfo();
1258 
1259  // Get the number of bytes allocated from the FrameInfo.
1260  int FrameSize = MFI.getStackSize();
1261 
1262  // Get processor type.
1263  bool isPPC64 = Subtarget.isPPC64();
1264  // Get the ABI.
1265  bool isSVR4ABI = Subtarget.isSVR4ABI();
1266 
1267  // Check if the link register (LR) has been saved.
1269  bool MustSaveLR = FI->mustSaveLR();
1270  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1271  bool MustSaveCR = !MustSaveCRs.empty();
1272  // Do we have a frame pointer and/or base pointer for this function?
1273  bool HasFP = hasFP(MF);
1274  bool HasBP = RegInfo->hasBasePointer(MF);
1275  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1276 
1277  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1278  unsigned BPReg = RegInfo->getBaseRegister(MF);
1279  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1280  unsigned ScratchReg = 0;
1281  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1282  const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1283  : PPC::MTLR );
1284  const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1285  : PPC::LWZ );
1286  const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1287  : PPC::LIS );
1288  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1289  : PPC::OR );
1290  const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1291  : PPC::ORI );
1292  const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1293  : PPC::ADDI );
1294  const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1295  : PPC::ADD4 );
1296 
1297  int LROffset = getReturnSaveOffset();
1298 
1299  int FPOffset = 0;
1300 
1301  // Using the same bool variable as below to suppress compiler warnings.
1302  bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
1303  &TempReg);
1304  assert(SingleScratchReg &&
1305  "Could not find an available scratch register");
1306 
1307  SingleScratchReg = ScratchReg == TempReg;
1308 
1309  if (HasFP) {
1310  if (isSVR4ABI) {
1311  int FPIndex = FI->getFramePointerSaveIndex();
1312  assert(FPIndex && "No Frame Pointer Save Slot!");
1313  FPOffset = MFI.getObjectOffset(FPIndex);
1314  } else {
1315  FPOffset = getFramePointerSaveOffset();
1316  }
1317  }
1318 
1319  int BPOffset = 0;
1320  if (HasBP) {
1321  if (isSVR4ABI) {
1322  int BPIndex = FI->getBasePointerSaveIndex();
1323  assert(BPIndex && "No Base Pointer Save Slot!");
1324  BPOffset = MFI.getObjectOffset(BPIndex);
1325  } else {
1326  BPOffset = getBasePointerSaveOffset();
1327  }
1328  }
1329 
1330  int PBPOffset = 0;
1331  if (FI->usesPICBase()) {
1332  int PBPIndex = FI->getPICBasePointerSaveIndex();
1333  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1334  PBPOffset = MFI.getObjectOffset(PBPIndex);
1335  }
1336 
1337  bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1338 
1339  if (IsReturnBlock) {
1340  unsigned RetOpcode = MBBI->getOpcode();
1341  bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1342  RetOpcode == PPC::TCRETURNdi ||
1343  RetOpcode == PPC::TCRETURNai ||
1344  RetOpcode == PPC::TCRETURNri8 ||
1345  RetOpcode == PPC::TCRETURNdi8 ||
1346  RetOpcode == PPC::TCRETURNai8;
1347 
1348  if (UsesTCRet) {
1349  int MaxTCRetDelta = FI->getTailCallSPDelta();
1350  MachineOperand &StackAdjust = MBBI->getOperand(1);
1351  assert(StackAdjust.isImm() && "Expecting immediate value.");
1352  // Adjust stack pointer.
1353  int StackAdj = StackAdjust.getImm();
1354  int Delta = StackAdj - MaxTCRetDelta;
1355  assert((Delta >= 0) && "Delta must be positive");
1356  if (MaxTCRetDelta>0)
1357  FrameSize += (StackAdj +Delta);
1358  else
1359  FrameSize += StackAdj;
1360  }
1361  }
1362 
1363  // Frames of 32KB & larger require special handling because they cannot be
1364  // indexed into with a simple LD/LWZ immediate offset operand.
1365  bool isLargeFrame = !isInt<16>(FrameSize);
1366 
1367  // On targets without red zone, the SP needs to be restored last, so that
1368  // all live contents of the stack frame are upwards of the SP. This means
1369  // that we cannot restore SP just now, since there may be more registers
1370  // to restore from the stack frame (e.g. R31). If the frame size is not
1371  // a simple immediate value, we will need a spare register to hold the
1372  // restored SP. If the frame size is known and small, we can simply adjust
1373  // the offsets of the registers to be restored, and still use SP to restore
1374  // them. In such case, the final update of SP will be to add the frame
1375  // size to it.
1376  // To simplify the code, set RBReg to the base register used to restore
1377  // values from the stack, and set SPAdd to the value that needs to be added
1378  // to the SP at the end. The default values are as if red zone was present.
1379  unsigned RBReg = SPReg;
1380  unsigned SPAdd = 0;
1381 
1382  if (FrameSize) {
1383  // In the prologue, the loaded (or persistent) stack pointer value is
1384  // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
1385  // zone add this offset back now.
1386 
1387  // If this function contained a fastcc call and GuaranteedTailCallOpt is
1388  // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1389  // call which invalidates the stack pointer value in SP(0). So we use the
1390  // value of R31 in this case.
1391  if (FI->hasFastCall()) {
1392  assert(HasFP && "Expecting a valid frame pointer.");
1393  if (!HasRedZone)
1394  RBReg = FPReg;
1395  if (!isLargeFrame) {
1396  BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1397  .addReg(FPReg).addImm(FrameSize);
1398  } else {
1399  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1400  .addImm(FrameSize >> 16);
1401  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1402  .addReg(ScratchReg, RegState::Kill)
1403  .addImm(FrameSize & 0xFFFF);
1404  BuildMI(MBB, MBBI, dl, AddInst)
1405  .addReg(RBReg)
1406  .addReg(FPReg)
1407  .addReg(ScratchReg);
1408  }
1409  } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
1410  if (HasRedZone) {
1411  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1412  .addReg(SPReg)
1413  .addImm(FrameSize);
1414  } else {
1415  // Make sure that adding FrameSize will not overflow the max offset
1416  // size.
1417  assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1418  "Local offsets should be negative");
1419  SPAdd = FrameSize;
1420  FPOffset += FrameSize;
1421  BPOffset += FrameSize;
1422  PBPOffset += FrameSize;
1423  }
1424  } else {
1425  // We don't want to use ScratchReg as a base register, because it
1426  // could happen to be R0. Use FP instead, but make sure to preserve it.
1427  if (!HasRedZone) {
1428  // If FP is not saved, copy it to ScratchReg.
1429  if (!HasFP)
1430  BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1431  .addReg(FPReg)
1432  .addReg(FPReg);
1433  RBReg = FPReg;
1434  }
1435  BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
1436  .addImm(0)
1437  .addReg(SPReg);
1438  }
1439  }
1440  assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
1441  // If there is no red zone, ScratchReg may be needed for holding a useful
1442  // value (although not the base register). Make sure it is not overwritten
1443  // too early.
1444 
1445  assert((isPPC64 || !MustSaveCR) &&
1446  "Epilogue CR restoring supported only in 64-bit mode");
1447 
1448  // If we need to restore both the LR and the CR and we only have one
1449  // available scratch register, we must do them one at a time.
1450  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1451  // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
1452  // is live here.
1453  assert(HasRedZone && "Expecting red zone");
1454  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1455  .addImm(8)
1456  .addReg(SPReg);
1457  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1458  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1459  .addReg(TempReg, getKillRegState(i == e-1));
1460  }
1461 
1462  // Delay restoring of the LR if ScratchReg is needed. This is ok, since
1463  // LR is stored in the caller's stack frame. ScratchReg will be needed
1464  // if RBReg is anything other than SP. We shouldn't use ScratchReg as
1465  // a base register anyway, because it may happen to be R0.
1466  bool LoadedLR = false;
1467  if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1468  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1469  .addImm(LROffset+SPAdd)
1470  .addReg(RBReg);
1471  LoadedLR = true;
1472  }
1473 
1474  if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1475  // This will only occur for PPC64.
1476  assert(isPPC64 && "Expecting 64-bit mode");
1477  assert(RBReg == SPReg && "Should be using SP as a base register");
1478  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1479  .addImm(8)
1480  .addReg(RBReg);
1481  }
1482 
1483  if (HasFP) {
1484  // If there is red zone, restore FP directly, since SP has already been
1485  // restored. Otherwise, restore the value of FP into ScratchReg.
1486  if (HasRedZone || RBReg == SPReg)
1487  BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1488  .addImm(FPOffset)
1489  .addReg(SPReg);
1490  else
1491  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1492  .addImm(FPOffset)
1493  .addReg(RBReg);
1494  }
1495 
1496  if (FI->usesPICBase())
1497  BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)
1498  .addImm(PBPOffset)
1499  .addReg(RBReg);
1500 
1501  if (HasBP)
1502  BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1503  .addImm(BPOffset)
1504  .addReg(RBReg);
1505 
1506  // There is nothing more to be loaded from the stack, so now we can
1507  // restore SP: SP = RBReg + SPAdd.
1508  if (RBReg != SPReg || SPAdd != 0) {
1509  assert(!HasRedZone && "This should not happen with red zone");
1510  // If SPAdd is 0, generate a copy.
1511  if (SPAdd == 0)
1512  BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1513  .addReg(RBReg)
1514  .addReg(RBReg);
1515  else
1516  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1517  .addReg(RBReg)
1518  .addImm(SPAdd);
1519 
1520  assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
1521  if (RBReg == FPReg)
1522  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1523  .addReg(ScratchReg)
1524  .addReg(ScratchReg);
1525 
1526  // Now load the LR from the caller's stack frame.
1527  if (MustSaveLR && !LoadedLR)
1528  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1529  .addImm(LROffset)
1530  .addReg(SPReg);
1531  }
1532 
1533  if (MustSaveCR &&
1534  !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1535  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1536  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1537  .addReg(TempReg, getKillRegState(i == e-1));
1538 
1539  if (MustSaveLR)
1540  BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1541 
1542  // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1543  // call optimization
1544  if (IsReturnBlock) {
1545  unsigned RetOpcode = MBBI->getOpcode();
1547  (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1550  unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1551 
1552  if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1553  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1554  .addReg(SPReg).addImm(CallerAllocatedAmt);
1555  } else {
1556  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1557  .addImm(CallerAllocatedAmt >> 16);
1558  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1559  .addReg(ScratchReg, RegState::Kill)
1560  .addImm(CallerAllocatedAmt & 0xFFFF);
1561  BuildMI(MBB, MBBI, dl, AddInst)
1562  .addReg(SPReg)
1563  .addReg(FPReg)
1564  .addReg(ScratchReg);
1565  }
1566  } else {
1567  createTailCallBranchInstr(MBB);
1568  }
1569  }
1570 }
1571 
1572 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const {
1574 
1575  // If we got this far a first terminator should exist.
1576  assert(MBBI != MBB.end() && "Failed to find the first terminator.");
1577 
1578  DebugLoc dl = MBBI->getDebugLoc();
1579  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1580 
1581  // Create branch instruction for pseudo tail call return instruction
1582  unsigned RetOpcode = MBBI->getOpcode();
1583  if (RetOpcode == PPC::TCRETURNdi) {
1584  MBBI = MBB.getLastNonDebugInstr();
1585  MachineOperand &JumpTarget = MBBI->getOperand(0);
1586  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1587  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1588  } else if (RetOpcode == PPC::TCRETURNri) {
1589  MBBI = MBB.getLastNonDebugInstr();
1590  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1591  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1592  } else if (RetOpcode == PPC::TCRETURNai) {
1593  MBBI = MBB.getLastNonDebugInstr();
1594  MachineOperand &JumpTarget = MBBI->getOperand(0);
1595  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1596  } else if (RetOpcode == PPC::TCRETURNdi8) {
1597  MBBI = MBB.getLastNonDebugInstr();
1598  MachineOperand &JumpTarget = MBBI->getOperand(0);
1599  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1600  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1601  } else if (RetOpcode == PPC::TCRETURNri8) {
1602  MBBI = MBB.getLastNonDebugInstr();
1603  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1604  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1605  } else if (RetOpcode == PPC::TCRETURNai8) {
1606  MBBI = MBB.getLastNonDebugInstr();
1607  MachineOperand &JumpTarget = MBBI->getOperand(0);
1608  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1609  }
1610 }
1611 
1613  BitVector &SavedRegs,
1614  RegScavenger *RS) const {
1615  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1616 
1617  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1618 
1619  // Save and clear the LR state.
1621  unsigned LR = RegInfo->getRARegister();
1622  FI->setMustSaveLR(MustSaveLR(MF, LR));
1623  SavedRegs.reset(LR);
1624 
1625  // Save R31 if necessary
1626  int FPSI = FI->getFramePointerSaveIndex();
1627  bool isPPC64 = Subtarget.isPPC64();
1628  bool isDarwinABI = Subtarget.isDarwinABI();
1629  MachineFrameInfo &MFI = MF.getFrameInfo();
1630 
1631  // If the frame pointer save index hasn't been defined yet.
1632  if (!FPSI && needsFP(MF)) {
1633  // Find out what the fix offset of the frame pointer save area.
1634  int FPOffset = getFramePointerSaveOffset();
1635  // Allocate the frame index for frame pointer save area.
1636  FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1637  // Save the result.
1638  FI->setFramePointerSaveIndex(FPSI);
1639  }
1640 
1641  int BPSI = FI->getBasePointerSaveIndex();
1642  if (!BPSI && RegInfo->hasBasePointer(MF)) {
1643  int BPOffset = getBasePointerSaveOffset();
1644  // Allocate the frame index for the base pointer save area.
1645  BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1646  // Save the result.
1647  FI->setBasePointerSaveIndex(BPSI);
1648  }
1649 
1650  // Reserve stack space for the PIC Base register (R30).
1651  // Only used in SVR4 32-bit.
1652  if (FI->usesPICBase()) {
1653  int PBPSI = MFI.CreateFixedObject(4, -8, true);
1654  FI->setPICBasePointerSaveIndex(PBPSI);
1655  }
1656 
1657  // Make sure we don't explicitly spill r31, because, for example, we have
1658  // some inline asm which explicitly clobbers it, when we otherwise have a
1659  // frame pointer and are using r31's spill slot for the prologue/epilogue
1660  // code. Same goes for the base pointer and the PIC base register.
1661  if (needsFP(MF))
1662  SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
1663  if (RegInfo->hasBasePointer(MF))
1664  SavedRegs.reset(RegInfo->getBaseRegister(MF));
1665  if (FI->usesPICBase())
1666  SavedRegs.reset(PPC::R30);
1667 
1668  // Reserve stack space to move the linkage area to in case of a tail call.
1669  int TCSPDelta = 0;
1671  (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1672  MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1673  }
1674 
1675  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1676  // function uses CR 2, 3, or 4.
1677  if (!isPPC64 && !isDarwinABI &&
1678  (SavedRegs.test(PPC::CR2) ||
1679  SavedRegs.test(PPC::CR3) ||
1680  SavedRegs.test(PPC::CR4))) {
1681  int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1682  FI->setCRSpillFrameIndex(FrameIdx);
1683  }
1684 }
1685 
1687  RegScavenger *RS) const {
1688  // Early exit if not using the SVR4 ABI.
1689  if (!Subtarget.isSVR4ABI()) {
1690  addScavengingSpillSlot(MF, RS);
1691  return;
1692  }
1693 
1694  // Get callee saved register information.
1695  MachineFrameInfo &MFI = MF.getFrameInfo();
1696  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1697 
1698  // If the function is shrink-wrapped, and if the function has a tail call, the
1699  // tail call might not be in the new RestoreBlock, so real branch instruction
1700  // won't be generated by emitEpilogue(), because shrink-wrap has chosen new
1701  // RestoreBlock. So we handle this case here.
1702  if (MFI.getSavePoint() && MFI.hasTailCall()) {
1703  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
1704  for (MachineBasicBlock &MBB : MF) {
1705  if (MBB.isReturnBlock() && (&MBB) != RestoreBlock)
1706  createTailCallBranchInstr(MBB);
1707  }
1708  }
1709 
1710  // Early exit if no callee saved registers are modified!
1711  if (CSI.empty() && !needsFP(MF)) {
1712  addScavengingSpillSlot(MF, RS);
1713  return;
1714  }
1715 
1716  unsigned MinGPR = PPC::R31;
1717  unsigned MinG8R = PPC::X31;
1718  unsigned MinFPR = PPC::F31;
1719  unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
1720 
1721  bool HasGPSaveArea = false;
1722  bool HasG8SaveArea = false;
1723  bool HasFPSaveArea = false;
1724  bool HasVRSAVESaveArea = false;
1725  bool HasVRSaveArea = false;
1726 
1731 
1732  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1733  unsigned Reg = CSI[i].getReg();
1734  if (PPC::GPRCRegClass.contains(Reg) ||
1735  PPC::SPE4RCRegClass.contains(Reg)) {
1736  HasGPSaveArea = true;
1737 
1738  GPRegs.push_back(CSI[i]);
1739 
1740  if (Reg < MinGPR) {
1741  MinGPR = Reg;
1742  }
1743  } else if (PPC::G8RCRegClass.contains(Reg)) {
1744  HasG8SaveArea = true;
1745 
1746  G8Regs.push_back(CSI[i]);
1747 
1748  if (Reg < MinG8R) {
1749  MinG8R = Reg;
1750  }
1751  } else if (PPC::F8RCRegClass.contains(Reg)) {
1752  HasFPSaveArea = true;
1753 
1754  FPRegs.push_back(CSI[i]);
1755 
1756  if (Reg < MinFPR) {
1757  MinFPR = Reg;
1758  }
1759  } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1760  PPC::CRRCRegClass.contains(Reg)) {
1761  ; // do nothing, as we already know whether CRs are spilled
1762  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1763  HasVRSAVESaveArea = true;
1764  } else if (PPC::VRRCRegClass.contains(Reg) ||
1765  PPC::SPERCRegClass.contains(Reg)) {
1766  // Altivec and SPE are mutually exclusive, but have the same stack
1767  // alignment requirements, so overload the save area for both cases.
1768  HasVRSaveArea = true;
1769 
1770  VRegs.push_back(CSI[i]);
1771 
1772  if (Reg < MinVR) {
1773  MinVR = Reg;
1774  }
1775  } else {
1776  llvm_unreachable("Unknown RegisterClass!");
1777  }
1778  }
1779 
1781  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1782 
1783  int64_t LowerBound = 0;
1784 
1785  // Take into account stack space reserved for tail calls.
1786  int TCSPDelta = 0;
1788  (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1789  LowerBound = TCSPDelta;
1790  }
1791 
1792  // The Floating-point register save area is right below the back chain word
1793  // of the previous stack frame.
1794  if (HasFPSaveArea) {
1795  for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1796  int FI = FPRegs[i].getFrameIdx();
1797 
1798  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1799  }
1800 
1801  LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1802  }
1803 
1804  // Check whether the frame pointer register is allocated. If so, make sure it
1805  // is spilled to the correct offset.
1806  if (needsFP(MF)) {
1807  int FI = PFI->getFramePointerSaveIndex();
1808  assert(FI && "No Frame Pointer Save Slot!");
1809  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1810  // FP is R31/X31, so no need to update MinGPR/MinG8R.
1811  HasGPSaveArea = true;
1812  }
1813 
1814  if (PFI->usesPICBase()) {
1815  int FI = PFI->getPICBasePointerSaveIndex();
1816  assert(FI && "No PIC Base Pointer Save Slot!");
1817  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1818 
1819  MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
1820  HasGPSaveArea = true;
1821  }
1822 
1823  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1824  if (RegInfo->hasBasePointer(MF)) {
1825  int FI = PFI->getBasePointerSaveIndex();
1826  assert(FI && "No Base Pointer Save Slot!");
1827  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1828 
1829  unsigned BP = RegInfo->getBaseRegister(MF);
1830  if (PPC::G8RCRegClass.contains(BP)) {
1831  MinG8R = std::min<unsigned>(MinG8R, BP);
1832  HasG8SaveArea = true;
1833  } else if (PPC::GPRCRegClass.contains(BP)) {
1834  MinGPR = std::min<unsigned>(MinGPR, BP);
1835  HasGPSaveArea = true;
1836  }
1837  }
1838 
1839  // General register save area starts right below the Floating-point
1840  // register save area.
1841  if (HasGPSaveArea || HasG8SaveArea) {
1842  // Move general register save area spill slots down, taking into account
1843  // the size of the Floating-point register save area.
1844  for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1845  if (!GPRegs[i].isSpilledToReg()) {
1846  int FI = GPRegs[i].getFrameIdx();
1847  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1848  }
1849  }
1850 
1851  // Move general register save area spill slots down, taking into account
1852  // the size of the Floating-point register save area.
1853  for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1854  if (!G8Regs[i].isSpilledToReg()) {
1855  int FI = G8Regs[i].getFrameIdx();
1856  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1857  }
1858  }
1859 
1860  unsigned MinReg =
1861  std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1862  TRI->getEncodingValue(MinG8R));
1863 
1864  if (Subtarget.isPPC64()) {
1865  LowerBound -= (31 - MinReg + 1) * 8;
1866  } else {
1867  LowerBound -= (31 - MinReg + 1) * 4;
1868  }
1869  }
1870 
1871  // For 32-bit only, the CR save area is below the general register
1872  // save area. For 64-bit SVR4, the CR save area is addressed relative
1873  // to the stack pointer and hence does not need an adjustment here.
1874  // Only CR2 (the first nonvolatile spilled) has an associated frame
1875  // index so that we have a single uniform save area.
1876  if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1877  // Adjust the frame index of the CR spill slot.
1878  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1879  unsigned Reg = CSI[i].getReg();
1880 
1881  if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1882  // Leave Darwin logic as-is.
1883  || (!Subtarget.isSVR4ABI() &&
1884  (PPC::CRBITRCRegClass.contains(Reg) ||
1885  PPC::CRRCRegClass.contains(Reg)))) {
1886  int FI = CSI[i].getFrameIdx();
1887 
1888  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1889  }
1890  }
1891 
1892  LowerBound -= 4; // The CR save area is always 4 bytes long.
1893  }
1894 
1895  if (HasVRSAVESaveArea) {
1896  // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1897  // which have the VRSAVE register class?
1898  // Adjust the frame index of the VRSAVE spill slot.
1899  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1900  unsigned Reg = CSI[i].getReg();
1901 
1902  if (PPC::VRSAVERCRegClass.contains(Reg)) {
1903  int FI = CSI[i].getFrameIdx();
1904 
1905  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1906  }
1907  }
1908 
1909  LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1910  }
1911 
1912  // Both Altivec and SPE have the same alignment and padding requirements
1913  // within the stack frame.
1914  if (HasVRSaveArea) {
1915  // Insert alignment padding, we need 16-byte alignment. Note: for positive
1916  // number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since
1917  // we are using negative number here (the stack grows downward). We should
1918  // use formula : y = x & (~(n-1)). Where x is the size before aligning, n
1919  // is the alignment size ( n = 16 here) and y is the size after aligning.
1920  assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
1921  LowerBound &= ~(15);
1922 
1923  for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1924  int FI = VRegs[i].getFrameIdx();
1925 
1926  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1927  }
1928  }
1929 
1930  addScavengingSpillSlot(MF, RS);
1931 }
1932 
1933 void
1935  RegScavenger *RS) const {
1936  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1937  // a large stack, which will require scavenging a register to materialize a
1938  // large offset.
1939 
1940  // We need to have a scavenger spill slot for spills if the frame size is
1941  // large. In case there is no free register for large-offset addressing,
1942  // this slot is used for the necessary emergency spill. Also, we need the
1943  // slot for dynamic stack allocations.
1944 
1945  // The scavenger might be invoked if the frame offset does not fit into
1946  // the 16-bit immediate. We don't know the complete frame size here
1947  // because we've not yet computed callee-saved register spills or the
1948  // needed alignment padding.
1949  unsigned StackSize = determineFrameLayout(MF, false, true);
1950  MachineFrameInfo &MFI = MF.getFrameInfo();
1951  if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1952  hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1953  const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
1954  const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
1955  const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
1956  const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
1957  unsigned Size = TRI.getSpillSize(RC);
1958  unsigned Align = TRI.getSpillAlignment(RC);
1959  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1960 
1961  // Might we have over-aligned allocas?
1962  bool HasAlVars = MFI.hasVarSizedObjects() &&
1964 
1965  // These kinds of spills might need two registers.
1966  if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1967  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1968 
1969  }
1970 }
1971 
1972 // This function checks if a callee saved gpr can be spilled to a volatile
1973 // vector register. This occurs for leaf functions when the option
1974 // ppc-enable-pe-vector-spills is enabled. If there are any remaining registers
1975 // which were not spilled to vectors, return false so the target independent
1976 // code can handle them by assigning a FrameIdx to a stack slot.
1979  std::vector<CalleeSavedInfo> &CSI) const {
1980 
1981  if (CSI.empty())
1982  return true; // Early exit if no callee saved registers are modified!
1983 
1984  // Early exit if cannot spill gprs to volatile vector registers.
1985  MachineFrameInfo &MFI = MF.getFrameInfo();
1986  if (!EnablePEVectorSpills || MFI.hasCalls() || !Subtarget.hasP9Vector())
1987  return false;
1988 
1989  // Build a BitVector of VSRs that can be used for spilling GPRs.
1990  BitVector BVAllocatable = TRI->getAllocatableSet(MF);
1991  BitVector BVCalleeSaved(TRI->getNumRegs());
1992  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1993  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1994  for (unsigned i = 0; CSRegs[i]; ++i)
1995  BVCalleeSaved.set(CSRegs[i]);
1996 
1997  for (unsigned Reg : BVAllocatable.set_bits()) {
1998  // Set to 0 if the register is not a volatile VF/F8 register, or if it is
1999  // used in the function.
2000  if (BVCalleeSaved[Reg] ||
2001  (!PPC::F8RCRegClass.contains(Reg) &&
2002  !PPC::VFRCRegClass.contains(Reg)) ||
2003  (MF.getRegInfo().isPhysRegUsed(Reg)))
2004  BVAllocatable.reset(Reg);
2005  }
2006 
2007  bool AllSpilledToReg = true;
2008  for (auto &CS : CSI) {
2009  if (BVAllocatable.none())
2010  return false;
2011 
2012  unsigned Reg = CS.getReg();
2013  if (!PPC::G8RCRegClass.contains(Reg) && !PPC::GPRCRegClass.contains(Reg)) {
2014  AllSpilledToReg = false;
2015  continue;
2016  }
2017 
2018  unsigned VolatileVFReg = BVAllocatable.find_first();
2019  if (VolatileVFReg < BVAllocatable.size()) {
2020  CS.setDstReg(VolatileVFReg);
2021  BVAllocatable.reset(VolatileVFReg);
2022  } else {
2023  AllSpilledToReg = false;
2024  }
2025  }
2026  return AllSpilledToReg;
2027 }
2028 
2029 
2030 bool
2033  const std::vector<CalleeSavedInfo> &CSI,
2034  const TargetRegisterInfo *TRI) const {
2035 
2036  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
2037  // Return false otherwise to maintain pre-existing behavior.
2038  if (!Subtarget.isSVR4ABI())
2039  return false;
2040 
2041  MachineFunction *MF = MBB.getParent();
2042  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
2043  DebugLoc DL;
2044  bool CRSpilled = false;
2045  MachineInstrBuilder CRMIB;
2046 
2047  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2048  unsigned Reg = CSI[i].getReg();
2049  // Only Darwin actually uses the VRSAVE register, but it can still appear
2050  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
2051  // Darwin, ignore it.
2052  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
2053  continue;
2054 
2055  // CR2 through CR4 are the nonvolatile CR fields.
2056  bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
2057 
2058  // Add the callee-saved register as live-in; it's killed at the spill.
2059  // Do not do this for callee-saved registers that are live-in to the
2060  // function because they will already be marked live-in and this will be
2061  // adding it for a second time. It is an error to add the same register
2062  // to the set more than once.
2063  const MachineRegisterInfo &MRI = MF->getRegInfo();
2064  bool IsLiveIn = MRI.isLiveIn(Reg);
2065  if (!IsLiveIn)
2066  MBB.addLiveIn(Reg);
2067 
2068  if (CRSpilled && IsCRField) {
2069  CRMIB.addReg(Reg, RegState::ImplicitKill);
2070  continue;
2071  }
2072 
2073  // Insert the spill to the stack frame.
2074  if (IsCRField) {
2075  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
2076  if (Subtarget.isPPC64()) {
2077  // The actual spill will happen at the start of the prologue.
2078  FuncInfo->addMustSaveCR(Reg);
2079  } else {
2080  CRSpilled = true;
2081  FuncInfo->setSpillsCR();
2082 
2083  // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
2084  // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
2085  CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
2086  .addReg(Reg, RegState::ImplicitKill);
2087 
2088  MBB.insert(MI, CRMIB);
2089  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
2090  .addReg(PPC::R12,
2091  getKillRegState(true)),
2092  CSI[i].getFrameIdx()));
2093  }
2094  } else {
2095  if (CSI[i].isSpilledToReg()) {
2096  NumPESpillVSR++;
2097  BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRD), CSI[i].getDstReg())
2098  .addReg(Reg, getKillRegState(true));
2099  } else {
2100  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2101  // Use !IsLiveIn for the kill flag.
2102  // We do not want to kill registers that are live in this function
2103  // before their use because they will become undefined registers.
2104  TII.storeRegToStackSlot(MBB, MI, Reg, !IsLiveIn,
2105  CSI[i].getFrameIdx(), RC, TRI);
2106  }
2107  }
2108  }
2109  return true;
2110 }
2111 
2112 static void
2113 restoreCRs(bool isPPC64, bool is31,
2114  bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
2116  const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
2117 
2118  MachineFunction *MF = MBB.getParent();
2119  const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
2120  DebugLoc DL;
2121  unsigned RestoreOp, MoveReg;
2122 
2123  if (isPPC64)
2124  // This is handled during epilogue generation.
2125  return;
2126  else {
2127  // 32-bit: FP-relative
2128  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
2129  PPC::R12),
2130  CSI[CSIIndex].getFrameIdx()));
2131  RestoreOp = PPC::MTOCRF;
2132  MoveReg = PPC::R12;
2133  }
2134 
2135  if (CR2Spilled)
2136  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2137  .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2138 
2139  if (CR3Spilled)
2140  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2141  .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2142 
2143  if (CR4Spilled)
2144  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2145  .addReg(MoveReg, getKillRegState(true)));
2146 }
2147 
2151  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2153  I->getOpcode() == PPC::ADJCALLSTACKUP) {
2154  // Add (actually subtract) back the amount the callee popped on return.
2155  if (int CalleeAmt = I->getOperand(1).getImm()) {
2156  bool is64Bit = Subtarget.isPPC64();
2157  CalleeAmt *= -1;
2158  unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2159  unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2160  unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2161  unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2162  unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2163  unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2164  const DebugLoc &dl = I->getDebugLoc();
2165 
2166  if (isInt<16>(CalleeAmt)) {
2167  BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2168  .addReg(StackReg, RegState::Kill)
2169  .addImm(CalleeAmt);
2170  } else {
2172  BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2173  .addImm(CalleeAmt >> 16);
2174  BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2175  .addReg(TmpReg, RegState::Kill)
2176  .addImm(CalleeAmt & 0xFFFF);
2177  BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2178  .addReg(StackReg, RegState::Kill)
2179  .addReg(TmpReg);
2180  }
2181  }
2182  }
2183  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
2184  return MBB.erase(I);
2185 }
2186 
2187 bool
2190  std::vector<CalleeSavedInfo> &CSI,
2191  const TargetRegisterInfo *TRI) const {
2192 
2193  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
2194  // Return false otherwise to maintain pre-existing behavior.
2195  if (!Subtarget.isSVR4ABI())
2196  return false;
2197 
2198  MachineFunction *MF = MBB.getParent();
2199  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
2200  bool CR2Spilled = false;
2201  bool CR3Spilled = false;
2202  bool CR4Spilled = false;
2203  unsigned CSIIndex = 0;
2204 
2205  // Initialize insertion-point logic; we will be restoring in reverse
2206  // order of spill.
2207  MachineBasicBlock::iterator I = MI, BeforeI = I;
2208  bool AtStart = I == MBB.begin();
2209 
2210  if (!AtStart)
2211  --BeforeI;
2212 
2213  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2214  unsigned Reg = CSI[i].getReg();
2215 
2216  // Only Darwin actually uses the VRSAVE register, but it can still appear
2217  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
2218  // Darwin, ignore it.
2219  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
2220  continue;
2221 
2222  if (Reg == PPC::CR2) {
2223  CR2Spilled = true;
2224  // The spill slot is associated only with CR2, which is the
2225  // first nonvolatile spilled. Save it here.
2226  CSIIndex = i;
2227  continue;
2228  } else if (Reg == PPC::CR3) {
2229  CR3Spilled = true;
2230  continue;
2231  } else if (Reg == PPC::CR4) {
2232  CR4Spilled = true;
2233  continue;
2234  } else {
2235  // When we first encounter a non-CR register after seeing at
2236  // least one CR register, restore all spilled CRs together.
2237  if ((CR2Spilled || CR3Spilled || CR4Spilled)
2238  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2239  bool is31 = needsFP(*MF);
2240  restoreCRs(Subtarget.isPPC64(), is31,
2241  CR2Spilled, CR3Spilled, CR4Spilled,
2242  MBB, I, CSI, CSIIndex);
2243  CR2Spilled = CR3Spilled = CR4Spilled = false;
2244  }
2245 
2246  if (CSI[i].isSpilledToReg()) {
2247  DebugLoc DL;
2248  NumPEReloadVSR++;
2249  BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), Reg)
2250  .addReg(CSI[i].getDstReg(), getKillRegState(true));
2251  } else {
2252  // Default behavior for non-CR saves.
2253  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2254  TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), RC, TRI);
2255  assert(I != MBB.begin() &&
2256  "loadRegFromStackSlot didn't insert any code!");
2257  }
2258  }
2259 
2260  // Insert in reverse order.
2261  if (AtStart)
2262  I = MBB.begin();
2263  else {
2264  I = BeforeI;
2265  ++I;
2266  }
2267  }
2268 
2269  // If we haven't yet spilled the CRs, do so now.
2270  if (CR2Spilled || CR3Spilled || CR4Spilled) {
2271  bool is31 = needsFP(*MF);
2272  restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
2273  MBB, I, CSI, CSIIndex);
2274  }
2275 
2276  return true;
2277 }
2278 
2281  return false;
2282  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
2283  MF.getSubtarget<PPCSubtarget>().isPPC64());
2284 }
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool hasDebugInfo() const
Returns true if valid debug info is present.
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addMustSaveCR(unsigned Reg)
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
unsigned Reg
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool test(unsigned Idx) const
Definition: BitVector.h:501
void setFramePointerSaveIndex(int Idx)
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1026
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
An instruction for reading from memory.
Definition: Instructions.h:167
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:474
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool hasSPE() const
Definition: PPCSubtarget.h:243
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
MachineBasicBlock * getRestorePoint() const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:331
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:339
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
def_iterator def_begin(unsigned RegNo) const
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool isELFv2ABI() const
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool hasP9Vector() const
Definition: PPCSubtarget.h:250
const MCContext & getContext() const
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:192
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
Definition: Instructions.h:320
bool hasBasePointer(const MachineFunction &MF) const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getBaseRegister(const MachineFunction &MF) const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:467
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
BitVector & reset()
Definition: BitVector.h:438
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
size_t size() const
Definition: SmallVector.h:52
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:189
Iterator for intrusive lists based on ilist_node.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:182
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
Information about stack frame layout on the target.
bool isDarwinABI() const
Definition: PPCSubtarget.h:310
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
static bool spillsVRSAVE(const MachineFunction &MF)
static bool hasSpills(const MachineFunction &MF)
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
unsigned getMinReservedArea() const
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:572
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
static bool spillsCR(const MachineFunction &MF)
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:284
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:201
void setPICBasePointerSaveIndex(int Idx)
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
TargetOptions Options
Definition: TargetMachine.h:96
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
void setMaxCallFrameSize(unsigned S)
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool needsFP(const MachineFunction &MF) const
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
uint32_t Size
Definition: Profile.cpp:46
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock * getSavePoint() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:129
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:311
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
Definition: MCDwarf.h:502
void replaceFPWithRealFP(MachineFunction &MF) const
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.