LLVM  6.0.0svn
PPCFrameLowering.cpp
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1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
26 #include "llvm/IR/Function.h"
28 
29 using namespace llvm;
30 
31 /// VRRegNo - Map from a numbered VR register to its enum value.
32 ///
33 static const MCPhysReg VRRegNo[] = {
34  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 };
39 
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41  if (STI.isDarwinABI())
42  return STI.isPPC64() ? 16 : 8;
43  // SVR4 ABI:
44  return STI.isPPC64() ? 16 : 4;
45 }
46 
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48  return STI.isELFv2ABI() ? 24 : 40;
49 }
50 
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52  // For the Darwin ABI:
53  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54  // for saving the frame pointer (if needed.) While the published ABI has
55  // not used this slot since at least MacOSX 10.2, there is older code
56  // around that does use it, and that needs to continue to work.
57  if (STI.isDarwinABI())
58  return STI.isPPC64() ? -8U : -4U;
59 
60  // SVR4 ABI: First slot in the general register save area.
61  return STI.isPPC64() ? -8U : -4U;
62 }
63 
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65  if (STI.isDarwinABI() || STI.isPPC64())
66  return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
67 
68  // SVR4 ABI:
69  return 8;
70 }
71 
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73  if (STI.isDarwinABI())
74  return STI.isPPC64() ? -16U : -8U;
75 
76  // SVR4 ABI: First slot in the general register save area.
77  return STI.isPPC64()
78  ? -16U
79  : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
80 }
81 
83  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
84  STI.getPlatformStackAlignment(), 0),
85  Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
86  TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
87  FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
88  LinkageSize(computeLinkageSize(Subtarget)),
89  BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
90 
91 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
93  unsigned &NumEntries) const {
94  if (Subtarget.isDarwinABI()) {
95  NumEntries = 1;
96  if (Subtarget.isPPC64()) {
97  static const SpillSlot darwin64Offsets = {PPC::X31, -8};
98  return &darwin64Offsets;
99  } else {
100  static const SpillSlot darwinOffsets = {PPC::R31, -4};
101  return &darwinOffsets;
102  }
103  }
104 
105  // Early exit if not using the SVR4 ABI.
106  if (!Subtarget.isSVR4ABI()) {
107  NumEntries = 0;
108  return nullptr;
109  }
110 
111  // Note that the offsets here overlap, but this is fixed up in
112  // processFunctionBeforeFrameFinalized.
113 
114  static const SpillSlot Offsets[] = {
115  // Floating-point register save area offsets.
116  {PPC::F31, -8},
117  {PPC::F30, -16},
118  {PPC::F29, -24},
119  {PPC::F28, -32},
120  {PPC::F27, -40},
121  {PPC::F26, -48},
122  {PPC::F25, -56},
123  {PPC::F24, -64},
124  {PPC::F23, -72},
125  {PPC::F22, -80},
126  {PPC::F21, -88},
127  {PPC::F20, -96},
128  {PPC::F19, -104},
129  {PPC::F18, -112},
130  {PPC::F17, -120},
131  {PPC::F16, -128},
132  {PPC::F15, -136},
133  {PPC::F14, -144},
134 
135  // General register save area offsets.
136  {PPC::R31, -4},
137  {PPC::R30, -8},
138  {PPC::R29, -12},
139  {PPC::R28, -16},
140  {PPC::R27, -20},
141  {PPC::R26, -24},
142  {PPC::R25, -28},
143  {PPC::R24, -32},
144  {PPC::R23, -36},
145  {PPC::R22, -40},
146  {PPC::R21, -44},
147  {PPC::R20, -48},
148  {PPC::R19, -52},
149  {PPC::R18, -56},
150  {PPC::R17, -60},
151  {PPC::R16, -64},
152  {PPC::R15, -68},
153  {PPC::R14, -72},
154 
155  // CR save area offset. We map each of the nonvolatile CR fields
156  // to the slot for CR2, which is the first of the nonvolatile CR
157  // fields to be assigned, so that we only allocate one save slot.
158  // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
159  {PPC::CR2, -4},
160 
161  // VRSAVE save area offset.
162  {PPC::VRSAVE, -4},
163 
164  // Vector register save area
165  {PPC::V31, -16},
166  {PPC::V30, -32},
167  {PPC::V29, -48},
168  {PPC::V28, -64},
169  {PPC::V27, -80},
170  {PPC::V26, -96},
171  {PPC::V25, -112},
172  {PPC::V24, -128},
173  {PPC::V23, -144},
174  {PPC::V22, -160},
175  {PPC::V21, -176},
176  {PPC::V20, -192}};
177 
178  static const SpillSlot Offsets64[] = {
179  // Floating-point register save area offsets.
180  {PPC::F31, -8},
181  {PPC::F30, -16},
182  {PPC::F29, -24},
183  {PPC::F28, -32},
184  {PPC::F27, -40},
185  {PPC::F26, -48},
186  {PPC::F25, -56},
187  {PPC::F24, -64},
188  {PPC::F23, -72},
189  {PPC::F22, -80},
190  {PPC::F21, -88},
191  {PPC::F20, -96},
192  {PPC::F19, -104},
193  {PPC::F18, -112},
194  {PPC::F17, -120},
195  {PPC::F16, -128},
196  {PPC::F15, -136},
197  {PPC::F14, -144},
198 
199  // General register save area offsets.
200  {PPC::X31, -8},
201  {PPC::X30, -16},
202  {PPC::X29, -24},
203  {PPC::X28, -32},
204  {PPC::X27, -40},
205  {PPC::X26, -48},
206  {PPC::X25, -56},
207  {PPC::X24, -64},
208  {PPC::X23, -72},
209  {PPC::X22, -80},
210  {PPC::X21, -88},
211  {PPC::X20, -96},
212  {PPC::X19, -104},
213  {PPC::X18, -112},
214  {PPC::X17, -120},
215  {PPC::X16, -128},
216  {PPC::X15, -136},
217  {PPC::X14, -144},
218 
219  // VRSAVE save area offset.
220  {PPC::VRSAVE, -4},
221 
222  // Vector register save area
223  {PPC::V31, -16},
224  {PPC::V30, -32},
225  {PPC::V29, -48},
226  {PPC::V28, -64},
227  {PPC::V27, -80},
228  {PPC::V26, -96},
229  {PPC::V25, -112},
230  {PPC::V24, -128},
231  {PPC::V23, -144},
232  {PPC::V22, -160},
233  {PPC::V21, -176},
234  {PPC::V20, -192}};
235 
236  if (Subtarget.isPPC64()) {
237  NumEntries = array_lengthof(Offsets64);
238 
239  return Offsets64;
240  } else {
241  NumEntries = array_lengthof(Offsets);
242 
243  return Offsets;
244  }
245 }
246 
247 /// RemoveVRSaveCode - We have found that this function does not need any code
248 /// to manipulate the VRSAVE register, even though it uses vector registers.
249 /// This can happen when the only registers used are known to be live in or out
250 /// of the function. Remove all of the VRSAVE related code from the function.
251 /// FIXME: The removal of the code results in a compile failure at -O0 when the
252 /// function contains a function call, as the GPR containing original VRSAVE
253 /// contents is spilled and reloaded around the call. Without the prolog code,
254 /// the spill instruction refers to an undefined register. This code needs
255 /// to account for all uses of that GPR.
257  MachineBasicBlock *Entry = MI.getParent();
258  MachineFunction *MF = Entry->getParent();
259 
260  // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
262  ++MBBI;
263  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
264  MBBI->eraseFromParent();
265 
266  bool RemovedAllMTVRSAVEs = true;
267  // See if we can find and remove the MTVRSAVE instruction from all of the
268  // epilog blocks.
269  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
270  // If last instruction is a return instruction, add an epilogue
271  if (I->isReturnBlock()) {
272  bool FoundIt = false;
273  for (MBBI = I->end(); MBBI != I->begin(); ) {
274  --MBBI;
275  if (MBBI->getOpcode() == PPC::MTVRSAVE) {
276  MBBI->eraseFromParent(); // remove it.
277  FoundIt = true;
278  break;
279  }
280  }
281  RemovedAllMTVRSAVEs &= FoundIt;
282  }
283  }
284 
285  // If we found and removed all MTVRSAVE instructions, remove the read of
286  // VRSAVE as well.
287  if (RemovedAllMTVRSAVEs) {
288  MBBI = MI;
289  assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
290  --MBBI;
291  assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
292  MBBI->eraseFromParent();
293  }
294 
295  // Finally, nuke the UPDATE_VRSAVE.
296  MI.eraseFromParent();
297 }
298 
299 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
300 // instruction selector. Based on the vector registers that have been used,
301 // transform this into the appropriate ORI instruction.
303  MachineFunction *MF = MI.getParent()->getParent();
304  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
305  DebugLoc dl = MI.getDebugLoc();
306 
307  const MachineRegisterInfo &MRI = MF->getRegInfo();
308  unsigned UsedRegMask = 0;
309  for (unsigned i = 0; i != 32; ++i)
310  if (MRI.isPhysRegModified(VRRegNo[i]))
311  UsedRegMask |= 1 << (31-i);
312 
313  // Live in and live out values already must be in the mask, so don't bother
314  // marking them.
315  for (std::pair<unsigned, unsigned> LI : MF->getRegInfo().liveins()) {
316  unsigned RegNo = TRI->getEncodingValue(LI.first);
317  if (VRRegNo[RegNo] == LI.first) // If this really is a vector reg.
318  UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
319  }
320 
321  // Live out registers appear as use operands on return instructions.
322  for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
323  UsedRegMask != 0 && BI != BE; ++BI) {
324  const MachineBasicBlock &MBB = *BI;
325  if (!MBB.isReturnBlock())
326  continue;
327  const MachineInstr &Ret = MBB.back();
328  for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
329  const MachineOperand &MO = Ret.getOperand(I);
330  if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
331  continue;
332  unsigned RegNo = TRI->getEncodingValue(MO.getReg());
333  UsedRegMask &= ~(1 << (31-RegNo));
334  }
335  }
336 
337  // If no registers are used, turn this into a copy.
338  if (UsedRegMask == 0) {
339  // Remove all VRSAVE code.
340  RemoveVRSaveCode(MI);
341  return;
342  }
343 
344  unsigned SrcReg = MI.getOperand(1).getReg();
345  unsigned DstReg = MI.getOperand(0).getReg();
346 
347  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
348  if (DstReg != SrcReg)
349  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
350  .addReg(SrcReg)
351  .addImm(UsedRegMask);
352  else
353  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
354  .addReg(SrcReg, RegState::Kill)
355  .addImm(UsedRegMask);
356  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
357  if (DstReg != SrcReg)
358  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
359  .addReg(SrcReg)
360  .addImm(UsedRegMask >> 16);
361  else
362  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
363  .addReg(SrcReg, RegState::Kill)
364  .addImm(UsedRegMask >> 16);
365  } else {
366  if (DstReg != SrcReg)
367  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
368  .addReg(SrcReg)
369  .addImm(UsedRegMask >> 16);
370  else
371  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
372  .addReg(SrcReg, RegState::Kill)
373  .addImm(UsedRegMask >> 16);
374 
375  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
376  .addReg(DstReg, RegState::Kill)
377  .addImm(UsedRegMask & 0xFFFF);
378  }
379 
380  // Remove the old UPDATE_VRSAVE instruction.
381  MI.eraseFromParent();
382 }
383 
384 static bool spillsCR(const MachineFunction &MF) {
385  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
386  return FuncInfo->isCRSpilled();
387 }
388 
389 static bool spillsVRSAVE(const MachineFunction &MF) {
390  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
391  return FuncInfo->isVRSAVESpilled();
392 }
393 
394 static bool hasSpills(const MachineFunction &MF) {
395  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
396  return FuncInfo->hasSpills();
397 }
398 
399 static bool hasNonRISpills(const MachineFunction &MF) {
400  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
401  return FuncInfo->hasNonRISpills();
402 }
403 
404 /// MustSaveLR - Return true if this function requires that we save the LR
405 /// register onto the stack in the prolog and restore it in the epilog of the
406 /// function.
407 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
408  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
409 
410  // We need a save/restore of LR if there is any def of LR (which is
411  // defined by calls, including the PIC setup sequence), or if there is
412  // some use of the LR stack slot (e.g. for builtin_return_address).
413  // (LR comes in 32 and 64 bit versions.)
415  return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
416 }
417 
418 /// determineFrameLayout - Determine the size of the frame and maximum call
419 /// frame size.
421  bool UpdateMF,
422  bool UseEstimate) const {
423  MachineFrameInfo &MFI = MF.getFrameInfo();
424 
425  // Get the number of bytes to allocate from the FrameInfo
426  unsigned FrameSize =
427  UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
428 
429  // Get stack alignments. The frame must be aligned to the greatest of these:
430  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
431  unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
432  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
433 
434  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
435 
436  unsigned LR = RegInfo->getRARegister();
437  bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
438  bool CanUseRedZone = !MFI.hasVarSizedObjects() && // No dynamic alloca.
439  !MFI.adjustsStack() && // No calls.
440  !MustSaveLR(MF, LR) && // No need to save LR.
441  !RegInfo->hasBasePointer(MF); // No special alignment.
442 
443  // Note: for PPC32 SVR4ABI (Non-DarwinABI), we can still generate stackless
444  // code if all local vars are reg-allocated.
445  bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize();
446 
447  // Check whether we can skip adjusting the stack pointer (by using red zone)
448  if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
449  // No need for frame
450  if (UpdateMF)
451  MFI.setStackSize(0);
452  return 0;
453  }
454 
455  // Get the maximum call frame size of all the calls.
456  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
457 
458  // Maximum call frame needs to be at least big enough for linkage area.
459  unsigned minCallFrameSize = getLinkageSize();
460  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
461 
462  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
463  // that allocations will be aligned.
464  if (MFI.hasVarSizedObjects())
465  maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
466 
467  // Update maximum call frame size.
468  if (UpdateMF)
469  MFI.setMaxCallFrameSize(maxCallFrameSize);
470 
471  // Include call frame size in total.
472  FrameSize += maxCallFrameSize;
473 
474  // Make sure the frame is aligned.
475  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
476 
477  // Update frame info.
478  if (UpdateMF)
479  MFI.setStackSize(FrameSize);
480 
481  return FrameSize;
482 }
483 
484 // hasFP - Return true if the specified function actually has a dedicated frame
485 // pointer register.
487  const MachineFrameInfo &MFI = MF.getFrameInfo();
488  // FIXME: This is pretty much broken by design: hasFP() might be called really
489  // early, before the stack layout was calculated and thus hasFP() might return
490  // true or false here depending on the time of call.
491  return (MFI.getStackSize()) && needsFP(MF);
492 }
493 
494 // needsFP - Return true if the specified function should have a dedicated frame
495 // pointer register. This is true if the function has variable sized allocas or
496 // if frame pointer elimination is disabled.
498  const MachineFrameInfo &MFI = MF.getFrameInfo();
499 
500  // Naked functions have no stack frame pushed, so we don't have a frame
501  // pointer.
502  if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
503  return false;
504 
505  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
506  MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint() ||
508  MF.getInfo<PPCFunctionInfo>()->hasFastCall());
509 }
510 
512  bool is31 = needsFP(MF);
513  unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
514  unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
515 
516  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
517  bool HasBP = RegInfo->hasBasePointer(MF);
518  unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
519  unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
520 
521  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
522  BI != BE; ++BI)
523  for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
524  --MBBI;
525  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
526  MachineOperand &MO = MBBI->getOperand(I);
527  if (!MO.isReg())
528  continue;
529 
530  switch (MO.getReg()) {
531  case PPC::FP:
532  MO.setReg(FPReg);
533  break;
534  case PPC::FP8:
535  MO.setReg(FP8Reg);
536  break;
537  case PPC::BP:
538  MO.setReg(BPReg);
539  break;
540  case PPC::BP8:
541  MO.setReg(BP8Reg);
542  break;
543 
544  }
545  }
546  }
547 }
548 
549 /* This function will do the following:
550  - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
551  respectively (defaults recommended by the ABI) and return true
552  - If MBB is not an entry block, initialize the register scavenger and look
553  for available registers.
554  - If the defaults (R0/R12) are available, return true
555  - If TwoUniqueRegsRequired is set to true, it looks for two unique
556  registers. Otherwise, look for a single available register.
557  - If the required registers are found, set SR1 and SR2 and return true.
558  - If the required registers are not found, set SR2 or both SR1 and SR2 to
559  PPC::NoRegister and return false.
560 
561  Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
562  is not set, this function will attempt to find two different registers, but
563  still return true if only one register is available (and set SR1 == SR2).
564 */
565 bool
566 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
567  bool UseAtEnd,
568  bool TwoUniqueRegsRequired,
569  unsigned *SR1,
570  unsigned *SR2) const {
571  RegScavenger RS;
572  unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
573  unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
574 
575  // Set the defaults for the two scratch registers.
576  if (SR1)
577  *SR1 = R0;
578 
579  if (SR2) {
580  assert (SR1 && "Asking for the second scratch register but not the first?");
581  *SR2 = R12;
582  }
583 
584  // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
585  if ((UseAtEnd && MBB->isReturnBlock()) ||
586  (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
587  return true;
588 
589  RS.enterBasicBlock(*MBB);
590 
591  if (UseAtEnd && !MBB->empty()) {
592  // The scratch register will be used at the end of the block, so must
593  // consider all registers used within the block
594 
596  // If no terminator, back iterator up to previous instruction.
597  if (MBBI == MBB->end())
598  MBBI = std::prev(MBBI);
599 
600  if (MBBI != MBB->begin())
601  RS.forward(MBBI);
602  }
603 
604  // If the two registers are available, we're all good.
605  // Note that we only return here if both R0 and R12 are available because
606  // although the function may not require two unique registers, it may benefit
607  // from having two so we should try to provide them.
608  if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
609  return true;
610 
611  // Get the list of callee-saved registers for the target.
612  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
613  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
614 
615  // Get all the available registers in the block.
616  BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
617  &PPC::GPRCRegClass);
618 
619  // We shouldn't use callee-saved registers as scratch registers as they may be
620  // available when looking for a candidate block for shrink wrapping but not
621  // available when the actual prologue/epilogue is being emitted because they
622  // were added as live-in to the prologue block by PrologueEpilogueInserter.
623  for (int i = 0; CSRegs[i]; ++i)
624  BV.reset(CSRegs[i]);
625 
626  // Set the first scratch register to the first available one.
627  if (SR1) {
628  int FirstScratchReg = BV.find_first();
629  *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
630  }
631 
632  // If there is another one available, set the second scratch register to that.
633  // Otherwise, set it to either PPC::NoRegister if this function requires two
634  // or to whatever SR1 is set to if this function doesn't require two.
635  if (SR2) {
636  int SecondScratchReg = BV.find_next(*SR1);
637  if (SecondScratchReg != -1)
638  *SR2 = SecondScratchReg;
639  else
640  *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
641  }
642 
643  // Now that we've done our best to provide both registers, double check
644  // whether we were unable to provide enough.
645  if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U))
646  return false;
647 
648  return true;
649 }
650 
651 // We need a scratch register for spilling LR and for spilling CR. By default,
652 // we use two scratch registers to hide latency. However, if only one scratch
653 // register is available, we can adjust for that by not overlapping the spill
654 // code. However, if we need to realign the stack (i.e. have a base pointer)
655 // and the stack frame is large, we need two scratch registers.
656 bool
657 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
658  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
659  MachineFunction &MF = *(MBB->getParent());
660  bool HasBP = RegInfo->hasBasePointer(MF);
661  unsigned FrameSize = determineFrameLayout(MF, false);
662  int NegFrameSize = -FrameSize;
663  bool IsLargeFrame = !isInt<16>(NegFrameSize);
664  MachineFrameInfo &MFI = MF.getFrameInfo();
665  unsigned MaxAlign = MFI.getMaxAlignment();
666  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
667 
668  return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
669 }
670 
672  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
673 
674  return findScratchRegister(TmpMBB, false,
675  twoUniqueScratchRegsRequired(TmpMBB));
676 }
677 
679  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
680 
681  return findScratchRegister(TmpMBB, true);
682 }
683 
685  MachineBasicBlock &MBB) const {
686  MachineBasicBlock::iterator MBBI = MBB.begin();
687  MachineFrameInfo &MFI = MF.getFrameInfo();
688  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
689  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
690 
691  MachineModuleInfo &MMI = MF.getMMI();
692  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
693  DebugLoc dl;
694  bool needsCFI = MMI.hasDebugInfo() ||
696 
697  // Get processor type.
698  bool isPPC64 = Subtarget.isPPC64();
699  // Get the ABI.
700  bool isSVR4ABI = Subtarget.isSVR4ABI();
701  bool isELFv2ABI = Subtarget.isELFv2ABI();
702  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
703  "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
704 
705  // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
706  // process it.
707  if (!isSVR4ABI)
708  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
709  if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
710  HandleVRSaveUpdate(*MBBI, TII);
711  break;
712  }
713  }
714 
715  // Move MBBI back to the beginning of the prologue block.
716  MBBI = MBB.begin();
717 
718  // Work out frame sizes.
719  unsigned FrameSize = determineFrameLayout(MF);
720  int NegFrameSize = -FrameSize;
721  if (!isInt<32>(NegFrameSize))
722  llvm_unreachable("Unhandled stack size!");
723 
724  if (MFI.isFrameAddressTaken())
726 
727  // Check if the link register (LR) must be saved.
729  bool MustSaveLR = FI->mustSaveLR();
730  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
731  bool MustSaveCR = !MustSaveCRs.empty();
732  // Do we have a frame pointer and/or base pointer for this function?
733  bool HasFP = hasFP(MF);
734  bool HasBP = RegInfo->hasBasePointer(MF);
735  bool HasRedZone = isPPC64 || !isSVR4ABI;
736 
737  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
738  unsigned BPReg = RegInfo->getBaseRegister(MF);
739  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
740  unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
741  unsigned ScratchReg = 0;
742  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
743  // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
744  const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
745  : PPC::MFLR );
746  const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
747  : PPC::STW );
748  const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
749  : PPC::STWU );
750  const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
751  : PPC::STWUX);
752  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
753  : PPC::LIS );
754  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
755  : PPC::ORI );
756  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
757  : PPC::OR );
758  const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
759  : PPC::SUBFC);
760  const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
761  : PPC::SUBFIC);
762 
763  // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
764  // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
765  // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
766  // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
767  assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
768  "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
769 
770  // Using the same bool variable as below to suppress compiler warnings.
771  bool SingleScratchReg =
772  findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
773  &ScratchReg, &TempReg);
774  assert(SingleScratchReg &&
775  "Required number of registers not available in this block");
776 
777  SingleScratchReg = ScratchReg == TempReg;
778 
779  int LROffset = getReturnSaveOffset();
780 
781  int FPOffset = 0;
782  if (HasFP) {
783  if (isSVR4ABI) {
784  MachineFrameInfo &MFI = MF.getFrameInfo();
785  int FPIndex = FI->getFramePointerSaveIndex();
786  assert(FPIndex && "No Frame Pointer Save Slot!");
787  FPOffset = MFI.getObjectOffset(FPIndex);
788  } else {
789  FPOffset = getFramePointerSaveOffset();
790  }
791  }
792 
793  int BPOffset = 0;
794  if (HasBP) {
795  if (isSVR4ABI) {
796  MachineFrameInfo &MFI = MF.getFrameInfo();
797  int BPIndex = FI->getBasePointerSaveIndex();
798  assert(BPIndex && "No Base Pointer Save Slot!");
799  BPOffset = MFI.getObjectOffset(BPIndex);
800  } else {
801  BPOffset = getBasePointerSaveOffset();
802  }
803  }
804 
805  int PBPOffset = 0;
806  if (FI->usesPICBase()) {
807  MachineFrameInfo &MFI = MF.getFrameInfo();
808  int PBPIndex = FI->getPICBasePointerSaveIndex();
809  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
810  PBPOffset = MFI.getObjectOffset(PBPIndex);
811  }
812 
813  // Get stack alignments.
814  unsigned MaxAlign = MFI.getMaxAlignment();
815  if (HasBP && MaxAlign > 1)
816  assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
817  "Invalid alignment!");
818 
819  // Frames of 32KB & larger require special handling because they cannot be
820  // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
821  bool isLargeFrame = !isInt<16>(NegFrameSize);
822 
823  assert((isPPC64 || !MustSaveCR) &&
824  "Prologue CR saving supported only in 64-bit mode");
825 
826  // If we need to spill the CR and the LR but we don't have two separate
827  // registers available, we must spill them one at a time
828  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
829  // In the ELFv2 ABI, we are not required to save all CR fields.
830  // If only one or two CR fields are clobbered, it is more efficient to use
831  // mfocrf to selectively save just those fields, because mfocrf has short
832  // latency compares to mfcr.
833  unsigned MfcrOpcode = PPC::MFCR8;
834  unsigned CrState = RegState::ImplicitKill;
835  if (isELFv2ABI && MustSaveCRs.size() == 1) {
836  MfcrOpcode = PPC::MFOCRF8;
837  CrState = RegState::Kill;
838  }
839  MachineInstrBuilder MIB =
840  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
841  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
842  MIB.addReg(MustSaveCRs[i], CrState);
843  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
844  .addReg(TempReg, getKillRegState(true))
845  .addImm(8)
846  .addReg(SPReg);
847  }
848 
849  if (MustSaveLR)
850  BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
851 
852  if (MustSaveCR &&
853  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
854  // In the ELFv2 ABI, we are not required to save all CR fields.
855  // If only one or two CR fields are clobbered, it is more efficient to use
856  // mfocrf to selectively save just those fields, because mfocrf has short
857  // latency compares to mfcr.
858  unsigned MfcrOpcode = PPC::MFCR8;
859  unsigned CrState = RegState::ImplicitKill;
860  if (isELFv2ABI && MustSaveCRs.size() == 1) {
861  MfcrOpcode = PPC::MFOCRF8;
862  CrState = RegState::Kill;
863  }
864  MachineInstrBuilder MIB =
865  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
866  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
867  MIB.addReg(MustSaveCRs[i], CrState);
868  }
869 
870  if (HasRedZone) {
871  if (HasFP)
872  BuildMI(MBB, MBBI, dl, StoreInst)
873  .addReg(FPReg)
874  .addImm(FPOffset)
875  .addReg(SPReg);
876  if (FI->usesPICBase())
877  BuildMI(MBB, MBBI, dl, StoreInst)
878  .addReg(PPC::R30)
879  .addImm(PBPOffset)
880  .addReg(SPReg);
881  if (HasBP)
882  BuildMI(MBB, MBBI, dl, StoreInst)
883  .addReg(BPReg)
884  .addImm(BPOffset)
885  .addReg(SPReg);
886  }
887 
888  if (MustSaveLR)
889  BuildMI(MBB, MBBI, dl, StoreInst)
890  .addReg(ScratchReg, getKillRegState(true))
891  .addImm(LROffset)
892  .addReg(SPReg);
893 
894  if (MustSaveCR &&
895  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
896  assert(HasRedZone && "A red zone is always available on PPC64");
897  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
898  .addReg(TempReg, getKillRegState(true))
899  .addImm(8)
900  .addReg(SPReg);
901  }
902 
903  // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
904  if (!FrameSize)
905  return;
906 
907  // Adjust stack pointer: r1 += NegFrameSize.
908  // If there is a preferred stack alignment, align R1 now
909 
910  if (HasBP && HasRedZone) {
911  // Save a copy of r1 as the base pointer.
912  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
913  .addReg(SPReg)
914  .addReg(SPReg);
915  }
916 
917  // Have we generated a STUX instruction to claim stack frame? If so,
918  // the negated frame size will be placed in ScratchReg.
919  bool HasSTUX = false;
920 
921  // This condition must be kept in sync with canUseAsPrologue.
922  if (HasBP && MaxAlign > 1) {
923  if (isPPC64)
924  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
925  .addReg(SPReg)
926  .addImm(0)
927  .addImm(64 - Log2_32(MaxAlign));
928  else // PPC32...
929  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
930  .addReg(SPReg)
931  .addImm(0)
932  .addImm(32 - Log2_32(MaxAlign))
933  .addImm(31);
934  if (!isLargeFrame) {
935  BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
936  .addReg(ScratchReg, RegState::Kill)
937  .addImm(NegFrameSize);
938  } else {
939  assert(!SingleScratchReg && "Only a single scratch reg available");
940  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
941  .addImm(NegFrameSize >> 16);
942  BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
943  .addReg(TempReg, RegState::Kill)
944  .addImm(NegFrameSize & 0xFFFF);
945  BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
946  .addReg(ScratchReg, RegState::Kill)
947  .addReg(TempReg, RegState::Kill);
948  }
949 
950  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
951  .addReg(SPReg, RegState::Kill)
952  .addReg(SPReg)
953  .addReg(ScratchReg);
954  HasSTUX = true;
955 
956  } else if (!isLargeFrame) {
957  BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
958  .addReg(SPReg)
959  .addImm(NegFrameSize)
960  .addReg(SPReg);
961 
962  } else {
963  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
964  .addImm(NegFrameSize >> 16);
965  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
966  .addReg(ScratchReg, RegState::Kill)
967  .addImm(NegFrameSize & 0xFFFF);
968  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
969  .addReg(SPReg, RegState::Kill)
970  .addReg(SPReg)
971  .addReg(ScratchReg);
972  HasSTUX = true;
973  }
974 
975  if (!HasRedZone) {
976  assert(!isPPC64 && "A red zone is always available on PPC64");
977  if (HasSTUX) {
978  // The negated frame size is in ScratchReg, and the SPReg has been
979  // decremented by the frame size: SPReg = old SPReg + ScratchReg.
980  // Since FPOffset, PBPOffset, etc. are relative to the beginning of
981  // the stack frame (i.e. the old SP), ideally, we would put the old
982  // SP into a register and use it as the base for the stores. The
983  // problem is that the only available register may be ScratchReg,
984  // which could be R0, and R0 cannot be used as a base address.
985 
986  // First, set ScratchReg to the old SP. This may need to be modified
987  // later.
988  BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
989  .addReg(ScratchReg, RegState::Kill)
990  .addReg(SPReg);
991 
992  if (ScratchReg == PPC::R0) {
993  // R0 cannot be used as a base register, but it can be used as an
994  // index in a store-indexed.
995  int LastOffset = 0;
996  if (HasFP) {
997  // R0 += (FPOffset-LastOffset).
998  // Need addic, since addi treats R0 as 0.
999  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1000  .addReg(ScratchReg)
1001  .addImm(FPOffset-LastOffset);
1002  LastOffset = FPOffset;
1003  // Store FP into *R0.
1004  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1005  .addReg(FPReg, RegState::Kill) // Save FP.
1006  .addReg(PPC::ZERO)
1007  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1008  }
1009  if (FI->usesPICBase()) {
1010  // R0 += (PBPOffset-LastOffset).
1011  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1012  .addReg(ScratchReg)
1013  .addImm(PBPOffset-LastOffset);
1014  LastOffset = PBPOffset;
1015  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1016  .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1017  .addReg(PPC::ZERO)
1018  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1019  }
1020  if (HasBP) {
1021  // R0 += (BPOffset-LastOffset).
1022  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1023  .addReg(ScratchReg)
1024  .addImm(BPOffset-LastOffset);
1025  LastOffset = BPOffset;
1026  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1027  .addReg(BPReg, RegState::Kill) // Save BP.
1028  .addReg(PPC::ZERO)
1029  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1030  // BP = R0-LastOffset
1031  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1032  .addReg(ScratchReg, RegState::Kill)
1033  .addImm(-LastOffset);
1034  }
1035  } else {
1036  // ScratchReg is not R0, so use it as the base register. It is
1037  // already set to the old SP, so we can use the offsets directly.
1038 
1039  // Now that the stack frame has been allocated, save all the necessary
1040  // registers using ScratchReg as the base address.
1041  if (HasFP)
1042  BuildMI(MBB, MBBI, dl, StoreInst)
1043  .addReg(FPReg)
1044  .addImm(FPOffset)
1045  .addReg(ScratchReg);
1046  if (FI->usesPICBase())
1047  BuildMI(MBB, MBBI, dl, StoreInst)
1048  .addReg(PPC::R30)
1049  .addImm(PBPOffset)
1050  .addReg(ScratchReg);
1051  if (HasBP) {
1052  BuildMI(MBB, MBBI, dl, StoreInst)
1053  .addReg(BPReg)
1054  .addImm(BPOffset)
1055  .addReg(ScratchReg);
1056  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1057  .addReg(ScratchReg, RegState::Kill)
1058  .addReg(ScratchReg);
1059  }
1060  }
1061  } else {
1062  // The frame size is a known 16-bit constant (fitting in the immediate
1063  // field of STWU). To be here we have to be compiling for PPC32.
1064  // Since the SPReg has been decreased by FrameSize, add it back to each
1065  // offset.
1066  if (HasFP)
1067  BuildMI(MBB, MBBI, dl, StoreInst)
1068  .addReg(FPReg)
1069  .addImm(FrameSize + FPOffset)
1070  .addReg(SPReg);
1071  if (FI->usesPICBase())
1072  BuildMI(MBB, MBBI, dl, StoreInst)
1073  .addReg(PPC::R30)
1074  .addImm(FrameSize + PBPOffset)
1075  .addReg(SPReg);
1076  if (HasBP) {
1077  BuildMI(MBB, MBBI, dl, StoreInst)
1078  .addReg(BPReg)
1079  .addImm(FrameSize + BPOffset)
1080  .addReg(SPReg);
1081  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1082  .addReg(SPReg)
1083  .addImm(FrameSize);
1084  }
1085  }
1086  }
1087 
1088  // Add Call Frame Information for the instructions we generated above.
1089  if (needsCFI) {
1090  unsigned CFIIndex;
1091 
1092  if (HasBP) {
1093  // Define CFA in terms of BP. Do this in preference to using FP/SP,
1094  // because if the stack needed aligning then CFA won't be at a fixed
1095  // offset from FP/SP.
1096  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1097  CFIIndex = MF.addFrameInst(
1099  } else {
1100  // Adjust the definition of CFA to account for the change in SP.
1101  assert(NegFrameSize);
1102  CFIIndex = MF.addFrameInst(
1103  MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
1104  }
1105  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1106  .addCFIIndex(CFIIndex);
1107 
1108  if (HasFP) {
1109  // Describe where FP was saved, at a fixed offset from CFA.
1110  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1111  CFIIndex = MF.addFrameInst(
1112  MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
1113  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1114  .addCFIIndex(CFIIndex);
1115  }
1116 
1117  if (FI->usesPICBase()) {
1118  // Describe where FP was saved, at a fixed offset from CFA.
1119  unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
1120  CFIIndex = MF.addFrameInst(
1121  MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
1122  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1123  .addCFIIndex(CFIIndex);
1124  }
1125 
1126  if (HasBP) {
1127  // Describe where BP was saved, at a fixed offset from CFA.
1128  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1129  CFIIndex = MF.addFrameInst(
1130  MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
1131  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1132  .addCFIIndex(CFIIndex);
1133  }
1134 
1135  if (MustSaveLR) {
1136  // Describe where LR was saved, at a fixed offset from CFA.
1137  unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1138  CFIIndex = MF.addFrameInst(
1139  MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
1140  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1141  .addCFIIndex(CFIIndex);
1142  }
1143  }
1144 
1145  // If there is a frame pointer, copy R1 into R31
1146  if (HasFP) {
1147  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1148  .addReg(SPReg)
1149  .addReg(SPReg);
1150 
1151  if (!HasBP && needsCFI) {
1152  // Change the definition of CFA from SP+offset to FP+offset, because SP
1153  // will change at every alloca.
1154  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1155  unsigned CFIIndex = MF.addFrameInst(
1157 
1158  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1159  .addCFIIndex(CFIIndex);
1160  }
1161  }
1162 
1163  if (needsCFI) {
1164  // Describe where callee saved registers were saved, at fixed offsets from
1165  // CFA.
1166  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1167  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1168  unsigned Reg = CSI[I].getReg();
1169  if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1170 
1171  // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
1172  // subregisters of CR2. We just need to emit a move of CR2.
1173  if (PPC::CRBITRCRegClass.contains(Reg))
1174  continue;
1175 
1176  // For SVR4, don't emit a move for the CR spill slot if we haven't
1177  // spilled CRs.
1178  if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1179  && !MustSaveCR)
1180  continue;
1181 
1182  // For 64-bit SVR4 when we have spilled CRs, the spill location
1183  // is SP+8, not a frame-relative slot.
1184  if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1185  // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1186  // the whole CR word. In the ELFv2 ABI, every CR that was
1187  // actually saved gets its own CFI record.
1188  unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1189  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1190  nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
1191  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1192  .addCFIIndex(CFIIndex);
1193  continue;
1194  }
1195 
1196  int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());
1197  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1198  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
1199  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1200  .addCFIIndex(CFIIndex);
1201  }
1202  }
1203 }
1204 
1206  MachineBasicBlock &MBB) const {
1208  DebugLoc dl;
1209 
1210  if (MBBI != MBB.end())
1211  dl = MBBI->getDebugLoc();
1212 
1213  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1214  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1215 
1216  // Get alignment info so we know how to restore the SP.
1217  const MachineFrameInfo &MFI = MF.getFrameInfo();
1218 
1219  // Get the number of bytes allocated from the FrameInfo.
1220  int FrameSize = MFI.getStackSize();
1221 
1222  // Get processor type.
1223  bool isPPC64 = Subtarget.isPPC64();
1224  // Get the ABI.
1225  bool isSVR4ABI = Subtarget.isSVR4ABI();
1226 
1227  // Check if the link register (LR) has been saved.
1229  bool MustSaveLR = FI->mustSaveLR();
1230  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1231  bool MustSaveCR = !MustSaveCRs.empty();
1232  // Do we have a frame pointer and/or base pointer for this function?
1233  bool HasFP = hasFP(MF);
1234  bool HasBP = RegInfo->hasBasePointer(MF);
1235  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1236 
1237  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1238  unsigned BPReg = RegInfo->getBaseRegister(MF);
1239  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1240  unsigned ScratchReg = 0;
1241  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1242  const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1243  : PPC::MTLR );
1244  const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1245  : PPC::LWZ );
1246  const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1247  : PPC::LIS );
1248  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1249  : PPC::OR );
1250  const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1251  : PPC::ORI );
1252  const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1253  : PPC::ADDI );
1254  const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1255  : PPC::ADD4 );
1256 
1257  int LROffset = getReturnSaveOffset();
1258 
1259  int FPOffset = 0;
1260 
1261  // Using the same bool variable as below to suppress compiler warnings.
1262  bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
1263  &TempReg);
1264  assert(SingleScratchReg &&
1265  "Could not find an available scratch register");
1266 
1267  SingleScratchReg = ScratchReg == TempReg;
1268 
1269  if (HasFP) {
1270  if (isSVR4ABI) {
1271  int FPIndex = FI->getFramePointerSaveIndex();
1272  assert(FPIndex && "No Frame Pointer Save Slot!");
1273  FPOffset = MFI.getObjectOffset(FPIndex);
1274  } else {
1275  FPOffset = getFramePointerSaveOffset();
1276  }
1277  }
1278 
1279  int BPOffset = 0;
1280  if (HasBP) {
1281  if (isSVR4ABI) {
1282  int BPIndex = FI->getBasePointerSaveIndex();
1283  assert(BPIndex && "No Base Pointer Save Slot!");
1284  BPOffset = MFI.getObjectOffset(BPIndex);
1285  } else {
1286  BPOffset = getBasePointerSaveOffset();
1287  }
1288  }
1289 
1290  int PBPOffset = 0;
1291  if (FI->usesPICBase()) {
1292  int PBPIndex = FI->getPICBasePointerSaveIndex();
1293  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1294  PBPOffset = MFI.getObjectOffset(PBPIndex);
1295  }
1296 
1297  bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1298 
1299  if (IsReturnBlock) {
1300  unsigned RetOpcode = MBBI->getOpcode();
1301  bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1302  RetOpcode == PPC::TCRETURNdi ||
1303  RetOpcode == PPC::TCRETURNai ||
1304  RetOpcode == PPC::TCRETURNri8 ||
1305  RetOpcode == PPC::TCRETURNdi8 ||
1306  RetOpcode == PPC::TCRETURNai8;
1307 
1308  if (UsesTCRet) {
1309  int MaxTCRetDelta = FI->getTailCallSPDelta();
1310  MachineOperand &StackAdjust = MBBI->getOperand(1);
1311  assert(StackAdjust.isImm() && "Expecting immediate value.");
1312  // Adjust stack pointer.
1313  int StackAdj = StackAdjust.getImm();
1314  int Delta = StackAdj - MaxTCRetDelta;
1315  assert((Delta >= 0) && "Delta must be positive");
1316  if (MaxTCRetDelta>0)
1317  FrameSize += (StackAdj +Delta);
1318  else
1319  FrameSize += StackAdj;
1320  }
1321  }
1322 
1323  // Frames of 32KB & larger require special handling because they cannot be
1324  // indexed into with a simple LD/LWZ immediate offset operand.
1325  bool isLargeFrame = !isInt<16>(FrameSize);
1326 
1327  // On targets without red zone, the SP needs to be restored last, so that
1328  // all live contents of the stack frame are upwards of the SP. This means
1329  // that we cannot restore SP just now, since there may be more registers
1330  // to restore from the stack frame (e.g. R31). If the frame size is not
1331  // a simple immediate value, we will need a spare register to hold the
1332  // restored SP. If the frame size is known and small, we can simply adjust
1333  // the offsets of the registers to be restored, and still use SP to restore
1334  // them. In such case, the final update of SP will be to add the frame
1335  // size to it.
1336  // To simplify the code, set RBReg to the base register used to restore
1337  // values from the stack, and set SPAdd to the value that needs to be added
1338  // to the SP at the end. The default values are as if red zone was present.
1339  unsigned RBReg = SPReg;
1340  unsigned SPAdd = 0;
1341 
1342  if (FrameSize) {
1343  // In the prologue, the loaded (or persistent) stack pointer value is
1344  // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
1345  // zone add this offset back now.
1346 
1347  // If this function contained a fastcc call and GuaranteedTailCallOpt is
1348  // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1349  // call which invalidates the stack pointer value in SP(0). So we use the
1350  // value of R31 in this case.
1351  if (FI->hasFastCall()) {
1352  assert(HasFP && "Expecting a valid frame pointer.");
1353  if (!HasRedZone)
1354  RBReg = FPReg;
1355  if (!isLargeFrame) {
1356  BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1357  .addReg(FPReg).addImm(FrameSize);
1358  } else {
1359  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1360  .addImm(FrameSize >> 16);
1361  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1362  .addReg(ScratchReg, RegState::Kill)
1363  .addImm(FrameSize & 0xFFFF);
1364  BuildMI(MBB, MBBI, dl, AddInst)
1365  .addReg(RBReg)
1366  .addReg(FPReg)
1367  .addReg(ScratchReg);
1368  }
1369  } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
1370  if (HasRedZone) {
1371  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1372  .addReg(SPReg)
1373  .addImm(FrameSize);
1374  } else {
1375  // Make sure that adding FrameSize will not overflow the max offset
1376  // size.
1377  assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1378  "Local offsets should be negative");
1379  SPAdd = FrameSize;
1380  FPOffset += FrameSize;
1381  BPOffset += FrameSize;
1382  PBPOffset += FrameSize;
1383  }
1384  } else {
1385  // We don't want to use ScratchReg as a base register, because it
1386  // could happen to be R0. Use FP instead, but make sure to preserve it.
1387  if (!HasRedZone) {
1388  // If FP is not saved, copy it to ScratchReg.
1389  if (!HasFP)
1390  BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1391  .addReg(FPReg)
1392  .addReg(FPReg);
1393  RBReg = FPReg;
1394  }
1395  BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
1396  .addImm(0)
1397  .addReg(SPReg);
1398  }
1399  }
1400  assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
1401  // If there is no red zone, ScratchReg may be needed for holding a useful
1402  // value (although not the base register). Make sure it is not overwritten
1403  // too early.
1404 
1405  assert((isPPC64 || !MustSaveCR) &&
1406  "Epilogue CR restoring supported only in 64-bit mode");
1407 
1408  // If we need to restore both the LR and the CR and we only have one
1409  // available scratch register, we must do them one at a time.
1410  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1411  // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
1412  // is live here.
1413  assert(HasRedZone && "Expecting red zone");
1414  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1415  .addImm(8)
1416  .addReg(SPReg);
1417  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1418  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1419  .addReg(TempReg, getKillRegState(i == e-1));
1420  }
1421 
1422  // Delay restoring of the LR if ScratchReg is needed. This is ok, since
1423  // LR is stored in the caller's stack frame. ScratchReg will be needed
1424  // if RBReg is anything other than SP. We shouldn't use ScratchReg as
1425  // a base register anyway, because it may happen to be R0.
1426  bool LoadedLR = false;
1427  if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1428  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1429  .addImm(LROffset+SPAdd)
1430  .addReg(RBReg);
1431  LoadedLR = true;
1432  }
1433 
1434  if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1435  // This will only occur for PPC64.
1436  assert(isPPC64 && "Expecting 64-bit mode");
1437  assert(RBReg == SPReg && "Should be using SP as a base register");
1438  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1439  .addImm(8)
1440  .addReg(RBReg);
1441  }
1442 
1443  if (HasFP) {
1444  // If there is red zone, restore FP directly, since SP has already been
1445  // restored. Otherwise, restore the value of FP into ScratchReg.
1446  if (HasRedZone || RBReg == SPReg)
1447  BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1448  .addImm(FPOffset)
1449  .addReg(SPReg);
1450  else
1451  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1452  .addImm(FPOffset)
1453  .addReg(RBReg);
1454  }
1455 
1456  if (FI->usesPICBase())
1457  BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)
1458  .addImm(PBPOffset)
1459  .addReg(RBReg);
1460 
1461  if (HasBP)
1462  BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1463  .addImm(BPOffset)
1464  .addReg(RBReg);
1465 
1466  // There is nothing more to be loaded from the stack, so now we can
1467  // restore SP: SP = RBReg + SPAdd.
1468  if (RBReg != SPReg || SPAdd != 0) {
1469  assert(!HasRedZone && "This should not happen with red zone");
1470  // If SPAdd is 0, generate a copy.
1471  if (SPAdd == 0)
1472  BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1473  .addReg(RBReg)
1474  .addReg(RBReg);
1475  else
1476  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1477  .addReg(RBReg)
1478  .addImm(SPAdd);
1479 
1480  assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
1481  if (RBReg == FPReg)
1482  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1483  .addReg(ScratchReg)
1484  .addReg(ScratchReg);
1485 
1486  // Now load the LR from the caller's stack frame.
1487  if (MustSaveLR && !LoadedLR)
1488  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1489  .addImm(LROffset)
1490  .addReg(SPReg);
1491  }
1492 
1493  if (MustSaveCR &&
1494  !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1495  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1496  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1497  .addReg(TempReg, getKillRegState(i == e-1));
1498 
1499  if (MustSaveLR)
1500  BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1501 
1502  // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1503  // call optimization
1504  if (IsReturnBlock) {
1505  unsigned RetOpcode = MBBI->getOpcode();
1507  (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1510  unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1511 
1512  if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1513  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1514  .addReg(SPReg).addImm(CallerAllocatedAmt);
1515  } else {
1516  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1517  .addImm(CallerAllocatedAmt >> 16);
1518  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1519  .addReg(ScratchReg, RegState::Kill)
1520  .addImm(CallerAllocatedAmt & 0xFFFF);
1521  BuildMI(MBB, MBBI, dl, AddInst)
1522  .addReg(SPReg)
1523  .addReg(FPReg)
1524  .addReg(ScratchReg);
1525  }
1526  } else {
1527  createTailCallBranchInstr(MBB);
1528  }
1529  }
1530 }
1531 
1532 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const {
1534  DebugLoc dl;
1535 
1536  if (MBBI != MBB.end())
1537  dl = MBBI->getDebugLoc();
1538 
1539  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1540 
1541  // Create branch instruction for pseudo tail call return instruction
1542  unsigned RetOpcode = MBBI->getOpcode();
1543  if (RetOpcode == PPC::TCRETURNdi) {
1544  MBBI = MBB.getLastNonDebugInstr();
1545  MachineOperand &JumpTarget = MBBI->getOperand(0);
1546  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1547  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1548  } else if (RetOpcode == PPC::TCRETURNri) {
1549  MBBI = MBB.getLastNonDebugInstr();
1550  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1551  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1552  } else if (RetOpcode == PPC::TCRETURNai) {
1553  MBBI = MBB.getLastNonDebugInstr();
1554  MachineOperand &JumpTarget = MBBI->getOperand(0);
1555  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1556  } else if (RetOpcode == PPC::TCRETURNdi8) {
1557  MBBI = MBB.getLastNonDebugInstr();
1558  MachineOperand &JumpTarget = MBBI->getOperand(0);
1559  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1560  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1561  } else if (RetOpcode == PPC::TCRETURNri8) {
1562  MBBI = MBB.getLastNonDebugInstr();
1563  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1564  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1565  } else if (RetOpcode == PPC::TCRETURNai8) {
1566  MBBI = MBB.getLastNonDebugInstr();
1567  MachineOperand &JumpTarget = MBBI->getOperand(0);
1568  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1569  }
1570 }
1571 
1573  BitVector &SavedRegs,
1574  RegScavenger *RS) const {
1575  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1576 
1577  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1578 
1579  // Save and clear the LR state.
1581  unsigned LR = RegInfo->getRARegister();
1582  FI->setMustSaveLR(MustSaveLR(MF, LR));
1583  SavedRegs.reset(LR);
1584 
1585  // Save R31 if necessary
1586  int FPSI = FI->getFramePointerSaveIndex();
1587  bool isPPC64 = Subtarget.isPPC64();
1588  bool isDarwinABI = Subtarget.isDarwinABI();
1589  MachineFrameInfo &MFI = MF.getFrameInfo();
1590 
1591  // If the frame pointer save index hasn't been defined yet.
1592  if (!FPSI && needsFP(MF)) {
1593  // Find out what the fix offset of the frame pointer save area.
1594  int FPOffset = getFramePointerSaveOffset();
1595  // Allocate the frame index for frame pointer save area.
1596  FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1597  // Save the result.
1598  FI->setFramePointerSaveIndex(FPSI);
1599  }
1600 
1601  int BPSI = FI->getBasePointerSaveIndex();
1602  if (!BPSI && RegInfo->hasBasePointer(MF)) {
1603  int BPOffset = getBasePointerSaveOffset();
1604  // Allocate the frame index for the base pointer save area.
1605  BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1606  // Save the result.
1607  FI->setBasePointerSaveIndex(BPSI);
1608  }
1609 
1610  // Reserve stack space for the PIC Base register (R30).
1611  // Only used in SVR4 32-bit.
1612  if (FI->usesPICBase()) {
1613  int PBPSI = MFI.CreateFixedObject(4, -8, true);
1614  FI->setPICBasePointerSaveIndex(PBPSI);
1615  }
1616 
1617  // Make sure we don't explicitly spill r31, because, for example, we have
1618  // some inline asm which explicity clobbers it, when we otherwise have a
1619  // frame pointer and are using r31's spill slot for the prologue/epilogue
1620  // code. Same goes for the base pointer and the PIC base register.
1621  if (needsFP(MF))
1622  SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
1623  if (RegInfo->hasBasePointer(MF))
1624  SavedRegs.reset(RegInfo->getBaseRegister(MF));
1625  if (FI->usesPICBase())
1626  SavedRegs.reset(PPC::R30);
1627 
1628  // Reserve stack space to move the linkage area to in case of a tail call.
1629  int TCSPDelta = 0;
1631  (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1632  MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1633  }
1634 
1635  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1636  // function uses CR 2, 3, or 4.
1637  if (!isPPC64 && !isDarwinABI &&
1638  (SavedRegs.test(PPC::CR2) ||
1639  SavedRegs.test(PPC::CR3) ||
1640  SavedRegs.test(PPC::CR4))) {
1641  int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1642  FI->setCRSpillFrameIndex(FrameIdx);
1643  }
1644 }
1645 
1647  RegScavenger *RS) const {
1648  // Early exit if not using the SVR4 ABI.
1649  if (!Subtarget.isSVR4ABI()) {
1650  addScavengingSpillSlot(MF, RS);
1651  return;
1652  }
1653 
1654  // Get callee saved register information.
1655  MachineFrameInfo &MFI = MF.getFrameInfo();
1656  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1657 
1658  // If the function is shrink-wrapped, and if the function has a tail call, the
1659  // tail call might not be in the new RestoreBlock, so real branch instruction
1660  // won't be generated by emitEpilogue(), because shrink-wrap has chosen new
1661  // RestoreBlock. So we handle this case here.
1662  if (MFI.getSavePoint() && MFI.hasTailCall()) {
1663  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
1664  for (MachineBasicBlock &MBB : MF) {
1665  if (MBB.isReturnBlock() && (&MBB) != RestoreBlock)
1666  createTailCallBranchInstr(MBB);
1667  }
1668  }
1669 
1670  // Early exit if no callee saved registers are modified!
1671  if (CSI.empty() && !needsFP(MF)) {
1672  addScavengingSpillSlot(MF, RS);
1673  return;
1674  }
1675 
1676  unsigned MinGPR = PPC::R31;
1677  unsigned MinG8R = PPC::X31;
1678  unsigned MinFPR = PPC::F31;
1679  unsigned MinVR = PPC::V31;
1680 
1681  bool HasGPSaveArea = false;
1682  bool HasG8SaveArea = false;
1683  bool HasFPSaveArea = false;
1684  bool HasVRSAVESaveArea = false;
1685  bool HasVRSaveArea = false;
1686 
1691 
1692  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1693  unsigned Reg = CSI[i].getReg();
1694  if (PPC::GPRCRegClass.contains(Reg)) {
1695  HasGPSaveArea = true;
1696 
1697  GPRegs.push_back(CSI[i]);
1698 
1699  if (Reg < MinGPR) {
1700  MinGPR = Reg;
1701  }
1702  } else if (PPC::G8RCRegClass.contains(Reg)) {
1703  HasG8SaveArea = true;
1704 
1705  G8Regs.push_back(CSI[i]);
1706 
1707  if (Reg < MinG8R) {
1708  MinG8R = Reg;
1709  }
1710  } else if (PPC::F8RCRegClass.contains(Reg)) {
1711  HasFPSaveArea = true;
1712 
1713  FPRegs.push_back(CSI[i]);
1714 
1715  if (Reg < MinFPR) {
1716  MinFPR = Reg;
1717  }
1718  } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1719  PPC::CRRCRegClass.contains(Reg)) {
1720  ; // do nothing, as we already know whether CRs are spilled
1721  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1722  HasVRSAVESaveArea = true;
1723  } else if (PPC::VRRCRegClass.contains(Reg)) {
1724  HasVRSaveArea = true;
1725 
1726  VRegs.push_back(CSI[i]);
1727 
1728  if (Reg < MinVR) {
1729  MinVR = Reg;
1730  }
1731  } else {
1732  llvm_unreachable("Unknown RegisterClass!");
1733  }
1734  }
1735 
1737  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1738 
1739  int64_t LowerBound = 0;
1740 
1741  // Take into account stack space reserved for tail calls.
1742  int TCSPDelta = 0;
1744  (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1745  LowerBound = TCSPDelta;
1746  }
1747 
1748  // The Floating-point register save area is right below the back chain word
1749  // of the previous stack frame.
1750  if (HasFPSaveArea) {
1751  for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1752  int FI = FPRegs[i].getFrameIdx();
1753 
1754  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1755  }
1756 
1757  LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1758  }
1759 
1760  // Check whether the frame pointer register is allocated. If so, make sure it
1761  // is spilled to the correct offset.
1762  if (needsFP(MF)) {
1763  int FI = PFI->getFramePointerSaveIndex();
1764  assert(FI && "No Frame Pointer Save Slot!");
1765  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1766  // FP is R31/X31, so no need to update MinGPR/MinG8R.
1767  HasGPSaveArea = true;
1768  }
1769 
1770  if (PFI->usesPICBase()) {
1771  int FI = PFI->getPICBasePointerSaveIndex();
1772  assert(FI && "No PIC Base Pointer Save Slot!");
1773  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1774 
1775  MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
1776  HasGPSaveArea = true;
1777  }
1778 
1779  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1780  if (RegInfo->hasBasePointer(MF)) {
1781  int FI = PFI->getBasePointerSaveIndex();
1782  assert(FI && "No Base Pointer Save Slot!");
1783  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1784 
1785  unsigned BP = RegInfo->getBaseRegister(MF);
1786  if (PPC::G8RCRegClass.contains(BP)) {
1787  MinG8R = std::min<unsigned>(MinG8R, BP);
1788  HasG8SaveArea = true;
1789  } else if (PPC::GPRCRegClass.contains(BP)) {
1790  MinGPR = std::min<unsigned>(MinGPR, BP);
1791  HasGPSaveArea = true;
1792  }
1793  }
1794 
1795  // General register save area starts right below the Floating-point
1796  // register save area.
1797  if (HasGPSaveArea || HasG8SaveArea) {
1798  // Move general register save area spill slots down, taking into account
1799  // the size of the Floating-point register save area.
1800  for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1801  int FI = GPRegs[i].getFrameIdx();
1802 
1803  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1804  }
1805 
1806  // Move general register save area spill slots down, taking into account
1807  // the size of the Floating-point register save area.
1808  for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1809  int FI = G8Regs[i].getFrameIdx();
1810 
1811  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1812  }
1813 
1814  unsigned MinReg =
1815  std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1816  TRI->getEncodingValue(MinG8R));
1817 
1818  if (Subtarget.isPPC64()) {
1819  LowerBound -= (31 - MinReg + 1) * 8;
1820  } else {
1821  LowerBound -= (31 - MinReg + 1) * 4;
1822  }
1823  }
1824 
1825  // For 32-bit only, the CR save area is below the general register
1826  // save area. For 64-bit SVR4, the CR save area is addressed relative
1827  // to the stack pointer and hence does not need an adjustment here.
1828  // Only CR2 (the first nonvolatile spilled) has an associated frame
1829  // index so that we have a single uniform save area.
1830  if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1831  // Adjust the frame index of the CR spill slot.
1832  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1833  unsigned Reg = CSI[i].getReg();
1834 
1835  if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1836  // Leave Darwin logic as-is.
1837  || (!Subtarget.isSVR4ABI() &&
1838  (PPC::CRBITRCRegClass.contains(Reg) ||
1839  PPC::CRRCRegClass.contains(Reg)))) {
1840  int FI = CSI[i].getFrameIdx();
1841 
1842  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1843  }
1844  }
1845 
1846  LowerBound -= 4; // The CR save area is always 4 bytes long.
1847  }
1848 
1849  if (HasVRSAVESaveArea) {
1850  // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1851  // which have the VRSAVE register class?
1852  // Adjust the frame index of the VRSAVE spill slot.
1853  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1854  unsigned Reg = CSI[i].getReg();
1855 
1856  if (PPC::VRSAVERCRegClass.contains(Reg)) {
1857  int FI = CSI[i].getFrameIdx();
1858 
1859  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1860  }
1861  }
1862 
1863  LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1864  }
1865 
1866  if (HasVRSaveArea) {
1867  // Insert alignment padding, we need 16-byte alignment. Note: for postive
1868  // number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since
1869  // we are using negative number here (the stack grows downward). We should
1870  // use formula : y = x & (~(n-1)). Where x is the size before aligning, n
1871  // is the alignment size ( n = 16 here) and y is the size after aligning.
1872  assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
1873  LowerBound &= ~(15);
1874 
1875  for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1876  int FI = VRegs[i].getFrameIdx();
1877 
1878  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1879  }
1880  }
1881 
1882  addScavengingSpillSlot(MF, RS);
1883 }
1884 
1885 void
1887  RegScavenger *RS) const {
1888  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1889  // a large stack, which will require scavenging a register to materialize a
1890  // large offset.
1891 
1892  // We need to have a scavenger spill slot for spills if the frame size is
1893  // large. In case there is no free register for large-offset addressing,
1894  // this slot is used for the necessary emergency spill. Also, we need the
1895  // slot for dynamic stack allocations.
1896 
1897  // The scavenger might be invoked if the frame offset does not fit into
1898  // the 16-bit immediate. We don't know the complete frame size here
1899  // because we've not yet computed callee-saved register spills or the
1900  // needed alignment padding.
1901  unsigned StackSize = determineFrameLayout(MF, false, true);
1902  MachineFrameInfo &MFI = MF.getFrameInfo();
1903  if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1904  hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1905  const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
1906  const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
1907  const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
1908  const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
1909  unsigned Size = TRI.getSpillSize(RC);
1910  unsigned Align = TRI.getSpillAlignment(RC);
1911  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1912 
1913  // Might we have over-aligned allocas?
1914  bool HasAlVars = MFI.hasVarSizedObjects() &&
1916 
1917  // These kinds of spills might need two registers.
1918  if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1919  RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1920 
1921  }
1922 }
1923 
1924 bool
1927  const std::vector<CalleeSavedInfo> &CSI,
1928  const TargetRegisterInfo *TRI) const {
1929 
1930  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1931  // Return false otherwise to maintain pre-existing behavior.
1932  if (!Subtarget.isSVR4ABI())
1933  return false;
1934 
1935  MachineFunction *MF = MBB.getParent();
1936  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1937  DebugLoc DL;
1938  bool CRSpilled = false;
1939  MachineInstrBuilder CRMIB;
1940 
1941  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1942  unsigned Reg = CSI[i].getReg();
1943  // Only Darwin actually uses the VRSAVE register, but it can still appear
1944  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1945  // Darwin, ignore it.
1946  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1947  continue;
1948 
1949  // CR2 through CR4 are the nonvolatile CR fields.
1950  bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1951 
1952  // Add the callee-saved register as live-in; it's killed at the spill.
1953  MBB.addLiveIn(Reg);
1954 
1955  if (CRSpilled && IsCRField) {
1956  CRMIB.addReg(Reg, RegState::ImplicitKill);
1957  continue;
1958  }
1959 
1960  // Insert the spill to the stack frame.
1961  if (IsCRField) {
1962  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1963  if (Subtarget.isPPC64()) {
1964  // The actual spill will happen at the start of the prologue.
1965  FuncInfo->addMustSaveCR(Reg);
1966  } else {
1967  CRSpilled = true;
1968  FuncInfo->setSpillsCR();
1969 
1970  // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1971  // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1972  CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1973  .addReg(Reg, RegState::ImplicitKill);
1974 
1975  MBB.insert(MI, CRMIB);
1976  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1977  .addReg(PPC::R12,
1978  getKillRegState(true)),
1979  CSI[i].getFrameIdx()));
1980  }
1981  } else {
1982  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1983  TII.storeRegToStackSlot(MBB, MI, Reg, true,
1984  CSI[i].getFrameIdx(), RC, TRI);
1985  }
1986  }
1987  return true;
1988 }
1989 
1990 static void
1991 restoreCRs(bool isPPC64, bool is31,
1992  bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1994  const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1995 
1996  MachineFunction *MF = MBB.getParent();
1997  const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
1998  DebugLoc DL;
1999  unsigned RestoreOp, MoveReg;
2000 
2001  if (isPPC64)
2002  // This is handled during epilogue generation.
2003  return;
2004  else {
2005  // 32-bit: FP-relative
2006  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
2007  PPC::R12),
2008  CSI[CSIIndex].getFrameIdx()));
2009  RestoreOp = PPC::MTOCRF;
2010  MoveReg = PPC::R12;
2011  }
2012 
2013  if (CR2Spilled)
2014  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2015  .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2016 
2017  if (CR3Spilled)
2018  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2019  .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2020 
2021  if (CR4Spilled)
2022  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2023  .addReg(MoveReg, getKillRegState(true)));
2024 }
2025 
2029  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2031  I->getOpcode() == PPC::ADJCALLSTACKUP) {
2032  // Add (actually subtract) back the amount the callee popped on return.
2033  if (int CalleeAmt = I->getOperand(1).getImm()) {
2034  bool is64Bit = Subtarget.isPPC64();
2035  CalleeAmt *= -1;
2036  unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2037  unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2038  unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2039  unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2040  unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2041  unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2042  const DebugLoc &dl = I->getDebugLoc();
2043 
2044  if (isInt<16>(CalleeAmt)) {
2045  BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2046  .addReg(StackReg, RegState::Kill)
2047  .addImm(CalleeAmt);
2048  } else {
2050  BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2051  .addImm(CalleeAmt >> 16);
2052  BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2053  .addReg(TmpReg, RegState::Kill)
2054  .addImm(CalleeAmt & 0xFFFF);
2055  BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2056  .addReg(StackReg, RegState::Kill)
2057  .addReg(TmpReg);
2058  }
2059  }
2060  }
2061  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
2062  return MBB.erase(I);
2063 }
2064 
2065 bool
2068  std::vector<CalleeSavedInfo> &CSI,
2069  const TargetRegisterInfo *TRI) const {
2070 
2071  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
2072  // Return false otherwise to maintain pre-existing behavior.
2073  if (!Subtarget.isSVR4ABI())
2074  return false;
2075 
2076  MachineFunction *MF = MBB.getParent();
2077  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
2078  bool CR2Spilled = false;
2079  bool CR3Spilled = false;
2080  bool CR4Spilled = false;
2081  unsigned CSIIndex = 0;
2082 
2083  // Initialize insertion-point logic; we will be restoring in reverse
2084  // order of spill.
2085  MachineBasicBlock::iterator I = MI, BeforeI = I;
2086  bool AtStart = I == MBB.begin();
2087 
2088  if (!AtStart)
2089  --BeforeI;
2090 
2091  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2092  unsigned Reg = CSI[i].getReg();
2093 
2094  // Only Darwin actually uses the VRSAVE register, but it can still appear
2095  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
2096  // Darwin, ignore it.
2097  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
2098  continue;
2099 
2100  if (Reg == PPC::CR2) {
2101  CR2Spilled = true;
2102  // The spill slot is associated only with CR2, which is the
2103  // first nonvolatile spilled. Save it here.
2104  CSIIndex = i;
2105  continue;
2106  } else if (Reg == PPC::CR3) {
2107  CR3Spilled = true;
2108  continue;
2109  } else if (Reg == PPC::CR4) {
2110  CR4Spilled = true;
2111  continue;
2112  } else {
2113  // When we first encounter a non-CR register after seeing at
2114  // least one CR register, restore all spilled CRs together.
2115  if ((CR2Spilled || CR3Spilled || CR4Spilled)
2116  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2117  bool is31 = needsFP(*MF);
2118  restoreCRs(Subtarget.isPPC64(), is31,
2119  CR2Spilled, CR3Spilled, CR4Spilled,
2120  MBB, I, CSI, CSIIndex);
2121  CR2Spilled = CR3Spilled = CR4Spilled = false;
2122  }
2123 
2124  // Default behavior for non-CR saves.
2125  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2126  TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
2127  RC, TRI);
2128  assert(I != MBB.begin() &&
2129  "loadRegFromStackSlot didn't insert any code!");
2130  }
2131 
2132  // Insert in reverse order.
2133  if (AtStart)
2134  I = MBB.begin();
2135  else {
2136  I = BeforeI;
2137  ++I;
2138  }
2139  }
2140 
2141  // If we haven't yet spilled the CRs, do so now.
2142  if (CR2Spilled || CR3Spilled || CR4Spilled) {
2143  bool is31 = needsFP(*MF);
2144  restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
2145  MBB, I, CSI, CSIIndex);
2146  }
2147 
2148  return true;
2149 }
2150 
2152  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
2153  MF.getSubtarget<PPCSubtarget>().isPPC64());
2154 }
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
static const unsigned GPRegs[]
bool hasDebugInfo() const
Returns true if valid debug info is present.
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addMustSaveCR(unsigned Reg)
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:404
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool test(unsigned Idx) const
Definition: BitVector.h:502
void setFramePointerSaveIndex(int Idx)
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:935
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static const MCPhysReg VRegs[32]
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
A debug info location.
Definition: DebugLoc.h:34
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
An instruction for reading from memory.
Definition: Instructions.h:164
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:391
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
MachineBasicBlock * getRestorePoint() const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
Reg
All possible values of the reg field in the ModR/M byte.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
def_iterator def_begin(unsigned RegNo) const
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool isELFv2ABI() const
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:189
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
Definition: Instructions.h:306
bool hasBasePointer(const MachineFunction &MF) const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getBaseRegister(const MachineFunction &MF) const
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
static const unsigned G8Regs[]
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:384
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
BitVector & reset()
Definition: BitVector.h:439
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:186
Iterator for intrusive lists based on ilist_node.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:179
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:674
Information about stack frame layout on the target.
bool isDarwinABI() const
Definition: PPCSubtarget.h:304
static bool spillsVRSAVE(const MachineFunction &MF)
static bool hasSpills(const MachineFunction &MF)
int64_t getImm() const
unsigned getMinReservedArea() const
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:505
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:531
static bool spillsCR(const MachineFunction &MF)
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:278
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void setPICBasePointerSaveIndex(int Idx)
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:96
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
void setMaxCallFrameSize(unsigned S)
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool needsFP(const MachineFunction &MF) const
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock * getSavePoint() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:285
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:305
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
void replaceFPWithRealFP(MachineFunction &MF) const
This class contains meta information specific to a module.