LLVM  8.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
16 #include "HexagonFrameLowering.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
80 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
98 
99 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
101  cl::desc("Use the DFA based hazard recognizer."));
102 
103 /// Constants for Hexagon instructions.
104 const int Hexagon_MEMW_OFFSET_MAX = 4095;
105 const int Hexagon_MEMW_OFFSET_MIN = -4096;
106 const int Hexagon_MEMD_OFFSET_MAX = 8191;
107 const int Hexagon_MEMD_OFFSET_MIN = -8192;
108 const int Hexagon_MEMH_OFFSET_MAX = 2047;
109 const int Hexagon_MEMH_OFFSET_MIN = -2048;
110 const int Hexagon_MEMB_OFFSET_MAX = 1023;
111 const int Hexagon_MEMB_OFFSET_MIN = -1024;
112 const int Hexagon_ADDI_OFFSET_MAX = 32767;
113 const int Hexagon_ADDI_OFFSET_MIN = -32768;
114 
115 // Pin the vtable to this file.
116 void HexagonInstrInfo::anchor() {}
117 
119  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
120  Subtarget(ST) {}
121 
122 static bool isIntRegForSubInst(unsigned Reg) {
123  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
124  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
125 }
126 
127 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
128  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
129  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
130 }
131 
132 /// Calculate number of instructions excluding the debug instructions.
135  unsigned Count = 0;
136  for (; MIB != MIE; ++MIB) {
137  if (!MIB->isDebugInstr())
138  ++Count;
139  }
140  return Count;
141 }
142 
143 /// Find the hardware loop instruction used to set-up the specified loop.
144 /// On Hexagon, we have two instructions used to set-up the hardware loop
145 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
146 /// to indicate the end of a loop.
148  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
149  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
150  unsigned LOOPi;
151  unsigned LOOPr;
152  if (EndLoopOp == Hexagon::ENDLOOP0) {
153  LOOPi = Hexagon::J2_loop0i;
154  LOOPr = Hexagon::J2_loop0r;
155  } else { // EndLoopOp == Hexagon::EndLOOP1
156  LOOPi = Hexagon::J2_loop1i;
157  LOOPr = Hexagon::J2_loop1r;
158  }
159 
160  // The loop set-up instruction will be in a predecessor block
161  for (MachineBasicBlock *PB : BB->predecessors()) {
162  // If this has been visited, already skip it.
163  if (!Visited.insert(PB).second)
164  continue;
165  if (PB == BB)
166  continue;
167  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
168  unsigned Opc = I->getOpcode();
169  if (Opc == LOOPi || Opc == LOOPr)
170  return &*I;
171  // We've reached a different loop, which means the loop01 has been
172  // removed.
173  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
174  return nullptr;
175  }
176  // Check the predecessors for the LOOP instruction.
177  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
178  return Loop;
179  }
180  return nullptr;
181 }
182 
183 /// Gather register def/uses from MI.
184 /// This treats possible (predicated) defs as actually happening ones
185 /// (conservatively).
186 static inline void parseOperands(const MachineInstr &MI,
188  Defs.clear();
189  Uses.clear();
190 
191  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
192  const MachineOperand &MO = MI.getOperand(i);
193 
194  if (!MO.isReg())
195  continue;
196 
197  unsigned Reg = MO.getReg();
198  if (!Reg)
199  continue;
200 
201  if (MO.isUse())
202  Uses.push_back(MO.getReg());
203 
204  if (MO.isDef())
205  Defs.push_back(MO.getReg());
206  }
207 }
208 
209 // Position dependent, so check twice for swap.
210 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
211  switch (Ga) {
213  default:
214  return false;
215  case HexagonII::HSIG_L1:
216  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
217  case HexagonII::HSIG_L2:
218  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
219  Gb == HexagonII::HSIG_A);
220  case HexagonII::HSIG_S1:
221  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
222  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
223  case HexagonII::HSIG_S2:
224  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
225  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
226  Gb == HexagonII::HSIG_A);
227  case HexagonII::HSIG_A:
228  return (Gb == HexagonII::HSIG_A);
230  return (Gb == HexagonII::HSIG_Compound);
231  }
232  return false;
233 }
234 
235 /// isLoadFromStackSlot - If the specified machine instruction is a direct
236 /// load from a stack slot, return the virtual or physical register number of
237 /// the destination along with the FrameIndex of the loaded stack slot. If
238 /// not, return 0. This predicate must return 0 if the instruction has
239 /// any side effects other than loading from the stack slot.
241  int &FrameIndex) const {
242  switch (MI.getOpcode()) {
243  default:
244  break;
245  case Hexagon::L2_loadri_io:
246  case Hexagon::L2_loadrd_io:
247  case Hexagon::V6_vL32b_ai:
248  case Hexagon::V6_vL32b_nt_ai:
249  case Hexagon::V6_vL32Ub_ai:
250  case Hexagon::LDriw_pred:
251  case Hexagon::LDriw_ctr:
252  case Hexagon::PS_vloadrq_ai:
253  case Hexagon::PS_vloadrw_ai:
254  case Hexagon::PS_vloadrw_nt_ai: {
255  const MachineOperand OpFI = MI.getOperand(1);
256  if (!OpFI.isFI())
257  return 0;
258  const MachineOperand OpOff = MI.getOperand(2);
259  if (!OpOff.isImm() || OpOff.getImm() != 0)
260  return 0;
261  FrameIndex = OpFI.getIndex();
262  return MI.getOperand(0).getReg();
263  }
264 
265  case Hexagon::L2_ploadrit_io:
266  case Hexagon::L2_ploadrif_io:
267  case Hexagon::L2_ploadrdt_io:
268  case Hexagon::L2_ploadrdf_io: {
269  const MachineOperand OpFI = MI.getOperand(2);
270  if (!OpFI.isFI())
271  return 0;
272  const MachineOperand OpOff = MI.getOperand(3);
273  if (!OpOff.isImm() || OpOff.getImm() != 0)
274  return 0;
275  FrameIndex = OpFI.getIndex();
276  return MI.getOperand(0).getReg();
277  }
278  }
279 
280  return 0;
281 }
282 
283 /// isStoreToStackSlot - If the specified machine instruction is a direct
284 /// store to a stack slot, return the virtual or physical register number of
285 /// the source reg along with the FrameIndex of the loaded stack slot. If
286 /// not, return 0. This predicate must return 0 if the instruction has
287 /// any side effects other than storing to the stack slot.
289  int &FrameIndex) const {
290  switch (MI.getOpcode()) {
291  default:
292  break;
293  case Hexagon::S2_storerb_io:
294  case Hexagon::S2_storerh_io:
295  case Hexagon::S2_storeri_io:
296  case Hexagon::S2_storerd_io:
297  case Hexagon::V6_vS32b_ai:
298  case Hexagon::V6_vS32Ub_ai:
299  case Hexagon::STriw_pred:
300  case Hexagon::STriw_ctr:
301  case Hexagon::PS_vstorerq_ai:
302  case Hexagon::PS_vstorerw_ai: {
303  const MachineOperand &OpFI = MI.getOperand(0);
304  if (!OpFI.isFI())
305  return 0;
306  const MachineOperand &OpOff = MI.getOperand(1);
307  if (!OpOff.isImm() || OpOff.getImm() != 0)
308  return 0;
309  FrameIndex = OpFI.getIndex();
310  return MI.getOperand(2).getReg();
311  }
312 
313  case Hexagon::S2_pstorerbt_io:
314  case Hexagon::S2_pstorerbf_io:
315  case Hexagon::S2_pstorerht_io:
316  case Hexagon::S2_pstorerhf_io:
317  case Hexagon::S2_pstorerit_io:
318  case Hexagon::S2_pstorerif_io:
319  case Hexagon::S2_pstorerdt_io:
320  case Hexagon::S2_pstorerdf_io: {
321  const MachineOperand &OpFI = MI.getOperand(1);
322  if (!OpFI.isFI())
323  return 0;
324  const MachineOperand &OpOff = MI.getOperand(2);
325  if (!OpOff.isImm() || OpOff.getImm() != 0)
326  return 0;
327  FrameIndex = OpFI.getIndex();
328  return MI.getOperand(3).getReg();
329  }
330  }
331 
332  return 0;
333 }
334 
335 /// This function checks if the instruction or bundle of instructions
336 /// has load from stack slot and returns frameindex and machine memory
337 /// operand of that instruction if true.
339  const MachineInstr &MI,
341  if (MI.isBundle()) {
342  const MachineBasicBlock *MBB = MI.getParent();
344  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
345  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
346  return true;
347  return false;
348  }
349 
350  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
351 }
352 
353 /// This function checks if the instruction or bundle of instructions
354 /// has store to stack slot and returns frameindex and machine memory
355 /// operand of that instruction if true.
357  const MachineInstr &MI,
359  if (MI.isBundle()) {
360  const MachineBasicBlock *MBB = MI.getParent();
362  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
363  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
364  return true;
365  return false;
366  }
367 
368  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
369 }
370 
371 /// This function can analyze one/two way branching only and should (mostly) be
372 /// called by target independent side.
373 /// First entry is always the opcode of the branching instruction, except when
374 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
375 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
376 /// e.g. Jump_c p will have
377 /// Cond[0] = Jump_c
378 /// Cond[1] = p
379 /// HW-loop ENDLOOP:
380 /// Cond[0] = ENDLOOP
381 /// Cond[1] = MBB
382 /// New value jump:
383 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
384 /// Cond[1] = R
385 /// Cond[2] = Imm
387  MachineBasicBlock *&TBB,
388  MachineBasicBlock *&FBB,
390  bool AllowModify) const {
391  TBB = nullptr;
392  FBB = nullptr;
393  Cond.clear();
394 
395  // If the block has no terminators, it just falls into the block after it.
397  if (I == MBB.instr_begin())
398  return false;
399 
400  // A basic block may looks like this:
401  //
402  // [ insn
403  // EH_LABEL
404  // insn
405  // insn
406  // insn
407  // EH_LABEL
408  // insn ]
409  //
410  // It has two succs but does not have a terminator
411  // Don't know how to handle it.
412  do {
413  --I;
414  if (I->isEHLabel())
415  // Don't analyze EH branches.
416  return true;
417  } while (I != MBB.instr_begin());
418 
419  I = MBB.instr_end();
420  --I;
421 
422  while (I->isDebugInstr()) {
423  if (I == MBB.instr_begin())
424  return false;
425  --I;
426  }
427 
428  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
429  I->getOperand(0).isMBB();
430  // Delete the J2_jump if it's equivalent to a fall-through.
431  if (AllowModify && JumpToBlock &&
432  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
433  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
434  I->eraseFromParent();
435  I = MBB.instr_end();
436  if (I == MBB.instr_begin())
437  return false;
438  --I;
439  }
440  if (!isUnpredicatedTerminator(*I))
441  return false;
442 
443  // Get the last instruction in the block.
444  MachineInstr *LastInst = &*I;
445  MachineInstr *SecondLastInst = nullptr;
446  // Find one more terminator if present.
447  while (true) {
448  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
449  if (!SecondLastInst)
450  SecondLastInst = &*I;
451  else
452  // This is a third branch.
453  return true;
454  }
455  if (I == MBB.instr_begin())
456  break;
457  --I;
458  }
459 
460  int LastOpcode = LastInst->getOpcode();
461  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
462  // If the branch target is not a basic block, it could be a tail call.
463  // (It is, if the target is a function.)
464  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
465  return true;
466  if (SecLastOpcode == Hexagon::J2_jump &&
467  !SecondLastInst->getOperand(0).isMBB())
468  return true;
469 
470  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
471  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
472 
473  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
474  return true;
475 
476  // If there is only one terminator instruction, process it.
477  if (LastInst && !SecondLastInst) {
478  if (LastOpcode == Hexagon::J2_jump) {
479  TBB = LastInst->getOperand(0).getMBB();
480  return false;
481  }
482  if (isEndLoopN(LastOpcode)) {
483  TBB = LastInst->getOperand(0).getMBB();
484  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
485  Cond.push_back(LastInst->getOperand(0));
486  return false;
487  }
488  if (LastOpcodeHasJMP_c) {
489  TBB = LastInst->getOperand(1).getMBB();
490  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
491  Cond.push_back(LastInst->getOperand(0));
492  return false;
493  }
494  // Only supporting rr/ri versions of new-value jumps.
495  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
496  TBB = LastInst->getOperand(2).getMBB();
497  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
498  Cond.push_back(LastInst->getOperand(0));
499  Cond.push_back(LastInst->getOperand(1));
500  return false;
501  }
502  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
503  << " with one jump\n";);
504  // Otherwise, don't know what this is.
505  return true;
506  }
507 
508  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
509  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
510  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
511  if (!SecondLastInst->getOperand(1).isMBB())
512  return true;
513  TBB = SecondLastInst->getOperand(1).getMBB();
514  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
515  Cond.push_back(SecondLastInst->getOperand(0));
516  FBB = LastInst->getOperand(0).getMBB();
517  return false;
518  }
519 
520  // Only supporting rr/ri versions of new-value jumps.
521  if (SecLastOpcodeHasNVJump &&
522  (SecondLastInst->getNumExplicitOperands() == 3) &&
523  (LastOpcode == Hexagon::J2_jump)) {
524  TBB = SecondLastInst->getOperand(2).getMBB();
525  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
526  Cond.push_back(SecondLastInst->getOperand(0));
527  Cond.push_back(SecondLastInst->getOperand(1));
528  FBB = LastInst->getOperand(0).getMBB();
529  return false;
530  }
531 
532  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
533  // executed, so remove it.
534  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
535  TBB = SecondLastInst->getOperand(0).getMBB();
536  I = LastInst->getIterator();
537  if (AllowModify)
538  I->eraseFromParent();
539  return false;
540  }
541 
542  // If the block ends with an ENDLOOP, and J2_jump, handle it.
543  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
544  TBB = SecondLastInst->getOperand(0).getMBB();
545  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
546  Cond.push_back(SecondLastInst->getOperand(0));
547  FBB = LastInst->getOperand(0).getMBB();
548  return false;
549  }
550  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
551  << " with two jumps";);
552  // Otherwise, can't handle this.
553  return true;
554 }
555 
557  int *BytesRemoved) const {
558  assert(!BytesRemoved && "code size not handled");
559 
560  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
562  unsigned Count = 0;
563  while (I != MBB.begin()) {
564  --I;
565  if (I->isDebugInstr())
566  continue;
567  // Only removing branches from end of MBB.
568  if (!I->isBranch())
569  return Count;
570  if (Count && (I->getOpcode() == Hexagon::J2_jump))
571  llvm_unreachable("Malformed basic block: unconditional branch not last");
572  MBB.erase(&MBB.back());
573  I = MBB.end();
574  ++Count;
575  }
576  return Count;
577 }
578 
580  MachineBasicBlock *TBB,
581  MachineBasicBlock *FBB,
583  const DebugLoc &DL,
584  int *BytesAdded) const {
585  unsigned BOpc = Hexagon::J2_jump;
586  unsigned BccOpc = Hexagon::J2_jumpt;
587  assert(validateBranchCond(Cond) && "Invalid branching condition");
588  assert(TBB && "insertBranch must not be told to insert a fallthrough");
589  assert(!BytesAdded && "code size not handled");
590 
591  // Check if reverseBranchCondition has asked to reverse this branch
592  // If we want to reverse the branch an odd number of times, we want
593  // J2_jumpf.
594  if (!Cond.empty() && Cond[0].isImm())
595  BccOpc = Cond[0].getImm();
596 
597  if (!FBB) {
598  if (Cond.empty()) {
599  // Due to a bug in TailMerging/CFG Optimization, we need to add a
600  // special case handling of a predicated jump followed by an
601  // unconditional jump. If not, Tail Merging and CFG Optimization go
602  // into an infinite loop.
603  MachineBasicBlock *NewTBB, *NewFBB;
605  auto Term = MBB.getFirstTerminator();
606  if (Term != MBB.end() && isPredicated(*Term) &&
607  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
608  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
610  removeBranch(MBB);
611  return insertBranch(MBB, TBB, nullptr, Cond, DL);
612  }
613  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
614  } else if (isEndLoopN(Cond[0].getImm())) {
615  int EndLoopOp = Cond[0].getImm();
616  assert(Cond[1].isMBB());
617  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
618  // Check for it, and change the BB target if needed.
620  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
621  VisitedBBs);
622  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
623  Loop->getOperand(0).setMBB(TBB);
624  // Add the ENDLOOP after the finding the LOOP0.
625  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
626  } else if (isNewValueJump(Cond[0].getImm())) {
627  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
628  // New value jump
629  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
630  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
631  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
632  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
633  << printMBBReference(MBB););
634  if (Cond[2].isReg()) {
635  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
636  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
637  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
638  } else if(Cond[2].isImm()) {
639  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
640  addImm(Cond[2].getImm()).addMBB(TBB);
641  } else
642  llvm_unreachable("Invalid condition for branching");
643  } else {
644  assert((Cond.size() == 2) && "Malformed cond vector");
645  const MachineOperand &RO = Cond[1];
646  unsigned Flags = getUndefRegState(RO.isUndef());
647  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
648  }
649  return 1;
650  }
651  assert((!Cond.empty()) &&
652  "Cond. cannot be empty when multiple branchings are required");
653  assert((!isNewValueJump(Cond[0].getImm())) &&
654  "NV-jump cannot be inserted with another branch");
655  // Special case for hardware loops. The condition is a basic block.
656  if (isEndLoopN(Cond[0].getImm())) {
657  int EndLoopOp = Cond[0].getImm();
658  assert(Cond[1].isMBB());
659  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
660  // Check for it, and change the BB target if needed.
662  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
663  VisitedBBs);
664  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
665  Loop->getOperand(0).setMBB(TBB);
666  // Add the ENDLOOP after the finding the LOOP0.
667  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
668  } else {
669  const MachineOperand &RO = Cond[1];
670  unsigned Flags = getUndefRegState(RO.isUndef());
671  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
672  }
673  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
674 
675  return 2;
676 }
677 
678 /// Analyze the loop code to find the loop induction variable and compare used
679 /// to compute the number of iterations. Currently, we analyze loop that are
680 /// controlled using hardware loops. In this case, the induction variable
681 /// instruction is null. For all other cases, this function returns true, which
682 /// means we're unable to analyze it.
684  MachineInstr *&IndVarInst,
685  MachineInstr *&CmpInst) const {
686 
687  MachineBasicBlock *LoopEnd = L.getBottomBlock();
689  // We really "analyze" only hardware loops right now.
690  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
691  IndVarInst = nullptr;
692  CmpInst = &*I;
693  return false;
694  }
695  return true;
696 }
697 
698 /// Generate code to reduce the loop iteration by one and check if the loop is
699 /// finished. Return the value/register of the new loop count. this function
700 /// assumes the nth iteration is peeled first.
702  MachineInstr *IndVar, MachineInstr &Cmp,
705  unsigned Iter, unsigned MaxIter) const {
706  // We expect a hardware loop currently. This means that IndVar is set
707  // to null, and the compare is the ENDLOOP instruction.
708  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
709  && "Expecting a hardware loop");
710  MachineFunction *MF = MBB.getParent();
711  DebugLoc DL = Cmp.getDebugLoc();
713  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
714  Cmp.getOperand(0).getMBB(), VisitedBBs);
715  if (!Loop)
716  return 0;
717  // If the loop trip count is a compile-time value, then just change the
718  // value.
719  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
720  Loop->getOpcode() == Hexagon::J2_loop1i) {
721  int64_t Offset = Loop->getOperand(1).getImm();
722  if (Offset <= 1)
723  Loop->eraseFromParent();
724  else
725  Loop->getOperand(1).setImm(Offset - 1);
726  return Offset - 1;
727  }
728  // The loop trip count is a run-time value. We generate code to subtract
729  // one from the trip count, and update the loop instruction.
730  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
731  unsigned LoopCount = Loop->getOperand(1).getReg();
732  // Check if we're done with the loop.
733  unsigned LoopEnd = createVR(MF, MVT::i1);
734  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
735  addReg(LoopCount).addImm(1);
736  unsigned NewLoopCount = createVR(MF, MVT::i32);
737  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
738  addReg(LoopCount).addImm(-1);
739  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
740  // Update the previously generated instructions with the new loop counter.
742  E = PrevInsts.end(); I != E; ++I)
743  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
744  PrevInsts.clear();
745  PrevInsts.push_back(NewCmp);
746  PrevInsts.push_back(NewAdd);
747  // Insert the new loop instruction if this is the last time the loop is
748  // decremented.
749  if (Iter == MaxIter)
750  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
751  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
752  // Delete the old loop instruction.
753  if (Iter == 0)
754  Loop->eraseFromParent();
755  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
756  Cond.push_back(NewCmp->getOperand(0));
757  return NewLoopCount;
758 }
759 
761  unsigned NumCycles, unsigned ExtraPredCycles,
762  BranchProbability Probability) const {
763  return nonDbgBBSize(&MBB) <= 3;
764 }
765 
767  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
768  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
769  const {
770  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
771 }
772 
774  unsigned NumInstrs, BranchProbability Probability) const {
775  return NumInstrs <= 4;
776 }
777 
780  const DebugLoc &DL, unsigned DestReg,
781  unsigned SrcReg, bool KillSrc) const {
782  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
783  unsigned KillFlag = getKillRegState(KillSrc);
784 
785  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
786  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
787  .addReg(SrcReg, KillFlag);
788  return;
789  }
790  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
791  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
792  .addReg(SrcReg, KillFlag);
793  return;
794  }
795  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
796  // Map Pd = Ps to Pd = or(Ps, Ps).
797  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
798  .addReg(SrcReg).addReg(SrcReg, KillFlag);
799  return;
800  }
801  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
802  Hexagon::IntRegsRegClass.contains(SrcReg)) {
803  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
804  .addReg(SrcReg, KillFlag);
805  return;
806  }
807  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
808  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
809  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
810  .addReg(SrcReg, KillFlag);
811  return;
812  }
813  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
814  Hexagon::IntRegsRegClass.contains(SrcReg)) {
815  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
816  .addReg(SrcReg, KillFlag);
817  return;
818  }
819  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
820  Hexagon::IntRegsRegClass.contains(DestReg)) {
821  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
822  .addReg(SrcReg, KillFlag);
823  return;
824  }
825  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
826  Hexagon::PredRegsRegClass.contains(DestReg)) {
827  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
828  .addReg(SrcReg, KillFlag);
829  return;
830  }
831  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
832  Hexagon::IntRegsRegClass.contains(DestReg)) {
833  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
834  .addReg(SrcReg, KillFlag);
835  return;
836  }
837  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
838  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
839  addReg(SrcReg, KillFlag);
840  return;
841  }
842  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
843  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
844  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
845  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
846  .addReg(HiSrc, KillFlag)
847  .addReg(LoSrc, KillFlag);
848  return;
849  }
850  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
851  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
852  .addReg(SrcReg)
853  .addReg(SrcReg, KillFlag);
854  return;
855  }
856  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
857  Hexagon::HvxVRRegClass.contains(DestReg)) {
858  llvm_unreachable("Unimplemented pred to vec");
859  return;
860  }
861  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
862  Hexagon::HvxVRRegClass.contains(SrcReg)) {
863  llvm_unreachable("Unimplemented vec to pred");
864  return;
865  }
866 
867 #ifndef NDEBUG
868  // Show the invalid registers to ease debugging.
869  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
870  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
871 #endif
872  llvm_unreachable("Unimplemented");
873 }
874 
876  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
877  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
878  DebugLoc DL = MBB.findDebugLoc(I);
879  MachineFunction &MF = *MBB.getParent();
880  MachineFrameInfo &MFI = MF.getFrameInfo();
881  unsigned SlotAlign = MFI.getObjectAlignment(FI);
882  unsigned RegAlign = TRI->getSpillAlignment(*RC);
883  unsigned KillFlag = getKillRegState(isKill);
884  bool HasAlloca = MFI.hasVarSizedObjects();
885  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
886 
889  MFI.getObjectSize(FI), SlotAlign);
890 
891  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
892  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
893  .addFrameIndex(FI).addImm(0)
894  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
895  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
896  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
897  .addFrameIndex(FI).addImm(0)
898  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
899  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
900  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
901  .addFrameIndex(FI).addImm(0)
902  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
903  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
904  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
905  .addFrameIndex(FI).addImm(0)
906  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
907  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
908  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
909  .addFrameIndex(FI).addImm(0)
910  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
911  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
912  // If there are variable-sized objects, spills will not be aligned.
913  if (HasAlloca)
914  SlotAlign = HFI.getStackAlignment();
915  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
916  : Hexagon::V6_vS32b_ai;
919  MFI.getObjectSize(FI), SlotAlign);
920  BuildMI(MBB, I, DL, get(Opc))
921  .addFrameIndex(FI).addImm(0)
922  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
923  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
924  // If there are variable-sized objects, spills will not be aligned.
925  if (HasAlloca)
926  SlotAlign = HFI.getStackAlignment();
927  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
928  : Hexagon::PS_vstorerw_ai;
931  MFI.getObjectSize(FI), SlotAlign);
932  BuildMI(MBB, I, DL, get(Opc))
933  .addFrameIndex(FI).addImm(0)
934  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
935  } else {
936  llvm_unreachable("Unimplemented");
937  }
938 }
939 
941  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
942  int FI, const TargetRegisterClass *RC,
943  const TargetRegisterInfo *TRI) const {
944  DebugLoc DL = MBB.findDebugLoc(I);
945  MachineFunction &MF = *MBB.getParent();
946  MachineFrameInfo &MFI = MF.getFrameInfo();
947  unsigned SlotAlign = MFI.getObjectAlignment(FI);
948  unsigned RegAlign = TRI->getSpillAlignment(*RC);
949  bool HasAlloca = MFI.hasVarSizedObjects();
950  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
951 
954  MFI.getObjectSize(FI), SlotAlign);
955 
956  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
957  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
958  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
959  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
960  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
961  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
962  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
963  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
964  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
965  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
966  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
967  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
968  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
969  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
970  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
972  // If there are variable-sized objects, spills will not be aligned.
973  if (HasAlloca)
974  SlotAlign = HFI.getStackAlignment();
975  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
976  : Hexagon::V6_vL32b_ai;
979  MFI.getObjectSize(FI), SlotAlign);
980  BuildMI(MBB, I, DL, get(Opc), DestReg)
981  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
982  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
983  // If there are variable-sized objects, spills will not be aligned.
984  if (HasAlloca)
985  SlotAlign = HFI.getStackAlignment();
986  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
987  : Hexagon::PS_vloadrw_ai;
990  MFI.getObjectSize(FI), SlotAlign);
991  BuildMI(MBB, I, DL, get(Opc), DestReg)
992  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
993  } else {
994  llvm_unreachable("Can't store this register to stack slot");
995  }
996 }
997 
998 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
999  const MachineBasicBlock &B = *MI.getParent();
1000  Regs.addLiveOuts(B);
1001  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1002  for (auto I = B.rbegin(); I != E; ++I)
1003  Regs.stepBackward(*I);
1004 }
1005 
1006 /// expandPostRAPseudo - This function is called for all pseudo instructions
1007 /// that remain after register allocation. Many pseudo instructions are
1008 /// created to help register allocation. This is the place to convert them
1009 /// into real instructions. The target can edit MI in place, or it can insert
1010 /// new instructions and erase MI. The function should return true if
1011 /// anything was changed.
1013  MachineBasicBlock &MBB = *MI.getParent();
1014  MachineFunction &MF = *MBB.getParent();
1016  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1017  DebugLoc DL = MI.getDebugLoc();
1018  unsigned Opc = MI.getOpcode();
1019 
1020  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1021  unsigned Mx = MI.getOperand(MxOp).getReg();
1022  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1023  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1024  .add(MI.getOperand((HasImm ? 5 : 4)));
1025  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1026  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1027  if (HasImm)
1028  MIB.add(MI.getOperand(4));
1029  MIB.addReg(CSx, RegState::Implicit);
1030  MBB.erase(MI);
1031  return true;
1032  };
1033 
1034  switch (Opc) {
1035  case TargetOpcode::COPY: {
1036  MachineOperand &MD = MI.getOperand(0);
1037  MachineOperand &MS = MI.getOperand(1);
1039  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1040  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1041  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1042  }
1043  MBB.erase(MBBI);
1044  return true;
1045  }
1046  case Hexagon::PS_aligna:
1047  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1048  .addReg(HRI.getFrameRegister())
1049  .addImm(-MI.getOperand(1).getImm());
1050  MBB.erase(MI);
1051  return true;
1052  case Hexagon::V6_vassignp: {
1053  unsigned SrcReg = MI.getOperand(1).getReg();
1054  unsigned DstReg = MI.getOperand(0).getReg();
1055  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1056  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1057  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1058  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1059  MBB.erase(MI);
1060  return true;
1061  }
1062  case Hexagon::V6_lo: {
1063  unsigned SrcReg = MI.getOperand(1).getReg();
1064  unsigned DstReg = MI.getOperand(0).getReg();
1065  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1066  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1067  MBB.erase(MI);
1068  MRI.clearKillFlags(SrcSubLo);
1069  return true;
1070  }
1071  case Hexagon::V6_hi: {
1072  unsigned SrcReg = MI.getOperand(1).getReg();
1073  unsigned DstReg = MI.getOperand(0).getReg();
1074  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1075  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1076  MBB.erase(MI);
1077  MRI.clearKillFlags(SrcSubHi);
1078  return true;
1079  }
1080  case Hexagon::PS_vstorerw_ai:
1081  case Hexagon::PS_vstorerwu_ai: {
1082  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1083  unsigned SrcReg = MI.getOperand(2).getReg();
1084  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1085  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1086  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1087  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1088 
1089  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1090  .add(MI.getOperand(0))
1091  .addImm(MI.getOperand(1).getImm())
1092  .addReg(SrcSubLo)
1093  .cloneMemRefs(MI);
1094  MI1New->getOperand(0).setIsKill(false);
1095  BuildMI(MBB, MI, DL, get(NewOpc))
1096  .add(MI.getOperand(0))
1097  // The Vectors are indexed in multiples of vector size.
1098  .addImm(MI.getOperand(1).getImm() + Offset)
1099  .addReg(SrcSubHi)
1100  .cloneMemRefs(MI);
1101  MBB.erase(MI);
1102  return true;
1103  }
1104  case Hexagon::PS_vloadrw_ai:
1105  case Hexagon::PS_vloadrwu_ai: {
1106  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1107  unsigned DstReg = MI.getOperand(0).getReg();
1108  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1109  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1110 
1111  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1112  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1113  .add(MI.getOperand(1))
1114  .addImm(MI.getOperand(2).getImm())
1115  .cloneMemRefs(MI);
1116  MI1New->getOperand(1).setIsKill(false);
1117  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1118  .add(MI.getOperand(1))
1119  // The Vectors are indexed in multiples of vector size.
1120  .addImm(MI.getOperand(2).getImm() + Offset)
1121  .cloneMemRefs(MI);
1122  MBB.erase(MI);
1123  return true;
1124  }
1125  case Hexagon::PS_true: {
1126  unsigned Reg = MI.getOperand(0).getReg();
1127  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1128  .addReg(Reg, RegState::Undef)
1129  .addReg(Reg, RegState::Undef);
1130  MBB.erase(MI);
1131  return true;
1132  }
1133  case Hexagon::PS_false: {
1134  unsigned Reg = MI.getOperand(0).getReg();
1135  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1136  .addReg(Reg, RegState::Undef)
1137  .addReg(Reg, RegState::Undef);
1138  MBB.erase(MI);
1139  return true;
1140  }
1141  case Hexagon::PS_qtrue: {
1142  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1143  .addReg(Hexagon::V0, RegState::Undef)
1144  .addReg(Hexagon::V0, RegState::Undef);
1145  MBB.erase(MI);
1146  return true;
1147  }
1148  case Hexagon::PS_qfalse: {
1149  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1150  .addReg(Hexagon::V0, RegState::Undef)
1151  .addReg(Hexagon::V0, RegState::Undef);
1152  MBB.erase(MI);
1153  return true;
1154  }
1155  case Hexagon::PS_vdd0: {
1156  unsigned Vd = MI.getOperand(0).getReg();
1157  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1158  .addReg(Vd, RegState::Undef)
1159  .addReg(Vd, RegState::Undef);
1160  MBB.erase(MI);
1161  return true;
1162  }
1163  case Hexagon::PS_vmulw: {
1164  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1165  unsigned DstReg = MI.getOperand(0).getReg();
1166  unsigned Src1Reg = MI.getOperand(1).getReg();
1167  unsigned Src2Reg = MI.getOperand(2).getReg();
1168  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1169  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1170  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1171  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1172  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1173  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1174  .addReg(Src1SubHi)
1175  .addReg(Src2SubHi);
1176  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1177  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1178  .addReg(Src1SubLo)
1179  .addReg(Src2SubLo);
1180  MBB.erase(MI);
1181  MRI.clearKillFlags(Src1SubHi);
1182  MRI.clearKillFlags(Src1SubLo);
1183  MRI.clearKillFlags(Src2SubHi);
1184  MRI.clearKillFlags(Src2SubLo);
1185  return true;
1186  }
1187  case Hexagon::PS_vmulw_acc: {
1188  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1189  unsigned DstReg = MI.getOperand(0).getReg();
1190  unsigned Src1Reg = MI.getOperand(1).getReg();
1191  unsigned Src2Reg = MI.getOperand(2).getReg();
1192  unsigned Src3Reg = MI.getOperand(3).getReg();
1193  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1194  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1195  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1196  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1197  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1198  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1199  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1200  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1201  .addReg(Src1SubHi)
1202  .addReg(Src2SubHi)
1203  .addReg(Src3SubHi);
1204  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1205  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1206  .addReg(Src1SubLo)
1207  .addReg(Src2SubLo)
1208  .addReg(Src3SubLo);
1209  MBB.erase(MI);
1210  MRI.clearKillFlags(Src1SubHi);
1211  MRI.clearKillFlags(Src1SubLo);
1212  MRI.clearKillFlags(Src2SubHi);
1213  MRI.clearKillFlags(Src2SubLo);
1214  MRI.clearKillFlags(Src3SubHi);
1215  MRI.clearKillFlags(Src3SubLo);
1216  return true;
1217  }
1218  case Hexagon::PS_pselect: {
1219  const MachineOperand &Op0 = MI.getOperand(0);
1220  const MachineOperand &Op1 = MI.getOperand(1);
1221  const MachineOperand &Op2 = MI.getOperand(2);
1222  const MachineOperand &Op3 = MI.getOperand(3);
1223  unsigned Rd = Op0.getReg();
1224  unsigned Pu = Op1.getReg();
1225  unsigned Rs = Op2.getReg();
1226  unsigned Rt = Op3.getReg();
1227  DebugLoc DL = MI.getDebugLoc();
1228  unsigned K1 = getKillRegState(Op1.isKill());
1229  unsigned K2 = getKillRegState(Op2.isKill());
1230  unsigned K3 = getKillRegState(Op3.isKill());
1231  if (Rd != Rs)
1232  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1233  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1234  .addReg(Rs, K2);
1235  if (Rd != Rt)
1236  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1237  .addReg(Pu, K1)
1238  .addReg(Rt, K3);
1239  MBB.erase(MI);
1240  return true;
1241  }
1242  case Hexagon::PS_vselect: {
1243  const MachineOperand &Op0 = MI.getOperand(0);
1244  const MachineOperand &Op1 = MI.getOperand(1);
1245  const MachineOperand &Op2 = MI.getOperand(2);
1246  const MachineOperand &Op3 = MI.getOperand(3);
1247  LivePhysRegs LiveAtMI(HRI);
1248  getLiveRegsAt(LiveAtMI, MI);
1249  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1250  unsigned PReg = Op1.getReg();
1251  assert(Op1.getSubReg() == 0);
1252  unsigned PState = getRegState(Op1);
1253 
1254  if (Op0.getReg() != Op2.getReg()) {
1255  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1256  : PState;
1257  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1258  .add(Op0)
1259  .addReg(PReg, S)
1260  .add(Op2);
1261  if (IsDestLive)
1262  T.addReg(Op0.getReg(), RegState::Implicit);
1263  IsDestLive = true;
1264  }
1265  if (Op0.getReg() != Op3.getReg()) {
1266  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1267  .add(Op0)
1268  .addReg(PReg, PState)
1269  .add(Op3);
1270  if (IsDestLive)
1271  T.addReg(Op0.getReg(), RegState::Implicit);
1272  }
1273  MBB.erase(MI);
1274  return true;
1275  }
1276  case Hexagon::PS_wselect: {
1277  MachineOperand &Op0 = MI.getOperand(0);
1278  MachineOperand &Op1 = MI.getOperand(1);
1279  MachineOperand &Op2 = MI.getOperand(2);
1280  MachineOperand &Op3 = MI.getOperand(3);
1281  LivePhysRegs LiveAtMI(HRI);
1282  getLiveRegsAt(LiveAtMI, MI);
1283  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1284  unsigned PReg = Op1.getReg();
1285  assert(Op1.getSubReg() == 0);
1286  unsigned PState = getRegState(Op1);
1287 
1288  if (Op0.getReg() != Op2.getReg()) {
1289  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1290  : PState;
1291  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1292  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1293  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1294  .add(Op0)
1295  .addReg(PReg, S)
1296  .add(Op1)
1297  .addReg(SrcHi)
1298  .addReg(SrcLo);
1299  if (IsDestLive)
1300  T.addReg(Op0.getReg(), RegState::Implicit);
1301  IsDestLive = true;
1302  }
1303  if (Op0.getReg() != Op3.getReg()) {
1304  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1305  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1306  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1307  .add(Op0)
1308  .addReg(PReg, PState)
1309  .addReg(SrcHi)
1310  .addReg(SrcLo);
1311  if (IsDestLive)
1312  T.addReg(Op0.getReg(), RegState::Implicit);
1313  }
1314  MBB.erase(MI);
1315  return true;
1316  }
1317 
1318  case Hexagon::PS_tailcall_i:
1319  MI.setDesc(get(Hexagon::J2_jump));
1320  return true;
1321  case Hexagon::PS_tailcall_r:
1322  case Hexagon::PS_jmpret:
1323  MI.setDesc(get(Hexagon::J2_jumpr));
1324  return true;
1325  case Hexagon::PS_jmprett:
1326  MI.setDesc(get(Hexagon::J2_jumprt));
1327  return true;
1328  case Hexagon::PS_jmpretf:
1329  MI.setDesc(get(Hexagon::J2_jumprf));
1330  return true;
1331  case Hexagon::PS_jmprettnewpt:
1332  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1333  return true;
1334  case Hexagon::PS_jmpretfnewpt:
1335  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1336  return true;
1337  case Hexagon::PS_jmprettnew:
1338  MI.setDesc(get(Hexagon::J2_jumprtnew));
1339  return true;
1340  case Hexagon::PS_jmpretfnew:
1341  MI.setDesc(get(Hexagon::J2_jumprfnew));
1342  return true;
1343 
1344  case Hexagon::PS_loadrub_pci:
1345  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1346  case Hexagon::PS_loadrb_pci:
1347  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1348  case Hexagon::PS_loadruh_pci:
1349  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1350  case Hexagon::PS_loadrh_pci:
1351  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1352  case Hexagon::PS_loadri_pci:
1353  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1354  case Hexagon::PS_loadrd_pci:
1355  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1356  case Hexagon::PS_loadrub_pcr:
1357  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1358  case Hexagon::PS_loadrb_pcr:
1359  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1360  case Hexagon::PS_loadruh_pcr:
1361  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1362  case Hexagon::PS_loadrh_pcr:
1363  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1364  case Hexagon::PS_loadri_pcr:
1365  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1366  case Hexagon::PS_loadrd_pcr:
1367  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1368  case Hexagon::PS_storerb_pci:
1369  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1370  case Hexagon::PS_storerh_pci:
1371  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1372  case Hexagon::PS_storerf_pci:
1373  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1374  case Hexagon::PS_storeri_pci:
1375  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1376  case Hexagon::PS_storerd_pci:
1377  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1378  case Hexagon::PS_storerb_pcr:
1379  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1380  case Hexagon::PS_storerh_pcr:
1381  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1382  case Hexagon::PS_storerf_pcr:
1383  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1384  case Hexagon::PS_storeri_pcr:
1385  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1386  case Hexagon::PS_storerd_pcr:
1387  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1388  }
1389 
1390  return false;
1391 }
1392 
1395  MachineBasicBlock &MBB = *MI.getParent();
1396  const DebugLoc &DL = MI.getDebugLoc();
1397  unsigned Opc = MI.getOpcode();
1399 
1400  switch (Opc) {
1401  case Hexagon::V6_vgathermh_pseudo:
1402  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1403  .add(MI.getOperand(1))
1404  .add(MI.getOperand(2))
1405  .add(MI.getOperand(3));
1406  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1407  .add(MI.getOperand(0))
1408  .addImm(0)
1409  .addReg(Hexagon::VTMP);
1410  MBB.erase(MI);
1411  return First.getInstrIterator();
1412 
1413  case Hexagon::V6_vgathermw_pseudo:
1414  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1415  .add(MI.getOperand(1))
1416  .add(MI.getOperand(2))
1417  .add(MI.getOperand(3));
1418  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1419  .add(MI.getOperand(0))
1420  .addImm(0)
1421  .addReg(Hexagon::VTMP);
1422  MBB.erase(MI);
1423  return First.getInstrIterator();
1424 
1425  case Hexagon::V6_vgathermhw_pseudo:
1426  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1427  .add(MI.getOperand(1))
1428  .add(MI.getOperand(2))
1429  .add(MI.getOperand(3));
1430  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1431  .add(MI.getOperand(0))
1432  .addImm(0)
1433  .addReg(Hexagon::VTMP);
1434  MBB.erase(MI);
1435  return First.getInstrIterator();
1436 
1437  case Hexagon::V6_vgathermhq_pseudo:
1438  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1439  .add(MI.getOperand(1))
1440  .add(MI.getOperand(2))
1441  .add(MI.getOperand(3))
1442  .add(MI.getOperand(4));
1443  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1444  .add(MI.getOperand(0))
1445  .addImm(0)
1446  .addReg(Hexagon::VTMP);
1447  MBB.erase(MI);
1448  return First.getInstrIterator();
1449 
1450  case Hexagon::V6_vgathermwq_pseudo:
1451  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1452  .add(MI.getOperand(1))
1453  .add(MI.getOperand(2))
1454  .add(MI.getOperand(3))
1455  .add(MI.getOperand(4));
1456  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1457  .add(MI.getOperand(0))
1458  .addImm(0)
1459  .addReg(Hexagon::VTMP);
1460  MBB.erase(MI);
1461  return First.getInstrIterator();
1462 
1463  case Hexagon::V6_vgathermhwq_pseudo:
1464  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1465  .add(MI.getOperand(1))
1466  .add(MI.getOperand(2))
1467  .add(MI.getOperand(3))
1468  .add(MI.getOperand(4));
1469  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1470  .add(MI.getOperand(0))
1471  .addImm(0)
1472  .addReg(Hexagon::VTMP);
1473  MBB.erase(MI);
1474  return First.getInstrIterator();
1475  }
1476 
1477  return MI.getIterator();
1478 }
1479 
1480 // We indicate that we want to reverse the branch by
1481 // inserting the reversed branching opcode.
1483  SmallVectorImpl<MachineOperand> &Cond) const {
1484  if (Cond.empty())
1485  return true;
1486  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1487  unsigned opcode = Cond[0].getImm();
1488  //unsigned temp;
1489  assert(get(opcode).isBranch() && "Should be a branching condition.");
1490  if (isEndLoopN(opcode))
1491  return true;
1492  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1493  Cond[0].setImm(NewOpcode);
1494  return false;
1495 }
1496 
1499  DebugLoc DL;
1500  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1501 }
1502 
1504  return getAddrMode(MI) == HexagonII::PostInc;
1505 }
1506 
1507 // Returns true if an instruction is predicated irrespective of the predicate
1508 // sense. For example, all of the following will return true.
1509 // if (p0) R1 = add(R2, R3)
1510 // if (!p0) R1 = add(R2, R3)
1511 // if (p0.new) R1 = add(R2, R3)
1512 // if (!p0.new) R1 = add(R2, R3)
1513 // Note: New-value stores are not included here as in the current
1514 // implementation, we don't need to check their predicate sense.
1516  const uint64_t F = MI.getDesc().TSFlags;
1518 }
1519 
1521  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1522  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1523  isEndLoopN(Cond[0].getImm())) {
1524  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1525  return false;
1526  }
1527  int Opc = MI.getOpcode();
1528  assert (isPredicable(MI) && "Expected predicable instruction");
1529  bool invertJump = predOpcodeHasNot(Cond);
1530 
1531  // We have to predicate MI "in place", i.e. after this function returns,
1532  // MI will need to be transformed into a predicated form. To avoid com-
1533  // plicated manipulations with the operands (handling tied operands,
1534  // etc.), build a new temporary instruction, then overwrite MI with it.
1535 
1536  MachineBasicBlock &B = *MI.getParent();
1537  DebugLoc DL = MI.getDebugLoc();
1538  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1539  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1540  unsigned NOp = 0, NumOps = MI.getNumOperands();
1541  while (NOp < NumOps) {
1542  MachineOperand &Op = MI.getOperand(NOp);
1543  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1544  break;
1545  T.add(Op);
1546  NOp++;
1547  }
1548 
1549  unsigned PredReg, PredRegPos, PredRegFlags;
1550  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1551  (void)GotPredReg;
1552  assert(GotPredReg);
1553  T.addReg(PredReg, PredRegFlags);
1554  while (NOp < NumOps)
1555  T.add(MI.getOperand(NOp++));
1556 
1557  MI.setDesc(get(PredOpc));
1558  while (unsigned n = MI.getNumOperands())
1559  MI.RemoveOperand(n-1);
1560  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1561  MI.addOperand(T->getOperand(i));
1562 
1564  B.erase(TI);
1565 
1567  MRI.clearKillFlags(PredReg);
1568  return true;
1569 }
1570 
1572  ArrayRef<MachineOperand> Pred2) const {
1573  // TODO: Fix this
1574  return false;
1575 }
1576 
1578  std::vector<MachineOperand> &Pred) const {
1579  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1580 
1581  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1582  MachineOperand MO = MI.getOperand(oper);
1583  if (MO.isReg()) {
1584  if (!MO.isDef())
1585  continue;
1586  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1587  if (RC == &Hexagon::PredRegsRegClass) {
1588  Pred.push_back(MO);
1589  return true;
1590  }
1591  continue;
1592  } else if (MO.isRegMask()) {
1593  for (unsigned PR : Hexagon::PredRegsRegClass) {
1594  if (!MI.modifiesRegister(PR, &HRI))
1595  continue;
1596  Pred.push_back(MO);
1597  return true;
1598  }
1599  }
1600  }
1601  return false;
1602 }
1603 
1605  if (!MI.getDesc().isPredicable())
1606  return false;
1607 
1608  if (MI.isCall() || isTailCall(MI)) {
1609  if (!Subtarget.usePredicatedCalls())
1610  return false;
1611  }
1612 
1613  // HVX loads are not predicable on v60, but are on v62.
1614  if (!Subtarget.hasV62Ops()) {
1615  switch (MI.getOpcode()) {
1616  case Hexagon::V6_vL32b_ai:
1617  case Hexagon::V6_vL32b_pi:
1618  case Hexagon::V6_vL32b_ppu:
1619  case Hexagon::V6_vL32b_cur_ai:
1620  case Hexagon::V6_vL32b_cur_pi:
1621  case Hexagon::V6_vL32b_cur_ppu:
1622  case Hexagon::V6_vL32b_nt_ai:
1623  case Hexagon::V6_vL32b_nt_pi:
1624  case Hexagon::V6_vL32b_nt_ppu:
1625  case Hexagon::V6_vL32b_tmp_ai:
1626  case Hexagon::V6_vL32b_tmp_pi:
1627  case Hexagon::V6_vL32b_tmp_ppu:
1628  case Hexagon::V6_vL32b_nt_cur_ai:
1629  case Hexagon::V6_vL32b_nt_cur_pi:
1630  case Hexagon::V6_vL32b_nt_cur_ppu:
1631  case Hexagon::V6_vL32b_nt_tmp_ai:
1632  case Hexagon::V6_vL32b_nt_tmp_pi:
1633  case Hexagon::V6_vL32b_nt_tmp_ppu:
1634  return false;
1635  }
1636  }
1637  return true;
1638 }
1639 
1641  const MachineBasicBlock *MBB,
1642  const MachineFunction &MF) const {
1643  // Debug info is never a scheduling boundary. It's necessary to be explicit
1644  // due to the special treatment of IT instructions below, otherwise a
1645  // dbg_value followed by an IT will result in the IT instruction being
1646  // considered a scheduling hazard, which is wrong. It should be the actual
1647  // instruction preceding the dbg_value instruction(s), just like it is
1648  // when debug info is not present.
1649  if (MI.isDebugInstr())
1650  return false;
1651 
1652  // Throwing call is a boundary.
1653  if (MI.isCall()) {
1654  // Don't mess around with no return calls.
1655  if (doesNotReturn(MI))
1656  return true;
1657  // If any of the block's successors is a landing pad, this could be a
1658  // throwing call.
1659  for (auto I : MBB->successors())
1660  if (I->isEHPad())
1661  return true;
1662  }
1663 
1664  // Terminators and labels can't be scheduled around.
1665  if (MI.getDesc().isTerminator() || MI.isPosition())
1666  return true;
1667 
1668  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1669  return true;
1670 
1671  return false;
1672 }
1673 
1674 /// Measure the specified inline asm to determine an approximation of its
1675 /// length.
1676 /// Comments (which run till the next SeparatorString or newline) do not
1677 /// count as an instruction.
1678 /// Any other non-whitespace text is considered an instruction, with
1679 /// multiple instructions separated by SeparatorString or newlines.
1680 /// Variable-length instructions are not handled here; this function
1681 /// may be overloaded in the target code to do that.
1682 /// Hexagon counts the number of ##'s and adjust for that many
1683 /// constant exenders.
1684 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1685  const MCAsmInfo &MAI) const {
1686  StringRef AStr(Str);
1687  // Count the number of instructions in the asm.
1688  bool atInsnStart = true;
1689  unsigned Length = 0;
1690  for (; *Str; ++Str) {
1691  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1692  strlen(MAI.getSeparatorString())) == 0)
1693  atInsnStart = true;
1694  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1695  Length += MAI.getMaxInstLength();
1696  atInsnStart = false;
1697  }
1698  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1699  MAI.getCommentString().size()) == 0)
1700  atInsnStart = false;
1701  }
1702 
1703  // Add to size number of constant extenders seen * 4.
1704  StringRef Occ("##");
1705  Length += AStr.count(Occ)*4;
1706  return Length;
1707 }
1708 
1711  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1712  if (UseDFAHazardRec)
1713  return new HexagonHazardRecognizer(II, this, Subtarget);
1715 }
1716 
1717 /// For a comparison instruction, return the source registers in
1718 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1719 /// compares against in CmpValue. Return true if the comparison instruction
1720 /// can be analyzed.
1721 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1722  unsigned &SrcReg2, int &Mask,
1723  int &Value) const {
1724  unsigned Opc = MI.getOpcode();
1725 
1726  // Set mask and the first source register.
1727  switch (Opc) {
1728  case Hexagon::C2_cmpeq:
1729  case Hexagon::C2_cmpeqp:
1730  case Hexagon::C2_cmpgt:
1731  case Hexagon::C2_cmpgtp:
1732  case Hexagon::C2_cmpgtu:
1733  case Hexagon::C2_cmpgtup:
1734  case Hexagon::C4_cmpneq:
1735  case Hexagon::C4_cmplte:
1736  case Hexagon::C4_cmplteu:
1737  case Hexagon::C2_cmpeqi:
1738  case Hexagon::C2_cmpgti:
1739  case Hexagon::C2_cmpgtui:
1740  case Hexagon::C4_cmpneqi:
1741  case Hexagon::C4_cmplteui:
1742  case Hexagon::C4_cmpltei:
1743  SrcReg = MI.getOperand(1).getReg();
1744  Mask = ~0;
1745  break;
1746  case Hexagon::A4_cmpbeq:
1747  case Hexagon::A4_cmpbgt:
1748  case Hexagon::A4_cmpbgtu:
1749  case Hexagon::A4_cmpbeqi:
1750  case Hexagon::A4_cmpbgti:
1751  case Hexagon::A4_cmpbgtui:
1752  SrcReg = MI.getOperand(1).getReg();
1753  Mask = 0xFF;
1754  break;
1755  case Hexagon::A4_cmpheq:
1756  case Hexagon::A4_cmphgt:
1757  case Hexagon::A4_cmphgtu:
1758  case Hexagon::A4_cmpheqi:
1759  case Hexagon::A4_cmphgti:
1760  case Hexagon::A4_cmphgtui:
1761  SrcReg = MI.getOperand(1).getReg();
1762  Mask = 0xFFFF;
1763  break;
1764  }
1765 
1766  // Set the value/second source register.
1767  switch (Opc) {
1768  case Hexagon::C2_cmpeq:
1769  case Hexagon::C2_cmpeqp:
1770  case Hexagon::C2_cmpgt:
1771  case Hexagon::C2_cmpgtp:
1772  case Hexagon::C2_cmpgtu:
1773  case Hexagon::C2_cmpgtup:
1774  case Hexagon::A4_cmpbeq:
1775  case Hexagon::A4_cmpbgt:
1776  case Hexagon::A4_cmpbgtu:
1777  case Hexagon::A4_cmpheq:
1778  case Hexagon::A4_cmphgt:
1779  case Hexagon::A4_cmphgtu:
1780  case Hexagon::C4_cmpneq:
1781  case Hexagon::C4_cmplte:
1782  case Hexagon::C4_cmplteu:
1783  SrcReg2 = MI.getOperand(2).getReg();
1784  return true;
1785 
1786  case Hexagon::C2_cmpeqi:
1787  case Hexagon::C2_cmpgtui:
1788  case Hexagon::C2_cmpgti:
1789  case Hexagon::C4_cmpneqi:
1790  case Hexagon::C4_cmplteui:
1791  case Hexagon::C4_cmpltei:
1792  case Hexagon::A4_cmpbeqi:
1793  case Hexagon::A4_cmpbgti:
1794  case Hexagon::A4_cmpbgtui:
1795  case Hexagon::A4_cmpheqi:
1796  case Hexagon::A4_cmphgti:
1797  case Hexagon::A4_cmphgtui: {
1798  SrcReg2 = 0;
1799  const MachineOperand &Op2 = MI.getOperand(2);
1800  if (!Op2.isImm())
1801  return false;
1802  Value = MI.getOperand(2).getImm();
1803  return true;
1804  }
1805  }
1806 
1807  return false;
1808 }
1809 
1811  const MachineInstr &MI,
1812  unsigned *PredCost) const {
1813  return getInstrTimingClassLatency(ItinData, MI);
1814 }
1815 
1817  const TargetSubtargetInfo &STI) const {
1818  const InstrItineraryData *II = STI.getInstrItineraryData();
1819  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1820 }
1821 
1822 // Inspired by this pair:
1823 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1824 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1825 // Currently AA considers the addresses in these instructions to be aliasing.
1827  MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1828  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1830  return false;
1831 
1832  // Instructions that are pure loads, not loads and stores like memops are not
1833  // dependent.
1834  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1835  return true;
1836 
1837  // Get the base register in MIa.
1838  unsigned BasePosA, OffsetPosA;
1839  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1840  return false;
1841  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1842  unsigned BaseRegA = BaseA.getReg();
1843  unsigned BaseSubA = BaseA.getSubReg();
1844 
1845  // Get the base register in MIb.
1846  unsigned BasePosB, OffsetPosB;
1847  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1848  return false;
1849  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1850  unsigned BaseRegB = BaseB.getReg();
1851  unsigned BaseSubB = BaseB.getSubReg();
1852 
1853  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1854  return false;
1855 
1856  // Get the access sizes.
1857  unsigned SizeA = getMemAccessSize(MIa);
1858  unsigned SizeB = getMemAccessSize(MIb);
1859 
1860  // Get the offsets. Handle immediates only for now.
1861  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1862  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1863  if (!MIa.getOperand(OffsetPosA).isImm() ||
1864  !MIb.getOperand(OffsetPosB).isImm())
1865  return false;
1866  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1867  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1868 
1869  // This is a mem access with the same base register and known offsets from it.
1870  // Reason about it.
1871  if (OffsetA > OffsetB) {
1872  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1873  return SizeB <= OffDiff;
1874  }
1875  if (OffsetA < OffsetB) {
1876  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1877  return SizeA <= OffDiff;
1878  }
1879 
1880  return false;
1881 }
1882 
1883 /// If the instruction is an increment of a constant value, return the amount.
1885  int &Value) const {
1886  if (isPostIncrement(MI)) {
1887  unsigned BasePos = 0, OffsetPos = 0;
1888  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1889  return false;
1890  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1891  if (OffsetOp.isImm()) {
1892  Value = OffsetOp.getImm();
1893  return true;
1894  }
1895  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1896  const MachineOperand &AddOp = MI.getOperand(2);
1897  if (AddOp.isImm()) {
1898  Value = AddOp.getImm();
1899  return true;
1900  }
1901  }
1902 
1903  return false;
1904 }
1905 
1906 std::pair<unsigned, unsigned>
1908  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1909  TF & HexagonII::MO_Bitmasks);
1910 }
1911 
1914  using namespace HexagonII;
1915 
1916  static const std::pair<unsigned, const char*> Flags[] = {
1917  {MO_PCREL, "hexagon-pcrel"},
1918  {MO_GOT, "hexagon-got"},
1919  {MO_LO16, "hexagon-lo16"},
1920  {MO_HI16, "hexagon-hi16"},
1921  {MO_GPREL, "hexagon-gprel"},
1922  {MO_GDGOT, "hexagon-gdgot"},
1923  {MO_GDPLT, "hexagon-gdplt"},
1924  {MO_IE, "hexagon-ie"},
1925  {MO_IEGOT, "hexagon-iegot"},
1926  {MO_TPREL, "hexagon-tprel"}
1927  };
1928  return makeArrayRef(Flags);
1929 }
1930 
1933  using namespace HexagonII;
1934 
1935  static const std::pair<unsigned, const char*> Flags[] = {
1936  {HMOTF_ConstExtended, "hexagon-ext"}
1937  };
1938  return makeArrayRef(Flags);
1939 }
1940 
1943  const TargetRegisterClass *TRC;
1944  if (VT == MVT::i1) {
1945  TRC = &Hexagon::PredRegsRegClass;
1946  } else if (VT == MVT::i32 || VT == MVT::f32) {
1947  TRC = &Hexagon::IntRegsRegClass;
1948  } else if (VT == MVT::i64 || VT == MVT::f64) {
1949  TRC = &Hexagon::DoubleRegsRegClass;
1950  } else {
1951  llvm_unreachable("Cannot handle this register class");
1952  }
1953 
1954  unsigned NewReg = MRI.createVirtualRegister(TRC);
1955  return NewReg;
1956 }
1957 
1959  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1960 }
1961 
1963  const uint64_t F = MI.getDesc().TSFlags;
1965 }
1966 
1968  return getAddrMode(MI) == HexagonII::BaseImmOffset;
1969 }
1970 
1972  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
1973  !MI.getDesc().mayStore() &&
1974  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
1975  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
1976  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
1977 }
1978 
1979 // Return true if the instruction is a compund branch instruction.
1981  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1982 }
1983 
1984 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1985 // isFPImm and later getFPImm as well.
1987  const uint64_t F = MI.getDesc().TSFlags;
1989  if (isExtended) // Instruction must be extended.
1990  return true;
1991 
1992  unsigned isExtendable =
1994  if (!isExtendable)
1995  return false;
1996 
1997  if (MI.isCall())
1998  return false;
1999 
2000  short ExtOpNum = getCExtOpNum(MI);
2001  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2002  // Use MO operand flags to determine if MO
2003  // has the HMOTF_ConstExtended flag set.
2005  return true;
2006  // If this is a Machine BB address we are talking about, and it is
2007  // not marked as extended, say so.
2008  if (MO.isMBB())
2009  return false;
2010 
2011  // We could be using an instruction with an extendable immediate and shoehorn
2012  // a global address into it. If it is a global address it will be constant
2013  // extended. We do this for COMBINE.
2014  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2015  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2016  return true;
2017 
2018  // If the extendable operand is not 'Immediate' type, the instruction should
2019  // have 'isExtended' flag set.
2020  assert(MO.isImm() && "Extendable operand must be Immediate type");
2021 
2022  int MinValue = getMinValue(MI);
2023  int MaxValue = getMaxValue(MI);
2024  int ImmValue = MO.getImm();
2025 
2026  return (ImmValue < MinValue || ImmValue > MaxValue);
2027 }
2028 
2030  switch (MI.getOpcode()) {
2031  case Hexagon::L4_return:
2032  case Hexagon::L4_return_t:
2033  case Hexagon::L4_return_f:
2034  case Hexagon::L4_return_tnew_pnt:
2035  case Hexagon::L4_return_fnew_pnt:
2036  case Hexagon::L4_return_tnew_pt:
2037  case Hexagon::L4_return_fnew_pt:
2038  return true;
2039  }
2040  return false;
2041 }
2042 
2043 // Return true when ConsMI uses a register defined by ProdMI.
2045  const MachineInstr &ConsMI) const {
2046  if (!ProdMI.getDesc().getNumDefs())
2047  return false;
2048  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2049 
2054 
2055  parseOperands(ProdMI, DefsA, UsesA);
2056  parseOperands(ConsMI, DefsB, UsesB);
2057 
2058  for (auto &RegA : DefsA)
2059  for (auto &RegB : UsesB) {
2060  // True data dependency.
2061  if (RegA == RegB)
2062  return true;
2063 
2065  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2066  if (RegB == *SubRegs)
2067  return true;
2068 
2070  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2071  if (RegA == *SubRegs)
2072  return true;
2073  }
2074 
2075  return false;
2076 }
2077 
2078 // Returns true if the instruction is alread a .cur.
2080  switch (MI.getOpcode()) {
2081  case Hexagon::V6_vL32b_cur_pi:
2082  case Hexagon::V6_vL32b_cur_ai:
2083  return true;
2084  }
2085  return false;
2086 }
2087 
2088 // Returns true, if any one of the operands is a dot new
2089 // insn, whether it is predicated dot new or register dot new.
2091  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2092  return true;
2093 
2094  return false;
2095 }
2096 
2097 /// Symmetrical. See if these two instructions are fit for duplex pair.
2099  const MachineInstr &MIb) const {
2102  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2103 }
2104 
2106  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2107  return true;
2108 
2109  // Multiply
2110  unsigned SchedClass = MI.getDesc().getSchedClass();
2111  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2112 }
2113 
2114 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2115  return (Opcode == Hexagon::ENDLOOP0 ||
2116  Opcode == Hexagon::ENDLOOP1);
2117 }
2118 
2119 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2120  switch(OpType) {
2127  return true;
2128  default:
2129  return false;
2130  }
2131 }
2132 
2134  const MCInstrDesc &MID = MI.getDesc();
2135  const uint64_t F = MID.TSFlags;
2137  return true;
2138 
2139  // TODO: This is largely obsolete now. Will need to be removed
2140  // in consecutive patches.
2141  switch (MI.getOpcode()) {
2142  // PS_fi and PS_fia remain special cases.
2143  case Hexagon::PS_fi:
2144  case Hexagon::PS_fia:
2145  return true;
2146  default:
2147  return false;
2148  }
2149  return false;
2150 }
2151 
2152 // This returns true in two cases:
2153 // - The OP code itself indicates that this is an extended instruction.
2154 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2156  // First check if this is permanently extended op code.
2157  const uint64_t F = MI.getDesc().TSFlags;
2159  return true;
2160  // Use MO operand flags to determine if one of MI's operands
2161  // has HMOTF_ConstExtended flag set.
2162  for (const MachineOperand &MO : MI.operands())
2163  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2164  return true;
2165  return false;
2166 }
2167 
2169  unsigned Opcode = MI.getOpcode();
2170  const uint64_t F = get(Opcode).TSFlags;
2171  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2172 }
2173 
2174 // No V60 HVX VMEM with A_INDIRECT.
2176  const MachineInstr &J) const {
2177  if (!isHVXVec(I))
2178  return false;
2179  if (!I.mayLoad() && !I.mayStore())
2180  return false;
2181  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2182 }
2183 
2185  switch (MI.getOpcode()) {
2186  case Hexagon::J2_callr:
2187  case Hexagon::J2_callrf:
2188  case Hexagon::J2_callrt:
2189  case Hexagon::PS_call_nr:
2190  return true;
2191  }
2192  return false;
2193 }
2194 
2196  switch (MI.getOpcode()) {
2197  case Hexagon::L4_return:
2198  case Hexagon::L4_return_t:
2199  case Hexagon::L4_return_f:
2200  case Hexagon::L4_return_fnew_pnt:
2201  case Hexagon::L4_return_fnew_pt:
2202  case Hexagon::L4_return_tnew_pnt:
2203  case Hexagon::L4_return_tnew_pt:
2204  return true;
2205  }
2206  return false;
2207 }
2208 
2210  switch (MI.getOpcode()) {
2211  case Hexagon::J2_jumpr:
2212  case Hexagon::J2_jumprt:
2213  case Hexagon::J2_jumprf:
2214  case Hexagon::J2_jumprtnewpt:
2215  case Hexagon::J2_jumprfnewpt:
2216  case Hexagon::J2_jumprtnew:
2217  case Hexagon::J2_jumprfnew:
2218  return true;
2219  }
2220  return false;
2221 }
2222 
2223 // Return true if a given MI can accommodate given offset.
2224 // Use abs estimate as oppose to the exact number.
2225 // TODO: This will need to be changed to use MC level
2226 // definition of instruction extendable field size.
2228  unsigned offset) const {
2229  // This selection of jump instructions matches to that what
2230  // analyzeBranch can parse, plus NVJ.
2231  if (isNewValueJump(MI)) // r9:2
2232  return isInt<11>(offset);
2233 
2234  switch (MI.getOpcode()) {
2235  // Still missing Jump to address condition on register value.
2236  default:
2237  return false;
2238  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2239  case Hexagon::J2_call:
2240  case Hexagon::PS_call_nr:
2241  return isInt<24>(offset);
2242  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2243  case Hexagon::J2_jumpf:
2244  case Hexagon::J2_jumptnew:
2245  case Hexagon::J2_jumptnewpt:
2246  case Hexagon::J2_jumpfnew:
2247  case Hexagon::J2_jumpfnewpt:
2248  case Hexagon::J2_callt:
2249  case Hexagon::J2_callf:
2250  return isInt<17>(offset);
2251  case Hexagon::J2_loop0i:
2252  case Hexagon::J2_loop0iext:
2253  case Hexagon::J2_loop0r:
2254  case Hexagon::J2_loop0rext:
2255  case Hexagon::J2_loop1i:
2256  case Hexagon::J2_loop1iext:
2257  case Hexagon::J2_loop1r:
2258  case Hexagon::J2_loop1rext:
2259  return isInt<9>(offset);
2260  // TODO: Add all the compound branches here. Can we do this in Relation model?
2261  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2262  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2263  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2264  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2265  return isInt<11>(offset);
2266  }
2267 }
2268 
2270  const MachineInstr &ESMI) const {
2271  bool isLate = isLateResultInstr(LRMI);
2272  bool isEarly = isEarlySourceInstr(ESMI);
2273 
2274  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2275  LLVM_DEBUG(LRMI.dump());
2276  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2277  LLVM_DEBUG(ESMI.dump());
2278 
2279  if (isLate && isEarly) {
2280  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2281  return true;
2282  }
2283 
2284  return false;
2285 }
2286 
2288  switch (MI.getOpcode()) {
2289  case TargetOpcode::EXTRACT_SUBREG:
2290  case TargetOpcode::INSERT_SUBREG:
2291  case TargetOpcode::SUBREG_TO_REG:
2292  case TargetOpcode::REG_SEQUENCE:
2293  case TargetOpcode::IMPLICIT_DEF:
2294  case TargetOpcode::COPY:
2296  case TargetOpcode::PHI:
2297  return false;
2298  default:
2299  break;
2300  }
2301 
2302  unsigned SchedClass = MI.getDesc().getSchedClass();
2303  return !is_TC1(SchedClass);
2304 }
2305 
2307  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2308  // resource, but all operands can be received late like an ALU instruction.
2309  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2310 }
2311 
2313  unsigned Opcode = MI.getOpcode();
2314  return Opcode == Hexagon::J2_loop0i ||
2315  Opcode == Hexagon::J2_loop0r ||
2316  Opcode == Hexagon::J2_loop0iext ||
2317  Opcode == Hexagon::J2_loop0rext ||
2318  Opcode == Hexagon::J2_loop1i ||
2319  Opcode == Hexagon::J2_loop1r ||
2320  Opcode == Hexagon::J2_loop1iext ||
2321  Opcode == Hexagon::J2_loop1rext;
2322 }
2323 
2325  switch (MI.getOpcode()) {
2326  default: return false;
2327  case Hexagon::L4_iadd_memopw_io:
2328  case Hexagon::L4_isub_memopw_io:
2329  case Hexagon::L4_add_memopw_io:
2330  case Hexagon::L4_sub_memopw_io:
2331  case Hexagon::L4_and_memopw_io:
2332  case Hexagon::L4_or_memopw_io:
2333  case Hexagon::L4_iadd_memoph_io:
2334  case Hexagon::L4_isub_memoph_io:
2335  case Hexagon::L4_add_memoph_io:
2336  case Hexagon::L4_sub_memoph_io:
2337  case Hexagon::L4_and_memoph_io:
2338  case Hexagon::L4_or_memoph_io:
2339  case Hexagon::L4_iadd_memopb_io:
2340  case Hexagon::L4_isub_memopb_io:
2341  case Hexagon::L4_add_memopb_io:
2342  case Hexagon::L4_sub_memopb_io:
2343  case Hexagon::L4_and_memopb_io:
2344  case Hexagon::L4_or_memopb_io:
2345  case Hexagon::L4_ior_memopb_io:
2346  case Hexagon::L4_ior_memoph_io:
2347  case Hexagon::L4_ior_memopw_io:
2348  case Hexagon::L4_iand_memopb_io:
2349  case Hexagon::L4_iand_memoph_io:
2350  case Hexagon::L4_iand_memopw_io:
2351  return true;
2352  }
2353  return false;
2354 }
2355 
2357  const uint64_t F = MI.getDesc().TSFlags;
2359 }
2360 
2361 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2362  const uint64_t F = get(Opcode).TSFlags;
2364 }
2365 
2367  return isNewValueJump(MI) || isNewValueStore(MI);
2368 }
2369 
2371  return isNewValue(MI) && MI.isBranch();
2372 }
2373 
2374 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2375  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2376 }
2377 
2379  const uint64_t F = MI.getDesc().TSFlags;
2381 }
2382 
2383 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2384  const uint64_t F = get(Opcode).TSFlags;
2386 }
2387 
2388 // Returns true if a particular operand is extendable for an instruction.
2390  unsigned OperandNum) const {
2391  const uint64_t F = MI.getDesc().TSFlags;
2393  == OperandNum;
2394 }
2395 
2397  const uint64_t F = MI.getDesc().TSFlags;
2398  assert(isPredicated(MI));
2400 }
2401 
2402 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2403  const uint64_t F = get(Opcode).TSFlags;
2404  assert(isPredicated(Opcode));
2406 }
2407 
2409  const uint64_t F = MI.getDesc().TSFlags;
2410  return !((F >> HexagonII::PredicatedFalsePos) &
2412 }
2413 
2414 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2415  const uint64_t F = get(Opcode).TSFlags;
2416  // Make sure that the instruction is predicated.
2418  return !((F >> HexagonII::PredicatedFalsePos) &
2420 }
2421 
2422 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2423  const uint64_t F = get(Opcode).TSFlags;
2425 }
2426 
2427 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2428  const uint64_t F = get(Opcode).TSFlags;
2430 }
2431 
2432 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2433  const uint64_t F = get(Opcode).TSFlags;
2434  assert(get(Opcode).isBranch() &&
2435  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2436  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2437 }
2438 
2440  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2441  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2442  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2443  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2444 }
2445 
2447  switch (MI.getOpcode()) {
2448  // Byte
2449  case Hexagon::L2_loadrb_io:
2450  case Hexagon::L4_loadrb_ur:
2451  case Hexagon::L4_loadrb_ap:
2452  case Hexagon::L2_loadrb_pr:
2453  case Hexagon::L2_loadrb_pbr:
2454  case Hexagon::L2_loadrb_pi:
2455  case Hexagon::L2_loadrb_pci:
2456  case Hexagon::L2_loadrb_pcr:
2457  case Hexagon::L2_loadbsw2_io:
2458  case Hexagon::L4_loadbsw2_ur:
2459  case Hexagon::L4_loadbsw2_ap:
2460  case Hexagon::L2_loadbsw2_pr:
2461  case Hexagon::L2_loadbsw2_pbr:
2462  case Hexagon::L2_loadbsw2_pi:
2463  case Hexagon::L2_loadbsw2_pci:
2464  case Hexagon::L2_loadbsw2_pcr:
2465  case Hexagon::L2_loadbsw4_io:
2466  case Hexagon::L4_loadbsw4_ur:
2467  case Hexagon::L4_loadbsw4_ap:
2468  case Hexagon::L2_loadbsw4_pr:
2469  case Hexagon::L2_loadbsw4_pbr:
2470  case Hexagon::L2_loadbsw4_pi:
2471  case Hexagon::L2_loadbsw4_pci:
2472  case Hexagon::L2_loadbsw4_pcr:
2473  case Hexagon::L4_loadrb_rr:
2474  case Hexagon::L2_ploadrbt_io:
2475  case Hexagon::L2_ploadrbt_pi:
2476  case Hexagon::L2_ploadrbf_io:
2477  case Hexagon::L2_ploadrbf_pi:
2478  case Hexagon::L2_ploadrbtnew_io:
2479  case Hexagon::L2_ploadrbfnew_io:
2480  case Hexagon::L4_ploadrbt_rr:
2481  case Hexagon::L4_ploadrbf_rr:
2482  case Hexagon::L4_ploadrbtnew_rr:
2483  case Hexagon::L4_ploadrbfnew_rr:
2484  case Hexagon::L2_ploadrbtnew_pi:
2485  case Hexagon::L2_ploadrbfnew_pi:
2486  case Hexagon::L4_ploadrbt_abs:
2487  case Hexagon::L4_ploadrbf_abs:
2488  case Hexagon::L4_ploadrbtnew_abs:
2489  case Hexagon::L4_ploadrbfnew_abs:
2490  case Hexagon::L2_loadrbgp:
2491  // Half
2492  case Hexagon::L2_loadrh_io:
2493  case Hexagon::L4_loadrh_ur:
2494  case Hexagon::L4_loadrh_ap:
2495  case Hexagon::L2_loadrh_pr:
2496  case Hexagon::L2_loadrh_pbr:
2497  case Hexagon::L2_loadrh_pi:
2498  case Hexagon::L2_loadrh_pci:
2499  case Hexagon::L2_loadrh_pcr:
2500  case Hexagon::L4_loadrh_rr:
2501  case Hexagon::L2_ploadrht_io:
2502  case Hexagon::L2_ploadrht_pi:
2503  case Hexagon::L2_ploadrhf_io:
2504  case Hexagon::L2_ploadrhf_pi:
2505  case Hexagon::L2_ploadrhtnew_io:
2506  case Hexagon::L2_ploadrhfnew_io:
2507  case Hexagon::L4_ploadrht_rr:
2508  case Hexagon::L4_ploadrhf_rr:
2509  case Hexagon::L4_ploadrhtnew_rr:
2510  case Hexagon::L4_ploadrhfnew_rr:
2511  case Hexagon::L2_ploadrhtnew_pi:
2512  case Hexagon::L2_ploadrhfnew_pi:
2513  case Hexagon::L4_ploadrht_abs:
2514  case Hexagon::L4_ploadrhf_abs:
2515  case Hexagon::L4_ploadrhtnew_abs:
2516  case Hexagon::L4_ploadrhfnew_abs:
2517  case Hexagon::L2_loadrhgp:
2518  return true;
2519  default:
2520  return false;
2521  }
2522 }
2523 
2525  const uint64_t F = MI.getDesc().TSFlags;
2526  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2527 }
2528 
2530  switch (MI.getOpcode()) {
2531  case Hexagon::STriw_pred:
2532  case Hexagon::LDriw_pred:
2533  return true;
2534  default:
2535  return false;
2536  }
2537 }
2538 
2540  if (!MI.isBranch())
2541  return false;
2542 
2543  for (auto &Op : MI.operands())
2544  if (Op.isGlobal() || Op.isSymbol())
2545  return true;
2546  return false;
2547 }
2548 
2549 // Returns true when SU has a timing class TC1.
2551  unsigned SchedClass = MI.getDesc().getSchedClass();
2552  return is_TC1(SchedClass);
2553 }
2554 
2556  unsigned SchedClass = MI.getDesc().getSchedClass();
2557  return is_TC2(SchedClass);
2558 }
2559 
2561  unsigned SchedClass = MI.getDesc().getSchedClass();
2562  return is_TC2early(SchedClass);
2563 }
2564 
2566  unsigned SchedClass = MI.getDesc().getSchedClass();
2567  return is_TC4x(SchedClass);
2568 }
2569 
2570 // Schedule this ASAP.
2572  const MachineInstr &MI2) const {
2573  if (mayBeCurLoad(MI1)) {
2574  // if (result of SU is used in Next) return true;
2575  unsigned DstReg = MI1.getOperand(0).getReg();
2576  int N = MI2.getNumOperands();
2577  for (int I = 0; I < N; I++)
2578  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2579  return true;
2580  }
2581  if (mayBeNewStore(MI2))
2582  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2583  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2584  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2585  return true;
2586  return false;
2587 }
2588 
2590  const uint64_t V = getType(MI);
2592 }
2593 
2594 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2596  int Size = VT.getSizeInBits() / 8;
2597  if (Offset % Size != 0)
2598  return false;
2599  int Count = Offset / Size;
2600 
2601  switch (VT.getSimpleVT().SimpleTy) {
2602  // For scalars the auto-inc is s4
2603  case MVT::i8:
2604  case MVT::i16:
2605  case MVT::i32:
2606  case MVT::i64:
2607  case MVT::f32:
2608  case MVT::f64:
2609  case MVT::v2i16:
2610  case MVT::v2i32:
2611  case MVT::v4i8:
2612  case MVT::v4i16:
2613  case MVT::v8i8:
2614  return isInt<4>(Count);
2615  // For HVX vectors the auto-inc is s3
2616  case MVT::v64i8:
2617  case MVT::v32i16:
2618  case MVT::v16i32:
2619  case MVT::v8i64:
2620  case MVT::v128i8:
2621  case MVT::v64i16:
2622  case MVT::v32i32:
2623  case MVT::v16i64:
2624  return isInt<3>(Count);
2625  default:
2626  break;
2627  }
2628 
2629  llvm_unreachable("Not an valid type!");
2630 }
2631 
2632 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2633  const TargetRegisterInfo *TRI, bool Extend) const {
2634  // This function is to check whether the "Offset" is in the correct range of
2635  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2636  // inserted to calculate the final address. Due to this reason, the function
2637  // assumes that the "Offset" has correct alignment.
2638  // We used to assert if the offset was not properly aligned, however,
2639  // there are cases where a misaligned pointer recast can cause this
2640  // problem, and we need to allow for it. The front end warns of such
2641  // misaligns with respect to load size.
2642  switch (Opcode) {
2643  case Hexagon::PS_vstorerq_ai:
2644  case Hexagon::PS_vstorerw_ai:
2645  case Hexagon::PS_vstorerw_nt_ai:
2646  case Hexagon::PS_vloadrq_ai:
2647  case Hexagon::PS_vloadrw_ai:
2648  case Hexagon::PS_vloadrw_nt_ai:
2649  case Hexagon::V6_vL32b_ai:
2650  case Hexagon::V6_vS32b_ai:
2651  case Hexagon::V6_vL32b_nt_ai:
2652  case Hexagon::V6_vS32b_nt_ai:
2653  case Hexagon::V6_vL32Ub_ai:
2654  case Hexagon::V6_vS32Ub_ai: {
2655  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2656  assert(isPowerOf2_32(VectorSize));
2657  if (Offset & (VectorSize-1))
2658  return false;
2659  return isInt<4>(Offset >> Log2_32(VectorSize));
2660  }
2661 
2662  case Hexagon::J2_loop0i:
2663  case Hexagon::J2_loop1i:
2664  return isUInt<10>(Offset);
2665 
2666  case Hexagon::S4_storeirb_io:
2667  case Hexagon::S4_storeirbt_io:
2668  case Hexagon::S4_storeirbf_io:
2669  return isUInt<6>(Offset);
2670 
2671  case Hexagon::S4_storeirh_io:
2672  case Hexagon::S4_storeirht_io:
2673  case Hexagon::S4_storeirhf_io:
2674  return isShiftedUInt<6,1>(Offset);
2675 
2676  case Hexagon::S4_storeiri_io:
2677  case Hexagon::S4_storeirit_io:
2678  case Hexagon::S4_storeirif_io:
2679  return isShiftedUInt<6,2>(Offset);
2680  }
2681 
2682  if (Extend)
2683  return true;
2684 
2685  switch (Opcode) {
2686  case Hexagon::L2_loadri_io:
2687  case Hexagon::S2_storeri_io:
2688  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2689  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2690 
2691  case Hexagon::L2_loadrd_io:
2692  case Hexagon::S2_storerd_io:
2693  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2694  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2695 
2696  case Hexagon::L2_loadrh_io:
2697  case Hexagon::L2_loadruh_io:
2698  case Hexagon::S2_storerh_io:
2699  case Hexagon::S2_storerf_io:
2700  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2701  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2702 
2703  case Hexagon::L2_loadrb_io:
2704  case Hexagon::L2_loadrub_io:
2705  case Hexagon::S2_storerb_io:
2706  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2707  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2708 
2709  case Hexagon::A2_addi:
2710  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2711  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2712 
2713  case Hexagon::L4_iadd_memopw_io:
2714  case Hexagon::L4_isub_memopw_io:
2715  case Hexagon::L4_add_memopw_io:
2716  case Hexagon::L4_sub_memopw_io:
2717  case Hexagon::L4_and_memopw_io:
2718  case Hexagon::L4_or_memopw_io:
2719  return (0 <= Offset && Offset <= 255);
2720 
2721  case Hexagon::L4_iadd_memoph_io:
2722  case Hexagon::L4_isub_memoph_io:
2723  case Hexagon::L4_add_memoph_io:
2724  case Hexagon::L4_sub_memoph_io:
2725  case Hexagon::L4_and_memoph_io:
2726  case Hexagon::L4_or_memoph_io:
2727  return (0 <= Offset && Offset <= 127);
2728 
2729  case Hexagon::L4_iadd_memopb_io:
2730  case Hexagon::L4_isub_memopb_io:
2731  case Hexagon::L4_add_memopb_io:
2732  case Hexagon::L4_sub_memopb_io:
2733  case Hexagon::L4_and_memopb_io:
2734  case Hexagon::L4_or_memopb_io:
2735  return (0 <= Offset && Offset <= 63);
2736 
2737  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2738  // any size. Later pass knows how to handle it.
2739  case Hexagon::STriw_pred:
2740  case Hexagon::LDriw_pred:
2741  case Hexagon::STriw_ctr:
2742  case Hexagon::LDriw_ctr:
2743  return true;
2744 
2745  case Hexagon::PS_fi:
2746  case Hexagon::PS_fia:
2747  case Hexagon::INLINEASM:
2748  return true;
2749 
2750  case Hexagon::L2_ploadrbt_io:
2751  case Hexagon::L2_ploadrbf_io:
2752  case Hexagon::L2_ploadrubt_io:
2753  case Hexagon::L2_ploadrubf_io:
2754  case Hexagon::S2_pstorerbt_io:
2755  case Hexagon::S2_pstorerbf_io:
2756  return isUInt<6>(Offset);
2757 
2758  case Hexagon::L2_ploadrht_io:
2759  case Hexagon::L2_ploadrhf_io:
2760  case Hexagon::L2_ploadruht_io:
2761  case Hexagon::L2_ploadruhf_io:
2762  case Hexagon::S2_pstorerht_io:
2763  case Hexagon::S2_pstorerhf_io:
2764  return isShiftedUInt<6,1>(Offset);
2765 
2766  case Hexagon::L2_ploadrit_io:
2767  case Hexagon::L2_ploadrif_io:
2768  case Hexagon::S2_pstorerit_io:
2769  case Hexagon::S2_pstorerif_io:
2770  return isShiftedUInt<6,2>(Offset);
2771 
2772  case Hexagon::L2_ploadrdt_io:
2773  case Hexagon::L2_ploadrdf_io:
2774  case Hexagon::S2_pstorerdt_io:
2775  case Hexagon::S2_pstorerdf_io:
2776  return isShiftedUInt<6,3>(Offset);
2777  } // switch
2778 
2779  llvm_unreachable("No offset range is defined for this opcode. "
2780  "Please define it in the above switch statement!");
2781 }
2782 
2784  return isHVXVec(MI) && isAccumulator(MI);
2785 }
2786 
2788  const uint64_t F = get(MI.getOpcode()).TSFlags;
2789  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2790  return
2791  V == HexagonII::TypeCVI_VA ||
2793 }
2794 
2796  const MachineInstr &ConsMI) const {
2797  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2798  return true;
2799 
2800  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2801  return true;
2802 
2803  if (mayBeNewStore(ConsMI))
2804  return true;
2805 
2806  return false;
2807 }
2808 
2810  switch (MI.getOpcode()) {
2811  // Byte
2812  case Hexagon::L2_loadrub_io:
2813  case Hexagon::L4_loadrub_ur:
2814  case Hexagon::L4_loadrub_ap:
2815  case Hexagon::L2_loadrub_pr:
2816  case Hexagon::L2_loadrub_pbr:
2817  case Hexagon::L2_loadrub_pi:
2818  case Hexagon::L2_loadrub_pci:
2819  case Hexagon::L2_loadrub_pcr:
2820  case Hexagon::L2_loadbzw2_io:
2821  case Hexagon::L4_loadbzw2_ur:
2822  case Hexagon::L4_loadbzw2_ap:
2823  case Hexagon::L2_loadbzw2_pr:
2824  case Hexagon::L2_loadbzw2_pbr:
2825  case Hexagon::L2_loadbzw2_pi:
2826  case Hexagon::L2_loadbzw2_pci:
2827  case Hexagon::L2_loadbzw2_pcr:
2828  case Hexagon::L2_loadbzw4_io:
2829  case Hexagon::L4_loadbzw4_ur:
2830  case Hexagon::L4_loadbzw4_ap:
2831  case Hexagon::L2_loadbzw4_pr:
2832  case Hexagon::L2_loadbzw4_pbr:
2833  case Hexagon::L2_loadbzw4_pi:
2834  case Hexagon::L2_loadbzw4_pci:
2835  case Hexagon::L2_loadbzw4_pcr:
2836  case Hexagon::L4_loadrub_rr:
2837  case Hexagon::L2_ploadrubt_io:
2838  case Hexagon::L2_ploadrubt_pi:
2839  case Hexagon::L2_ploadrubf_io:
2840  case Hexagon::L2_ploadrubf_pi:
2841  case Hexagon::L2_ploadrubtnew_io:
2842  case Hexagon::L2_ploadrubfnew_io:
2843  case Hexagon::L4_ploadrubt_rr:
2844  case Hexagon::L4_ploadrubf_rr:
2845  case Hexagon::L4_ploadrubtnew_rr:
2846  case Hexagon::L4_ploadrubfnew_rr:
2847  case Hexagon::L2_ploadrubtnew_pi:
2848  case Hexagon::L2_ploadrubfnew_pi:
2849  case Hexagon::L4_ploadrubt_abs:
2850  case Hexagon::L4_ploadrubf_abs:
2851  case Hexagon::L4_ploadrubtnew_abs:
2852  case Hexagon::L4_ploadrubfnew_abs:
2853  case Hexagon::L2_loadrubgp:
2854  // Half
2855  case Hexagon::L2_loadruh_io:
2856  case Hexagon::L4_loadruh_ur:
2857  case Hexagon::L4_loadruh_ap:
2858  case Hexagon::L2_loadruh_pr:
2859  case Hexagon::L2_loadruh_pbr:
2860  case Hexagon::L2_loadruh_pi:
2861  case Hexagon::L2_loadruh_pci:
2862  case Hexagon::L2_loadruh_pcr:
2863  case Hexagon::L4_loadruh_rr:
2864  case Hexagon::L2_ploadruht_io:
2865  case Hexagon::L2_ploadruht_pi:
2866  case Hexagon::L2_ploadruhf_io:
2867  case Hexagon::L2_ploadruhf_pi:
2868  case Hexagon::L2_ploadruhtnew_io:
2869  case Hexagon::L2_ploadruhfnew_io:
2870  case Hexagon::L4_ploadruht_rr:
2871  case Hexagon::L4_ploadruhf_rr:
2872  case Hexagon::L4_ploadruhtnew_rr:
2873  case Hexagon::L4_ploadruhfnew_rr:
2874  case Hexagon::L2_ploadruhtnew_pi:
2875  case Hexagon::L2_ploadruhfnew_pi:
2876  case Hexagon::L4_ploadruht_abs:
2877  case Hexagon::L4_ploadruhf_abs:
2878  case Hexagon::L4_ploadruhtnew_abs:
2879  case Hexagon::L4_ploadruhfnew_abs:
2880  case Hexagon::L2_loadruhgp:
2881  return true;
2882  default:
2883  return false;
2884  }
2885 }
2886 
2887 // Add latency to instruction.
2889  const MachineInstr &MI2) const {
2890  if (isHVXVec(MI1) && isHVXVec(MI2))
2891  if (!isVecUsableNextPacket(MI1, MI2))
2892  return true;
2893  return false;
2894 }
2895 
2896 /// Get the base register and byte offset of a load/store instr.
2898  unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2899  const {
2900  unsigned AccessSize = 0;
2901  int OffsetVal = 0;
2902  BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2903  Offset = OffsetVal;
2904  return BaseReg != 0;
2905 }
2906 
2907 /// Can these instructions execute at the same time in a bundle.
2909  const MachineInstr &Second) const {
2910  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2911  const MachineOperand &Op = Second.getOperand(0);
2912  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2913  return true;
2914  }
2915  if (DisableNVSchedule)
2916  return false;
2917  if (mayBeNewStore(Second)) {
2918  // Make sure the definition of the first instruction is the value being
2919  // stored.
2920  const MachineOperand &Stored =
2921  Second.getOperand(Second.getNumOperands() - 1);
2922  if (!Stored.isReg())
2923  return false;
2924  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2925  const MachineOperand &Op = First.getOperand(i);
2926  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2927  return true;
2928  }
2929  }
2930  return false;
2931 }
2932 
2934  unsigned Opc = CallMI.getOpcode();
2935  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2936 }
2937 
2939  for (auto &I : *B)
2940  if (I.isEHLabel())
2941  return true;
2942  return false;
2943 }
2944 
2945 // Returns true if an instruction can be converted into a non-extended
2946 // equivalent instruction.
2948  short NonExtOpcode;
2949  // Check if the instruction has a register form that uses register in place
2950  // of the extended operand, if so return that as the non-extended form.
2951  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2952  return true;
2953 
2954  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2955  // Check addressing mode and retrieve non-ext equivalent instruction.
2956 
2957  switch (getAddrMode(MI)) {
2958  case HexagonII::Absolute:
2959  // Load/store with absolute addressing mode can be converted into
2960  // base+offset mode.
2961  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2962  break;
2964  // Load/store with base+offset addressing mode can be converted into
2965  // base+register offset addressing mode. However left shift operand should
2966  // be set to 0.
2967  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
2968  break;
2970  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
2971  break;
2972  default:
2973  return false;
2974  }
2975  if (NonExtOpcode < 0)
2976  return false;
2977  return true;
2978  }
2979  return false;
2980 }
2981 
2983  return Hexagon::getRealHWInstr(MI.getOpcode(),
2984  Hexagon::InstrType_Pseudo) >= 0;
2985 }
2986 
2988  const {
2990  while (I != E) {
2991  if (I->isBarrier())
2992  return true;
2993  ++I;
2994  }
2995  return false;
2996 }
2997 
2998 // Returns true, if a LD insn can be promoted to a cur load.
3000  const uint64_t F = MI.getDesc().TSFlags;
3002  Subtarget.hasV60Ops();
3003 }
3004 
3005 // Returns true, if a ST insn can be promoted to a new-value store.
3007  if (MI.mayStore() && !Subtarget.useNewValueStores())
3008  return false;
3009 
3010  const uint64_t F = MI.getDesc().TSFlags;
3012 }
3013 
3015  const MachineInstr &ConsMI) const {
3016  // There is no stall when ProdMI is not a V60 vector.
3017  if (!isHVXVec(ProdMI))
3018  return false;
3019 
3020  // There is no stall when ProdMI and ConsMI are not dependent.
3021  if (!isDependent(ProdMI, ConsMI))
3022  return false;
3023 
3024  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3025  // are scheduled in consecutive packets.
3026  if (isVecUsableNextPacket(ProdMI, ConsMI))
3027  return false;
3028 
3029  return true;
3030 }
3031 
3034  // There is no stall when I is not a V60 vector.
3035  if (!isHVXVec(MI))
3036  return false;
3037 
3039  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3040 
3041  if (!MII->isBundle())
3042  return producesStall(*MII, MI);
3043 
3044  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3045  const MachineInstr &J = *MII;
3046  if (producesStall(J, MI))
3047  return true;
3048  }
3049  return false;
3050 }
3051 
3053  unsigned PredReg) const {
3054  for (const MachineOperand &MO : MI.operands()) {
3055  // Predicate register must be explicitly defined.
3056  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3057  return false;
3058  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3059  return false;
3060  }
3061 
3062  // Instruction that produce late predicate cannot be used as sources of
3063  // dot-new.
3064  switch (MI.getOpcode()) {
3065  case Hexagon::A4_addp_c:
3066  case Hexagon::A4_subp_c:
3067  case Hexagon::A4_tlbmatch:
3068  case Hexagon::A5_ACS:
3069  case Hexagon::F2_sfinvsqrta:
3070  case Hexagon::F2_sfrecipa:
3071  case Hexagon::J2_endloop0:
3072  case Hexagon::J2_endloop01:
3073  case Hexagon::J2_ploop1si:
3074  case Hexagon::J2_ploop1sr:
3075  case Hexagon::J2_ploop2si:
3076  case Hexagon::J2_ploop2sr:
3077  case Hexagon::J2_ploop3si:
3078  case Hexagon::J2_ploop3sr:
3079  case Hexagon::S2_cabacdecbin:
3080  case Hexagon::S2_storew_locked:
3081  case Hexagon::S4_stored_locked:
3082  return false;
3083  }
3084  return true;
3085 }
3086 
3087 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3088  return Opcode == Hexagon::J2_jumpt ||
3089  Opcode == Hexagon::J2_jumptpt ||
3090  Opcode == Hexagon::J2_jumpf ||
3091  Opcode == Hexagon::J2_jumpfpt ||
3092  Opcode == Hexagon::J2_jumptnew ||
3093  Opcode == Hexagon::J2_jumpfnew ||
3094  Opcode == Hexagon::J2_jumptnewpt ||
3095  Opcode == Hexagon::J2_jumpfnewpt;
3096 }
3097 
3099  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3100  return false;
3101  return !isPredicatedTrue(Cond[0].getImm());
3102 }
3103 
3105  const uint64_t F = MI.getDesc().TSFlags;
3107 }
3108 
3109 // Returns the base register in a memory access (load/store). The offset is
3110 // returned in Offset and the access size is returned in AccessSize.
3111 // If the base register has a subregister or the offset field does not contain
3112 // an immediate value, return 0.
3114  int &Offset, unsigned &AccessSize) const {
3115  // Return if it is not a base+offset type instruction or a MemOp.
3118  !isMemOp(MI) && !isPostIncrement(MI))
3119  return 0;
3120 
3121  AccessSize = getMemAccessSize(MI);
3122 
3123  unsigned BasePos = 0, OffsetPos = 0;
3124  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3125  return 0;
3126 
3127  // Post increment updates its EA after the mem access,
3128  // so we need to treat its offset as zero.
3129  if (isPostIncrement(MI)) {
3130  Offset = 0;
3131  } else {
3132  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3133  if (!OffsetOp.isImm())
3134  return 0;
3135  Offset = OffsetOp.getImm();
3136  }
3137 
3138  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3139  if (BaseOp.getSubReg() != 0)
3140  return 0;
3141  return BaseOp.getReg();
3142 }
3143 
3144 /// Return the position of the base and offset operands for this instruction.
3146  unsigned &BasePos, unsigned &OffsetPos) const {
3147  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3148  return false;
3149 
3150  // Deal with memops first.
3151  if (isMemOp(MI)) {
3152  BasePos = 0;
3153  OffsetPos = 1;
3154  } else if (MI.mayStore()) {
3155  BasePos = 0;
3156  OffsetPos = 1;
3157  } else if (MI.mayLoad()) {
3158  BasePos = 1;
3159  OffsetPos = 2;
3160  } else
3161  return false;
3162 
3163  if (isPredicated(MI)) {
3164  BasePos++;
3165  OffsetPos++;
3166  }
3167  if (isPostIncrement(MI)) {
3168  BasePos++;
3169  OffsetPos++;
3170  }
3171 
3172  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3173  return false;
3174 
3175  return true;
3176 }
3177 
3178 // Inserts branching instructions in reverse order of their occurrence.
3179 // e.g. jump_t t1 (i1)
3180 // jump t2 (i2)
3181 // Jumpers = {i2, i1}
3183  MachineBasicBlock& MBB) const {
3185  // If the block has no terminators, it just falls into the block after it.
3187  if (I == MBB.instr_begin())
3188  return Jumpers;
3189 
3190  // A basic block may looks like this:
3191  //
3192  // [ insn
3193  // EH_LABEL
3194  // insn
3195  // insn
3196  // insn
3197  // EH_LABEL
3198  // insn ]
3199  //
3200  // It has two succs but does not have a terminator
3201  // Don't know how to handle it.
3202  do {
3203  --I;
3204  if (I->isEHLabel())
3205  return Jumpers;
3206  } while (I != MBB.instr_begin());
3207 
3208  I = MBB.instr_end();
3209  --I;
3210 
3211  while (I->isDebugInstr()) {
3212  if (I == MBB.instr_begin())
3213  return Jumpers;
3214  --I;
3215  }
3216  if (!isUnpredicatedTerminator(*I))
3217  return Jumpers;
3218 
3219  // Get the last instruction in the block.
3220  MachineInstr *LastInst = &*I;
3221  Jumpers.push_back(LastInst);
3222  MachineInstr *SecondLastInst = nullptr;
3223  // Find one more terminator if present.
3224  do {
3225  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3226  if (!SecondLastInst) {
3227  SecondLastInst = &*I;
3228  Jumpers.push_back(SecondLastInst);
3229  } else // This is a third branch.
3230  return Jumpers;
3231  }
3232  if (I == MBB.instr_begin())
3233  break;
3234  --I;
3235  } while (true);
3236  return Jumpers;
3237 }
3238 
3239 // Returns Operand Index for the constant extended instruction.
3241  const uint64_t F = MI.getDesc().TSFlags;
3243 }
3244 
3245 // See if instruction could potentially be a duplex candidate.
3246 // If so, return its group. Zero otherwise.
3248  const MachineInstr &MI) const {
3249  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3250 
3251  switch (MI.getOpcode()) {
3252  default:
3253  return HexagonII::HCG_None;
3254  //
3255  // Compound pairs.
3256  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3257  // "Rd16=#U6 ; jump #r9:2"
3258  // "Rd16=Rs16 ; jump #r9:2"
3259  //
3260  case Hexagon::C2_cmpeq:
3261  case Hexagon::C2_cmpgt:
3262  case Hexagon::C2_cmpgtu:
3263  DstReg = MI.getOperand(0).getReg();
3264  Src1Reg = MI.getOperand(1).getReg();
3265  Src2Reg = MI.getOperand(2).getReg();
3266  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3267  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3268  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3269  return HexagonII::HCG_A;
3270  break;
3271  case Hexagon::C2_cmpeqi:
3272  case Hexagon::C2_cmpgti:
3273  case Hexagon::C2_cmpgtui:
3274  // P0 = cmp.eq(Rs,#u2)
3275  DstReg = MI.getOperand(0).getReg();
3276  SrcReg = MI.getOperand(1).getReg();
3277  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3278  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3279  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3280  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3281  (MI.getOperand(2).getImm() == -1)))
3282  return HexagonII::HCG_A;
3283  break;
3284  case Hexagon::A2_tfr:
3285  // Rd = Rs
3286  DstReg = MI.getOperand(0).getReg();
3287  SrcReg = MI.getOperand(1).getReg();
3288  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3289  return HexagonII::HCG_A;
3290  break;
3291  case Hexagon::A2_tfrsi:
3292  // Rd = #u6
3293  // Do not test for #u6 size since the const is getting extended
3294  // regardless and compound could be formed.
3295  DstReg = MI.getOperand(0).getReg();
3296  if (isIntRegForSubInst(DstReg))
3297  return HexagonII::HCG_A;
3298  break;
3299  case Hexagon::S2_tstbit_i:
3300  DstReg = MI.getOperand(0).getReg();
3301  Src1Reg = MI.getOperand(1).getReg();
3302  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3303  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3304  MI.getOperand(2).isImm() &&
3305  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3306  return HexagonII::HCG_A;
3307  break;
3308  // The fact that .new form is used pretty much guarantees
3309  // that predicate register will match. Nevertheless,
3310  // there could be some false positives without additional
3311  // checking.
3312  case Hexagon::J2_jumptnew:
3313  case Hexagon::J2_jumpfnew:
3314  case Hexagon::J2_jumptnewpt:
3315  case Hexagon::J2_jumpfnewpt:
3316  Src1Reg = MI.getOperand(0).getReg();
3317  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3318  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3319  return HexagonII::HCG_B;
3320  break;
3321  // Transfer and jump:
3322  // Rd=#U6 ; jump #r9:2
3323  // Rd=Rs ; jump #r9:2
3324  // Do not test for jump range here.
3325  case Hexagon::J2_jump:
3326  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3327  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3328  return HexagonII::HCG_C;
3329  }
3330 
3331  return HexagonII::HCG_None;
3332 }
3333 
3334 // Returns -1 when there is no opcode found.
3336  const MachineInstr &GB) const {
3339  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3340  (GB.getOpcode() != Hexagon::J2_jumptnew))
3341  return -1u;
3342  unsigned DestReg = GA.getOperand(0).getReg();
3343  if (!GB.readsRegister(DestReg))
3344  return -1u;
3345  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3346  return -1u;
3347  // The value compared against must be either u5 or -1.
3348  const MachineOperand &CmpOp = GA.getOperand(2);
3349  if (!CmpOp.isImm())
3350  return -1u;
3351  int V = CmpOp.getImm();
3352  if (V == -1)
3353  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3354  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3355  if (!isUInt<5>(V))
3356  return -1u;
3357  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3358  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3359 }
3360 
3361 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3362  enum Hexagon::PredSense inPredSense;
3363  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3364  Hexagon::PredSense_true;
3365  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3366  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3367  return CondOpcode;
3368 
3369  llvm_unreachable("Unexpected predicable instruction");
3370 }
3371 
3372 // Return the cur value instruction for a given store.
3374  switch (MI.getOpcode()) {
3375  default: llvm_unreachable("Unknown .cur type");
3376  case Hexagon::V6_vL32b_pi:
3377  return Hexagon::V6_vL32b_cur_pi;
3378  case Hexagon::V6_vL32b_ai:
3379  return Hexagon::V6_vL32b_cur_ai;
3380  case Hexagon::V6_vL32b_nt_pi:
3381  return Hexagon::V6_vL32b_nt_cur_pi;
3382  case Hexagon::V6_vL32b_nt_ai:
3383  return Hexagon::V6_vL32b_nt_cur_ai;
3384  }
3385  return 0;
3386 }
3387 
3388 // Return the regular version of the .cur instruction.
3390  switch (MI.getOpcode()) {
3391  default: llvm_unreachable("Unknown .cur type");
3392  case Hexagon::V6_vL32b_cur_pi:
3393  return Hexagon::V6_vL32b_pi;
3394  case Hexagon::V6_vL32b_cur_ai:
3395  return Hexagon::V6_vL32b_ai;
3396  case Hexagon::V6_vL32b_nt_cur_pi:
3397  return Hexagon::V6_vL32b_nt_pi;
3398  case Hexagon::V6_vL32b_nt_cur_ai:
3399  return Hexagon::V6_vL32b_nt_ai;
3400  }
3401  return 0;
3402 }
3403 
3404 // The diagram below shows the steps involved in the conversion of a predicated
3405 // store instruction to its .new predicated new-value form.
3406 //
3407 // Note: It doesn't include conditional new-value stores as they can't be
3408 // converted to .new predicate.
3409 //
3410 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3411 // ^ ^
3412 // / \ (not OK. it will cause new-value store to be
3413 // / X conditional on p0.new while R2 producer is
3414 // / \ on p0)
3415 // / \.
3416 // p.new store p.old NV store
3417 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3418 // ^ ^
3419 // \ /
3420 // \ /
3421 // \ /
3422 // p.old store
3423 // [if (p0)memw(R0+#0)=R2]
3424 //
3425 // The following set of instructions further explains the scenario where
3426 // conditional new-value store becomes invalid when promoted to .new predicate
3427 // form.
3428 //
3429 // { 1) if (p0) r0 = add(r1, r2)
3430 // 2) p0 = cmp.eq(r3, #0) }
3431 //
3432 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3433 // the first two instructions because in instr 1, r0 is conditional on old value
3434 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3435 // is not valid for new-value stores.
3436 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3437 // from the "Conditional Store" list. Because a predicated new value store
3438 // would NOT be promoted to a double dot new store. See diagram below:
3439 // This function returns yes for those stores that are predicated but not
3440 // yet promoted to predicate dot new instructions.
3441 //
3442 // +---------------------+
3443 // /-----| if (p0) memw(..)=r0 |---------\~
3444 // || +---------------------+ ||
3445 // promote || /\ /\ || promote
3446 // || /||\ /||\ ||
3447 // \||/ demote || \||/
3448 // \/ || || \/
3449 // +-------------------------+ || +-------------------------+
3450 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3451 // +-------------------------+ || +-------------------------+
3452 // || || ||
3453 // || demote \||/
3454 // promote || \/ NOT possible
3455 // || || /\~
3456 // \||/ || /||\~
3457 // \/ || ||
3458 // +-----------------------------+
3459 // | if (p0.new) memw(..)=r0.new |
3460 // +-----------------------------+
3461 // Double Dot New Store
3462 //
3463 // Returns the most basic instruction for the .new predicated instructions and
3464 // new-value stores.
3465 // For example, all of the following instructions will be converted back to the
3466 // same instruction:
3467 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3468 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3469 // 3) if (p0.new) memw(R0+#0) = R1 --->
3470 //
3471 // To understand the translation of instruction 1 to its original form, consider
3472 // a packet with 3 instructions.
3473 // { p0 = cmp.eq(R0,R1)
3474 // if (p0.new) R2 = add(R3, R4)
3475 // R5 = add (R3, R1)
3476 // }
3477 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3478 //
3479 // This instruction can be part of the previous packet only if both p0 and R2
3480 // are promoted to .new values. This promotion happens in steps, first
3481 // predicate register is promoted to .new and in the next iteration R2 is
3482 // promoted. Therefore, in case of dependence check failure (due to R5) during
3483 // next iteration, it should be converted back to its most basic form.
3484 
3485 // Return the new value instruction for a given store.
3487  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3488  if (NVOpcode >= 0) // Valid new-value store instruction.
3489  return NVOpcode;
3490 
3491  switch (MI.getOpcode()) {
3492  default:
3493  report_fatal_error(std::string("Unknown .new type: ") +
3494  std::to_string(MI.getOpcode()));
3495  case Hexagon::S4_storerb_ur:
3496  return Hexagon::S4_storerbnew_ur;
3497 
3498  case Hexagon::S2_storerb_pci:
3499  return Hexagon::S2_storerb_pci;
3500 
3501  case Hexagon::S2_storeri_pci:
3502  return Hexagon::S2_storeri_pci;
3503 
3504  case Hexagon::S2_storerh_pci:
3505  return Hexagon::S2_storerh_pci;
3506 
3507  case Hexagon::S2_storerd_pci:
3508  return Hexagon::S2_storerd_pci;
3509 
3510  case Hexagon::S2_storerf_pci:
3511  return Hexagon::S2_storerf_pci;
3512 
3513  case Hexagon::V6_vS32b_ai:
3514  return Hexagon::V6_vS32b_new_ai;
3515 
3516  case Hexagon::V6_vS32b_pi:
3517  return Hexagon::V6_vS32b_new_pi;
3518  }
3519  return 0;
3520 }
3521 
3522 // Returns the opcode to use when converting MI, which is a conditional jump,
3523 // into a conditional instruction which uses the .new value of the predicate.
3524 // We also use branch probabilities to add a hint to the jump.
3525 // If MBPI is null, all edges will be treated as equally likely for the
3526 // purposes of establishing a predication hint.
3528  const MachineBranchProbabilityInfo *MBPI) const {
3529  // We assume that block can have at most two successors.
3530  const MachineBasicBlock *Src = MI.getParent();
3531  const MachineOperand &BrTarget = MI.getOperand(1);
3532  bool Taken = false;
3533  const BranchProbability OneHalf(1, 2);
3534 
3535  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3536  const MachineBasicBlock *Dst) {
3537  if (MBPI)
3538  return MBPI->getEdgeProbability(Src, Dst);
3539  return BranchProbability(1, Src->succ_size());
3540  };
3541 
3542  if (BrTarget.isMBB()) {
3543  const MachineBasicBlock *Dst = BrTarget.getMBB();
3544  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3545  } else {
3546  // The branch target is not a basic block (most likely a function).
3547  // Since BPI only gives probabilities for targets that are basic blocks,
3548  // try to identify another target of this branch (potentially a fall-
3549  // -through) and check the probability of that target.
3550  //
3551  // The only handled branch combinations are:
3552  // - one conditional branch,
3553  // - one conditional branch followed by one unconditional branch.
3554  // Otherwise, assume not-taken.
3556  const MachineBasicBlock &B = *MI.getParent();
3557  bool SawCond = false, Bad = false;
3558  for (const MachineInstr &I : B) {
3559  if (!I.isBranch())
3560  continue;
3561  if (I.isConditionalBranch()) {
3562  SawCond = true;
3563  if (&I != &MI) {
3564  Bad = true;
3565  break;
3566  }
3567  }
3568  if (I.isUnconditionalBranch() && !SawCond) {
3569  Bad = true;
3570  break;
3571  }
3572  }
3573  if (!Bad) {
3575  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3576  if (NextIt == B.instr_end()) {
3577  // If this branch is the last, look for the fall-through block.
3578  for (const MachineBasicBlock *SB : B.successors()) {
3579  if (!B.isLayoutSuccessor(SB))
3580  continue;
3581  Taken = getEdgeProbability(Src, SB) < OneHalf;
3582  break;
3583  }
3584  } else {
3585  assert(NextIt->isUnconditionalBranch());
3586  // Find the first MBB operand and assume it's the target.
3587  const MachineBasicBlock *BT = nullptr;
3588  for (const MachineOperand &Op : NextIt->operands()) {
3589  if (!Op.isMBB())
3590  continue;
3591  BT = Op.getMBB();
3592  break;
3593  }
3594  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3595  }
3596  } // if (!Bad)
3597  }
3598 
3599  // The Taken flag should be set to something reasonable by this point.
3600 
3601  switch (MI.getOpcode()) {
3602  case Hexagon::J2_jumpt:
3603  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3604  case Hexagon::J2_jumpf:
3605  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3606 
3607  default:
3608  llvm_unreachable("Unexpected jump instruction.");
3609  }
3610 }
3611 
3612 // Return .new predicate version for an instruction.
3614  const MachineBranchProbabilityInfo *MBPI) const {
3615  switch (MI.getOpcode()) {
3616  // Condtional Jumps
3617  case Hexagon::J2_jumpt:
3618  case Hexagon::J2_jumpf:
3619  return getDotNewPredJumpOp(MI, MBPI);
3620  }
3621 
3622  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3623  if (NewOpcode >= 0)
3624  return NewOpcode;
3625  return 0;
3626 }
3627 
3629  int NewOp = MI.getOpcode();
3630  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3631  NewOp = Hexagon::getPredOldOpcode(NewOp);
3632  // All Hexagon architectures have prediction bits on dot-new branches,
3633  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3634  // to pick the right opcode when converting back to dot-old.
3635  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3636  switch (NewOp) {
3637  case Hexagon::J2_jumptpt:
3638  NewOp = Hexagon::J2_jumpt;
3639  break;
3640  case Hexagon::J2_jumpfpt:
3641  NewOp = Hexagon::J2_jumpf;
3642  break;
3643  case Hexagon::J2_jumprtpt:
3644  NewOp = Hexagon::J2_jumprt;
3645  break;
3646  case Hexagon::J2_jumprfpt:
3647  NewOp = Hexagon::J2_jumprf;
3648  break;
3649  }
3650  }
3651  assert(NewOp >= 0 &&
3652  "Couldn't change predicate new instruction to its old form.");
3653  }
3654 
3655  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3656  NewOp = Hexagon::getNonNVStore(NewOp);
3657  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3658  }
3659 
3660  if (Subtarget.hasV60Ops())
3661  return NewOp;
3662 
3663  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3664  switch (NewOp) {
3665  case Hexagon::J2_jumpfpt:
3666  return Hexagon::J2_jumpf;
3667  case Hexagon::J2_jumptpt:
3668  return Hexagon::J2_jumpt;
3669  case Hexagon::J2_jumprfpt:
3670  return Hexagon::J2_jumprf;
3671  case Hexagon::J2_jumprtpt:
3672  return Hexagon::J2_jumprt;
3673  }
3674  return NewOp;
3675 }
3676 
3677 // See if instruction could potentially be a duplex candidate.
3678 // If so, return its group. Zero otherwise.
3680  const MachineInstr &MI) const {
3681  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3682  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3683 
3684  switch (MI.getOpcode()) {
3685  default:
3686  return HexagonII::HSIG_None;
3687  //
3688  // Group L1:
3689  //
3690  // Rd = memw(Rs+#u4:2)
3691  // Rd = memub(Rs+#u4:0)
3692  case Hexagon::L2_loadri_io:
3693  DstReg = MI.getOperand(0).getReg();
3694  SrcReg = MI.getOperand(1).getReg();
3695  // Special case this one from Group L2.
3696  // Rd = memw(r29+#u5:2)
3697  if (isIntRegForSubInst(DstReg)) {
3698  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3699  HRI.getStackRegister() == SrcReg &&
3700  MI.getOperand(2).isImm() &&
3701  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3702  return HexagonII::HSIG_L2;
3703  // Rd = memw(Rs+#u4:2)
3704  if (isIntRegForSubInst(SrcReg) &&
3705  (MI.getOperand(2).isImm() &&
3706  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3707  return HexagonII::HSIG_L1;
3708  }
3709  break;
3710  case Hexagon::L2_loadrub_io:
3711  // Rd = memub(Rs+#u4:0)
3712  DstReg = MI.getOperand(0).getReg();
3713  SrcReg = MI.getOperand(1).getReg();
3714  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3715  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3716  return HexagonII::HSIG_L1;
3717  break;
3718  //
3719  // Group L2:
3720  //
3721  // Rd = memh/memuh(Rs+#u3:1)
3722  // Rd = memb(Rs+#u3:0)
3723  // Rd = memw(r29+#u5:2) - Handled above.
3724  // Rdd = memd(r29+#u5:3)
3725  // deallocframe
3726  // [if ([!]p0[.new])] dealloc_return
3727  // [if ([!]p0[.new])] jumpr r31
3728  case Hexagon::L2_loadrh_io:
3729  case Hexagon::L2_loadruh_io:
3730  // Rd = memh/memuh(Rs+#u3:1)
3731  DstReg = MI.getOperand(0).getReg();
3732  SrcReg = MI.getOperand(1).getReg();
3733  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3734  MI.getOperand(2).isImm() &&
3735  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3736  return HexagonII::HSIG_L2;
3737  break;
3738  case Hexagon::L2_loadrb_io:
3739  // Rd = memb(Rs+#u3:0)
3740  DstReg = MI.getOperand(0).getReg();
3741  SrcReg = MI.getOperand(1).getReg();
3742  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3743  MI.getOperand(2).isImm() &&
3744  isUInt<3>(MI.getOperand(2).getImm()))
3745  return HexagonII::HSIG_L2;
3746  break;
3747  case Hexagon::L2_loadrd_io:
3748  // Rdd = memd(r29+#u5:3)
3749  DstReg = MI.getOperand(0).getReg();
3750  SrcReg = MI.getOperand(1).getReg();
3751  if (isDblRegForSubInst(DstReg, HRI) &&
3752  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3753  HRI.getStackRegister() == SrcReg &&
3754  MI.getOperand(2).isImm() &&
3755  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3756  return HexagonII::HSIG_L2;
3757  break;
3758  // dealloc_return is not documented in Hexagon Manual, but marked
3759  // with A_SUBINSN attribute in iset_v4classic.py.
3760  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3761  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3762  case Hexagon::L4_return:
3763  case Hexagon::L2_deallocframe:
3764  return HexagonII::HSIG_L2;
3765  case Hexagon::EH_RETURN_JMPR:
3766  case Hexagon::PS_jmpret:
3767  case Hexagon::SL2_jumpr31:
3768  // jumpr r31
3769  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3770  DstReg = MI.getOperand(0).getReg();
3771  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3772  return HexagonII::HSIG_L2;
3773  break;
3774  case Hexagon::PS_jmprett:
3775  case Hexagon::PS_jmpretf:
3776  case Hexagon::PS_jmprettnewpt:
3777  case Hexagon::PS_jmpretfnewpt:
3778  case Hexagon::PS_jmprettnew:
3779  case Hexagon::PS_jmpretfnew:
3780  case Hexagon::SL2_jumpr31_t:
3781  case Hexagon::SL2_jumpr31_f:
3782  case Hexagon::SL2_jumpr31_tnew:
3783  DstReg = MI.getOperand(1).getReg();
3784  SrcReg = MI.getOperand(0).getReg();
3785  // [if ([!]p0[.new])] jumpr r31
3786  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3787  (Hexagon::P0 == SrcReg)) &&
3788  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3789  return HexagonII::HSIG_L2;
3790  break;
3791  case Hexagon::L4_return_t:
3792  case Hexagon::L4_return_f:
3793  case Hexagon::L4_return_tnew_pnt:
3794  case Hexagon::L4_return_fnew_pnt:
3795  case Hexagon::L4_return_tnew_pt:
3796  case Hexagon::L4_return_fnew_pt:
3797  // [if ([!]p0[.new])] dealloc_return
3798  SrcReg = MI.getOperand(0).getReg();
3799  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3800  return HexagonII::HSIG_L2;
3801  break;
3802  //
3803  // Group S1:
3804  //
3805  // memw(Rs+#u4:2) = Rt
3806  // memb(Rs+#u4:0) = Rt
3807  case Hexagon::S2_storeri_io:
3808  // Special case this one from Group S2.
3809  // memw(r29+#u5:2) = Rt
3810  Src1Reg = MI.getOperand(0).getReg();
3811  Src2Reg = MI.getOperand(2).getReg();
3812  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3813  isIntRegForSubInst(Src2Reg) &&
3814  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3815  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3816  return HexagonII::HSIG_S2;
3817  // memw(Rs+#u4:2) = Rt
3818  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3819  MI.getOperand(1).isImm() &&
3820  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3821  return HexagonII::HSIG_S1;
3822  break;
3823  case Hexagon::S2_storerb_io:
3824  // memb(Rs+#u4:0) = Rt
3825  Src1Reg = MI.getOperand(0).getReg();
3826  Src2Reg = MI.getOperand(2).getReg();
3827  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3828  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3829  return HexagonII::HSIG_S1;
3830  break;
3831  //
3832  // Group S2:
3833  //
3834  // memh(Rs+#u3:1) = Rt
3835  // memw(r29+#u5:2) = Rt
3836  // memd(r29+#s6:3) = Rtt
3837  // memw(Rs+#u4:2) = #U1
3838  // memb(Rs+#u4) = #U1
3839  // allocframe(#u5:3)
3840  case Hexagon::S2_storerh_io:
3841  // memh(Rs+#u3:1) = Rt
3842  Src1Reg = MI.getOperand(0).getReg();
3843  Src2Reg = MI.getOperand(2).getReg();
3844  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3845  MI.getOperand(1).isImm() &&
3846  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3847  return HexagonII::HSIG_S1;
3848  break;
3849  case Hexagon::S2_storerd_io:
3850  // memd(r29+#s6:3) = Rtt
3851  Src1Reg = MI.getOperand(0).getReg();
3852  Src2Reg = MI.getOperand(2).getReg();
3853  if (isDblRegForSubInst(Src2Reg, HRI) &&
3854  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3855  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3856  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3857  return HexagonII::HSIG_S2;
3858  break;
3859  case Hexagon::S4_storeiri_io:
3860  // memw(Rs+#u4:2) = #U1
3861  Src1Reg = MI.getOperand(0).getReg();
3862  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3863  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3864  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3865  return HexagonII::HSIG_S2;
3866  break;
3867  case Hexagon::S4_storeirb_io:
3868  // memb(Rs+#u4) = #U1
3869  Src1Reg = MI.getOperand(0).getReg();
3870  if (isIntRegForSubInst(Src1Reg) &&
3871  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3872  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3873  return HexagonII::HSIG_S2;
3874  break;
3875  case Hexagon::S2_allocframe:
3876  if (MI.getOperand(2).isImm() &&
3877  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3878  return HexagonII::HSIG_S1;
3879  break;
3880  //
3881  // Group A:
3882  //
3883  // Rx = add(Rx,#s7)
3884  // Rd = Rs
3885  // Rd = #u6
3886  // Rd = #-1
3887  // if ([!]P0[.new]) Rd = #0
3888  // Rd = add(r29,#u6:2)
3889  // Rx = add(Rx,Rs)
3890  // P0 = cmp.eq(Rs,#u2)
3891  // Rdd = combine(#0,Rs)
3892  // Rdd = combine(Rs,#0)
3893  // Rdd = combine(#u2,#U2)
3894  // Rd = add(Rs,#1)
3895  // Rd = add(Rs,#-1)
3896  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3897  // Rd = and(Rs,#1)
3898  case Hexagon::A2_addi:
3899  DstReg = MI.getOperand(0).getReg();
3900  SrcReg = MI.getOperand(1).getReg();
3901  if (isIntRegForSubInst(DstReg)) {
3902  // Rd = add(r29,#u6:2)
3903  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3904  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3905  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3906  return HexagonII::HSIG_A;
3907  // Rx = add(Rx,#s7)
3908  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3909  isInt<7>(MI.getOperand(2).getImm()))
3910  return HexagonII::HSIG_A;
3911  // Rd = add(Rs,#1)
3912  // Rd = add(Rs,#-1)
3913  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3914  ((MI.getOperand(2).getImm() == 1) ||
3915  (MI.getOperand(2).getImm() == -1)))
3916  return HexagonII::HSIG_A;
3917  }
3918  break;
3919  case Hexagon::A2_add:
3920  // Rx = add(Rx,Rs)
3921  DstReg = MI.getOperand(0).getReg();
3922  Src1Reg = MI.getOperand(1).getReg();
3923  Src2Reg = MI.getOperand(2).getReg();
3924  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3925  isIntRegForSubInst(Src2Reg))
3926  return HexagonII::HSIG_A;
3927  break;
3928  case Hexagon::A2_andir:
3929  // Same as zxtb.
3930  // Rd16=and(Rs16,#255)
3931  // Rd16=and(Rs16,#1)
3932  DstReg = MI.getOperand(0).getReg();
3933  SrcReg = MI.getOperand(1).getReg();
3934  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3935  MI.getOperand(2).isImm() &&
3936  ((MI.getOperand(2).getImm() == 1) ||
3937  (MI.getOperand(2).getImm() == 255)))
3938  return HexagonII::HSIG_A;
3939  break;
3940  case Hexagon::A2_tfr:
3941  // Rd = Rs
3942  DstReg = MI.getOperand(0).getReg();
3943  SrcReg = MI.getOperand(1).getReg();
3944  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3945  return HexagonII::HSIG_A;
3946  break;
3947  case Hexagon::A2_tfrsi:
3948  // Rd = #u6
3949  // Do not test for #u6 size since the const is getting extended
3950  // regardless and compound could be formed.
3951  // Rd = #-1
3952  DstReg = MI.getOperand(0).getReg();
3953  if (isIntRegForSubInst(DstReg))
3954  return HexagonII::HSIG_A;
3955  break;
3956  case Hexagon::C2_cmoveit:
3957  case Hexagon::C2_cmovenewit:
3958  case Hexagon::C2_cmoveif:
3959  case Hexagon::C2_cmovenewif:
3960  // if ([!]P0[.new]) Rd = #0
3961  // Actual form:
3962  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3963  DstReg = MI.getOperand(0).getReg();
3964  SrcReg = MI.getOperand(1).getReg();
3965  if (isIntRegForSubInst(DstReg) &&
3966  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3967  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3968  return HexagonII::HSIG_A;
3969  break;
3970  case Hexagon::C2_cmpeqi:
3971  // P0 = cmp.eq(Rs,#u2)
3972  DstReg = MI.getOperand(0).getReg();
3973  SrcReg = MI.getOperand(1).getReg();
3974  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3975  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3976  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3977  return HexagonII::HSIG_A;
3978  break;
3979  case Hexagon::A2_combineii:
3980  case Hexagon::A4_combineii:
3981  // Rdd = combine(#u2,#U2)
3982  DstReg = MI.getOperand(0).getReg();
3983  if (isDblRegForSubInst(DstReg, HRI) &&
3984  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3985  (MI.getOperand(1).isGlobal() &&
3986  isUInt<2>(MI.getOperand(1).getOffset()))) &&
3987  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3988  (MI.getOperand(2).isGlobal() &&
3989  isUInt<2>(MI.getOperand(2).getOffset()))))
3990  return HexagonII::HSIG_A;
3991  break;
3992  case Hexagon::A4_combineri:
3993  // Rdd = combine(Rs,#0)
3994  DstReg = MI.getOperand(0).getReg();
3995  SrcReg = MI.getOperand(1).getReg();
3996  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3997  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3998  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3999  return HexagonII::HSIG_A;
4000  break;
4001  case Hexagon::A4_combineir:
4002  // Rdd = combine(#0,Rs)
4003  DstReg = MI.getOperand(0).getReg();
4004  SrcReg = MI.getOperand(2).getReg();
4005  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4006  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4007  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4008  return HexagonII::HSIG_A;
4009  break;
4010  case Hexagon::A2_sxtb:
4011  case Hexagon::A2_sxth:
4012  case Hexagon::A2_zxtb:
4013  case Hexagon::A2_zxth:
4014  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4015  DstReg = MI.getOperand(0).getReg();
4016  SrcReg = MI.getOperand(1).getReg();
4017  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4018  return HexagonII::HSIG_A;
4019  break;
4020  }
4021 
4022  return HexagonII::HSIG_None;
4023 }
4024 
4026  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4027 }
4028 
4030  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4031  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4032  // still have a MinLatency property, which getStageLatency checks.
4033  if (!ItinData)
4034  return getInstrLatency(ItinData, MI);
4035 
4036  if (MI.isTransient())
4037  return 0;
4038  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4039 }
4040 
4041 /// getOperandLatency - Compute and return the use operand latency of a given
4042 /// pair of def and use.
4043 /// In most cases, the static scheduling itinerary was enough to determine the
4044 /// operand latency. But it may not be possible for instructions with variable
4045 /// number of defs / uses.
4046 ///
4047 /// This is a raw interface to the itinerary that may be directly overriden by
4048 /// a target. Use computeOperandLatency to get the best estimate of latency.
4050  const MachineInstr &DefMI,
4051  unsigned DefIdx,
4052  const MachineInstr &UseMI,
4053  unsigned UseIdx) const {
4054  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4055 
4056  // Get DefIdx and UseIdx for super registers.
4057  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4058 
4059  if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
4060  if (DefMO.isImplicit()) {
4061  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4062  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4063  if (Idx != -1) {
4064  DefIdx = Idx;
4065  break;
4066  }
4067  }
4068  }
4069 
4070  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4071  if (UseMO.isImplicit()) {
4072  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4073  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4074  if (Idx != -1) {
4075  UseIdx = Idx;
4076  break;
4077  }
4078  }
4079  }
4080  }
4081 
4082  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4083  UseMI, UseIdx);
4084  if (!Latency)
4085  // We should never have 0 cycle latency between two instructions unless
4086  // they can be packetized together. However, this decision can't be made
4087  // here.
4088  Latency = 1;
4089  return Latency;
4090 }
4091 
4092 // inverts the predication logic.
4093 // p -> NotP
4094 // NotP -> P
4096  SmallVectorImpl<MachineOperand> &Cond) const {
4097  if (Cond.empty())
4098  return false;
4099  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4100  Cond[0].setImm(Opc);
4101  return true;
4102 }
4103 
4104 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4105  int InvPredOpcode;
4106  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4107  : Hexagon::getTruePredOpcode(Opc);
4108  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4109  return InvPredOpcode;
4110 
4111  llvm_unreachable("Unexpected predicated instruction");
4112 }
4113 
4114 // Returns the max value that doesn't need to be extended.
4116  const uint64_t F = MI.getDesc().TSFlags;
4117  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4119  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4121 
4122  if (isSigned) // if value is signed
4123  return ~(-1U << (bits - 1));
4124  else
4125  return ~(-1U << bits);
4126 }
4127 
4128 
4130  switch (MI.getOpcode()) {
4131  case Hexagon::L2_loadrbgp:
4132  case Hexagon::L2_loadrdgp:
4133  case Hexagon::L2_loadrhgp:
4134  case Hexagon::L2_loadrigp:
4135  case Hexagon::L2_loadrubgp:
4136  case Hexagon::L2_loadruhgp:
4137  case Hexagon::S2_storerbgp:
4138  case Hexagon::S2_storerbnewgp:
4139  case Hexagon::S2_storerhgp:
4140  case Hexagon::S2_storerhnewgp:
4141  case Hexagon::S2_storerigp:
4142  case Hexagon::S2_storerinewgp:
4143  case Hexagon::S2_storerdgp:
4144  case Hexagon::S2_storerfgp:
4145  return true;
4146  }
4147  const uint64_t F = MI.getDesc().TSFlags;
4148  unsigned addrMode =
4150  // Disallow any base+offset instruction. The assembler does not yet reorder
4151  // based up any zero offset instruction.
4152  return (addrMode == HexagonII::BaseRegOffset ||
4153  addrMode == HexagonII::BaseImmOffset ||
4154  addrMode == HexagonII::BaseLongOffset);
4155 }
4156 
4158  using namespace HexagonII;
4159 
4160  const uint64_t F = MI.getDesc().TSFlags;
4161  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4163  if (Size != 0)
4164  return Size;
4165 
4166  // Handle vector access sizes.
4167  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4168  switch (S) {
4170  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4171  default:
4172  llvm_unreachable("Unexpected instruction");
4173  }
4174 }
4175 
4176 // Returns the min value that doesn't need to be extended.
4178  const uint64_t F = MI.getDesc().TSFlags;
4179  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4181  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4183 
4184  if (isSigned) // if value is signed
4185  return -1U << (bits - 1);
4186  else
4187  return 0;
4188 }
4189 
4190 // Returns opcode of the non-extended equivalent instruction.
4192  // Check if the instruction has a register form that uses register in place
4193  // of the extended operand, if so return that as the non-extended form.
4194  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4195  if (NonExtOpcode >= 0)
4196  return NonExtOpcode;
4197 
4198  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4199  // Check addressing mode and retrieve non-ext equivalent instruction.
4200  switch (getAddrMode(MI)) {
4201  case HexagonII::Absolute:
4202  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4204  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4206  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4207 
4208  default:
4209  return -1;
4210  }
4211  }
4212  return -1;
4213 }
4214 
4216  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4217  if (Cond.empty())
4218  return false;
4219  assert(Cond.size() == 2);
4220  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4221  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4222  return false;
4223  }
4224  PredReg = Cond[1].getReg();
4225  PredRegPos = 1;
4226  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4227  PredRegFlags = 0;
4228  if (Cond[1].isImplicit())
4229  PredRegFlags = RegState::Implicit;
4230  if (Cond[1].isUndef())
4231  PredRegFlags |= RegState::Undef;
4232  return true;
4233 }
4234 
4236  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4237 }
4238 
4240  return Hexagon::getRegForm(MI.getOpcode());
4241 }
4242 
4243 // Return the number of bytes required to encode the instruction.
4244 // Hexagon instructions are fixed length, 4 bytes, unless they
4245 // use a constant extender, which requires another 4 bytes.
4246 // For debug instructions and prolog labels, return 0.
4248  if (MI.isDebugInstr() || MI.isPosition())
4249  return 0;
4250 
4251  unsigned Size = MI.getDesc().getSize();
4252  if (!Size)
4253  // Assume the default insn size in case it cannot be determined
4254  // for whatever reason.
4255  Size = HEXAGON_INSTR_SIZE;
4256 
4257  if (isConstExtended(MI) || isExtended(MI))
4258  Size += HEXAGON_INSTR_SIZE;
4259 
4260  // Try and compute number of instructions in asm.
4262  const MachineBasicBlock &MBB = *MI.getParent();
4263  const MachineFunction *MF = MBB.getParent();
4264  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4265 
4266  // Count the number of register definitions to find the asm string.
4267  unsigned NumDefs = 0;
4268  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4269  ++NumDefs)
4270  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4271 
4272  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4273  // Disassemble the AsmStr and approximate number of instructions.
4274  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4275  Size = getInlineAsmLength(AsmStr, *MAI);
4276  }
4277 
4278  return Size;
4279 }
4280 
4282  const uint64_t F = MI.getDesc().TSFlags;
4283  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4284 }
4285 
4287  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4288  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4289 
4290  return IS.getUnits();
4291 }
4292 
4293 // Calculate size of the basic block without debug instructions.
4295  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4296 }
4297 
4299  MachineBasicBlock::const_iterator BundleHead) const {
4300  assert(BundleHead->isBundle() && "Not a bundle header");
4301  auto MII = BundleHead.getInstrIterator();
4302  // Skip the bundle header.
4303  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4304 }
4305 
4306 /// immediateExtend - Changes the instruction in place to one using an immediate
4307 /// extender.
4309  assert((isExtendable(MI)||isConstExtended(MI)) &&
4310  "Instruction must be extendable");
4311  // Find which operand is extendable.
4312  short ExtOpNum = getCExtOpNum(MI);
4313  MachineOperand &MO = MI.getOperand(ExtOpNum);
4314  // This needs to be something we understand.
4315  assert((MO.isMBB() || MO.isImm()) &&
4316  "Branch with unknown extendable field type");
4317  // Mark given operand as extended.
4319 }
4320 
4322  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4323  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4324  << printMBBReference(*NewTarget);
4325  MI.dump(););
4326  assert(MI.isBranch());
4327  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4328  int TargetPos = MI.getNumOperands() - 1;
4329  // In general branch target is the last operand,
4330  // but some implicit defs added at the end might change it.
4331  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4332  --TargetPos;
4333  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4334  MI.getOperand(TargetPos).setMBB(NewTarget);
4336  NewOpcode = reversePrediction(NewOpcode);
4337  }
4338  MI.setDesc(get(NewOpcode));
4339  return true;
4340 }
4341 
4343  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4345  MachineBasicBlock &B = *A;
4347  DebugLoc DL = I->getDebugLoc();
4348  MachineInstr *NewMI;
4349 
4350  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4351  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4352  NewMI = BuildMI(B, I, DL, get(insn));
4353  LLVM_DEBUG(dbgs() << "\n"
4354  << getName(NewMI->getOpcode())
4355  << " Class: " << NewMI->getDesc().getSchedClass());
4356  NewMI->eraseFromParent();
4357  }
4358  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4359 }
4360 
4361 // inverts the predication logic.
4362 // p -> NotP
4363 // NotP -> P
4365  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4367  return true;
4368 }
4369 
4370 // Reverse the branch prediction.
4371 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4372  int PredRevOpcode = -1;
4373  if (isPredictedTaken(Opcode))
4374  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4375  else
4376  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4377  assert(PredRevOpcode > 0);
4378  return PredRevOpcode;
4379 }
4380 
4381 // TODO: Add more rigorous validation.
4383  const {
4384  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4385 }
4386 
4387 void HexagonInstrInfo::
4389  assert(MIB->isBundle());
4390  MachineOperand &Operand = MIB->getOperand(0);
4391  if (Operand.isImm())
4392  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4393  else
4394  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4395 }
4396 
4398  assert(MIB.isBundle());
4399  const MachineOperand &Operand = MIB.getOperand(0);
4400  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4401 }
4402 
4403 // Addressing mode relations.
4405  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4406 }
4407 
4409  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4410 }
4411 
4413  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4414 }
4415 
4417  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4418 }
4419 
4421  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4422 }
4423 
4425  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4426 }
4427 
4429  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4430 }
4431 
4433  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4434 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
void push_back(const T &Elt)
Definition: SmallVector.h:218
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:675
short changeAddrMode_rr_io(short Opc) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool isInlineAsm() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
demanded bits
MachineBasicBlock reference.
#define HEXAGON_INSTR_SIZE
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:393
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:412
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:476
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:627
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:663
bool isEndLoopN(unsigned Opcode) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isBundle() const
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:657
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:623
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:571
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:694
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const char * getSeparatorString() const
Definition: MCAsmInfo.h:480
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
Definition: He