LLVM  7.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
16 #include "HexagonFrameLowering.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
80 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
98 
99 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
101  cl::desc("Use the DFA based hazard recognizer."));
102 
103 /// Constants for Hexagon instructions.
104 const int Hexagon_MEMW_OFFSET_MAX = 4095;
105 const int Hexagon_MEMW_OFFSET_MIN = -4096;
106 const int Hexagon_MEMD_OFFSET_MAX = 8191;
107 const int Hexagon_MEMD_OFFSET_MIN = -8192;
108 const int Hexagon_MEMH_OFFSET_MAX = 2047;
109 const int Hexagon_MEMH_OFFSET_MIN = -2048;
110 const int Hexagon_MEMB_OFFSET_MAX = 1023;
111 const int Hexagon_MEMB_OFFSET_MIN = -1024;
112 const int Hexagon_ADDI_OFFSET_MAX = 32767;
113 const int Hexagon_ADDI_OFFSET_MIN = -32768;
114 
115 // Pin the vtable to this file.
116 void HexagonInstrInfo::anchor() {}
117 
119  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
120  Subtarget(ST) {}
121 
122 static bool isIntRegForSubInst(unsigned Reg) {
123  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
124  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
125 }
126 
127 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
128  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
129  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
130 }
131 
132 /// Calculate number of instructions excluding the debug instructions.
135  unsigned Count = 0;
136  for (; MIB != MIE; ++MIB) {
137  if (!MIB->isDebugInstr())
138  ++Count;
139  }
140  return Count;
141 }
142 
143 /// Find the hardware loop instruction used to set-up the specified loop.
144 /// On Hexagon, we have two instructions used to set-up the hardware loop
145 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
146 /// to indicate the end of a loop.
148  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
149  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
150  unsigned LOOPi;
151  unsigned LOOPr;
152  if (EndLoopOp == Hexagon::ENDLOOP0) {
153  LOOPi = Hexagon::J2_loop0i;
154  LOOPr = Hexagon::J2_loop0r;
155  } else { // EndLoopOp == Hexagon::EndLOOP1
156  LOOPi = Hexagon::J2_loop1i;
157  LOOPr = Hexagon::J2_loop1r;
158  }
159 
160  // The loop set-up instruction will be in a predecessor block
161  for (MachineBasicBlock *PB : BB->predecessors()) {
162  // If this has been visited, already skip it.
163  if (!Visited.insert(PB).second)
164  continue;
165  if (PB == BB)
166  continue;
167  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
168  unsigned Opc = I->getOpcode();
169  if (Opc == LOOPi || Opc == LOOPr)
170  return &*I;
171  // We've reached a different loop, which means the loop01 has been
172  // removed.
173  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
174  return nullptr;
175  }
176  // Check the predecessors for the LOOP instruction.
177  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
178  return Loop;
179  }
180  return nullptr;
181 }
182 
183 /// Gather register def/uses from MI.
184 /// This treats possible (predicated) defs as actually happening ones
185 /// (conservatively).
186 static inline void parseOperands(const MachineInstr &MI,
188  Defs.clear();
189  Uses.clear();
190 
191  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
192  const MachineOperand &MO = MI.getOperand(i);
193 
194  if (!MO.isReg())
195  continue;
196 
197  unsigned Reg = MO.getReg();
198  if (!Reg)
199  continue;
200 
201  if (MO.isUse())
202  Uses.push_back(MO.getReg());
203 
204  if (MO.isDef())
205  Defs.push_back(MO.getReg());
206  }
207 }
208 
209 // Position dependent, so check twice for swap.
210 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
211  switch (Ga) {
213  default:
214  return false;
215  case HexagonII::HSIG_L1:
216  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
217  case HexagonII::HSIG_L2:
218  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
219  Gb == HexagonII::HSIG_A);
220  case HexagonII::HSIG_S1:
221  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
222  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
223  case HexagonII::HSIG_S2:
224  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
225  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
226  Gb == HexagonII::HSIG_A);
227  case HexagonII::HSIG_A:
228  return (Gb == HexagonII::HSIG_A);
230  return (Gb == HexagonII::HSIG_Compound);
231  }
232  return false;
233 }
234 
235 /// isLoadFromStackSlot - If the specified machine instruction is a direct
236 /// load from a stack slot, return the virtual or physical register number of
237 /// the destination along with the FrameIndex of the loaded stack slot. If
238 /// not, return 0. This predicate must return 0 if the instruction has
239 /// any side effects other than loading from the stack slot.
241  int &FrameIndex) const {
242  switch (MI.getOpcode()) {
243  default:
244  break;
245  case Hexagon::L2_loadri_io:
246  case Hexagon::L2_loadrd_io:
247  case Hexagon::V6_vL32b_ai:
248  case Hexagon::V6_vL32b_nt_ai:
249  case Hexagon::V6_vL32Ub_ai:
250  case Hexagon::LDriw_pred:
251  case Hexagon::LDriw_ctr:
252  case Hexagon::PS_vloadrq_ai:
253  case Hexagon::PS_vloadrw_ai:
254  case Hexagon::PS_vloadrw_nt_ai: {
255  const MachineOperand OpFI = MI.getOperand(1);
256  if (!OpFI.isFI())
257  return 0;
258  const MachineOperand OpOff = MI.getOperand(2);
259  if (!OpOff.isImm() || OpOff.getImm() != 0)
260  return 0;
261  FrameIndex = OpFI.getIndex();
262  return MI.getOperand(0).getReg();
263  }
264 
265  case Hexagon::L2_ploadrit_io:
266  case Hexagon::L2_ploadrif_io:
267  case Hexagon::L2_ploadrdt_io:
268  case Hexagon::L2_ploadrdf_io: {
269  const MachineOperand OpFI = MI.getOperand(2);
270  if (!OpFI.isFI())
271  return 0;
272  const MachineOperand OpOff = MI.getOperand(3);
273  if (!OpOff.isImm() || OpOff.getImm() != 0)
274  return 0;
275  FrameIndex = OpFI.getIndex();
276  return MI.getOperand(0).getReg();
277  }
278  }
279 
280  return 0;
281 }
282 
283 /// isStoreToStackSlot - If the specified machine instruction is a direct
284 /// store to a stack slot, return the virtual or physical register number of
285 /// the source reg along with the FrameIndex of the loaded stack slot. If
286 /// not, return 0. This predicate must return 0 if the instruction has
287 /// any side effects other than storing to the stack slot.
289  int &FrameIndex) const {
290  switch (MI.getOpcode()) {
291  default:
292  break;
293  case Hexagon::S2_storerb_io:
294  case Hexagon::S2_storerh_io:
295  case Hexagon::S2_storeri_io:
296  case Hexagon::S2_storerd_io:
297  case Hexagon::V6_vS32b_ai:
298  case Hexagon::V6_vS32Ub_ai:
299  case Hexagon::STriw_pred:
300  case Hexagon::STriw_ctr:
301  case Hexagon::PS_vstorerq_ai:
302  case Hexagon::PS_vstorerw_ai: {
303  const MachineOperand &OpFI = MI.getOperand(0);
304  if (!OpFI.isFI())
305  return 0;
306  const MachineOperand &OpOff = MI.getOperand(1);
307  if (!OpOff.isImm() || OpOff.getImm() != 0)
308  return 0;
309  FrameIndex = OpFI.getIndex();
310  return MI.getOperand(2).getReg();
311  }
312 
313  case Hexagon::S2_pstorerbt_io:
314  case Hexagon::S2_pstorerbf_io:
315  case Hexagon::S2_pstorerht_io:
316  case Hexagon::S2_pstorerhf_io:
317  case Hexagon::S2_pstorerit_io:
318  case Hexagon::S2_pstorerif_io:
319  case Hexagon::S2_pstorerdt_io:
320  case Hexagon::S2_pstorerdf_io: {
321  const MachineOperand &OpFI = MI.getOperand(1);
322  if (!OpFI.isFI())
323  return 0;
324  const MachineOperand &OpOff = MI.getOperand(2);
325  if (!OpOff.isImm() || OpOff.getImm() != 0)
326  return 0;
327  FrameIndex = OpFI.getIndex();
328  return MI.getOperand(3).getReg();
329  }
330  }
331 
332  return 0;
333 }
334 
335 /// This function checks if the instruction or bundle of instructions
336 /// has load from stack slot and returns frameindex and machine memory
337 /// operand of that instruction if true.
339  const MachineMemOperand *&MMO,
340  int &FrameIndex) const {
341  if (MI.isBundle()) {
342  const MachineBasicBlock *MBB = MI.getParent();
344  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
345  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, MMO, FrameIndex))
346  return true;
347  return false;
348  }
349 
350  return TargetInstrInfo::hasLoadFromStackSlot(MI, MMO, FrameIndex);
351 }
352 
353 /// This function checks if the instruction or bundle of instructions
354 /// has store to stack slot and returns frameindex and machine memory
355 /// operand of that instruction if true.
357  const MachineMemOperand *&MMO,
358  int &FrameIndex) const {
359  if (MI.isBundle()) {
360  const MachineBasicBlock *MBB = MI.getParent();
362  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
363  if (TargetInstrInfo::hasStoreToStackSlot(*MII, MMO, FrameIndex))
364  return true;
365  return false;
366  }
367 
368  return TargetInstrInfo::hasStoreToStackSlot(MI, MMO, FrameIndex);
369 }
370 
371 /// This function can analyze one/two way branching only and should (mostly) be
372 /// called by target independent side.
373 /// First entry is always the opcode of the branching instruction, except when
374 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
375 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
376 /// e.g. Jump_c p will have
377 /// Cond[0] = Jump_c
378 /// Cond[1] = p
379 /// HW-loop ENDLOOP:
380 /// Cond[0] = ENDLOOP
381 /// Cond[1] = MBB
382 /// New value jump:
383 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
384 /// Cond[1] = R
385 /// Cond[2] = Imm
387  MachineBasicBlock *&TBB,
388  MachineBasicBlock *&FBB,
390  bool AllowModify) const {
391  TBB = nullptr;
392  FBB = nullptr;
393  Cond.clear();
394 
395  // If the block has no terminators, it just falls into the block after it.
397  if (I == MBB.instr_begin())
398  return false;
399 
400  // A basic block may looks like this:
401  //
402  // [ insn
403  // EH_LABEL
404  // insn
405  // insn
406  // insn
407  // EH_LABEL
408  // insn ]
409  //
410  // It has two succs but does not have a terminator
411  // Don't know how to handle it.
412  do {
413  --I;
414  if (I->isEHLabel())
415  // Don't analyze EH branches.
416  return true;
417  } while (I != MBB.instr_begin());
418 
419  I = MBB.instr_end();
420  --I;
421 
422  while (I->isDebugInstr()) {
423  if (I == MBB.instr_begin())
424  return false;
425  --I;
426  }
427 
428  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
429  I->getOperand(0).isMBB();
430  // Delete the J2_jump if it's equivalent to a fall-through.
431  if (AllowModify && JumpToBlock &&
432  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
433  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
434  I->eraseFromParent();
435  I = MBB.instr_end();
436  if (I == MBB.instr_begin())
437  return false;
438  --I;
439  }
440  if (!isUnpredicatedTerminator(*I))
441  return false;
442 
443  // Get the last instruction in the block.
444  MachineInstr *LastInst = &*I;
445  MachineInstr *SecondLastInst = nullptr;
446  // Find one more terminator if present.
447  while (true) {
448  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
449  if (!SecondLastInst)
450  SecondLastInst = &*I;
451  else
452  // This is a third branch.
453  return true;
454  }
455  if (I == MBB.instr_begin())
456  break;
457  --I;
458  }
459 
460  int LastOpcode = LastInst->getOpcode();
461  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
462  // If the branch target is not a basic block, it could be a tail call.
463  // (It is, if the target is a function.)
464  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
465  return true;
466  if (SecLastOpcode == Hexagon::J2_jump &&
467  !SecondLastInst->getOperand(0).isMBB())
468  return true;
469 
470  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
471  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
472 
473  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
474  return true;
475 
476  // If there is only one terminator instruction, process it.
477  if (LastInst && !SecondLastInst) {
478  if (LastOpcode == Hexagon::J2_jump) {
479  TBB = LastInst->getOperand(0).getMBB();
480  return false;
481  }
482  if (isEndLoopN(LastOpcode)) {
483  TBB = LastInst->getOperand(0).getMBB();
484  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
485  Cond.push_back(LastInst->getOperand(0));
486  return false;
487  }
488  if (LastOpcodeHasJMP_c) {
489  TBB = LastInst->getOperand(1).getMBB();
490  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
491  Cond.push_back(LastInst->getOperand(0));
492  return false;
493  }
494  // Only supporting rr/ri versions of new-value jumps.
495  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
496  TBB = LastInst->getOperand(2).getMBB();
497  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
498  Cond.push_back(LastInst->getOperand(0));
499  Cond.push_back(LastInst->getOperand(1));
500  return false;
501  }
502  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
503  << " with one jump\n";);
504  // Otherwise, don't know what this is.
505  return true;
506  }
507 
508  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
509  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
510  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
511  if (!SecondLastInst->getOperand(1).isMBB())
512  return true;
513  TBB = SecondLastInst->getOperand(1).getMBB();
514  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
515  Cond.push_back(SecondLastInst->getOperand(0));
516  FBB = LastInst->getOperand(0).getMBB();
517  return false;
518  }
519 
520  // Only supporting rr/ri versions of new-value jumps.
521  if (SecLastOpcodeHasNVJump &&
522  (SecondLastInst->getNumExplicitOperands() == 3) &&
523  (LastOpcode == Hexagon::J2_jump)) {
524  TBB = SecondLastInst->getOperand(2).getMBB();
525  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
526  Cond.push_back(SecondLastInst->getOperand(0));
527  Cond.push_back(SecondLastInst->getOperand(1));
528  FBB = LastInst->getOperand(0).getMBB();
529  return false;
530  }
531 
532  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
533  // executed, so remove it.
534  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
535  TBB = SecondLastInst->getOperand(0).getMBB();
536  I = LastInst->getIterator();
537  if (AllowModify)
538  I->eraseFromParent();
539  return false;
540  }
541 
542  // If the block ends with an ENDLOOP, and J2_jump, handle it.
543  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
544  TBB = SecondLastInst->getOperand(0).getMBB();
545  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
546  Cond.push_back(SecondLastInst->getOperand(0));
547  FBB = LastInst->getOperand(0).getMBB();
548  return false;
549  }
550  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
551  << " with two jumps";);
552  // Otherwise, can't handle this.
553  return true;
554 }
555 
557  int *BytesRemoved) const {
558  assert(!BytesRemoved && "code size not handled");
559 
560  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
562  unsigned Count = 0;
563  while (I != MBB.begin()) {
564  --I;
565  if (I->isDebugInstr())
566  continue;
567  // Only removing branches from end of MBB.
568  if (!I->isBranch())
569  return Count;
570  if (Count && (I->getOpcode() == Hexagon::J2_jump))
571  llvm_unreachable("Malformed basic block: unconditional branch not last");
572  MBB.erase(&MBB.back());
573  I = MBB.end();
574  ++Count;
575  }
576  return Count;
577 }
578 
580  MachineBasicBlock *TBB,
581  MachineBasicBlock *FBB,
583  const DebugLoc &DL,
584  int *BytesAdded) const {
585  unsigned BOpc = Hexagon::J2_jump;
586  unsigned BccOpc = Hexagon::J2_jumpt;
587  assert(validateBranchCond(Cond) && "Invalid branching condition");
588  assert(TBB && "insertBranch must not be told to insert a fallthrough");
589  assert(!BytesAdded && "code size not handled");
590 
591  // Check if reverseBranchCondition has asked to reverse this branch
592  // If we want to reverse the branch an odd number of times, we want
593  // J2_jumpf.
594  if (!Cond.empty() && Cond[0].isImm())
595  BccOpc = Cond[0].getImm();
596 
597  if (!FBB) {
598  if (Cond.empty()) {
599  // Due to a bug in TailMerging/CFG Optimization, we need to add a
600  // special case handling of a predicated jump followed by an
601  // unconditional jump. If not, Tail Merging and CFG Optimization go
602  // into an infinite loop.
603  MachineBasicBlock *NewTBB, *NewFBB;
605  auto Term = MBB.getFirstTerminator();
606  if (Term != MBB.end() && isPredicated(*Term) &&
607  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
608  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
610  removeBranch(MBB);
611  return insertBranch(MBB, TBB, nullptr, Cond, DL);
612  }
613  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
614  } else if (isEndLoopN(Cond[0].getImm())) {
615  int EndLoopOp = Cond[0].getImm();
616  assert(Cond[1].isMBB());
617  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
618  // Check for it, and change the BB target if needed.
620  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
621  VisitedBBs);
622  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
623  Loop->getOperand(0).setMBB(TBB);
624  // Add the ENDLOOP after the finding the LOOP0.
625  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
626  } else if (isNewValueJump(Cond[0].getImm())) {
627  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
628  // New value jump
629  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
630  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
631  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
632  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
633  << printMBBReference(MBB););
634  if (Cond[2].isReg()) {
635  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
636  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
637  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
638  } else if(Cond[2].isImm()) {
639  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
640  addImm(Cond[2].getImm()).addMBB(TBB);
641  } else
642  llvm_unreachable("Invalid condition for branching");
643  } else {
644  assert((Cond.size() == 2) && "Malformed cond vector");
645  const MachineOperand &RO = Cond[1];
646  unsigned Flags = getUndefRegState(RO.isUndef());
647  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
648  }
649  return 1;
650  }
651  assert((!Cond.empty()) &&
652  "Cond. cannot be empty when multiple branchings are required");
653  assert((!isNewValueJump(Cond[0].getImm())) &&
654  "NV-jump cannot be inserted with another branch");
655  // Special case for hardware loops. The condition is a basic block.
656  if (isEndLoopN(Cond[0].getImm())) {
657  int EndLoopOp = Cond[0].getImm();
658  assert(Cond[1].isMBB());
659  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
660  // Check for it, and change the BB target if needed.
662  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
663  VisitedBBs);
664  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
665  Loop->getOperand(0).setMBB(TBB);
666  // Add the ENDLOOP after the finding the LOOP0.
667  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
668  } else {
669  const MachineOperand &RO = Cond[1];
670  unsigned Flags = getUndefRegState(RO.isUndef());
671  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
672  }
673  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
674 
675  return 2;
676 }
677 
678 /// Analyze the loop code to find the loop induction variable and compare used
679 /// to compute the number of iterations. Currently, we analyze loop that are
680 /// controlled using hardware loops. In this case, the induction variable
681 /// instruction is null. For all other cases, this function returns true, which
682 /// means we're unable to analyze it.
684  MachineInstr *&IndVarInst,
685  MachineInstr *&CmpInst) const {
686 
687  MachineBasicBlock *LoopEnd = L.getBottomBlock();
689  // We really "analyze" only hardware loops right now.
690  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
691  IndVarInst = nullptr;
692  CmpInst = &*I;
693  return false;
694  }
695  return true;
696 }
697 
698 /// Generate code to reduce the loop iteration by one and check if the loop is
699 /// finished. Return the value/register of the new loop count. this function
700 /// assumes the nth iteration is peeled first.
702  MachineInstr *IndVar, MachineInstr &Cmp,
705  unsigned Iter, unsigned MaxIter) const {
706  // We expect a hardware loop currently. This means that IndVar is set
707  // to null, and the compare is the ENDLOOP instruction.
708  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
709  && "Expecting a hardware loop");
710  MachineFunction *MF = MBB.getParent();
711  DebugLoc DL = Cmp.getDebugLoc();
713  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
714  Cmp.getOperand(0).getMBB(), VisitedBBs);
715  if (!Loop)
716  return 0;
717  // If the loop trip count is a compile-time value, then just change the
718  // value.
719  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
720  Loop->getOpcode() == Hexagon::J2_loop1i) {
721  int64_t Offset = Loop->getOperand(1).getImm();
722  if (Offset <= 1)
723  Loop->eraseFromParent();
724  else
725  Loop->getOperand(1).setImm(Offset - 1);
726  return Offset - 1;
727  }
728  // The loop trip count is a run-time value. We generate code to subtract
729  // one from the trip count, and update the loop instruction.
730  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
731  unsigned LoopCount = Loop->getOperand(1).getReg();
732  // Check if we're done with the loop.
733  unsigned LoopEnd = createVR(MF, MVT::i1);
734  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
735  addReg(LoopCount).addImm(1);
736  unsigned NewLoopCount = createVR(MF, MVT::i32);
737  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
738  addReg(LoopCount).addImm(-1);
739  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
740  // Update the previously generated instructions with the new loop counter.
742  E = PrevInsts.end(); I != E; ++I)
743  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
744  PrevInsts.clear();
745  PrevInsts.push_back(NewCmp);
746  PrevInsts.push_back(NewAdd);
747  // Insert the new loop instruction if this is the last time the loop is
748  // decremented.
749  if (Iter == MaxIter)
750  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
751  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
752  // Delete the old loop instruction.
753  if (Iter == 0)
754  Loop->eraseFromParent();
755  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
756  Cond.push_back(NewCmp->getOperand(0));
757  return NewLoopCount;
758 }
759 
761  unsigned NumCycles, unsigned ExtraPredCycles,
762  BranchProbability Probability) const {
763  return nonDbgBBSize(&MBB) <= 3;
764 }
765 
767  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
768  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
769  const {
770  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
771 }
772 
774  unsigned NumInstrs, BranchProbability Probability) const {
775  return NumInstrs <= 4;
776 }
777 
780  const DebugLoc &DL, unsigned DestReg,
781  unsigned SrcReg, bool KillSrc) const {
782  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
783  unsigned KillFlag = getKillRegState(KillSrc);
784 
785  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
786  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
787  .addReg(SrcReg, KillFlag);
788  return;
789  }
790  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
791  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
792  .addReg(SrcReg, KillFlag);
793  return;
794  }
795  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
796  // Map Pd = Ps to Pd = or(Ps, Ps).
797  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
798  .addReg(SrcReg).addReg(SrcReg, KillFlag);
799  return;
800  }
801  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
802  Hexagon::IntRegsRegClass.contains(SrcReg)) {
803  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
804  .addReg(SrcReg, KillFlag);
805  return;
806  }
807  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
808  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
809  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
810  .addReg(SrcReg, KillFlag);
811  return;
812  }
813  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
814  Hexagon::IntRegsRegClass.contains(SrcReg)) {
815  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
816  .addReg(SrcReg, KillFlag);
817  return;
818  }
819  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
820  Hexagon::IntRegsRegClass.contains(DestReg)) {
821  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
822  .addReg(SrcReg, KillFlag);
823  return;
824  }
825  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
826  Hexagon::PredRegsRegClass.contains(DestReg)) {
827  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
828  .addReg(SrcReg, KillFlag);
829  return;
830  }
831  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
832  Hexagon::IntRegsRegClass.contains(DestReg)) {
833  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
834  .addReg(SrcReg, KillFlag);
835  return;
836  }
837  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
838  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
839  addReg(SrcReg, KillFlag);
840  return;
841  }
842  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
843  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
844  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
845  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
846  .addReg(HiSrc, KillFlag)
847  .addReg(LoSrc, KillFlag);
848  return;
849  }
850  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
851  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
852  .addReg(SrcReg)
853  .addReg(SrcReg, KillFlag);
854  return;
855  }
856  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
857  Hexagon::HvxVRRegClass.contains(DestReg)) {
858  llvm_unreachable("Unimplemented pred to vec");
859  return;
860  }
861  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
862  Hexagon::HvxVRRegClass.contains(SrcReg)) {
863  llvm_unreachable("Unimplemented vec to pred");
864  return;
865  }
866 
867 #ifndef NDEBUG
868  // Show the invalid registers to ease debugging.
869  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
870  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
871 #endif
872  llvm_unreachable("Unimplemented");
873 }
874 
876  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
877  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
878  DebugLoc DL = MBB.findDebugLoc(I);
879  MachineFunction &MF = *MBB.getParent();
880  MachineFrameInfo &MFI = MF.getFrameInfo();
881  unsigned SlotAlign = MFI.getObjectAlignment(FI);
882  unsigned RegAlign = TRI->getSpillAlignment(*RC);
883  unsigned KillFlag = getKillRegState(isKill);
884  bool HasAlloca = MFI.hasVarSizedObjects();
885  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
886 
889  MFI.getObjectSize(FI), SlotAlign);
890 
891  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
892  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
893  .addFrameIndex(FI).addImm(0)
894  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
895  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
896  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
897  .addFrameIndex(FI).addImm(0)
898  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
899  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
900  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
901  .addFrameIndex(FI).addImm(0)
902  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
903  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
904  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
905  .addFrameIndex(FI).addImm(0)
906  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
907  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
908  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
909  .addFrameIndex(FI).addImm(0)
910  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
911  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
912  // If there are variable-sized objects, spills will not be aligned.
913  if (HasAlloca)
914  SlotAlign = HFI.getStackAlignment();
915  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
916  : Hexagon::V6_vS32b_ai;
919  MFI.getObjectSize(FI), SlotAlign);
920  BuildMI(MBB, I, DL, get(Opc))
921  .addFrameIndex(FI).addImm(0)
922  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
923  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
924  // If there are variable-sized objects, spills will not be aligned.
925  if (HasAlloca)
926  SlotAlign = HFI.getStackAlignment();
927  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
928  : Hexagon::PS_vstorerw_ai;
931  MFI.getObjectSize(FI), SlotAlign);
932  BuildMI(MBB, I, DL, get(Opc))
933  .addFrameIndex(FI).addImm(0)
934  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
935  } else {
936  llvm_unreachable("Unimplemented");
937  }
938 }
939 
941  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
942  int FI, const TargetRegisterClass *RC,
943  const TargetRegisterInfo *TRI) const {
944  DebugLoc DL = MBB.findDebugLoc(I);
945  MachineFunction &MF = *MBB.getParent();
946  MachineFrameInfo &MFI = MF.getFrameInfo();
947  unsigned SlotAlign = MFI.getObjectAlignment(FI);
948  unsigned RegAlign = TRI->getSpillAlignment(*RC);
949  bool HasAlloca = MFI.hasVarSizedObjects();
950  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
951 
954  MFI.getObjectSize(FI), SlotAlign);
955 
956  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
957  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
958  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
959  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
960  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
961  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
962  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
963  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
964  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
965  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
966  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
967  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
968  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
969  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
970  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
972  // If there are variable-sized objects, spills will not be aligned.
973  if (HasAlloca)
974  SlotAlign = HFI.getStackAlignment();
975  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
976  : Hexagon::V6_vL32b_ai;
979  MFI.getObjectSize(FI), SlotAlign);
980  BuildMI(MBB, I, DL, get(Opc), DestReg)
981  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
982  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
983  // If there are variable-sized objects, spills will not be aligned.
984  if (HasAlloca)
985  SlotAlign = HFI.getStackAlignment();
986  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
987  : Hexagon::PS_vloadrw_ai;
990  MFI.getObjectSize(FI), SlotAlign);
991  BuildMI(MBB, I, DL, get(Opc), DestReg)
992  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
993  } else {
994  llvm_unreachable("Can't store this register to stack slot");
995  }
996 }
997 
999  const MachineBasicBlock &B = *MI.getParent();
1000  Regs.addLiveOuts(B);
1001  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1002  for (auto I = B.rbegin(); I != E; ++I)
1003  Regs.stepBackward(*I);
1004 }
1005 
1006 /// expandPostRAPseudo - This function is called for all pseudo instructions
1007 /// that remain after register allocation. Many pseudo instructions are
1008 /// created to help register allocation. This is the place to convert them
1009 /// into real instructions. The target can edit MI in place, or it can insert
1010 /// new instructions and erase MI. The function should return true if
1011 /// anything was changed.
1013  MachineBasicBlock &MBB = *MI.getParent();
1014  MachineFunction &MF = *MBB.getParent();
1016  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1017  DebugLoc DL = MI.getDebugLoc();
1018  unsigned Opc = MI.getOpcode();
1019 
1020  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1021  unsigned Mx = MI.getOperand(MxOp).getReg();
1022  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1023  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1024  .add(MI.getOperand((HasImm ? 5 : 4)));
1025  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1026  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1027  if (HasImm)
1028  MIB.add(MI.getOperand(4));
1029  MIB.addReg(CSx, RegState::Implicit);
1030  MBB.erase(MI);
1031  return true;
1032  };
1033 
1034  switch (Opc) {
1035  case TargetOpcode::COPY: {
1036  MachineOperand &MD = MI.getOperand(0);
1037  MachineOperand &MS = MI.getOperand(1);
1039  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1040  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1041  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1042  }
1043  MBB.erase(MBBI);
1044  return true;
1045  }
1046  case Hexagon::PS_aligna:
1047  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1048  .addReg(HRI.getFrameRegister())
1049  .addImm(-MI.getOperand(1).getImm());
1050  MBB.erase(MI);
1051  return true;
1052  case Hexagon::V6_vassignp: {
1053  unsigned SrcReg = MI.getOperand(1).getReg();
1054  unsigned DstReg = MI.getOperand(0).getReg();
1055  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1056  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1057  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1058  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1059  MBB.erase(MI);
1060  return true;
1061  }
1062  case Hexagon::V6_lo: {
1063  unsigned SrcReg = MI.getOperand(1).getReg();
1064  unsigned DstReg = MI.getOperand(0).getReg();
1065  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1066  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1067  MBB.erase(MI);
1068  MRI.clearKillFlags(SrcSubLo);
1069  return true;
1070  }
1071  case Hexagon::V6_hi: {
1072  unsigned SrcReg = MI.getOperand(1).getReg();
1073  unsigned DstReg = MI.getOperand(0).getReg();
1074  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1075  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1076  MBB.erase(MI);
1077  MRI.clearKillFlags(SrcSubHi);
1078  return true;
1079  }
1080  case Hexagon::PS_vstorerw_ai:
1081  case Hexagon::PS_vstorerwu_ai: {
1082  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1083  unsigned SrcReg = MI.getOperand(2).getReg();
1084  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1085  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1086  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1087  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1088 
1089  MachineInstr *MI1New =
1090  BuildMI(MBB, MI, DL, get(NewOpc))
1091  .add(MI.getOperand(0))
1092  .addImm(MI.getOperand(1).getImm())
1093  .addReg(SrcSubLo)
1095  MI1New->getOperand(0).setIsKill(false);
1096  BuildMI(MBB, MI, DL, get(NewOpc))
1097  .add(MI.getOperand(0))
1098  // The Vectors are indexed in multiples of vector size.
1099  .addImm(MI.getOperand(1).getImm() + Offset)
1100  .addReg(SrcSubHi)
1102  MBB.erase(MI);
1103  return true;
1104  }
1105  case Hexagon::PS_vloadrw_ai:
1106  case Hexagon::PS_vloadrwu_ai: {
1107  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1108  unsigned DstReg = MI.getOperand(0).getReg();
1109  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1110  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1111 
1112  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1113  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1114  .add(MI.getOperand(1))
1115  .addImm(MI.getOperand(2).getImm())
1116  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1117  MI1New->getOperand(1).setIsKill(false);
1118  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1119  .add(MI.getOperand(1))
1120  // The Vectors are indexed in multiples of vector size.
1121  .addImm(MI.getOperand(2).getImm() + Offset)
1122  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1123  MBB.erase(MI);
1124  return true;
1125  }
1126  case Hexagon::PS_true: {
1127  unsigned Reg = MI.getOperand(0).getReg();
1128  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1129  .addReg(Reg, RegState::Undef)
1130  .addReg(Reg, RegState::Undef);
1131  MBB.erase(MI);
1132  return true;
1133  }
1134  case Hexagon::PS_false: {
1135  unsigned Reg = MI.getOperand(0).getReg();
1136  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1137  .addReg(Reg, RegState::Undef)
1138  .addReg(Reg, RegState::Undef);
1139  MBB.erase(MI);
1140  return true;
1141  }
1142  case Hexagon::PS_qtrue: {
1143  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1144  .addReg(Hexagon::V0, RegState::Undef)
1145  .addReg(Hexagon::V0, RegState::Undef);
1146  MBB.erase(MI);
1147  return true;
1148  }
1149  case Hexagon::PS_qfalse: {
1150  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1151  .addReg(Hexagon::V0, RegState::Undef)
1152  .addReg(Hexagon::V0, RegState::Undef);
1153  MBB.erase(MI);
1154  return true;
1155  }
1156  case Hexagon::PS_vdd0: {
1157  unsigned Vd = MI.getOperand(0).getReg();
1158  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1159  .addReg(Vd, RegState::Undef)
1160  .addReg(Vd, RegState::Undef);
1161  MBB.erase(MI);
1162  return true;
1163  }
1164  case Hexagon::PS_vmulw: {
1165  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1166  unsigned DstReg = MI.getOperand(0).getReg();
1167  unsigned Src1Reg = MI.getOperand(1).getReg();
1168  unsigned Src2Reg = MI.getOperand(2).getReg();
1169  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1170  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1171  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1172  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1173  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1174  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1175  .addReg(Src1SubHi)
1176  .addReg(Src2SubHi);
1177  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1178  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1179  .addReg(Src1SubLo)
1180  .addReg(Src2SubLo);
1181  MBB.erase(MI);
1182  MRI.clearKillFlags(Src1SubHi);
1183  MRI.clearKillFlags(Src1SubLo);
1184  MRI.clearKillFlags(Src2SubHi);
1185  MRI.clearKillFlags(Src2SubLo);
1186  return true;
1187  }
1188  case Hexagon::PS_vmulw_acc: {
1189  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1190  unsigned DstReg = MI.getOperand(0).getReg();
1191  unsigned Src1Reg = MI.getOperand(1).getReg();
1192  unsigned Src2Reg = MI.getOperand(2).getReg();
1193  unsigned Src3Reg = MI.getOperand(3).getReg();
1194  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1195  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1196  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1197  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1198  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1199  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1200  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1201  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1202  .addReg(Src1SubHi)
1203  .addReg(Src2SubHi)
1204  .addReg(Src3SubHi);
1205  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1206  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1207  .addReg(Src1SubLo)
1208  .addReg(Src2SubLo)
1209  .addReg(Src3SubLo);
1210  MBB.erase(MI);
1211  MRI.clearKillFlags(Src1SubHi);
1212  MRI.clearKillFlags(Src1SubLo);
1213  MRI.clearKillFlags(Src2SubHi);
1214  MRI.clearKillFlags(Src2SubLo);
1215  MRI.clearKillFlags(Src3SubHi);
1216  MRI.clearKillFlags(Src3SubLo);
1217  return true;
1218  }
1219  case Hexagon::PS_pselect: {
1220  const MachineOperand &Op0 = MI.getOperand(0);
1221  const MachineOperand &Op1 = MI.getOperand(1);
1222  const MachineOperand &Op2 = MI.getOperand(2);
1223  const MachineOperand &Op3 = MI.getOperand(3);
1224  unsigned Rd = Op0.getReg();
1225  unsigned Pu = Op1.getReg();
1226  unsigned Rs = Op2.getReg();
1227  unsigned Rt = Op3.getReg();
1228  DebugLoc DL = MI.getDebugLoc();
1229  unsigned K1 = getKillRegState(Op1.isKill());
1230  unsigned K2 = getKillRegState(Op2.isKill());
1231  unsigned K3 = getKillRegState(Op3.isKill());
1232  if (Rd != Rs)
1233  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1234  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1235  .addReg(Rs, K2);
1236  if (Rd != Rt)
1237  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1238  .addReg(Pu, K1)
1239  .addReg(Rt, K3);
1240  MBB.erase(MI);
1241  return true;
1242  }
1243  case Hexagon::PS_vselect: {
1244  const MachineOperand &Op0 = MI.getOperand(0);
1245  const MachineOperand &Op1 = MI.getOperand(1);
1246  const MachineOperand &Op2 = MI.getOperand(2);
1247  const MachineOperand &Op3 = MI.getOperand(3);
1248  LivePhysRegs LiveAtMI(HRI);
1249  getLiveRegsAt(LiveAtMI, MI);
1250  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1251  unsigned PReg = Op1.getReg();
1252  assert(Op1.getSubReg() == 0);
1253  unsigned PState = getRegState(Op1);
1254 
1255  if (Op0.getReg() != Op2.getReg()) {
1256  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1257  : PState;
1258  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1259  .add(Op0)
1260  .addReg(PReg, S)
1261  .add(Op2);
1262  if (IsDestLive)
1263  T.addReg(Op0.getReg(), RegState::Implicit);
1264  IsDestLive = true;
1265  }
1266  if (Op0.getReg() != Op3.getReg()) {
1267  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1268  .add(Op0)
1269  .addReg(PReg, PState)
1270  .add(Op3);
1271  if (IsDestLive)
1272  T.addReg(Op0.getReg(), RegState::Implicit);
1273  }
1274  MBB.erase(MI);
1275  return true;
1276  }
1277  case Hexagon::PS_wselect: {
1278  MachineOperand &Op0 = MI.getOperand(0);
1279  MachineOperand &Op1 = MI.getOperand(1);
1280  MachineOperand &Op2 = MI.getOperand(2);
1281  MachineOperand &Op3 = MI.getOperand(3);
1282  LivePhysRegs LiveAtMI(HRI);
1283  getLiveRegsAt(LiveAtMI, MI);
1284  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1285  unsigned PReg = Op1.getReg();
1286  assert(Op1.getSubReg() == 0);
1287  unsigned PState = getRegState(Op1);
1288 
1289  if (Op0.getReg() != Op2.getReg()) {
1290  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1291  : PState;
1292  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1293  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1294  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1295  .add(Op0)
1296  .addReg(PReg, S)
1297  .add(Op1)
1298  .addReg(SrcHi)
1299  .addReg(SrcLo);
1300  if (IsDestLive)
1301  T.addReg(Op0.getReg(), RegState::Implicit);
1302  IsDestLive = true;
1303  }
1304  if (Op0.getReg() != Op3.getReg()) {
1305  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1306  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1307  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1308  .add(Op0)
1309  .addReg(PReg, PState)
1310  .addReg(SrcHi)
1311  .addReg(SrcLo);
1312  if (IsDestLive)
1313  T.addReg(Op0.getReg(), RegState::Implicit);
1314  }
1315  MBB.erase(MI);
1316  return true;
1317  }
1318 
1319  case Hexagon::PS_tailcall_i:
1320  MI.setDesc(get(Hexagon::J2_jump));
1321  return true;
1322  case Hexagon::PS_tailcall_r:
1323  case Hexagon::PS_jmpret:
1324  MI.setDesc(get(Hexagon::J2_jumpr));
1325  return true;
1326  case Hexagon::PS_jmprett:
1327  MI.setDesc(get(Hexagon::J2_jumprt));
1328  return true;
1329  case Hexagon::PS_jmpretf:
1330  MI.setDesc(get(Hexagon::J2_jumprf));
1331  return true;
1332  case Hexagon::PS_jmprettnewpt:
1333  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1334  return true;
1335  case Hexagon::PS_jmpretfnewpt:
1336  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1337  return true;
1338  case Hexagon::PS_jmprettnew:
1339  MI.setDesc(get(Hexagon::J2_jumprtnew));
1340  return true;
1341  case Hexagon::PS_jmpretfnew:
1342  MI.setDesc(get(Hexagon::J2_jumprfnew));
1343  return true;
1344 
1345  case Hexagon::V6_vgathermh_pseudo:
1346  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1347  .add(MI.getOperand(1))
1348  .add(MI.getOperand(2))
1349  .add(MI.getOperand(3));
1350  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1351  .add(MI.getOperand(0))
1352  .addImm(0)
1353  .addReg(Hexagon::VTMP);
1354  MBB.erase(MI);
1355  return true;
1356 
1357  case Hexagon::V6_vgathermw_pseudo:
1358  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1359  .add(MI.getOperand(1))
1360  .add(MI.getOperand(2))
1361  .add(MI.getOperand(3));
1362  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1363  .add(MI.getOperand(0))
1364  .addImm(0)
1365  .addReg(Hexagon::VTMP);
1366  MBB.erase(MI);
1367  return true;
1368 
1369  case Hexagon::V6_vgathermhw_pseudo:
1370  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1371  .add(MI.getOperand(1))
1372  .add(MI.getOperand(2))
1373  .add(MI.getOperand(3));
1374  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1375  .add(MI.getOperand(0))
1376  .addImm(0)
1377  .addReg(Hexagon::VTMP);
1378  MBB.erase(MI);
1379  return true;
1380 
1381  case Hexagon::V6_vgathermhq_pseudo:
1382  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1383  .add(MI.getOperand(1))
1384  .add(MI.getOperand(2))
1385  .add(MI.getOperand(3))
1386  .add(MI.getOperand(4));
1387  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1388  .add(MI.getOperand(0))
1389  .addImm(0)
1390  .addReg(Hexagon::VTMP);
1391  MBB.erase(MI);
1392  return true;
1393 
1394  case Hexagon::V6_vgathermwq_pseudo:
1395  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1396  .add(MI.getOperand(1))
1397  .add(MI.getOperand(2))
1398  .add(MI.getOperand(3))
1399  .add(MI.getOperand(4));
1400  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1401  .add(MI.getOperand(0))
1402  .addImm(0)
1403  .addReg(Hexagon::VTMP);
1404  MBB.erase(MI);
1405  return true;
1406 
1407  case Hexagon::V6_vgathermhwq_pseudo:
1408  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1409  .add(MI.getOperand(1))
1410  .add(MI.getOperand(2))
1411  .add(MI.getOperand(3))
1412  .add(MI.getOperand(4));
1413  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1414  .add(MI.getOperand(0))
1415  .addImm(0)
1416  .addReg(Hexagon::VTMP);
1417  MBB.erase(MI);
1418  return true;
1419 
1420  case Hexagon::PS_loadrub_pci:
1421  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1422  case Hexagon::PS_loadrb_pci:
1423  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1424  case Hexagon::PS_loadruh_pci:
1425  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1426  case Hexagon::PS_loadrh_pci:
1427  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1428  case Hexagon::PS_loadri_pci:
1429  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1430  case Hexagon::PS_loadrd_pci:
1431  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1432  case Hexagon::PS_loadrub_pcr:
1433  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1434  case Hexagon::PS_loadrb_pcr:
1435  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1436  case Hexagon::PS_loadruh_pcr:
1437  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1438  case Hexagon::PS_loadrh_pcr:
1439  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1440  case Hexagon::PS_loadri_pcr:
1441  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1442  case Hexagon::PS_loadrd_pcr:
1443  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1444  case Hexagon::PS_storerb_pci:
1445  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1446  case Hexagon::PS_storerh_pci:
1447  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1448  case Hexagon::PS_storerf_pci:
1449  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1450  case Hexagon::PS_storeri_pci:
1451  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1452  case Hexagon::PS_storerd_pci:
1453  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1454  case Hexagon::PS_storerb_pcr:
1455  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1456  case Hexagon::PS_storerh_pcr:
1457  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1458  case Hexagon::PS_storerf_pcr:
1459  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1460  case Hexagon::PS_storeri_pcr:
1461  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1462  case Hexagon::PS_storerd_pcr:
1463  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1464  }
1465 
1466  return false;
1467 }
1468 
1469 // We indicate that we want to reverse the branch by
1470 // inserting the reversed branching opcode.
1472  SmallVectorImpl<MachineOperand> &Cond) const {
1473  if (Cond.empty())
1474  return true;
1475  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1476  unsigned opcode = Cond[0].getImm();
1477  //unsigned temp;
1478  assert(get(opcode).isBranch() && "Should be a branching condition.");
1479  if (isEndLoopN(opcode))
1480  return true;
1481  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1482  Cond[0].setImm(NewOpcode);
1483  return false;
1484 }
1485 
1488  DebugLoc DL;
1489  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1490 }
1491 
1493  return getAddrMode(MI) == HexagonII::PostInc;
1494 }
1495 
1496 // Returns true if an instruction is predicated irrespective of the predicate
1497 // sense. For example, all of the following will return true.
1498 // if (p0) R1 = add(R2, R3)
1499 // if (!p0) R1 = add(R2, R3)
1500 // if (p0.new) R1 = add(R2, R3)
1501 // if (!p0.new) R1 = add(R2, R3)
1502 // Note: New-value stores are not included here as in the current
1503 // implementation, we don't need to check their predicate sense.
1505  const uint64_t F = MI.getDesc().TSFlags;
1507 }
1508 
1510  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1511  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1512  isEndLoopN(Cond[0].getImm())) {
1513  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1514  return false;
1515  }
1516  int Opc = MI.getOpcode();
1517  assert (isPredicable(MI) && "Expected predicable instruction");
1518  bool invertJump = predOpcodeHasNot(Cond);
1519 
1520  // We have to predicate MI "in place", i.e. after this function returns,
1521  // MI will need to be transformed into a predicated form. To avoid com-
1522  // plicated manipulations with the operands (handling tied operands,
1523  // etc.), build a new temporary instruction, then overwrite MI with it.
1524 
1525  MachineBasicBlock &B = *MI.getParent();
1526  DebugLoc DL = MI.getDebugLoc();
1527  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1528  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1529  unsigned NOp = 0, NumOps = MI.getNumOperands();
1530  while (NOp < NumOps) {
1531  MachineOperand &Op = MI.getOperand(NOp);
1532  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1533  break;
1534  T.add(Op);
1535  NOp++;
1536  }
1537 
1538  unsigned PredReg, PredRegPos, PredRegFlags;
1539  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1540  (void)GotPredReg;
1541  assert(GotPredReg);
1542  T.addReg(PredReg, PredRegFlags);
1543  while (NOp < NumOps)
1544  T.add(MI.getOperand(NOp++));
1545 
1546  MI.setDesc(get(PredOpc));
1547  while (unsigned n = MI.getNumOperands())
1548  MI.RemoveOperand(n-1);
1549  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1550  MI.addOperand(T->getOperand(i));
1551 
1553  B.erase(TI);
1554 
1556  MRI.clearKillFlags(PredReg);
1557  return true;
1558 }
1559 
1561  ArrayRef<MachineOperand> Pred2) const {
1562  // TODO: Fix this
1563  return false;
1564 }
1565 
1567  std::vector<MachineOperand> &Pred) const {
1568  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1569 
1570  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1571  MachineOperand MO = MI.getOperand(oper);
1572  if (MO.isReg()) {
1573  if (!MO.isDef())
1574  continue;
1575  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1576  if (RC == &Hexagon::PredRegsRegClass) {
1577  Pred.push_back(MO);
1578  return true;
1579  }
1580  continue;
1581  } else if (MO.isRegMask()) {
1582  for (unsigned PR : Hexagon::PredRegsRegClass) {
1583  if (!MI.modifiesRegister(PR, &HRI))
1584  continue;
1585  Pred.push_back(MO);
1586  return true;
1587  }
1588  }
1589  }
1590  return false;
1591 }
1592 
1594  if (!MI.getDesc().isPredicable())
1595  return false;
1596 
1597  if (MI.isCall() || isTailCall(MI)) {
1598  if (!Subtarget.usePredicatedCalls())
1599  return false;
1600  }
1601 
1602  // HVX loads are not predicable on v60, but are on v62.
1603  if (!Subtarget.hasV62Ops()) {
1604  switch (MI.getOpcode()) {
1605  case Hexagon::V6_vL32b_ai:
1606  case Hexagon::V6_vL32b_pi:
1607  case Hexagon::V6_vL32b_ppu:
1608  case Hexagon::V6_vL32b_cur_ai:
1609  case Hexagon::V6_vL32b_cur_pi:
1610  case Hexagon::V6_vL32b_cur_ppu:
1611  case Hexagon::V6_vL32b_nt_ai:
1612  case Hexagon::V6_vL32b_nt_pi:
1613  case Hexagon::V6_vL32b_nt_ppu:
1614  case Hexagon::V6_vL32b_tmp_ai:
1615  case Hexagon::V6_vL32b_tmp_pi:
1616  case Hexagon::V6_vL32b_tmp_ppu:
1617  case Hexagon::V6_vL32b_nt_cur_ai:
1618  case Hexagon::V6_vL32b_nt_cur_pi:
1619  case Hexagon::V6_vL32b_nt_cur_ppu:
1620  case Hexagon::V6_vL32b_nt_tmp_ai:
1621  case Hexagon::V6_vL32b_nt_tmp_pi:
1622  case Hexagon::V6_vL32b_nt_tmp_ppu:
1623  return false;
1624  }
1625  }
1626  return true;
1627 }
1628 
1630  const MachineBasicBlock *MBB,
1631  const MachineFunction &MF) const {
1632  // Debug info is never a scheduling boundary. It's necessary to be explicit
1633  // due to the special treatment of IT instructions below, otherwise a
1634  // dbg_value followed by an IT will result in the IT instruction being
1635  // considered a scheduling hazard, which is wrong. It should be the actual
1636  // instruction preceding the dbg_value instruction(s), just like it is
1637  // when debug info is not present.
1638  if (MI.isDebugInstr())
1639  return false;
1640 
1641  // Throwing call is a boundary.
1642  if (MI.isCall()) {
1643  // Don't mess around with no return calls.
1644  if (doesNotReturn(MI))
1645  return true;
1646  // If any of the block's successors is a landing pad, this could be a
1647  // throwing call.
1648  for (auto I : MBB->successors())
1649  if (I->isEHPad())
1650  return true;
1651  }
1652 
1653  // Terminators and labels can't be scheduled around.
1654  if (MI.getDesc().isTerminator() || MI.isPosition())
1655  return true;
1656 
1657  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1658  return true;
1659 
1660  return false;
1661 }
1662 
1663 /// Measure the specified inline asm to determine an approximation of its
1664 /// length.
1665 /// Comments (which run till the next SeparatorString or newline) do not
1666 /// count as an instruction.
1667 /// Any other non-whitespace text is considered an instruction, with
1668 /// multiple instructions separated by SeparatorString or newlines.
1669 /// Variable-length instructions are not handled here; this function
1670 /// may be overloaded in the target code to do that.
1671 /// Hexagon counts the number of ##'s and adjust for that many
1672 /// constant exenders.
1673 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1674  const MCAsmInfo &MAI) const {
1675  StringRef AStr(Str);
1676  // Count the number of instructions in the asm.
1677  bool atInsnStart = true;
1678  unsigned Length = 0;
1679  for (; *Str; ++Str) {
1680  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1681  strlen(MAI.getSeparatorString())) == 0)
1682  atInsnStart = true;
1683  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1684  Length += MAI.getMaxInstLength();
1685  atInsnStart = false;
1686  }
1687  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1688  MAI.getCommentString().size()) == 0)
1689  atInsnStart = false;
1690  }
1691 
1692  // Add to size number of constant extenders seen * 4.
1693  StringRef Occ("##");
1694  Length += AStr.count(Occ)*4;
1695  return Length;
1696 }
1697 
1700  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1701  if (UseDFAHazardRec)
1702  return new HexagonHazardRecognizer(II, this, Subtarget);
1704 }
1705 
1706 /// For a comparison instruction, return the source registers in
1707 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1708 /// compares against in CmpValue. Return true if the comparison instruction
1709 /// can be analyzed.
1710 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1711  unsigned &SrcReg2, int &Mask,
1712  int &Value) const {
1713  unsigned Opc = MI.getOpcode();
1714 
1715  // Set mask and the first source register.
1716  switch (Opc) {
1717  case Hexagon::C2_cmpeq:
1718  case Hexagon::C2_cmpeqp:
1719  case Hexagon::C2_cmpgt:
1720  case Hexagon::C2_cmpgtp:
1721  case Hexagon::C2_cmpgtu:
1722  case Hexagon::C2_cmpgtup:
1723  case Hexagon::C4_cmpneq:
1724  case Hexagon::C4_cmplte:
1725  case Hexagon::C4_cmplteu:
1726  case Hexagon::C2_cmpeqi:
1727  case Hexagon::C2_cmpgti:
1728  case Hexagon::C2_cmpgtui:
1729  case Hexagon::C4_cmpneqi:
1730  case Hexagon::C4_cmplteui:
1731  case Hexagon::C4_cmpltei:
1732  SrcReg = MI.getOperand(1).getReg();
1733  Mask = ~0;
1734  break;
1735  case Hexagon::A4_cmpbeq:
1736  case Hexagon::A4_cmpbgt:
1737  case Hexagon::A4_cmpbgtu:
1738  case Hexagon::A4_cmpbeqi:
1739  case Hexagon::A4_cmpbgti:
1740  case Hexagon::A4_cmpbgtui:
1741  SrcReg = MI.getOperand(1).getReg();
1742  Mask = 0xFF;
1743  break;
1744  case Hexagon::A4_cmpheq:
1745  case Hexagon::A4_cmphgt:
1746  case Hexagon::A4_cmphgtu:
1747  case Hexagon::A4_cmpheqi:
1748  case Hexagon::A4_cmphgti:
1749  case Hexagon::A4_cmphgtui:
1750  SrcReg = MI.getOperand(1).getReg();
1751  Mask = 0xFFFF;
1752  break;
1753  }
1754 
1755  // Set the value/second source register.
1756  switch (Opc) {
1757  case Hexagon::C2_cmpeq:
1758  case Hexagon::C2_cmpeqp:
1759  case Hexagon::C2_cmpgt:
1760  case Hexagon::C2_cmpgtp:
1761  case Hexagon::C2_cmpgtu:
1762  case Hexagon::C2_cmpgtup:
1763  case Hexagon::A4_cmpbeq:
1764  case Hexagon::A4_cmpbgt:
1765  case Hexagon::A4_cmpbgtu:
1766  case Hexagon::A4_cmpheq:
1767  case Hexagon::A4_cmphgt:
1768  case Hexagon::A4_cmphgtu:
1769  case Hexagon::C4_cmpneq:
1770  case Hexagon::C4_cmplte:
1771  case Hexagon::C4_cmplteu:
1772  SrcReg2 = MI.getOperand(2).getReg();
1773  return true;
1774 
1775  case Hexagon::C2_cmpeqi:
1776  case Hexagon::C2_cmpgtui:
1777  case Hexagon::C2_cmpgti:
1778  case Hexagon::C4_cmpneqi:
1779  case Hexagon::C4_cmplteui:
1780  case Hexagon::C4_cmpltei:
1781  case Hexagon::A4_cmpbeqi:
1782  case Hexagon::A4_cmpbgti:
1783  case Hexagon::A4_cmpbgtui:
1784  case Hexagon::A4_cmpheqi:
1785  case Hexagon::A4_cmphgti:
1786  case Hexagon::A4_cmphgtui: {
1787  SrcReg2 = 0;
1788  const MachineOperand &Op2 = MI.getOperand(2);
1789  if (!Op2.isImm())
1790  return false;
1791  Value = MI.getOperand(2).getImm();
1792  return true;
1793  }
1794  }
1795 
1796  return false;
1797 }
1798 
1800  const MachineInstr &MI,
1801  unsigned *PredCost) const {
1802  return getInstrTimingClassLatency(ItinData, MI);
1803 }
1804 
1806  const TargetSubtargetInfo &STI) const {
1807  const InstrItineraryData *II = STI.getInstrItineraryData();
1808  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1809 }
1810 
1811 // Inspired by this pair:
1812 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1813 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1814 // Currently AA considers the addresses in these instructions to be aliasing.
1816  MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1817  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1819  return false;
1820 
1821  // Instructions that are pure loads, not loads and stores like memops are not
1822  // dependent.
1823  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1824  return true;
1825 
1826  // Get the base register in MIa.
1827  unsigned BasePosA, OffsetPosA;
1828  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1829  return false;
1830  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1831  unsigned BaseRegA = BaseA.getReg();
1832  unsigned BaseSubA = BaseA.getSubReg();
1833 
1834  // Get the base register in MIb.
1835  unsigned BasePosB, OffsetPosB;
1836  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1837  return false;
1838  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1839  unsigned BaseRegB = BaseB.getReg();
1840  unsigned BaseSubB = BaseB.getSubReg();
1841 
1842  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1843  return false;
1844 
1845  // Get the access sizes.
1846  unsigned SizeA = getMemAccessSize(MIa);
1847  unsigned SizeB = getMemAccessSize(MIb);
1848 
1849  // Get the offsets. Handle immediates only for now.
1850  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1851  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1852  if (!MIa.getOperand(OffsetPosA).isImm() ||
1853  !MIb.getOperand(OffsetPosB).isImm())
1854  return false;
1855  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1856  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1857 
1858  // This is a mem access with the same base register and known offsets from it.
1859  // Reason about it.
1860  if (OffsetA > OffsetB) {
1861  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1862  return SizeB <= OffDiff;
1863  }
1864  if (OffsetA < OffsetB) {
1865  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1866  return SizeA <= OffDiff;
1867  }
1868 
1869  return false;
1870 }
1871 
1872 /// If the instruction is an increment of a constant value, return the amount.
1874  int &Value) const {
1875  if (isPostIncrement(MI)) {
1876  unsigned BasePos = 0, OffsetPos = 0;
1877  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1878  return false;
1879  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1880  if (OffsetOp.isImm()) {
1881  Value = OffsetOp.getImm();
1882  return true;
1883  }
1884  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1885  const MachineOperand &AddOp = MI.getOperand(2);
1886  if (AddOp.isImm()) {
1887  Value = AddOp.getImm();
1888  return true;
1889  }
1890  }
1891 
1892  return false;
1893 }
1894 
1895 std::pair<unsigned, unsigned>
1897  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1898  TF & HexagonII::MO_Bitmasks);
1899 }
1900 
1903  using namespace HexagonII;
1904 
1905  static const std::pair<unsigned, const char*> Flags[] = {
1906  {MO_PCREL, "hexagon-pcrel"},
1907  {MO_GOT, "hexagon-got"},
1908  {MO_LO16, "hexagon-lo16"},
1909  {MO_HI16, "hexagon-hi16"},
1910  {MO_GPREL, "hexagon-gprel"},
1911  {MO_GDGOT, "hexagon-gdgot"},
1912  {MO_GDPLT, "hexagon-gdplt"},
1913  {MO_IE, "hexagon-ie"},
1914  {MO_IEGOT, "hexagon-iegot"},
1915  {MO_TPREL, "hexagon-tprel"}
1916  };
1917  return makeArrayRef(Flags);
1918 }
1919 
1922  using namespace HexagonII;
1923 
1924  static const std::pair<unsigned, const char*> Flags[] = {
1925  {HMOTF_ConstExtended, "hexagon-ext"}
1926  };
1927  return makeArrayRef(Flags);
1928 }
1929 
1932  const TargetRegisterClass *TRC;
1933  if (VT == MVT::i1) {
1934  TRC = &Hexagon::PredRegsRegClass;
1935  } else if (VT == MVT::i32 || VT == MVT::f32) {
1936  TRC = &Hexagon::IntRegsRegClass;
1937  } else if (VT == MVT::i64 || VT == MVT::f64) {
1938  TRC = &Hexagon::DoubleRegsRegClass;
1939  } else {
1940  llvm_unreachable("Cannot handle this register class");
1941  }
1942 
1943  unsigned NewReg = MRI.createVirtualRegister(TRC);
1944  return NewReg;
1945 }
1946 
1948  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1949 }
1950 
1952  const uint64_t F = MI.getDesc().TSFlags;
1954 }
1955 
1957  return getAddrMode(MI) == HexagonII::BaseImmOffset;
1958 }
1959 
1961  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
1962  !MI.getDesc().mayStore() &&
1963  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
1964  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
1965  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
1966 }
1967 
1968 // Return true if the instruction is a compund branch instruction.
1970  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1971 }
1972 
1973 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1974 // isFPImm and later getFPImm as well.
1976  const uint64_t F = MI.getDesc().TSFlags;
1978  if (isExtended) // Instruction must be extended.
1979  return true;
1980 
1981  unsigned isExtendable =
1983  if (!isExtendable)
1984  return false;
1985 
1986  if (MI.isCall())
1987  return false;
1988 
1989  short ExtOpNum = getCExtOpNum(MI);
1990  const MachineOperand &MO = MI.getOperand(ExtOpNum);
1991  // Use MO operand flags to determine if MO
1992  // has the HMOTF_ConstExtended flag set.
1994  return true;
1995  // If this is a Machine BB address we are talking about, and it is
1996  // not marked as extended, say so.
1997  if (MO.isMBB())
1998  return false;
1999 
2000  // We could be using an instruction with an extendable immediate and shoehorn
2001  // a global address into it. If it is a global address it will be constant
2002  // extended. We do this for COMBINE.
2003  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2004  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2005  return true;
2006 
2007  // If the extendable operand is not 'Immediate' type, the instruction should
2008  // have 'isExtended' flag set.
2009  assert(MO.isImm() && "Extendable operand must be Immediate type");
2010 
2011  int MinValue = getMinValue(MI);
2012  int MaxValue = getMaxValue(MI);
2013  int ImmValue = MO.getImm();
2014 
2015  return (ImmValue < MinValue || ImmValue > MaxValue);
2016 }
2017 
2019  switch (MI.getOpcode()) {
2020  case Hexagon::L4_return:
2021  case Hexagon::L4_return_t:
2022  case Hexagon::L4_return_f:
2023  case Hexagon::L4_return_tnew_pnt:
2024  case Hexagon::L4_return_fnew_pnt:
2025  case Hexagon::L4_return_tnew_pt:
2026  case Hexagon::L4_return_fnew_pt:
2027  return true;
2028  }
2029  return false;
2030 }
2031 
2032 // Return true when ConsMI uses a register defined by ProdMI.
2034  const MachineInstr &ConsMI) const {
2035  if (!ProdMI.getDesc().getNumDefs())
2036  return false;
2037  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2038 
2043 
2044  parseOperands(ProdMI, DefsA, UsesA);
2045  parseOperands(ConsMI, DefsB, UsesB);
2046 
2047  for (auto &RegA : DefsA)
2048  for (auto &RegB : UsesB) {
2049  // True data dependency.
2050  if (RegA == RegB)
2051  return true;
2052 
2054  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2055  if (RegB == *SubRegs)
2056  return true;
2057 
2059  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2060  if (RegA == *SubRegs)
2061  return true;
2062  }
2063 
2064  return false;
2065 }
2066 
2067 // Returns true if the instruction is alread a .cur.
2069  switch (MI.getOpcode()) {
2070  case Hexagon::V6_vL32b_cur_pi:
2071  case Hexagon::V6_vL32b_cur_ai:
2072  return true;
2073  }
2074  return false;
2075 }
2076 
2077 // Returns true, if any one of the operands is a dot new
2078 // insn, whether it is predicated dot new or register dot new.
2080  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2081  return true;
2082 
2083  return false;
2084 }
2085 
2086 /// Symmetrical. See if these two instructions are fit for duplex pair.
2088  const MachineInstr &MIb) const {
2091  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2092 }
2093 
2095  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2096  return true;
2097 
2098  // Multiply
2099  unsigned SchedClass = MI.getDesc().getSchedClass();
2100  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2101 }
2102 
2103 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2104  return (Opcode == Hexagon::ENDLOOP0 ||
2105  Opcode == Hexagon::ENDLOOP1);
2106 }
2107 
2108 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2109  switch(OpType) {
2116  return true;
2117  default:
2118  return false;
2119  }
2120 }
2121 
2123  const MCInstrDesc &MID = MI.getDesc();
2124  const uint64_t F = MID.TSFlags;
2126  return true;
2127 
2128  // TODO: This is largely obsolete now. Will need to be removed
2129  // in consecutive patches.
2130  switch (MI.getOpcode()) {
2131  // PS_fi and PS_fia remain special cases.
2132  case Hexagon::PS_fi:
2133  case Hexagon::PS_fia:
2134  return true;
2135  default:
2136  return false;
2137  }
2138  return false;
2139 }
2140 
2141 // This returns true in two cases:
2142 // - The OP code itself indicates that this is an extended instruction.
2143 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2145  // First check if this is permanently extended op code.
2146  const uint64_t F = MI.getDesc().TSFlags;
2148  return true;
2149  // Use MO operand flags to determine if one of MI's operands
2150  // has HMOTF_ConstExtended flag set.
2151  for (const MachineOperand &MO : MI.operands())
2152  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2153  return true;
2154  return false;
2155 }
2156 
2158  unsigned Opcode = MI.getOpcode();
2159  const uint64_t F = get(Opcode).TSFlags;
2160  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2161 }
2162 
2163 // No V60 HVX VMEM with A_INDIRECT.
2165  const MachineInstr &J) const {
2166  if (!isHVXVec(I))
2167  return false;
2168  if (!I.mayLoad() && !I.mayStore())
2169  return false;
2170  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2171 }
2172 
2174  switch (MI.getOpcode()) {
2175  case Hexagon::J2_callr:
2176  case Hexagon::J2_callrf:
2177  case Hexagon::J2_callrt:
2178  case Hexagon::PS_call_nr:
2179  return true;
2180  }
2181  return false;
2182 }
2183 
2185  switch (MI.getOpcode()) {
2186  case Hexagon::L4_return:
2187  case Hexagon::L4_return_t:
2188  case Hexagon::L4_return_f:
2189  case Hexagon::L4_return_fnew_pnt:
2190  case Hexagon::L4_return_fnew_pt:
2191  case Hexagon::L4_return_tnew_pnt:
2192  case Hexagon::L4_return_tnew_pt:
2193  return true;
2194  }
2195  return false;
2196 }
2197 
2199  switch (MI.getOpcode()) {
2200  case Hexagon::J2_jumpr:
2201  case Hexagon::J2_jumprt:
2202  case Hexagon::J2_jumprf:
2203  case Hexagon::J2_jumprtnewpt:
2204  case Hexagon::J2_jumprfnewpt:
2205  case Hexagon::J2_jumprtnew:
2206  case Hexagon::J2_jumprfnew:
2207  return true;
2208  }
2209  return false;
2210 }
2211 
2212 // Return true if a given MI can accommodate given offset.
2213 // Use abs estimate as oppose to the exact number.
2214 // TODO: This will need to be changed to use MC level
2215 // definition of instruction extendable field size.
2217  unsigned offset) const {
2218  // This selection of jump instructions matches to that what
2219  // analyzeBranch can parse, plus NVJ.
2220  if (isNewValueJump(MI)) // r9:2
2221  return isInt<11>(offset);
2222 
2223  switch (MI.getOpcode()) {
2224  // Still missing Jump to address condition on register value.
2225  default:
2226  return false;
2227  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2228  case Hexagon::J2_call:
2229  case Hexagon::PS_call_nr:
2230  return isInt<24>(offset);
2231  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2232  case Hexagon::J2_jumpf:
2233  case Hexagon::J2_jumptnew:
2234  case Hexagon::J2_jumptnewpt:
2235  case Hexagon::J2_jumpfnew:
2236  case Hexagon::J2_jumpfnewpt:
2237  case Hexagon::J2_callt:
2238  case Hexagon::J2_callf:
2239  return isInt<17>(offset);
2240  case Hexagon::J2_loop0i:
2241  case Hexagon::J2_loop0iext:
2242  case Hexagon::J2_loop0r:
2243  case Hexagon::J2_loop0rext:
2244  case Hexagon::J2_loop1i:
2245  case Hexagon::J2_loop1iext:
2246  case Hexagon::J2_loop1r:
2247  case Hexagon::J2_loop1rext:
2248  return isInt<9>(offset);
2249  // TODO: Add all the compound branches here. Can we do this in Relation model?
2250  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2251  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2252  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2253  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2254  return isInt<11>(offset);
2255  }
2256 }
2257 
2259  const MachineInstr &ESMI) const {
2260  bool isLate = isLateResultInstr(LRMI);
2261  bool isEarly = isEarlySourceInstr(ESMI);
2262 
2263  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2264  LLVM_DEBUG(LRMI.dump());
2265  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2266  LLVM_DEBUG(ESMI.dump());
2267 
2268  if (isLate && isEarly) {
2269  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2270  return true;
2271  }
2272 
2273  return false;
2274 }
2275 
2277  switch (MI.getOpcode()) {
2278  case TargetOpcode::EXTRACT_SUBREG:
2279  case TargetOpcode::INSERT_SUBREG:
2280  case TargetOpcode::SUBREG_TO_REG:
2281  case TargetOpcode::REG_SEQUENCE:
2282  case TargetOpcode::IMPLICIT_DEF:
2283  case TargetOpcode::COPY:
2285  case TargetOpcode::PHI:
2286  return false;
2287  default:
2288  break;
2289  }
2290 
2291  unsigned SchedClass = MI.getDesc().getSchedClass();
2292  return !is_TC1(SchedClass);
2293 }
2294 
2296  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2297  // resource, but all operands can be received late like an ALU instruction.
2298  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2299 }
2300 
2302  unsigned Opcode = MI.getOpcode();
2303  return Opcode == Hexagon::J2_loop0i ||
2304  Opcode == Hexagon::J2_loop0r ||
2305  Opcode == Hexagon::J2_loop0iext ||
2306  Opcode == Hexagon::J2_loop0rext ||
2307  Opcode == Hexagon::J2_loop1i ||
2308  Opcode == Hexagon::J2_loop1r ||
2309  Opcode == Hexagon::J2_loop1iext ||
2310  Opcode == Hexagon::J2_loop1rext;
2311 }
2312 
2314  switch (MI.getOpcode()) {
2315  default: return false;
2316  case Hexagon::L4_iadd_memopw_io:
2317  case Hexagon::L4_isub_memopw_io:
2318  case Hexagon::L4_add_memopw_io:
2319  case Hexagon::L4_sub_memopw_io:
2320  case Hexagon::L4_and_memopw_io:
2321  case Hexagon::L4_or_memopw_io:
2322  case Hexagon::L4_iadd_memoph_io:
2323  case Hexagon::L4_isub_memoph_io:
2324  case Hexagon::L4_add_memoph_io:
2325  case Hexagon::L4_sub_memoph_io:
2326  case Hexagon::L4_and_memoph_io:
2327  case Hexagon::L4_or_memoph_io:
2328  case Hexagon::L4_iadd_memopb_io:
2329  case Hexagon::L4_isub_memopb_io:
2330  case Hexagon::L4_add_memopb_io:
2331  case Hexagon::L4_sub_memopb_io:
2332  case Hexagon::L4_and_memopb_io:
2333  case Hexagon::L4_or_memopb_io:
2334  case Hexagon::L4_ior_memopb_io:
2335  case Hexagon::L4_ior_memoph_io:
2336  case Hexagon::L4_ior_memopw_io:
2337  case Hexagon::L4_iand_memopb_io:
2338  case Hexagon::L4_iand_memoph_io:
2339  case Hexagon::L4_iand_memopw_io:
2340  return true;
2341  }
2342  return false;
2343 }
2344 
2346  const uint64_t F = MI.getDesc().TSFlags;
2348 }
2349 
2350 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2351  const uint64_t F = get(Opcode).TSFlags;
2353 }
2354 
2356  return isNewValueJump(MI) || isNewValueStore(MI);
2357 }
2358 
2360  return isNewValue(MI) && MI.isBranch();
2361 }
2362 
2363 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2364  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2365 }
2366 
2368  const uint64_t F = MI.getDesc().TSFlags;
2370 }
2371 
2372 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2373  const uint64_t F = get(Opcode).TSFlags;
2375 }
2376 
2377 // Returns true if a particular operand is extendable for an instruction.
2379  unsigned OperandNum) const {
2380  const uint64_t F = MI.getDesc().TSFlags;
2382  == OperandNum;
2383 }
2384 
2386  const uint64_t F = MI.getDesc().TSFlags;
2387  assert(isPredicated(MI));
2389 }
2390 
2391 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2392  const uint64_t F = get(Opcode).TSFlags;
2393  assert(isPredicated(Opcode));
2395 }
2396 
2398  const uint64_t F = MI.getDesc().TSFlags;
2399  return !((F >> HexagonII::PredicatedFalsePos) &
2401 }
2402 
2403 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2404  const uint64_t F = get(Opcode).TSFlags;
2405  // Make sure that the instruction is predicated.
2407  return !((F >> HexagonII::PredicatedFalsePos) &
2409 }
2410 
2411 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2412  const uint64_t F = get(Opcode).TSFlags;
2414 }
2415 
2416 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2417  const uint64_t F = get(Opcode).TSFlags;
2419 }
2420 
2421 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2422  const uint64_t F = get(Opcode).TSFlags;
2423  assert(get(Opcode).isBranch() &&
2424  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2425  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2426 }
2427 
2429  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2430  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2431  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2432  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2433 }
2434 
2436  switch (MI.getOpcode()) {
2437  // Byte
2438  case Hexagon::L2_loadrb_io:
2439  case Hexagon::L4_loadrb_ur:
2440  case Hexagon::L4_loadrb_ap:
2441  case Hexagon::L2_loadrb_pr:
2442  case Hexagon::L2_loadrb_pbr:
2443  case Hexagon::L2_loadrb_pi:
2444  case Hexagon::L2_loadrb_pci:
2445  case Hexagon::L2_loadrb_pcr:
2446  case Hexagon::L2_loadbsw2_io:
2447  case Hexagon::L4_loadbsw2_ur:
2448  case Hexagon::L4_loadbsw2_ap:
2449  case Hexagon::L2_loadbsw2_pr:
2450  case Hexagon::L2_loadbsw2_pbr:
2451  case Hexagon::L2_loadbsw2_pi:
2452  case Hexagon::L2_loadbsw2_pci:
2453  case Hexagon::L2_loadbsw2_pcr:
2454  case Hexagon::L2_loadbsw4_io:
2455  case Hexagon::L4_loadbsw4_ur:
2456  case Hexagon::L4_loadbsw4_ap:
2457  case Hexagon::L2_loadbsw4_pr:
2458  case Hexagon::L2_loadbsw4_pbr:
2459  case Hexagon::L2_loadbsw4_pi:
2460  case Hexagon::L2_loadbsw4_pci:
2461  case Hexagon::L2_loadbsw4_pcr:
2462  case Hexagon::L4_loadrb_rr:
2463  case Hexagon::L2_ploadrbt_io:
2464  case Hexagon::L2_ploadrbt_pi:
2465  case Hexagon::L2_ploadrbf_io:
2466  case Hexagon::L2_ploadrbf_pi:
2467  case Hexagon::L2_ploadrbtnew_io:
2468  case Hexagon::L2_ploadrbfnew_io:
2469  case Hexagon::L4_ploadrbt_rr:
2470  case Hexagon::L4_ploadrbf_rr:
2471  case Hexagon::L4_ploadrbtnew_rr:
2472  case Hexagon::L4_ploadrbfnew_rr:
2473  case Hexagon::L2_ploadrbtnew_pi:
2474  case Hexagon::L2_ploadrbfnew_pi:
2475  case Hexagon::L4_ploadrbt_abs:
2476  case Hexagon::L4_ploadrbf_abs:
2477  case Hexagon::L4_ploadrbtnew_abs:
2478  case Hexagon::L4_ploadrbfnew_abs:
2479  case Hexagon::L2_loadrbgp:
2480  // Half
2481  case Hexagon::L2_loadrh_io:
2482  case Hexagon::L4_loadrh_ur:
2483  case Hexagon::L4_loadrh_ap:
2484  case Hexagon::L2_loadrh_pr:
2485  case Hexagon::L2_loadrh_pbr:
2486  case Hexagon::L2_loadrh_pi:
2487  case Hexagon::L2_loadrh_pci:
2488  case Hexagon::L2_loadrh_pcr:
2489  case Hexagon::L4_loadrh_rr:
2490  case Hexagon::L2_ploadrht_io:
2491  case Hexagon::L2_ploadrht_pi:
2492  case Hexagon::L2_ploadrhf_io:
2493  case Hexagon::L2_ploadrhf_pi:
2494  case Hexagon::L2_ploadrhtnew_io:
2495  case Hexagon::L2_ploadrhfnew_io:
2496  case Hexagon::L4_ploadrht_rr:
2497  case Hexagon::L4_ploadrhf_rr:
2498  case Hexagon::L4_ploadrhtnew_rr:
2499  case Hexagon::L4_ploadrhfnew_rr:
2500  case Hexagon::L2_ploadrhtnew_pi:
2501  case Hexagon::L2_ploadrhfnew_pi:
2502  case Hexagon::L4_ploadrht_abs:
2503  case Hexagon::L4_ploadrhf_abs:
2504  case Hexagon::L4_ploadrhtnew_abs:
2505  case Hexagon::L4_ploadrhfnew_abs:
2506  case Hexagon::L2_loadrhgp:
2507  return true;
2508  default:
2509  return false;
2510  }
2511 }
2512 
2514  const uint64_t F = MI.getDesc().TSFlags;
2515  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2516 }
2517 
2519  switch (MI.getOpcode()) {
2520  case Hexagon::STriw_pred:
2521  case Hexagon::LDriw_pred:
2522  return true;
2523  default:
2524  return false;
2525  }
2526 }
2527 
2529  if (!MI.isBranch())
2530  return false;
2531 
2532  for (auto &Op : MI.operands())
2533  if (Op.isGlobal() || Op.isSymbol())
2534  return true;
2535  return false;
2536 }
2537 
2538 // Returns true when SU has a timing class TC1.
2540  unsigned SchedClass = MI.getDesc().getSchedClass();
2541  return is_TC1(SchedClass);
2542 }
2543 
2545  unsigned SchedClass = MI.getDesc().getSchedClass();
2546  return is_TC2(SchedClass);
2547 }
2548 
2550  unsigned SchedClass = MI.getDesc().getSchedClass();
2551  return is_TC2early(SchedClass);
2552 }
2553 
2555  unsigned SchedClass = MI.getDesc().getSchedClass();
2556  return is_TC4x(SchedClass);
2557 }
2558 
2559 // Schedule this ASAP.
2561  const MachineInstr &MI2) const {
2562  if (mayBeCurLoad(MI1)) {
2563  // if (result of SU is used in Next) return true;
2564  unsigned DstReg = MI1.getOperand(0).getReg();
2565  int N = MI2.getNumOperands();
2566  for (int I = 0; I < N; I++)
2567  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2568  return true;
2569  }
2570  if (mayBeNewStore(MI2))
2571  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2572  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2573  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2574  return true;
2575  return false;
2576 }
2577 
2579  const uint64_t V = getType(MI);
2581 }
2582 
2583 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2585  int Size = VT.getSizeInBits() / 8;
2586  if (Offset % Size != 0)
2587  return false;
2588  int Count = Offset / Size;
2589 
2590  switch (VT.getSimpleVT().SimpleTy) {
2591  // For scalars the auto-inc is s4
2592  case MVT::i8:
2593  case MVT::i16:
2594  case MVT::i32:
2595  case MVT::i64:
2596  case MVT::f32:
2597  case MVT::f64:
2598  case MVT::v2i16:
2599  case MVT::v2i32:
2600  case MVT::v4i8:
2601  case MVT::v4i16:
2602  case MVT::v8i8:
2603  return isInt<4>(Count);
2604  // For HVX vectors the auto-inc is s3
2605  case MVT::v64i8:
2606  case MVT::v32i16:
2607  case MVT::v16i32:
2608  case MVT::v8i64:
2609  case MVT::v128i8:
2610  case MVT::v64i16:
2611  case MVT::v32i32:
2612  case MVT::v16i64:
2613  return isInt<3>(Count);
2614  default:
2615  break;
2616  }
2617 
2618  llvm_unreachable("Not an valid type!");
2619 }
2620 
2621 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2622  const TargetRegisterInfo *TRI, bool Extend) const {
2623  // This function is to check whether the "Offset" is in the correct range of
2624  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2625  // inserted to calculate the final address. Due to this reason, the function
2626  // assumes that the "Offset" has correct alignment.
2627  // We used to assert if the offset was not properly aligned, however,
2628  // there are cases where a misaligned pointer recast can cause this
2629  // problem, and we need to allow for it. The front end warns of such
2630  // misaligns with respect to load size.
2631  switch (Opcode) {
2632  case Hexagon::PS_vstorerq_ai:
2633  case Hexagon::PS_vstorerw_ai:
2634  case Hexagon::PS_vstorerw_nt_ai:
2635  case Hexagon::PS_vloadrq_ai:
2636  case Hexagon::PS_vloadrw_ai:
2637  case Hexagon::PS_vloadrw_nt_ai:
2638  case Hexagon::V6_vL32b_ai:
2639  case Hexagon::V6_vS32b_ai:
2640  case Hexagon::V6_vL32b_nt_ai:
2641  case Hexagon::V6_vS32b_nt_ai:
2642  case Hexagon::V6_vL32Ub_ai:
2643  case Hexagon::V6_vS32Ub_ai: {
2644  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2645  assert(isPowerOf2_32(VectorSize));
2646  if (Offset & (VectorSize-1))
2647  return false;
2648  return isInt<4>(Offset >> Log2_32(VectorSize));
2649  }
2650 
2651  case Hexagon::J2_loop0i:
2652  case Hexagon::J2_loop1i:
2653  return isUInt<10>(Offset);
2654 
2655  case Hexagon::S4_storeirb_io:
2656  case Hexagon::S4_storeirbt_io:
2657  case Hexagon::S4_storeirbf_io:
2658  return isUInt<6>(Offset);
2659 
2660  case Hexagon::S4_storeirh_io:
2661  case Hexagon::S4_storeirht_io:
2662  case Hexagon::S4_storeirhf_io:
2663  return isShiftedUInt<6,1>(Offset);
2664 
2665  case Hexagon::S4_storeiri_io:
2666  case Hexagon::S4_storeirit_io:
2667  case Hexagon::S4_storeirif_io:
2668  return isShiftedUInt<6,2>(Offset);
2669  }
2670 
2671  if (Extend)
2672  return true;
2673 
2674  switch (Opcode) {
2675  case Hexagon::L2_loadri_io:
2676  case Hexagon::S2_storeri_io:
2677  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2678  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2679 
2680  case Hexagon::L2_loadrd_io:
2681  case Hexagon::S2_storerd_io:
2682  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2683  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2684 
2685  case Hexagon::L2_loadrh_io:
2686  case Hexagon::L2_loadruh_io:
2687  case Hexagon::S2_storerh_io:
2688  case Hexagon::S2_storerf_io:
2689  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2690  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2691 
2692  case Hexagon::L2_loadrb_io:
2693  case Hexagon::L2_loadrub_io:
2694  case Hexagon::S2_storerb_io:
2695  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2696  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2697 
2698  case Hexagon::A2_addi:
2699  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2700  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2701 
2702  case Hexagon::L4_iadd_memopw_io:
2703  case Hexagon::L4_isub_memopw_io:
2704  case Hexagon::L4_add_memopw_io:
2705  case Hexagon::L4_sub_memopw_io:
2706  case Hexagon::L4_and_memopw_io:
2707  case Hexagon::L4_or_memopw_io:
2708  return (0 <= Offset && Offset <= 255);
2709 
2710  case Hexagon::L4_iadd_memoph_io:
2711  case Hexagon::L4_isub_memoph_io:
2712  case Hexagon::L4_add_memoph_io:
2713  case Hexagon::L4_sub_memoph_io:
2714  case Hexagon::L4_and_memoph_io:
2715  case Hexagon::L4_or_memoph_io:
2716  return (0 <= Offset && Offset <= 127);
2717 
2718  case Hexagon::L4_iadd_memopb_io:
2719  case Hexagon::L4_isub_memopb_io:
2720  case Hexagon::L4_add_memopb_io:
2721  case Hexagon::L4_sub_memopb_io:
2722  case Hexagon::L4_and_memopb_io:
2723  case Hexagon::L4_or_memopb_io:
2724  return (0 <= Offset && Offset <= 63);
2725 
2726  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2727  // any size. Later pass knows how to handle it.
2728  case Hexagon::STriw_pred:
2729  case Hexagon::LDriw_pred:
2730  case Hexagon::STriw_ctr:
2731  case Hexagon::LDriw_ctr:
2732  return true;
2733 
2734  case Hexagon::PS_fi:
2735  case Hexagon::PS_fia:
2736  case Hexagon::INLINEASM:
2737  return true;
2738 
2739  case Hexagon::L2_ploadrbt_io:
2740  case Hexagon::L2_ploadrbf_io:
2741  case Hexagon::L2_ploadrubt_io:
2742  case Hexagon::L2_ploadrubf_io:
2743  case Hexagon::S2_pstorerbt_io:
2744  case Hexagon::S2_pstorerbf_io:
2745  return isUInt<6>(Offset);
2746 
2747  case Hexagon::L2_ploadrht_io:
2748  case Hexagon::L2_ploadrhf_io:
2749  case Hexagon::L2_ploadruht_io:
2750  case Hexagon::L2_ploadruhf_io:
2751  case Hexagon::S2_pstorerht_io:
2752  case Hexagon::S2_pstorerhf_io:
2753  return isShiftedUInt<6,1>(Offset);
2754 
2755  case Hexagon::L2_ploadrit_io:
2756  case Hexagon::L2_ploadrif_io:
2757  case Hexagon::S2_pstorerit_io:
2758  case Hexagon::S2_pstorerif_io:
2759  return isShiftedUInt<6,2>(Offset);
2760 
2761  case Hexagon::L2_ploadrdt_io:
2762  case Hexagon::L2_ploadrdf_io:
2763  case Hexagon::S2_pstorerdt_io:
2764  case Hexagon::S2_pstorerdf_io:
2765  return isShiftedUInt<6,3>(Offset);
2766  } // switch
2767 
2768  llvm_unreachable("No offset range is defined for this opcode. "
2769  "Please define it in the above switch statement!");
2770 }
2771 
2773  return isHVXVec(MI) && isAccumulator(MI);
2774 }
2775 
2777  const uint64_t F = get(MI.getOpcode()).TSFlags;
2778  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2779  return
2780  V == HexagonII::TypeCVI_VA ||
2782 }
2783 
2785  const MachineInstr &ConsMI) const {
2786  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2787  return true;
2788 
2789  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2790  return true;
2791 
2792  if (mayBeNewStore(ConsMI))
2793  return true;
2794 
2795  return false;
2796 }
2797 
2799  switch (MI.getOpcode()) {
2800  // Byte
2801  case Hexagon::L2_loadrub_io:
2802  case Hexagon::L4_loadrub_ur:
2803  case Hexagon::L4_loadrub_ap:
2804  case Hexagon::L2_loadrub_pr:
2805  case Hexagon::L2_loadrub_pbr:
2806  case Hexagon::L2_loadrub_pi:
2807  case Hexagon::L2_loadrub_pci:
2808  case Hexagon::L2_loadrub_pcr:
2809  case Hexagon::L2_loadbzw2_io:
2810  case Hexagon::L4_loadbzw2_ur:
2811  case Hexagon::L4_loadbzw2_ap:
2812  case Hexagon::L2_loadbzw2_pr:
2813  case Hexagon::L2_loadbzw2_pbr:
2814  case Hexagon::L2_loadbzw2_pi:
2815  case Hexagon::L2_loadbzw2_pci:
2816  case Hexagon::L2_loadbzw2_pcr:
2817  case Hexagon::L2_loadbzw4_io:
2818  case Hexagon::L4_loadbzw4_ur:
2819  case Hexagon::L4_loadbzw4_ap:
2820  case Hexagon::L2_loadbzw4_pr:
2821  case Hexagon::L2_loadbzw4_pbr:
2822  case Hexagon::L2_loadbzw4_pi:
2823  case Hexagon::L2_loadbzw4_pci:
2824  case Hexagon::L2_loadbzw4_pcr:
2825  case Hexagon::L4_loadrub_rr:
2826  case Hexagon::L2_ploadrubt_io:
2827  case Hexagon::L2_ploadrubt_pi:
2828  case Hexagon::L2_ploadrubf_io:
2829  case Hexagon::L2_ploadrubf_pi:
2830  case Hexagon::L2_ploadrubtnew_io:
2831  case Hexagon::L2_ploadrubfnew_io:
2832  case Hexagon::L4_ploadrubt_rr:
2833  case Hexagon::L4_ploadrubf_rr:
2834  case Hexagon::L4_ploadrubtnew_rr:
2835  case Hexagon::L4_ploadrubfnew_rr:
2836  case Hexagon::L2_ploadrubtnew_pi:
2837  case Hexagon::L2_ploadrubfnew_pi:
2838  case Hexagon::L4_ploadrubt_abs:
2839  case Hexagon::L4_ploadrubf_abs:
2840  case Hexagon::L4_ploadrubtnew_abs:
2841  case Hexagon::L4_ploadrubfnew_abs:
2842  case Hexagon::L2_loadrubgp:
2843  // Half
2844  case Hexagon::L2_loadruh_io:
2845  case Hexagon::L4_loadruh_ur:
2846  case Hexagon::L4_loadruh_ap:
2847  case Hexagon::L2_loadruh_pr:
2848  case Hexagon::L2_loadruh_pbr:
2849  case Hexagon::L2_loadruh_pi:
2850  case Hexagon::L2_loadruh_pci:
2851  case Hexagon::L2_loadruh_pcr:
2852  case Hexagon::L4_loadruh_rr:
2853  case Hexagon::L2_ploadruht_io:
2854  case Hexagon::L2_ploadruht_pi:
2855  case Hexagon::L2_ploadruhf_io:
2856  case Hexagon::L2_ploadruhf_pi:
2857  case Hexagon::L2_ploadruhtnew_io:
2858  case Hexagon::L2_ploadruhfnew_io:
2859  case Hexagon::L4_ploadruht_rr:
2860  case Hexagon::L4_ploadruhf_rr:
2861  case Hexagon::L4_ploadruhtnew_rr:
2862  case Hexagon::L4_ploadruhfnew_rr:
2863  case Hexagon::L2_ploadruhtnew_pi:
2864  case Hexagon::L2_ploadruhfnew_pi:
2865  case Hexagon::L4_ploadruht_abs:
2866  case Hexagon::L4_ploadruhf_abs:
2867  case Hexagon::L4_ploadruhtnew_abs:
2868  case Hexagon::L4_ploadruhfnew_abs:
2869  case Hexagon::L2_loadruhgp:
2870  return true;
2871  default:
2872  return false;
2873  }
2874 }
2875 
2876 // Add latency to instruction.
2878  const MachineInstr &MI2) const {
2879  if (isHVXVec(MI1) && isHVXVec(MI2))
2880  if (!isVecUsableNextPacket(MI1, MI2))
2881  return true;
2882  return false;
2883 }
2884 
2885 /// Get the base register and byte offset of a load/store instr.
2887  unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2888  const {
2889  unsigned AccessSize = 0;
2890  int OffsetVal = 0;
2891  BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2892  Offset = OffsetVal;
2893  return BaseReg != 0;
2894 }
2895 
2896 /// Can these instructions execute at the same time in a bundle.
2898  const MachineInstr &Second) const {
2899  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2900  const MachineOperand &Op = Second.getOperand(0);
2901  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2902  return true;
2903  }
2904  if (DisableNVSchedule)
2905  return false;
2906  if (mayBeNewStore(Second)) {
2907  // Make sure the definition of the first instruction is the value being
2908  // stored.
2909  const MachineOperand &Stored =
2910  Second.getOperand(Second.getNumOperands() - 1);
2911  if (!Stored.isReg())
2912  return false;
2913  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2914  const MachineOperand &Op = First.getOperand(i);
2915  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2916  return true;
2917  }
2918  }
2919  return false;
2920 }
2921 
2923  unsigned Opc = CallMI.getOpcode();
2924  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2925 }
2926 
2928  for (auto &I : *B)
2929  if (I.isEHLabel())
2930  return true;
2931  return false;
2932 }
2933 
2934 // Returns true if an instruction can be converted into a non-extended
2935 // equivalent instruction.
2937  short NonExtOpcode;
2938  // Check if the instruction has a register form that uses register in place
2939  // of the extended operand, if so return that as the non-extended form.
2940  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2941  return true;
2942 
2943  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2944  // Check addressing mode and retrieve non-ext equivalent instruction.
2945 
2946  switch (getAddrMode(MI)) {
2947  case HexagonII::Absolute:
2948  // Load/store with absolute addressing mode can be converted into
2949  // base+offset mode.
2950  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2951  break;
2953  // Load/store with base+offset addressing mode can be converted into
2954  // base+register offset addressing mode. However left shift operand should
2955  // be set to 0.
2956  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
2957  break;
2959  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
2960  break;
2961  default:
2962  return false;
2963  }
2964  if (NonExtOpcode < 0)
2965  return false;
2966  return true;
2967  }
2968  return false;
2969 }
2970 
2972  return Hexagon::getRealHWInstr(MI.getOpcode(),
2973  Hexagon::InstrType_Pseudo) >= 0;
2974 }
2975 
2977  const {
2979  while (I != E) {
2980  if (I->isBarrier())
2981  return true;
2982  ++I;
2983  }
2984  return false;
2985 }
2986 
2987 // Returns true, if a LD insn can be promoted to a cur load.
2989  const uint64_t F = MI.getDesc().TSFlags;
2991  Subtarget.hasV60Ops();
2992 }
2993 
2994 // Returns true, if a ST insn can be promoted to a new-value store.
2996  if (MI.mayStore() && !Subtarget.useNewValueStores())
2997  return false;
2998 
2999  const uint64_t F = MI.getDesc().TSFlags;
3001 }
3002 
3004  const MachineInstr &ConsMI) const {
3005  // There is no stall when ProdMI is not a V60 vector.
3006  if (!isHVXVec(ProdMI))
3007  return false;
3008 
3009  // There is no stall when ProdMI and ConsMI are not dependent.
3010  if (!isDependent(ProdMI, ConsMI))
3011  return false;
3012 
3013  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3014  // are scheduled in consecutive packets.
3015  if (isVecUsableNextPacket(ProdMI, ConsMI))
3016  return false;
3017 
3018  return true;
3019 }
3020 
3023  // There is no stall when I is not a V60 vector.
3024  if (!isHVXVec(MI))
3025  return false;
3026 
3028  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3029 
3030  if (!MII->isBundle())
3031  return producesStall(*MII, MI);
3032 
3033  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3034  const MachineInstr &J = *MII;
3035  if (producesStall(J, MI))
3036  return true;
3037  }
3038  return false;
3039 }
3040 
3042  unsigned PredReg) const {
3043  for (const MachineOperand &MO : MI.operands()) {
3044  // Predicate register must be explicitly defined.
3045  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3046  return false;
3047  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3048  return false;
3049  }
3050 
3051  // Instruction that produce late predicate cannot be used as sources of
3052  // dot-new.
3053  switch (MI.getOpcode()) {
3054  case Hexagon::A4_addp_c:
3055  case Hexagon::A4_subp_c:
3056  case Hexagon::A4_tlbmatch:
3057  case Hexagon::A5_ACS:
3058  case Hexagon::F2_sfinvsqrta:
3059  case Hexagon::F2_sfrecipa:
3060  case Hexagon::J2_endloop0:
3061  case Hexagon::J2_endloop01:
3062  case Hexagon::J2_ploop1si:
3063  case Hexagon::J2_ploop1sr:
3064  case Hexagon::J2_ploop2si:
3065  case Hexagon::J2_ploop2sr:
3066  case Hexagon::J2_ploop3si:
3067  case Hexagon::J2_ploop3sr:
3068  case Hexagon::S2_cabacdecbin:
3069  case Hexagon::S2_storew_locked:
3070  case Hexagon::S4_stored_locked:
3071  return false;
3072  }
3073  return true;
3074 }
3075 
3076 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3077  return Opcode == Hexagon::J2_jumpt ||
3078  Opcode == Hexagon::J2_jumptpt ||
3079  Opcode == Hexagon::J2_jumpf ||
3080  Opcode == Hexagon::J2_jumpfpt ||
3081  Opcode == Hexagon::J2_jumptnew ||
3082  Opcode == Hexagon::J2_jumpfnew ||
3083  Opcode == Hexagon::J2_jumptnewpt ||
3084  Opcode == Hexagon::J2_jumpfnewpt;
3085 }
3086 
3088  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3089  return false;
3090  return !isPredicatedTrue(Cond[0].getImm());
3091 }
3092 
3094  const uint64_t F = MI.getDesc().TSFlags;
3096 }
3097 
3098 // Returns the base register in a memory access (load/store). The offset is
3099 // returned in Offset and the access size is returned in AccessSize.
3100 // If the base register has a subregister or the offset field does not contain
3101 // an immediate value, return 0.
3103  int &Offset, unsigned &AccessSize) const {
3104  // Return if it is not a base+offset type instruction or a MemOp.
3107  !isMemOp(MI) && !isPostIncrement(MI))
3108  return 0;
3109 
3110  AccessSize = getMemAccessSize(MI);
3111 
3112  unsigned BasePos = 0, OffsetPos = 0;
3113  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3114  return 0;
3115 
3116  // Post increment updates its EA after the mem access,
3117  // so we need to treat its offset as zero.
3118  if (isPostIncrement(MI)) {
3119  Offset = 0;
3120  } else {
3121  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3122  if (!OffsetOp.isImm())
3123  return 0;
3124  Offset = OffsetOp.getImm();
3125  }
3126 
3127  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3128  if (BaseOp.getSubReg() != 0)
3129  return 0;
3130  return BaseOp.getReg();
3131 }
3132 
3133 /// Return the position of the base and offset operands for this instruction.
3135  unsigned &BasePos, unsigned &OffsetPos) const {
3136  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3137  return false;
3138 
3139  // Deal with memops first.
3140  if (isMemOp(MI)) {
3141  BasePos = 0;
3142  OffsetPos = 1;
3143  } else if (MI.mayStore()) {
3144  BasePos = 0;
3145  OffsetPos = 1;
3146  } else if (MI.mayLoad()) {
3147  BasePos = 1;
3148  OffsetPos = 2;
3149  } else
3150  return false;
3151 
3152  if (isPredicated(MI)) {
3153  BasePos++;
3154  OffsetPos++;
3155  }
3156  if (isPostIncrement(MI)) {
3157  BasePos++;
3158  OffsetPos++;
3159  }
3160 
3161  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3162  return false;
3163 
3164  return true;
3165 }
3166 
3167 // Inserts branching instructions in reverse order of their occurrence.
3168 // e.g. jump_t t1 (i1)
3169 // jump t2 (i2)
3170 // Jumpers = {i2, i1}
3172  MachineBasicBlock& MBB) const {
3174  // If the block has no terminators, it just falls into the block after it.
3176  if (I == MBB.instr_begin())
3177  return Jumpers;
3178 
3179  // A basic block may looks like this:
3180  //
3181  // [ insn
3182  // EH_LABEL
3183  // insn
3184  // insn
3185  // insn
3186  // EH_LABEL
3187  // insn ]
3188  //
3189  // It has two succs but does not have a terminator
3190  // Don't know how to handle it.
3191  do {
3192  --I;
3193  if (I->isEHLabel())
3194  return Jumpers;
3195  } while (I != MBB.instr_begin());
3196 
3197  I = MBB.instr_end();
3198  --I;
3199 
3200  while (I->isDebugInstr()) {
3201  if (I == MBB.instr_begin())
3202  return Jumpers;
3203  --I;
3204  }
3205  if (!isUnpredicatedTerminator(*I))
3206  return Jumpers;
3207 
3208  // Get the last instruction in the block.
3209  MachineInstr *LastInst = &*I;
3210  Jumpers.push_back(LastInst);
3211  MachineInstr *SecondLastInst = nullptr;
3212  // Find one more terminator if present.
3213  do {
3214  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3215  if (!SecondLastInst) {
3216  SecondLastInst = &*I;
3217  Jumpers.push_back(SecondLastInst);
3218  } else // This is a third branch.
3219  return Jumpers;
3220  }
3221  if (I == MBB.instr_begin())
3222  break;
3223  --I;
3224  } while (true);
3225  return Jumpers;
3226 }
3227 
3228 // Returns Operand Index for the constant extended instruction.
3230  const uint64_t F = MI.getDesc().TSFlags;
3232 }
3233 
3234 // See if instruction could potentially be a duplex candidate.
3235 // If so, return its group. Zero otherwise.
3237  const MachineInstr &MI) const {
3238  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3239 
3240  switch (MI.getOpcode()) {
3241  default:
3242  return HexagonII::HCG_None;
3243  //
3244  // Compound pairs.
3245  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3246  // "Rd16=#U6 ; jump #r9:2"
3247  // "Rd16=Rs16 ; jump #r9:2"
3248  //
3249  case Hexagon::C2_cmpeq:
3250  case Hexagon::C2_cmpgt:
3251  case Hexagon::C2_cmpgtu:
3252  DstReg = MI.getOperand(0).getReg();
3253  Src1Reg = MI.getOperand(1).getReg();
3254  Src2Reg = MI.getOperand(2).getReg();
3255  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3256  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3257  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3258  return HexagonII::HCG_A;
3259  break;
3260  case Hexagon::C2_cmpeqi:
3261  case Hexagon::C2_cmpgti:
3262  case Hexagon::C2_cmpgtui:
3263  // P0 = cmp.eq(Rs,#u2)
3264  DstReg = MI.getOperand(0).getReg();
3265  SrcReg = MI.getOperand(1).getReg();
3266  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3267  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3268  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3269  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3270  (MI.getOperand(2).getImm() == -1)))
3271  return HexagonII::HCG_A;
3272  break;
3273  case Hexagon::A2_tfr:
3274  // Rd = Rs
3275  DstReg = MI.getOperand(0).getReg();
3276  SrcReg = MI.getOperand(1).getReg();
3277  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3278  return HexagonII::HCG_A;
3279  break;
3280  case Hexagon::A2_tfrsi:
3281  // Rd = #u6
3282  // Do not test for #u6 size since the const is getting extended
3283  // regardless and compound could be formed.
3284  DstReg = MI.getOperand(0).getReg();
3285  if (isIntRegForSubInst(DstReg))
3286  return HexagonII::HCG_A;
3287  break;
3288  case Hexagon::S2_tstbit_i:
3289  DstReg = MI.getOperand(0).getReg();
3290  Src1Reg = MI.getOperand(1).getReg();
3291  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3292  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3293  MI.getOperand(2).isImm() &&
3294  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3295  return HexagonII::HCG_A;
3296  break;
3297  // The fact that .new form is used pretty much guarantees
3298  // that predicate register will match. Nevertheless,
3299  // there could be some false positives without additional
3300  // checking.
3301  case Hexagon::J2_jumptnew:
3302  case Hexagon::J2_jumpfnew:
3303  case Hexagon::J2_jumptnewpt:
3304  case Hexagon::J2_jumpfnewpt:
3305  Src1Reg = MI.getOperand(0).getReg();
3306  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3307  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3308  return HexagonII::HCG_B;
3309  break;
3310  // Transfer and jump:
3311  // Rd=#U6 ; jump #r9:2
3312  // Rd=Rs ; jump #r9:2
3313  // Do not test for jump range here.
3314  case Hexagon::J2_jump:
3315  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3316  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3317  return HexagonII::HCG_C;
3318  }
3319 
3320  return HexagonII::HCG_None;
3321 }
3322 
3323 // Returns -1 when there is no opcode found.
3325  const MachineInstr &GB) const {
3328  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3329  (GB.getOpcode() != Hexagon::J2_jumptnew))
3330  return -1u;
3331  unsigned DestReg = GA.getOperand(0).getReg();
3332  if (!GB.readsRegister(DestReg))
3333  return -1u;
3334  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3335  return -1u;
3336  // The value compared against must be either u5 or -1.
3337  const MachineOperand &CmpOp = GA.getOperand(2);
3338  if (!CmpOp.isImm())
3339  return -1u;
3340  int V = CmpOp.getImm();
3341  if (V == -1)
3342  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3343  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3344  if (!isUInt<5>(V))
3345  return -1u;
3346  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3347  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3348 }
3349 
3350 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3351  enum Hexagon::PredSense inPredSense;
3352  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3353  Hexagon::PredSense_true;
3354  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3355  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3356  return CondOpcode;
3357 
3358  llvm_unreachable("Unexpected predicable instruction");
3359 }
3360 
3361 // Return the cur value instruction for a given store.
3363  switch (MI.getOpcode()) {
3364  default: llvm_unreachable("Unknown .cur type");
3365  case Hexagon::V6_vL32b_pi:
3366  return Hexagon::V6_vL32b_cur_pi;
3367  case Hexagon::V6_vL32b_ai:
3368  return Hexagon::V6_vL32b_cur_ai;
3369  case Hexagon::V6_vL32b_nt_pi:
3370  return Hexagon::V6_vL32b_nt_cur_pi;
3371  case Hexagon::V6_vL32b_nt_ai:
3372  return Hexagon::V6_vL32b_nt_cur_ai;
3373  }
3374  return 0;
3375 }
3376 
3377 // Return the regular version of the .cur instruction.
3379  switch (MI.getOpcode()) {
3380  default: llvm_unreachable("Unknown .cur type");
3381  case Hexagon::V6_vL32b_cur_pi:
3382  return Hexagon::V6_vL32b_pi;
3383  case Hexagon::V6_vL32b_cur_ai:
3384  return Hexagon::V6_vL32b_ai;
3385  case Hexagon::V6_vL32b_nt_cur_pi:
3386  return Hexagon::V6_vL32b_nt_pi;
3387  case Hexagon::V6_vL32b_nt_cur_ai:
3388  return Hexagon::V6_vL32b_nt_ai;
3389  }
3390  return 0;
3391 }
3392 
3393 // The diagram below shows the steps involved in the conversion of a predicated
3394 // store instruction to its .new predicated new-value form.
3395 //
3396 // Note: It doesn't include conditional new-value stores as they can't be
3397 // converted to .new predicate.
3398 //
3399 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3400 // ^ ^
3401 // / \ (not OK. it will cause new-value store to be
3402 // / X conditional on p0.new while R2 producer is
3403 // / \ on p0)
3404 // / \.
3405 // p.new store p.old NV store
3406 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3407 // ^ ^
3408 // \ /
3409 // \ /
3410 // \ /
3411 // p.old store
3412 // [if (p0)memw(R0+#0)=R2]
3413 //
3414 // The following set of instructions further explains the scenario where
3415 // conditional new-value store becomes invalid when promoted to .new predicate
3416 // form.
3417 //
3418 // { 1) if (p0) r0 = add(r1, r2)
3419 // 2) p0 = cmp.eq(r3, #0) }
3420 //
3421 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3422 // the first two instructions because in instr 1, r0 is conditional on old value
3423 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3424 // is not valid for new-value stores.
3425 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3426 // from the "Conditional Store" list. Because a predicated new value store
3427 // would NOT be promoted to a double dot new store. See diagram below:
3428 // This function returns yes for those stores that are predicated but not
3429 // yet promoted to predicate dot new instructions.
3430 //
3431 // +---------------------+
3432 // /-----| if (p0) memw(..)=r0 |---------\~
3433 // || +---------------------+ ||
3434 // promote || /\ /\ || promote
3435 // || /||\ /||\ ||
3436 // \||/ demote || \||/
3437 // \/ || || \/
3438 // +-------------------------+ || +-------------------------+
3439 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3440 // +-------------------------+ || +-------------------------+
3441 // || || ||
3442 // || demote \||/
3443 // promote || \/ NOT possible
3444 // || || /\~
3445 // \||/ || /||\~
3446 // \/ || ||
3447 // +-----------------------------+
3448 // | if (p0.new) memw(..)=r0.new |
3449 // +-----------------------------+
3450 // Double Dot New Store
3451 //
3452 // Returns the most basic instruction for the .new predicated instructions and
3453 // new-value stores.
3454 // For example, all of the following instructions will be converted back to the
3455 // same instruction:
3456 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3457 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3458 // 3) if (p0.new) memw(R0+#0) = R1 --->
3459 //
3460 // To understand the translation of instruction 1 to its original form, consider
3461 // a packet with 3 instructions.
3462 // { p0 = cmp.eq(R0,R1)
3463 // if (p0.new) R2 = add(R3, R4)
3464 // R5 = add (R3, R1)
3465 // }
3466 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3467 //
3468 // This instruction can be part of the previous packet only if both p0 and R2
3469 // are promoted to .new values. This promotion happens in steps, first
3470 // predicate register is promoted to .new and in the next iteration R2 is
3471 // promoted. Therefore, in case of dependence check failure (due to R5) during
3472 // next iteration, it should be converted back to its most basic form.
3473 
3474 // Return the new value instruction for a given store.
3476  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3477  if (NVOpcode >= 0) // Valid new-value store instruction.
3478  return NVOpcode;
3479 
3480  switch (MI.getOpcode()) {
3481  default:
3482  report_fatal_error(std::string("Unknown .new type: ") +
3483  std::to_string(MI.getOpcode()));
3484  case Hexagon::S4_storerb_ur:
3485  return Hexagon::S4_storerbnew_ur;
3486 
3487  case Hexagon::S2_storerb_pci:
3488  return Hexagon::S2_storerb_pci;
3489 
3490  case Hexagon::S2_storeri_pci:
3491  return Hexagon::S2_storeri_pci;
3492 
3493  case Hexagon::S2_storerh_pci:
3494  return Hexagon::S2_storerh_pci;
3495 
3496  case Hexagon::S2_storerd_pci:
3497  return Hexagon::S2_storerd_pci;
3498 
3499  case Hexagon::S2_storerf_pci:
3500  return Hexagon::S2_storerf_pci;
3501 
3502  case Hexagon::V6_vS32b_ai:
3503  return Hexagon::V6_vS32b_new_ai;
3504 
3505  case Hexagon::V6_vS32b_pi:
3506  return Hexagon::V6_vS32b_new_pi;
3507  }
3508  return 0;
3509 }
3510 
3511 // Returns the opcode to use when converting MI, which is a conditional jump,
3512 // into a conditional instruction which uses the .new value of the predicate.
3513 // We also use branch probabilities to add a hint to the jump.
3514 // If MBPI is null, all edges will be treated as equally likely for the
3515 // purposes of establishing a predication hint.
3517  const MachineBranchProbabilityInfo *MBPI) const {
3518  // We assume that block can have at most two successors.
3519  const MachineBasicBlock *Src = MI.getParent();
3520  const MachineOperand &BrTarget = MI.getOperand(1);
3521  bool Taken = false;
3522  const BranchProbability OneHalf(1, 2);
3523 
3524  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3525  const MachineBasicBlock *Dst) {
3526  if (MBPI)
3527  return MBPI->getEdgeProbability(Src, Dst);
3528  return BranchProbability(1, Src->succ_size());
3529  };
3530 
3531  if (BrTarget.isMBB()) {
3532  const MachineBasicBlock *Dst = BrTarget.getMBB();
3533  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3534  } else {
3535  // The branch target is not a basic block (most likely a function).
3536  // Since BPI only gives probabilities for targets that are basic blocks,
3537  // try to identify another target of this branch (potentially a fall-
3538  // -through) and check the probability of that target.
3539  //
3540  // The only handled branch combinations are:
3541  // - one conditional branch,
3542  // - one conditional branch followed by one unconditional branch.
3543  // Otherwise, assume not-taken.
3545  const MachineBasicBlock &B = *MI.getParent();
3546  bool SawCond = false, Bad = false;
3547  for (const MachineInstr &I : B) {
3548  if (!I.isBranch())
3549  continue;
3550  if (I.isConditionalBranch()) {
3551  SawCond = true;
3552  if (&I != &MI) {
3553  Bad = true;
3554  break;
3555  }
3556  }
3557  if (I.isUnconditionalBranch() && !SawCond) {
3558  Bad = true;
3559  break;
3560  }
3561  }
3562  if (!Bad) {
3564  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3565  if (NextIt == B.instr_end()) {
3566  // If this branch is the last, look for the fall-through block.
3567  for (const MachineBasicBlock *SB : B.successors()) {
3568  if (!B.isLayoutSuccessor(SB))
3569  continue;
3570  Taken = getEdgeProbability(Src, SB) < OneHalf;
3571  break;
3572  }
3573  } else {
3574  assert(NextIt->isUnconditionalBranch());
3575  // Find the first MBB operand and assume it's the target.
3576  const MachineBasicBlock *BT = nullptr;
3577  for (const MachineOperand &Op : NextIt->operands()) {
3578  if (!Op.isMBB())
3579  continue;
3580  BT = Op.getMBB();
3581  break;
3582  }
3583  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3584  }
3585  } // if (!Bad)
3586  }
3587 
3588  // The Taken flag should be set to something reasonable by this point.
3589 
3590  switch (MI.getOpcode()) {
3591  case Hexagon::J2_jumpt:
3592  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3593  case Hexagon::J2_jumpf:
3594  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3595 
3596  default:
3597  llvm_unreachable("Unexpected jump instruction.");
3598  }
3599 }
3600 
3601 // Return .new predicate version for an instruction.
3603  const MachineBranchProbabilityInfo *MBPI) const {
3604  switch (MI.getOpcode()) {
3605  // Condtional Jumps
3606  case Hexagon::J2_jumpt:
3607  case Hexagon::J2_jumpf:
3608  return getDotNewPredJumpOp(MI, MBPI);
3609  }
3610 
3611  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3612  if (NewOpcode >= 0)
3613  return NewOpcode;
3614  return 0;
3615 }
3616 
3618  int NewOp = MI.getOpcode();
3619  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3620  NewOp = Hexagon::getPredOldOpcode(NewOp);
3621  // All Hexagon architectures have prediction bits on dot-new branches,
3622  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3623  // to pick the right opcode when converting back to dot-old.
3624  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3625  switch (NewOp) {
3626  case Hexagon::J2_jumptpt:
3627  NewOp = Hexagon::J2_jumpt;
3628  break;
3629  case Hexagon::J2_jumpfpt:
3630  NewOp = Hexagon::J2_jumpf;
3631  break;
3632  case Hexagon::J2_jumprtpt:
3633  NewOp = Hexagon::J2_jumprt;
3634  break;
3635  case Hexagon::J2_jumprfpt:
3636  NewOp = Hexagon::J2_jumprf;
3637  break;
3638  }
3639  }
3640  assert(NewOp >= 0 &&
3641  "Couldn't change predicate new instruction to its old form.");
3642  }
3643 
3644  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3645  NewOp = Hexagon::getNonNVStore(NewOp);
3646  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3647  }
3648 
3649  if (Subtarget.hasV60Ops())
3650  return NewOp;
3651 
3652  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3653  switch (NewOp) {
3654  case Hexagon::J2_jumpfpt:
3655  return Hexagon::J2_jumpf;
3656  case Hexagon::J2_jumptpt:
3657  return Hexagon::J2_jumpt;
3658  case Hexagon::J2_jumprfpt:
3659  return Hexagon::J2_jumprf;
3660  case Hexagon::J2_jumprtpt:
3661  return Hexagon::J2_jumprt;
3662  }
3663  return NewOp;
3664 }
3665 
3666 // See if instruction could potentially be a duplex candidate.
3667 // If so, return its group. Zero otherwise.
3669  const MachineInstr &MI) const {
3670  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3671  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3672 
3673  switch (MI.getOpcode()) {
3674  default:
3675  return HexagonII::HSIG_None;
3676  //
3677  // Group L1:
3678  //
3679  // Rd = memw(Rs+#u4:2)
3680  // Rd = memub(Rs+#u4:0)
3681  case Hexagon::L2_loadri_io:
3682  DstReg = MI.getOperand(0).getReg();
3683  SrcReg = MI.getOperand(1).getReg();
3684  // Special case this one from Group L2.
3685  // Rd = memw(r29+#u5:2)
3686  if (isIntRegForSubInst(DstReg)) {
3687  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3688  HRI.getStackRegister() == SrcReg &&
3689  MI.getOperand(2).isImm() &&
3690  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3691  return HexagonII::HSIG_L2;
3692  // Rd = memw(Rs+#u4:2)
3693  if (isIntRegForSubInst(SrcReg) &&
3694  (MI.getOperand(2).isImm() &&
3695  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3696  return HexagonII::HSIG_L1;
3697  }
3698  break;
3699  case Hexagon::L2_loadrub_io:
3700  // Rd = memub(Rs+#u4:0)
3701  DstReg = MI.getOperand(0).getReg();
3702  SrcReg = MI.getOperand(1).getReg();
3703  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3704  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3705  return HexagonII::HSIG_L1;
3706  break;
3707  //
3708  // Group L2:
3709  //
3710  // Rd = memh/memuh(Rs+#u3:1)
3711  // Rd = memb(Rs+#u3:0)
3712  // Rd = memw(r29+#u5:2) - Handled above.
3713  // Rdd = memd(r29+#u5:3)
3714  // deallocframe
3715  // [if ([!]p0[.new])] dealloc_return
3716  // [if ([!]p0[.new])] jumpr r31
3717  case Hexagon::L2_loadrh_io:
3718  case Hexagon::L2_loadruh_io:
3719  // Rd = memh/memuh(Rs+#u3:1)
3720  DstReg = MI.getOperand(0).getReg();
3721  SrcReg = MI.getOperand(1).getReg();
3722  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3723  MI.getOperand(2).isImm() &&
3724  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3725  return HexagonII::HSIG_L2;
3726  break;
3727  case Hexagon::L2_loadrb_io:
3728  // Rd = memb(Rs+#u3:0)
3729  DstReg = MI.getOperand(0).getReg();
3730  SrcReg = MI.getOperand(1).getReg();
3731  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3732  MI.getOperand(2).isImm() &&
3733  isUInt<3>(MI.getOperand(2).getImm()))
3734  return HexagonII::HSIG_L2;
3735  break;
3736  case Hexagon::L2_loadrd_io:
3737  // Rdd = memd(r29+#u5:3)
3738  DstReg = MI.getOperand(0).getReg();
3739  SrcReg = MI.getOperand(1).getReg();
3740  if (isDblRegForSubInst(DstReg, HRI) &&
3741  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3742  HRI.getStackRegister() == SrcReg &&
3743  MI.getOperand(2).isImm() &&
3744  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3745  return HexagonII::HSIG_L2;
3746  break;
3747  // dealloc_return is not documented in Hexagon Manual, but marked
3748  // with A_SUBINSN attribute in iset_v4classic.py.
3749  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3750  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3751  case Hexagon::L4_return:
3752  case Hexagon::L2_deallocframe:
3753  return HexagonII::HSIG_L2;
3754  case Hexagon::EH_RETURN_JMPR:
3755  case Hexagon::PS_jmpret:
3756  case Hexagon::SL2_jumpr31:
3757  // jumpr r31
3758  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3759  DstReg = MI.getOperand(0).getReg();
3760  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3761  return HexagonII::HSIG_L2;
3762  break;
3763  case Hexagon::PS_jmprett:
3764  case Hexagon::PS_jmpretf:
3765  case Hexagon::PS_jmprettnewpt:
3766  case Hexagon::PS_jmpretfnewpt:
3767  case Hexagon::PS_jmprettnew:
3768  case Hexagon::PS_jmpretfnew:
3769  case Hexagon::SL2_jumpr31_t:
3770  case Hexagon::SL2_jumpr31_f:
3771  case Hexagon::SL2_jumpr31_tnew:
3772  DstReg = MI.getOperand(1).getReg();
3773  SrcReg = MI.getOperand(0).getReg();
3774  // [if ([!]p0[.new])] jumpr r31
3775  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3776  (Hexagon::P0 == SrcReg)) &&
3777  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3778  return HexagonII::HSIG_L2;
3779  break;
3780  case Hexagon::L4_return_t:
3781  case Hexagon::L4_return_f:
3782  case Hexagon::L4_return_tnew_pnt:
3783  case Hexagon::L4_return_fnew_pnt:
3784  case Hexagon::L4_return_tnew_pt:
3785  case Hexagon::L4_return_fnew_pt:
3786  // [if ([!]p0[.new])] dealloc_return
3787  SrcReg = MI.getOperand(0).getReg();
3788  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3789  return HexagonII::HSIG_L2;
3790  break;
3791  //
3792  // Group S1:
3793  //
3794  // memw(Rs+#u4:2) = Rt
3795  // memb(Rs+#u4:0) = Rt
3796  case Hexagon::S2_storeri_io:
3797  // Special case this one from Group S2.
3798  // memw(r29+#u5:2) = Rt
3799  Src1Reg = MI.getOperand(0).getReg();
3800  Src2Reg = MI.getOperand(2).getReg();
3801  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3802  isIntRegForSubInst(Src2Reg) &&
3803  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3804  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3805  return HexagonII::HSIG_S2;
3806  // memw(Rs+#u4:2) = Rt
3807  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3808  MI.getOperand(1).isImm() &&
3809  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3810  return HexagonII::HSIG_S1;
3811  break;
3812  case Hexagon::S2_storerb_io:
3813  // memb(Rs+#u4:0) = Rt
3814  Src1Reg = MI.getOperand(0).getReg();
3815  Src2Reg = MI.getOperand(2).getReg();
3816  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3817  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3818  return HexagonII::HSIG_S1;
3819  break;
3820  //
3821  // Group S2:
3822  //
3823  // memh(Rs+#u3:1) = Rt
3824  // memw(r29+#u5:2) = Rt
3825  // memd(r29+#s6:3) = Rtt
3826  // memw(Rs+#u4:2) = #U1
3827  // memb(Rs+#u4) = #U1
3828  // allocframe(#u5:3)
3829  case Hexagon::S2_storerh_io:
3830  // memh(Rs+#u3:1) = Rt
3831  Src1Reg = MI.getOperand(0).getReg();
3832  Src2Reg = MI.getOperand(2).getReg();
3833  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3834  MI.getOperand(1).isImm() &&
3835  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3836  return HexagonII::HSIG_S1;
3837  break;
3838  case Hexagon::S2_storerd_io:
3839  // memd(r29+#s6:3) = Rtt
3840  Src1Reg = MI.getOperand(0).getReg();
3841  Src2Reg = MI.getOperand(2).getReg();
3842  if (isDblRegForSubInst(Src2Reg, HRI) &&
3843  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3844  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3845  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3846  return HexagonII::HSIG_S2;
3847  break;
3848  case Hexagon::S4_storeiri_io:
3849  // memw(Rs+#u4:2) = #U1
3850  Src1Reg = MI.getOperand(0).getReg();
3851  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3852  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3853  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3854  return HexagonII::HSIG_S2;
3855  break;
3856  case Hexagon::S4_storeirb_io:
3857  // memb(Rs+#u4) = #U1
3858  Src1Reg = MI.getOperand(0).getReg();
3859  if (isIntRegForSubInst(Src1Reg) &&
3860  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3861  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3862  return HexagonII::HSIG_S2;
3863  break;
3864  case Hexagon::S2_allocframe:
3865  if (MI.getOperand(2).isImm() &&
3866  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3867  return HexagonII::HSIG_S1;
3868  break;
3869  //
3870  // Group A:
3871  //
3872  // Rx = add(Rx,#s7)
3873  // Rd = Rs
3874  // Rd = #u6
3875  // Rd = #-1
3876  // if ([!]P0[.new]) Rd = #0
3877  // Rd = add(r29,#u6:2)
3878  // Rx = add(Rx,Rs)
3879  // P0 = cmp.eq(Rs,#u2)
3880  // Rdd = combine(#0,Rs)
3881  // Rdd = combine(Rs,#0)
3882  // Rdd = combine(#u2,#U2)
3883  // Rd = add(Rs,#1)
3884  // Rd = add(Rs,#-1)
3885  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3886  // Rd = and(Rs,#1)
3887  case Hexagon::A2_addi:
3888  DstReg = MI.getOperand(0).getReg();
3889  SrcReg = MI.getOperand(1).getReg();
3890  if (isIntRegForSubInst(DstReg)) {
3891  // Rd = add(r29,#u6:2)
3892  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3893  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3894  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3895  return HexagonII::HSIG_A;
3896  // Rx = add(Rx,#s7)
3897  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3898  isInt<7>(MI.getOperand(2).getImm()))
3899  return HexagonII::HSIG_A;
3900  // Rd = add(Rs,#1)
3901  // Rd = add(Rs,#-1)
3902  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3903  ((MI.getOperand(2).getImm() == 1) ||
3904  (MI.getOperand(2).getImm() == -1)))
3905  return HexagonII::HSIG_A;
3906  }
3907  break;
3908  case Hexagon::A2_add:
3909  // Rx = add(Rx,Rs)
3910  DstReg = MI.getOperand(0).getReg();
3911  Src1Reg = MI.getOperand(1).getReg();
3912  Src2Reg = MI.getOperand(2).getReg();
3913  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3914  isIntRegForSubInst(Src2Reg))
3915  return HexagonII::HSIG_A;
3916  break;
3917  case Hexagon::A2_andir:
3918  // Same as zxtb.
3919  // Rd16=and(Rs16,#255)
3920  // Rd16=and(Rs16,#1)
3921  DstReg = MI.getOperand(0).getReg();
3922  SrcReg = MI.getOperand(1).getReg();
3923  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3924  MI.getOperand(2).isImm() &&
3925  ((MI.getOperand(2).getImm() == 1) ||
3926  (MI.getOperand(2).getImm() == 255)))
3927  return HexagonII::HSIG_A;
3928  break;
3929  case Hexagon::A2_tfr:
3930  // Rd = Rs
3931  DstReg = MI.getOperand(0).getReg();
3932  SrcReg = MI.getOperand(1).getReg();
3933  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3934  return HexagonII::HSIG_A;
3935  break;
3936  case Hexagon::A2_tfrsi:
3937  // Rd = #u6
3938  // Do not test for #u6 size since the const is getting extended
3939  // regardless and compound could be formed.
3940  // Rd = #-1
3941  DstReg = MI.getOperand(0).getReg();
3942  if (isIntRegForSubInst(DstReg))
3943  return HexagonII::HSIG_A;
3944  break;
3945  case Hexagon::C2_cmoveit:
3946  case Hexagon::C2_cmovenewit:
3947  case Hexagon::C2_cmoveif:
3948  case Hexagon::C2_cmovenewif:
3949  // if ([!]P0[.new]) Rd = #0
3950  // Actual form:
3951  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3952  DstReg = MI.getOperand(0).getReg();
3953  SrcReg = MI.getOperand(1).getReg();
3954  if (isIntRegForSubInst(DstReg) &&
3955  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3956  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3957  return HexagonII::HSIG_A;
3958  break;
3959  case Hexagon::C2_cmpeqi:
3960  // P0 = cmp.eq(Rs,#u2)
3961  DstReg = MI.getOperand(0).getReg();
3962  SrcReg = MI.getOperand(1).getReg();
3963  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3964  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3965  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3966  return HexagonII::HSIG_A;
3967  break;
3968  case Hexagon::A2_combineii:
3969  case Hexagon::A4_combineii:
3970  // Rdd = combine(#u2,#U2)
3971  DstReg = MI.getOperand(0).getReg();
3972  if (isDblRegForSubInst(DstReg, HRI) &&
3973  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3974  (MI.getOperand(1).isGlobal() &&
3975  isUInt<2>(MI.getOperand(1).getOffset()))) &&
3976  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3977  (MI.getOperand(2).isGlobal() &&
3978  isUInt<2>(MI.getOperand(2).getOffset()))))
3979  return HexagonII::HSIG_A;
3980  break;
3981  case Hexagon::A4_combineri:
3982  // Rdd = combine(Rs,#0)
3983  DstReg = MI.getOperand(0).getReg();
3984  SrcReg = MI.getOperand(1).getReg();
3985  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3986  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3987  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3988  return HexagonII::HSIG_A;
3989  break;
3990  case Hexagon::A4_combineir:
3991  // Rdd = combine(#0,Rs)
3992  DstReg = MI.getOperand(0).getReg();
3993  SrcReg = MI.getOperand(2).getReg();
3994  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3995  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3996  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3997  return HexagonII::HSIG_A;
3998  break;
3999  case Hexagon::A2_sxtb:
4000  case Hexagon::A2_sxth:
4001  case Hexagon::A2_zxtb:
4002  case Hexagon::A2_zxth:
4003  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4004  DstReg = MI.getOperand(0).getReg();
4005  SrcReg = MI.getOperand(1).getReg();
4006  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4007  return HexagonII::HSIG_A;
4008  break;
4009  }
4010 
4011  return HexagonII::HSIG_None;
4012 }
4013 
4015  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4016 }
4017 
4019  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4020  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4021  // still have a MinLatency property, which getStageLatency checks.
4022  if (!ItinData)
4023  return getInstrLatency(ItinData, MI);
4024 
4025  if (MI.isTransient())
4026  return 0;
4027  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4028 }
4029 
4030 /// getOperandLatency - Compute and return the use operand latency of a given
4031 /// pair of def and use.
4032 /// In most cases, the static scheduling itinerary was enough to determine the
4033 /// operand latency. But it may not be possible for instructions with variable
4034 /// number of defs / uses.
4035 ///
4036 /// This is a raw interface to the itinerary that may be directly overriden by
4037 /// a target. Use computeOperandLatency to get the best estimate of latency.
4039  const MachineInstr &DefMI,
4040  unsigned DefIdx,
4041  const MachineInstr &UseMI,
4042  unsigned UseIdx) const {
4043  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4044 
4045  // Get DefIdx and UseIdx for super registers.
4046  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4047 
4048  if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
4049  if (DefMO.isImplicit()) {
4050  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4051  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4052  if (Idx != -1) {
4053  DefIdx = Idx;
4054  break;
4055  }
4056  }
4057  }
4058 
4059  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4060  if (UseMO.isImplicit()) {
4061  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4062  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4063  if (Idx != -1) {
4064  UseIdx = Idx;
4065  break;
4066  }
4067  }
4068  }
4069  }
4070 
4071  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4072  UseMI, UseIdx);
4073  if (!Latency)
4074  // We should never have 0 cycle latency between two instructions unless
4075  // they can be packetized together. However, this decision can't be made
4076  // here.
4077  Latency = 1;
4078  return Latency;
4079 }
4080 
4081 // inverts the predication logic.
4082 // p -> NotP
4083 // NotP -> P
4085  SmallVectorImpl<MachineOperand> &Cond) const {
4086  if (Cond.empty())
4087  return false;
4088  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4089  Cond[0].setImm(Opc);
4090  return true;
4091 }
4092 
4093 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4094  int InvPredOpcode;
4095  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4096  : Hexagon::getTruePredOpcode(Opc);
4097  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4098  return InvPredOpcode;
4099 
4100  llvm_unreachable("Unexpected predicated instruction");
4101 }
4102 
4103 // Returns the max value that doesn't need to be extended.
4105  const uint64_t F = MI.getDesc().TSFlags;
4106  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4108  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4110 
4111  if (isSigned) // if value is signed
4112  return ~(-1U << (bits - 1));
4113  else
4114  return ~(-1U << bits);
4115 }
4116 
4117 
4119  switch (MI.getOpcode()) {
4120  case Hexagon::L2_loadrbgp:
4121  case Hexagon::L2_loadrdgp:
4122  case Hexagon::L2_loadrhgp:
4123  case Hexagon::L2_loadrigp:
4124  case Hexagon::L2_loadrubgp:
4125  case Hexagon::L2_loadruhgp:
4126  case Hexagon::S2_storerbgp:
4127  case Hexagon::S2_storerbnewgp:
4128  case Hexagon::S2_storerhgp:
4129  case Hexagon::S2_storerhnewgp:
4130  case Hexagon::S2_storerigp:
4131  case Hexagon::S2_storerinewgp:
4132  case Hexagon::S2_storerdgp:
4133  case Hexagon::S2_storerfgp:
4134  return true;
4135  }
4136  const uint64_t F = MI.getDesc().TSFlags;
4137  unsigned addrMode =
4139  // Disallow any base+offset instruction. The assembler does not yet reorder
4140  // based up any zero offset instruction.
4141  return (addrMode == HexagonII::BaseRegOffset ||
4142  addrMode == HexagonII::BaseImmOffset ||
4143  addrMode == HexagonII::BaseLongOffset);
4144 }
4145 
4147  using namespace HexagonII;
4148 
4149  const uint64_t F = MI.getDesc().TSFlags;
4150  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4152  if (Size != 0)
4153  return Size;
4154 
4155  // Handle vector access sizes.
4156  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4157  switch (S) {
4159  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4160  default:
4161  llvm_unreachable("Unexpected instruction");
4162  }
4163 }
4164 
4165 // Returns the min value that doesn't need to be extended.
4167  const uint64_t F = MI.getDesc().TSFlags;
4168  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4170  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4172 
4173  if (isSigned) // if value is signed
4174  return -1U << (bits - 1);
4175  else
4176  return 0;
4177 }
4178 
4179 // Returns opcode of the non-extended equivalent instruction.
4181  // Check if the instruction has a register form that uses register in place
4182  // of the extended operand, if so return that as the non-extended form.
4183  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4184  if (NonExtOpcode >= 0)
4185  return NonExtOpcode;
4186 
4187  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4188  // Check addressing mode and retrieve non-ext equivalent instruction.
4189  switch (getAddrMode(MI)) {
4190  case HexagonII::Absolute:
4191  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4193  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4195  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4196 
4197  default:
4198  return -1;
4199  }
4200  }
4201  return -1;
4202 }
4203 
4205  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4206  if (Cond.empty())
4207  return false;
4208  assert(Cond.size() == 2);
4209  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4210  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4211  return false;
4212  }
4213  PredReg = Cond[1].getReg();
4214  PredRegPos = 1;
4215  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4216  PredRegFlags = 0;
4217  if (Cond[1].isImplicit())
4218  PredRegFlags = RegState::Implicit;
4219  if (Cond[1].isUndef())
4220  PredRegFlags |= RegState::Undef;
4221  return true;
4222 }
4223 
4225  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4226 }
4227 
4229  return Hexagon::getRegForm(MI.getOpcode());
4230 }
4231 
4232 // Return the number of bytes required to encode the instruction.
4233 // Hexagon instructions are fixed length, 4 bytes, unless they
4234 // use a constant extender, which requires another 4 bytes.
4235 // For debug instructions and prolog labels, return 0.
4237  if (MI.isDebugInstr() || MI.isPosition())
4238  return 0;
4239 
4240  unsigned Size = MI.getDesc().getSize();
4241  if (!Size)
4242  // Assume the default insn size in case it cannot be determined
4243  // for whatever reason.
4244  Size = HEXAGON_INSTR_SIZE;
4245 
4246  if (isConstExtended(MI) || isExtended(MI))
4247  Size += HEXAGON_INSTR_SIZE;
4248 
4249  // Try and compute number of instructions in asm.
4251  const MachineBasicBlock &MBB = *MI.getParent();
4252  const MachineFunction *MF = MBB.getParent();
4253  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4254 
4255  // Count the number of register definitions to find the asm string.
4256  unsigned NumDefs = 0;
4257  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4258  ++NumDefs)
4259  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4260 
4261  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4262  // Disassemble the AsmStr and approximate number of instructions.
4263  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4264  Size = getInlineAsmLength(AsmStr, *MAI);
4265  }
4266 
4267  return Size;
4268 }
4269 
4271  const uint64_t F = MI.getDesc().TSFlags;
4272  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4273 }
4274 
4276  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4277  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4278 
4279  return IS.getUnits();
4280 }
4281 
4282 // Calculate size of the basic block without debug instructions.
4284  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4285 }
4286 
4288  MachineBasicBlock::const_iterator BundleHead) const {
4289  assert(BundleHead->isBundle() && "Not a bundle header");
4290  auto MII = BundleHead.getInstrIterator();
4291  // Skip the bundle header.
4292  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4293 }
4294 
4295 /// immediateExtend - Changes the instruction in place to one using an immediate
4296 /// extender.
4298  assert((isExtendable(MI)||isConstExtended(MI)) &&
4299  "Instruction must be extendable");
4300  // Find which operand is extendable.
4301  short ExtOpNum = getCExtOpNum(MI);
4302  MachineOperand &MO = MI.getOperand(ExtOpNum);
4303  // This needs to be something we understand.
4304  assert((MO.isMBB() || MO.isImm()) &&
4305  "Branch with unknown extendable field type");
4306  // Mark given operand as extended.
4308 }
4309 
4311  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4312  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4313  << printMBBReference(*NewTarget);
4314  MI.dump(););
4315  assert(MI.isBranch());
4316  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4317  int TargetPos = MI.getNumOperands() - 1;
4318  // In general branch target is the last operand,
4319  // but some implicit defs added at the end might change it.
4320  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4321  --TargetPos;
4322  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4323  MI.getOperand(TargetPos).setMBB(NewTarget);
4325  NewOpcode = reversePrediction(NewOpcode);
4326  }
4327  MI.setDesc(get(NewOpcode));
4328  return true;
4329 }
4330 
4332  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4334  MachineBasicBlock &B = *A;
4336  DebugLoc DL = I->getDebugLoc();
4337  MachineInstr *NewMI;
4338 
4339  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4340  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4341  NewMI = BuildMI(B, I, DL, get(insn));
4342  LLVM_DEBUG(dbgs() << "\n"
4343  << getName(NewMI->getOpcode())
4344  << " Class: " << NewMI->getDesc().getSchedClass());
4345  NewMI->eraseFromParent();
4346  }
4347  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4348 }
4349 
4350 // inverts the predication logic.
4351 // p -> NotP
4352 // NotP -> P
4354  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4356  return true;
4357 }
4358 
4359 // Reverse the branch prediction.
4360 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4361  int PredRevOpcode = -1;
4362  if (isPredictedTaken(Opcode))
4363  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4364  else
4365  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4366  assert(PredRevOpcode > 0);
4367  return PredRevOpcode;
4368 }
4369 
4370 // TODO: Add more rigorous validation.
4372  const {
4373  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4374 }
4375 
4376 void HexagonInstrInfo::
4378  assert(MIB->isBundle());
4379  MachineOperand &Operand = MIB->getOperand(0);
4380  if (Operand.isImm())
4381  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4382  else
4383  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4384 }
4385 
4387  assert(MIB.isBundle());
4388  const MachineOperand &Operand = MIB.getOperand(0);
4389  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4390 }
4391 
4392 // Addressing mode relations.
4394  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4395 }
4396 
4398  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4399 }
4400 
4402  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4403 }
4404 
4406  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4407 }
4408 
4410  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4411 }
4412 
4414  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4415 }
4416 
4418  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4419 }
4420 
4422  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4423 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
void push_back(const T &Elt)
Definition: SmallVector.h:213
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:875
short changeAddrMode_rr_io(short Opc) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:485
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool isInlineAsm() const
Definition: MachineInstr.h:867
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
Check if the instruction or the bundle of instructions has store to stack slots.
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:938
demanded bits
MachineBasicBlock reference.
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:392
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:361
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:476
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:628
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:515
bool isEndLoopN(unsigned Opcode) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isBundle() const
Definition: MachineInstr.h:888
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
const RegList & Regs
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:509
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:481
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:570
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:672
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:546
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const char * getSeparatorString() const
Definition: MCAsmInfo.h:475
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:117
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_io_abs(short Opc) const