LLVM  6.0.0svn
HexagonInstrInfo.cpp
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1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInstrDesc.h"
39 #include "llvm/MC/MCRegisterInfo.h"
42 #include "llvm/Support/Debug.h"
48 #include <cassert>
49 #include <cctype>
50 #include <cstdint>
51 #include <cstring>
52 #include <iterator>
53 
54 using namespace llvm;
55 
56 #define DEBUG_TYPE "hexagon-instrinfo"
57 
58 #define GET_INSTRINFO_CTOR_DTOR
59 #define GET_INSTRMAP_INFO
61 #include "HexagonGenDFAPacketizer.inc"
62 #include "HexagonGenInstrInfo.inc"
63 
64 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
65  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
66  "packetization boundary."));
67 
68 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
69  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
70 
71 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
73  cl::desc("Disable schedule adjustment for new value stores."));
74 
76  "enable-timing-class-latency", cl::Hidden, cl::init(false),
77  cl::desc("Enable timing class latency"));
78 
80  "enable-alu-forwarding", cl::Hidden, cl::init(true),
81  cl::desc("Enable vec alu forwarding"));
82 
84  "enable-acc-forwarding", cl::Hidden, cl::init(true),
85  cl::desc("Enable vec acc forwarding"));
86 
87 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
88  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
89 
90 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
92  cl::desc("Use the DFA based hazard recognizer."));
93 
94 ///
95 /// Constants for Hexagon instructions.
96 ///
97 const int Hexagon_MEMW_OFFSET_MAX = 4095;
98 const int Hexagon_MEMW_OFFSET_MIN = -4096;
99 const int Hexagon_MEMD_OFFSET_MAX = 8191;
100 const int Hexagon_MEMD_OFFSET_MIN = -8192;
101 const int Hexagon_MEMH_OFFSET_MAX = 2047;
102 const int Hexagon_MEMH_OFFSET_MIN = -2048;
103 const int Hexagon_MEMB_OFFSET_MAX = 1023;
104 const int Hexagon_MEMB_OFFSET_MIN = -1024;
105 const int Hexagon_ADDI_OFFSET_MAX = 32767;
106 const int Hexagon_ADDI_OFFSET_MIN = -32768;
108 const int Hexagon_MEMD_AUTOINC_MIN = -64;
110 const int Hexagon_MEMW_AUTOINC_MIN = -32;
112 const int Hexagon_MEMH_AUTOINC_MIN = -16;
115 const int Hexagon_MEMV_AUTOINC_MAX = 192; // #s3
116 const int Hexagon_MEMV_AUTOINC_MIN = -256; // #s3
117 const int Hexagon_MEMV_AUTOINC_MAX_128B = 384; // #s3
118 const int Hexagon_MEMV_AUTOINC_MIN_128B = -512; // #s3
119 
120 // Pin the vtable to this file.
121 void HexagonInstrInfo::anchor() {}
122 
124  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
125  RI() {}
126 
127 static bool isIntRegForSubInst(unsigned Reg) {
128  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
129  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
130 }
131 
132 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
133  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
134  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
135 }
136 
137 /// Calculate number of instructions excluding the debug instructions.
140  unsigned Count = 0;
141  for (; MIB != MIE; ++MIB) {
142  if (!MIB->isDebugValue())
143  ++Count;
144  }
145  return Count;
146 }
147 
148 /// Find the hardware loop instruction used to set-up the specified loop.
149 /// On Hexagon, we have two instructions used to set-up the hardware loop
150 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
151 /// to indicate the end of a loop.
152 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
153  MachineBasicBlock *TargetBB,
155  unsigned LOOPi;
156  unsigned LOOPr;
157  if (EndLoopOp == Hexagon::ENDLOOP0) {
158  LOOPi = Hexagon::J2_loop0i;
159  LOOPr = Hexagon::J2_loop0r;
160  } else { // EndLoopOp == Hexagon::EndLOOP1
161  LOOPi = Hexagon::J2_loop1i;
162  LOOPr = Hexagon::J2_loop1r;
163  }
164 
165  // The loop set-up instruction will be in a predecessor block
166  for (MachineBasicBlock *PB : BB->predecessors()) {
167  // If this has been visited, already skip it.
168  if (!Visited.insert(PB).second)
169  continue;
170  if (PB == BB)
171  continue;
172  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
173  unsigned Opc = I->getOpcode();
174  if (Opc == LOOPi || Opc == LOOPr)
175  return &*I;
176  // We've reached a different loop, which means the loop01 has been
177  // removed.
178  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
179  return nullptr;
180  }
181  // Check the predecessors for the LOOP instruction.
182  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
183  return Loop;
184  }
185  return nullptr;
186 }
187 
188 /// Gather register def/uses from MI.
189 /// This treats possible (predicated) defs as actually happening ones
190 /// (conservatively).
191 static inline void parseOperands(const MachineInstr &MI,
193  Defs.clear();
194  Uses.clear();
195 
196  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
197  const MachineOperand &MO = MI.getOperand(i);
198 
199  if (!MO.isReg())
200  continue;
201 
202  unsigned Reg = MO.getReg();
203  if (!Reg)
204  continue;
205 
206  if (MO.isUse())
207  Uses.push_back(MO.getReg());
208 
209  if (MO.isDef())
210  Defs.push_back(MO.getReg());
211  }
212 }
213 
214 // Position dependent, so check twice for swap.
215 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
216  switch (Ga) {
218  default:
219  return false;
220  case HexagonII::HSIG_L1:
221  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
222  case HexagonII::HSIG_L2:
223  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224  Gb == HexagonII::HSIG_A);
225  case HexagonII::HSIG_S1:
226  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
227  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
228  case HexagonII::HSIG_S2:
229  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
230  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
231  Gb == HexagonII::HSIG_A);
232  case HexagonII::HSIG_A:
233  return (Gb == HexagonII::HSIG_A);
235  return (Gb == HexagonII::HSIG_Compound);
236  }
237  return false;
238 }
239 
240 /// isLoadFromStackSlot - If the specified machine instruction is a direct
241 /// load from a stack slot, return the virtual or physical register number of
242 /// the destination along with the FrameIndex of the loaded stack slot. If
243 /// not, return 0. This predicate must return 0 if the instruction has
244 /// any side effects other than loading from the stack slot.
246  int &FrameIndex) const {
247  switch (MI.getOpcode()) {
248  default:
249  break;
250  case Hexagon::L2_loadri_io:
251  case Hexagon::L2_loadrd_io:
252  case Hexagon::V6_vL32b_ai:
253  case Hexagon::V6_vL32b_nt_ai:
254  case Hexagon::V6_vL32b_ai_128B:
255  case Hexagon::V6_vL32b_nt_ai_128B:
256  case Hexagon::V6_vL32Ub_ai:
257  case Hexagon::V6_vL32Ub_ai_128B:
258  case Hexagon::LDriw_pred:
259  case Hexagon::LDriw_mod:
260  case Hexagon::PS_vloadrq_ai:
261  case Hexagon::PS_vloadrw_ai:
262  case Hexagon::PS_vloadrw_nt_ai:
263  case Hexagon::PS_vloadrq_ai_128B:
264  case Hexagon::PS_vloadrw_ai_128B:
265  case Hexagon::PS_vloadrw_nt_ai_128B: {
266  const MachineOperand OpFI = MI.getOperand(1);
267  if (!OpFI.isFI())
268  return 0;
269  const MachineOperand OpOff = MI.getOperand(2);
270  if (!OpOff.isImm() || OpOff.getImm() != 0)
271  return 0;
272  FrameIndex = OpFI.getIndex();
273  return MI.getOperand(0).getReg();
274  }
275 
276  case Hexagon::L2_ploadrit_io:
277  case Hexagon::L2_ploadrif_io:
278  case Hexagon::L2_ploadrdt_io:
279  case Hexagon::L2_ploadrdf_io: {
280  const MachineOperand OpFI = MI.getOperand(2);
281  if (!OpFI.isFI())
282  return 0;
283  const MachineOperand OpOff = MI.getOperand(3);
284  if (!OpOff.isImm() || OpOff.getImm() != 0)
285  return 0;
286  FrameIndex = OpFI.getIndex();
287  return MI.getOperand(0).getReg();
288  }
289  }
290 
291  return 0;
292 }
293 
294 /// isStoreToStackSlot - If the specified machine instruction is a direct
295 /// store to a stack slot, return the virtual or physical register number of
296 /// the source reg along with the FrameIndex of the loaded stack slot. If
297 /// not, return 0. This predicate must return 0 if the instruction has
298 /// any side effects other than storing to the stack slot.
300  int &FrameIndex) const {
301  switch (MI.getOpcode()) {
302  default:
303  break;
304  case Hexagon::S2_storerb_io:
305  case Hexagon::S2_storerh_io:
306  case Hexagon::S2_storeri_io:
307  case Hexagon::S2_storerd_io:
308  case Hexagon::V6_vS32b_ai:
309  case Hexagon::V6_vS32b_ai_128B:
310  case Hexagon::V6_vS32Ub_ai:
311  case Hexagon::V6_vS32Ub_ai_128B:
312  case Hexagon::STriw_pred:
313  case Hexagon::STriw_mod:
314  case Hexagon::PS_vstorerq_ai:
315  case Hexagon::PS_vstorerw_ai:
316  case Hexagon::PS_vstorerq_ai_128B:
317  case Hexagon::PS_vstorerw_ai_128B: {
318  const MachineOperand &OpFI = MI.getOperand(0);
319  if (!OpFI.isFI())
320  return 0;
321  const MachineOperand &OpOff = MI.getOperand(1);
322  if (!OpOff.isImm() || OpOff.getImm() != 0)
323  return 0;
324  FrameIndex = OpFI.getIndex();
325  return MI.getOperand(2).getReg();
326  }
327 
328  case Hexagon::S2_pstorerbt_io:
329  case Hexagon::S2_pstorerbf_io:
330  case Hexagon::S2_pstorerht_io:
331  case Hexagon::S2_pstorerhf_io:
332  case Hexagon::S2_pstorerit_io:
333  case Hexagon::S2_pstorerif_io:
334  case Hexagon::S2_pstorerdt_io:
335  case Hexagon::S2_pstorerdf_io: {
336  const MachineOperand &OpFI = MI.getOperand(1);
337  if (!OpFI.isFI())
338  return 0;
339  const MachineOperand &OpOff = MI.getOperand(2);
340  if (!OpOff.isImm() || OpOff.getImm() != 0)
341  return 0;
342  FrameIndex = OpFI.getIndex();
343  return MI.getOperand(3).getReg();
344  }
345  }
346 
347  return 0;
348 }
349 
350 /// This function can analyze one/two way branching only and should (mostly) be
351 /// called by target independent side.
352 /// First entry is always the opcode of the branching instruction, except when
353 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
354 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
355 /// e.g. Jump_c p will have
356 /// Cond[0] = Jump_c
357 /// Cond[1] = p
358 /// HW-loop ENDLOOP:
359 /// Cond[0] = ENDLOOP
360 /// Cond[1] = MBB
361 /// New value jump:
362 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
363 /// Cond[1] = R
364 /// Cond[2] = Imm
365 ///
367  MachineBasicBlock *&TBB,
368  MachineBasicBlock *&FBB,
370  bool AllowModify) const {
371  TBB = nullptr;
372  FBB = nullptr;
373  Cond.clear();
374 
375  // If the block has no terminators, it just falls into the block after it.
377  if (I == MBB.instr_begin())
378  return false;
379 
380  // A basic block may looks like this:
381  //
382  // [ insn
383  // EH_LABEL
384  // insn
385  // insn
386  // insn
387  // EH_LABEL
388  // insn ]
389  //
390  // It has two succs but does not have a terminator
391  // Don't know how to handle it.
392  do {
393  --I;
394  if (I->isEHLabel())
395  // Don't analyze EH branches.
396  return true;
397  } while (I != MBB.instr_begin());
398 
399  I = MBB.instr_end();
400  --I;
401 
402  while (I->isDebugValue()) {
403  if (I == MBB.instr_begin())
404  return false;
405  --I;
406  }
407 
408  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
409  I->getOperand(0).isMBB();
410  // Delete the J2_jump if it's equivalent to a fall-through.
411  if (AllowModify && JumpToBlock &&
412  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
413  DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
414  I->eraseFromParent();
415  I = MBB.instr_end();
416  if (I == MBB.instr_begin())
417  return false;
418  --I;
419  }
420  if (!isUnpredicatedTerminator(*I))
421  return false;
422 
423  // Get the last instruction in the block.
424  MachineInstr *LastInst = &*I;
425  MachineInstr *SecondLastInst = nullptr;
426  // Find one more terminator if present.
427  while (true) {
428  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
429  if (!SecondLastInst)
430  SecondLastInst = &*I;
431  else
432  // This is a third branch.
433  return true;
434  }
435  if (I == MBB.instr_begin())
436  break;
437  --I;
438  }
439 
440  int LastOpcode = LastInst->getOpcode();
441  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
442  // If the branch target is not a basic block, it could be a tail call.
443  // (It is, if the target is a function.)
444  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
445  return true;
446  if (SecLastOpcode == Hexagon::J2_jump &&
447  !SecondLastInst->getOperand(0).isMBB())
448  return true;
449 
450  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
451  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
452 
453  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
454  return true;
455 
456  // If there is only one terminator instruction, process it.
457  if (LastInst && !SecondLastInst) {
458  if (LastOpcode == Hexagon::J2_jump) {
459  TBB = LastInst->getOperand(0).getMBB();
460  return false;
461  }
462  if (isEndLoopN(LastOpcode)) {
463  TBB = LastInst->getOperand(0).getMBB();
464  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
465  Cond.push_back(LastInst->getOperand(0));
466  return false;
467  }
468  if (LastOpcodeHasJMP_c) {
469  TBB = LastInst->getOperand(1).getMBB();
470  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
471  Cond.push_back(LastInst->getOperand(0));
472  return false;
473  }
474  // Only supporting rr/ri versions of new-value jumps.
475  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
476  TBB = LastInst->getOperand(2).getMBB();
477  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
478  Cond.push_back(LastInst->getOperand(0));
479  Cond.push_back(LastInst->getOperand(1));
480  return false;
481  }
482  DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
483  << " with one jump\n";);
484  // Otherwise, don't know what this is.
485  return true;
486  }
487 
488  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
489  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
490  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
491  if (!SecondLastInst->getOperand(1).isMBB())
492  return true;
493  TBB = SecondLastInst->getOperand(1).getMBB();
494  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
495  Cond.push_back(SecondLastInst->getOperand(0));
496  FBB = LastInst->getOperand(0).getMBB();
497  return false;
498  }
499 
500  // Only supporting rr/ri versions of new-value jumps.
501  if (SecLastOpcodeHasNVJump &&
502  (SecondLastInst->getNumExplicitOperands() == 3) &&
503  (LastOpcode == Hexagon::J2_jump)) {
504  TBB = SecondLastInst->getOperand(2).getMBB();
505  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
506  Cond.push_back(SecondLastInst->getOperand(0));
507  Cond.push_back(SecondLastInst->getOperand(1));
508  FBB = LastInst->getOperand(0).getMBB();
509  return false;
510  }
511 
512  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
513  // executed, so remove it.
514  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
515  TBB = SecondLastInst->getOperand(0).getMBB();
516  I = LastInst->getIterator();
517  if (AllowModify)
518  I->eraseFromParent();
519  return false;
520  }
521 
522  // If the block ends with an ENDLOOP, and J2_jump, handle it.
523  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
524  TBB = SecondLastInst->getOperand(0).getMBB();
525  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
526  Cond.push_back(SecondLastInst->getOperand(0));
527  FBB = LastInst->getOperand(0).getMBB();
528  return false;
529  }
530  DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
531  << " with two jumps";);
532  // Otherwise, can't handle this.
533  return true;
534 }
535 
537  int *BytesRemoved) const {
538  assert(!BytesRemoved && "code size not handled");
539 
540  DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
542  unsigned Count = 0;
543  while (I != MBB.begin()) {
544  --I;
545  if (I->isDebugValue())
546  continue;
547  // Only removing branches from end of MBB.
548  if (!I->isBranch())
549  return Count;
550  if (Count && (I->getOpcode() == Hexagon::J2_jump))
551  llvm_unreachable("Malformed basic block: unconditional branch not last");
552  MBB.erase(&MBB.back());
553  I = MBB.end();
554  ++Count;
555  }
556  return Count;
557 }
558 
560  MachineBasicBlock *TBB,
561  MachineBasicBlock *FBB,
563  const DebugLoc &DL,
564  int *BytesAdded) const {
565  unsigned BOpc = Hexagon::J2_jump;
566  unsigned BccOpc = Hexagon::J2_jumpt;
567  assert(validateBranchCond(Cond) && "Invalid branching condition");
568  assert(TBB && "insertBranch must not be told to insert a fallthrough");
569  assert(!BytesAdded && "code size not handled");
570 
571  // Check if reverseBranchCondition has asked to reverse this branch
572  // If we want to reverse the branch an odd number of times, we want
573  // J2_jumpf.
574  if (!Cond.empty() && Cond[0].isImm())
575  BccOpc = Cond[0].getImm();
576 
577  if (!FBB) {
578  if (Cond.empty()) {
579  // Due to a bug in TailMerging/CFG Optimization, we need to add a
580  // special case handling of a predicated jump followed by an
581  // unconditional jump. If not, Tail Merging and CFG Optimization go
582  // into an infinite loop.
583  MachineBasicBlock *NewTBB, *NewFBB;
585  auto Term = MBB.getFirstTerminator();
586  if (Term != MBB.end() && isPredicated(*Term) &&
587  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
588  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
590  removeBranch(MBB);
591  return insertBranch(MBB, TBB, nullptr, Cond, DL);
592  }
593  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
594  } else if (isEndLoopN(Cond[0].getImm())) {
595  int EndLoopOp = Cond[0].getImm();
596  assert(Cond[1].isMBB());
597  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
598  // Check for it, and change the BB target if needed.
600  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
601  VisitedBBs);
602  assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
603  Loop->getOperand(0).setMBB(TBB);
604  // Add the ENDLOOP after the finding the LOOP0.
605  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
606  } else if (isNewValueJump(Cond[0].getImm())) {
607  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
608  // New value jump
609  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
610  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
611  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
612  DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
613  if (Cond[2].isReg()) {
614  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
615  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
616  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
617  } else if(Cond[2].isImm()) {
618  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
619  addImm(Cond[2].getImm()).addMBB(TBB);
620  } else
621  llvm_unreachable("Invalid condition for branching");
622  } else {
623  assert((Cond.size() == 2) && "Malformed cond vector");
624  const MachineOperand &RO = Cond[1];
625  unsigned Flags = getUndefRegState(RO.isUndef());
626  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
627  }
628  return 1;
629  }
630  assert((!Cond.empty()) &&
631  "Cond. cannot be empty when multiple branchings are required");
632  assert((!isNewValueJump(Cond[0].getImm())) &&
633  "NV-jump cannot be inserted with another branch");
634  // Special case for hardware loops. The condition is a basic block.
635  if (isEndLoopN(Cond[0].getImm())) {
636  int EndLoopOp = Cond[0].getImm();
637  assert(Cond[1].isMBB());
638  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
639  // Check for it, and change the BB target if needed.
641  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
642  VisitedBBs);
643  assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
644  Loop->getOperand(0).setMBB(TBB);
645  // Add the ENDLOOP after the finding the LOOP0.
646  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
647  } else {
648  const MachineOperand &RO = Cond[1];
649  unsigned Flags = getUndefRegState(RO.isUndef());
650  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
651  }
652  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
653 
654  return 2;
655 }
656 
657 /// Analyze the loop code to find the loop induction variable and compare used
658 /// to compute the number of iterations. Currently, we analyze loop that are
659 /// controlled using hardware loops. In this case, the induction variable
660 /// instruction is null. For all other cases, this function returns true, which
661 /// means we're unable to analyze it.
663  MachineInstr *&IndVarInst,
664  MachineInstr *&CmpInst) const {
665 
666  MachineBasicBlock *LoopEnd = L.getBottomBlock();
668  // We really "analyze" only hardware loops right now.
669  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
670  IndVarInst = nullptr;
671  CmpInst = &*I;
672  return false;
673  }
674  return true;
675 }
676 
677 /// Generate code to reduce the loop iteration by one and check if the loop is
678 /// finished. Return the value/register of the new loop count. this function
679 /// assumes the nth iteration is peeled first.
681  MachineInstr *IndVar, MachineInstr &Cmp,
684  unsigned Iter, unsigned MaxIter) const {
685  // We expect a hardware loop currently. This means that IndVar is set
686  // to null, and the compare is the ENDLOOP instruction.
687  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
688  && "Expecting a hardware loop");
689  MachineFunction *MF = MBB.getParent();
690  DebugLoc DL = Cmp.getDebugLoc();
692  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
693  Cmp.getOperand(0).getMBB(), VisitedBBs);
694  if (!Loop)
695  return 0;
696  // If the loop trip count is a compile-time value, then just change the
697  // value.
698  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
699  Loop->getOpcode() == Hexagon::J2_loop1i) {
700  int64_t Offset = Loop->getOperand(1).getImm();
701  if (Offset <= 1)
702  Loop->eraseFromParent();
703  else
704  Loop->getOperand(1).setImm(Offset - 1);
705  return Offset - 1;
706  }
707  // The loop trip count is a run-time value. We generate code to subtract
708  // one from the trip count, and update the loop instruction.
709  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
710  unsigned LoopCount = Loop->getOperand(1).getReg();
711  // Check if we're done with the loop.
712  unsigned LoopEnd = createVR(MF, MVT::i1);
713  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
714  addReg(LoopCount).addImm(1);
715  unsigned NewLoopCount = createVR(MF, MVT::i32);
716  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
717  addReg(LoopCount).addImm(-1);
718  // Update the previously generated instructions with the new loop counter.
720  E = PrevInsts.end(); I != E; ++I)
721  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo());
722  PrevInsts.clear();
723  PrevInsts.push_back(NewCmp);
724  PrevInsts.push_back(NewAdd);
725  // Insert the new loop instruction if this is the last time the loop is
726  // decremented.
727  if (Iter == MaxIter)
728  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
729  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
730  // Delete the old loop instruction.
731  if (Iter == 0)
732  Loop->eraseFromParent();
733  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
734  Cond.push_back(NewCmp->getOperand(0));
735  return NewLoopCount;
736 }
737 
739  unsigned NumCycles, unsigned ExtraPredCycles,
740  BranchProbability Probability) const {
741  return nonDbgBBSize(&MBB) <= 3;
742 }
743 
745  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
746  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
747  const {
748  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
749 }
750 
752  unsigned NumInstrs, BranchProbability Probability) const {
753  return NumInstrs <= 4;
754 }
755 
758  const DebugLoc &DL, unsigned DestReg,
759  unsigned SrcReg, bool KillSrc) const {
760  auto &HRI = getRegisterInfo();
761  unsigned KillFlag = getKillRegState(KillSrc);
762 
763  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
764  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
765  .addReg(SrcReg, KillFlag);
766  return;
767  }
768  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
769  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
770  .addReg(SrcReg, KillFlag);
771  return;
772  }
773  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
774  // Map Pd = Ps to Pd = or(Ps, Ps).
775  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
776  .addReg(SrcReg).addReg(SrcReg, KillFlag);
777  return;
778  }
779  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
780  Hexagon::IntRegsRegClass.contains(SrcReg)) {
781  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
782  .addReg(SrcReg, KillFlag);
783  return;
784  }
785  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
786  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
787  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
788  .addReg(SrcReg, KillFlag);
789  return;
790  }
791  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
792  Hexagon::IntRegsRegClass.contains(SrcReg)) {
793  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
794  .addReg(SrcReg, KillFlag);
795  return;
796  }
797  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
798  Hexagon::IntRegsRegClass.contains(DestReg)) {
799  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
800  .addReg(SrcReg, KillFlag);
801  return;
802  }
803  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
804  Hexagon::PredRegsRegClass.contains(DestReg)) {
805  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
806  .addReg(SrcReg, KillFlag);
807  return;
808  }
809  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
810  Hexagon::IntRegsRegClass.contains(DestReg)) {
811  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
812  .addReg(SrcReg, KillFlag);
813  return;
814  }
815  if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
816  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
817  addReg(SrcReg, KillFlag);
818  return;
819  }
820  if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
821  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
822  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
823  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
824  .addReg(HiSrc, KillFlag)
825  .addReg(LoSrc, KillFlag);
826  return;
827  }
828  if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
829  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
830  .addReg(SrcReg)
831  .addReg(SrcReg, KillFlag);
832  return;
833  }
834  if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
835  Hexagon::VectorRegsRegClass.contains(DestReg)) {
836  llvm_unreachable("Unimplemented pred to vec");
837  return;
838  }
839  if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
840  Hexagon::VectorRegsRegClass.contains(SrcReg)) {
841  llvm_unreachable("Unimplemented vec to pred");
842  return;
843  }
844  if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
845  unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
846  unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
847  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
848  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
849  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
850  .addReg(HiSrc, KillFlag);
851  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
852  .addReg(LoSrc, KillFlag);
853  return;
854  }
855 
856 #ifndef NDEBUG
857  // Show the invalid registers to ease debugging.
858  dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
859  << ": " << PrintReg(DestReg, &HRI)
860  << " = " << PrintReg(SrcReg, &HRI) << '\n';
861 #endif
862  llvm_unreachable("Unimplemented");
863 }
864 
866  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
867  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
868  DebugLoc DL = MBB.findDebugLoc(I);
869  MachineFunction &MF = *MBB.getParent();
870  MachineFrameInfo &MFI = MF.getFrameInfo();
871  unsigned Align = MFI.getObjectAlignment(FI);
872  unsigned KillFlag = getKillRegState(isKill);
873  bool HasAlloca = MFI.hasVarSizedObjects();
874  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
875  const HexagonFrameLowering &HFI = *HST.getFrameLowering();
876 
879  MFI.getObjectSize(FI), Align);
880 
881  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
882  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
883  .addFrameIndex(FI).addImm(0)
884  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
885  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
886  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
887  .addFrameIndex(FI).addImm(0)
888  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
889  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
890  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
891  .addFrameIndex(FI).addImm(0)
892  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
893  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
894  BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
895  .addFrameIndex(FI).addImm(0)
896  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
897  } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
898  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B))
899  .addFrameIndex(FI).addImm(0)
900  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
901  } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
902  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
903  .addFrameIndex(FI).addImm(0)
904  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
905  } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
906  // If there are variable-sized objects, spills will not be aligned.
907  if (HasAlloca)
908  Align = HFI.getStackAlignment();
909  unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
910  : Hexagon::V6_vS32b_ai_128B;
911  BuildMI(MBB, I, DL, get(Opc))
912  .addFrameIndex(FI).addImm(0)
913  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
914  } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
915  // If there are variable-sized objects, spills will not be aligned.
916  if (HasAlloca)
917  Align = HFI.getStackAlignment();
918  unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
919  : Hexagon::V6_vS32b_ai;
920  BuildMI(MBB, I, DL, get(Opc))
921  .addFrameIndex(FI).addImm(0)
922  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
923  } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
924  // If there are variable-sized objects, spills will not be aligned.
925  if (HasAlloca)
926  Align = HFI.getStackAlignment();
927  unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
928  : Hexagon::PS_vstorerw_ai;
929  BuildMI(MBB, I, DL, get(Opc))
930  .addFrameIndex(FI).addImm(0)
931  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
932  } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
933  // If there are variable-sized objects, spills will not be aligned.
934  if (HasAlloca)
935  Align = HFI.getStackAlignment();
936  unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
937  : Hexagon::PS_vstorerw_ai_128B;
938  BuildMI(MBB, I, DL, get(Opc))
939  .addFrameIndex(FI).addImm(0)
940  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
941  } else {
942  llvm_unreachable("Unimplemented");
943  }
944 }
945 
947  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
948  int FI, const TargetRegisterClass *RC,
949  const TargetRegisterInfo *TRI) const {
950  DebugLoc DL = MBB.findDebugLoc(I);
951  MachineFunction &MF = *MBB.getParent();
952  MachineFrameInfo &MFI = MF.getFrameInfo();
953  unsigned Align = MFI.getObjectAlignment(FI);
954  bool HasAlloca = MFI.hasVarSizedObjects();
955  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
956  const HexagonFrameLowering &HFI = *HST.getFrameLowering();
957 
960  MFI.getObjectSize(FI), Align);
961 
962  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
963  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
964  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
965  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
966  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
967  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
968  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
969  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
970  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
972  BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
973  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
974  } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
975  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg)
976  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
977  } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
978  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
979  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
980  } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
981  // If there are variable-sized objects, spills will not be aligned.
982  if (HasAlloca)
983  Align = HFI.getStackAlignment();
984  unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
985  : Hexagon::PS_vloadrw_ai_128B;
986  BuildMI(MBB, I, DL, get(Opc), DestReg)
987  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
988  } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
989  // If there are variable-sized objects, spills will not be aligned.
990  if (HasAlloca)
991  Align = HFI.getStackAlignment();
992  unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
993  : Hexagon::V6_vL32b_ai_128B;
994  BuildMI(MBB, I, DL, get(Opc), DestReg)
995  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
996  } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
997  // If there are variable-sized objects, spills will not be aligned.
998  if (HasAlloca)
999  Align = HFI.getStackAlignment();
1000  unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
1001  : Hexagon::V6_vL32b_ai;
1002  BuildMI(MBB, I, DL, get(Opc), DestReg)
1003  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1004  } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
1005  // If there are variable-sized objects, spills will not be aligned.
1006  if (HasAlloca)
1007  Align = HFI.getStackAlignment();
1008  unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
1009  : Hexagon::PS_vloadrw_ai;
1010  BuildMI(MBB, I, DL, get(Opc), DestReg)
1011  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1012  } else {
1013  llvm_unreachable("Can't store this register to stack slot");
1014  }
1015 }
1016 
1018  const MachineBasicBlock &B = *MI.getParent();
1019  Regs.addLiveOuts(B);
1020  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1021  for (auto I = B.rbegin(); I != E; ++I)
1022  Regs.stepBackward(*I);
1023 }
1024 
1025 /// expandPostRAPseudo - This function is called for all pseudo instructions
1026 /// that remain after register allocation. Many pseudo instructions are
1027 /// created to help register allocation. This is the place to convert them
1028 /// into real instructions. The target can edit MI in place, or it can insert
1029 /// new instructions and erase MI. The function should return true if
1030 /// anything was changed.
1032  const HexagonRegisterInfo &HRI = getRegisterInfo();
1034  MachineBasicBlock &MBB = *MI.getParent();
1035  DebugLoc DL = MI.getDebugLoc();
1036  unsigned Opc = MI.getOpcode();
1037  const unsigned VecOffset = 1;
1038 
1039  switch (Opc) {
1040  case TargetOpcode::COPY: {
1041  MachineOperand &MD = MI.getOperand(0);
1042  MachineOperand &MS = MI.getOperand(1);
1044  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1045  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1046  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1047  }
1048  MBB.erase(MBBI);
1049  return true;
1050  }
1051  case Hexagon::PS_aligna:
1052  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1053  .addReg(HRI.getFrameRegister())
1054  .addImm(-MI.getOperand(1).getImm());
1055  MBB.erase(MI);
1056  return true;
1057  case Hexagon::V6_vassignp_128B:
1058  case Hexagon::V6_vassignp: {
1059  unsigned SrcReg = MI.getOperand(1).getReg();
1060  unsigned DstReg = MI.getOperand(0).getReg();
1061  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1062  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1063  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1064  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1065  MBB.erase(MI);
1066  return true;
1067  }
1068  case Hexagon::V6_lo_128B:
1069  case Hexagon::V6_lo: {
1070  unsigned SrcReg = MI.getOperand(1).getReg();
1071  unsigned DstReg = MI.getOperand(0).getReg();
1072  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1073  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1074  MBB.erase(MI);
1075  MRI.clearKillFlags(SrcSubLo);
1076  return true;
1077  }
1078  case Hexagon::V6_hi_128B:
1079  case Hexagon::V6_hi: {
1080  unsigned SrcReg = MI.getOperand(1).getReg();
1081  unsigned DstReg = MI.getOperand(0).getReg();
1082  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1083  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1084  MBB.erase(MI);
1085  MRI.clearKillFlags(SrcSubHi);
1086  return true;
1087  }
1088  case Hexagon::PS_vstorerw_ai:
1089  case Hexagon::PS_vstorerwu_ai:
1090  case Hexagon::PS_vstorerw_ai_128B:
1091  case Hexagon::PS_vstorerwu_ai_128B: {
1092  bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B ||
1093  Opc == Hexagon::PS_vstorerwu_ai_128B);
1094  bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
1095  Opc == Hexagon::PS_vstorerw_ai_128B);
1096  unsigned SrcReg = MI.getOperand(2).getReg();
1097  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1098  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1099  unsigned NewOpc;
1100  if (Aligned)
1101  NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
1102  : Hexagon::V6_vS32b_ai;
1103  else
1104  NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B
1105  : Hexagon::V6_vS32Ub_ai;
1106 
1107  unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1108  MachineInstr *MI1New =
1109  BuildMI(MBB, MI, DL, get(NewOpc))
1110  .add(MI.getOperand(0))
1111  .addImm(MI.getOperand(1).getImm())
1112  .addReg(SrcSubLo)
1114  MI1New->getOperand(0).setIsKill(false);
1115  BuildMI(MBB, MI, DL, get(NewOpc))
1116  .add(MI.getOperand(0))
1117  // The Vectors are indexed in multiples of vector size.
1118  .addImm(MI.getOperand(1).getImm() + Offset)
1119  .addReg(SrcSubHi)
1121  MBB.erase(MI);
1122  return true;
1123  }
1124  case Hexagon::PS_vloadrw_ai:
1125  case Hexagon::PS_vloadrwu_ai:
1126  case Hexagon::PS_vloadrw_ai_128B:
1127  case Hexagon::PS_vloadrwu_ai_128B: {
1128  bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B ||
1129  Opc == Hexagon::PS_vloadrwu_ai_128B);
1130  bool Aligned = (Opc == Hexagon::PS_vloadrw_ai ||
1131  Opc == Hexagon::PS_vloadrw_ai_128B);
1132  unsigned NewOpc;
1133  if (Aligned)
1134  NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
1135  : Hexagon::V6_vL32b_ai;
1136  else
1137  NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B
1138  : Hexagon::V6_vL32Ub_ai;
1139 
1140  unsigned DstReg = MI.getOperand(0).getReg();
1141  unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1142  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1143  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1144  .add(MI.getOperand(1))
1145  .addImm(MI.getOperand(2).getImm())
1146  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1147  MI1New->getOperand(1).setIsKill(false);
1148  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1149  .add(MI.getOperand(1))
1150  // The Vectors are indexed in multiples of vector size.
1151  .addImm(MI.getOperand(2).getImm() + Offset)
1152  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1153  MBB.erase(MI);
1154  return true;
1155  }
1156  case Hexagon::PS_true: {
1157  unsigned Reg = MI.getOperand(0).getReg();
1158  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1159  .addReg(Reg, RegState::Undef)
1160  .addReg(Reg, RegState::Undef);
1161  MBB.erase(MI);
1162  return true;
1163  }
1164  case Hexagon::PS_false: {
1165  unsigned Reg = MI.getOperand(0).getReg();
1166  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1167  .addReg(Reg, RegState::Undef)
1168  .addReg(Reg, RegState::Undef);
1169  MBB.erase(MI);
1170  return true;
1171  }
1172  case Hexagon::PS_vmulw: {
1173  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1174  unsigned DstReg = MI.getOperand(0).getReg();
1175  unsigned Src1Reg = MI.getOperand(1).getReg();
1176  unsigned Src2Reg = MI.getOperand(2).getReg();
1177  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1178  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1179  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1180  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1181  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1182  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1183  .addReg(Src1SubHi)
1184  .addReg(Src2SubHi);
1185  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1186  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1187  .addReg(Src1SubLo)
1188  .addReg(Src2SubLo);
1189  MBB.erase(MI);
1190  MRI.clearKillFlags(Src1SubHi);
1191  MRI.clearKillFlags(Src1SubLo);
1192  MRI.clearKillFlags(Src2SubHi);
1193  MRI.clearKillFlags(Src2SubLo);
1194  return true;
1195  }
1196  case Hexagon::PS_vmulw_acc: {
1197  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1198  unsigned DstReg = MI.getOperand(0).getReg();
1199  unsigned Src1Reg = MI.getOperand(1).getReg();
1200  unsigned Src2Reg = MI.getOperand(2).getReg();
1201  unsigned Src3Reg = MI.getOperand(3).getReg();
1202  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1203  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1204  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1205  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1206  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1207  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1208  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1209  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1210  .addReg(Src1SubHi)
1211  .addReg(Src2SubHi)
1212  .addReg(Src3SubHi);
1213  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1214  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1215  .addReg(Src1SubLo)
1216  .addReg(Src2SubLo)
1217  .addReg(Src3SubLo);
1218  MBB.erase(MI);
1219  MRI.clearKillFlags(Src1SubHi);
1220  MRI.clearKillFlags(Src1SubLo);
1221  MRI.clearKillFlags(Src2SubHi);
1222  MRI.clearKillFlags(Src2SubLo);
1223  MRI.clearKillFlags(Src3SubHi);
1224  MRI.clearKillFlags(Src3SubLo);
1225  return true;
1226  }
1227  case Hexagon::PS_pselect: {
1228  const MachineOperand &Op0 = MI.getOperand(0);
1229  const MachineOperand &Op1 = MI.getOperand(1);
1230  const MachineOperand &Op2 = MI.getOperand(2);
1231  const MachineOperand &Op3 = MI.getOperand(3);
1232  unsigned Rd = Op0.getReg();
1233  unsigned Pu = Op1.getReg();
1234  unsigned Rs = Op2.getReg();
1235  unsigned Rt = Op3.getReg();
1236  DebugLoc DL = MI.getDebugLoc();
1237  unsigned K1 = getKillRegState(Op1.isKill());
1238  unsigned K2 = getKillRegState(Op2.isKill());
1239  unsigned K3 = getKillRegState(Op3.isKill());
1240  if (Rd != Rs)
1241  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1242  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1243  .addReg(Rs, K2);
1244  if (Rd != Rt)
1245  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1246  .addReg(Pu, K1)
1247  .addReg(Rt, K3);
1248  MBB.erase(MI);
1249  return true;
1250  }
1251  case Hexagon::PS_vselect:
1252  case Hexagon::PS_vselect_128B: {
1253  const MachineOperand &Op0 = MI.getOperand(0);
1254  const MachineOperand &Op1 = MI.getOperand(1);
1255  const MachineOperand &Op2 = MI.getOperand(2);
1256  const MachineOperand &Op3 = MI.getOperand(3);
1257  LivePhysRegs LiveAtMI(HRI);
1258  getLiveRegsAt(LiveAtMI, MI);
1259  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1260  unsigned PReg = Op1.getReg();
1261  assert(Op1.getSubReg() == 0);
1262  unsigned PState = getRegState(Op1);
1263 
1264  if (Op0.getReg() != Op2.getReg()) {
1265  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1266  : PState;
1267  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1268  .add(Op0)
1269  .addReg(PReg, S)
1270  .add(Op2);
1271  if (IsDestLive)
1272  T.addReg(Op0.getReg(), RegState::Implicit);
1273  IsDestLive = true;
1274  }
1275  if (Op0.getReg() != Op3.getReg()) {
1276  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1277  .add(Op0)
1278  .addReg(PReg, PState)
1279  .add(Op3);
1280  if (IsDestLive)
1281  T.addReg(Op0.getReg(), RegState::Implicit);
1282  }
1283  MBB.erase(MI);
1284  return true;
1285  }
1286  case Hexagon::PS_wselect:
1287  case Hexagon::PS_wselect_128B: {
1288  MachineOperand &Op0 = MI.getOperand(0);
1289  MachineOperand &Op1 = MI.getOperand(1);
1290  MachineOperand &Op2 = MI.getOperand(2);
1291  MachineOperand &Op3 = MI.getOperand(3);
1292  LivePhysRegs LiveAtMI(HRI);
1293  getLiveRegsAt(LiveAtMI, MI);
1294  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1295  unsigned PReg = Op1.getReg();
1296  assert(Op1.getSubReg() == 0);
1297  unsigned PState = getRegState(Op1);
1298 
1299  if (Op0.getReg() != Op2.getReg()) {
1300  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1301  : PState;
1302  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1303  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1304  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1305  .add(Op0)
1306  .addReg(PReg, S)
1307  .add(Op1)
1308  .addReg(SrcHi)
1309  .addReg(SrcLo);
1310  if (IsDestLive)
1311  T.addReg(Op0.getReg(), RegState::Implicit);
1312  IsDestLive = true;
1313  }
1314  if (Op0.getReg() != Op3.getReg()) {
1315  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1316  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1317  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1318  .add(Op0)
1319  .addReg(PReg, PState)
1320  .addReg(SrcHi)
1321  .addReg(SrcLo);
1322  if (IsDestLive)
1323  T.addReg(Op0.getReg(), RegState::Implicit);
1324  }
1325  MBB.erase(MI);
1326  return true;
1327  }
1328  case Hexagon::PS_tailcall_i:
1329  MI.setDesc(get(Hexagon::J2_jump));
1330  return true;
1331  case Hexagon::PS_tailcall_r:
1332  case Hexagon::PS_jmpret:
1333  MI.setDesc(get(Hexagon::J2_jumpr));
1334  return true;
1335  case Hexagon::PS_jmprett:
1336  MI.setDesc(get(Hexagon::J2_jumprt));
1337  return true;
1338  case Hexagon::PS_jmpretf:
1339  MI.setDesc(get(Hexagon::J2_jumprf));
1340  return true;
1341  case Hexagon::PS_jmprettnewpt:
1342  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1343  return true;
1344  case Hexagon::PS_jmpretfnewpt:
1345  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1346  return true;
1347  case Hexagon::PS_jmprettnew:
1348  MI.setDesc(get(Hexagon::J2_jumprtnew));
1349  return true;
1350  case Hexagon::PS_jmpretfnew:
1351  MI.setDesc(get(Hexagon::J2_jumprfnew));
1352  return true;
1353  }
1354 
1355  return false;
1356 }
1357 
1358 // We indicate that we want to reverse the branch by
1359 // inserting the reversed branching opcode.
1361  SmallVectorImpl<MachineOperand> &Cond) const {
1362  if (Cond.empty())
1363  return true;
1364  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1365  unsigned opcode = Cond[0].getImm();
1366  //unsigned temp;
1367  assert(get(opcode).isBranch() && "Should be a branching condition.");
1368  if (isEndLoopN(opcode))
1369  return true;
1370  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1371  Cond[0].setImm(NewOpcode);
1372  return false;
1373 }
1374 
1377  DebugLoc DL;
1378  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1379 }
1380 
1382  return getAddrMode(MI) == HexagonII::PostInc;
1383 }
1384 
1385 // Returns true if an instruction is predicated irrespective of the predicate
1386 // sense. For example, all of the following will return true.
1387 // if (p0) R1 = add(R2, R3)
1388 // if (!p0) R1 = add(R2, R3)
1389 // if (p0.new) R1 = add(R2, R3)
1390 // if (!p0.new) R1 = add(R2, R3)
1391 // Note: New-value stores are not included here as in the current
1392 // implementation, we don't need to check their predicate sense.
1394  const uint64_t F = MI.getDesc().TSFlags;
1396 }
1397 
1399  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1400  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1401  isEndLoopN(Cond[0].getImm())) {
1402  DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1403  return false;
1404  }
1405  int Opc = MI.getOpcode();
1406  assert (isPredicable(MI) && "Expected predicable instruction");
1407  bool invertJump = predOpcodeHasNot(Cond);
1408 
1409  // We have to predicate MI "in place", i.e. after this function returns,
1410  // MI will need to be transformed into a predicated form. To avoid com-
1411  // plicated manipulations with the operands (handling tied operands,
1412  // etc.), build a new temporary instruction, then overwrite MI with it.
1413 
1414  MachineBasicBlock &B = *MI.getParent();
1415  DebugLoc DL = MI.getDebugLoc();
1416  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1417  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1418  unsigned NOp = 0, NumOps = MI.getNumOperands();
1419  while (NOp < NumOps) {
1420  MachineOperand &Op = MI.getOperand(NOp);
1421  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1422  break;
1423  T.add(Op);
1424  NOp++;
1425  }
1426 
1427  unsigned PredReg, PredRegPos, PredRegFlags;
1428  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1429  (void)GotPredReg;
1430  assert(GotPredReg);
1431  T.addReg(PredReg, PredRegFlags);
1432  while (NOp < NumOps)
1433  T.add(MI.getOperand(NOp++));
1434 
1435  MI.setDesc(get(PredOpc));
1436  while (unsigned n = MI.getNumOperands())
1437  MI.RemoveOperand(n-1);
1438  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1439  MI.addOperand(T->getOperand(i));
1440 
1442  B.erase(TI);
1443 
1445  MRI.clearKillFlags(PredReg);
1446  return true;
1447 }
1448 
1450  ArrayRef<MachineOperand> Pred2) const {
1451  // TODO: Fix this
1452  return false;
1453 }
1454 
1456  MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
1457  auto &HRI = getRegisterInfo();
1458  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1459  MachineOperand MO = MI.getOperand(oper);
1460  if (MO.isReg()) {
1461  if (!MO.isDef())
1462  continue;
1463  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1464  if (RC == &Hexagon::PredRegsRegClass) {
1465  Pred.push_back(MO);
1466  return true;
1467  }
1468  continue;
1469  } else if (MO.isRegMask()) {
1470  for (unsigned PR : Hexagon::PredRegsRegClass) {
1471  if (!MI.modifiesRegister(PR, &HRI))
1472  continue;
1473  Pred.push_back(MO);
1474  return true;
1475  }
1476  }
1477  }
1478  return false;
1479 }
1480 
1482  if (!MI.getDesc().isPredicable())
1483  return false;
1484 
1485  if (MI.isCall() || isTailCall(MI)) {
1486  const MachineFunction &MF = *MI.getParent()->getParent();
1488  return false;
1489  }
1490  return true;
1491 }
1492 
1494  const MachineBasicBlock *MBB,
1495  const MachineFunction &MF) const {
1496  // Debug info is never a scheduling boundary. It's necessary to be explicit
1497  // due to the special treatment of IT instructions below, otherwise a
1498  // dbg_value followed by an IT will result in the IT instruction being
1499  // considered a scheduling hazard, which is wrong. It should be the actual
1500  // instruction preceding the dbg_value instruction(s), just like it is
1501  // when debug info is not present.
1502  if (MI.isDebugValue())
1503  return false;
1504 
1505  // Throwing call is a boundary.
1506  if (MI.isCall()) {
1507  // Don't mess around with no return calls.
1508  if (doesNotReturn(MI))
1509  return true;
1510  // If any of the block's successors is a landing pad, this could be a
1511  // throwing call.
1512  for (auto I : MBB->successors())
1513  if (I->isEHPad())
1514  return true;
1515  }
1516 
1517  // Terminators and labels can't be scheduled around.
1518  if (MI.getDesc().isTerminator() || MI.isPosition())
1519  return true;
1520 
1521  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1522  return true;
1523 
1524  return false;
1525 }
1526 
1527 /// Measure the specified inline asm to determine an approximation of its
1528 /// length.
1529 /// Comments (which run till the next SeparatorString or newline) do not
1530 /// count as an instruction.
1531 /// Any other non-whitespace text is considered an instruction, with
1532 /// multiple instructions separated by SeparatorString or newlines.
1533 /// Variable-length instructions are not handled here; this function
1534 /// may be overloaded in the target code to do that.
1535 /// Hexagon counts the number of ##'s and adjust for that many
1536 /// constant exenders.
1537 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1538  const MCAsmInfo &MAI) const {
1539  StringRef AStr(Str);
1540  // Count the number of instructions in the asm.
1541  bool atInsnStart = true;
1542  unsigned Length = 0;
1543  for (; *Str; ++Str) {
1544  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1545  strlen(MAI.getSeparatorString())) == 0)
1546  atInsnStart = true;
1547  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1548  Length += MAI.getMaxInstLength();
1549  atInsnStart = false;
1550  }
1551  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1552  MAI.getCommentString().size()) == 0)
1553  atInsnStart = false;
1554  }
1555 
1556  // Add to size number of constant extenders seen * 4.
1557  StringRef Occ("##");
1558  Length += AStr.count(Occ)*4;
1559  return Length;
1560 }
1561 
1564  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1565  if (UseDFAHazardRec) {
1566  auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
1567  return new HexagonHazardRecognizer(II, this, HST);
1568  }
1570 }
1571 
1572 /// \brief For a comparison instruction, return the source registers in
1573 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1574 /// compares against in CmpValue. Return true if the comparison instruction
1575 /// can be analyzed.
1576 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1577  unsigned &SrcReg2, int &Mask,
1578  int &Value) const {
1579  unsigned Opc = MI.getOpcode();
1580 
1581  // Set mask and the first source register.
1582  switch (Opc) {
1583  case Hexagon::C2_cmpeq:
1584  case Hexagon::C2_cmpeqp:
1585  case Hexagon::C2_cmpgt:
1586  case Hexagon::C2_cmpgtp:
1587  case Hexagon::C2_cmpgtu:
1588  case Hexagon::C2_cmpgtup:
1589  case Hexagon::C4_cmpneq:
1590  case Hexagon::C4_cmplte:
1591  case Hexagon::C4_cmplteu:
1592  case Hexagon::C2_cmpeqi:
1593  case Hexagon::C2_cmpgti:
1594  case Hexagon::C2_cmpgtui:
1595  case Hexagon::C4_cmpneqi:
1596  case Hexagon::C4_cmplteui:
1597  case Hexagon::C4_cmpltei:
1598  SrcReg = MI.getOperand(1).getReg();
1599  Mask = ~0;
1600  break;
1601  case Hexagon::A4_cmpbeq:
1602  case Hexagon::A4_cmpbgt:
1603  case Hexagon::A4_cmpbgtu:
1604  case Hexagon::A4_cmpbeqi:
1605  case Hexagon::A4_cmpbgti:
1606  case Hexagon::A4_cmpbgtui:
1607  SrcReg = MI.getOperand(1).getReg();
1608  Mask = 0xFF;
1609  break;
1610  case Hexagon::A4_cmpheq:
1611  case Hexagon::A4_cmphgt:
1612  case Hexagon::A4_cmphgtu:
1613  case Hexagon::A4_cmpheqi:
1614  case Hexagon::A4_cmphgti:
1615  case Hexagon::A4_cmphgtui:
1616  SrcReg = MI.getOperand(1).getReg();
1617  Mask = 0xFFFF;
1618  break;
1619  }
1620 
1621  // Set the value/second source register.
1622  switch (Opc) {
1623  case Hexagon::C2_cmpeq:
1624  case Hexagon::C2_cmpeqp:
1625  case Hexagon::C2_cmpgt:
1626  case Hexagon::C2_cmpgtp:
1627  case Hexagon::C2_cmpgtu:
1628  case Hexagon::C2_cmpgtup:
1629  case Hexagon::A4_cmpbeq:
1630  case Hexagon::A4_cmpbgt:
1631  case Hexagon::A4_cmpbgtu:
1632  case Hexagon::A4_cmpheq:
1633  case Hexagon::A4_cmphgt:
1634  case Hexagon::A4_cmphgtu:
1635  case Hexagon::C4_cmpneq:
1636  case Hexagon::C4_cmplte:
1637  case Hexagon::C4_cmplteu:
1638  SrcReg2 = MI.getOperand(2).getReg();
1639  return true;
1640 
1641  case Hexagon::C2_cmpeqi:
1642  case Hexagon::C2_cmpgtui:
1643  case Hexagon::C2_cmpgti:
1644  case Hexagon::C4_cmpneqi:
1645  case Hexagon::C4_cmplteui:
1646  case Hexagon::C4_cmpltei:
1647  case Hexagon::A4_cmpbeqi:
1648  case Hexagon::A4_cmpbgti:
1649  case Hexagon::A4_cmpbgtui:
1650  case Hexagon::A4_cmpheqi:
1651  case Hexagon::A4_cmphgti:
1652  case Hexagon::A4_cmphgtui:
1653  SrcReg2 = 0;
1654  Value = MI.getOperand(2).getImm();
1655  return true;
1656  }
1657 
1658  return false;
1659 }
1660 
1662  const MachineInstr &MI,
1663  unsigned *PredCost) const {
1664  return getInstrTimingClassLatency(ItinData, MI);
1665 }
1666 
1667 
1669  const TargetSubtargetInfo &STI) const {
1670  const InstrItineraryData *II = STI.getInstrItineraryData();
1671  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1672 }
1673 
1674 // Inspired by this pair:
1675 // %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
1676 // S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
1677 // Currently AA considers the addresses in these instructions to be aliasing.
1679  MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1680  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1682  return false;
1683 
1684  // Instructions that are pure loads, not loads and stores like memops are not
1685  // dependent.
1686  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1687  return true;
1688 
1689  // Get the base register in MIa.
1690  unsigned BasePosA, OffsetPosA;
1691  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1692  return false;
1693  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1694  unsigned BaseRegA = BaseA.getReg();
1695  unsigned BaseSubA = BaseA.getSubReg();
1696 
1697  // Get the base register in MIb.
1698  unsigned BasePosB, OffsetPosB;
1699  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1700  return false;
1701  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1702  unsigned BaseRegB = BaseB.getReg();
1703  unsigned BaseSubB = BaseB.getSubReg();
1704 
1705  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1706  return false;
1707 
1708  // Get the access sizes.
1709  unsigned SizeA = (1u << (getMemAccessSize(MIa) - 1));
1710  unsigned SizeB = (1u << (getMemAccessSize(MIb) - 1));
1711 
1712  // Get the offsets. Handle immediates only for now.
1713  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1714  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1715  if (!MIa.getOperand(OffsetPosA).isImm() ||
1716  !MIb.getOperand(OffsetPosB).isImm())
1717  return false;
1718  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1719  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1720 
1721  // This is a mem access with the same base register and known offsets from it.
1722  // Reason about it.
1723  if (OffsetA > OffsetB) {
1724  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1725  return SizeB <= OffDiff;
1726  }
1727  if (OffsetA < OffsetB) {
1728  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1729  return SizeA <= OffDiff;
1730  }
1731 
1732  return false;
1733 }
1734 
1735 /// If the instruction is an increment of a constant value, return the amount.
1737  int &Value) const {
1738  if (isPostIncrement(MI)) {
1739  unsigned AccessSize;
1740  return getBaseAndOffset(MI, Value, AccessSize);
1741  }
1742  if (MI.getOpcode() == Hexagon::A2_addi) {
1743  Value = MI.getOperand(2).getImm();
1744  return true;
1745  }
1746 
1747  return false;
1748 }
1749 
1750 std::pair<unsigned, unsigned>
1752  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1753  TF & HexagonII::MO_Bitmasks);
1754 }
1755 
1758  using namespace HexagonII;
1759  static const std::pair<unsigned, const char*> Flags[] = {
1760  {MO_PCREL, "hexagon-pcrel"},
1761  {MO_GOT, "hexagon-got"},
1762  {MO_LO16, "hexagon-lo16"},
1763  {MO_HI16, "hexagon-hi16"},
1764  {MO_GPREL, "hexagon-gprel"},
1765  {MO_GDGOT, "hexagon-gdgot"},
1766  {MO_GDPLT, "hexagon-gdplt"},
1767  {MO_IE, "hexagon-ie"},
1768  {MO_IEGOT, "hexagon-iegot"},
1769  {MO_TPREL, "hexagon-tprel"}
1770  };
1771  return makeArrayRef(Flags);
1772 }
1773 
1776  using namespace HexagonII;
1777  static const std::pair<unsigned, const char*> Flags[] = {
1778  {HMOTF_ConstExtended, "hexagon-ext"}
1779  };
1780  return makeArrayRef(Flags);
1781 }
1782 
1785  const TargetRegisterClass *TRC;
1786  if (VT == MVT::i1) {
1787  TRC = &Hexagon::PredRegsRegClass;
1788  } else if (VT == MVT::i32 || VT == MVT::f32) {
1789  TRC = &Hexagon::IntRegsRegClass;
1790  } else if (VT == MVT::i64 || VT == MVT::f64) {
1791  TRC = &Hexagon::DoubleRegsRegClass;
1792  } else {
1793  llvm_unreachable("Cannot handle this register class");
1794  }
1795 
1796  unsigned NewReg = MRI.createVirtualRegister(TRC);
1797  return NewReg;
1798 }
1799 
1801  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1802 }
1803 
1805  const uint64_t F = MI.getDesc().TSFlags;
1807 }
1808 
1810  const MachineFunction *MF = MI.getParent()->getParent();
1811  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1812  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1813 
1814  if (!(isTC1(MI))
1815  && !(QII->isTC2Early(MI))
1816  && !(MI.getDesc().mayLoad())
1817  && !(MI.getDesc().mayStore())
1818  && (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
1819  && (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
1820  && !(QII->isMemOp(MI))
1821  && !(MI.isBranch())
1822  && !(MI.isReturn())
1823  && !MI.isCall())
1824  return true;
1825 
1826  return false;
1827 }
1828 
1829 // Return true if the instruction is a compund branch instruction.
1831  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1832 }
1833 
1834 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1835 // isFPImm and later getFPImm as well.
1837  const uint64_t F = MI.getDesc().TSFlags;
1839  if (isExtended) // Instruction must be extended.
1840  return true;
1841 
1842  unsigned isExtendable =
1844  if (!isExtendable)
1845  return false;
1846 
1847  if (MI.isCall())
1848  return false;
1849 
1850  short ExtOpNum = getCExtOpNum(MI);
1851  const MachineOperand &MO = MI.getOperand(ExtOpNum);
1852  // Use MO operand flags to determine if MO
1853  // has the HMOTF_ConstExtended flag set.
1855  return true;
1856  // If this is a Machine BB address we are talking about, and it is
1857  // not marked as extended, say so.
1858  if (MO.isMBB())
1859  return false;
1860 
1861  // We could be using an instruction with an extendable immediate and shoehorn
1862  // a global address into it. If it is a global address it will be constant
1863  // extended. We do this for COMBINE.
1864  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1865  MO.isJTI() || MO.isCPI() || MO.isFPImm())
1866  return true;
1867 
1868  // If the extendable operand is not 'Immediate' type, the instruction should
1869  // have 'isExtended' flag set.
1870  assert(MO.isImm() && "Extendable operand must be Immediate type");
1871 
1872  int MinValue = getMinValue(MI);
1873  int MaxValue = getMaxValue(MI);
1874  int ImmValue = MO.getImm();
1875 
1876  return (ImmValue < MinValue || ImmValue > MaxValue);
1877 }
1878 
1880  switch (MI.getOpcode()) {
1881  case Hexagon::L4_return :
1882  case Hexagon::L4_return_t :
1883  case Hexagon::L4_return_f :
1884  case Hexagon::L4_return_tnew_pnt :
1885  case Hexagon::L4_return_fnew_pnt :
1886  case Hexagon::L4_return_tnew_pt :
1887  case Hexagon::L4_return_fnew_pt :
1888  return true;
1889  }
1890  return false;
1891 }
1892 
1893 // Return true when ConsMI uses a register defined by ProdMI.
1895  const MachineInstr &ConsMI) const {
1896  if (!ProdMI.getDesc().getNumDefs())
1897  return false;
1898 
1899  auto &HRI = getRegisterInfo();
1900 
1905 
1906  parseOperands(ProdMI, DefsA, UsesA);
1907  parseOperands(ConsMI, DefsB, UsesB);
1908 
1909  for (auto &RegA : DefsA)
1910  for (auto &RegB : UsesB) {
1911  // True data dependency.
1912  if (RegA == RegB)
1913  return true;
1914 
1916  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1917  if (RegB == *SubRegs)
1918  return true;
1919 
1921  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1922  if (RegA == *SubRegs)
1923  return true;
1924  }
1925 
1926  return false;
1927 }
1928 
1929 // Returns true if the instruction is alread a .cur.
1931  switch (MI.getOpcode()) {
1932  case Hexagon::V6_vL32b_cur_pi:
1933  case Hexagon::V6_vL32b_cur_ai:
1934  case Hexagon::V6_vL32b_cur_pi_128B:
1935  case Hexagon::V6_vL32b_cur_ai_128B:
1936  return true;
1937  }
1938  return false;
1939 }
1940 
1941 // Returns true, if any one of the operands is a dot new
1942 // insn, whether it is predicated dot new or register dot new.
1944  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
1945  return true;
1946 
1947  return false;
1948 }
1949 
1950 /// Symmetrical. See if these two instructions are fit for duplex pair.
1952  const MachineInstr &MIb) const {
1955  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
1956 }
1957 
1959  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
1960  return true;
1961 
1962  // Multiply
1963  unsigned SchedClass = MI.getDesc().getSchedClass();
1964  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
1965 }
1966 
1967 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
1968  return (Opcode == Hexagon::ENDLOOP0 ||
1969  Opcode == Hexagon::ENDLOOP1);
1970 }
1971 
1972 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
1973  switch(OpType) {
1980  return true;
1981  default:
1982  return false;
1983  }
1984 }
1985 
1987  const MCInstrDesc &MID = MI.getDesc();
1988  const uint64_t F = MID.TSFlags;
1990  return true;
1991 
1992  // TODO: This is largely obsolete now. Will need to be removed
1993  // in consecutive patches.
1994  switch (MI.getOpcode()) {
1995  // PS_fi and PS_fia remain special cases.
1996  case Hexagon::PS_fi:
1997  case Hexagon::PS_fia:
1998  return true;
1999  default:
2000  return false;
2001  }
2002  return false;
2003 }
2004 
2005 // This returns true in two cases:
2006 // - The OP code itself indicates that this is an extended instruction.
2007 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2009  // First check if this is permanently extended op code.
2010  const uint64_t F = MI.getDesc().TSFlags;
2012  return true;
2013  // Use MO operand flags to determine if one of MI's operands
2014  // has HMOTF_ConstExtended flag set.
2015  for (const MachineOperand &MO : MI.operands())
2016  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2017  return true;
2018  return false;
2019 }
2020 
2022  unsigned Opcode = MI.getOpcode();
2023  const uint64_t F = get(Opcode).TSFlags;
2024  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2025 }
2026 
2027 // No V60 HVX VMEM with A_INDIRECT.
2029  const MachineInstr &J) const {
2030  if (!isHVXVec(I))
2031  return false;
2032  if (!I.mayLoad() && !I.mayStore())
2033  return false;
2034  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2035 }
2036 
2038  switch (MI.getOpcode()) {
2039  case Hexagon::J2_callr :
2040  case Hexagon::J2_callrf :
2041  case Hexagon::J2_callrt :
2042  case Hexagon::PS_call_nr :
2043  return true;
2044  }
2045  return false;
2046 }
2047 
2049  switch (MI.getOpcode()) {
2050  case Hexagon::L4_return :
2051  case Hexagon::L4_return_t :
2052  case Hexagon::L4_return_f :
2053  case Hexagon::L4_return_fnew_pnt :
2054  case Hexagon::L4_return_fnew_pt :
2055  case Hexagon::L4_return_tnew_pnt :
2056  case Hexagon::L4_return_tnew_pt :
2057  return true;
2058  }
2059  return false;
2060 }
2061 
2063  switch (MI.getOpcode()) {
2064  case Hexagon::J2_jumpr :
2065  case Hexagon::J2_jumprt :
2066  case Hexagon::J2_jumprf :
2067  case Hexagon::J2_jumprtnewpt :
2068  case Hexagon::J2_jumprfnewpt :
2069  case Hexagon::J2_jumprtnew :
2070  case Hexagon::J2_jumprfnew :
2071  return true;
2072  }
2073  return false;
2074 }
2075 
2076 // Return true if a given MI can accommodate given offset.
2077 // Use abs estimate as oppose to the exact number.
2078 // TODO: This will need to be changed to use MC level
2079 // definition of instruction extendable field size.
2081  unsigned offset) const {
2082  // This selection of jump instructions matches to that what
2083  // analyzeBranch can parse, plus NVJ.
2084  if (isNewValueJump(MI)) // r9:2
2085  return isInt<11>(offset);
2086 
2087  switch (MI.getOpcode()) {
2088  // Still missing Jump to address condition on register value.
2089  default:
2090  return false;
2091  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2092  case Hexagon::J2_call:
2093  case Hexagon::PS_call_nr:
2094  return isInt<24>(offset);
2095  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2096  case Hexagon::J2_jumpf:
2097  case Hexagon::J2_jumptnew:
2098  case Hexagon::J2_jumptnewpt:
2099  case Hexagon::J2_jumpfnew:
2100  case Hexagon::J2_jumpfnewpt:
2101  case Hexagon::J2_callt:
2102  case Hexagon::J2_callf:
2103  return isInt<17>(offset);
2104  case Hexagon::J2_loop0i:
2105  case Hexagon::J2_loop0iext:
2106  case Hexagon::J2_loop0r:
2107  case Hexagon::J2_loop0rext:
2108  case Hexagon::J2_loop1i:
2109  case Hexagon::J2_loop1iext:
2110  case Hexagon::J2_loop1r:
2111  case Hexagon::J2_loop1rext:
2112  return isInt<9>(offset);
2113  // TODO: Add all the compound branches here. Can we do this in Relation model?
2114  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2115  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2116  return isInt<11>(offset);
2117  }
2118 }
2119 
2121  const MachineInstr &ESMI) const {
2122  bool isLate = isLateResultInstr(LRMI);
2123  bool isEarly = isEarlySourceInstr(ESMI);
2124 
2125  DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2126  DEBUG(LRMI.dump());
2127  DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2128  DEBUG(ESMI.dump());
2129 
2130  if (isLate && isEarly) {
2131  DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2132  return true;
2133  }
2134 
2135  return false;
2136 }
2137 
2139  switch (MI.getOpcode()) {
2140  case TargetOpcode::EXTRACT_SUBREG:
2141  case TargetOpcode::INSERT_SUBREG:
2142  case TargetOpcode::SUBREG_TO_REG:
2143  case TargetOpcode::REG_SEQUENCE:
2144  case TargetOpcode::IMPLICIT_DEF:
2145  case TargetOpcode::COPY:
2147  case TargetOpcode::PHI:
2148  return false;
2149  default:
2150  break;
2151  }
2152 
2153  unsigned SchedClass = MI.getDesc().getSchedClass();
2154  return !is_TC1(SchedClass);
2155 }
2156 
2158  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2159  // resource, but all operands can be received late like an ALU instruction.
2160  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2161 }
2162 
2164  unsigned Opcode = MI.getOpcode();
2165  return Opcode == Hexagon::J2_loop0i ||
2166  Opcode == Hexagon::J2_loop0r ||
2167  Opcode == Hexagon::J2_loop0iext ||
2168  Opcode == Hexagon::J2_loop0rext ||
2169  Opcode == Hexagon::J2_loop1i ||
2170  Opcode == Hexagon::J2_loop1r ||
2171  Opcode == Hexagon::J2_loop1iext ||
2172  Opcode == Hexagon::J2_loop1rext;
2173 }
2174 
2176  switch (MI.getOpcode()) {
2177  default: return false;
2178  case Hexagon::L4_iadd_memopw_io :
2179  case Hexagon::L4_isub_memopw_io :
2180  case Hexagon::L4_add_memopw_io :
2181  case Hexagon::L4_sub_memopw_io :
2182  case Hexagon::L4_and_memopw_io :
2183  case Hexagon::L4_or_memopw_io :
2184  case Hexagon::L4_iadd_memoph_io :
2185  case Hexagon::L4_isub_memoph_io :
2186  case Hexagon::L4_add_memoph_io :
2187  case Hexagon::L4_sub_memoph_io :
2188  case Hexagon::L4_and_memoph_io :
2189  case Hexagon::L4_or_memoph_io :
2190  case Hexagon::L4_iadd_memopb_io :
2191  case Hexagon::L4_isub_memopb_io :
2192  case Hexagon::L4_add_memopb_io :
2193  case Hexagon::L4_sub_memopb_io :
2194  case Hexagon::L4_and_memopb_io :
2195  case Hexagon::L4_or_memopb_io :
2196  case Hexagon::L4_ior_memopb_io:
2197  case Hexagon::L4_ior_memoph_io:
2198  case Hexagon::L4_ior_memopw_io:
2199  case Hexagon::L4_iand_memopb_io:
2200  case Hexagon::L4_iand_memoph_io:
2201  case Hexagon::L4_iand_memopw_io:
2202  return true;
2203  }
2204  return false;
2205 }
2206 
2208  const uint64_t F = MI.getDesc().TSFlags;
2210 }
2211 
2212 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2213  const uint64_t F = get(Opcode).TSFlags;
2215 }
2216 
2218  return isNewValueJump(MI) || isNewValueStore(MI);
2219 }
2220 
2222  return isNewValue(MI) && MI.isBranch();
2223 }
2224 
2225 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2226  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2227 }
2228 
2230  const uint64_t F = MI.getDesc().TSFlags;
2232 }
2233 
2234 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2235  const uint64_t F = get(Opcode).TSFlags;
2237 }
2238 
2239 // Returns true if a particular operand is extendable for an instruction.
2241  unsigned OperandNum) const {
2242  const uint64_t F = MI.getDesc().TSFlags;
2244  == OperandNum;
2245 }
2246 
2248  const uint64_t F = MI.getDesc().TSFlags;
2249  assert(isPredicated(MI));
2251 }
2252 
2253 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2254  const uint64_t F = get(Opcode).TSFlags;
2255  assert(isPredicated(Opcode));
2257 }
2258 
2260  const uint64_t F = MI.getDesc().TSFlags;
2261  return !((F >> HexagonII::PredicatedFalsePos) &
2263 }
2264 
2265 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2266  const uint64_t F = get(Opcode).TSFlags;
2267  // Make sure that the instruction is predicated.
2269  return !((F >> HexagonII::PredicatedFalsePos) &
2271 }
2272 
2273 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2274  const uint64_t F = get(Opcode).TSFlags;
2276 }
2277 
2278 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2279  const uint64_t F = get(Opcode).TSFlags;
2281 }
2282 
2283 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2284  const uint64_t F = get(Opcode).TSFlags;
2285  assert(get(Opcode).isBranch() &&
2286  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2287  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2288 }
2289 
2291  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2292  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2293  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2294  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2295 }
2296 
2298  switch (MI.getOpcode()) {
2299  // Byte
2300  case Hexagon::L2_loadrb_io:
2301  case Hexagon::L4_loadrb_ur:
2302  case Hexagon::L4_loadrb_ap:
2303  case Hexagon::L2_loadrb_pr:
2304  case Hexagon::L2_loadrb_pbr:
2305  case Hexagon::L2_loadrb_pi:
2306  case Hexagon::L2_loadrb_pci:
2307  case Hexagon::L2_loadrb_pcr:
2308  case Hexagon::L2_loadbsw2_io:
2309  case Hexagon::L4_loadbsw2_ur:
2310  case Hexagon::L4_loadbsw2_ap:
2311  case Hexagon::L2_loadbsw2_pr:
2312  case Hexagon::L2_loadbsw2_pbr:
2313  case Hexagon::L2_loadbsw2_pi:
2314  case Hexagon::L2_loadbsw2_pci:
2315  case Hexagon::L2_loadbsw2_pcr:
2316  case Hexagon::L2_loadbsw4_io:
2317  case Hexagon::L4_loadbsw4_ur:
2318  case Hexagon::L4_loadbsw4_ap:
2319  case Hexagon::L2_loadbsw4_pr:
2320  case Hexagon::L2_loadbsw4_pbr:
2321  case Hexagon::L2_loadbsw4_pi:
2322  case Hexagon::L2_loadbsw4_pci:
2323  case Hexagon::L2_loadbsw4_pcr:
2324  case Hexagon::L4_loadrb_rr:
2325  case Hexagon::L2_ploadrbt_io:
2326  case Hexagon::L2_ploadrbt_pi:
2327  case Hexagon::L2_ploadrbf_io:
2328  case Hexagon::L2_ploadrbf_pi:
2329  case Hexagon::L2_ploadrbtnew_io:
2330  case Hexagon::L2_ploadrbfnew_io:
2331  case Hexagon::L4_ploadrbt_rr:
2332  case Hexagon::L4_ploadrbf_rr:
2333  case Hexagon::L4_ploadrbtnew_rr:
2334  case Hexagon::L4_ploadrbfnew_rr:
2335  case Hexagon::L2_ploadrbtnew_pi:
2336  case Hexagon::L2_ploadrbfnew_pi:
2337  case Hexagon::L4_ploadrbt_abs:
2338  case Hexagon::L4_ploadrbf_abs:
2339  case Hexagon::L4_ploadrbtnew_abs:
2340  case Hexagon::L4_ploadrbfnew_abs:
2341  case Hexagon::L2_loadrbgp:
2342  // Half
2343  case Hexagon::L2_loadrh_io:
2344  case Hexagon::L4_loadrh_ur:
2345  case Hexagon::L4_loadrh_ap:
2346  case Hexagon::L2_loadrh_pr:
2347  case Hexagon::L2_loadrh_pbr:
2348  case Hexagon::L2_loadrh_pi:
2349  case Hexagon::L2_loadrh_pci:
2350  case Hexagon::L2_loadrh_pcr:
2351  case Hexagon::L4_loadrh_rr:
2352  case Hexagon::L2_ploadrht_io:
2353  case Hexagon::L2_ploadrht_pi:
2354  case Hexagon::L2_ploadrhf_io:
2355  case Hexagon::L2_ploadrhf_pi:
2356  case Hexagon::L2_ploadrhtnew_io:
2357  case Hexagon::L2_ploadrhfnew_io:
2358  case Hexagon::L4_ploadrht_rr:
2359  case Hexagon::L4_ploadrhf_rr:
2360  case Hexagon::L4_ploadrhtnew_rr:
2361  case Hexagon::L4_ploadrhfnew_rr:
2362  case Hexagon::L2_ploadrhtnew_pi:
2363  case Hexagon::L2_ploadrhfnew_pi:
2364  case Hexagon::L4_ploadrht_abs:
2365  case Hexagon::L4_ploadrhf_abs:
2366  case Hexagon::L4_ploadrhtnew_abs:
2367  case Hexagon::L4_ploadrhfnew_abs:
2368  case Hexagon::L2_loadrhgp:
2369  return true;
2370  default:
2371  return false;
2372  }
2373 }
2374 
2376  const uint64_t F = MI.getDesc().TSFlags;
2377  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2378 }
2379 
2381  switch (MI.getOpcode()) {
2382  case Hexagon::STriw_pred :
2383  case Hexagon::LDriw_pred :
2384  return true;
2385  default:
2386  return false;
2387  }
2388 }
2389 
2391  if (!MI.isBranch())
2392  return false;
2393 
2394  for (auto &Op : MI.operands())
2395  if (Op.isGlobal() || Op.isSymbol())
2396  return true;
2397  return false;
2398 }
2399 
2400 // Returns true when SU has a timing class TC1.
2402  unsigned SchedClass = MI.getDesc().getSchedClass();
2403  return is_TC1(SchedClass);
2404 }
2405 
2407  unsigned SchedClass = MI.getDesc().getSchedClass();
2408  return is_TC2(SchedClass);
2409 }
2410 
2412  unsigned SchedClass = MI.getDesc().getSchedClass();
2413  return is_TC2early(SchedClass);
2414 }
2415 
2417  unsigned SchedClass = MI.getDesc().getSchedClass();
2418  return is_TC4x(SchedClass);
2419 }
2420 
2421 // Schedule this ASAP.
2423  const MachineInstr &MI2) const {
2424  if (mayBeCurLoad(MI1)) {
2425  // if (result of SU is used in Next) return true;
2426  unsigned DstReg = MI1.getOperand(0).getReg();
2427  int N = MI2.getNumOperands();
2428  for (int I = 0; I < N; I++)
2429  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2430  return true;
2431  }
2432  if (mayBeNewStore(MI2))
2433  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2434  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2435  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2436  return true;
2437  return false;
2438 }
2439 
2441  const uint64_t V = getType(MI);
2443 }
2444 
2445 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2446 //
2447 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2448  if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
2449  VT == MVT::v32i16 || VT == MVT::v64i8) {
2450  return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
2451  Offset <= Hexagon_MEMV_AUTOINC_MAX &&
2452  (Offset & 0x3f) == 0);
2453  }
2454  // 128B
2455  if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
2456  VT == MVT::v64i16 || VT == MVT::v128i8) {
2457  return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
2458  Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
2459  (Offset & 0x7f) == 0);
2460  }
2461  if (VT == MVT::i64) {
2462  return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2463  Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2464  (Offset & 0x7) == 0);
2465  }
2466  if (VT == MVT::i32) {
2467  return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2468  Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2469  (Offset & 0x3) == 0);
2470  }
2471  if (VT == MVT::i16) {
2472  return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2473  Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2474  (Offset & 0x1) == 0);
2475  }
2476  if (VT == MVT::i8) {
2477  return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2478  Offset <= Hexagon_MEMB_AUTOINC_MAX);
2479  }
2480  llvm_unreachable("Not an auto-inc opc!");
2481 }
2482 
2483 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2484  bool Extend) const {
2485  // This function is to check whether the "Offset" is in the correct range of
2486  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2487  // inserted to calculate the final address. Due to this reason, the function
2488  // assumes that the "Offset" has correct alignment.
2489  // We used to assert if the offset was not properly aligned, however,
2490  // there are cases where a misaligned pointer recast can cause this
2491  // problem, and we need to allow for it. The front end warns of such
2492  // misaligns with respect to load size.
2493 
2494  switch (Opcode) {
2495  case Hexagon::PS_vstorerq_ai:
2496  case Hexagon::PS_vstorerw_ai:
2497  case Hexagon::PS_vstorerw_nt_ai:
2498  case Hexagon::PS_vloadrq_ai:
2499  case Hexagon::PS_vloadrw_ai:
2500  case Hexagon::PS_vloadrw_nt_ai:
2501  case Hexagon::V6_vL32b_ai:
2502  case Hexagon::V6_vS32b_ai:
2503  case Hexagon::V6_vL32b_nt_ai:
2504  case Hexagon::V6_vS32b_nt_ai:
2505  case Hexagon::V6_vL32Ub_ai:
2506  case Hexagon::V6_vS32Ub_ai:
2507  return isShiftedInt<4,6>(Offset);
2508 
2509  case Hexagon::PS_vstorerq_ai_128B:
2510  case Hexagon::PS_vstorerw_ai_128B:
2511  case Hexagon::PS_vstorerw_nt_ai_128B:
2512  case Hexagon::PS_vloadrq_ai_128B:
2513  case Hexagon::PS_vloadrw_ai_128B:
2514  case Hexagon::PS_vloadrw_nt_ai_128B:
2515  case Hexagon::V6_vL32b_ai_128B:
2516  case Hexagon::V6_vS32b_ai_128B:
2517  case Hexagon::V6_vL32b_nt_ai_128B:
2518  case Hexagon::V6_vS32b_nt_ai_128B:
2519  case Hexagon::V6_vL32Ub_ai_128B:
2520  case Hexagon::V6_vS32Ub_ai_128B:
2521  return isShiftedInt<4,7>(Offset);
2522 
2523  case Hexagon::J2_loop0i:
2524  case Hexagon::J2_loop1i:
2525  return isUInt<10>(Offset);
2526 
2527  case Hexagon::S4_storeirb_io:
2528  case Hexagon::S4_storeirbt_io:
2529  case Hexagon::S4_storeirbf_io:
2530  return isUInt<6>(Offset);
2531 
2532  case Hexagon::S4_storeirh_io:
2533  case Hexagon::S4_storeirht_io:
2534  case Hexagon::S4_storeirhf_io:
2535  return isShiftedUInt<6,1>(Offset);
2536 
2537  case Hexagon::S4_storeiri_io:
2538  case Hexagon::S4_storeirit_io:
2539  case Hexagon::S4_storeirif_io:
2540  return isShiftedUInt<6,2>(Offset);
2541  }
2542 
2543  if (Extend)
2544  return true;
2545 
2546  switch (Opcode) {
2547  case Hexagon::L2_loadri_io:
2548  case Hexagon::S2_storeri_io:
2549  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2550  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2551 
2552  case Hexagon::L2_loadrd_io:
2553  case Hexagon::S2_storerd_io:
2554  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2555  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2556 
2557  case Hexagon::L2_loadrh_io:
2558  case Hexagon::L2_loadruh_io:
2559  case Hexagon::S2_storerh_io:
2560  case Hexagon::S2_storerf_io:
2561  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2562  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2563 
2564  case Hexagon::L2_loadrb_io:
2565  case Hexagon::L2_loadrub_io:
2566  case Hexagon::S2_storerb_io:
2567  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2568  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2569 
2570  case Hexagon::A2_addi:
2571  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2572  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2573 
2574  case Hexagon::L4_iadd_memopw_io :
2575  case Hexagon::L4_isub_memopw_io :
2576  case Hexagon::L4_add_memopw_io :
2577  case Hexagon::L4_sub_memopw_io :
2578  case Hexagon::L4_and_memopw_io :
2579  case Hexagon::L4_or_memopw_io :
2580  return (0 <= Offset && Offset <= 255);
2581 
2582  case Hexagon::L4_iadd_memoph_io :
2583  case Hexagon::L4_isub_memoph_io :
2584  case Hexagon::L4_add_memoph_io :
2585  case Hexagon::L4_sub_memoph_io :
2586  case Hexagon::L4_and_memoph_io :
2587  case Hexagon::L4_or_memoph_io :
2588  return (0 <= Offset && Offset <= 127);
2589 
2590  case Hexagon::L4_iadd_memopb_io :
2591  case Hexagon::L4_isub_memopb_io :
2592  case Hexagon::L4_add_memopb_io :
2593  case Hexagon::L4_sub_memopb_io :
2594  case Hexagon::L4_and_memopb_io :
2595  case Hexagon::L4_or_memopb_io :
2596  return (0 <= Offset && Offset <= 63);
2597 
2598  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2599  // any size. Later pass knows how to handle it.
2600  case Hexagon::STriw_pred:
2601  case Hexagon::LDriw_pred:
2602  case Hexagon::STriw_mod:
2603  case Hexagon::LDriw_mod:
2604  return true;
2605 
2606  case Hexagon::PS_fi:
2607  case Hexagon::PS_fia:
2608  case Hexagon::INLINEASM:
2609  return true;
2610 
2611  case Hexagon::L2_ploadrbt_io:
2612  case Hexagon::L2_ploadrbf_io:
2613  case Hexagon::L2_ploadrubt_io:
2614  case Hexagon::L2_ploadrubf_io:
2615  case Hexagon::S2_pstorerbt_io:
2616  case Hexagon::S2_pstorerbf_io:
2617  return isUInt<6>(Offset);
2618 
2619  case Hexagon::L2_ploadrht_io:
2620  case Hexagon::L2_ploadrhf_io:
2621  case Hexagon::L2_ploadruht_io:
2622  case Hexagon::L2_ploadruhf_io:
2623  case Hexagon::S2_pstorerht_io:
2624  case Hexagon::S2_pstorerhf_io:
2625  return isShiftedUInt<6,1>(Offset);
2626 
2627  case Hexagon::L2_ploadrit_io:
2628  case Hexagon::L2_ploadrif_io:
2629  case Hexagon::S2_pstorerit_io:
2630  case Hexagon::S2_pstorerif_io:
2631  return isShiftedUInt<6,2>(Offset);
2632 
2633  case Hexagon::L2_ploadrdt_io:
2634  case Hexagon::L2_ploadrdf_io:
2635  case Hexagon::S2_pstorerdt_io:
2636  case Hexagon::S2_pstorerdf_io:
2637  return isShiftedUInt<6,3>(Offset);
2638  } // switch
2639 
2640  llvm_unreachable("No offset range is defined for this opcode. "
2641  "Please define it in the above switch statement!");
2642 }
2643 
2645  return isHVXVec(MI) && isAccumulator(MI);
2646 }
2647 
2649  const uint64_t F = get(MI.getOpcode()).TSFlags;
2650  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2651  return
2652  V == HexagonII::TypeCVI_VA ||
2654 }
2655 
2657  const MachineInstr &ConsMI) const {
2658  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2659  return true;
2660 
2661  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2662  return true;
2663 
2664  if (mayBeNewStore(ConsMI))
2665  return true;
2666 
2667  return false;
2668 }
2669 
2671  switch (MI.getOpcode()) {
2672  // Byte
2673  case Hexagon::L2_loadrub_io:
2674  case Hexagon::L4_loadrub_ur:
2675  case Hexagon::L4_loadrub_ap:
2676  case Hexagon::L2_loadrub_pr:
2677  case Hexagon::L2_loadrub_pbr:
2678  case Hexagon::L2_loadrub_pi:
2679  case Hexagon::L2_loadrub_pci:
2680  case Hexagon::L2_loadrub_pcr:
2681  case Hexagon::L2_loadbzw2_io:
2682  case Hexagon::L4_loadbzw2_ur:
2683  case Hexagon::L4_loadbzw2_ap:
2684  case Hexagon::L2_loadbzw2_pr:
2685  case Hexagon::L2_loadbzw2_pbr:
2686  case Hexagon::L2_loadbzw2_pi:
2687  case Hexagon::L2_loadbzw2_pci:
2688  case Hexagon::L2_loadbzw2_pcr:
2689  case Hexagon::L2_loadbzw4_io:
2690  case Hexagon::L4_loadbzw4_ur:
2691  case Hexagon::L4_loadbzw4_ap:
2692  case Hexagon::L2_loadbzw4_pr:
2693  case Hexagon::L2_loadbzw4_pbr:
2694  case Hexagon::L2_loadbzw4_pi:
2695  case Hexagon::L2_loadbzw4_pci:
2696  case Hexagon::L2_loadbzw4_pcr:
2697  case Hexagon::L4_loadrub_rr:
2698  case Hexagon::L2_ploadrubt_io:
2699  case Hexagon::L2_ploadrubt_pi:
2700  case Hexagon::L2_ploadrubf_io:
2701  case Hexagon::L2_ploadrubf_pi:
2702  case Hexagon::L2_ploadrubtnew_io:
2703  case Hexagon::L2_ploadrubfnew_io:
2704  case Hexagon::L4_ploadrubt_rr:
2705  case Hexagon::L4_ploadrubf_rr:
2706  case Hexagon::L4_ploadrubtnew_rr:
2707  case Hexagon::L4_ploadrubfnew_rr:
2708  case Hexagon::L2_ploadrubtnew_pi:
2709  case Hexagon::L2_ploadrubfnew_pi:
2710  case Hexagon::L4_ploadrubt_abs:
2711  case Hexagon::L4_ploadrubf_abs:
2712  case Hexagon::L4_ploadrubtnew_abs:
2713  case Hexagon::L4_ploadrubfnew_abs:
2714  case Hexagon::L2_loadrubgp:
2715  // Half
2716  case Hexagon::L2_loadruh_io:
2717  case Hexagon::L4_loadruh_ur:
2718  case Hexagon::L4_loadruh_ap:
2719  case Hexagon::L2_loadruh_pr:
2720  case Hexagon::L2_loadruh_pbr:
2721  case Hexagon::L2_loadruh_pi:
2722  case Hexagon::L2_loadruh_pci:
2723  case Hexagon::L2_loadruh_pcr:
2724  case Hexagon::L4_loadruh_rr:
2725  case Hexagon::L2_ploadruht_io:
2726  case Hexagon::L2_ploadruht_pi:
2727  case Hexagon::L2_ploadruhf_io:
2728  case Hexagon::L2_ploadruhf_pi:
2729  case Hexagon::L2_ploadruhtnew_io:
2730  case Hexagon::L2_ploadruhfnew_io:
2731  case Hexagon::L4_ploadruht_rr:
2732  case Hexagon::L4_ploadruhf_rr:
2733  case Hexagon::L4_ploadruhtnew_rr:
2734  case Hexagon::L4_ploadruhfnew_rr:
2735  case Hexagon::L2_ploadruhtnew_pi:
2736  case Hexagon::L2_ploadruhfnew_pi:
2737  case Hexagon::L4_ploadruht_abs:
2738  case Hexagon::L4_ploadruhf_abs:
2739  case Hexagon::L4_ploadruhtnew_abs:
2740  case Hexagon::L4_ploadruhfnew_abs:
2741  case Hexagon::L2_loadruhgp:
2742  return true;
2743  default:
2744  return false;
2745  }
2746 }
2747 
2748 // Add latency to instruction.
2750  const MachineInstr &MI2) const {
2751  if (isHVXVec(MI1) && isHVXVec(MI2))
2752  if (!isVecUsableNextPacket(MI1, MI2))
2753  return true;
2754  return false;
2755 }
2756 
2757 /// \brief Get the base register and byte offset of a load/store instr.
2759  unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2760  const {
2761  unsigned AccessSize = 0;
2762  int OffsetVal = 0;
2763  BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2764  Offset = OffsetVal;
2765  return BaseReg != 0;
2766 }
2767 
2768 /// \brief Can these instructions execute at the same time in a bundle.
2770  const MachineInstr &Second) const {
2771  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2772  const MachineOperand &Op = Second.getOperand(0);
2773  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2774  return true;
2775  }
2776  if (DisableNVSchedule)
2777  return false;
2778  if (mayBeNewStore(Second)) {
2779  // Make sure the definition of the first instruction is the value being
2780  // stored.
2781  const MachineOperand &Stored =
2782  Second.getOperand(Second.getNumOperands() - 1);
2783  if (!Stored.isReg())
2784  return false;
2785  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2786  const MachineOperand &Op = First.getOperand(i);
2787  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2788  return true;
2789  }
2790  }
2791  return false;
2792 }
2793 
2795  unsigned Opc = CallMI.getOpcode();
2796  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2797 }
2798 
2800  for (auto &I : *B)
2801  if (I.isEHLabel())
2802  return true;
2803  return false;
2804 }
2805 
2806 // Returns true if an instruction can be converted into a non-extended
2807 // equivalent instruction.
2809  short NonExtOpcode;
2810  // Check if the instruction has a register form that uses register in place
2811  // of the extended operand, if so return that as the non-extended form.
2812  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2813  return true;
2814 
2815  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2816  // Check addressing mode and retrieve non-ext equivalent instruction.
2817 
2818  switch (getAddrMode(MI)) {
2819  case HexagonII::Absolute :
2820  // Load/store with absolute addressing mode can be converted into
2821  // base+offset mode.
2822  NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode());
2823  break;
2825  // Load/store with base+offset addressing mode can be converted into
2826  // base+register offset addressing mode. However left shift operand should
2827  // be set to 0.
2828  NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode());
2829  break;
2831  NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode());
2832  break;
2833  default:
2834  return false;
2835  }
2836  if (NonExtOpcode < 0)
2837  return false;
2838  return true;
2839  }
2840  return false;
2841 }
2842 
2844  return Hexagon::getRealHWInstr(MI.getOpcode(),
2845  Hexagon::InstrType_Pseudo) >= 0;
2846 }
2847 
2849  const {
2851  while (I != E) {
2852  if (I->isBarrier())
2853  return true;
2854  ++I;
2855  }
2856  return false;
2857 }
2858 
2859 // Returns true, if a LD insn can be promoted to a cur load.
2861  auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
2862  const uint64_t F = MI.getDesc().TSFlags;
2864  HST.hasV60TOps();
2865 }
2866 
2867 // Returns true, if a ST insn can be promoted to a new-value store.
2869  const uint64_t F = MI.getDesc().TSFlags;
2871 }
2872 
2874  const MachineInstr &ConsMI) const {
2875  // There is no stall when ProdMI is not a V60 vector.
2876  if (!isHVXVec(ProdMI))
2877  return false;
2878 
2879  // There is no stall when ProdMI and ConsMI are not dependent.
2880  if (!isDependent(ProdMI, ConsMI))
2881  return false;
2882 
2883  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
2884  // are scheduled in consecutive packets.
2885  if (isVecUsableNextPacket(ProdMI, ConsMI))
2886  return false;
2887 
2888  return true;
2889 }
2890 
2893  // There is no stall when I is not a V60 vector.
2894  if (!isHVXVec(MI))
2895  return false;
2896 
2898  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
2899 
2900  if (!(*MII).isBundle()) {
2901  const MachineInstr &J = *MII;
2902  return producesStall(J, MI);
2903  }
2904 
2905  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
2906  const MachineInstr &J = *MII;
2907  if (producesStall(J, MI))
2908  return true;
2909  }
2910  return false;
2911 }
2912 
2914  unsigned PredReg) const {
2915  for (const MachineOperand &MO : MI.operands()) {
2916  // Predicate register must be explicitly defined.
2917  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
2918  return false;
2919  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
2920  return false;
2921  }
2922 
2923  // Hexagon Programmer's Reference says that decbin, memw_locked, and
2924  // memd_locked cannot be used as .new as well,
2925  // but we don't seem to have these instructions defined.
2926  return MI.getOpcode() != Hexagon::A4_tlbmatch;
2927 }
2928 
2929 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
2930  return Opcode == Hexagon::J2_jumpt ||
2931  Opcode == Hexagon::J2_jumptpt ||
2932  Opcode == Hexagon::J2_jumpf ||
2933  Opcode == Hexagon::J2_jumpfpt ||
2934  Opcode == Hexagon::J2_jumptnew ||
2935  Opcode == Hexagon::J2_jumpfnew ||
2936  Opcode == Hexagon::J2_jumptnewpt ||
2937  Opcode == Hexagon::J2_jumpfnewpt;
2938 }
2939 
2941  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
2942  return false;
2943  return !isPredicatedTrue(Cond[0].getImm());
2944 }
2945 
2947  return Hexagon::getAbsoluteForm(MI.getOpcode());
2948 }
2949 
2951  const uint64_t F = MI.getDesc().TSFlags;
2953 }
2954 
2955 // Returns the base register in a memory access (load/store). The offset is
2956 // returned in Offset and the access size is returned in AccessSize.
2957 // If the base register has a subregister or the offset field does not contain
2958 // an immediate value, return 0.
2960  int &Offset, unsigned &AccessSize) const {
2961  // Return if it is not a base+offset type instruction or a MemOp.
2964  !isMemOp(MI) && !isPostIncrement(MI))
2965  return 0;
2966 
2967  // Since it is a memory access instruction, getMemAccessSize() should never
2968  // return 0.
2969  assert (getMemAccessSize(MI) &&
2970  "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
2971 
2972  // Return Values of getMemAccessSize() are
2973  // 0 - Checked in the assert above.
2974  // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
2975  // MemAccessSize is represented as 1+log2(N) where N is size in bits.
2976  AccessSize = (1U << (getMemAccessSize(MI) - 1));
2977 
2978  unsigned BasePos = 0, OffsetPos = 0;
2979  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2980  return 0;
2981 
2982  // Post increment updates its EA after the mem access,
2983  // so we need to treat its offset as zero.
2984  if (isPostIncrement(MI)) {
2985  Offset = 0;
2986  } else {
2987  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2988  if (!OffsetOp.isImm())
2989  return 0;
2990  Offset = OffsetOp.getImm();
2991  }
2992 
2993  const MachineOperand &BaseOp = MI.getOperand(BasePos);
2994  if (BaseOp.getSubReg() != 0)
2995  return 0;
2996  return BaseOp.getReg();
2997 }
2998 
2999 /// Return the position of the base and offset operands for this instruction.
3001  unsigned &BasePos, unsigned &OffsetPos) const {
3002  // Deal with memops first.
3003  if (isMemOp(MI)) {
3004  BasePos = 0;
3005  OffsetPos = 1;
3006  } else if (MI.mayStore()) {
3007  BasePos = 0;
3008  OffsetPos = 1;
3009  } else if (MI.mayLoad()) {
3010  BasePos = 1;
3011  OffsetPos = 2;
3012  } else
3013  return false;
3014 
3015  if (isPredicated(MI)) {
3016  BasePos++;
3017  OffsetPos++;
3018  }
3019  if (isPostIncrement(MI)) {
3020  BasePos++;
3021  OffsetPos++;
3022  }
3023 
3024  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3025  return false;
3026 
3027  return true;
3028 }
3029 
3030 // Inserts branching instructions in reverse order of their occurrence.
3031 // e.g. jump_t t1 (i1)
3032 // jump t2 (i2)
3033 // Jumpers = {i2, i1}
3035  MachineBasicBlock& MBB) const {
3037  // If the block has no terminators, it just falls into the block after it.
3039  if (I == MBB.instr_begin())
3040  return Jumpers;
3041 
3042  // A basic block may looks like this:
3043  //
3044  // [ insn
3045  // EH_LABEL
3046  // insn
3047  // insn
3048  // insn
3049  // EH_LABEL
3050  // insn ]
3051  //
3052  // It has two succs but does not have a terminator
3053  // Don't know how to handle it.
3054  do {
3055  --I;
3056  if (I->isEHLabel())
3057  return Jumpers;
3058  } while (I != MBB.instr_begin());
3059 
3060  I = MBB.instr_end();
3061  --I;
3062 
3063  while (I->isDebugValue()) {
3064  if (I == MBB.instr_begin())
3065  return Jumpers;
3066  --I;
3067  }
3068  if (!isUnpredicatedTerminator(*I))
3069  return Jumpers;
3070 
3071  // Get the last instruction in the block.
3072  MachineInstr *LastInst = &*I;
3073  Jumpers.push_back(LastInst);
3074  MachineInstr *SecondLastInst = nullptr;
3075  // Find one more terminator if present.
3076  do {
3077  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3078  if (!SecondLastInst) {
3079  SecondLastInst = &*I;
3080  Jumpers.push_back(SecondLastInst);
3081  } else // This is a third branch.
3082  return Jumpers;
3083  }
3084  if (I == MBB.instr_begin())
3085  break;
3086  --I;
3087  } while (true);
3088  return Jumpers;
3089 }
3090 
3091 short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
3092  if (Opcode < 0)
3093  return -1;
3094  return Hexagon::getBaseWithLongOffset(Opcode);
3095 }
3096 
3098  return Hexagon::getBaseWithLongOffset(MI.getOpcode());
3099 }
3100 
3102  return Hexagon::getBaseWithRegOffset(MI.getOpcode());
3103 }
3104 
3105 // Returns Operand Index for the constant extended instruction.
3107  const uint64_t F = MI.getDesc().TSFlags;
3109 }
3110 
3111 // See if instruction could potentially be a duplex candidate.
3112 // If so, return its group. Zero otherwise.
3114  const MachineInstr &MI) const {
3115  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3116 
3117  switch (MI.getOpcode()) {
3118  default:
3119  return HexagonII::HCG_None;
3120  //
3121  // Compound pairs.
3122  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3123  // "Rd16=#U6 ; jump #r9:2"
3124  // "Rd16=Rs16 ; jump #r9:2"
3125  //
3126  case Hexagon::C2_cmpeq:
3127  case Hexagon::C2_cmpgt:
3128  case Hexagon::C2_cmpgtu:
3129  DstReg = MI.getOperand(0).getReg();
3130  Src1Reg = MI.getOperand(1).getReg();
3131  Src2Reg = MI.getOperand(2).getReg();
3132  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3133  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3134  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3135  return HexagonII::HCG_A;
3136  break;
3137  case Hexagon::C2_cmpeqi:
3138  case Hexagon::C2_cmpgti:
3139  case Hexagon::C2_cmpgtui:
3140  // P0 = cmp.eq(Rs,#u2)
3141  DstReg = MI.getOperand(0).getReg();
3142  SrcReg = MI.getOperand(1).getReg();
3143  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3144  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3145  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3146  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3147  (MI.getOperand(2).getImm() == -1)))
3148  return HexagonII::HCG_A;
3149  break;
3150  case Hexagon::A2_tfr:
3151  // Rd = Rs
3152  DstReg = MI.getOperand(0).getReg();
3153  SrcReg = MI.getOperand(1).getReg();
3154  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3155  return HexagonII::HCG_A;
3156  break;
3157  case Hexagon::A2_tfrsi:
3158  // Rd = #u6
3159  // Do not test for #u6 size since the const is getting extended
3160  // regardless and compound could be formed.
3161  DstReg = MI.getOperand(0).getReg();
3162  if (isIntRegForSubInst(DstReg))
3163  return HexagonII::HCG_A;
3164  break;
3165  case Hexagon::S2_tstbit_i:
3166  DstReg = MI.getOperand(0).getReg();
3167  Src1Reg = MI.getOperand(1).getReg();
3168  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3169  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3170  MI.getOperand(2).isImm() &&
3171  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3172  return HexagonII::HCG_A;
3173  break;
3174  // The fact that .new form is used pretty much guarantees
3175  // that predicate register will match. Nevertheless,
3176  // there could be some false positives without additional
3177  // checking.
3178  case Hexagon::J2_jumptnew:
3179  case Hexagon::J2_jumpfnew:
3180  case Hexagon::J2_jumptnewpt:
3181  case Hexagon::J2_jumpfnewpt:
3182  Src1Reg = MI.getOperand(0).getReg();
3183  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3184  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3185  return HexagonII::HCG_B;
3186  break;
3187  // Transfer and jump:
3188  // Rd=#U6 ; jump #r9:2
3189  // Rd=Rs ; jump #r9:2
3190  // Do not test for jump range here.
3191  case Hexagon::J2_jump:
3192  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3193  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3194  return HexagonII::HCG_C;
3195  break;
3196  }
3197 
3198  return HexagonII::HCG_None;
3199 }
3200 
3201 // Returns -1 when there is no opcode found.
3203  const MachineInstr &GB) const {
3206  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3207  (GB.getOpcode() != Hexagon::J2_jumptnew))
3208  return -1;
3209  unsigned DestReg = GA.getOperand(0).getReg();
3210  if (!GB.readsRegister(DestReg))
3211  return -1;
3212  if (DestReg == Hexagon::P0)
3213  return Hexagon::J4_cmpeqi_tp0_jump_nt;
3214  if (DestReg == Hexagon::P1)
3215  return Hexagon::J4_cmpeqi_tp1_jump_nt;
3216  return -1;
3217 }
3218 
3219 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3220  enum Hexagon::PredSense inPredSense;
3221  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3222  Hexagon::PredSense_true;
3223  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3224  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3225  return CondOpcode;
3226 
3227  llvm_unreachable("Unexpected predicable instruction");
3228 }
3229 
3230 // Return the cur value instruction for a given store.
3232  switch (MI.getOpcode()) {
3233  default: llvm_unreachable("Unknown .cur type");
3234  case Hexagon::V6_vL32b_pi:
3235  return Hexagon::V6_vL32b_cur_pi;
3236  case Hexagon::V6_vL32b_ai:
3237  return Hexagon::V6_vL32b_cur_ai;
3238  case Hexagon::V6_vL32b_nt_pi:
3239  return Hexagon::V6_vL32b_nt_cur_pi;
3240  case Hexagon::V6_vL32b_nt_ai:
3241  return Hexagon::V6_vL32b_nt_cur_ai;
3242  //128B
3243  case Hexagon::V6_vL32b_pi_128B:
3244  return Hexagon::V6_vL32b_cur_pi_128B;
3245  case Hexagon::V6_vL32b_ai_128B:
3246  return Hexagon::V6_vL32b_cur_ai_128B;
3247  case Hexagon::V6_vL32b_nt_pi_128B:
3248  return Hexagon::V6_vL32b_nt_cur_pi_128B;
3249  case Hexagon::V6_vL32b_nt_ai_128B:
3250  return Hexagon::V6_vL32b_nt_cur_ai_128B;
3251  }
3252  return 0;
3253 }
3254 
3255 // Return the regular version of the .cur instruction.
3257  switch (MI.getOpcode()) {
3258  default: llvm_unreachable("Unknown .cur type");
3259  case Hexagon::V6_vL32b_cur_pi:
3260  return Hexagon::V6_vL32b_pi;
3261  case Hexagon::V6_vL32b_cur_ai:
3262  return Hexagon::V6_vL32b_ai;
3263  case Hexagon::V6_vL32b_nt_cur_pi:
3264  return Hexagon::V6_vL32b_nt_pi;
3265  case Hexagon::V6_vL32b_nt_cur_ai:
3266  return Hexagon::V6_vL32b_nt_ai;
3267  //128B
3268  case Hexagon::V6_vL32b_cur_pi_128B:
3269  return Hexagon::V6_vL32b_pi_128B;
3270  case Hexagon::V6_vL32b_cur_ai_128B:
3271  return Hexagon::V6_vL32b_ai_128B;
3272  case Hexagon::V6_vL32b_nt_cur_pi_128B:
3273  return Hexagon::V6_vL32b_nt_pi_128B;
3274  case Hexagon::V6_vL32b_nt_cur_ai_128B:
3275  return Hexagon::V6_vL32b_nt_ai_128B;
3276  }
3277  return 0;
3278 }
3279 
3280 
3281 // The diagram below shows the steps involved in the conversion of a predicated
3282 // store instruction to its .new predicated new-value form.
3283 //
3284 // Note: It doesn't include conditional new-value stores as they can't be
3285 // converted to .new predicate.
3286 //
3287 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3288 // ^ ^
3289 // / \ (not OK. it will cause new-value store to be
3290 // / X conditional on p0.new while R2 producer is
3291 // / \ on p0)
3292 // / \.
3293 // p.new store p.old NV store
3294 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3295 // ^ ^
3296 // \ /
3297 // \ /
3298 // \ /
3299 // p.old store
3300 // [if (p0)memw(R0+#0)=R2]
3301 //
3302 // The following set of instructions further explains the scenario where
3303 // conditional new-value store becomes invalid when promoted to .new predicate
3304 // form.
3305 //
3306 // { 1) if (p0) r0 = add(r1, r2)
3307 // 2) p0 = cmp.eq(r3, #0) }
3308 //
3309 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3310 // the first two instructions because in instr 1, r0 is conditional on old value
3311 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3312 // is not valid for new-value stores.
3313 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3314 // from the "Conditional Store" list. Because a predicated new value store
3315 // would NOT be promoted to a double dot new store. See diagram below:
3316 // This function returns yes for those stores that are predicated but not
3317 // yet promoted to predicate dot new instructions.
3318 //
3319 // +---------------------+
3320 // /-----| if (p0) memw(..)=r0 |---------\~
3321 // || +---------------------+ ||
3322 // promote || /\ /\ || promote
3323 // || /||\ /||\ ||
3324 // \||/ demote || \||/
3325 // \/ || || \/
3326 // +-------------------------+ || +-------------------------+
3327 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3328 // +-------------------------+ || +-------------------------+
3329 // || || ||
3330 // || demote \||/
3331 // promote || \/ NOT possible
3332 // || || /\~
3333 // \||/ || /||\~
3334 // \/ || ||
3335 // +-----------------------------+
3336 // | if (p0.new) memw(..)=r0.new |
3337 // +-----------------------------+
3338 // Double Dot New Store
3339 //
3340 // Returns the most basic instruction for the .new predicated instructions and
3341 // new-value stores.
3342 // For example, all of the following instructions will be converted back to the
3343 // same instruction:
3344 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3345 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3346 // 3) if (p0.new) memw(R0+#0) = R1 --->
3347 //
3348 // To understand the translation of instruction 1 to its original form, consider
3349 // a packet with 3 instructions.
3350 // { p0 = cmp.eq(R0,R1)
3351 // if (p0.new) R2 = add(R3, R4)
3352 // R5 = add (R3, R1)
3353 // }
3354 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3355 //
3356 // This instruction can be part of the previous packet only if both p0 and R2
3357 // are promoted to .new values. This promotion happens in steps, first
3358 // predicate register is promoted to .new and in the next iteration R2 is
3359 // promoted. Therefore, in case of dependence check failure (due to R5) during
3360 // next iteration, it should be converted back to its most basic form.
3361 
3362 // Return the new value instruction for a given store.
3364  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3365  if (NVOpcode >= 0) // Valid new-value store instruction.
3366  return NVOpcode;
3367 
3368  switch (MI.getOpcode()) {
3369  default:
3370  llvm::report_fatal_error(std::string("Unknown .new type: ") +
3371  std::to_string(MI.getOpcode()).c_str());
3372  case Hexagon::S4_storerb_ur:
3373  return Hexagon::S4_storerbnew_ur;
3374 
3375  case Hexagon::S2_storerb_pci:
3376  return Hexagon::S2_storerb_pci;
3377 
3378  case Hexagon::S2_storeri_pci:
3379  return Hexagon::S2_storeri_pci;
3380 
3381  case Hexagon::S2_storerh_pci:
3382  return Hexagon::S2_storerh_pci;
3383 
3384  case Hexagon::S2_storerd_pci:
3385  return Hexagon::S2_storerd_pci;
3386 
3387  case Hexagon::S2_storerf_pci:
3388  return Hexagon::S2_storerf_pci;
3389 
3390  case Hexagon::V6_vS32b_ai:
3391  return Hexagon::V6_vS32b_new_ai;
3392 
3393  case Hexagon::V6_vS32b_pi:
3394  return Hexagon::V6_vS32b_new_pi;
3395 
3396  // 128B
3397  case Hexagon::V6_vS32b_ai_128B:
3398  return Hexagon::V6_vS32b_new_ai_128B;
3399 
3400  case Hexagon::V6_vS32b_pi_128B:
3401  return Hexagon::V6_vS32b_new_pi_128B;
3402  }
3403  return 0;
3404 }
3405 
3406 // Returns the opcode to use when converting MI, which is a conditional jump,
3407 // into a conditional instruction which uses the .new value of the predicate.
3408 // We also use branch probabilities to add a hint to the jump.
3409 // If MBPI is null, all edges will be treated as equally likely for the
3410 // purposes of establishing a predication hint.
3412  const MachineBranchProbabilityInfo *MBPI) const {
3413  // We assume that block can have at most two successors.
3414  const MachineBasicBlock *Src = MI.getParent();
3415  const MachineOperand &BrTarget = MI.getOperand(1);
3416  bool Taken = false;
3417  const BranchProbability OneHalf(1, 2);
3418 
3419  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3420  const MachineBasicBlock *Dst) {
3421  if (MBPI)
3422  return MBPI->getEdgeProbability(Src, Dst);
3423  return BranchProbability(1, Src->succ_size());
3424  };
3425 
3426  if (BrTarget.isMBB()) {
3427  const MachineBasicBlock *Dst = BrTarget.getMBB();
3428  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3429  } else {
3430  // The branch target is not a basic block (most likely a function).
3431  // Since BPI only gives probabilities for targets that are basic blocks,
3432  // try to identify another target of this branch (potentially a fall-
3433  // -through) and check the probability of that target.
3434  //
3435  // The only handled branch combinations are:
3436  // - one conditional branch,
3437  // - one conditional branch followed by one unconditional branch.
3438  // Otherwise, assume not-taken.
3440  const MachineBasicBlock &B = *MI.getParent();
3441  bool SawCond = false, Bad = false;
3442  for (const MachineInstr &I : B) {
3443  if (!I.isBranch())
3444  continue;
3445  if (I.isConditionalBranch()) {
3446  SawCond = true;
3447  if (&I != &MI) {
3448  Bad = true;
3449  break;
3450  }
3451  }
3452  if (I.isUnconditionalBranch() && !SawCond) {
3453  Bad = true;
3454  break;
3455  }
3456  }
3457  if (!Bad) {
3459  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3460  if (NextIt == B.instr_end()) {
3461  // If this branch is the last, look for the fall-through block.
3462  for (const MachineBasicBlock *SB : B.successors()) {
3463  if (!B.isLayoutSuccessor(SB))
3464  continue;
3465  Taken = getEdgeProbability(Src, SB) < OneHalf;
3466  break;
3467  }
3468  } else {
3469  assert(NextIt->isUnconditionalBranch());
3470  // Find the first MBB operand and assume it's the target.
3471  const MachineBasicBlock *BT = nullptr;
3472  for (const MachineOperand &Op : NextIt->operands()) {
3473  if (!Op.isMBB())
3474  continue;
3475  BT = Op.getMBB();
3476  break;
3477  }
3478  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3479  }
3480  } // if (!Bad)
3481  }
3482 
3483  // The Taken flag should be set to something reasonable by this point.
3484 
3485  switch (MI.getOpcode()) {
3486  case Hexagon::J2_jumpt:
3487  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3488  case Hexagon::J2_jumpf:
3489  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3490 
3491  default:
3492  llvm_unreachable("Unexpected jump instruction.");
3493  }
3494 }
3495 
3496 // Return .new predicate version for an instruction.
3498  const MachineBranchProbabilityInfo *MBPI) const {
3499  switch (MI.getOpcode()) {
3500  // Condtional Jumps
3501  case Hexagon::J2_jumpt:
3502  case Hexagon::J2_jumpf:
3503  return getDotNewPredJumpOp(MI, MBPI);
3504  }
3505 
3506  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3507  if (NewOpcode >= 0)
3508  return NewOpcode;
3509  return 0;
3510 }
3511 
3513  const MachineFunction &MF = *MI.getParent()->getParent();
3514  const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
3515  int NewOp = MI.getOpcode();
3516  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3517  NewOp = Hexagon::getPredOldOpcode(NewOp);
3518  // All Hexagon architectures have prediction bits on dot-new branches,
3519  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3520  // to pick the right opcode when converting back to dot-old.
3521  if (!HST.getFeatureBits()[Hexagon::ArchV60]) {
3522  switch (NewOp) {
3523  case Hexagon::J2_jumptpt:
3524  NewOp = Hexagon::J2_jumpt;
3525  break;
3526  case Hexagon::J2_jumpfpt:
3527  NewOp = Hexagon::J2_jumpf;
3528  break;
3529  case Hexagon::J2_jumprtpt:
3530  NewOp = Hexagon::J2_jumprt;
3531  break;
3532  case Hexagon::J2_jumprfpt:
3533  NewOp = Hexagon::J2_jumprf;
3534  break;
3535  }
3536  }
3537  assert(NewOp >= 0 &&
3538  "Couldn't change predicate new instruction to its old form.");
3539  }
3540 
3541  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3542  NewOp = Hexagon::getNonNVStore(NewOp);
3543  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3544  }
3545 
3546  if (HST.hasV60TOps())
3547  return NewOp;
3548 
3549  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3550  switch (NewOp) {
3551  case Hexagon::J2_jumpfpt:
3552  return Hexagon::J2_jumpf;
3553  case Hexagon::J2_jumptpt:
3554  return Hexagon::J2_jumpt;
3555  case Hexagon::J2_jumprfpt:
3556  return Hexagon::J2_jumprf;
3557  case Hexagon::J2_jumprtpt:
3558  return Hexagon::J2_jumprt;
3559  }
3560  return NewOp;
3561 }
3562 
3563 // See if instruction could potentially be a duplex candidate.
3564 // If so, return its group. Zero otherwise.
3566  const MachineInstr &MI) const {
3567  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3568  auto &HRI = getRegisterInfo();
3569 
3570  switch (MI.getOpcode()) {
3571  default:
3572  return HexagonII::HSIG_None;
3573  //
3574  // Group L1:
3575  //
3576  // Rd = memw(Rs+#u4:2)
3577  // Rd = memub(Rs+#u4:0)
3578  case Hexagon::L2_loadri_io:
3579  DstReg = MI.getOperand(0).getReg();
3580  SrcReg = MI.getOperand(1).getReg();
3581  // Special case this one from Group L2.
3582  // Rd = memw(r29+#u5:2)
3583  if (isIntRegForSubInst(DstReg)) {
3584  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3585  HRI.getStackRegister() == SrcReg &&
3586  MI.getOperand(2).isImm() &&
3587  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3588  return HexagonII::HSIG_L2;
3589  // Rd = memw(Rs+#u4:2)
3590  if (isIntRegForSubInst(SrcReg) &&
3591  (MI.getOperand(2).isImm() &&
3592  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3593  return HexagonII::HSIG_L1;
3594  }
3595  break;
3596  case Hexagon::L2_loadrub_io:
3597  // Rd = memub(Rs+#u4:0)
3598  DstReg = MI.getOperand(0).getReg();
3599  SrcReg = MI.getOperand(1).getReg();
3600  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3601  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3602  return HexagonII::HSIG_L1;
3603  break;
3604  //
3605  // Group L2:
3606  //
3607  // Rd = memh/memuh(Rs+#u3:1)
3608  // Rd = memb(Rs+#u3:0)
3609  // Rd = memw(r29+#u5:2) - Handled above.
3610  // Rdd = memd(r29+#u5:3)
3611  // deallocframe
3612  // [if ([!]p0[.new])] dealloc_return
3613  // [if ([!]p0[.new])] jumpr r31
3614  case Hexagon::L2_loadrh_io:
3615  case Hexagon::L2_loadruh_io:
3616  // Rd = memh/memuh(Rs+#u3:1)
3617  DstReg = MI.getOperand(0).getReg();
3618  SrcReg = MI.getOperand(1).getReg();
3619  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3620  MI.getOperand(2).isImm() &&
3621  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3622  return HexagonII::HSIG_L2;
3623  break;
3624  case Hexagon::L2_loadrb_io:
3625  // Rd = memb(Rs+#u3:0)
3626  DstReg = MI.getOperand(0).getReg();
3627  SrcReg = MI.getOperand(1).getReg();
3628  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3629  MI.getOperand(2).isImm() &&
3630  isUInt<3>(MI.getOperand(2).getImm()))
3631  return HexagonII::HSIG_L2;
3632  break;
3633  case Hexagon::L2_loadrd_io:
3634  // Rdd = memd(r29+#u5:3)
3635  DstReg = MI.getOperand(0).getReg();
3636  SrcReg = MI.getOperand(1).getReg();
3637  if (isDblRegForSubInst(DstReg, HRI) &&
3638  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3639  HRI.getStackRegister() == SrcReg &&
3640  MI.getOperand(2).isImm() &&
3641  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3642  return HexagonII::HSIG_L2;
3643  break;
3644  // dealloc_return is not documented in Hexagon Manual, but marked
3645  // with A_SUBINSN attribute in iset_v4classic.py.
3646  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3647  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3648  case Hexagon::L4_return:
3649  case Hexagon::L2_deallocframe:
3650  return HexagonII::HSIG_L2;
3651  case Hexagon::EH_RETURN_JMPR:
3652  case Hexagon::PS_jmpret:
3653  // jumpr r31
3654  // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
3655  DstReg = MI.getOperand(0).getReg();
3656  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3657  return HexagonII::HSIG_L2;
3658  break;
3659  case Hexagon::PS_jmprett:
3660  case Hexagon::PS_jmpretf:
3661  case Hexagon::PS_jmprettnewpt:
3662  case Hexagon::PS_jmpretfnewpt:
3663  case Hexagon::PS_jmprettnew:
3664  case Hexagon::PS_jmpretfnew:
3665  DstReg = MI.getOperand(1).getReg();
3666  SrcReg = MI.getOperand(0).getReg();
3667  // [if ([!]p0[.new])] jumpr r31
3668  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3669  (Hexagon::P0 == SrcReg)) &&
3670  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3671  return HexagonII::HSIG_L2;
3672  break;
3673  case Hexagon::L4_return_t :
3674  case Hexagon::L4_return_f :
3675  case Hexagon::L4_return_tnew_pnt :
3676  case Hexagon::L4_return_fnew_pnt :
3677  case Hexagon::L4_return_tnew_pt :
3678  case Hexagon::L4_return_fnew_pt :
3679  // [if ([!]p0[.new])] dealloc_return
3680  SrcReg = MI.getOperand(0).getReg();
3681  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3682  return HexagonII::HSIG_L2;
3683  break;
3684  //
3685  // Group S1:
3686  //
3687  // memw(Rs+#u4:2) = Rt
3688  // memb(Rs+#u4:0) = Rt
3689  case Hexagon::S2_storeri_io:
3690  // Special case this one from Group S2.
3691  // memw(r29+#u5:2) = Rt
3692  Src1Reg = MI.getOperand(0).getReg();
3693  Src2Reg = MI.getOperand(2).getReg();
3694  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3695  isIntRegForSubInst(Src2Reg) &&
3696  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3697  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3698  return HexagonII::HSIG_S2;
3699  // memw(Rs+#u4:2) = Rt
3700  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3701  MI.getOperand(1).isImm() &&
3702  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3703  return HexagonII::HSIG_S1;
3704  break;
3705  case Hexagon::S2_storerb_io:
3706  // memb(Rs+#u4:0) = Rt
3707  Src1Reg = MI.getOperand(0).getReg();
3708  Src2Reg = MI.getOperand(2).getReg();
3709  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3710  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3711  return HexagonII::HSIG_S1;
3712  break;
3713  //
3714  // Group S2:
3715  //
3716  // memh(Rs+#u3:1) = Rt
3717  // memw(r29+#u5:2) = Rt
3718  // memd(r29+#s6:3) = Rtt
3719  // memw(Rs+#u4:2) = #U1
3720  // memb(Rs+#u4) = #U1
3721  // allocframe(#u5:3)
3722  case Hexagon::S2_storerh_io:
3723  // memh(Rs+#u3:1) = Rt
3724  Src1Reg = MI.getOperand(0).getReg();
3725  Src2Reg = MI.getOperand(2).getReg();
3726  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3727  MI.getOperand(1).isImm() &&
3728  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3729  return HexagonII::HSIG_S1;
3730  break;
3731  case Hexagon::S2_storerd_io:
3732  // memd(r29+#s6:3) = Rtt
3733  Src1Reg = MI.getOperand(0).getReg();
3734  Src2Reg = MI.getOperand(2).getReg();
3735  if (isDblRegForSubInst(Src2Reg, HRI) &&
3736  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3737  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3738  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3739  return HexagonII::HSIG_S2;
3740  break;
3741  case Hexagon::S4_storeiri_io:
3742  // memw(Rs+#u4:2) = #U1
3743  Src1Reg = MI.getOperand(0).getReg();
3744  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3745  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3746  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3747  return HexagonII::HSIG_S2;
3748  break;
3749  case Hexagon::S4_storeirb_io:
3750  // memb(Rs+#u4) = #U1
3751  Src1Reg = MI.getOperand(0).getReg();
3752  if (isIntRegForSubInst(Src1Reg) &&
3753  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3754  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3755  return HexagonII::HSIG_S2;
3756  break;
3757  case Hexagon::S2_allocframe:
3758  if (MI.getOperand(0).isImm() &&
3759  isShiftedUInt<5,3>(MI.getOperand(0).getImm()))
3760  return HexagonII::HSIG_S1;
3761  break;
3762  //
3763  // Group A:
3764  //
3765  // Rx = add(Rx,#s7)
3766  // Rd = Rs
3767  // Rd = #u6
3768  // Rd = #-1
3769  // if ([!]P0[.new]) Rd = #0
3770  // Rd = add(r29,#u6:2)
3771  // Rx = add(Rx,Rs)
3772  // P0 = cmp.eq(Rs,#u2)
3773  // Rdd = combine(#0,Rs)
3774  // Rdd = combine(Rs,#0)
3775  // Rdd = combine(#u2,#U2)
3776  // Rd = add(Rs,#1)
3777  // Rd = add(Rs,#-1)
3778  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3779  // Rd = and(Rs,#1)
3780  case Hexagon::A2_addi:
3781  DstReg = MI.getOperand(0).getReg();
3782  SrcReg = MI.getOperand(1).getReg();
3783  if (isIntRegForSubInst(DstReg)) {
3784  // Rd = add(r29,#u6:2)
3785  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3786  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3787  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3788  return HexagonII::HSIG_A;
3789  // Rx = add(Rx,#s7)
3790  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3791  isInt<7>(MI.getOperand(2).getImm()))
3792  return HexagonII::HSIG_A;
3793  // Rd = add(Rs,#1)
3794  // Rd = add(Rs,#-1)
3795  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3796  ((MI.getOperand(2).getImm() == 1) ||
3797  (MI.getOperand(2).getImm() == -1)))
3798  return HexagonII::HSIG_A;
3799  }
3800  break;
3801  case Hexagon::A2_add:
3802  // Rx = add(Rx,Rs)
3803  DstReg = MI.getOperand(0).getReg();
3804  Src1Reg = MI.getOperand(1).getReg();
3805  Src2Reg = MI.getOperand(2).getReg();
3806  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3807  isIntRegForSubInst(Src2Reg))
3808  return HexagonII::HSIG_A;
3809  break;
3810  case Hexagon::A2_andir:
3811  // Same as zxtb.
3812  // Rd16=and(Rs16,#255)
3813  // Rd16=and(Rs16,#1)
3814  DstReg = MI.getOperand(0).getReg();
3815  SrcReg = MI.getOperand(1).getReg();
3816  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3817  MI.getOperand(2).isImm() &&
3818  ((MI.getOperand(2).getImm() == 1) ||
3819  (MI.getOperand(2).getImm() == 255)))
3820  return HexagonII::HSIG_A;
3821  break;
3822  case Hexagon::A2_tfr:
3823  // Rd = Rs
3824  DstReg = MI.getOperand(0).getReg();
3825  SrcReg = MI.getOperand(1).getReg();
3826  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3827  return HexagonII::HSIG_A;
3828  break;
3829  case Hexagon::A2_tfrsi:
3830  // Rd = #u6
3831  // Do not test for #u6 size since the const is getting extended
3832  // regardless and compound could be formed.
3833  // Rd = #-1
3834  DstReg = MI.getOperand(0).getReg();
3835  if (isIntRegForSubInst(DstReg))
3836  return HexagonII::HSIG_A;
3837  break;
3838  case Hexagon::C2_cmoveit:
3839  case Hexagon::C2_cmovenewit:
3840  case Hexagon::C2_cmoveif:
3841  case Hexagon::C2_cmovenewif:
3842  // if ([!]P0[.new]) Rd = #0
3843  // Actual form:
3844  // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
3845  DstReg = MI.getOperand(0).getReg();
3846  SrcReg = MI.getOperand(1).getReg();
3847  if (isIntRegForSubInst(DstReg) &&
3848  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3849  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3850  return HexagonII::HSIG_A;
3851  break;
3852  case Hexagon::C2_cmpeqi:
3853  // P0 = cmp.eq(Rs,#u2)
3854  DstReg = MI.getOperand(0).getReg();
3855  SrcReg = MI.getOperand(1).getReg();
3856  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3857  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3858  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3859  return HexagonII::HSIG_A;
3860  break;
3861  case Hexagon::A2_combineii:
3862  case Hexagon::A4_combineii:
3863  // Rdd = combine(#u2,#U2)
3864  DstReg = MI.getOperand(0).getReg();
3865  if (isDblRegForSubInst(DstReg, HRI) &&
3866  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3867  (MI.getOperand(1).isGlobal() &&
3868  isUInt<2>(MI.getOperand(1).getOffset()))) &&
3869  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3870  (MI.getOperand(2).isGlobal() &&
3871  isUInt<2>(MI.getOperand(2).getOffset()))))
3872  return HexagonII::HSIG_A;
3873  break;
3874  case Hexagon::A4_combineri:
3875  // Rdd = combine(Rs,#0)
3876  DstReg = MI.getOperand(0).getReg();
3877  SrcReg = MI.getOperand(1).getReg();
3878  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3879  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3880  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3881  return HexagonII::HSIG_A;
3882  break;
3883  case Hexagon::A4_combineir:
3884  // Rdd = combine(#0,Rs)
3885  DstReg = MI.getOperand(0).getReg();
3886  SrcReg = MI.getOperand(2).getReg();
3887  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3888  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3889  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3890  return HexagonII::HSIG_A;
3891  break;
3892  case Hexagon::A2_sxtb:
3893  case Hexagon::A2_sxth:
3894  case Hexagon::A2_zxtb:
3895  case Hexagon::A2_zxth:
3896  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3897  DstReg = MI.getOperand(0).getReg();
3898  SrcReg = MI.getOperand(1).getReg();
3899  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3900  return HexagonII::HSIG_A;
3901  break;
3902  }
3903 
3904  return HexagonII::HSIG_None;
3905 }
3906 
3908  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
3909 }
3910 
3912  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
3913  // Default to one cycle for no itinerary. However, an "empty" itinerary may
3914  // still have a MinLatency property, which getStageLatency checks.
3915  if (!ItinData)
3916  return getInstrLatency(ItinData, MI);
3917 
3918  if (MI.isTransient())
3919  return 0;
3920  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
3921 }
3922 
3923 /// getOperandLatency - Compute and return the use operand latency of a given
3924 /// pair of def and use.
3925 /// In most cases, the static scheduling itinerary was enough to determine the
3926 /// operand latency. But it may not be possible for instructions with variable
3927 /// number of defs / uses.
3928 ///
3929 /// This is a raw interface to the itinerary that may be directly overriden by
3930 /// a target. Use computeOperandLatency to get the best estimate of latency.
3932  const MachineInstr &DefMI,
3933  unsigned DefIdx,
3934  const MachineInstr &UseMI,
3935  unsigned UseIdx) const {
3936  auto &RI = getRegisterInfo();
3937  // Get DefIdx and UseIdx for super registers.
3938  MachineOperand DefMO = DefMI.getOperand(DefIdx);
3939 
3940  if (RI.isPhysicalRegister(DefMO.getReg())) {
3941  if (DefMO.isImplicit()) {
3942  for (MCSuperRegIterator SR(DefMO.getReg(), &RI); SR.isValid(); ++SR) {
3943  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &RI);
3944  if (Idx != -1) {
3945  DefIdx = Idx;
3946  break;
3947  }
3948  }
3949  }
3950 
3951  MachineOperand UseMO = UseMI.getOperand(UseIdx);
3952  if (UseMO.isImplicit()) {
3953  for (MCSuperRegIterator SR(UseMO.getReg(), &RI); SR.isValid(); ++SR) {
3954  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &RI);
3955  if (Idx != -1) {
3956  UseIdx = Idx;
3957  break;
3958  }
3959  }
3960  }
3961  }
3962 
3963  return TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
3964  UseMI, UseIdx);
3965 }
3966 
3967 // inverts the predication logic.
3968 // p -> NotP
3969 // NotP -> P
3971  SmallVectorImpl<MachineOperand> &Cond) const {
3972  if (Cond.empty())
3973  return false;
3974  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
3975  Cond[0].setImm(Opc);
3976  return true;
3977 }
3978 
3979 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
3980  int InvPredOpcode;
3981  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
3982  : Hexagon::getTruePredOpcode(Opc);
3983  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
3984  return InvPredOpcode;
3985 
3986  llvm_unreachable("Unexpected predicated instruction");
3987 }
3988 
3989 // Returns the max value that doesn't need to be extended.
3991  const uint64_t F = MI.getDesc().TSFlags;
3992  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3994  unsigned bits = (F >> HexagonII::ExtentBitsPos)
3996 
3997  if (isSigned) // if value is signed
3998  return ~(-1U << (bits - 1));
3999  else
4000  return ~(-1U << bits);
4001 }
4002 
4004  const uint64_t F = MI.getDesc().TSFlags;
4006 }
4007 
4008 // Returns the min value that doesn't need to be extended.
4010  const uint64_t F = MI.getDesc().TSFlags;
4011  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4013  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4015 
4016  if (isSigned) // if value is signed
4017  return -1U << (bits - 1);
4018  else
4019  return 0;
4020 }
4021 
4022 // Returns opcode of the non-extended equivalent instruction.
4024  // Check if the instruction has a register form that uses register in place
4025  // of the extended operand, if so return that as the non-extended form.
4026  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4027  if (NonExtOpcode >= 0)
4028  return NonExtOpcode;
4029 
4030  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4031  // Check addressing mode and retrieve non-ext equivalent instruction.
4032  switch (getAddrMode(MI)) {
4033  case HexagonII::Absolute :
4034  return Hexagon::getBaseWithImmOffset(MI.getOpcode());
4036  return Hexagon::getBaseWithRegOffset(MI.getOpcode());
4038  return Hexagon::getRegShlForm(MI.getOpcode());
4039 
4040  default:
4041  return -1;
4042  }
4043  }
4044  return -1;
4045 }
4046 
4048  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4049  if (Cond.empty())
4050  return false;
4051  assert(Cond.size() == 2);
4052  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4053  DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4054  return false;
4055  }
4056  PredReg = Cond[1].getReg();
4057  PredRegPos = 1;
4058  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4059  PredRegFlags = 0;
4060  if (Cond[1].isImplicit())
4061  PredRegFlags = RegState::Implicit;
4062  if (Cond[1].isUndef())
4063  PredRegFlags |= RegState::Undef;
4064  return true;
4065 }
4066 
4068  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4069 }
4070 
4072  return Hexagon::getRegForm(MI.getOpcode());
4073 }
4074 
4075 // Return the number of bytes required to encode the instruction.
4076 // Hexagon instructions are fixed length, 4 bytes, unless they
4077 // use a constant extender, which requires another 4 bytes.
4078 // For debug instructions and prolog labels, return 0.
4080  if (MI.isDebugValue() || MI.isPosition())
4081  return 0;
4082 
4083  unsigned Size = MI.getDesc().getSize();
4084  if (!Size)
4085  // Assume the default insn size in case it cannot be determined
4086  // for whatever reason.
4087  Size = HEXAGON_INSTR_SIZE;
4088 
4089  if (isConstExtended(MI) || isExtended(MI))
4090  Size += HEXAGON_INSTR_SIZE;
4091 
4092  // Try and compute number of instructions in asm.
4094  const MachineBasicBlock &MBB = *MI.getParent();
4095  const MachineFunction *MF = MBB.getParent();
4096  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4097 
4098  // Count the number of register definitions to find the asm string.
4099  unsigned NumDefs = 0;
4100  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4101  ++NumDefs)
4102  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4103 
4104  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4105  // Disassemble the AsmStr and approximate number of instructions.
4106  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4107  Size = getInlineAsmLength(AsmStr, *MAI);
4108  }
4109 
4110  return Size;
4111 }
4112 
4114  const uint64_t F = MI.getDesc().TSFlags;
4115  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4116 }
4117 
4120  const InstrItineraryData &II = *ST.getInstrItineraryData();
4121  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4122 
4123  return IS.getUnits();
4124 }
4125 
4126 // Calculate size of the basic block without debug instructions.
4128  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4129 }
4130 
4132  MachineBasicBlock::const_iterator BundleHead) const {
4133  assert(BundleHead->isBundle() && "Not a bundle header");
4134  auto MII = BundleHead.getInstrIterator();
4135  // Skip the bundle header.
4136  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4137 }
4138 
4139 /// immediateExtend - Changes the instruction in place to one using an immediate
4140 /// extender.
4142  assert((isExtendable(MI)||isConstExtended(MI)) &&
4143  "Instruction must be extendable");
4144  // Find which operand is extendable.
4145  short ExtOpNum = getCExtOpNum(MI);
4146  MachineOperand &MO = MI.getOperand(ExtOpNum);
4147  // This needs to be something we understand.
4148  assert((MO.isMBB() || MO.isImm()) &&
4149  "Branch with unknown extendable field type");
4150  // Mark given operand as extended.
4152 }
4153 
4155  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4156  DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
4157  << NewTarget->getNumber(); MI.dump(););
4158  assert(MI.isBranch());
4159  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4160  int TargetPos = MI.getNumOperands() - 1;
4161  // In general branch target is the last operand,
4162  // but some implicit defs added at the end might change it.
4163  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4164  --TargetPos;
4165  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4166  MI.getOperand(TargetPos).setMBB(NewTarget);
4168  NewOpcode = reversePrediction(NewOpcode);
4169  }
4170  MI.setDesc(get(NewOpcode));
4171  return true;
4172 }
4173 
4175  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4177  MachineBasicBlock &B = *A;
4179  DebugLoc DL = I->getDebugLoc();
4180  MachineInstr *NewMI;
4181 
4182  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4183  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4184  NewMI = BuildMI(B, I, DL, get(insn));
4185  DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
4186  " Class: " << NewMI->getDesc().getSchedClass());
4187  NewMI->eraseFromParent();
4188  }
4189  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4190 }
4191 
4192 // inverts the predication logic.
4193 // p -> NotP
4194 // NotP -> P
4196  DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4198  return true;
4199 }
4200 
4201 // Reverse the branch prediction.
4202 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4203  int PredRevOpcode = -1;
4204  if (isPredictedTaken(Opcode))
4205  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4206  else
4207  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4208  assert(PredRevOpcode > 0);
4209  return PredRevOpcode;
4210 }
4211 
4212 // TODO: Add more rigorous validation.
4214  const {
4215  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4216 }
4217 
4219  return Hexagon::xformRegToImmOffset(MI.getOpcode());
4220 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
void push_back(const T &Elt)
Definition: SmallVector.h:212
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:850
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:927
static bool is_TC3x(unsigned SchedClass)
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:429
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:103
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
static bool is_TC1(unsigned SchedClass)
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:257
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
bool isInlineAsm() const
Definition: MachineInstr.h:795
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
static bool is_TC2early(unsigned SchedClass)
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:863
demanded bits
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
MachineBasicBlock reference.
short getBaseWithLongOffset(short Opcode) const
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMV_AUTOINC_MIN
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:387
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:306
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:570
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
static bool is_TC2(unsigned SchedClass)
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:282
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:476
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
static StringRef getName(Value *V)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:279
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
const int Hexagon_MEMH_AUTOINC_MIN
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const int Hexagon_MEMB_AUTOINC_MAX
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:633
static MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited)
Find the hardware loop instruction used to set-up the specified loop.
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:276
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:459
#define F(x, y, z)
Definition: MD5.cpp:55
bool isEndLoopN(unsigned Opcode) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
const RegList & Regs
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const int Hexagon_MEMD_AUTOINC_MIN
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
const int Hexagon_MEMV_AUTOINC_MAX
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
bool isTC1(const MachineInstr &MI) const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
const int Hexagon_MEMW_AUTOINC_MAX
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:453
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:425
static bool is_TC4x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:610
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:404
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
const int Hexagon_MEMH_AUTOINC_MAX
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:490
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
const char * getSeparatorString() const
Definition: MCAsmInfo.h:464
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
bool hasUncondBranch(const MachineBasicBlock *B) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
#define A
Definition: LargeTest.cpp:12
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:372
unsigned getAddrMode(const MachineInstr &MI) const
int getNonDotCurOp(const MachineInstr &MI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
void setMBB(MachineBasicBlock *MBB)
bool isTC2Early(const MachineInstr &MI) const
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
Address of a basic block.
static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI)
bool isValidAutoIncImm(const EVT VT, const int Offset) const
StringRef getCommentString() const
Definition: MCAsmInfo.h:470
bool isFloat(const MachineInstr &MI) const
void setImm(int64_t immVal)
self_iterator getIterator()
Definition: ilist_node.h:82
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
iterator_range< pred_iterator > predecessors()
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
void genAllInsnTimingClasses(MachineFunction &MF) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
short getPseudoInstrPair(const MachineInstr &MI) const
MCSubRegIterator enumerates all sub-registers of Reg.
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
bool isEarlySourceInstr(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isExtendable(const MachineInstr &MI) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:286
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
static cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
void setIsKill(bool Val=true)
bool hasPseudoInstrPair(const MachineInstr &MI) const
The memory access writes data.
bool isIndirectCall(const MachineInstr &MI) const
bool isTC4x(const MachineInstr &MI) const
bool isDotCurInst(const MachineInstr &MI) const
static bool isIntRegForSubInst(unsigned Reg)
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:467
Iterator for intrusive lists based on ilist_node.
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:423
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
#define E
Definition: LargeTest.cpp:27
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool isNewValueStore(const MachineInstr &MI) const
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
const int Hexagon_MEMW_AUTOINC_MIN
HexagonInstrInfo(HexagonSubtarget &ST)
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
#define B
Definition: LargeTest.cpp:24
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:363
bool isNewValueInst(const MachineInstr &MI) const
bool isDebugValue() const
Definition: MachineInstr.h:782
MachineOperand class - Representation of each machine instruction operand.
bool isVecAcc(const MachineInstr &MI) const
MachineInstrBuilder MachineInstrBuilder & DefMI
bool hasEHLabel(const MachineBasicBlock *B) const
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
unsigned getUnits(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
const size_t N
uint64_t getType(const MachineInstr &MI) const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
bool isSignExtendingLoad(const MachineInstr &MI) const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isLateSourceInstr(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
unsigned getMaxInstLength() const
Definition: MCAsmInfo.h:461