LLVM  7.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
16 #include "HexagonFrameLowering.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCInstrDesc.h"
47 #include "llvm/MC/MCRegisterInfo.h"
50 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
80 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
98 
99 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
101  cl::desc("Use the DFA based hazard recognizer."));
102 
103 /// Constants for Hexagon instructions.
104 const int Hexagon_MEMW_OFFSET_MAX = 4095;
105 const int Hexagon_MEMW_OFFSET_MIN = -4096;
106 const int Hexagon_MEMD_OFFSET_MAX = 8191;
107 const int Hexagon_MEMD_OFFSET_MIN = -8192;
108 const int Hexagon_MEMH_OFFSET_MAX = 2047;
109 const int Hexagon_MEMH_OFFSET_MIN = -2048;
110 const int Hexagon_MEMB_OFFSET_MAX = 1023;
111 const int Hexagon_MEMB_OFFSET_MIN = -1024;
112 const int Hexagon_ADDI_OFFSET_MAX = 32767;
113 const int Hexagon_ADDI_OFFSET_MIN = -32768;
114 
115 // Pin the vtable to this file.
116 void HexagonInstrInfo::anchor() {}
117 
119  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
120  Subtarget(ST) {}
121 
122 static bool isIntRegForSubInst(unsigned Reg) {
123  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
124  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
125 }
126 
127 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
128  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
129  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
130 }
131 
132 /// Calculate number of instructions excluding the debug instructions.
135  unsigned Count = 0;
136  for (; MIB != MIE; ++MIB) {
137  if (!MIB->isDebugValue())
138  ++Count;
139  }
140  return Count;
141 }
142 
143 /// Find the hardware loop instruction used to set-up the specified loop.
144 /// On Hexagon, we have two instructions used to set-up the hardware loop
145 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
146 /// to indicate the end of a loop.
147 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
148  MachineBasicBlock *TargetBB,
150  unsigned LOOPi;
151  unsigned LOOPr;
152  if (EndLoopOp == Hexagon::ENDLOOP0) {
153  LOOPi = Hexagon::J2_loop0i;
154  LOOPr = Hexagon::J2_loop0r;
155  } else { // EndLoopOp == Hexagon::EndLOOP1
156  LOOPi = Hexagon::J2_loop1i;
157  LOOPr = Hexagon::J2_loop1r;
158  }
159 
160  // The loop set-up instruction will be in a predecessor block
161  for (MachineBasicBlock *PB : BB->predecessors()) {
162  // If this has been visited, already skip it.
163  if (!Visited.insert(PB).second)
164  continue;
165  if (PB == BB)
166  continue;
167  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
168  unsigned Opc = I->getOpcode();
169  if (Opc == LOOPi || Opc == LOOPr)
170  return &*I;
171  // We've reached a different loop, which means the loop01 has been
172  // removed.
173  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
174  return nullptr;
175  }
176  // Check the predecessors for the LOOP instruction.
177  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
178  return Loop;
179  }
180  return nullptr;
181 }
182 
183 /// Gather register def/uses from MI.
184 /// This treats possible (predicated) defs as actually happening ones
185 /// (conservatively).
186 static inline void parseOperands(const MachineInstr &MI,
188  Defs.clear();
189  Uses.clear();
190 
191  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
192  const MachineOperand &MO = MI.getOperand(i);
193 
194  if (!MO.isReg())
195  continue;
196 
197  unsigned Reg = MO.getReg();
198  if (!Reg)
199  continue;
200 
201  if (MO.isUse())
202  Uses.push_back(MO.getReg());
203 
204  if (MO.isDef())
205  Defs.push_back(MO.getReg());
206  }
207 }
208 
209 // Position dependent, so check twice for swap.
210 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
211  switch (Ga) {
213  default:
214  return false;
215  case HexagonII::HSIG_L1:
216  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
217  case HexagonII::HSIG_L2:
218  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
219  Gb == HexagonII::HSIG_A);
220  case HexagonII::HSIG_S1:
221  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
222  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
223  case HexagonII::HSIG_S2:
224  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
225  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
226  Gb == HexagonII::HSIG_A);
227  case HexagonII::HSIG_A:
228  return (Gb == HexagonII::HSIG_A);
230  return (Gb == HexagonII::HSIG_Compound);
231  }
232  return false;
233 }
234 
235 /// isLoadFromStackSlot - If the specified machine instruction is a direct
236 /// load from a stack slot, return the virtual or physical register number of
237 /// the destination along with the FrameIndex of the loaded stack slot. If
238 /// not, return 0. This predicate must return 0 if the instruction has
239 /// any side effects other than loading from the stack slot.
241  int &FrameIndex) const {
242  switch (MI.getOpcode()) {
243  default:
244  break;
245  case Hexagon::L2_loadri_io:
246  case Hexagon::L2_loadrd_io:
247  case Hexagon::V6_vL32b_ai:
248  case Hexagon::V6_vL32b_nt_ai:
249  case Hexagon::V6_vL32Ub_ai:
250  case Hexagon::LDriw_pred:
251  case Hexagon::LDriw_mod:
252  case Hexagon::PS_vloadrq_ai:
253  case Hexagon::PS_vloadrw_ai:
254  case Hexagon::PS_vloadrw_nt_ai: {
255  const MachineOperand OpFI = MI.getOperand(1);
256  if (!OpFI.isFI())
257  return 0;
258  const MachineOperand OpOff = MI.getOperand(2);
259  if (!OpOff.isImm() || OpOff.getImm() != 0)
260  return 0;
261  FrameIndex = OpFI.getIndex();
262  return MI.getOperand(0).getReg();
263  }
264 
265  case Hexagon::L2_ploadrit_io:
266  case Hexagon::L2_ploadrif_io:
267  case Hexagon::L2_ploadrdt_io:
268  case Hexagon::L2_ploadrdf_io: {
269  const MachineOperand OpFI = MI.getOperand(2);
270  if (!OpFI.isFI())
271  return 0;
272  const MachineOperand OpOff = MI.getOperand(3);
273  if (!OpOff.isImm() || OpOff.getImm() != 0)
274  return 0;
275  FrameIndex = OpFI.getIndex();
276  return MI.getOperand(0).getReg();
277  }
278  }
279 
280  return 0;
281 }
282 
283 /// isStoreToStackSlot - If the specified machine instruction is a direct
284 /// store to a stack slot, return the virtual or physical register number of
285 /// the source reg along with the FrameIndex of the loaded stack slot. If
286 /// not, return 0. This predicate must return 0 if the instruction has
287 /// any side effects other than storing to the stack slot.
289  int &FrameIndex) const {
290  switch (MI.getOpcode()) {
291  default:
292  break;
293  case Hexagon::S2_storerb_io:
294  case Hexagon::S2_storerh_io:
295  case Hexagon::S2_storeri_io:
296  case Hexagon::S2_storerd_io:
297  case Hexagon::V6_vS32b_ai:
298  case Hexagon::V6_vS32Ub_ai:
299  case Hexagon::STriw_pred:
300  case Hexagon::STriw_mod:
301  case Hexagon::PS_vstorerq_ai:
302  case Hexagon::PS_vstorerw_ai: {
303  const MachineOperand &OpFI = MI.getOperand(0);
304  if (!OpFI.isFI())
305  return 0;
306  const MachineOperand &OpOff = MI.getOperand(1);
307  if (!OpOff.isImm() || OpOff.getImm() != 0)
308  return 0;
309  FrameIndex = OpFI.getIndex();
310  return MI.getOperand(2).getReg();
311  }
312 
313  case Hexagon::S2_pstorerbt_io:
314  case Hexagon::S2_pstorerbf_io:
315  case Hexagon::S2_pstorerht_io:
316  case Hexagon::S2_pstorerhf_io:
317  case Hexagon::S2_pstorerit_io:
318  case Hexagon::S2_pstorerif_io:
319  case Hexagon::S2_pstorerdt_io:
320  case Hexagon::S2_pstorerdf_io: {
321  const MachineOperand &OpFI = MI.getOperand(1);
322  if (!OpFI.isFI())
323  return 0;
324  const MachineOperand &OpOff = MI.getOperand(2);
325  if (!OpOff.isImm() || OpOff.getImm() != 0)
326  return 0;
327  FrameIndex = OpFI.getIndex();
328  return MI.getOperand(3).getReg();
329  }
330  }
331 
332  return 0;
333 }
334 
335 /// This function checks if the instruction or bundle of instructions
336 /// has load from stack slot and returns frameindex and machine memory
337 /// operand of that instruction if true.
339  const MachineMemOperand *&MMO,
340  int &FrameIndex) const {
341  if (MI.isBundle()) {
342  const MachineBasicBlock *MBB = MI.getParent();
344  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
345  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, MMO, FrameIndex))
346  return true;
347  return false;
348  }
349 
350  return TargetInstrInfo::hasLoadFromStackSlot(MI, MMO, FrameIndex);
351 }
352 
353 /// This function checks if the instruction or bundle of instructions
354 /// has store to stack slot and returns frameindex and machine memory
355 /// operand of that instruction if true.
357  const MachineMemOperand *&MMO,
358  int &FrameIndex) const {
359  if (MI.isBundle()) {
360  const MachineBasicBlock *MBB = MI.getParent();
362  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
363  if (TargetInstrInfo::hasStoreToStackSlot(*MII, MMO, FrameIndex))
364  return true;
365  return false;
366  }
367 
368  return TargetInstrInfo::hasStoreToStackSlot(MI, MMO, FrameIndex);
369 }
370 
371 /// This function can analyze one/two way branching only and should (mostly) be
372 /// called by target independent side.
373 /// First entry is always the opcode of the branching instruction, except when
374 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
375 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
376 /// e.g. Jump_c p will have
377 /// Cond[0] = Jump_c
378 /// Cond[1] = p
379 /// HW-loop ENDLOOP:
380 /// Cond[0] = ENDLOOP
381 /// Cond[1] = MBB
382 /// New value jump:
383 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
384 /// Cond[1] = R
385 /// Cond[2] = Imm
387  MachineBasicBlock *&TBB,
388  MachineBasicBlock *&FBB,
390  bool AllowModify) const {
391  TBB = nullptr;
392  FBB = nullptr;
393  Cond.clear();
394 
395  // If the block has no terminators, it just falls into the block after it.
397  if (I == MBB.instr_begin())
398  return false;
399 
400  // A basic block may looks like this:
401  //
402  // [ insn
403  // EH_LABEL
404  // insn
405  // insn
406  // insn
407  // EH_LABEL
408  // insn ]
409  //
410  // It has two succs but does not have a terminator
411  // Don't know how to handle it.
412  do {
413  --I;
414  if (I->isEHLabel())
415  // Don't analyze EH branches.
416  return true;
417  } while (I != MBB.instr_begin());
418 
419  I = MBB.instr_end();
420  --I;
421 
422  while (I->isDebugValue()) {
423  if (I == MBB.instr_begin())
424  return false;
425  --I;
426  }
427 
428  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
429  I->getOperand(0).isMBB();
430  // Delete the J2_jump if it's equivalent to a fall-through.
431  if (AllowModify && JumpToBlock &&
432  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
433  DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
434  I->eraseFromParent();
435  I = MBB.instr_end();
436  if (I == MBB.instr_begin())
437  return false;
438  --I;
439  }
440  if (!isUnpredicatedTerminator(*I))
441  return false;
442 
443  // Get the last instruction in the block.
444  MachineInstr *LastInst = &*I;
445  MachineInstr *SecondLastInst = nullptr;
446  // Find one more terminator if present.
447  while (true) {
448  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
449  if (!SecondLastInst)
450  SecondLastInst = &*I;
451  else
452  // This is a third branch.
453  return true;
454  }
455  if (I == MBB.instr_begin())
456  break;
457  --I;
458  }
459 
460  int LastOpcode = LastInst->getOpcode();
461  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
462  // If the branch target is not a basic block, it could be a tail call.
463  // (It is, if the target is a function.)
464  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
465  return true;
466  if (SecLastOpcode == Hexagon::J2_jump &&
467  !SecondLastInst->getOperand(0).isMBB())
468  return true;
469 
470  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
471  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
472 
473  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
474  return true;
475 
476  // If there is only one terminator instruction, process it.
477  if (LastInst && !SecondLastInst) {
478  if (LastOpcode == Hexagon::J2_jump) {
479  TBB = LastInst->getOperand(0).getMBB();
480  return false;
481  }
482  if (isEndLoopN(LastOpcode)) {
483  TBB = LastInst->getOperand(0).getMBB();
484  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
485  Cond.push_back(LastInst->getOperand(0));
486  return false;
487  }
488  if (LastOpcodeHasJMP_c) {
489  TBB = LastInst->getOperand(1).getMBB();
490  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
491  Cond.push_back(LastInst->getOperand(0));
492  return false;
493  }
494  // Only supporting rr/ri versions of new-value jumps.
495  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
496  TBB = LastInst->getOperand(2).getMBB();
497  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
498  Cond.push_back(LastInst->getOperand(0));
499  Cond.push_back(LastInst->getOperand(1));
500  return false;
501  }
502  DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
503  << " with one jump\n";);
504  // Otherwise, don't know what this is.
505  return true;
506  }
507 
508  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
509  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
510  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
511  if (!SecondLastInst->getOperand(1).isMBB())
512  return true;
513  TBB = SecondLastInst->getOperand(1).getMBB();
514  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
515  Cond.push_back(SecondLastInst->getOperand(0));
516  FBB = LastInst->getOperand(0).getMBB();
517  return false;
518  }
519 
520  // Only supporting rr/ri versions of new-value jumps.
521  if (SecLastOpcodeHasNVJump &&
522  (SecondLastInst->getNumExplicitOperands() == 3) &&
523  (LastOpcode == Hexagon::J2_jump)) {
524  TBB = SecondLastInst->getOperand(2).getMBB();
525  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
526  Cond.push_back(SecondLastInst->getOperand(0));
527  Cond.push_back(SecondLastInst->getOperand(1));
528  FBB = LastInst->getOperand(0).getMBB();
529  return false;
530  }
531 
532  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
533  // executed, so remove it.
534  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
535  TBB = SecondLastInst->getOperand(0).getMBB();
536  I = LastInst->getIterator();
537  if (AllowModify)
538  I->eraseFromParent();
539  return false;
540  }
541 
542  // If the block ends with an ENDLOOP, and J2_jump, handle it.
543  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
544  TBB = SecondLastInst->getOperand(0).getMBB();
545  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
546  Cond.push_back(SecondLastInst->getOperand(0));
547  FBB = LastInst->getOperand(0).getMBB();
548  return false;
549  }
550  DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
551  << " with two jumps";);
552  // Otherwise, can't handle this.
553  return true;
554 }
555 
557  int *BytesRemoved) const {
558  assert(!BytesRemoved && "code size not handled");
559 
560  DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
562  unsigned Count = 0;
563  while (I != MBB.begin()) {
564  --I;
565  if (I->isDebugValue())
566  continue;
567  // Only removing branches from end of MBB.
568  if (!I->isBranch())
569  return Count;
570  if (Count && (I->getOpcode() == Hexagon::J2_jump))
571  llvm_unreachable("Malformed basic block: unconditional branch not last");
572  MBB.erase(&MBB.back());
573  I = MBB.end();
574  ++Count;
575  }
576  return Count;
577 }
578 
580  MachineBasicBlock *TBB,
581  MachineBasicBlock *FBB,
583  const DebugLoc &DL,
584  int *BytesAdded) const {
585  unsigned BOpc = Hexagon::J2_jump;
586  unsigned BccOpc = Hexagon::J2_jumpt;
587  assert(validateBranchCond(Cond) && "Invalid branching condition");
588  assert(TBB && "insertBranch must not be told to insert a fallthrough");
589  assert(!BytesAdded && "code size not handled");
590 
591  // Check if reverseBranchCondition has asked to reverse this branch
592  // If we want to reverse the branch an odd number of times, we want
593  // J2_jumpf.
594  if (!Cond.empty() && Cond[0].isImm())
595  BccOpc = Cond[0].getImm();
596 
597  if (!FBB) {
598  if (Cond.empty()) {
599  // Due to a bug in TailMerging/CFG Optimization, we need to add a
600  // special case handling of a predicated jump followed by an
601  // unconditional jump. If not, Tail Merging and CFG Optimization go
602  // into an infinite loop.
603  MachineBasicBlock *NewTBB, *NewFBB;
605  auto Term = MBB.getFirstTerminator();
606  if (Term != MBB.end() && isPredicated(*Term) &&
607  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
608  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
610  removeBranch(MBB);
611  return insertBranch(MBB, TBB, nullptr, Cond, DL);
612  }
613  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
614  } else if (isEndLoopN(Cond[0].getImm())) {
615  int EndLoopOp = Cond[0].getImm();
616  assert(Cond[1].isMBB());
617  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
618  // Check for it, and change the BB target if needed.
620  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
621  VisitedBBs);
622  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
623  Loop->getOperand(0).setMBB(TBB);
624  // Add the ENDLOOP after the finding the LOOP0.
625  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
626  } else if (isNewValueJump(Cond[0].getImm())) {
627  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
628  // New value jump
629  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
630  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
631  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
632  DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB););
633  if (Cond[2].isReg()) {
634  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
635  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
637  } else if(Cond[2].isImm()) {
638  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
639  addImm(Cond[2].getImm()).addMBB(TBB);
640  } else
641  llvm_unreachable("Invalid condition for branching");
642  } else {
643  assert((Cond.size() == 2) && "Malformed cond vector");
644  const MachineOperand &RO = Cond[1];
645  unsigned Flags = getUndefRegState(RO.isUndef());
646  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
647  }
648  return 1;
649  }
650  assert((!Cond.empty()) &&
651  "Cond. cannot be empty when multiple branchings are required");
652  assert((!isNewValueJump(Cond[0].getImm())) &&
653  "NV-jump cannot be inserted with another branch");
654  // Special case for hardware loops. The condition is a basic block.
655  if (isEndLoopN(Cond[0].getImm())) {
656  int EndLoopOp = Cond[0].getImm();
657  assert(Cond[1].isMBB());
658  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659  // Check for it, and change the BB target if needed.
661  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
662  VisitedBBs);
663  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
664  Loop->getOperand(0).setMBB(TBB);
665  // Add the ENDLOOP after the finding the LOOP0.
666  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
667  } else {
668  const MachineOperand &RO = Cond[1];
669  unsigned Flags = getUndefRegState(RO.isUndef());
670  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
671  }
672  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
673 
674  return 2;
675 }
676 
677 /// Analyze the loop code to find the loop induction variable and compare used
678 /// to compute the number of iterations. Currently, we analyze loop that are
679 /// controlled using hardware loops. In this case, the induction variable
680 /// instruction is null. For all other cases, this function returns true, which
681 /// means we're unable to analyze it.
683  MachineInstr *&IndVarInst,
684  MachineInstr *&CmpInst) const {
685 
686  MachineBasicBlock *LoopEnd = L.getBottomBlock();
688  // We really "analyze" only hardware loops right now.
689  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
690  IndVarInst = nullptr;
691  CmpInst = &*I;
692  return false;
693  }
694  return true;
695 }
696 
697 /// Generate code to reduce the loop iteration by one and check if the loop is
698 /// finished. Return the value/register of the new loop count. this function
699 /// assumes the nth iteration is peeled first.
701  MachineInstr *IndVar, MachineInstr &Cmp,
704  unsigned Iter, unsigned MaxIter) const {
705  // We expect a hardware loop currently. This means that IndVar is set
706  // to null, and the compare is the ENDLOOP instruction.
707  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
708  && "Expecting a hardware loop");
709  MachineFunction *MF = MBB.getParent();
710  DebugLoc DL = Cmp.getDebugLoc();
712  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
713  Cmp.getOperand(0).getMBB(), VisitedBBs);
714  if (!Loop)
715  return 0;
716  // If the loop trip count is a compile-time value, then just change the
717  // value.
718  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
719  Loop->getOpcode() == Hexagon::J2_loop1i) {
720  int64_t Offset = Loop->getOperand(1).getImm();
721  if (Offset <= 1)
722  Loop->eraseFromParent();
723  else
724  Loop->getOperand(1).setImm(Offset - 1);
725  return Offset - 1;
726  }
727  // The loop trip count is a run-time value. We generate code to subtract
728  // one from the trip count, and update the loop instruction.
729  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
730  unsigned LoopCount = Loop->getOperand(1).getReg();
731  // Check if we're done with the loop.
732  unsigned LoopEnd = createVR(MF, MVT::i1);
733  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
734  addReg(LoopCount).addImm(1);
735  unsigned NewLoopCount = createVR(MF, MVT::i32);
736  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
737  addReg(LoopCount).addImm(-1);
738  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
739  // Update the previously generated instructions with the new loop counter.
741  E = PrevInsts.end(); I != E; ++I)
742  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
743  PrevInsts.clear();
744  PrevInsts.push_back(NewCmp);
745  PrevInsts.push_back(NewAdd);
746  // Insert the new loop instruction if this is the last time the loop is
747  // decremented.
748  if (Iter == MaxIter)
749  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
750  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
751  // Delete the old loop instruction.
752  if (Iter == 0)
753  Loop->eraseFromParent();
754  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
755  Cond.push_back(NewCmp->getOperand(0));
756  return NewLoopCount;
757 }
758 
760  unsigned NumCycles, unsigned ExtraPredCycles,
761  BranchProbability Probability) const {
762  return nonDbgBBSize(&MBB) <= 3;
763 }
764 
766  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
767  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
768  const {
769  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
770 }
771 
773  unsigned NumInstrs, BranchProbability Probability) const {
774  return NumInstrs <= 4;
775 }
776 
779  const DebugLoc &DL, unsigned DestReg,
780  unsigned SrcReg, bool KillSrc) const {
781  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
782  unsigned KillFlag = getKillRegState(KillSrc);
783 
784  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
785  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
786  .addReg(SrcReg, KillFlag);
787  return;
788  }
789  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
790  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
791  .addReg(SrcReg, KillFlag);
792  return;
793  }
794  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
795  // Map Pd = Ps to Pd = or(Ps, Ps).
796  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
797  .addReg(SrcReg).addReg(SrcReg, KillFlag);
798  return;
799  }
800  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
801  Hexagon::IntRegsRegClass.contains(SrcReg)) {
802  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
803  .addReg(SrcReg, KillFlag);
804  return;
805  }
806  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
807  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
808  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
809  .addReg(SrcReg, KillFlag);
810  return;
811  }
812  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
813  Hexagon::IntRegsRegClass.contains(SrcReg)) {
814  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
815  .addReg(SrcReg, KillFlag);
816  return;
817  }
818  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
819  Hexagon::IntRegsRegClass.contains(DestReg)) {
820  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
821  .addReg(SrcReg, KillFlag);
822  return;
823  }
824  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
825  Hexagon::PredRegsRegClass.contains(DestReg)) {
826  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
827  .addReg(SrcReg, KillFlag);
828  return;
829  }
830  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
831  Hexagon::IntRegsRegClass.contains(DestReg)) {
832  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
833  .addReg(SrcReg, KillFlag);
834  return;
835  }
836  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
837  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
838  addReg(SrcReg, KillFlag);
839  return;
840  }
841  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
842  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
843  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
844  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
845  .addReg(HiSrc, KillFlag)
846  .addReg(LoSrc, KillFlag);
847  return;
848  }
849  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
850  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
851  .addReg(SrcReg)
852  .addReg(SrcReg, KillFlag);
853  return;
854  }
855  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
856  Hexagon::HvxVRRegClass.contains(DestReg)) {
857  llvm_unreachable("Unimplemented pred to vec");
858  return;
859  }
860  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
861  Hexagon::HvxVRRegClass.contains(SrcReg)) {
862  llvm_unreachable("Unimplemented vec to pred");
863  return;
864  }
865 
866 #ifndef NDEBUG
867  // Show the invalid registers to ease debugging.
868  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
869  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
870 #endif
871  llvm_unreachable("Unimplemented");
872 }
873 
875  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
876  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
877  DebugLoc DL = MBB.findDebugLoc(I);
878  MachineFunction &MF = *MBB.getParent();
879  MachineFrameInfo &MFI = MF.getFrameInfo();
880  unsigned SlotAlign = MFI.getObjectAlignment(FI);
881  unsigned RegAlign = TRI->getSpillAlignment(*RC);
882  unsigned KillFlag = getKillRegState(isKill);
883  bool HasAlloca = MFI.hasVarSizedObjects();
884  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
885 
888  MFI.getObjectSize(FI), SlotAlign);
889 
890  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
891  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
892  .addFrameIndex(FI).addImm(0)
893  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
894  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
895  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
896  .addFrameIndex(FI).addImm(0)
897  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
898  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
899  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
900  .addFrameIndex(FI).addImm(0)
901  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
902  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
903  BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
904  .addFrameIndex(FI).addImm(0)
905  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
906  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
907  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
908  .addFrameIndex(FI).addImm(0)
909  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
910  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
911  // If there are variable-sized objects, spills will not be aligned.
912  if (HasAlloca)
913  SlotAlign = HFI.getStackAlignment();
914  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
915  : Hexagon::V6_vS32b_ai;
918  MFI.getObjectSize(FI), SlotAlign);
919  BuildMI(MBB, I, DL, get(Opc))
920  .addFrameIndex(FI).addImm(0)
921  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
922  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
923  // If there are variable-sized objects, spills will not be aligned.
924  if (HasAlloca)
925  SlotAlign = HFI.getStackAlignment();
926  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
927  : Hexagon::PS_vstorerw_ai;
930  MFI.getObjectSize(FI), SlotAlign);
931  BuildMI(MBB, I, DL, get(Opc))
932  .addFrameIndex(FI).addImm(0)
933  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
934  } else {
935  llvm_unreachable("Unimplemented");
936  }
937 }
938 
940  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
941  int FI, const TargetRegisterClass *RC,
942  const TargetRegisterInfo *TRI) const {
943  DebugLoc DL = MBB.findDebugLoc(I);
944  MachineFunction &MF = *MBB.getParent();
945  MachineFrameInfo &MFI = MF.getFrameInfo();
946  unsigned SlotAlign = MFI.getObjectAlignment(FI);
947  unsigned RegAlign = TRI->getSpillAlignment(*RC);
948  bool HasAlloca = MFI.hasVarSizedObjects();
949  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
950 
953  MFI.getObjectSize(FI), SlotAlign);
954 
955  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
956  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
957  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
958  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
959  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
960  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
961  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
962  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
963  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
964  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
965  BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
966  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
967  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
968  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
969  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
970  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
971  // If there are variable-sized objects, spills will not be aligned.
972  if (HasAlloca)
973  SlotAlign = HFI.getStackAlignment();
974  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
975  : Hexagon::V6_vL32b_ai;
978  MFI.getObjectSize(FI), SlotAlign);
979  BuildMI(MBB, I, DL, get(Opc), DestReg)
980  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
981  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
982  // If there are variable-sized objects, spills will not be aligned.
983  if (HasAlloca)
984  SlotAlign = HFI.getStackAlignment();
985  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
986  : Hexagon::PS_vloadrw_ai;
989  MFI.getObjectSize(FI), SlotAlign);
990  BuildMI(MBB, I, DL, get(Opc), DestReg)
991  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
992  } else {
993  llvm_unreachable("Can't store this register to stack slot");
994  }
995 }
996 
998  const MachineBasicBlock &B = *MI.getParent();
999  Regs.addLiveOuts(B);
1000  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1001  for (auto I = B.rbegin(); I != E; ++I)
1002  Regs.stepBackward(*I);
1003 }
1004 
1005 /// expandPostRAPseudo - This function is called for all pseudo instructions
1006 /// that remain after register allocation. Many pseudo instructions are
1007 /// created to help register allocation. This is the place to convert them
1008 /// into real instructions. The target can edit MI in place, or it can insert
1009 /// new instructions and erase MI. The function should return true if
1010 /// anything was changed.
1012  MachineBasicBlock &MBB = *MI.getParent();
1013  MachineFunction &MF = *MBB.getParent();
1015  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1016  DebugLoc DL = MI.getDebugLoc();
1017  unsigned Opc = MI.getOpcode();
1018 
1019  switch (Opc) {
1020  case TargetOpcode::COPY: {
1021  MachineOperand &MD = MI.getOperand(0);
1022  MachineOperand &MS = MI.getOperand(1);
1024  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1025  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1026  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1027  }
1028  MBB.erase(MBBI);
1029  return true;
1030  }
1031  case Hexagon::PS_aligna:
1032  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1033  .addReg(HRI.getFrameRegister())
1034  .addImm(-MI.getOperand(1).getImm());
1035  MBB.erase(MI);
1036  return true;
1037  case Hexagon::V6_vassignp: {
1038  unsigned SrcReg = MI.getOperand(1).getReg();
1039  unsigned DstReg = MI.getOperand(0).getReg();
1040  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1041  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1042  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1043  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1044  MBB.erase(MI);
1045  return true;
1046  }
1047  case Hexagon::V6_lo: {
1048  unsigned SrcReg = MI.getOperand(1).getReg();
1049  unsigned DstReg = MI.getOperand(0).getReg();
1050  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1051  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1052  MBB.erase(MI);
1053  MRI.clearKillFlags(SrcSubLo);
1054  return true;
1055  }
1056  case Hexagon::V6_hi: {
1057  unsigned SrcReg = MI.getOperand(1).getReg();
1058  unsigned DstReg = MI.getOperand(0).getReg();
1059  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1060  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1061  MBB.erase(MI);
1062  MRI.clearKillFlags(SrcSubHi);
1063  return true;
1064  }
1065  case Hexagon::PS_vstorerw_ai:
1066  case Hexagon::PS_vstorerwu_ai: {
1067  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1068  unsigned SrcReg = MI.getOperand(2).getReg();
1069  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1070  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1071  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1072  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1073 
1074  MachineInstr *MI1New =
1075  BuildMI(MBB, MI, DL, get(NewOpc))
1076  .add(MI.getOperand(0))
1077  .addImm(MI.getOperand(1).getImm())
1078  .addReg(SrcSubLo)
1080  MI1New->getOperand(0).setIsKill(false);
1081  BuildMI(MBB, MI, DL, get(NewOpc))
1082  .add(MI.getOperand(0))
1083  // The Vectors are indexed in multiples of vector size.
1084  .addImm(MI.getOperand(1).getImm() + Offset)
1085  .addReg(SrcSubHi)
1087  MBB.erase(MI);
1088  return true;
1089  }
1090  case Hexagon::PS_vloadrw_ai:
1091  case Hexagon::PS_vloadrwu_ai: {
1092  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1093  unsigned DstReg = MI.getOperand(0).getReg();
1094  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1095  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1096 
1097  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1098  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1099  .add(MI.getOperand(1))
1100  .addImm(MI.getOperand(2).getImm())
1101  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1102  MI1New->getOperand(1).setIsKill(false);
1103  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1104  .add(MI.getOperand(1))
1105  // The Vectors are indexed in multiples of vector size.
1106  .addImm(MI.getOperand(2).getImm() + Offset)
1107  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1108  MBB.erase(MI);
1109  return true;
1110  }
1111  case Hexagon::PS_true: {
1112  unsigned Reg = MI.getOperand(0).getReg();
1113  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1114  .addReg(Reg, RegState::Undef)
1115  .addReg(Reg, RegState::Undef);
1116  MBB.erase(MI);
1117  return true;
1118  }
1119  case Hexagon::PS_false: {
1120  unsigned Reg = MI.getOperand(0).getReg();
1121  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1122  .addReg(Reg, RegState::Undef)
1123  .addReg(Reg, RegState::Undef);
1124  MBB.erase(MI);
1125  return true;
1126  }
1127  case Hexagon::PS_qtrue: {
1128  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1129  .addReg(Hexagon::V0, RegState::Undef)
1130  .addReg(Hexagon::V0, RegState::Undef);
1131  MBB.erase(MI);
1132  return true;
1133  }
1134  case Hexagon::PS_qfalse: {
1135  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1136  .addReg(Hexagon::V0, RegState::Undef)
1137  .addReg(Hexagon::V0, RegState::Undef);
1138  MBB.erase(MI);
1139  return true;
1140  }
1141  case Hexagon::PS_vmulw: {
1142  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1143  unsigned DstReg = MI.getOperand(0).getReg();
1144  unsigned Src1Reg = MI.getOperand(1).getReg();
1145  unsigned Src2Reg = MI.getOperand(2).getReg();
1146  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1147  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1148  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1149  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1150  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1151  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1152  .addReg(Src1SubHi)
1153  .addReg(Src2SubHi);
1154  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1155  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1156  .addReg(Src1SubLo)
1157  .addReg(Src2SubLo);
1158  MBB.erase(MI);
1159  MRI.clearKillFlags(Src1SubHi);
1160  MRI.clearKillFlags(Src1SubLo);
1161  MRI.clearKillFlags(Src2SubHi);
1162  MRI.clearKillFlags(Src2SubLo);
1163  return true;
1164  }
1165  case Hexagon::PS_vmulw_acc: {
1166  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1167  unsigned DstReg = MI.getOperand(0).getReg();
1168  unsigned Src1Reg = MI.getOperand(1).getReg();
1169  unsigned Src2Reg = MI.getOperand(2).getReg();
1170  unsigned Src3Reg = MI.getOperand(3).getReg();
1171  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1172  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1173  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1174  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1175  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1176  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1177  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1178  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1179  .addReg(Src1SubHi)
1180  .addReg(Src2SubHi)
1181  .addReg(Src3SubHi);
1182  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1183  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1184  .addReg(Src1SubLo)
1185  .addReg(Src2SubLo)
1186  .addReg(Src3SubLo);
1187  MBB.erase(MI);
1188  MRI.clearKillFlags(Src1SubHi);
1189  MRI.clearKillFlags(Src1SubLo);
1190  MRI.clearKillFlags(Src2SubHi);
1191  MRI.clearKillFlags(Src2SubLo);
1192  MRI.clearKillFlags(Src3SubHi);
1193  MRI.clearKillFlags(Src3SubLo);
1194  return true;
1195  }
1196  case Hexagon::PS_pselect: {
1197  const MachineOperand &Op0 = MI.getOperand(0);
1198  const MachineOperand &Op1 = MI.getOperand(1);
1199  const MachineOperand &Op2 = MI.getOperand(2);
1200  const MachineOperand &Op3 = MI.getOperand(3);
1201  unsigned Rd = Op0.getReg();
1202  unsigned Pu = Op1.getReg();
1203  unsigned Rs = Op2.getReg();
1204  unsigned Rt = Op3.getReg();
1205  DebugLoc DL = MI.getDebugLoc();
1206  unsigned K1 = getKillRegState(Op1.isKill());
1207  unsigned K2 = getKillRegState(Op2.isKill());
1208  unsigned K3 = getKillRegState(Op3.isKill());
1209  if (Rd != Rs)
1210  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1211  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1212  .addReg(Rs, K2);
1213  if (Rd != Rt)
1214  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1215  .addReg(Pu, K1)
1216  .addReg(Rt, K3);
1217  MBB.erase(MI);
1218  return true;
1219  }
1220  case Hexagon::PS_vselect: {
1221  const MachineOperand &Op0 = MI.getOperand(0);
1222  const MachineOperand &Op1 = MI.getOperand(1);
1223  const MachineOperand &Op2 = MI.getOperand(2);
1224  const MachineOperand &Op3 = MI.getOperand(3);
1225  LivePhysRegs LiveAtMI(HRI);
1226  getLiveRegsAt(LiveAtMI, MI);
1227  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1228  unsigned PReg = Op1.getReg();
1229  assert(Op1.getSubReg() == 0);
1230  unsigned PState = getRegState(Op1);
1231 
1232  if (Op0.getReg() != Op2.getReg()) {
1233  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1234  : PState;
1235  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1236  .add(Op0)
1237  .addReg(PReg, S)
1238  .add(Op2);
1239  if (IsDestLive)
1240  T.addReg(Op0.getReg(), RegState::Implicit);
1241  IsDestLive = true;
1242  }
1243  if (Op0.getReg() != Op3.getReg()) {
1244  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1245  .add(Op0)
1246  .addReg(PReg, PState)
1247  .add(Op3);
1248  if (IsDestLive)
1249  T.addReg(Op0.getReg(), RegState::Implicit);
1250  }
1251  MBB.erase(MI);
1252  return true;
1253  }
1254  case Hexagon::PS_wselect: {
1255  MachineOperand &Op0 = MI.getOperand(0);
1256  MachineOperand &Op1 = MI.getOperand(1);
1257  MachineOperand &Op2 = MI.getOperand(2);
1258  MachineOperand &Op3 = MI.getOperand(3);
1259  LivePhysRegs LiveAtMI(HRI);
1260  getLiveRegsAt(LiveAtMI, MI);
1261  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1262  unsigned PReg = Op1.getReg();
1263  assert(Op1.getSubReg() == 0);
1264  unsigned PState = getRegState(Op1);
1265 
1266  if (Op0.getReg() != Op2.getReg()) {
1267  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1268  : PState;
1269  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1270  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1271  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1272  .add(Op0)
1273  .addReg(PReg, S)
1274  .add(Op1)
1275  .addReg(SrcHi)
1276  .addReg(SrcLo);
1277  if (IsDestLive)
1278  T.addReg(Op0.getReg(), RegState::Implicit);
1279  IsDestLive = true;
1280  }
1281  if (Op0.getReg() != Op3.getReg()) {
1282  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1283  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1284  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1285  .add(Op0)
1286  .addReg(PReg, PState)
1287  .addReg(SrcHi)
1288  .addReg(SrcLo);
1289  if (IsDestLive)
1290  T.addReg(Op0.getReg(), RegState::Implicit);
1291  }
1292  MBB.erase(MI);
1293  return true;
1294  }
1295 
1296  case Hexagon::PS_tailcall_i:
1297  MI.setDesc(get(Hexagon::J2_jump));
1298  return true;
1299  case Hexagon::PS_tailcall_r:
1300  case Hexagon::PS_jmpret:
1301  MI.setDesc(get(Hexagon::J2_jumpr));
1302  return true;
1303  case Hexagon::PS_jmprett:
1304  MI.setDesc(get(Hexagon::J2_jumprt));
1305  return true;
1306  case Hexagon::PS_jmpretf:
1307  MI.setDesc(get(Hexagon::J2_jumprf));
1308  return true;
1309  case Hexagon::PS_jmprettnewpt:
1310  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1311  return true;
1312  case Hexagon::PS_jmpretfnewpt:
1313  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1314  return true;
1315  case Hexagon::PS_jmprettnew:
1316  MI.setDesc(get(Hexagon::J2_jumprtnew));
1317  return true;
1318  case Hexagon::PS_jmpretfnew:
1319  MI.setDesc(get(Hexagon::J2_jumprfnew));
1320  return true;
1321 
1322  case Hexagon::V6_vgathermh_pseudo:
1323  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1324  .add(MI.getOperand(1))
1325  .add(MI.getOperand(2))
1326  .add(MI.getOperand(3));
1327  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1328  .add(MI.getOperand(0))
1329  .addImm(0)
1330  .addReg(Hexagon::VTMP);
1331  MBB.erase(MI);
1332  return true;
1333 
1334  case Hexagon::V6_vgathermw_pseudo:
1335  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1336  .add(MI.getOperand(1))
1337  .add(MI.getOperand(2))
1338  .add(MI.getOperand(3));
1339  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1340  .add(MI.getOperand(0))
1341  .addImm(0)
1342  .addReg(Hexagon::VTMP);
1343  MBB.erase(MI);
1344  return true;
1345 
1346  case Hexagon::V6_vgathermhw_pseudo:
1347  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1348  .add(MI.getOperand(1))
1349  .add(MI.getOperand(2))
1350  .add(MI.getOperand(3));
1351  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1352  .add(MI.getOperand(0))
1353  .addImm(0)
1354  .addReg(Hexagon::VTMP);
1355  MBB.erase(MI);
1356  return true;
1357 
1358  case Hexagon::V6_vgathermhq_pseudo:
1359  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1360  .add(MI.getOperand(1))
1361  .add(MI.getOperand(2))
1362  .add(MI.getOperand(3))
1363  .add(MI.getOperand(4));
1364  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1365  .add(MI.getOperand(0))
1366  .addImm(0)
1367  .addReg(Hexagon::VTMP);
1368  MBB.erase(MI);
1369  return true;
1370 
1371  case Hexagon::V6_vgathermwq_pseudo:
1372  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1373  .add(MI.getOperand(1))
1374  .add(MI.getOperand(2))
1375  .add(MI.getOperand(3))
1376  .add(MI.getOperand(4));
1377  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1378  .add(MI.getOperand(0))
1379  .addImm(0)
1380  .addReg(Hexagon::VTMP);
1381  MBB.erase(MI);
1382  return true;
1383 
1384  case Hexagon::V6_vgathermhwq_pseudo:
1385  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1386  .add(MI.getOperand(1))
1387  .add(MI.getOperand(2))
1388  .add(MI.getOperand(3))
1389  .add(MI.getOperand(4));
1390  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1391  .add(MI.getOperand(0))
1392  .addImm(0)
1393  .addReg(Hexagon::VTMP);
1394  MBB.erase(MI);
1395  return true;
1396 
1397  }
1398 
1399  return false;
1400 }
1401 
1402 // We indicate that we want to reverse the branch by
1403 // inserting the reversed branching opcode.
1405  SmallVectorImpl<MachineOperand> &Cond) const {
1406  if (Cond.empty())
1407  return true;
1408  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1409  unsigned opcode = Cond[0].getImm();
1410  //unsigned temp;
1411  assert(get(opcode).isBranch() && "Should be a branching condition.");
1412  if (isEndLoopN(opcode))
1413  return true;
1414  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1415  Cond[0].setImm(NewOpcode);
1416  return false;
1417 }
1418 
1421  DebugLoc DL;
1422  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1423 }
1424 
1426  return getAddrMode(MI) == HexagonII::PostInc;
1427 }
1428 
1429 // Returns true if an instruction is predicated irrespective of the predicate
1430 // sense. For example, all of the following will return true.
1431 // if (p0) R1 = add(R2, R3)
1432 // if (!p0) R1 = add(R2, R3)
1433 // if (p0.new) R1 = add(R2, R3)
1434 // if (!p0.new) R1 = add(R2, R3)
1435 // Note: New-value stores are not included here as in the current
1436 // implementation, we don't need to check their predicate sense.
1438  const uint64_t F = MI.getDesc().TSFlags;
1440 }
1441 
1443  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1444  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1445  isEndLoopN(Cond[0].getImm())) {
1446  DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1447  return false;
1448  }
1449  int Opc = MI.getOpcode();
1450  assert (isPredicable(MI) && "Expected predicable instruction");
1451  bool invertJump = predOpcodeHasNot(Cond);
1452 
1453  // We have to predicate MI "in place", i.e. after this function returns,
1454  // MI will need to be transformed into a predicated form. To avoid com-
1455  // plicated manipulations with the operands (handling tied operands,
1456  // etc.), build a new temporary instruction, then overwrite MI with it.
1457 
1458  MachineBasicBlock &B = *MI.getParent();
1459  DebugLoc DL = MI.getDebugLoc();
1460  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1461  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1462  unsigned NOp = 0, NumOps = MI.getNumOperands();
1463  while (NOp < NumOps) {
1464  MachineOperand &Op = MI.getOperand(NOp);
1465  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1466  break;
1467  T.add(Op);
1468  NOp++;
1469  }
1470 
1471  unsigned PredReg, PredRegPos, PredRegFlags;
1472  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1473  (void)GotPredReg;
1474  assert(GotPredReg);
1475  T.addReg(PredReg, PredRegFlags);
1476  while (NOp < NumOps)
1477  T.add(MI.getOperand(NOp++));
1478 
1479  MI.setDesc(get(PredOpc));
1480  while (unsigned n = MI.getNumOperands())
1481  MI.RemoveOperand(n-1);
1482  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1483  MI.addOperand(T->getOperand(i));
1484 
1486  B.erase(TI);
1487 
1489  MRI.clearKillFlags(PredReg);
1490  return true;
1491 }
1492 
1494  ArrayRef<MachineOperand> Pred2) const {
1495  // TODO: Fix this
1496  return false;
1497 }
1498 
1500  std::vector<MachineOperand> &Pred) const {
1501  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1502 
1503  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1504  MachineOperand MO = MI.getOperand(oper);
1505  if (MO.isReg()) {
1506  if (!MO.isDef())
1507  continue;
1508  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1509  if (RC == &Hexagon::PredRegsRegClass) {
1510  Pred.push_back(MO);
1511  return true;
1512  }
1513  continue;
1514  } else if (MO.isRegMask()) {
1515  for (unsigned PR : Hexagon::PredRegsRegClass) {
1516  if (!MI.modifiesRegister(PR, &HRI))
1517  continue;
1518  Pred.push_back(MO);
1519  return true;
1520  }
1521  }
1522  }
1523  return false;
1524 }
1525 
1527  if (!MI.getDesc().isPredicable())
1528  return false;
1529 
1530  if (MI.isCall() || isTailCall(MI)) {
1531  if (!Subtarget.usePredicatedCalls())
1532  return false;
1533  }
1534 
1535  // HVX loads are not predicable on v60, but are on v62.
1536  if (!Subtarget.hasV62TOps()) {
1537  switch (MI.getOpcode()) {
1538  case Hexagon::V6_vL32b_ai:
1539  case Hexagon::V6_vL32b_pi:
1540  case Hexagon::V6_vL32b_ppu:
1541  case Hexagon::V6_vL32b_cur_ai:
1542  case Hexagon::V6_vL32b_cur_pi:
1543  case Hexagon::V6_vL32b_cur_ppu:
1544  case Hexagon::V6_vL32b_nt_ai:
1545  case Hexagon::V6_vL32b_nt_pi:
1546  case Hexagon::V6_vL32b_nt_ppu:
1547  case Hexagon::V6_vL32b_tmp_ai:
1548  case Hexagon::V6_vL32b_tmp_pi:
1549  case Hexagon::V6_vL32b_tmp_ppu:
1550  case Hexagon::V6_vL32b_nt_cur_ai:
1551  case Hexagon::V6_vL32b_nt_cur_pi:
1552  case Hexagon::V6_vL32b_nt_cur_ppu:
1553  case Hexagon::V6_vL32b_nt_tmp_ai:
1554  case Hexagon::V6_vL32b_nt_tmp_pi:
1555  case Hexagon::V6_vL32b_nt_tmp_ppu:
1556  return false;
1557  }
1558  }
1559  return true;
1560 }
1561 
1563  const MachineBasicBlock *MBB,
1564  const MachineFunction &MF) const {
1565  // Debug info is never a scheduling boundary. It's necessary to be explicit
1566  // due to the special treatment of IT instructions below, otherwise a
1567  // dbg_value followed by an IT will result in the IT instruction being
1568  // considered a scheduling hazard, which is wrong. It should be the actual
1569  // instruction preceding the dbg_value instruction(s), just like it is
1570  // when debug info is not present.
1571  if (MI.isDebugValue())
1572  return false;
1573 
1574  // Throwing call is a boundary.
1575  if (MI.isCall()) {
1576  // Don't mess around with no return calls.
1577  if (doesNotReturn(MI))
1578  return true;
1579  // If any of the block's successors is a landing pad, this could be a
1580  // throwing call.
1581  for (auto I : MBB->successors())
1582  if (I->isEHPad())
1583  return true;
1584  }
1585 
1586  // Terminators and labels can't be scheduled around.
1587  if (MI.getDesc().isTerminator() || MI.isPosition())
1588  return true;
1589 
1590  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1591  return true;
1592 
1593  return false;
1594 }
1595 
1596 /// Measure the specified inline asm to determine an approximation of its
1597 /// length.
1598 /// Comments (which run till the next SeparatorString or newline) do not
1599 /// count as an instruction.
1600 /// Any other non-whitespace text is considered an instruction, with
1601 /// multiple instructions separated by SeparatorString or newlines.
1602 /// Variable-length instructions are not handled here; this function
1603 /// may be overloaded in the target code to do that.
1604 /// Hexagon counts the number of ##'s and adjust for that many
1605 /// constant exenders.
1606 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1607  const MCAsmInfo &MAI) const {
1608  StringRef AStr(Str);
1609  // Count the number of instructions in the asm.
1610  bool atInsnStart = true;
1611  unsigned Length = 0;
1612  for (; *Str; ++Str) {
1613  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1614  strlen(MAI.getSeparatorString())) == 0)
1615  atInsnStart = true;
1616  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1617  Length += MAI.getMaxInstLength();
1618  atInsnStart = false;
1619  }
1620  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1621  MAI.getCommentString().size()) == 0)
1622  atInsnStart = false;
1623  }
1624 
1625  // Add to size number of constant extenders seen * 4.
1626  StringRef Occ("##");
1627  Length += AStr.count(Occ)*4;
1628  return Length;
1629 }
1630 
1633  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1634  if (UseDFAHazardRec)
1635  return new HexagonHazardRecognizer(II, this, Subtarget);
1637 }
1638 
1639 /// \brief For a comparison instruction, return the source registers in
1640 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1641 /// compares against in CmpValue. Return true if the comparison instruction
1642 /// can be analyzed.
1643 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1644  unsigned &SrcReg2, int &Mask,
1645  int &Value) const {
1646  unsigned Opc = MI.getOpcode();
1647 
1648  // Set mask and the first source register.
1649  switch (Opc) {
1650  case Hexagon::C2_cmpeq:
1651  case Hexagon::C2_cmpeqp:
1652  case Hexagon::C2_cmpgt:
1653  case Hexagon::C2_cmpgtp:
1654  case Hexagon::C2_cmpgtu:
1655  case Hexagon::C2_cmpgtup:
1656  case Hexagon::C4_cmpneq:
1657  case Hexagon::C4_cmplte:
1658  case Hexagon::C4_cmplteu:
1659  case Hexagon::C2_cmpeqi:
1660  case Hexagon::C2_cmpgti:
1661  case Hexagon::C2_cmpgtui:
1662  case Hexagon::C4_cmpneqi:
1663  case Hexagon::C4_cmplteui:
1664  case Hexagon::C4_cmpltei:
1665  SrcReg = MI.getOperand(1).getReg();
1666  Mask = ~0;
1667  break;
1668  case Hexagon::A4_cmpbeq:
1669  case Hexagon::A4_cmpbgt:
1670  case Hexagon::A4_cmpbgtu:
1671  case Hexagon::A4_cmpbeqi:
1672  case Hexagon::A4_cmpbgti:
1673  case Hexagon::A4_cmpbgtui:
1674  SrcReg = MI.getOperand(1).getReg();
1675  Mask = 0xFF;
1676  break;
1677  case Hexagon::A4_cmpheq:
1678  case Hexagon::A4_cmphgt:
1679  case Hexagon::A4_cmphgtu:
1680  case Hexagon::A4_cmpheqi:
1681  case Hexagon::A4_cmphgti:
1682  case Hexagon::A4_cmphgtui:
1683  SrcReg = MI.getOperand(1).getReg();
1684  Mask = 0xFFFF;
1685  break;
1686  }
1687 
1688  // Set the value/second source register.
1689  switch (Opc) {
1690  case Hexagon::C2_cmpeq:
1691  case Hexagon::C2_cmpeqp:
1692  case Hexagon::C2_cmpgt:
1693  case Hexagon::C2_cmpgtp:
1694  case Hexagon::C2_cmpgtu:
1695  case Hexagon::C2_cmpgtup:
1696  case Hexagon::A4_cmpbeq:
1697  case Hexagon::A4_cmpbgt:
1698  case Hexagon::A4_cmpbgtu:
1699  case Hexagon::A4_cmpheq:
1700  case Hexagon::A4_cmphgt:
1701  case Hexagon::A4_cmphgtu:
1702  case Hexagon::C4_cmpneq:
1703  case Hexagon::C4_cmplte:
1704  case Hexagon::C4_cmplteu:
1705  SrcReg2 = MI.getOperand(2).getReg();
1706  return true;
1707 
1708  case Hexagon::C2_cmpeqi:
1709  case Hexagon::C2_cmpgtui:
1710  case Hexagon::C2_cmpgti:
1711  case Hexagon::C4_cmpneqi:
1712  case Hexagon::C4_cmplteui:
1713  case Hexagon::C4_cmpltei:
1714  case Hexagon::A4_cmpbeqi:
1715  case Hexagon::A4_cmpbgti:
1716  case Hexagon::A4_cmpbgtui:
1717  case Hexagon::A4_cmpheqi:
1718  case Hexagon::A4_cmphgti:
1719  case Hexagon::A4_cmphgtui: {
1720  SrcReg2 = 0;
1721  const MachineOperand &Op2 = MI.getOperand(2);
1722  if (!Op2.isImm())
1723  return false;
1724  Value = MI.getOperand(2).getImm();
1725  return true;
1726  }
1727  }
1728 
1729  return false;
1730 }
1731 
1733  const MachineInstr &MI,
1734  unsigned *PredCost) const {
1735  return getInstrTimingClassLatency(ItinData, MI);
1736 }
1737 
1739  const TargetSubtargetInfo &STI) const {
1740  const InstrItineraryData *II = STI.getInstrItineraryData();
1741  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1742 }
1743 
1744 // Inspired by this pair:
1745 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1746 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1747 // Currently AA considers the addresses in these instructions to be aliasing.
1749  MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1750  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1752  return false;
1753 
1754  // Instructions that are pure loads, not loads and stores like memops are not
1755  // dependent.
1756  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1757  return true;
1758 
1759  // Get the base register in MIa.
1760  unsigned BasePosA, OffsetPosA;
1761  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1762  return false;
1763  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1764  unsigned BaseRegA = BaseA.getReg();
1765  unsigned BaseSubA = BaseA.getSubReg();
1766 
1767  // Get the base register in MIb.
1768  unsigned BasePosB, OffsetPosB;
1769  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1770  return false;
1771  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1772  unsigned BaseRegB = BaseB.getReg();
1773  unsigned BaseSubB = BaseB.getSubReg();
1774 
1775  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1776  return false;
1777 
1778  // Get the access sizes.
1779  unsigned SizeA = getMemAccessSize(MIa);
1780  unsigned SizeB = getMemAccessSize(MIb);
1781 
1782  // Get the offsets. Handle immediates only for now.
1783  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1784  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1785  if (!MIa.getOperand(OffsetPosA).isImm() ||
1786  !MIb.getOperand(OffsetPosB).isImm())
1787  return false;
1788  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1789  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1790 
1791  // This is a mem access with the same base register and known offsets from it.
1792  // Reason about it.
1793  if (OffsetA > OffsetB) {
1794  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1795  return SizeB <= OffDiff;
1796  }
1797  if (OffsetA < OffsetB) {
1798  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1799  return SizeA <= OffDiff;
1800  }
1801 
1802  return false;
1803 }
1804 
1805 /// If the instruction is an increment of a constant value, return the amount.
1807  int &Value) const {
1808  if (isPostIncrement(MI)) {
1809  unsigned BasePos = 0, OffsetPos = 0;
1810  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1811  return false;
1812  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1813  if (OffsetOp.isImm()) {
1814  Value = OffsetOp.getImm();
1815  return true;
1816  }
1817  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1818  const MachineOperand &AddOp = MI.getOperand(2);
1819  if (AddOp.isImm()) {
1820  Value = AddOp.getImm();
1821  return true;
1822  }
1823  }
1824 
1825  return false;
1826 }
1827 
1828 std::pair<unsigned, unsigned>
1830  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1831  TF & HexagonII::MO_Bitmasks);
1832 }
1833 
1836  using namespace HexagonII;
1837 
1838  static const std::pair<unsigned, const char*> Flags[] = {
1839  {MO_PCREL, "hexagon-pcrel"},
1840  {MO_GOT, "hexagon-got"},
1841  {MO_LO16, "hexagon-lo16"},
1842  {MO_HI16, "hexagon-hi16"},
1843  {MO_GPREL, "hexagon-gprel"},
1844  {MO_GDGOT, "hexagon-gdgot"},
1845  {MO_GDPLT, "hexagon-gdplt"},
1846  {MO_IE, "hexagon-ie"},
1847  {MO_IEGOT, "hexagon-iegot"},
1848  {MO_TPREL, "hexagon-tprel"}
1849  };
1850  return makeArrayRef(Flags);
1851 }
1852 
1855  using namespace HexagonII;
1856 
1857  static const std::pair<unsigned, const char*> Flags[] = {
1858  {HMOTF_ConstExtended, "hexagon-ext"}
1859  };
1860  return makeArrayRef(Flags);
1861 }
1862 
1865  const TargetRegisterClass *TRC;
1866  if (VT == MVT::i1) {
1867  TRC = &Hexagon::PredRegsRegClass;
1868  } else if (VT == MVT::i32 || VT == MVT::f32) {
1869  TRC = &Hexagon::IntRegsRegClass;
1870  } else if (VT == MVT::i64 || VT == MVT::f64) {
1871  TRC = &Hexagon::DoubleRegsRegClass;
1872  } else {
1873  llvm_unreachable("Cannot handle this register class");
1874  }
1875 
1876  unsigned NewReg = MRI.createVirtualRegister(TRC);
1877  return NewReg;
1878 }
1879 
1881  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1882 }
1883 
1885  const uint64_t F = MI.getDesc().TSFlags;
1887 }
1888 
1890  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
1891  !MI.getDesc().mayStore() &&
1892  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
1893  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
1894  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
1895 }
1896 
1897 // Return true if the instruction is a compund branch instruction.
1899  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1900 }
1901 
1902 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1903 // isFPImm and later getFPImm as well.
1905  const uint64_t F = MI.getDesc().TSFlags;
1907  if (isExtended) // Instruction must be extended.
1908  return true;
1909 
1910  unsigned isExtendable =
1912  if (!isExtendable)
1913  return false;
1914 
1915  if (MI.isCall())
1916  return false;
1917 
1918  short ExtOpNum = getCExtOpNum(MI);
1919  const MachineOperand &MO = MI.getOperand(ExtOpNum);
1920  // Use MO operand flags to determine if MO
1921  // has the HMOTF_ConstExtended flag set.
1923  return true;
1924  // If this is a Machine BB address we are talking about, and it is
1925  // not marked as extended, say so.
1926  if (MO.isMBB())
1927  return false;
1928 
1929  // We could be using an instruction with an extendable immediate and shoehorn
1930  // a global address into it. If it is a global address it will be constant
1931  // extended. We do this for COMBINE.
1932  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1933  MO.isJTI() || MO.isCPI() || MO.isFPImm())
1934  return true;
1935 
1936  // If the extendable operand is not 'Immediate' type, the instruction should
1937  // have 'isExtended' flag set.
1938  assert(MO.isImm() && "Extendable operand must be Immediate type");
1939 
1940  int MinValue = getMinValue(MI);
1941  int MaxValue = getMaxValue(MI);
1942  int ImmValue = MO.getImm();
1943 
1944  return (ImmValue < MinValue || ImmValue > MaxValue);
1945 }
1946 
1948  switch (MI.getOpcode()) {
1949  case Hexagon::L4_return:
1950  case Hexagon::L4_return_t:
1951  case Hexagon::L4_return_f:
1952  case Hexagon::L4_return_tnew_pnt:
1953  case Hexagon::L4_return_fnew_pnt:
1954  case Hexagon::L4_return_tnew_pt:
1955  case Hexagon::L4_return_fnew_pt:
1956  return true;
1957  }
1958  return false;
1959 }
1960 
1961 // Return true when ConsMI uses a register defined by ProdMI.
1963  const MachineInstr &ConsMI) const {
1964  if (!ProdMI.getDesc().getNumDefs())
1965  return false;
1966  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1967 
1972 
1973  parseOperands(ProdMI, DefsA, UsesA);
1974  parseOperands(ConsMI, DefsB, UsesB);
1975 
1976  for (auto &RegA : DefsA)
1977  for (auto &RegB : UsesB) {
1978  // True data dependency.
1979  if (RegA == RegB)
1980  return true;
1981 
1983  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1984  if (RegB == *SubRegs)
1985  return true;
1986 
1988  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1989  if (RegA == *SubRegs)
1990  return true;
1991  }
1992 
1993  return false;
1994 }
1995 
1996 // Returns true if the instruction is alread a .cur.
1998  switch (MI.getOpcode()) {
1999  case Hexagon::V6_vL32b_cur_pi:
2000  case Hexagon::V6_vL32b_cur_ai:
2001  return true;
2002  }
2003  return false;
2004 }
2005 
2006 // Returns true, if any one of the operands is a dot new
2007 // insn, whether it is predicated dot new or register dot new.
2009  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2010  return true;
2011 
2012  return false;
2013 }
2014 
2015 /// Symmetrical. See if these two instructions are fit for duplex pair.
2017  const MachineInstr &MIb) const {
2020  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2021 }
2022 
2024  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2025  return true;
2026 
2027  // Multiply
2028  unsigned SchedClass = MI.getDesc().getSchedClass();
2029  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2030 }
2031 
2032 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2033  return (Opcode == Hexagon::ENDLOOP0 ||
2034  Opcode == Hexagon::ENDLOOP1);
2035 }
2036 
2037 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2038  switch(OpType) {
2045  return true;
2046  default:
2047  return false;
2048  }
2049 }
2050 
2052  const MCInstrDesc &MID = MI.getDesc();
2053  const uint64_t F = MID.TSFlags;
2055  return true;
2056 
2057  // TODO: This is largely obsolete now. Will need to be removed
2058  // in consecutive patches.
2059  switch (MI.getOpcode()) {
2060  // PS_fi and PS_fia remain special cases.
2061  case Hexagon::PS_fi:
2062  case Hexagon::PS_fia:
2063  return true;
2064  default:
2065  return false;
2066  }
2067  return false;
2068 }
2069 
2070 // This returns true in two cases:
2071 // - The OP code itself indicates that this is an extended instruction.
2072 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2074  // First check if this is permanently extended op code.
2075  const uint64_t F = MI.getDesc().TSFlags;
2077  return true;
2078  // Use MO operand flags to determine if one of MI's operands
2079  // has HMOTF_ConstExtended flag set.
2080  for (const MachineOperand &MO : MI.operands())
2081  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2082  return true;
2083  return false;
2084 }
2085 
2087  unsigned Opcode = MI.getOpcode();
2088  const uint64_t F = get(Opcode).TSFlags;
2089  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2090 }
2091 
2092 // No V60 HVX VMEM with A_INDIRECT.
2094  const MachineInstr &J) const {
2095  if (!isHVXVec(I))
2096  return false;
2097  if (!I.mayLoad() && !I.mayStore())
2098  return false;
2099  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2100 }
2101 
2103  switch (MI.getOpcode()) {
2104  case Hexagon::J2_callr:
2105  case Hexagon::J2_callrf:
2106  case Hexagon::J2_callrt:
2107  case Hexagon::PS_call_nr:
2108  return true;
2109  }
2110  return false;
2111 }
2112 
2114  switch (MI.getOpcode()) {
2115  case Hexagon::L4_return:
2116  case Hexagon::L4_return_t:
2117  case Hexagon::L4_return_f:
2118  case Hexagon::L4_return_fnew_pnt:
2119  case Hexagon::L4_return_fnew_pt:
2120  case Hexagon::L4_return_tnew_pnt:
2121  case Hexagon::L4_return_tnew_pt:
2122  return true;
2123  }
2124  return false;
2125 }
2126 
2128  switch (MI.getOpcode()) {
2129  case Hexagon::J2_jumpr:
2130  case Hexagon::J2_jumprt:
2131  case Hexagon::J2_jumprf:
2132  case Hexagon::J2_jumprtnewpt:
2133  case Hexagon::J2_jumprfnewpt:
2134  case Hexagon::J2_jumprtnew:
2135  case Hexagon::J2_jumprfnew:
2136  return true;
2137  }
2138  return false;
2139 }
2140 
2141 // Return true if a given MI can accommodate given offset.
2142 // Use abs estimate as oppose to the exact number.
2143 // TODO: This will need to be changed to use MC level
2144 // definition of instruction extendable field size.
2146  unsigned offset) const {
2147  // This selection of jump instructions matches to that what
2148  // analyzeBranch can parse, plus NVJ.
2149  if (isNewValueJump(MI)) // r9:2
2150  return isInt<11>(offset);
2151 
2152  switch (MI.getOpcode()) {
2153  // Still missing Jump to address condition on register value.
2154  default:
2155  return false;
2156  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2157  case Hexagon::J2_call:
2158  case Hexagon::PS_call_nr:
2159  return isInt<24>(offset);
2160  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2161  case Hexagon::J2_jumpf:
2162  case Hexagon::J2_jumptnew:
2163  case Hexagon::J2_jumptnewpt:
2164  case Hexagon::J2_jumpfnew:
2165  case Hexagon::J2_jumpfnewpt:
2166  case Hexagon::J2_callt:
2167  case Hexagon::J2_callf:
2168  return isInt<17>(offset);
2169  case Hexagon::J2_loop0i:
2170  case Hexagon::J2_loop0iext:
2171  case Hexagon::J2_loop0r:
2172  case Hexagon::J2_loop0rext:
2173  case Hexagon::J2_loop1i:
2174  case Hexagon::J2_loop1iext:
2175  case Hexagon::J2_loop1r:
2176  case Hexagon::J2_loop1rext:
2177  return isInt<9>(offset);
2178  // TODO: Add all the compound branches here. Can we do this in Relation model?
2179  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2180  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2181  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2182  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2183  return isInt<11>(offset);
2184  }
2185 }
2186 
2188  const MachineInstr &ESMI) const {
2189  bool isLate = isLateResultInstr(LRMI);
2190  bool isEarly = isEarlySourceInstr(ESMI);
2191 
2192  DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2193  DEBUG(LRMI.dump());
2194  DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2195  DEBUG(ESMI.dump());
2196 
2197  if (isLate && isEarly) {
2198  DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2199  return true;
2200  }
2201 
2202  return false;
2203 }
2204 
2206  switch (MI.getOpcode()) {
2207  case TargetOpcode::EXTRACT_SUBREG:
2208  case TargetOpcode::INSERT_SUBREG:
2209  case TargetOpcode::SUBREG_TO_REG:
2210  case TargetOpcode::REG_SEQUENCE:
2211  case TargetOpcode::IMPLICIT_DEF:
2212  case TargetOpcode::COPY:
2214  case TargetOpcode::PHI:
2215  return false;
2216  default:
2217  break;
2218  }
2219 
2220  unsigned SchedClass = MI.getDesc().getSchedClass();
2221  return !is_TC1(SchedClass);
2222 }
2223 
2225  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2226  // resource, but all operands can be received late like an ALU instruction.
2227  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2228 }
2229 
2231  unsigned Opcode = MI.getOpcode();
2232  return Opcode == Hexagon::J2_loop0i ||
2233  Opcode == Hexagon::J2_loop0r ||
2234  Opcode == Hexagon::J2_loop0iext ||
2235  Opcode == Hexagon::J2_loop0rext ||
2236  Opcode == Hexagon::J2_loop1i ||
2237  Opcode == Hexagon::J2_loop1r ||
2238  Opcode == Hexagon::J2_loop1iext ||
2239  Opcode == Hexagon::J2_loop1rext;
2240 }
2241 
2243  switch (MI.getOpcode()) {
2244  default: return false;
2245  case Hexagon::L4_iadd_memopw_io:
2246  case Hexagon::L4_isub_memopw_io:
2247  case Hexagon::L4_add_memopw_io:
2248  case Hexagon::L4_sub_memopw_io:
2249  case Hexagon::L4_and_memopw_io:
2250  case Hexagon::L4_or_memopw_io:
2251  case Hexagon::L4_iadd_memoph_io:
2252  case Hexagon::L4_isub_memoph_io:
2253  case Hexagon::L4_add_memoph_io:
2254  case Hexagon::L4_sub_memoph_io:
2255  case Hexagon::L4_and_memoph_io:
2256  case Hexagon::L4_or_memoph_io:
2257  case Hexagon::L4_iadd_memopb_io:
2258  case Hexagon::L4_isub_memopb_io:
2259  case Hexagon::L4_add_memopb_io:
2260  case Hexagon::L4_sub_memopb_io:
2261  case Hexagon::L4_and_memopb_io:
2262  case Hexagon::L4_or_memopb_io:
2263  case Hexagon::L4_ior_memopb_io:
2264  case Hexagon::L4_ior_memoph_io:
2265  case Hexagon::L4_ior_memopw_io:
2266  case Hexagon::L4_iand_memopb_io:
2267  case Hexagon::L4_iand_memoph_io:
2268  case Hexagon::L4_iand_memopw_io:
2269  return true;
2270  }
2271  return false;
2272 }
2273 
2275  const uint64_t F = MI.getDesc().TSFlags;
2277 }
2278 
2279 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2280  const uint64_t F = get(Opcode).TSFlags;
2282 }
2283 
2285  return isNewValueJump(MI) || isNewValueStore(MI);
2286 }
2287 
2289  return isNewValue(MI) && MI.isBranch();
2290 }
2291 
2292 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2293  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2294 }
2295 
2297  const uint64_t F = MI.getDesc().TSFlags;
2299 }
2300 
2301 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2302  const uint64_t F = get(Opcode).TSFlags;
2304 }
2305 
2306 // Returns true if a particular operand is extendable for an instruction.
2308  unsigned OperandNum) const {
2309  const uint64_t F = MI.getDesc().TSFlags;
2311  == OperandNum;
2312 }
2313 
2315  const uint64_t F = MI.getDesc().TSFlags;
2316  assert(isPredicated(MI));
2318 }
2319 
2320 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2321  const uint64_t F = get(Opcode).TSFlags;
2322  assert(isPredicated(Opcode));
2324 }
2325 
2327  const uint64_t F = MI.getDesc().TSFlags;
2328  return !((F >> HexagonII::PredicatedFalsePos) &
2330 }
2331 
2332 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2333  const uint64_t F = get(Opcode).TSFlags;
2334  // Make sure that the instruction is predicated.
2336  return !((F >> HexagonII::PredicatedFalsePos) &
2338 }
2339 
2340 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2341  const uint64_t F = get(Opcode).TSFlags;
2343 }
2344 
2345 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2346  const uint64_t F = get(Opcode).TSFlags;
2348 }
2349 
2350 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2351  const uint64_t F = get(Opcode).TSFlags;
2352  assert(get(Opcode).isBranch() &&
2353  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2354  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2355 }
2356 
2358  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2359  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2360  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2361  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2362 }
2363 
2365  switch (MI.getOpcode()) {
2366  // Byte
2367  case Hexagon::L2_loadrb_io:
2368  case Hexagon::L4_loadrb_ur:
2369  case Hexagon::L4_loadrb_ap:
2370  case Hexagon::L2_loadrb_pr:
2371  case Hexagon::L2_loadrb_pbr:
2372  case Hexagon::L2_loadrb_pi:
2373  case Hexagon::L2_loadrb_pci:
2374  case Hexagon::L2_loadrb_pcr:
2375  case Hexagon::L2_loadbsw2_io:
2376  case Hexagon::L4_loadbsw2_ur:
2377  case Hexagon::L4_loadbsw2_ap:
2378  case Hexagon::L2_loadbsw2_pr:
2379  case Hexagon::L2_loadbsw2_pbr:
2380  case Hexagon::L2_loadbsw2_pi:
2381  case Hexagon::L2_loadbsw2_pci:
2382  case Hexagon::L2_loadbsw2_pcr:
2383  case Hexagon::L2_loadbsw4_io:
2384  case Hexagon::L4_loadbsw4_ur:
2385  case Hexagon::L4_loadbsw4_ap:
2386  case Hexagon::L2_loadbsw4_pr:
2387  case Hexagon::L2_loadbsw4_pbr:
2388  case Hexagon::L2_loadbsw4_pi:
2389  case Hexagon::L2_loadbsw4_pci:
2390  case Hexagon::L2_loadbsw4_pcr:
2391  case Hexagon::L4_loadrb_rr:
2392  case Hexagon::L2_ploadrbt_io:
2393  case Hexagon::L2_ploadrbt_pi:
2394  case Hexagon::L2_ploadrbf_io:
2395  case Hexagon::L2_ploadrbf_pi:
2396  case Hexagon::L2_ploadrbtnew_io:
2397  case Hexagon::L2_ploadrbfnew_io:
2398  case Hexagon::L4_ploadrbt_rr:
2399  case Hexagon::L4_ploadrbf_rr:
2400  case Hexagon::L4_ploadrbtnew_rr:
2401  case Hexagon::L4_ploadrbfnew_rr:
2402  case Hexagon::L2_ploadrbtnew_pi:
2403  case Hexagon::L2_ploadrbfnew_pi:
2404  case Hexagon::L4_ploadrbt_abs:
2405  case Hexagon::L4_ploadrbf_abs:
2406  case Hexagon::L4_ploadrbtnew_abs:
2407  case Hexagon::L4_ploadrbfnew_abs:
2408  case Hexagon::L2_loadrbgp:
2409  // Half
2410  case Hexagon::L2_loadrh_io:
2411  case Hexagon::L4_loadrh_ur:
2412  case Hexagon::L4_loadrh_ap:
2413  case Hexagon::L2_loadrh_pr:
2414  case Hexagon::L2_loadrh_pbr:
2415  case Hexagon::L2_loadrh_pi:
2416  case Hexagon::L2_loadrh_pci:
2417  case Hexagon::L2_loadrh_pcr:
2418  case Hexagon::L4_loadrh_rr:
2419  case Hexagon::L2_ploadrht_io:
2420  case Hexagon::L2_ploadrht_pi:
2421  case Hexagon::L2_ploadrhf_io:
2422  case Hexagon::L2_ploadrhf_pi:
2423  case Hexagon::L2_ploadrhtnew_io:
2424  case Hexagon::L2_ploadrhfnew_io:
2425  case Hexagon::L4_ploadrht_rr:
2426  case Hexagon::L4_ploadrhf_rr:
2427  case Hexagon::L4_ploadrhtnew_rr:
2428  case Hexagon::L4_ploadrhfnew_rr:
2429  case Hexagon::L2_ploadrhtnew_pi:
2430  case Hexagon::L2_ploadrhfnew_pi:
2431  case Hexagon::L4_ploadrht_abs:
2432  case Hexagon::L4_ploadrhf_abs:
2433  case Hexagon::L4_ploadrhtnew_abs:
2434  case Hexagon::L4_ploadrhfnew_abs:
2435  case Hexagon::L2_loadrhgp:
2436  return true;
2437  default:
2438  return false;
2439  }
2440 }
2441 
2443  const uint64_t F = MI.getDesc().TSFlags;
2444  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2445 }
2446 
2448  switch (MI.getOpcode()) {
2449  case Hexagon::STriw_pred:
2450  case Hexagon::LDriw_pred:
2451  return true;
2452  default:
2453  return false;
2454  }
2455 }
2456 
2458  if (!MI.isBranch())
2459  return false;
2460 
2461  for (auto &Op : MI.operands())
2462  if (Op.isGlobal() || Op.isSymbol())
2463  return true;
2464  return false;
2465 }
2466 
2467 // Returns true when SU has a timing class TC1.
2469  unsigned SchedClass = MI.getDesc().getSchedClass();
2470  return is_TC1(SchedClass);
2471 }
2472 
2474  unsigned SchedClass = MI.getDesc().getSchedClass();
2475  return is_TC2(SchedClass);
2476 }
2477 
2479  unsigned SchedClass = MI.getDesc().getSchedClass();
2480  return is_TC2early(SchedClass);
2481 }
2482 
2484  unsigned SchedClass = MI.getDesc().getSchedClass();
2485  return is_TC4x(SchedClass);
2486 }
2487 
2488 // Schedule this ASAP.
2490  const MachineInstr &MI2) const {
2491  if (mayBeCurLoad(MI1)) {
2492  // if (result of SU is used in Next) return true;
2493  unsigned DstReg = MI1.getOperand(0).getReg();
2494  int N = MI2.getNumOperands();
2495  for (int I = 0; I < N; I++)
2496  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2497  return true;
2498  }
2499  if (mayBeNewStore(MI2))
2500  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2501  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2502  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2503  return true;
2504  return false;
2505 }
2506 
2508  const uint64_t V = getType(MI);
2510 }
2511 
2512 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2514  int Size = VT.getSizeInBits() / 8;
2515  if (Offset % Size != 0)
2516  return false;
2517  int Count = Offset / Size;
2518 
2519  switch (VT.getSimpleVT().SimpleTy) {
2520  // For scalars the auto-inc is s4
2521  case MVT::i8:
2522  case MVT::i16:
2523  case MVT::i32:
2524  case MVT::i64:
2525  return isInt<4>(Count);
2526  // For HVX vectors the auto-inc is s3
2527  case MVT::v64i8:
2528  case MVT::v32i16:
2529  case MVT::v16i32:
2530  case MVT::v8i64:
2531  case MVT::v128i8:
2532  case MVT::v64i16:
2533  case MVT::v32i32:
2534  case MVT::v16i64:
2535  return isInt<3>(Count);
2536  default:
2537  break;
2538  }
2539 
2540  llvm_unreachable("Not an valid type!");
2541 }
2542 
2543 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2544  const TargetRegisterInfo *TRI, bool Extend) const {
2545  // This function is to check whether the "Offset" is in the correct range of
2546  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2547  // inserted to calculate the final address. Due to this reason, the function
2548  // assumes that the "Offset" has correct alignment.
2549  // We used to assert if the offset was not properly aligned, however,
2550  // there are cases where a misaligned pointer recast can cause this
2551  // problem, and we need to allow for it. The front end warns of such
2552  // misaligns with respect to load size.
2553  switch (Opcode) {
2554  case Hexagon::PS_vstorerq_ai:
2555  case Hexagon::PS_vstorerw_ai:
2556  case Hexagon::PS_vstorerw_nt_ai:
2557  case Hexagon::PS_vloadrq_ai:
2558  case Hexagon::PS_vloadrw_ai:
2559  case Hexagon::PS_vloadrw_nt_ai:
2560  case Hexagon::V6_vL32b_ai:
2561  case Hexagon::V6_vS32b_ai:
2562  case Hexagon::V6_vL32b_nt_ai:
2563  case Hexagon::V6_vS32b_nt_ai:
2564  case Hexagon::V6_vL32Ub_ai:
2565  case Hexagon::V6_vS32Ub_ai: {
2566  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2567  assert(isPowerOf2_32(VectorSize));
2568  if (Offset & (VectorSize-1))
2569  return false;
2570  return isInt<4>(Offset >> Log2_32(VectorSize));
2571  }
2572 
2573  case Hexagon::J2_loop0i:
2574  case Hexagon::J2_loop1i:
2575  return isUInt<10>(Offset);
2576 
2577  case Hexagon::S4_storeirb_io:
2578  case Hexagon::S4_storeirbt_io:
2579  case Hexagon::S4_storeirbf_io:
2580  return isUInt<6>(Offset);
2581 
2582  case Hexagon::S4_storeirh_io:
2583  case Hexagon::S4_storeirht_io:
2584  case Hexagon::S4_storeirhf_io:
2585  return isShiftedUInt<6,1>(Offset);
2586 
2587  case Hexagon::S4_storeiri_io:
2588  case Hexagon::S4_storeirit_io:
2589  case Hexagon::S4_storeirif_io:
2590  return isShiftedUInt<6,2>(Offset);
2591  }
2592 
2593  if (Extend)
2594  return true;
2595 
2596  switch (Opcode) {
2597  case Hexagon::L2_loadri_io:
2598  case Hexagon::S2_storeri_io:
2599  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2600  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2601 
2602  case Hexagon::L2_loadrd_io:
2603  case Hexagon::S2_storerd_io:
2604  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2605  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2606 
2607  case Hexagon::L2_loadrh_io:
2608  case Hexagon::L2_loadruh_io:
2609  case Hexagon::S2_storerh_io:
2610  case Hexagon::S2_storerf_io:
2611  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2612  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2613 
2614  case Hexagon::L2_loadrb_io:
2615  case Hexagon::L2_loadrub_io:
2616  case Hexagon::S2_storerb_io:
2617  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2618  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2619 
2620  case Hexagon::A2_addi:
2621  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2622  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2623 
2624  case Hexagon::L4_iadd_memopw_io:
2625  case Hexagon::L4_isub_memopw_io:
2626  case Hexagon::L4_add_memopw_io:
2627  case Hexagon::L4_sub_memopw_io:
2628  case Hexagon::L4_and_memopw_io:
2629  case Hexagon::L4_or_memopw_io:
2630  return (0 <= Offset && Offset <= 255);
2631 
2632  case Hexagon::L4_iadd_memoph_io:
2633  case Hexagon::L4_isub_memoph_io:
2634  case Hexagon::L4_add_memoph_io:
2635  case Hexagon::L4_sub_memoph_io:
2636  case Hexagon::L4_and_memoph_io:
2637  case Hexagon::L4_or_memoph_io:
2638  return (0 <= Offset && Offset <= 127);
2639 
2640  case Hexagon::L4_iadd_memopb_io:
2641  case Hexagon::L4_isub_memopb_io:
2642  case Hexagon::L4_add_memopb_io:
2643  case Hexagon::L4_sub_memopb_io:
2644  case Hexagon::L4_and_memopb_io:
2645  case Hexagon::L4_or_memopb_io:
2646  return (0 <= Offset && Offset <= 63);
2647 
2648  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2649  // any size. Later pass knows how to handle it.
2650  case Hexagon::STriw_pred:
2651  case Hexagon::LDriw_pred:
2652  case Hexagon::STriw_mod:
2653  case Hexagon::LDriw_mod:
2654  return true;
2655 
2656  case Hexagon::PS_fi:
2657  case Hexagon::PS_fia:
2658  case Hexagon::INLINEASM:
2659  return true;
2660 
2661  case Hexagon::L2_ploadrbt_io:
2662  case Hexagon::L2_ploadrbf_io:
2663  case Hexagon::L2_ploadrubt_io:
2664  case Hexagon::L2_ploadrubf_io:
2665  case Hexagon::S2_pstorerbt_io:
2666  case Hexagon::S2_pstorerbf_io:
2667  return isUInt<6>(Offset);
2668 
2669  case Hexagon::L2_ploadrht_io:
2670  case Hexagon::L2_ploadrhf_io:
2671  case Hexagon::L2_ploadruht_io:
2672  case Hexagon::L2_ploadruhf_io:
2673  case Hexagon::S2_pstorerht_io:
2674  case Hexagon::S2_pstorerhf_io:
2675  return isShiftedUInt<6,1>(Offset);
2676 
2677  case Hexagon::L2_ploadrit_io:
2678  case Hexagon::L2_ploadrif_io:
2679  case Hexagon::S2_pstorerit_io:
2680  case Hexagon::S2_pstorerif_io:
2681  return isShiftedUInt<6,2>(Offset);
2682 
2683  case Hexagon::L2_ploadrdt_io:
2684  case Hexagon::L2_ploadrdf_io:
2685  case Hexagon::S2_pstorerdt_io:
2686  case Hexagon::S2_pstorerdf_io:
2687  return isShiftedUInt<6,3>(Offset);
2688  } // switch
2689 
2690  llvm_unreachable("No offset range is defined for this opcode. "
2691  "Please define it in the above switch statement!");
2692 }
2693 
2695  return isHVXVec(MI) && isAccumulator(MI);
2696 }
2697 
2699  const uint64_t F = get(MI.getOpcode()).TSFlags;
2700  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2701  return
2702  V == HexagonII::TypeCVI_VA ||
2704 }
2705 
2707  const MachineInstr &ConsMI) const {
2708  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2709  return true;
2710 
2711  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2712  return true;
2713 
2714  if (mayBeNewStore(ConsMI))
2715  return true;
2716 
2717  return false;
2718 }
2719 
2721  switch (MI.getOpcode()) {
2722  // Byte
2723  case Hexagon::L2_loadrub_io:
2724  case Hexagon::L4_loadrub_ur:
2725  case Hexagon::L4_loadrub_ap:
2726  case Hexagon::L2_loadrub_pr:
2727  case Hexagon::L2_loadrub_pbr:
2728  case Hexagon::L2_loadrub_pi:
2729  case Hexagon::L2_loadrub_pci:
2730  case Hexagon::L2_loadrub_pcr:
2731  case Hexagon::L2_loadbzw2_io:
2732  case Hexagon::L4_loadbzw2_ur:
2733  case Hexagon::L4_loadbzw2_ap:
2734  case Hexagon::L2_loadbzw2_pr:
2735  case Hexagon::L2_loadbzw2_pbr:
2736  case Hexagon::L2_loadbzw2_pi:
2737  case Hexagon::L2_loadbzw2_pci:
2738  case Hexagon::L2_loadbzw2_pcr:
2739  case Hexagon::L2_loadbzw4_io:
2740  case Hexagon::L4_loadbzw4_ur:
2741  case Hexagon::L4_loadbzw4_ap:
2742  case Hexagon::L2_loadbzw4_pr:
2743  case Hexagon::L2_loadbzw4_pbr:
2744  case Hexagon::L2_loadbzw4_pi:
2745  case Hexagon::L2_loadbzw4_pci:
2746  case Hexagon::L2_loadbzw4_pcr:
2747  case Hexagon::L4_loadrub_rr:
2748  case Hexagon::L2_ploadrubt_io:
2749  case Hexagon::L2_ploadrubt_pi:
2750  case Hexagon::L2_ploadrubf_io:
2751  case Hexagon::L2_ploadrubf_pi:
2752  case Hexagon::L2_ploadrubtnew_io:
2753  case Hexagon::L2_ploadrubfnew_io:
2754  case Hexagon::L4_ploadrubt_rr:
2755  case Hexagon::L4_ploadrubf_rr:
2756  case Hexagon::L4_ploadrubtnew_rr:
2757  case Hexagon::L4_ploadrubfnew_rr:
2758  case Hexagon::L2_ploadrubtnew_pi:
2759  case Hexagon::L2_ploadrubfnew_pi:
2760  case Hexagon::L4_ploadrubt_abs:
2761  case Hexagon::L4_ploadrubf_abs:
2762  case Hexagon::L4_ploadrubtnew_abs:
2763  case Hexagon::L4_ploadrubfnew_abs:
2764  case Hexagon::L2_loadrubgp:
2765  // Half
2766  case Hexagon::L2_loadruh_io:
2767  case Hexagon::L4_loadruh_ur:
2768  case Hexagon::L4_loadruh_ap:
2769  case Hexagon::L2_loadruh_pr:
2770  case Hexagon::L2_loadruh_pbr:
2771  case Hexagon::L2_loadruh_pi:
2772  case Hexagon::L2_loadruh_pci:
2773  case Hexagon::L2_loadruh_pcr:
2774  case Hexagon::L4_loadruh_rr:
2775  case Hexagon::L2_ploadruht_io:
2776  case Hexagon::L2_ploadruht_pi:
2777  case Hexagon::L2_ploadruhf_io:
2778  case Hexagon::L2_ploadruhf_pi:
2779  case Hexagon::L2_ploadruhtnew_io:
2780  case Hexagon::L2_ploadruhfnew_io:
2781  case Hexagon::L4_ploadruht_rr:
2782  case Hexagon::L4_ploadruhf_rr:
2783  case Hexagon::L4_ploadruhtnew_rr:
2784  case Hexagon::L4_ploadruhfnew_rr:
2785  case Hexagon::L2_ploadruhtnew_pi:
2786  case Hexagon::L2_ploadruhfnew_pi:
2787  case Hexagon::L4_ploadruht_abs:
2788  case Hexagon::L4_ploadruhf_abs:
2789  case Hexagon::L4_ploadruhtnew_abs:
2790  case Hexagon::L4_ploadruhfnew_abs:
2791  case Hexagon::L2_loadruhgp:
2792  return true;
2793  default:
2794  return false;
2795  }
2796 }
2797 
2798 // Add latency to instruction.
2800  const MachineInstr &MI2) const {
2801  if (isHVXVec(MI1) && isHVXVec(MI2))
2802  if (!isVecUsableNextPacket(MI1, MI2))
2803  return true;
2804  return false;
2805 }
2806 
2807 /// \brief Get the base register and byte offset of a load/store instr.
2809  unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2810  const {
2811  unsigned AccessSize = 0;
2812  int OffsetVal = 0;
2813  BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2814  Offset = OffsetVal;
2815  return BaseReg != 0;
2816 }
2817 
2818 /// \brief Can these instructions execute at the same time in a bundle.
2820  const MachineInstr &Second) const {
2821  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2822  const MachineOperand &Op = Second.getOperand(0);
2823  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2824  return true;
2825  }
2826  if (DisableNVSchedule)
2827  return false;
2828  if (mayBeNewStore(Second)) {
2829  // Make sure the definition of the first instruction is the value being
2830  // stored.
2831  const MachineOperand &Stored =
2832  Second.getOperand(Second.getNumOperands() - 1);
2833  if (!Stored.isReg())
2834  return false;
2835  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2836  const MachineOperand &Op = First.getOperand(i);
2837  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2838  return true;
2839  }
2840  }
2841  return false;
2842 }
2843 
2845  unsigned Opc = CallMI.getOpcode();
2846  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2847 }
2848 
2850  for (auto &I : *B)
2851  if (I.isEHLabel())
2852  return true;
2853  return false;
2854 }
2855 
2856 // Returns true if an instruction can be converted into a non-extended
2857 // equivalent instruction.
2859  short NonExtOpcode;
2860  // Check if the instruction has a register form that uses register in place
2861  // of the extended operand, if so return that as the non-extended form.
2862  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2863  return true;
2864 
2865  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2866  // Check addressing mode and retrieve non-ext equivalent instruction.
2867 
2868  switch (getAddrMode(MI)) {
2869  case HexagonII::Absolute:
2870  // Load/store with absolute addressing mode can be converted into
2871  // base+offset mode.
2872  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2873  break;
2875  // Load/store with base+offset addressing mode can be converted into
2876  // base+register offset addressing mode. However left shift operand should
2877  // be set to 0.
2878  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
2879  break;
2881  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
2882  break;
2883  default:
2884  return false;
2885  }
2886  if (NonExtOpcode < 0)
2887  return false;
2888  return true;
2889  }
2890  return false;
2891 }
2892 
2894  return Hexagon::getRealHWInstr(MI.getOpcode(),
2895  Hexagon::InstrType_Pseudo) >= 0;
2896 }
2897 
2899  const {
2901  while (I != E) {
2902  if (I->isBarrier())
2903  return true;
2904  ++I;
2905  }
2906  return false;
2907 }
2908 
2909 // Returns true, if a LD insn can be promoted to a cur load.
2911  const uint64_t F = MI.getDesc().TSFlags;
2913  Subtarget.hasV60TOps();
2914 }
2915 
2916 // Returns true, if a ST insn can be promoted to a new-value store.
2918  const uint64_t F = MI.getDesc().TSFlags;
2920 }
2921 
2923  const MachineInstr &ConsMI) const {
2924  // There is no stall when ProdMI is not a V60 vector.
2925  if (!isHVXVec(ProdMI))
2926  return false;
2927 
2928  // There is no stall when ProdMI and ConsMI are not dependent.
2929  if (!isDependent(ProdMI, ConsMI))
2930  return false;
2931 
2932  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
2933  // are scheduled in consecutive packets.
2934  if (isVecUsableNextPacket(ProdMI, ConsMI))
2935  return false;
2936 
2937  return true;
2938 }
2939 
2942  // There is no stall when I is not a V60 vector.
2943  if (!isHVXVec(MI))
2944  return false;
2945 
2947  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
2948 
2949  if (!MII->isBundle())
2950  return producesStall(*MII, MI);
2951 
2952  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
2953  const MachineInstr &J = *MII;
2954  if (producesStall(J, MI))
2955  return true;
2956  }
2957  return false;
2958 }
2959 
2961  unsigned PredReg) const {
2962  for (const MachineOperand &MO : MI.operands()) {
2963  // Predicate register must be explicitly defined.
2964  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
2965  return false;
2966  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
2967  return false;
2968  }
2969 
2970  // Hexagon Programmer's Reference says that decbin, memw_locked, and
2971  // memd_locked cannot be used as .new as well,
2972  // but we don't seem to have these instructions defined.
2973  return MI.getOpcode() != Hexagon::A4_tlbmatch;
2974 }
2975 
2976 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
2977  return Opcode == Hexagon::J2_jumpt ||
2978  Opcode == Hexagon::J2_jumptpt ||
2979  Opcode == Hexagon::J2_jumpf ||
2980  Opcode == Hexagon::J2_jumpfpt ||
2981  Opcode == Hexagon::J2_jumptnew ||
2982  Opcode == Hexagon::J2_jumpfnew ||
2983  Opcode == Hexagon::J2_jumptnewpt ||
2984  Opcode == Hexagon::J2_jumpfnewpt;
2985 }
2986 
2988  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
2989  return false;
2990  return !isPredicatedTrue(Cond[0].getImm());
2991 }
2992 
2994  const uint64_t F = MI.getDesc().TSFlags;
2996 }
2997 
2998 // Returns the base register in a memory access (load/store). The offset is
2999 // returned in Offset and the access size is returned in AccessSize.
3000 // If the base register has a subregister or the offset field does not contain
3001 // an immediate value, return 0.
3003  int &Offset, unsigned &AccessSize) const {
3004  // Return if it is not a base+offset type instruction or a MemOp.
3007  !isMemOp(MI) && !isPostIncrement(MI))
3008  return 0;
3009 
3010  AccessSize = getMemAccessSize(MI);
3011 
3012  unsigned BasePos = 0, OffsetPos = 0;
3013  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3014  return 0;
3015 
3016  // Post increment updates its EA after the mem access,
3017  // so we need to treat its offset as zero.
3018  if (isPostIncrement(MI)) {
3019  Offset = 0;
3020  } else {
3021  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3022  if (!OffsetOp.isImm())
3023  return 0;
3024  Offset = OffsetOp.getImm();
3025  }
3026 
3027  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3028  if (BaseOp.getSubReg() != 0)
3029  return 0;
3030  return BaseOp.getReg();
3031 }
3032 
3033 /// Return the position of the base and offset operands for this instruction.
3035  unsigned &BasePos, unsigned &OffsetPos) const {
3036  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3037  return false;
3038 
3039  // Deal with memops first.
3040  if (isMemOp(MI)) {
3041  BasePos = 0;
3042  OffsetPos = 1;
3043  } else if (MI.mayStore()) {
3044  BasePos = 0;
3045  OffsetPos = 1;
3046  } else if (MI.mayLoad()) {
3047  BasePos = 1;
3048  OffsetPos = 2;
3049  } else
3050  return false;
3051 
3052  if (isPredicated(MI)) {
3053  BasePos++;
3054  OffsetPos++;
3055  }
3056  if (isPostIncrement(MI)) {
3057  BasePos++;
3058  OffsetPos++;
3059  }
3060 
3061  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3062  return false;
3063 
3064  return true;
3065 }
3066 
3067 // Inserts branching instructions in reverse order of their occurrence.
3068 // e.g. jump_t t1 (i1)
3069 // jump t2 (i2)
3070 // Jumpers = {i2, i1}
3072  MachineBasicBlock& MBB) const {
3074  // If the block has no terminators, it just falls into the block after it.
3076  if (I == MBB.instr_begin())
3077  return Jumpers;
3078 
3079  // A basic block may looks like this:
3080  //
3081  // [ insn
3082  // EH_LABEL
3083  // insn
3084  // insn
3085  // insn
3086  // EH_LABEL
3087  // insn ]
3088  //
3089  // It has two succs but does not have a terminator
3090  // Don't know how to handle it.
3091  do {
3092  --I;
3093  if (I->isEHLabel())
3094  return Jumpers;
3095  } while (I != MBB.instr_begin());
3096 
3097  I = MBB.instr_end();
3098  --I;
3099 
3100  while (I->isDebugValue()) {
3101  if (I == MBB.instr_begin())
3102  return Jumpers;
3103  --I;
3104  }
3105  if (!isUnpredicatedTerminator(*I))
3106  return Jumpers;
3107 
3108  // Get the last instruction in the block.
3109  MachineInstr *LastInst = &*I;
3110  Jumpers.push_back(LastInst);
3111  MachineInstr *SecondLastInst = nullptr;
3112  // Find one more terminator if present.
3113  do {
3114  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3115  if (!SecondLastInst) {
3116  SecondLastInst = &*I;
3117  Jumpers.push_back(SecondLastInst);
3118  } else // This is a third branch.
3119  return Jumpers;
3120  }
3121  if (I == MBB.instr_begin())
3122  break;
3123  --I;
3124  } while (true);
3125  return Jumpers;
3126 }
3127 
3128 // Returns Operand Index for the constant extended instruction.
3130  const uint64_t F = MI.getDesc().TSFlags;
3132 }
3133 
3134 // See if instruction could potentially be a duplex candidate.
3135 // If so, return its group. Zero otherwise.
3137  const MachineInstr &MI) const {
3138  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3139 
3140  switch (MI.getOpcode()) {
3141  default:
3142  return HexagonII::HCG_None;
3143  //
3144  // Compound pairs.
3145  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3146  // "Rd16=#U6 ; jump #r9:2"
3147  // "Rd16=Rs16 ; jump #r9:2"
3148  //
3149  case Hexagon::C2_cmpeq:
3150  case Hexagon::C2_cmpgt:
3151  case Hexagon::C2_cmpgtu:
3152  DstReg = MI.getOperand(0).getReg();
3153  Src1Reg = MI.getOperand(1).getReg();
3154  Src2Reg = MI.getOperand(2).getReg();
3155  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3156  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3157  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3158  return HexagonII::HCG_A;
3159  break;
3160  case Hexagon::C2_cmpeqi:
3161  case Hexagon::C2_cmpgti:
3162  case Hexagon::C2_cmpgtui:
3163  // P0 = cmp.eq(Rs,#u2)
3164  DstReg = MI.getOperand(0).getReg();
3165  SrcReg = MI.getOperand(1).getReg();
3166  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3167  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3168  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3169  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3170  (MI.getOperand(2).getImm() == -1)))
3171  return HexagonII::HCG_A;
3172  break;
3173  case Hexagon::A2_tfr:
3174  // Rd = Rs
3175  DstReg = MI.getOperand(0).getReg();
3176  SrcReg = MI.getOperand(1).getReg();
3177  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3178  return HexagonII::HCG_A;
3179  break;
3180  case Hexagon::A2_tfrsi:
3181  // Rd = #u6
3182  // Do not test for #u6 size since the const is getting extended
3183  // regardless and compound could be formed.
3184  DstReg = MI.getOperand(0).getReg();
3185  if (isIntRegForSubInst(DstReg))
3186  return HexagonII::HCG_A;
3187  break;
3188  case Hexagon::S2_tstbit_i:
3189  DstReg = MI.getOperand(0).getReg();
3190  Src1Reg = MI.getOperand(1).getReg();
3191  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3192  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3193  MI.getOperand(2).isImm() &&
3194  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3195  return HexagonII::HCG_A;
3196  break;
3197  // The fact that .new form is used pretty much guarantees
3198  // that predicate register will match. Nevertheless,
3199  // there could be some false positives without additional
3200  // checking.
3201  case Hexagon::J2_jumptnew:
3202  case Hexagon::J2_jumpfnew:
3203  case Hexagon::J2_jumptnewpt:
3204  case Hexagon::J2_jumpfnewpt:
3205  Src1Reg = MI.getOperand(0).getReg();
3206  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3207  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3208  return HexagonII::HCG_B;
3209  break;
3210  // Transfer and jump:
3211  // Rd=#U6 ; jump #r9:2
3212  // Rd=Rs ; jump #r9:2
3213  // Do not test for jump range here.
3214  case Hexagon::J2_jump:
3215  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3216  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3217  return HexagonII::HCG_C;
3218  }
3219 
3220  return HexagonII::HCG_None;
3221 }
3222 
3223 // Returns -1 when there is no opcode found.
3225  const MachineInstr &GB) const {
3228  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3229  (GB.getOpcode() != Hexagon::J2_jumptnew))
3230  return -1u;
3231  unsigned DestReg = GA.getOperand(0).getReg();
3232  if (!GB.readsRegister(DestReg))
3233  return -1u;
3234  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3235  return -1u;
3236  // The value compared against must be either u5 or -1.
3237  const MachineOperand &CmpOp = GA.getOperand(2);
3238  if (!CmpOp.isImm())
3239  return -1u;
3240  int V = CmpOp.getImm();
3241  if (V == -1)
3242  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3243  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3244  if (!isUInt<5>(V))
3245  return -1u;
3246  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3247  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3248 }
3249 
3250 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3251  enum Hexagon::PredSense inPredSense;
3252  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3253  Hexagon::PredSense_true;
3254  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3255  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3256  return CondOpcode;
3257 
3258  llvm_unreachable("Unexpected predicable instruction");
3259 }
3260 
3261 // Return the cur value instruction for a given store.
3263  switch (MI.getOpcode()) {
3264  default: llvm_unreachable("Unknown .cur type");
3265  case Hexagon::V6_vL32b_pi:
3266  return Hexagon::V6_vL32b_cur_pi;
3267  case Hexagon::V6_vL32b_ai:
3268  return Hexagon::V6_vL32b_cur_ai;
3269  case Hexagon::V6_vL32b_nt_pi:
3270  return Hexagon::V6_vL32b_nt_cur_pi;
3271  case Hexagon::V6_vL32b_nt_ai:
3272  return Hexagon::V6_vL32b_nt_cur_ai;
3273  }
3274  return 0;
3275 }
3276 
3277 // Return the regular version of the .cur instruction.
3279  switch (MI.getOpcode()) {
3280  default: llvm_unreachable("Unknown .cur type");
3281  case Hexagon::V6_vL32b_cur_pi:
3282  return Hexagon::V6_vL32b_pi;
3283  case Hexagon::V6_vL32b_cur_ai:
3284  return Hexagon::V6_vL32b_ai;
3285  case Hexagon::V6_vL32b_nt_cur_pi:
3286  return Hexagon::V6_vL32b_nt_pi;
3287  case Hexagon::V6_vL32b_nt_cur_ai:
3288  return Hexagon::V6_vL32b_nt_ai;
3289  }
3290  return 0;
3291 }
3292 
3293 // The diagram below shows the steps involved in the conversion of a predicated
3294 // store instruction to its .new predicated new-value form.
3295 //
3296 // Note: It doesn't include conditional new-value stores as they can't be
3297 // converted to .new predicate.
3298 //
3299 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3300 // ^ ^
3301 // / \ (not OK. it will cause new-value store to be
3302 // / X conditional on p0.new while R2 producer is
3303 // / \ on p0)
3304 // / \.
3305 // p.new store p.old NV store
3306 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3307 // ^ ^
3308 // \ /
3309 // \ /
3310 // \ /
3311 // p.old store
3312 // [if (p0)memw(R0+#0)=R2]
3313 //
3314 // The following set of instructions further explains the scenario where
3315 // conditional new-value store becomes invalid when promoted to .new predicate
3316 // form.
3317 //
3318 // { 1) if (p0) r0 = add(r1, r2)
3319 // 2) p0 = cmp.eq(r3, #0) }
3320 //
3321 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3322 // the first two instructions because in instr 1, r0 is conditional on old value
3323 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3324 // is not valid for new-value stores.
3325 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3326 // from the "Conditional Store" list. Because a predicated new value store
3327 // would NOT be promoted to a double dot new store. See diagram below:
3328 // This function returns yes for those stores that are predicated but not
3329 // yet promoted to predicate dot new instructions.
3330 //
3331 // +---------------------+
3332 // /-----| if (p0) memw(..)=r0 |---------\~
3333 // || +---------------------+ ||
3334 // promote || /\ /\ || promote
3335 // || /||\ /||\ ||
3336 // \||/ demote || \||/
3337 // \/ || || \/
3338 // +-------------------------+ || +-------------------------+
3339 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3340 // +-------------------------+ || +-------------------------+
3341 // || || ||
3342 // || demote \||/
3343 // promote || \/ NOT possible
3344 // || || /\~
3345 // \||/ || /||\~
3346 // \/ || ||
3347 // +-----------------------------+
3348 // | if (p0.new) memw(..)=r0.new |
3349 // +-----------------------------+
3350 // Double Dot New Store
3351 //
3352 // Returns the most basic instruction for the .new predicated instructions and
3353 // new-value stores.
3354 // For example, all of the following instructions will be converted back to the
3355 // same instruction:
3356 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3357 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3358 // 3) if (p0.new) memw(R0+#0) = R1 --->
3359 //
3360 // To understand the translation of instruction 1 to its original form, consider
3361 // a packet with 3 instructions.
3362 // { p0 = cmp.eq(R0,R1)
3363 // if (p0.new) R2 = add(R3, R4)
3364 // R5 = add (R3, R1)
3365 // }
3366 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3367 //
3368 // This instruction can be part of the previous packet only if both p0 and R2
3369 // are promoted to .new values. This promotion happens in steps, first
3370 // predicate register is promoted to .new and in the next iteration R2 is
3371 // promoted. Therefore, in case of dependence check failure (due to R5) during
3372 // next iteration, it should be converted back to its most basic form.
3373 
3374 // Return the new value instruction for a given store.
3376  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3377  if (NVOpcode >= 0) // Valid new-value store instruction.
3378  return NVOpcode;
3379 
3380  switch (MI.getOpcode()) {
3381  default:
3382  report_fatal_error(std::string("Unknown .new type: ") +
3383  std::to_string(MI.getOpcode()));
3384  case Hexagon::S4_storerb_ur:
3385  return Hexagon::S4_storerbnew_ur;
3386 
3387  case Hexagon::S2_storerb_pci:
3388  return Hexagon::S2_storerb_pci;
3389 
3390  case Hexagon::S2_storeri_pci:
3391  return Hexagon::S2_storeri_pci;
3392 
3393  case Hexagon::S2_storerh_pci:
3394  return Hexagon::S2_storerh_pci;
3395 
3396  case Hexagon::S2_storerd_pci:
3397  return Hexagon::S2_storerd_pci;
3398 
3399  case Hexagon::S2_storerf_pci:
3400  return Hexagon::S2_storerf_pci;
3401 
3402  case Hexagon::V6_vS32b_ai:
3403  return Hexagon::V6_vS32b_new_ai;
3404 
3405  case Hexagon::V6_vS32b_pi:
3406  return Hexagon::V6_vS32b_new_pi;
3407  }
3408  return 0;
3409 }
3410 
3411 // Returns the opcode to use when converting MI, which is a conditional jump,
3412 // into a conditional instruction which uses the .new value of the predicate.
3413 // We also use branch probabilities to add a hint to the jump.
3414 // If MBPI is null, all edges will be treated as equally likely for the
3415 // purposes of establishing a predication hint.
3417  const MachineBranchProbabilityInfo *MBPI) const {
3418  // We assume that block can have at most two successors.
3419  const MachineBasicBlock *Src = MI.getParent();
3420  const MachineOperand &BrTarget = MI.getOperand(1);
3421  bool Taken = false;
3422  const BranchProbability OneHalf(1, 2);
3423 
3424  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3425  const MachineBasicBlock *Dst) {
3426  if (MBPI)
3427  return MBPI->getEdgeProbability(Src, Dst);
3428  return BranchProbability(1, Src->succ_size());
3429  };
3430 
3431  if (BrTarget.isMBB()) {
3432  const MachineBasicBlock *Dst = BrTarget.getMBB();
3433  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3434  } else {
3435  // The branch target is not a basic block (most likely a function).
3436  // Since BPI only gives probabilities for targets that are basic blocks,
3437  // try to identify another target of this branch (potentially a fall-
3438  // -through) and check the probability of that target.
3439  //
3440  // The only handled branch combinations are:
3441  // - one conditional branch,
3442  // - one conditional branch followed by one unconditional branch.
3443  // Otherwise, assume not-taken.
3445  const MachineBasicBlock &B = *MI.getParent();
3446  bool SawCond = false, Bad = false;
3447  for (const MachineInstr &I : B) {
3448  if (!I.isBranch())
3449  continue;
3450  if (I.isConditionalBranch()) {
3451  SawCond = true;
3452  if (&I != &MI) {
3453  Bad = true;
3454  break;
3455  }
3456  }
3457  if (I.isUnconditionalBranch() && !SawCond) {
3458  Bad = true;
3459  break;
3460  }
3461  }
3462  if (!Bad) {
3464  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3465  if (NextIt == B.instr_end()) {
3466  // If this branch is the last, look for the fall-through block.
3467  for (const MachineBasicBlock *SB : B.successors()) {
3468  if (!B.isLayoutSuccessor(SB))
3469  continue;
3470  Taken = getEdgeProbability(Src, SB) < OneHalf;
3471  break;
3472  }
3473  } else {
3474  assert(NextIt->isUnconditionalBranch());
3475  // Find the first MBB operand and assume it's the target.
3476  const MachineBasicBlock *BT = nullptr;
3477  for (const MachineOperand &Op : NextIt->operands()) {
3478  if (!Op.isMBB())
3479  continue;
3480  BT = Op.getMBB();
3481  break;
3482  }
3483  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3484  }
3485  } // if (!Bad)
3486  }
3487 
3488  // The Taken flag should be set to something reasonable by this point.
3489 
3490  switch (MI.getOpcode()) {
3491  case Hexagon::J2_jumpt:
3492  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3493  case Hexagon::J2_jumpf:
3494  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3495 
3496  default:
3497  llvm_unreachable("Unexpected jump instruction.");
3498  }
3499 }
3500 
3501 // Return .new predicate version for an instruction.
3503  const MachineBranchProbabilityInfo *MBPI) const {
3504  switch (MI.getOpcode()) {
3505  // Condtional Jumps
3506  case Hexagon::J2_jumpt:
3507  case Hexagon::J2_jumpf:
3508  return getDotNewPredJumpOp(MI, MBPI);
3509  }
3510 
3511  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3512  if (NewOpcode >= 0)
3513  return NewOpcode;
3514  return 0;
3515 }
3516 
3518  int NewOp = MI.getOpcode();
3519  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3520  NewOp = Hexagon::getPredOldOpcode(NewOp);
3521  // All Hexagon architectures have prediction bits on dot-new branches,
3522  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3523  // to pick the right opcode when converting back to dot-old.
3524  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3525  switch (NewOp) {
3526  case Hexagon::J2_jumptpt:
3527  NewOp = Hexagon::J2_jumpt;
3528  break;
3529  case Hexagon::J2_jumpfpt:
3530  NewOp = Hexagon::J2_jumpf;
3531  break;
3532  case Hexagon::J2_jumprtpt:
3533  NewOp = Hexagon::J2_jumprt;
3534  break;
3535  case Hexagon::J2_jumprfpt:
3536  NewOp = Hexagon::J2_jumprf;
3537  break;
3538  }
3539  }
3540  assert(NewOp >= 0 &&
3541  "Couldn't change predicate new instruction to its old form.");
3542  }
3543 
3544  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3545  NewOp = Hexagon::getNonNVStore(NewOp);
3546  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3547  }
3548 
3549  if (Subtarget.hasV60TOps())
3550  return NewOp;
3551 
3552  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3553  switch (NewOp) {
3554  case Hexagon::J2_jumpfpt:
3555  return Hexagon::J2_jumpf;
3556  case Hexagon::J2_jumptpt:
3557  return Hexagon::J2_jumpt;
3558  case Hexagon::J2_jumprfpt:
3559  return Hexagon::J2_jumprf;
3560  case Hexagon::J2_jumprtpt:
3561  return Hexagon::J2_jumprt;
3562  }
3563  return NewOp;
3564 }
3565 
3566 // See if instruction could potentially be a duplex candidate.
3567 // If so, return its group. Zero otherwise.
3569  const MachineInstr &MI) const {
3570  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3571  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3572 
3573  switch (MI.getOpcode()) {
3574  default:
3575  return HexagonII::HSIG_None;
3576  //
3577  // Group L1:
3578  //
3579  // Rd = memw(Rs+#u4:2)
3580  // Rd = memub(Rs+#u4:0)
3581  case Hexagon::L2_loadri_io:
3582  DstReg = MI.getOperand(0).getReg();
3583  SrcReg = MI.getOperand(1).getReg();
3584  // Special case this one from Group L2.
3585  // Rd = memw(r29+#u5:2)
3586  if (isIntRegForSubInst(DstReg)) {
3587  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3588  HRI.getStackRegister() == SrcReg &&
3589  MI.getOperand(2).isImm() &&
3590  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3591  return HexagonII::HSIG_L2;
3592  // Rd = memw(Rs+#u4:2)
3593  if (isIntRegForSubInst(SrcReg) &&
3594  (MI.getOperand(2).isImm() &&
3595  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3596  return HexagonII::HSIG_L1;
3597  }
3598  break;
3599  case Hexagon::L2_loadrub_io:
3600  // Rd = memub(Rs+#u4:0)
3601  DstReg = MI.getOperand(0).getReg();
3602  SrcReg = MI.getOperand(1).getReg();
3603  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3604  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3605  return HexagonII::HSIG_L1;
3606  break;
3607  //
3608  // Group L2:
3609  //
3610  // Rd = memh/memuh(Rs+#u3:1)
3611  // Rd = memb(Rs+#u3:0)
3612  // Rd = memw(r29+#u5:2) - Handled above.
3613  // Rdd = memd(r29+#u5:3)
3614  // deallocframe
3615  // [if ([!]p0[.new])] dealloc_return
3616  // [if ([!]p0[.new])] jumpr r31
3617  case Hexagon::L2_loadrh_io:
3618  case Hexagon::L2_loadruh_io:
3619  // Rd = memh/memuh(Rs+#u3:1)
3620  DstReg = MI.getOperand(0).getReg();
3621  SrcReg = MI.getOperand(1).getReg();
3622  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3623  MI.getOperand(2).isImm() &&
3624  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3625  return HexagonII::HSIG_L2;
3626  break;
3627  case Hexagon::L2_loadrb_io:
3628  // Rd = memb(Rs+#u3:0)
3629  DstReg = MI.getOperand(0).getReg();
3630  SrcReg = MI.getOperand(1).getReg();
3631  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3632  MI.getOperand(2).isImm() &&
3633  isUInt<3>(MI.getOperand(2).getImm()))
3634  return HexagonII::HSIG_L2;
3635  break;
3636  case Hexagon::L2_loadrd_io:
3637  // Rdd = memd(r29+#u5:3)
3638  DstReg = MI.getOperand(0).getReg();
3639  SrcReg = MI.getOperand(1).getReg();
3640  if (isDblRegForSubInst(DstReg, HRI) &&
3641  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3642  HRI.getStackRegister() == SrcReg &&
3643  MI.getOperand(2).isImm() &&
3644  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3645  return HexagonII::HSIG_L2;
3646  break;
3647  // dealloc_return is not documented in Hexagon Manual, but marked
3648  // with A_SUBINSN attribute in iset_v4classic.py.
3649  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3650  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3651  case Hexagon::L4_return:
3652  case Hexagon::L2_deallocframe:
3653  return HexagonII::HSIG_L2;
3654  case Hexagon::EH_RETURN_JMPR:
3655  case Hexagon::PS_jmpret:
3656  case Hexagon::SL2_jumpr31:
3657  // jumpr r31
3658  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3659  DstReg = MI.getOperand(0).getReg();
3660  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3661  return HexagonII::HSIG_L2;
3662  break;
3663  case Hexagon::PS_jmprett:
3664  case Hexagon::PS_jmpretf:
3665  case Hexagon::PS_jmprettnewpt:
3666  case Hexagon::PS_jmpretfnewpt:
3667  case Hexagon::PS_jmprettnew:
3668  case Hexagon::PS_jmpretfnew:
3669  case Hexagon::SL2_jumpr31_t:
3670  case Hexagon::SL2_jumpr31_f:
3671  case Hexagon::SL2_jumpr31_tnew:
3672  DstReg = MI.getOperand(1).getReg();
3673  SrcReg = MI.getOperand(0).getReg();
3674  // [if ([!]p0[.new])] jumpr r31
3675  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3676  (Hexagon::P0 == SrcReg)) &&
3677  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3678  return HexagonII::HSIG_L2;
3679  break;
3680  case Hexagon::L4_return_t:
3681  case Hexagon::L4_return_f:
3682  case Hexagon::L4_return_tnew_pnt:
3683  case Hexagon::L4_return_fnew_pnt:
3684  case Hexagon::L4_return_tnew_pt:
3685  case Hexagon::L4_return_fnew_pt:
3686  // [if ([!]p0[.new])] dealloc_return
3687  SrcReg = MI.getOperand(0).getReg();
3688  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3689  return HexagonII::HSIG_L2;
3690  break;
3691  //
3692  // Group S1:
3693  //
3694  // memw(Rs+#u4:2) = Rt
3695  // memb(Rs+#u4:0) = Rt
3696  case Hexagon::S2_storeri_io:
3697  // Special case this one from Group S2.
3698  // memw(r29+#u5:2) = Rt
3699  Src1Reg = MI.getOperand(0).getReg();
3700  Src2Reg = MI.getOperand(2).getReg();
3701  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3702  isIntRegForSubInst(Src2Reg) &&
3703  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3704  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3705  return HexagonII::HSIG_S2;
3706  // memw(Rs+#u4:2) = Rt
3707  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3708  MI.getOperand(1).isImm() &&
3709  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3710  return HexagonII::HSIG_S1;
3711  break;
3712  case Hexagon::S2_storerb_io:
3713  // memb(Rs+#u4:0) = Rt
3714  Src1Reg = MI.getOperand(0).getReg();
3715  Src2Reg = MI.getOperand(2).getReg();
3716  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3717  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3718  return HexagonII::HSIG_S1;
3719  break;
3720  //
3721  // Group S2:
3722  //
3723  // memh(Rs+#u3:1) = Rt
3724  // memw(r29+#u5:2) = Rt
3725  // memd(r29+#s6:3) = Rtt
3726  // memw(Rs+#u4:2) = #U1
3727  // memb(Rs+#u4) = #U1
3728  // allocframe(#u5:3)
3729  case Hexagon::S2_storerh_io:
3730  // memh(Rs+#u3:1) = Rt
3731  Src1Reg = MI.getOperand(0).getReg();
3732  Src2Reg = MI.getOperand(2).getReg();
3733  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3734  MI.getOperand(1).isImm() &&
3735  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3736  return HexagonII::HSIG_S1;
3737  break;
3738  case Hexagon::S2_storerd_io:
3739  // memd(r29+#s6:3) = Rtt
3740  Src1Reg = MI.getOperand(0).getReg();
3741  Src2Reg = MI.getOperand(2).getReg();
3742  if (isDblRegForSubInst(Src2Reg, HRI) &&
3743  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3744  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3745  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3746  return HexagonII::HSIG_S2;
3747  break;
3748  case Hexagon::S4_storeiri_io:
3749  // memw(Rs+#u4:2) = #U1
3750  Src1Reg = MI.getOperand(0).getReg();
3751  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3752  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3753  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3754  return HexagonII::HSIG_S2;
3755  break;
3756  case Hexagon::S4_storeirb_io:
3757  // memb(Rs+#u4) = #U1
3758  Src1Reg = MI.getOperand(0).getReg();
3759  if (isIntRegForSubInst(Src1Reg) &&
3760  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3761  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3762  return HexagonII::HSIG_S2;
3763  break;
3764  case Hexagon::S2_allocframe:
3765  if (MI.getOperand(2).isImm() &&
3766  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3767  return HexagonII::HSIG_S1;
3768  break;
3769  //
3770  // Group A:
3771  //
3772  // Rx = add(Rx,#s7)
3773  // Rd = Rs
3774  // Rd = #u6
3775  // Rd = #-1
3776  // if ([!]P0[.new]) Rd = #0
3777  // Rd = add(r29,#u6:2)
3778  // Rx = add(Rx,Rs)
3779  // P0 = cmp.eq(Rs,#u2)
3780  // Rdd = combine(#0,Rs)
3781  // Rdd = combine(Rs,#0)
3782  // Rdd = combine(#u2,#U2)
3783  // Rd = add(Rs,#1)
3784  // Rd = add(Rs,#-1)
3785  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3786  // Rd = and(Rs,#1)
3787  case Hexagon::A2_addi:
3788  DstReg = MI.getOperand(0).getReg();
3789  SrcReg = MI.getOperand(1).getReg();
3790  if (isIntRegForSubInst(DstReg)) {
3791  // Rd = add(r29,#u6:2)
3792  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3793  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3794  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3795  return HexagonII::HSIG_A;
3796  // Rx = add(Rx,#s7)
3797  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3798  isInt<7>(MI.getOperand(2).getImm()))
3799  return HexagonII::HSIG_A;
3800  // Rd = add(Rs,#1)
3801  // Rd = add(Rs,#-1)
3802  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3803  ((MI.getOperand(2).getImm() == 1) ||
3804  (MI.getOperand(2).getImm() == -1)))
3805  return HexagonII::HSIG_A;
3806  }
3807  break;
3808  case Hexagon::A2_add:
3809  // Rx = add(Rx,Rs)
3810  DstReg = MI.getOperand(0).getReg();
3811  Src1Reg = MI.getOperand(1).getReg();
3812  Src2Reg = MI.getOperand(2).getReg();
3813  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3814  isIntRegForSubInst(Src2Reg))
3815  return HexagonII::HSIG_A;
3816  break;
3817  case Hexagon::A2_andir:
3818  // Same as zxtb.
3819  // Rd16=and(Rs16,#255)
3820  // Rd16=and(Rs16,#1)
3821  DstReg = MI.getOperand(0).getReg();
3822  SrcReg = MI.getOperand(1).getReg();
3823  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3824  MI.getOperand(2).isImm() &&
3825  ((MI.getOperand(2).getImm() == 1) ||
3826  (MI.getOperand(2).getImm() == 255)))
3827  return HexagonII::HSIG_A;
3828  break;
3829  case Hexagon::A2_tfr:
3830  // Rd = Rs
3831  DstReg = MI.getOperand(0).getReg();
3832  SrcReg = MI.getOperand(1).getReg();
3833  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3834  return HexagonII::HSIG_A;
3835  break;
3836  case Hexagon::A2_tfrsi:
3837  // Rd = #u6
3838  // Do not test for #u6 size since the const is getting extended
3839  // regardless and compound could be formed.
3840  // Rd = #-1
3841  DstReg = MI.getOperand(0).getReg();
3842  if (isIntRegForSubInst(DstReg))
3843  return HexagonII::HSIG_A;
3844  break;
3845  case Hexagon::C2_cmoveit:
3846  case Hexagon::C2_cmovenewit:
3847  case Hexagon::C2_cmoveif:
3848  case Hexagon::C2_cmovenewif:
3849  // if ([!]P0[.new]) Rd = #0
3850  // Actual form:
3851  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3852  DstReg = MI.getOperand(0).getReg();
3853  SrcReg = MI.getOperand(1).getReg();
3854  if (isIntRegForSubInst(DstReg) &&
3855  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3856  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3857  return HexagonII::HSIG_A;
3858  break;
3859  case Hexagon::C2_cmpeqi:
3860  // P0 = cmp.eq(Rs,#u2)
3861  DstReg = MI.getOperand(0).getReg();
3862  SrcReg = MI.getOperand(1).getReg();
3863  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3864  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3865  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3866  return HexagonII::HSIG_A;
3867  break;
3868  case Hexagon::A2_combineii:
3869  case Hexagon::A4_combineii:
3870  // Rdd = combine(#u2,#U2)
3871  DstReg = MI.getOperand(0).getReg();
3872  if (isDblRegForSubInst(DstReg, HRI) &&
3873  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3874  (MI.getOperand(1).isGlobal() &&
3875  isUInt<2>(MI.getOperand(1).getOffset()))) &&
3876  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3877  (MI.getOperand(2).isGlobal() &&
3878  isUInt<2>(MI.getOperand(2).getOffset()))))
3879  return HexagonII::HSIG_A;
3880  break;
3881  case Hexagon::A4_combineri:
3882  // Rdd = combine(Rs,#0)
3883  DstReg = MI.getOperand(0).getReg();
3884  SrcReg = MI.getOperand(1).getReg();
3885  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3886  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3887  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3888  return HexagonII::HSIG_A;
3889  break;
3890  case Hexagon::A4_combineir:
3891  // Rdd = combine(#0,Rs)
3892  DstReg = MI.getOperand(0).getReg();
3893  SrcReg = MI.getOperand(2).getReg();
3894  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3895  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3896  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3897  return HexagonII::HSIG_A;
3898  break;
3899  case Hexagon::A2_sxtb:
3900  case Hexagon::A2_sxth:
3901  case Hexagon::A2_zxtb:
3902  case Hexagon::A2_zxth:
3903  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3904  DstReg = MI.getOperand(0).getReg();
3905  SrcReg = MI.getOperand(1).getReg();
3906  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3907  return HexagonII::HSIG_A;
3908  break;
3909  }
3910 
3911  return HexagonII::HSIG_None;
3912 }
3913 
3915  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
3916 }
3917 
3919  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
3920  // Default to one cycle for no itinerary. However, an "empty" itinerary may
3921  // still have a MinLatency property, which getStageLatency checks.
3922  if (!ItinData)
3923  return getInstrLatency(ItinData, MI);
3924 
3925  if (MI.isTransient())
3926  return 0;
3927  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
3928 }
3929 
3930 /// getOperandLatency - Compute and return the use operand latency of a given
3931 /// pair of def and use.
3932 /// In most cases, the static scheduling itinerary was enough to determine the
3933 /// operand latency. But it may not be possible for instructions with variable
3934 /// number of defs / uses.
3935 ///
3936 /// This is a raw interface to the itinerary that may be directly overriden by
3937 /// a target. Use computeOperandLatency to get the best estimate of latency.
3939  const MachineInstr &DefMI,
3940  unsigned DefIdx,
3941  const MachineInstr &UseMI,
3942  unsigned UseIdx) const {
3943  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3944 
3945  // Get DefIdx and UseIdx for super registers.
3946  MachineOperand DefMO = DefMI.getOperand(DefIdx);
3947 
3948  if (HRI.isPhysicalRegister(DefMO.getReg())) {
3949  if (DefMO.isImplicit()) {
3950  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
3951  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
3952  if (Idx != -1) {
3953  DefIdx = Idx;
3954  break;
3955  }
3956  }
3957  }
3958 
3959  MachineOperand UseMO = UseMI.getOperand(UseIdx);
3960  if (UseMO.isImplicit()) {
3961  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
3962  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
3963  if (Idx != -1) {
3964  UseIdx = Idx;
3965  break;
3966  }
3967  }
3968  }
3969  }
3970 
3971  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
3972  UseMI, UseIdx);
3973  if (!Latency)
3974  // We should never have 0 cycle latency between two instructions unless
3975  // they can be packetized together. However, this decision can't be made
3976  // here.
3977  Latency = 1;
3978  return Latency;
3979 }
3980 
3981 // inverts the predication logic.
3982 // p -> NotP
3983 // NotP -> P
3985  SmallVectorImpl<MachineOperand> &Cond) const {
3986  if (Cond.empty())
3987  return false;
3988  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
3989  Cond[0].setImm(Opc);
3990  return true;
3991 }
3992 
3993 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
3994  int InvPredOpcode;
3995  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
3996  : Hexagon::getTruePredOpcode(Opc);
3997  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
3998  return InvPredOpcode;
3999 
4000  llvm_unreachable("Unexpected predicated instruction");
4001 }
4002 
4003 // Returns the max value that doesn't need to be extended.
4005  const uint64_t F = MI.getDesc().TSFlags;
4006  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4008  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4010 
4011  if (isSigned) // if value is signed
4012  return ~(-1U << (bits - 1));
4013  else
4014  return ~(-1U << bits);
4015 }
4016 
4017 
4019  switch (MI.getOpcode()) {
4020  case Hexagon::L2_loadrbgp:
4021  case Hexagon::L2_loadrdgp:
4022  case Hexagon::L2_loadrhgp:
4023  case Hexagon::L2_loadrigp:
4024  case Hexagon::L2_loadrubgp:
4025  case Hexagon::L2_loadruhgp:
4026  case Hexagon::S2_storerbgp:
4027  case Hexagon::S2_storerbnewgp:
4028  case Hexagon::S2_storerhgp:
4029  case Hexagon::S2_storerhnewgp:
4030  case Hexagon::S2_storerigp:
4031  case Hexagon::S2_storerinewgp:
4032  case Hexagon::S2_storerdgp:
4033  case Hexagon::S2_storerfgp:
4034  return true;
4035  }
4036  const uint64_t F = MI.getDesc().TSFlags;
4037  unsigned addrMode =
4039  // Disallow any base+offset instruction. The assembler does not yet reorder
4040  // based up any zero offset instruction.
4041  return (addrMode == HexagonII::BaseRegOffset ||
4042  addrMode == HexagonII::BaseImmOffset ||
4043  addrMode == HexagonII::BaseLongOffset);
4044 }
4045 
4047  using namespace HexagonII;
4048 
4049  const uint64_t F = MI.getDesc().TSFlags;
4050  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4052  if (Size != 0)
4053  return Size;
4054 
4055  // Handle vector access sizes.
4056  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4057  switch (S) {
4059  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4060  default:
4061  llvm_unreachable("Unexpected instruction");
4062  }
4063 }
4064 
4065 // Returns the min value that doesn't need to be extended.
4067  const uint64_t F = MI.getDesc().TSFlags;
4068  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4070  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4072 
4073  if (isSigned) // if value is signed
4074  return -1U << (bits - 1);
4075  else
4076  return 0;
4077 }
4078 
4079 // Returns opcode of the non-extended equivalent instruction.
4081  // Check if the instruction has a register form that uses register in place
4082  // of the extended operand, if so return that as the non-extended form.
4083  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4084  if (NonExtOpcode >= 0)
4085  return NonExtOpcode;
4086 
4087  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4088  // Check addressing mode and retrieve non-ext equivalent instruction.
4089  switch (getAddrMode(MI)) {
4090  case HexagonII::Absolute:
4091  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4093  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4095  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4096 
4097  default:
4098  return -1;
4099  }
4100  }
4101  return -1;
4102 }
4103 
4105  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4106  if (Cond.empty())
4107  return false;
4108  assert(Cond.size() == 2);
4109  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4110  DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4111  return false;
4112  }
4113  PredReg = Cond[1].getReg();
4114  PredRegPos = 1;
4115  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4116  PredRegFlags = 0;
4117  if (Cond[1].isImplicit())
4118  PredRegFlags = RegState::Implicit;
4119  if (Cond[1].isUndef())
4120  PredRegFlags |= RegState::Undef;
4121  return true;
4122 }
4123 
4125  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4126 }
4127 
4129  return Hexagon::getRegForm(MI.getOpcode());
4130 }
4131 
4132 // Return the number of bytes required to encode the instruction.
4133 // Hexagon instructions are fixed length, 4 bytes, unless they
4134 // use a constant extender, which requires another 4 bytes.
4135 // For debug instructions and prolog labels, return 0.
4137  if (MI.isDebugValue() || MI.isPosition())
4138  return 0;
4139 
4140  unsigned Size = MI.getDesc().getSize();
4141  if (!Size)
4142  // Assume the default insn size in case it cannot be determined
4143  // for whatever reason.
4144  Size = HEXAGON_INSTR_SIZE;
4145 
4146  if (isConstExtended(MI) || isExtended(MI))
4147  Size += HEXAGON_INSTR_SIZE;
4148 
4149  // Try and compute number of instructions in asm.
4151  const MachineBasicBlock &MBB = *MI.getParent();
4152  const MachineFunction *MF = MBB.getParent();
4153  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4154 
4155  // Count the number of register definitions to find the asm string.
4156  unsigned NumDefs = 0;
4157  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4158  ++NumDefs)
4159  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4160 
4161  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4162  // Disassemble the AsmStr and approximate number of instructions.
4163  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4164  Size = getInlineAsmLength(AsmStr, *MAI);
4165  }
4166 
4167  return Size;
4168 }
4169 
4171  const uint64_t F = MI.getDesc().TSFlags;
4172  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4173 }
4174 
4176  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4177  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4178 
4179  return IS.getUnits();
4180 }
4181 
4182 // Calculate size of the basic block without debug instructions.
4184  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4185 }
4186 
4188  MachineBasicBlock::const_iterator BundleHead) const {
4189  assert(BundleHead->isBundle() && "Not a bundle header");
4190  auto MII = BundleHead.getInstrIterator();
4191  // Skip the bundle header.
4192  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4193 }
4194 
4195 /// immediateExtend - Changes the instruction in place to one using an immediate
4196 /// extender.
4198  assert((isExtendable(MI)||isConstExtended(MI)) &&
4199  "Instruction must be extendable");
4200  // Find which operand is extendable.
4201  short ExtOpNum = getCExtOpNum(MI);
4202  MachineOperand &MO = MI.getOperand(ExtOpNum);
4203  // This needs to be something we understand.
4204  assert((MO.isMBB() || MO.isImm()) &&
4205  "Branch with unknown extendable field type");
4206  // Mark given operand as extended.
4208 }
4209 
4211  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4212  DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4213  << printMBBReference(*NewTarget);
4214  MI.dump(););
4215  assert(MI.isBranch());
4216  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4217  int TargetPos = MI.getNumOperands() - 1;
4218  // In general branch target is the last operand,
4219  // but some implicit defs added at the end might change it.
4220  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4221  --TargetPos;
4222  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4223  MI.getOperand(TargetPos).setMBB(NewTarget);
4225  NewOpcode = reversePrediction(NewOpcode);
4226  }
4227  MI.setDesc(get(NewOpcode));
4228  return true;
4229 }
4230 
4232  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4234  MachineBasicBlock &B = *A;
4236  DebugLoc DL = I->getDebugLoc();
4237  MachineInstr *NewMI;
4238 
4239  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4240  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4241  NewMI = BuildMI(B, I, DL, get(insn));
4242  DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
4243  " Class: " << NewMI->getDesc().getSchedClass());
4244  NewMI->eraseFromParent();
4245  }
4246  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4247 }
4248 
4249 // inverts the predication logic.
4250 // p -> NotP
4251 // NotP -> P
4253  DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4255  return true;
4256 }
4257 
4258 // Reverse the branch prediction.
4259 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4260  int PredRevOpcode = -1;
4261  if (isPredictedTaken(Opcode))
4262  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4263  else
4264  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4265  assert(PredRevOpcode > 0);
4266  return PredRevOpcode;
4267 }
4268 
4269 // TODO: Add more rigorous validation.
4271  const {
4272  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4273 }
4274 
4275 void HexagonInstrInfo::
4277  assert(MIB->isBundle());
4278  MachineOperand &Operand = MIB->getOperand(0);
4279  if (Operand.isImm())
4280  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4281  else
4282  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4283 }
4284 
4286  assert(MIB.isBundle());
4287  const MachineOperand &Operand = MIB.getOperand(0);
4288  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4289 }
4290 
4291 // Addressing mode relations.
4293  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4294 }
4295 
4297  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4298 }
4299 
4301  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4302 }
4303 
4305  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4306 }
4307 
4309  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4310 }
4311 
4313  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4314 }
4315 
4317  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4318 }
4319 
4321  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4322 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
void push_back(const T &Elt)
Definition: SmallVector.h:212
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:864
short changeAddrMode_rr_io(short Opc) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:970
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool isInlineAsm() const
Definition: MachineInstr.h:835
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
Check if the instruction or the bundle of instructions has store to stack slots.
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:905
demanded bits
MachineBasicBlock reference.
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
A debug info location.
Definition: DebugLoc.h:34
F(f)
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:387
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:476
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:635
static MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited)
Find the hardware loop instruction used to set-up the specified loop.
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:491
bool isEndLoopN(unsigned Opcode) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isBundle() const
Definition: MachineInstr.h:856
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
const RegList & Regs
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:485
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:457
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:642
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:522
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const char * getSeparatorString() const
Definition: MCAsmInfo.h:465
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_io_abs(short Opc) const
bool hasUncondBranch(const MachineBasicBlock *B) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:371
short changeAddrMode_abs_io(short Opc) const
unsigned getAddrMode(const MachineInstr &MI) const
int getNonDotCurOp(const MachineInstr &MI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
void setMBB(MachineBasicBlock *MBB)
bool isTC2Early(const MachineInstr &MI) const
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
Address of a basic block.
static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI)
bool isValidAutoIncImm(const EVT VT, const int Offset) const
StringRef getCommentString() const
Definition: MCAsmInfo.h:471
bool isFloat(const MachineInstr &MI) const
void setImm(int64_t immVal)
self_iterator getIterator()
Definition: ilist_node.h:82
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
iterator_range< pred_iterator > predecessors()
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
void genAllInsnTimingClasses(MachineFunction &MF) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
short getPseudoInstrPair(const MachineInstr &MI) const
MCSubRegIterator enumerates all sub-registers of Reg.
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
bool isEarlySourceInstr(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isExtendable(const MachineInstr &MI) const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:225
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
static cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
void setIsKill(bool Val=true)
bool hasPseudoInstrPair(const MachineInstr &MI) const