LLVM  7.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
16 #include "HexagonFrameLowering.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
80 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
98 
99 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
101  cl::desc("Use the DFA based hazard recognizer."));
102 
103 /// Constants for Hexagon instructions.
104 const int Hexagon_MEMW_OFFSET_MAX = 4095;
105 const int Hexagon_MEMW_OFFSET_MIN = -4096;
106 const int Hexagon_MEMD_OFFSET_MAX = 8191;
107 const int Hexagon_MEMD_OFFSET_MIN = -8192;
108 const int Hexagon_MEMH_OFFSET_MAX = 2047;
109 const int Hexagon_MEMH_OFFSET_MIN = -2048;
110 const int Hexagon_MEMB_OFFSET_MAX = 1023;
111 const int Hexagon_MEMB_OFFSET_MIN = -1024;
112 const int Hexagon_ADDI_OFFSET_MAX = 32767;
113 const int Hexagon_ADDI_OFFSET_MIN = -32768;
114 
115 // Pin the vtable to this file.
116 void HexagonInstrInfo::anchor() {}
117 
119  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
120  Subtarget(ST) {}
121 
122 static bool isIntRegForSubInst(unsigned Reg) {
123  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
124  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
125 }
126 
127 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
128  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
129  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
130 }
131 
132 /// Calculate number of instructions excluding the debug instructions.
135  unsigned Count = 0;
136  for (; MIB != MIE; ++MIB) {
137  if (!MIB->isDebugInstr())
138  ++Count;
139  }
140  return Count;
141 }
142 
143 /// Find the hardware loop instruction used to set-up the specified loop.
144 /// On Hexagon, we have two instructions used to set-up the hardware loop
145 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
146 /// to indicate the end of a loop.
148  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
149  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
150  unsigned LOOPi;
151  unsigned LOOPr;
152  if (EndLoopOp == Hexagon::ENDLOOP0) {
153  LOOPi = Hexagon::J2_loop0i;
154  LOOPr = Hexagon::J2_loop0r;
155  } else { // EndLoopOp == Hexagon::EndLOOP1
156  LOOPi = Hexagon::J2_loop1i;
157  LOOPr = Hexagon::J2_loop1r;
158  }
159 
160  // The loop set-up instruction will be in a predecessor block
161  for (MachineBasicBlock *PB : BB->predecessors()) {
162  // If this has been visited, already skip it.
163  if (!Visited.insert(PB).second)
164  continue;
165  if (PB == BB)
166  continue;
167  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
168  unsigned Opc = I->getOpcode();
169  if (Opc == LOOPi || Opc == LOOPr)
170  return &*I;
171  // We've reached a different loop, which means the loop01 has been
172  // removed.
173  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
174  return nullptr;
175  }
176  // Check the predecessors for the LOOP instruction.
177  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
178  return Loop;
179  }
180  return nullptr;
181 }
182 
183 /// Gather register def/uses from MI.
184 /// This treats possible (predicated) defs as actually happening ones
185 /// (conservatively).
186 static inline void parseOperands(const MachineInstr &MI,
188  Defs.clear();
189  Uses.clear();
190 
191  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
192  const MachineOperand &MO = MI.getOperand(i);
193 
194  if (!MO.isReg())
195  continue;
196 
197  unsigned Reg = MO.getReg();
198  if (!Reg)
199  continue;
200 
201  if (MO.isUse())
202  Uses.push_back(MO.getReg());
203 
204  if (MO.isDef())
205  Defs.push_back(MO.getReg());
206  }
207 }
208 
209 // Position dependent, so check twice for swap.
210 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
211  switch (Ga) {
213  default:
214  return false;
215  case HexagonII::HSIG_L1:
216  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
217  case HexagonII::HSIG_L2:
218  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
219  Gb == HexagonII::HSIG_A);
220  case HexagonII::HSIG_S1:
221  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
222  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
223  case HexagonII::HSIG_S2:
224  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
225  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
226  Gb == HexagonII::HSIG_A);
227  case HexagonII::HSIG_A:
228  return (Gb == HexagonII::HSIG_A);
230  return (Gb == HexagonII::HSIG_Compound);
231  }
232  return false;
233 }
234 
235 /// isLoadFromStackSlot - If the specified machine instruction is a direct
236 /// load from a stack slot, return the virtual or physical register number of
237 /// the destination along with the FrameIndex of the loaded stack slot. If
238 /// not, return 0. This predicate must return 0 if the instruction has
239 /// any side effects other than loading from the stack slot.
241  int &FrameIndex) const {
242  switch (MI.getOpcode()) {
243  default:
244  break;
245  case Hexagon::L2_loadri_io:
246  case Hexagon::L2_loadrd_io:
247  case Hexagon::V6_vL32b_ai:
248  case Hexagon::V6_vL32b_nt_ai:
249  case Hexagon::V6_vL32Ub_ai:
250  case Hexagon::LDriw_pred:
251  case Hexagon::LDriw_ctr:
252  case Hexagon::PS_vloadrq_ai:
253  case Hexagon::PS_vloadrw_ai:
254  case Hexagon::PS_vloadrw_nt_ai: {
255  const MachineOperand OpFI = MI.getOperand(1);
256  if (!OpFI.isFI())
257  return 0;
258  const MachineOperand OpOff = MI.getOperand(2);
259  if (!OpOff.isImm() || OpOff.getImm() != 0)
260  return 0;
261  FrameIndex = OpFI.getIndex();
262  return MI.getOperand(0).getReg();
263  }
264 
265  case Hexagon::L2_ploadrit_io:
266  case Hexagon::L2_ploadrif_io:
267  case Hexagon::L2_ploadrdt_io:
268  case Hexagon::L2_ploadrdf_io: {
269  const MachineOperand OpFI = MI.getOperand(2);
270  if (!OpFI.isFI())
271  return 0;
272  const MachineOperand OpOff = MI.getOperand(3);
273  if (!OpOff.isImm() || OpOff.getImm() != 0)
274  return 0;
275  FrameIndex = OpFI.getIndex();
276  return MI.getOperand(0).getReg();
277  }
278  }
279 
280  return 0;
281 }
282 
283 /// isStoreToStackSlot - If the specified machine instruction is a direct
284 /// store to a stack slot, return the virtual or physical register number of
285 /// the source reg along with the FrameIndex of the loaded stack slot. If
286 /// not, return 0. This predicate must return 0 if the instruction has
287 /// any side effects other than storing to the stack slot.
289  int &FrameIndex) const {
290  switch (MI.getOpcode()) {
291  default:
292  break;
293  case Hexagon::S2_storerb_io:
294  case Hexagon::S2_storerh_io:
295  case Hexagon::S2_storeri_io:
296  case Hexagon::S2_storerd_io:
297  case Hexagon::V6_vS32b_ai:
298  case Hexagon::V6_vS32Ub_ai:
299  case Hexagon::STriw_pred:
300  case Hexagon::STriw_ctr:
301  case Hexagon::PS_vstorerq_ai:
302  case Hexagon::PS_vstorerw_ai: {
303  const MachineOperand &OpFI = MI.getOperand(0);
304  if (!OpFI.isFI())
305  return 0;
306  const MachineOperand &OpOff = MI.getOperand(1);
307  if (!OpOff.isImm() || OpOff.getImm() != 0)
308  return 0;
309  FrameIndex = OpFI.getIndex();
310  return MI.getOperand(2).getReg();
311  }
312 
313  case Hexagon::S2_pstorerbt_io:
314  case Hexagon::S2_pstorerbf_io:
315  case Hexagon::S2_pstorerht_io:
316  case Hexagon::S2_pstorerhf_io:
317  case Hexagon::S2_pstorerit_io:
318  case Hexagon::S2_pstorerif_io:
319  case Hexagon::S2_pstorerdt_io:
320  case Hexagon::S2_pstorerdf_io: {
321  const MachineOperand &OpFI = MI.getOperand(1);
322  if (!OpFI.isFI())
323  return 0;
324  const MachineOperand &OpOff = MI.getOperand(2);
325  if (!OpOff.isImm() || OpOff.getImm() != 0)
326  return 0;
327  FrameIndex = OpFI.getIndex();
328  return MI.getOperand(3).getReg();
329  }
330  }
331 
332  return 0;
333 }
334 
335 /// This function checks if the instruction or bundle of instructions
336 /// has load from stack slot and returns frameindex and machine memory
337 /// operand of that instruction if true.
339  const MachineMemOperand *&MMO,
340  int &FrameIndex) const {
341  if (MI.isBundle()) {
342  const MachineBasicBlock *MBB = MI.getParent();
344  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
345  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, MMO, FrameIndex))
346  return true;
347  return false;
348  }
349 
350  return TargetInstrInfo::hasLoadFromStackSlot(MI, MMO, FrameIndex);
351 }
352 
353 /// This function checks if the instruction or bundle of instructions
354 /// has store to stack slot and returns frameindex and machine memory
355 /// operand of that instruction if true.
357  const MachineMemOperand *&MMO,
358  int &FrameIndex) const {
359  if (MI.isBundle()) {
360  const MachineBasicBlock *MBB = MI.getParent();
362  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
363  if (TargetInstrInfo::hasStoreToStackSlot(*MII, MMO, FrameIndex))
364  return true;
365  return false;
366  }
367 
368  return TargetInstrInfo::hasStoreToStackSlot(MI, MMO, FrameIndex);
369 }
370 
371 /// This function can analyze one/two way branching only and should (mostly) be
372 /// called by target independent side.
373 /// First entry is always the opcode of the branching instruction, except when
374 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
375 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
376 /// e.g. Jump_c p will have
377 /// Cond[0] = Jump_c
378 /// Cond[1] = p
379 /// HW-loop ENDLOOP:
380 /// Cond[0] = ENDLOOP
381 /// Cond[1] = MBB
382 /// New value jump:
383 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
384 /// Cond[1] = R
385 /// Cond[2] = Imm
387  MachineBasicBlock *&TBB,
388  MachineBasicBlock *&FBB,
390  bool AllowModify) const {
391  TBB = nullptr;
392  FBB = nullptr;
393  Cond.clear();
394 
395  // If the block has no terminators, it just falls into the block after it.
397  if (I == MBB.instr_begin())
398  return false;
399 
400  // A basic block may looks like this:
401  //
402  // [ insn
403  // EH_LABEL
404  // insn
405  // insn
406  // insn
407  // EH_LABEL
408  // insn ]
409  //
410  // It has two succs but does not have a terminator
411  // Don't know how to handle it.
412  do {
413  --I;
414  if (I->isEHLabel())
415  // Don't analyze EH branches.
416  return true;
417  } while (I != MBB.instr_begin());
418 
419  I = MBB.instr_end();
420  --I;
421 
422  while (I->isDebugInstr()) {
423  if (I == MBB.instr_begin())
424  return false;
425  --I;
426  }
427 
428  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
429  I->getOperand(0).isMBB();
430  // Delete the J2_jump if it's equivalent to a fall-through.
431  if (AllowModify && JumpToBlock &&
432  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
433  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
434  I->eraseFromParent();
435  I = MBB.instr_end();
436  if (I == MBB.instr_begin())
437  return false;
438  --I;
439  }
440  if (!isUnpredicatedTerminator(*I))
441  return false;
442 
443  // Get the last instruction in the block.
444  MachineInstr *LastInst = &*I;
445  MachineInstr *SecondLastInst = nullptr;
446  // Find one more terminator if present.
447  while (true) {
448  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
449  if (!SecondLastInst)
450  SecondLastInst = &*I;
451  else
452  // This is a third branch.
453  return true;
454  }
455  if (I == MBB.instr_begin())
456  break;
457  --I;
458  }
459 
460  int LastOpcode = LastInst->getOpcode();
461  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
462  // If the branch target is not a basic block, it could be a tail call.
463  // (It is, if the target is a function.)
464  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
465  return true;
466  if (SecLastOpcode == Hexagon::J2_jump &&
467  !SecondLastInst->getOperand(0).isMBB())
468  return true;
469 
470  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
471  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
472 
473  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
474  return true;
475 
476  // If there is only one terminator instruction, process it.
477  if (LastInst && !SecondLastInst) {
478  if (LastOpcode == Hexagon::J2_jump) {
479  TBB = LastInst->getOperand(0).getMBB();
480  return false;
481  }
482  if (isEndLoopN(LastOpcode)) {
483  TBB = LastInst->getOperand(0).getMBB();
484  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
485  Cond.push_back(LastInst->getOperand(0));
486  return false;
487  }
488  if (LastOpcodeHasJMP_c) {
489  TBB = LastInst->getOperand(1).getMBB();
490  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
491  Cond.push_back(LastInst->getOperand(0));
492  return false;
493  }
494  // Only supporting rr/ri versions of new-value jumps.
495  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
496  TBB = LastInst->getOperand(2).getMBB();
497  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
498  Cond.push_back(LastInst->getOperand(0));
499  Cond.push_back(LastInst->getOperand(1));
500  return false;
501  }
502  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
503  << " with one jump\n";);
504  // Otherwise, don't know what this is.
505  return true;
506  }
507 
508  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
509  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
510  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
511  if (!SecondLastInst->getOperand(1).isMBB())
512  return true;
513  TBB = SecondLastInst->getOperand(1).getMBB();
514  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
515  Cond.push_back(SecondLastInst->getOperand(0));
516  FBB = LastInst->getOperand(0).getMBB();
517  return false;
518  }
519 
520  // Only supporting rr/ri versions of new-value jumps.
521  if (SecLastOpcodeHasNVJump &&
522  (SecondLastInst->getNumExplicitOperands() == 3) &&
523  (LastOpcode == Hexagon::J2_jump)) {
524  TBB = SecondLastInst->getOperand(2).getMBB();
525  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
526  Cond.push_back(SecondLastInst->getOperand(0));
527  Cond.push_back(SecondLastInst->getOperand(1));
528  FBB = LastInst->getOperand(0).getMBB();
529  return false;
530  }
531 
532  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
533  // executed, so remove it.
534  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
535  TBB = SecondLastInst->getOperand(0).getMBB();
536  I = LastInst->getIterator();
537  if (AllowModify)
538  I->eraseFromParent();
539  return false;
540  }
541 
542  // If the block ends with an ENDLOOP, and J2_jump, handle it.
543  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
544  TBB = SecondLastInst->getOperand(0).getMBB();
545  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
546  Cond.push_back(SecondLastInst->getOperand(0));
547  FBB = LastInst->getOperand(0).getMBB();
548  return false;
549  }
550  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
551  << " with two jumps";);
552  // Otherwise, can't handle this.
553  return true;
554 }
555 
557  int *BytesRemoved) const {
558  assert(!BytesRemoved && "code size not handled");
559 
560  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
562  unsigned Count = 0;
563  while (I != MBB.begin()) {
564  --I;
565  if (I->isDebugInstr())
566  continue;
567  // Only removing branches from end of MBB.
568  if (!I->isBranch())
569  return Count;
570  if (Count && (I->getOpcode() == Hexagon::J2_jump))
571  llvm_unreachable("Malformed basic block: unconditional branch not last");
572  MBB.erase(&MBB.back());
573  I = MBB.end();
574  ++Count;
575  }
576  return Count;
577 }
578 
580  MachineBasicBlock *TBB,
581  MachineBasicBlock *FBB,
583  const DebugLoc &DL,
584  int *BytesAdded) const {
585  unsigned BOpc = Hexagon::J2_jump;
586  unsigned BccOpc = Hexagon::J2_jumpt;
587  assert(validateBranchCond(Cond) && "Invalid branching condition");
588  assert(TBB && "insertBranch must not be told to insert a fallthrough");
589  assert(!BytesAdded && "code size not handled");
590 
591  // Check if reverseBranchCondition has asked to reverse this branch
592  // If we want to reverse the branch an odd number of times, we want
593  // J2_jumpf.
594  if (!Cond.empty() && Cond[0].isImm())
595  BccOpc = Cond[0].getImm();
596 
597  if (!FBB) {
598  if (Cond.empty()) {
599  // Due to a bug in TailMerging/CFG Optimization, we need to add a
600  // special case handling of a predicated jump followed by an
601  // unconditional jump. If not, Tail Merging and CFG Optimization go
602  // into an infinite loop.
603  MachineBasicBlock *NewTBB, *NewFBB;
605  auto Term = MBB.getFirstTerminator();
606  if (Term != MBB.end() && isPredicated(*Term) &&
607  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
608  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
610  removeBranch(MBB);
611  return insertBranch(MBB, TBB, nullptr, Cond, DL);
612  }
613  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
614  } else if (isEndLoopN(Cond[0].getImm())) {
615  int EndLoopOp = Cond[0].getImm();
616  assert(Cond[1].isMBB());
617  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
618  // Check for it, and change the BB target if needed.
620  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
621  VisitedBBs);
622  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
623  Loop->getOperand(0).setMBB(TBB);
624  // Add the ENDLOOP after the finding the LOOP0.
625  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
626  } else if (isNewValueJump(Cond[0].getImm())) {
627  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
628  // New value jump
629  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
630  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
631  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
632  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
633  << printMBBReference(MBB););
634  if (Cond[2].isReg()) {
635  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
636  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
637  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
638  } else if(Cond[2].isImm()) {
639  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
640  addImm(Cond[2].getImm()).addMBB(TBB);
641  } else
642  llvm_unreachable("Invalid condition for branching");
643  } else {
644  assert((Cond.size() == 2) && "Malformed cond vector");
645  const MachineOperand &RO = Cond[1];
646  unsigned Flags = getUndefRegState(RO.isUndef());
647  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
648  }
649  return 1;
650  }
651  assert((!Cond.empty()) &&
652  "Cond. cannot be empty when multiple branchings are required");
653  assert((!isNewValueJump(Cond[0].getImm())) &&
654  "NV-jump cannot be inserted with another branch");
655  // Special case for hardware loops. The condition is a basic block.
656  if (isEndLoopN(Cond[0].getImm())) {
657  int EndLoopOp = Cond[0].getImm();
658  assert(Cond[1].isMBB());
659  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
660  // Check for it, and change the BB target if needed.
662  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
663  VisitedBBs);
664  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
665  Loop->getOperand(0).setMBB(TBB);
666  // Add the ENDLOOP after the finding the LOOP0.
667  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
668  } else {
669  const MachineOperand &RO = Cond[1];
670  unsigned Flags = getUndefRegState(RO.isUndef());
671  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
672  }
673  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
674 
675  return 2;
676 }
677 
678 /// Analyze the loop code to find the loop induction variable and compare used
679 /// to compute the number of iterations. Currently, we analyze loop that are
680 /// controlled using hardware loops. In this case, the induction variable
681 /// instruction is null. For all other cases, this function returns true, which
682 /// means we're unable to analyze it.
684  MachineInstr *&IndVarInst,
685  MachineInstr *&CmpInst) const {
686 
687  MachineBasicBlock *LoopEnd = L.getBottomBlock();
689  // We really "analyze" only hardware loops right now.
690  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
691  IndVarInst = nullptr;
692  CmpInst = &*I;
693  return false;
694  }
695  return true;
696 }
697 
698 /// Generate code to reduce the loop iteration by one and check if the loop is
699 /// finished. Return the value/register of the new loop count. this function
700 /// assumes the nth iteration is peeled first.
702  MachineInstr *IndVar, MachineInstr &Cmp,
705  unsigned Iter, unsigned MaxIter) const {
706  // We expect a hardware loop currently. This means that IndVar is set
707  // to null, and the compare is the ENDLOOP instruction.
708  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
709  && "Expecting a hardware loop");
710  MachineFunction *MF = MBB.getParent();
711  DebugLoc DL = Cmp.getDebugLoc();
713  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
714  Cmp.getOperand(0).getMBB(), VisitedBBs);
715  if (!Loop)
716  return 0;
717  // If the loop trip count is a compile-time value, then just change the
718  // value.
719  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
720  Loop->getOpcode() == Hexagon::J2_loop1i) {
721  int64_t Offset = Loop->getOperand(1).getImm();
722  if (Offset <= 1)
723  Loop->eraseFromParent();
724  else
725  Loop->getOperand(1).setImm(Offset - 1);
726  return Offset - 1;
727  }
728  // The loop trip count is a run-time value. We generate code to subtract
729  // one from the trip count, and update the loop instruction.
730  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
731  unsigned LoopCount = Loop->getOperand(1).getReg();
732  // Check if we're done with the loop.
733  unsigned LoopEnd = createVR(MF, MVT::i1);
734  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
735  addReg(LoopCount).addImm(1);
736  unsigned NewLoopCount = createVR(MF, MVT::i32);
737  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
738  addReg(LoopCount).addImm(-1);
739  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
740  // Update the previously generated instructions with the new loop counter.
742  E = PrevInsts.end(); I != E; ++I)
743  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
744  PrevInsts.clear();
745  PrevInsts.push_back(NewCmp);
746  PrevInsts.push_back(NewAdd);
747  // Insert the new loop instruction if this is the last time the loop is
748  // decremented.
749  if (Iter == MaxIter)
750  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
751  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
752  // Delete the old loop instruction.
753  if (Iter == 0)
754  Loop->eraseFromParent();
755  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
756  Cond.push_back(NewCmp->getOperand(0));
757  return NewLoopCount;
758 }
759 
761  unsigned NumCycles, unsigned ExtraPredCycles,
762  BranchProbability Probability) const {
763  return nonDbgBBSize(&MBB) <= 3;
764 }
765 
767  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
768  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
769  const {
770  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
771 }
772 
774  unsigned NumInstrs, BranchProbability Probability) const {
775  return NumInstrs <= 4;
776 }
777 
780  const DebugLoc &DL, unsigned DestReg,
781  unsigned SrcReg, bool KillSrc) const {
782  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
783  unsigned KillFlag = getKillRegState(KillSrc);
784 
785  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
786  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
787  .addReg(SrcReg, KillFlag);
788  return;
789  }
790  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
791  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
792  .addReg(SrcReg, KillFlag);
793  return;
794  }
795  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
796  // Map Pd = Ps to Pd = or(Ps, Ps).
797  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
798  .addReg(SrcReg).addReg(SrcReg, KillFlag);
799  return;
800  }
801  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
802  Hexagon::IntRegsRegClass.contains(SrcReg)) {
803  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
804  .addReg(SrcReg, KillFlag);
805  return;
806  }
807  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
808  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
809  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
810  .addReg(SrcReg, KillFlag);
811  return;
812  }
813  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
814  Hexagon::IntRegsRegClass.contains(SrcReg)) {
815  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
816  .addReg(SrcReg, KillFlag);
817  return;
818  }
819  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
820  Hexagon::IntRegsRegClass.contains(DestReg)) {
821  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
822  .addReg(SrcReg, KillFlag);
823  return;
824  }
825  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
826  Hexagon::PredRegsRegClass.contains(DestReg)) {
827  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
828  .addReg(SrcReg, KillFlag);
829  return;
830  }
831  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
832  Hexagon::IntRegsRegClass.contains(DestReg)) {
833  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
834  .addReg(SrcReg, KillFlag);
835  return;
836  }
837  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
838  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
839  addReg(SrcReg, KillFlag);
840  return;
841  }
842  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
843  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
844  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
845  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
846  .addReg(HiSrc, KillFlag)
847  .addReg(LoSrc, KillFlag);
848  return;
849  }
850  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
851  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
852  .addReg(SrcReg)
853  .addReg(SrcReg, KillFlag);
854  return;
855  }
856  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
857  Hexagon::HvxVRRegClass.contains(DestReg)) {
858  llvm_unreachable("Unimplemented pred to vec");
859  return;
860  }
861  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
862  Hexagon::HvxVRRegClass.contains(SrcReg)) {
863  llvm_unreachable("Unimplemented vec to pred");
864  return;
865  }
866 
867 #ifndef NDEBUG
868  // Show the invalid registers to ease debugging.
869  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
870  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
871 #endif
872  llvm_unreachable("Unimplemented");
873 }
874 
876  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
877  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
878  DebugLoc DL = MBB.findDebugLoc(I);
879  MachineFunction &MF = *MBB.getParent();
880  MachineFrameInfo &MFI = MF.getFrameInfo();
881  unsigned SlotAlign = MFI.getObjectAlignment(FI);
882  unsigned RegAlign = TRI->getSpillAlignment(*RC);
883  unsigned KillFlag = getKillRegState(isKill);
884  bool HasAlloca = MFI.hasVarSizedObjects();
885  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
886 
889  MFI.getObjectSize(FI), SlotAlign);
890 
891  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
892  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
893  .addFrameIndex(FI).addImm(0)
894  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
895  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
896  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
897  .addFrameIndex(FI).addImm(0)
898  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
899  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
900  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
901  .addFrameIndex(FI).addImm(0)
902  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
903  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
904  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
905  .addFrameIndex(FI).addImm(0)
906  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
907  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
908  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
909  .addFrameIndex(FI).addImm(0)
910  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
911  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
912  // If there are variable-sized objects, spills will not be aligned.
913  if (HasAlloca)
914  SlotAlign = HFI.getStackAlignment();
915  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
916  : Hexagon::V6_vS32b_ai;
919  MFI.getObjectSize(FI), SlotAlign);
920  BuildMI(MBB, I, DL, get(Opc))
921  .addFrameIndex(FI).addImm(0)
922  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
923  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
924  // If there are variable-sized objects, spills will not be aligned.
925  if (HasAlloca)
926  SlotAlign = HFI.getStackAlignment();
927  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
928  : Hexagon::PS_vstorerw_ai;
931  MFI.getObjectSize(FI), SlotAlign);
932  BuildMI(MBB, I, DL, get(Opc))
933  .addFrameIndex(FI).addImm(0)
934  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
935  } else {
936  llvm_unreachable("Unimplemented");
937  }
938 }
939 
941  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
942  int FI, const TargetRegisterClass *RC,
943  const TargetRegisterInfo *TRI) const {
944  DebugLoc DL = MBB.findDebugLoc(I);
945  MachineFunction &MF = *MBB.getParent();
946  MachineFrameInfo &MFI = MF.getFrameInfo();
947  unsigned SlotAlign = MFI.getObjectAlignment(FI);
948  unsigned RegAlign = TRI->getSpillAlignment(*RC);
949  bool HasAlloca = MFI.hasVarSizedObjects();
950  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
951 
954  MFI.getObjectSize(FI), SlotAlign);
955 
956  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
957  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
958  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
959  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
960  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
961  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
962  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
963  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
964  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
965  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
966  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
967  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
968  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
969  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
970  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
972  // If there are variable-sized objects, spills will not be aligned.
973  if (HasAlloca)
974  SlotAlign = HFI.getStackAlignment();
975  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
976  : Hexagon::V6_vL32b_ai;
979  MFI.getObjectSize(FI), SlotAlign);
980  BuildMI(MBB, I, DL, get(Opc), DestReg)
981  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
982  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
983  // If there are variable-sized objects, spills will not be aligned.
984  if (HasAlloca)
985  SlotAlign = HFI.getStackAlignment();
986  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
987  : Hexagon::PS_vloadrw_ai;
990  MFI.getObjectSize(FI), SlotAlign);
991  BuildMI(MBB, I, DL, get(Opc), DestReg)
992  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
993  } else {
994  llvm_unreachable("Can't store this register to stack slot");
995  }
996 }
997 
999  const MachineBasicBlock &B = *MI.getParent();
1000  Regs.addLiveOuts(B);
1001  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1002  for (auto I = B.rbegin(); I != E; ++I)
1003  Regs.stepBackward(*I);
1004 }
1005 
1006 /// expandPostRAPseudo - This function is called for all pseudo instructions
1007 /// that remain after register allocation. Many pseudo instructions are
1008 /// created to help register allocation. This is the place to convert them
1009 /// into real instructions. The target can edit MI in place, or it can insert
1010 /// new instructions and erase MI. The function should return true if
1011 /// anything was changed.
1013  MachineBasicBlock &MBB = *MI.getParent();
1014  MachineFunction &MF = *MBB.getParent();
1016  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1017  DebugLoc DL = MI.getDebugLoc();
1018  unsigned Opc = MI.getOpcode();
1019 
1020  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1021  unsigned Mx = MI.getOperand(MxOp).getReg();
1022  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1023  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1024  .add(MI.getOperand((HasImm ? 5 : 4)));
1025  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1026  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1027  if (HasImm)
1028  MIB.add(MI.getOperand(4));
1029  MIB.addReg(CSx, RegState::Implicit);
1030  MBB.erase(MI);
1031  return true;
1032  };
1033 
1034  switch (Opc) {
1035  case TargetOpcode::COPY: {
1036  MachineOperand &MD = MI.getOperand(0);
1037  MachineOperand &MS = MI.getOperand(1);
1039  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1040  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1041  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1042  }
1043  MBB.erase(MBBI);
1044  return true;
1045  }
1046  case Hexagon::PS_aligna:
1047  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1048  .addReg(HRI.getFrameRegister())
1049  .addImm(-MI.getOperand(1).getImm());
1050  MBB.erase(MI);
1051  return true;
1052  case Hexagon::V6_vassignp: {
1053  unsigned SrcReg = MI.getOperand(1).getReg();
1054  unsigned DstReg = MI.getOperand(0).getReg();
1055  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1056  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1057  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1058  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1059  MBB.erase(MI);
1060  return true;
1061  }
1062  case Hexagon::V6_lo: {
1063  unsigned SrcReg = MI.getOperand(1).getReg();
1064  unsigned DstReg = MI.getOperand(0).getReg();
1065  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1066  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1067  MBB.erase(MI);
1068  MRI.clearKillFlags(SrcSubLo);
1069  return true;
1070  }
1071  case Hexagon::V6_hi: {
1072  unsigned SrcReg = MI.getOperand(1).getReg();
1073  unsigned DstReg = MI.getOperand(0).getReg();
1074  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1075  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1076  MBB.erase(MI);
1077  MRI.clearKillFlags(SrcSubHi);
1078  return true;
1079  }
1080  case Hexagon::PS_vstorerw_ai:
1081  case Hexagon::PS_vstorerwu_ai: {
1082  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1083  unsigned SrcReg = MI.getOperand(2).getReg();
1084  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1085  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1086  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1087  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1088 
1089  MachineInstr *MI1New =
1090  BuildMI(MBB, MI, DL, get(NewOpc))
1091  .add(MI.getOperand(0))
1092  .addImm(MI.getOperand(1).getImm())
1093  .addReg(SrcSubLo)
1095  MI1New->getOperand(0).setIsKill(false);
1096  BuildMI(MBB, MI, DL, get(NewOpc))
1097  .add(MI.getOperand(0))
1098  // The Vectors are indexed in multiples of vector size.
1099  .addImm(MI.getOperand(1).getImm() + Offset)
1100  .addReg(SrcSubHi)
1102  MBB.erase(MI);
1103  return true;
1104  }
1105  case Hexagon::PS_vloadrw_ai:
1106  case Hexagon::PS_vloadrwu_ai: {
1107  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1108  unsigned DstReg = MI.getOperand(0).getReg();
1109  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1110  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1111 
1112  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1113  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1114  .add(MI.getOperand(1))
1115  .addImm(MI.getOperand(2).getImm())
1116  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1117  MI1New->getOperand(1).setIsKill(false);
1118  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1119  .add(MI.getOperand(1))
1120  // The Vectors are indexed in multiples of vector size.
1121  .addImm(MI.getOperand(2).getImm() + Offset)
1122  .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1123  MBB.erase(MI);
1124  return true;
1125  }
1126  case Hexagon::PS_true: {
1127  unsigned Reg = MI.getOperand(0).getReg();
1128  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1129  .addReg(Reg, RegState::Undef)
1130  .addReg(Reg, RegState::Undef);
1131  MBB.erase(MI);
1132  return true;
1133  }
1134  case Hexagon::PS_false: {
1135  unsigned Reg = MI.getOperand(0).getReg();
1136  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1137  .addReg(Reg, RegState::Undef)
1138  .addReg(Reg, RegState::Undef);
1139  MBB.erase(MI);
1140  return true;
1141  }
1142  case Hexagon::PS_qtrue: {
1143  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1144  .addReg(Hexagon::V0, RegState::Undef)
1145  .addReg(Hexagon::V0, RegState::Undef);
1146  MBB.erase(MI);
1147  return true;
1148  }
1149  case Hexagon::PS_qfalse: {
1150  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1151  .addReg(Hexagon::V0, RegState::Undef)
1152  .addReg(Hexagon::V0, RegState::Undef);
1153  MBB.erase(MI);
1154  return true;
1155  }
1156  case Hexagon::PS_vmulw: {
1157  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1158  unsigned DstReg = MI.getOperand(0).getReg();
1159  unsigned Src1Reg = MI.getOperand(1).getReg();
1160  unsigned Src2Reg = MI.getOperand(2).getReg();
1161  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1162  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1163  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1164  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1165  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1166  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1167  .addReg(Src1SubHi)
1168  .addReg(Src2SubHi);
1169  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1170  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1171  .addReg(Src1SubLo)
1172  .addReg(Src2SubLo);
1173  MBB.erase(MI);
1174  MRI.clearKillFlags(Src1SubHi);
1175  MRI.clearKillFlags(Src1SubLo);
1176  MRI.clearKillFlags(Src2SubHi);
1177  MRI.clearKillFlags(Src2SubLo);
1178  return true;
1179  }
1180  case Hexagon::PS_vmulw_acc: {
1181  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1182  unsigned DstReg = MI.getOperand(0).getReg();
1183  unsigned Src1Reg = MI.getOperand(1).getReg();
1184  unsigned Src2Reg = MI.getOperand(2).getReg();
1185  unsigned Src3Reg = MI.getOperand(3).getReg();
1186  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1187  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1188  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1189  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1190  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1191  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1192  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1193  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1194  .addReg(Src1SubHi)
1195  .addReg(Src2SubHi)
1196  .addReg(Src3SubHi);
1197  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1198  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1199  .addReg(Src1SubLo)
1200  .addReg(Src2SubLo)
1201  .addReg(Src3SubLo);
1202  MBB.erase(MI);
1203  MRI.clearKillFlags(Src1SubHi);
1204  MRI.clearKillFlags(Src1SubLo);
1205  MRI.clearKillFlags(Src2SubHi);
1206  MRI.clearKillFlags(Src2SubLo);
1207  MRI.clearKillFlags(Src3SubHi);
1208  MRI.clearKillFlags(Src3SubLo);
1209  return true;
1210  }
1211  case Hexagon::PS_pselect: {
1212  const MachineOperand &Op0 = MI.getOperand(0);
1213  const MachineOperand &Op1 = MI.getOperand(1);
1214  const MachineOperand &Op2 = MI.getOperand(2);
1215  const MachineOperand &Op3 = MI.getOperand(3);
1216  unsigned Rd = Op0.getReg();
1217  unsigned Pu = Op1.getReg();
1218  unsigned Rs = Op2.getReg();
1219  unsigned Rt = Op3.getReg();
1220  DebugLoc DL = MI.getDebugLoc();
1221  unsigned K1 = getKillRegState(Op1.isKill());
1222  unsigned K2 = getKillRegState(Op2.isKill());
1223  unsigned K3 = getKillRegState(Op3.isKill());
1224  if (Rd != Rs)
1225  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1226  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1227  .addReg(Rs, K2);
1228  if (Rd != Rt)
1229  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1230  .addReg(Pu, K1)
1231  .addReg(Rt, K3);
1232  MBB.erase(MI);
1233  return true;
1234  }
1235  case Hexagon::PS_vselect: {
1236  const MachineOperand &Op0 = MI.getOperand(0);
1237  const MachineOperand &Op1 = MI.getOperand(1);
1238  const MachineOperand &Op2 = MI.getOperand(2);
1239  const MachineOperand &Op3 = MI.getOperand(3);
1240  LivePhysRegs LiveAtMI(HRI);
1241  getLiveRegsAt(LiveAtMI, MI);
1242  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1243  unsigned PReg = Op1.getReg();
1244  assert(Op1.getSubReg() == 0);
1245  unsigned PState = getRegState(Op1);
1246 
1247  if (Op0.getReg() != Op2.getReg()) {
1248  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1249  : PState;
1250  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1251  .add(Op0)
1252  .addReg(PReg, S)
1253  .add(Op2);
1254  if (IsDestLive)
1255  T.addReg(Op0.getReg(), RegState::Implicit);
1256  IsDestLive = true;
1257  }
1258  if (Op0.getReg() != Op3.getReg()) {
1259  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1260  .add(Op0)
1261  .addReg(PReg, PState)
1262  .add(Op3);
1263  if (IsDestLive)
1264  T.addReg(Op0.getReg(), RegState::Implicit);
1265  }
1266  MBB.erase(MI);
1267  return true;
1268  }
1269  case Hexagon::PS_wselect: {
1270  MachineOperand &Op0 = MI.getOperand(0);
1271  MachineOperand &Op1 = MI.getOperand(1);
1272  MachineOperand &Op2 = MI.getOperand(2);
1273  MachineOperand &Op3 = MI.getOperand(3);
1274  LivePhysRegs LiveAtMI(HRI);
1275  getLiveRegsAt(LiveAtMI, MI);
1276  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1277  unsigned PReg = Op1.getReg();
1278  assert(Op1.getSubReg() == 0);
1279  unsigned PState = getRegState(Op1);
1280 
1281  if (Op0.getReg() != Op2.getReg()) {
1282  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1283  : PState;
1284  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1285  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1286  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1287  .add(Op0)
1288  .addReg(PReg, S)
1289  .add(Op1)
1290  .addReg(SrcHi)
1291  .addReg(SrcLo);
1292  if (IsDestLive)
1293  T.addReg(Op0.getReg(), RegState::Implicit);
1294  IsDestLive = true;
1295  }
1296  if (Op0.getReg() != Op3.getReg()) {
1297  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1298  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1299  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1300  .add(Op0)
1301  .addReg(PReg, PState)
1302  .addReg(SrcHi)
1303  .addReg(SrcLo);
1304  if (IsDestLive)
1305  T.addReg(Op0.getReg(), RegState::Implicit);
1306  }
1307  MBB.erase(MI);
1308  return true;
1309  }
1310 
1311  case Hexagon::PS_tailcall_i:
1312  MI.setDesc(get(Hexagon::J2_jump));
1313  return true;
1314  case Hexagon::PS_tailcall_r:
1315  case Hexagon::PS_jmpret:
1316  MI.setDesc(get(Hexagon::J2_jumpr));
1317  return true;
1318  case Hexagon::PS_jmprett:
1319  MI.setDesc(get(Hexagon::J2_jumprt));
1320  return true;
1321  case Hexagon::PS_jmpretf:
1322  MI.setDesc(get(Hexagon::J2_jumprf));
1323  return true;
1324  case Hexagon::PS_jmprettnewpt:
1325  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1326  return true;
1327  case Hexagon::PS_jmpretfnewpt:
1328  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1329  return true;
1330  case Hexagon::PS_jmprettnew:
1331  MI.setDesc(get(Hexagon::J2_jumprtnew));
1332  return true;
1333  case Hexagon::PS_jmpretfnew:
1334  MI.setDesc(get(Hexagon::J2_jumprfnew));
1335  return true;
1336 
1337  case Hexagon::V6_vgathermh_pseudo:
1338  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1339  .add(MI.getOperand(1))
1340  .add(MI.getOperand(2))
1341  .add(MI.getOperand(3));
1342  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1343  .add(MI.getOperand(0))
1344  .addImm(0)
1345  .addReg(Hexagon::VTMP);
1346  MBB.erase(MI);
1347  return true;
1348 
1349  case Hexagon::V6_vgathermw_pseudo:
1350  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1351  .add(MI.getOperand(1))
1352  .add(MI.getOperand(2))
1353  .add(MI.getOperand(3));
1354  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1355  .add(MI.getOperand(0))
1356  .addImm(0)
1357  .addReg(Hexagon::VTMP);
1358  MBB.erase(MI);
1359  return true;
1360 
1361  case Hexagon::V6_vgathermhw_pseudo:
1362  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1363  .add(MI.getOperand(1))
1364  .add(MI.getOperand(2))
1365  .add(MI.getOperand(3));
1366  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1367  .add(MI.getOperand(0))
1368  .addImm(0)
1369  .addReg(Hexagon::VTMP);
1370  MBB.erase(MI);
1371  return true;
1372 
1373  case Hexagon::V6_vgathermhq_pseudo:
1374  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1375  .add(MI.getOperand(1))
1376  .add(MI.getOperand(2))
1377  .add(MI.getOperand(3))
1378  .add(MI.getOperand(4));
1379  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1380  .add(MI.getOperand(0))
1381  .addImm(0)
1382  .addReg(Hexagon::VTMP);
1383  MBB.erase(MI);
1384  return true;
1385 
1386  case Hexagon::V6_vgathermwq_pseudo:
1387  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1388  .add(MI.getOperand(1))
1389  .add(MI.getOperand(2))
1390  .add(MI.getOperand(3))
1391  .add(MI.getOperand(4));
1392  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1393  .add(MI.getOperand(0))
1394  .addImm(0)
1395  .addReg(Hexagon::VTMP);
1396  MBB.erase(MI);
1397  return true;
1398 
1399  case Hexagon::V6_vgathermhwq_pseudo:
1400  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1401  .add(MI.getOperand(1))
1402  .add(MI.getOperand(2))
1403  .add(MI.getOperand(3))
1404  .add(MI.getOperand(4));
1405  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1406  .add(MI.getOperand(0))
1407  .addImm(0)
1408  .addReg(Hexagon::VTMP);
1409  MBB.erase(MI);
1410  return true;
1411 
1412  case Hexagon::PS_loadrub_pci:
1413  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1414  case Hexagon::PS_loadrb_pci:
1415  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1416  case Hexagon::PS_loadruh_pci:
1417  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1418  case Hexagon::PS_loadrh_pci:
1419  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1420  case Hexagon::PS_loadri_pci:
1421  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1422  case Hexagon::PS_loadrd_pci:
1423  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1424  case Hexagon::PS_loadrub_pcr:
1425  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1426  case Hexagon::PS_loadrb_pcr:
1427  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1428  case Hexagon::PS_loadruh_pcr:
1429  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1430  case Hexagon::PS_loadrh_pcr:
1431  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1432  case Hexagon::PS_loadri_pcr:
1433  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1434  case Hexagon::PS_loadrd_pcr:
1435  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1436  case Hexagon::PS_storerb_pci:
1437  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1438  case Hexagon::PS_storerh_pci:
1439  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1440  case Hexagon::PS_storerf_pci:
1441  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1442  case Hexagon::PS_storeri_pci:
1443  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1444  case Hexagon::PS_storerd_pci:
1445  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1446  case Hexagon::PS_storerb_pcr:
1447  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1448  case Hexagon::PS_storerh_pcr:
1449  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1450  case Hexagon::PS_storerf_pcr:
1451  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1452  case Hexagon::PS_storeri_pcr:
1453  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1454  case Hexagon::PS_storerd_pcr:
1455  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1456  }
1457 
1458  return false;
1459 }
1460 
1461 // We indicate that we want to reverse the branch by
1462 // inserting the reversed branching opcode.
1464  SmallVectorImpl<MachineOperand> &Cond) const {
1465  if (Cond.empty())
1466  return true;
1467  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1468  unsigned opcode = Cond[0].getImm();
1469  //unsigned temp;
1470  assert(get(opcode).isBranch() && "Should be a branching condition.");
1471  if (isEndLoopN(opcode))
1472  return true;
1473  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1474  Cond[0].setImm(NewOpcode);
1475  return false;
1476 }
1477 
1480  DebugLoc DL;
1481  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1482 }
1483 
1485  return getAddrMode(MI) == HexagonII::PostInc;
1486 }
1487 
1488 // Returns true if an instruction is predicated irrespective of the predicate
1489 // sense. For example, all of the following will return true.
1490 // if (p0) R1 = add(R2, R3)
1491 // if (!p0) R1 = add(R2, R3)
1492 // if (p0.new) R1 = add(R2, R3)
1493 // if (!p0.new) R1 = add(R2, R3)
1494 // Note: New-value stores are not included here as in the current
1495 // implementation, we don't need to check their predicate sense.
1497  const uint64_t F = MI.getDesc().TSFlags;
1499 }
1500 
1502  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1503  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1504  isEndLoopN(Cond[0].getImm())) {
1505  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1506  return false;
1507  }
1508  int Opc = MI.getOpcode();
1509  assert (isPredicable(MI) && "Expected predicable instruction");
1510  bool invertJump = predOpcodeHasNot(Cond);
1511 
1512  // We have to predicate MI "in place", i.e. after this function returns,
1513  // MI will need to be transformed into a predicated form. To avoid com-
1514  // plicated manipulations with the operands (handling tied operands,
1515  // etc.), build a new temporary instruction, then overwrite MI with it.
1516 
1517  MachineBasicBlock &B = *MI.getParent();
1518  DebugLoc DL = MI.getDebugLoc();
1519  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1520  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1521  unsigned NOp = 0, NumOps = MI.getNumOperands();
1522  while (NOp < NumOps) {
1523  MachineOperand &Op = MI.getOperand(NOp);
1524  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1525  break;
1526  T.add(Op);
1527  NOp++;
1528  }
1529 
1530  unsigned PredReg, PredRegPos, PredRegFlags;
1531  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1532  (void)GotPredReg;
1533  assert(GotPredReg);
1534  T.addReg(PredReg, PredRegFlags);
1535  while (NOp < NumOps)
1536  T.add(MI.getOperand(NOp++));
1537 
1538  MI.setDesc(get(PredOpc));
1539  while (unsigned n = MI.getNumOperands())
1540  MI.RemoveOperand(n-1);
1541  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1542  MI.addOperand(T->getOperand(i));
1543 
1545  B.erase(TI);
1546 
1548  MRI.clearKillFlags(PredReg);
1549  return true;
1550 }
1551 
1553  ArrayRef<MachineOperand> Pred2) const {
1554  // TODO: Fix this
1555  return false;
1556 }
1557 
1559  std::vector<MachineOperand> &Pred) const {
1560  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1561 
1562  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1563  MachineOperand MO = MI.getOperand(oper);
1564  if (MO.isReg()) {
1565  if (!MO.isDef())
1566  continue;
1567  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1568  if (RC == &Hexagon::PredRegsRegClass) {
1569  Pred.push_back(MO);
1570  return true;
1571  }
1572  continue;
1573  } else if (MO.isRegMask()) {
1574  for (unsigned PR : Hexagon::PredRegsRegClass) {
1575  if (!MI.modifiesRegister(PR, &HRI))
1576  continue;
1577  Pred.push_back(MO);
1578  return true;
1579  }
1580  }
1581  }
1582  return false;
1583 }
1584 
1586  if (!MI.getDesc().isPredicable())
1587  return false;
1588 
1589  if (MI.isCall() || isTailCall(MI)) {
1590  if (!Subtarget.usePredicatedCalls())
1591  return false;
1592  }
1593 
1594  // HVX loads are not predicable on v60, but are on v62.
1595  if (!Subtarget.hasV62TOps()) {
1596  switch (MI.getOpcode()) {
1597  case Hexagon::V6_vL32b_ai:
1598  case Hexagon::V6_vL32b_pi:
1599  case Hexagon::V6_vL32b_ppu:
1600  case Hexagon::V6_vL32b_cur_ai:
1601  case Hexagon::V6_vL32b_cur_pi:
1602  case Hexagon::V6_vL32b_cur_ppu:
1603  case Hexagon::V6_vL32b_nt_ai:
1604  case Hexagon::V6_vL32b_nt_pi:
1605  case Hexagon::V6_vL32b_nt_ppu:
1606  case Hexagon::V6_vL32b_tmp_ai:
1607  case Hexagon::V6_vL32b_tmp_pi:
1608  case Hexagon::V6_vL32b_tmp_ppu:
1609  case Hexagon::V6_vL32b_nt_cur_ai:
1610  case Hexagon::V6_vL32b_nt_cur_pi:
1611  case Hexagon::V6_vL32b_nt_cur_ppu:
1612  case Hexagon::V6_vL32b_nt_tmp_ai:
1613  case Hexagon::V6_vL32b_nt_tmp_pi:
1614  case Hexagon::V6_vL32b_nt_tmp_ppu:
1615  return false;
1616  }
1617  }
1618  return true;
1619 }
1620 
1622  const MachineBasicBlock *MBB,
1623  const MachineFunction &MF) const {
1624  // Debug info is never a scheduling boundary. It's necessary to be explicit
1625  // due to the special treatment of IT instructions below, otherwise a
1626  // dbg_value followed by an IT will result in the IT instruction being
1627  // considered a scheduling hazard, which is wrong. It should be the actual
1628  // instruction preceding the dbg_value instruction(s), just like it is
1629  // when debug info is not present.
1630  if (MI.isDebugInstr())
1631  return false;
1632 
1633  // Throwing call is a boundary.
1634  if (MI.isCall()) {
1635  // Don't mess around with no return calls.
1636  if (doesNotReturn(MI))
1637  return true;
1638  // If any of the block's successors is a landing pad, this could be a
1639  // throwing call.
1640  for (auto I : MBB->successors())
1641  if (I->isEHPad())
1642  return true;
1643  }
1644 
1645  // Terminators and labels can't be scheduled around.
1646  if (MI.getDesc().isTerminator() || MI.isPosition())
1647  return true;
1648 
1649  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1650  return true;
1651 
1652  return false;
1653 }
1654 
1655 /// Measure the specified inline asm to determine an approximation of its
1656 /// length.
1657 /// Comments (which run till the next SeparatorString or newline) do not
1658 /// count as an instruction.
1659 /// Any other non-whitespace text is considered an instruction, with
1660 /// multiple instructions separated by SeparatorString or newlines.
1661 /// Variable-length instructions are not handled here; this function
1662 /// may be overloaded in the target code to do that.
1663 /// Hexagon counts the number of ##'s and adjust for that many
1664 /// constant exenders.
1665 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1666  const MCAsmInfo &MAI) const {
1667  StringRef AStr(Str);
1668  // Count the number of instructions in the asm.
1669  bool atInsnStart = true;
1670  unsigned Length = 0;
1671  for (; *Str; ++Str) {
1672  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1673  strlen(MAI.getSeparatorString())) == 0)
1674  atInsnStart = true;
1675  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1676  Length += MAI.getMaxInstLength();
1677  atInsnStart = false;
1678  }
1679  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1680  MAI.getCommentString().size()) == 0)
1681  atInsnStart = false;
1682  }
1683 
1684  // Add to size number of constant extenders seen * 4.
1685  StringRef Occ("##");
1686  Length += AStr.count(Occ)*4;
1687  return Length;
1688 }
1689 
1692  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1693  if (UseDFAHazardRec)
1694  return new HexagonHazardRecognizer(II, this, Subtarget);
1696 }
1697 
1698 /// For a comparison instruction, return the source registers in
1699 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1700 /// compares against in CmpValue. Return true if the comparison instruction
1701 /// can be analyzed.
1702 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1703  unsigned &SrcReg2, int &Mask,
1704  int &Value) const {
1705  unsigned Opc = MI.getOpcode();
1706 
1707  // Set mask and the first source register.
1708  switch (Opc) {
1709  case Hexagon::C2_cmpeq:
1710  case Hexagon::C2_cmpeqp:
1711  case Hexagon::C2_cmpgt:
1712  case Hexagon::C2_cmpgtp:
1713  case Hexagon::C2_cmpgtu:
1714  case Hexagon::C2_cmpgtup:
1715  case Hexagon::C4_cmpneq:
1716  case Hexagon::C4_cmplte:
1717  case Hexagon::C4_cmplteu:
1718  case Hexagon::C2_cmpeqi:
1719  case Hexagon::C2_cmpgti:
1720  case Hexagon::C2_cmpgtui:
1721  case Hexagon::C4_cmpneqi:
1722  case Hexagon::C4_cmplteui:
1723  case Hexagon::C4_cmpltei:
1724  SrcReg = MI.getOperand(1).getReg();
1725  Mask = ~0;
1726  break;
1727  case Hexagon::A4_cmpbeq:
1728  case Hexagon::A4_cmpbgt:
1729  case Hexagon::A4_cmpbgtu:
1730  case Hexagon::A4_cmpbeqi:
1731  case Hexagon::A4_cmpbgti:
1732  case Hexagon::A4_cmpbgtui:
1733  SrcReg = MI.getOperand(1).getReg();
1734  Mask = 0xFF;
1735  break;
1736  case Hexagon::A4_cmpheq:
1737  case Hexagon::A4_cmphgt:
1738  case Hexagon::A4_cmphgtu:
1739  case Hexagon::A4_cmpheqi:
1740  case Hexagon::A4_cmphgti:
1741  case Hexagon::A4_cmphgtui:
1742  SrcReg = MI.getOperand(1).getReg();
1743  Mask = 0xFFFF;
1744  break;
1745  }
1746 
1747  // Set the value/second source register.
1748  switch (Opc) {
1749  case Hexagon::C2_cmpeq:
1750  case Hexagon::C2_cmpeqp:
1751  case Hexagon::C2_cmpgt:
1752  case Hexagon::C2_cmpgtp:
1753  case Hexagon::C2_cmpgtu:
1754  case Hexagon::C2_cmpgtup:
1755  case Hexagon::A4_cmpbeq:
1756  case Hexagon::A4_cmpbgt:
1757  case Hexagon::A4_cmpbgtu:
1758  case Hexagon::A4_cmpheq:
1759  case Hexagon::A4_cmphgt:
1760  case Hexagon::A4_cmphgtu:
1761  case Hexagon::C4_cmpneq:
1762  case Hexagon::C4_cmplte:
1763  case Hexagon::C4_cmplteu:
1764  SrcReg2 = MI.getOperand(2).getReg();
1765  return true;
1766 
1767  case Hexagon::C2_cmpeqi:
1768  case Hexagon::C2_cmpgtui:
1769  case Hexagon::C2_cmpgti:
1770  case Hexagon::C4_cmpneqi:
1771  case Hexagon::C4_cmplteui:
1772  case Hexagon::C4_cmpltei:
1773  case Hexagon::A4_cmpbeqi:
1774  case Hexagon::A4_cmpbgti:
1775  case Hexagon::A4_cmpbgtui:
1776  case Hexagon::A4_cmpheqi:
1777  case Hexagon::A4_cmphgti:
1778  case Hexagon::A4_cmphgtui: {
1779  SrcReg2 = 0;
1780  const MachineOperand &Op2 = MI.getOperand(2);
1781  if (!Op2.isImm())
1782  return false;
1783  Value = MI.getOperand(2).getImm();
1784  return true;
1785  }
1786  }
1787 
1788  return false;
1789 }
1790 
1792  const MachineInstr &MI,
1793  unsigned *PredCost) const {
1794  return getInstrTimingClassLatency(ItinData, MI);
1795 }
1796 
1798  const TargetSubtargetInfo &STI) const {
1799  const InstrItineraryData *II = STI.getInstrItineraryData();
1800  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1801 }
1802 
1803 // Inspired by this pair:
1804 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1805 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1806 // Currently AA considers the addresses in these instructions to be aliasing.
1808  MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1809  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1811  return false;
1812 
1813  // Instructions that are pure loads, not loads and stores like memops are not
1814  // dependent.
1815  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1816  return true;
1817 
1818  // Get the base register in MIa.
1819  unsigned BasePosA, OffsetPosA;
1820  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1821  return false;
1822  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1823  unsigned BaseRegA = BaseA.getReg();
1824  unsigned BaseSubA = BaseA.getSubReg();
1825 
1826  // Get the base register in MIb.
1827  unsigned BasePosB, OffsetPosB;
1828  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1829  return false;
1830  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1831  unsigned BaseRegB = BaseB.getReg();
1832  unsigned BaseSubB = BaseB.getSubReg();
1833 
1834  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1835  return false;
1836 
1837  // Get the access sizes.
1838  unsigned SizeA = getMemAccessSize(MIa);
1839  unsigned SizeB = getMemAccessSize(MIb);
1840 
1841  // Get the offsets. Handle immediates only for now.
1842  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1843  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1844  if (!MIa.getOperand(OffsetPosA).isImm() ||
1845  !MIb.getOperand(OffsetPosB).isImm())
1846  return false;
1847  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1848  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1849 
1850  // This is a mem access with the same base register and known offsets from it.
1851  // Reason about it.
1852  if (OffsetA > OffsetB) {
1853  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1854  return SizeB <= OffDiff;
1855  }
1856  if (OffsetA < OffsetB) {
1857  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1858  return SizeA <= OffDiff;
1859  }
1860 
1861  return false;
1862 }
1863 
1864 /// If the instruction is an increment of a constant value, return the amount.
1866  int &Value) const {
1867  if (isPostIncrement(MI)) {
1868  unsigned BasePos = 0, OffsetPos = 0;
1869  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1870  return false;
1871  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1872  if (OffsetOp.isImm()) {
1873  Value = OffsetOp.getImm();
1874  return true;
1875  }
1876  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1877  const MachineOperand &AddOp = MI.getOperand(2);
1878  if (AddOp.isImm()) {
1879  Value = AddOp.getImm();
1880  return true;
1881  }
1882  }
1883 
1884  return false;
1885 }
1886 
1887 std::pair<unsigned, unsigned>
1889  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1890  TF & HexagonII::MO_Bitmasks);
1891 }
1892 
1895  using namespace HexagonII;
1896 
1897  static const std::pair<unsigned, const char*> Flags[] = {
1898  {MO_PCREL, "hexagon-pcrel"},
1899  {MO_GOT, "hexagon-got"},
1900  {MO_LO16, "hexagon-lo16"},
1901  {MO_HI16, "hexagon-hi16"},
1902  {MO_GPREL, "hexagon-gprel"},
1903  {MO_GDGOT, "hexagon-gdgot"},
1904  {MO_GDPLT, "hexagon-gdplt"},
1905  {MO_IE, "hexagon-ie"},
1906  {MO_IEGOT, "hexagon-iegot"},
1907  {MO_TPREL, "hexagon-tprel"}
1908  };
1909  return makeArrayRef(Flags);
1910 }
1911 
1914  using namespace HexagonII;
1915 
1916  static const std::pair<unsigned, const char*> Flags[] = {
1917  {HMOTF_ConstExtended, "hexagon-ext"}
1918  };
1919  return makeArrayRef(Flags);
1920 }
1921 
1924  const TargetRegisterClass *TRC;
1925  if (VT == MVT::i1) {
1926  TRC = &Hexagon::PredRegsRegClass;
1927  } else if (VT == MVT::i32 || VT == MVT::f32) {
1928  TRC = &Hexagon::IntRegsRegClass;
1929  } else if (VT == MVT::i64 || VT == MVT::f64) {
1930  TRC = &Hexagon::DoubleRegsRegClass;
1931  } else {
1932  llvm_unreachable("Cannot handle this register class");
1933  }
1934 
1935  unsigned NewReg = MRI.createVirtualRegister(TRC);
1936  return NewReg;
1937 }
1938 
1940  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1941 }
1942 
1944  const uint64_t F = MI.getDesc().TSFlags;
1946 }
1947 
1949  return getAddrMode(MI) == HexagonII::BaseImmOffset;
1950 }
1951 
1953  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
1954  !MI.getDesc().mayStore() &&
1955  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
1956  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
1957  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
1958 }
1959 
1960 // Return true if the instruction is a compund branch instruction.
1962  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1963 }
1964 
1965 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1966 // isFPImm and later getFPImm as well.
1968  const uint64_t F = MI.getDesc().TSFlags;
1970  if (isExtended) // Instruction must be extended.
1971  return true;
1972 
1973  unsigned isExtendable =
1975  if (!isExtendable)
1976  return false;
1977 
1978  if (MI.isCall())
1979  return false;
1980 
1981  short ExtOpNum = getCExtOpNum(MI);
1982  const MachineOperand &MO = MI.getOperand(ExtOpNum);
1983  // Use MO operand flags to determine if MO
1984  // has the HMOTF_ConstExtended flag set.
1986  return true;
1987  // If this is a Machine BB address we are talking about, and it is
1988  // not marked as extended, say so.
1989  if (MO.isMBB())
1990  return false;
1991 
1992  // We could be using an instruction with an extendable immediate and shoehorn
1993  // a global address into it. If it is a global address it will be constant
1994  // extended. We do this for COMBINE.
1995  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1996  MO.isJTI() || MO.isCPI() || MO.isFPImm())
1997  return true;
1998 
1999  // If the extendable operand is not 'Immediate' type, the instruction should
2000  // have 'isExtended' flag set.
2001  assert(MO.isImm() && "Extendable operand must be Immediate type");
2002 
2003  int MinValue = getMinValue(MI);
2004  int MaxValue = getMaxValue(MI);
2005  int ImmValue = MO.getImm();
2006 
2007  return (ImmValue < MinValue || ImmValue > MaxValue);
2008 }
2009 
2011  switch (MI.getOpcode()) {
2012  case Hexagon::L4_return:
2013  case Hexagon::L4_return_t:
2014  case Hexagon::L4_return_f:
2015  case Hexagon::L4_return_tnew_pnt:
2016  case Hexagon::L4_return_fnew_pnt:
2017  case Hexagon::L4_return_tnew_pt:
2018  case Hexagon::L4_return_fnew_pt:
2019  return true;
2020  }
2021  return false;
2022 }
2023 
2024 // Return true when ConsMI uses a register defined by ProdMI.
2026  const MachineInstr &ConsMI) const {
2027  if (!ProdMI.getDesc().getNumDefs())
2028  return false;
2029  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2030 
2035 
2036  parseOperands(ProdMI, DefsA, UsesA);
2037  parseOperands(ConsMI, DefsB, UsesB);
2038 
2039  for (auto &RegA : DefsA)
2040  for (auto &RegB : UsesB) {
2041  // True data dependency.
2042  if (RegA == RegB)
2043  return true;
2044 
2046  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2047  if (RegB == *SubRegs)
2048  return true;
2049 
2051  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2052  if (RegA == *SubRegs)
2053  return true;
2054  }
2055 
2056  return false;
2057 }
2058 
2059 // Returns true if the instruction is alread a .cur.
2061  switch (MI.getOpcode()) {
2062  case Hexagon::V6_vL32b_cur_pi:
2063  case Hexagon::V6_vL32b_cur_ai:
2064  return true;
2065  }
2066  return false;
2067 }
2068 
2069 // Returns true, if any one of the operands is a dot new
2070 // insn, whether it is predicated dot new or register dot new.
2072  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2073  return true;
2074 
2075  return false;
2076 }
2077 
2078 /// Symmetrical. See if these two instructions are fit for duplex pair.
2080  const MachineInstr &MIb) const {
2083  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2084 }
2085 
2087  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2088  return true;
2089 
2090  // Multiply
2091  unsigned SchedClass = MI.getDesc().getSchedClass();
2092  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2093 }
2094 
2095 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2096  return (Opcode == Hexagon::ENDLOOP0 ||
2097  Opcode == Hexagon::ENDLOOP1);
2098 }
2099 
2100 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2101  switch(OpType) {
2108  return true;
2109  default:
2110  return false;
2111  }
2112 }
2113 
2115  const MCInstrDesc &MID = MI.getDesc();
2116  const uint64_t F = MID.TSFlags;
2118  return true;
2119 
2120  // TODO: This is largely obsolete now. Will need to be removed
2121  // in consecutive patches.
2122  switch (MI.getOpcode()) {
2123  // PS_fi and PS_fia remain special cases.
2124  case Hexagon::PS_fi:
2125  case Hexagon::PS_fia:
2126  return true;
2127  default:
2128  return false;
2129  }
2130  return false;
2131 }
2132 
2133 // This returns true in two cases:
2134 // - The OP code itself indicates that this is an extended instruction.
2135 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2137  // First check if this is permanently extended op code.
2138  const uint64_t F = MI.getDesc().TSFlags;
2140  return true;
2141  // Use MO operand flags to determine if one of MI's operands
2142  // has HMOTF_ConstExtended flag set.
2143  for (const MachineOperand &MO : MI.operands())
2144  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2145  return true;
2146  return false;
2147 }
2148 
2150  unsigned Opcode = MI.getOpcode();
2151  const uint64_t F = get(Opcode).TSFlags;
2152  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2153 }
2154 
2155 // No V60 HVX VMEM with A_INDIRECT.
2157  const MachineInstr &J) const {
2158  if (!isHVXVec(I))
2159  return false;
2160  if (!I.mayLoad() && !I.mayStore())
2161  return false;
2162  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2163 }
2164 
2166  switch (MI.getOpcode()) {
2167  case Hexagon::J2_callr:
2168  case Hexagon::J2_callrf:
2169  case Hexagon::J2_callrt:
2170  case Hexagon::PS_call_nr:
2171  return true;
2172  }
2173  return false;
2174 }
2175 
2177  switch (MI.getOpcode()) {
2178  case Hexagon::L4_return:
2179  case Hexagon::L4_return_t:
2180  case Hexagon::L4_return_f:
2181  case Hexagon::L4_return_fnew_pnt:
2182  case Hexagon::L4_return_fnew_pt:
2183  case Hexagon::L4_return_tnew_pnt:
2184  case Hexagon::L4_return_tnew_pt:
2185  return true;
2186  }
2187  return false;
2188 }
2189 
2191  switch (MI.getOpcode()) {
2192  case Hexagon::J2_jumpr:
2193  case Hexagon::J2_jumprt:
2194  case Hexagon::J2_jumprf:
2195  case Hexagon::J2_jumprtnewpt:
2196  case Hexagon::J2_jumprfnewpt:
2197  case Hexagon::J2_jumprtnew:
2198  case Hexagon::J2_jumprfnew:
2199  return true;
2200  }
2201  return false;
2202 }
2203 
2204 // Return true if a given MI can accommodate given offset.
2205 // Use abs estimate as oppose to the exact number.
2206 // TODO: This will need to be changed to use MC level
2207 // definition of instruction extendable field size.
2209  unsigned offset) const {
2210  // This selection of jump instructions matches to that what
2211  // analyzeBranch can parse, plus NVJ.
2212  if (isNewValueJump(MI)) // r9:2
2213  return isInt<11>(offset);
2214 
2215  switch (MI.getOpcode()) {
2216  // Still missing Jump to address condition on register value.
2217  default:
2218  return false;
2219  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2220  case Hexagon::J2_call:
2221  case Hexagon::PS_call_nr:
2222  return isInt<24>(offset);
2223  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2224  case Hexagon::J2_jumpf:
2225  case Hexagon::J2_jumptnew:
2226  case Hexagon::J2_jumptnewpt:
2227  case Hexagon::J2_jumpfnew:
2228  case Hexagon::J2_jumpfnewpt:
2229  case Hexagon::J2_callt:
2230  case Hexagon::J2_callf:
2231  return isInt<17>(offset);
2232  case Hexagon::J2_loop0i:
2233  case Hexagon::J2_loop0iext:
2234  case Hexagon::J2_loop0r:
2235  case Hexagon::J2_loop0rext:
2236  case Hexagon::J2_loop1i:
2237  case Hexagon::J2_loop1iext:
2238  case Hexagon::J2_loop1r:
2239  case Hexagon::J2_loop1rext:
2240  return isInt<9>(offset);
2241  // TODO: Add all the compound branches here. Can we do this in Relation model?
2242  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2243  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2244  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2245  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2246  return isInt<11>(offset);
2247  }
2248 }
2249 
2251  const MachineInstr &ESMI) const {
2252  bool isLate = isLateResultInstr(LRMI);
2253  bool isEarly = isEarlySourceInstr(ESMI);
2254 
2255  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2256  LLVM_DEBUG(LRMI.dump());
2257  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2258  LLVM_DEBUG(ESMI.dump());
2259 
2260  if (isLate && isEarly) {
2261  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2262  return true;
2263  }
2264 
2265  return false;
2266 }
2267 
2269  switch (MI.getOpcode()) {
2270  case TargetOpcode::EXTRACT_SUBREG:
2271  case TargetOpcode::INSERT_SUBREG:
2272  case TargetOpcode::SUBREG_TO_REG:
2273  case TargetOpcode::REG_SEQUENCE:
2274  case TargetOpcode::IMPLICIT_DEF:
2275  case TargetOpcode::COPY:
2277  case TargetOpcode::PHI:
2278  return false;
2279  default:
2280  break;
2281  }
2282 
2283  unsigned SchedClass = MI.getDesc().getSchedClass();
2284  return !is_TC1(SchedClass);
2285 }
2286 
2288  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2289  // resource, but all operands can be received late like an ALU instruction.
2290  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2291 }
2292 
2294  unsigned Opcode = MI.getOpcode();
2295  return Opcode == Hexagon::J2_loop0i ||
2296  Opcode == Hexagon::J2_loop0r ||
2297  Opcode == Hexagon::J2_loop0iext ||
2298  Opcode == Hexagon::J2_loop0rext ||
2299  Opcode == Hexagon::J2_loop1i ||
2300  Opcode == Hexagon::J2_loop1r ||
2301  Opcode == Hexagon::J2_loop1iext ||
2302  Opcode == Hexagon::J2_loop1rext;
2303 }
2304 
2306  switch (MI.getOpcode()) {
2307  default: return false;
2308  case Hexagon::L4_iadd_memopw_io:
2309  case Hexagon::L4_isub_memopw_io:
2310  case Hexagon::L4_add_memopw_io:
2311  case Hexagon::L4_sub_memopw_io:
2312  case Hexagon::L4_and_memopw_io:
2313  case Hexagon::L4_or_memopw_io:
2314  case Hexagon::L4_iadd_memoph_io:
2315  case Hexagon::L4_isub_memoph_io:
2316  case Hexagon::L4_add_memoph_io:
2317  case Hexagon::L4_sub_memoph_io:
2318  case Hexagon::L4_and_memoph_io:
2319  case Hexagon::L4_or_memoph_io:
2320  case Hexagon::L4_iadd_memopb_io:
2321  case Hexagon::L4_isub_memopb_io:
2322  case Hexagon::L4_add_memopb_io:
2323  case Hexagon::L4_sub_memopb_io:
2324  case Hexagon::L4_and_memopb_io:
2325  case Hexagon::L4_or_memopb_io:
2326  case Hexagon::L4_ior_memopb_io:
2327  case Hexagon::L4_ior_memoph_io:
2328  case Hexagon::L4_ior_memopw_io:
2329  case Hexagon::L4_iand_memopb_io:
2330  case Hexagon::L4_iand_memoph_io:
2331  case Hexagon::L4_iand_memopw_io:
2332  return true;
2333  }
2334  return false;
2335 }
2336 
2338  const uint64_t F = MI.getDesc().TSFlags;
2340 }
2341 
2342 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2343  const uint64_t F = get(Opcode).TSFlags;
2345 }
2346 
2348  return isNewValueJump(MI) || isNewValueStore(MI);
2349 }
2350 
2352  return isNewValue(MI) && MI.isBranch();
2353 }
2354 
2355 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2356  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2357 }
2358 
2360  const uint64_t F = MI.getDesc().TSFlags;
2362 }
2363 
2364 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2365  const uint64_t F = get(Opcode).TSFlags;
2367 }
2368 
2369 // Returns true if a particular operand is extendable for an instruction.
2371  unsigned OperandNum) const {
2372  const uint64_t F = MI.getDesc().TSFlags;
2374  == OperandNum;
2375 }
2376 
2378  const uint64_t F = MI.getDesc().TSFlags;
2379  assert(isPredicated(MI));
2381 }
2382 
2383 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2384  const uint64_t F = get(Opcode).TSFlags;
2385  assert(isPredicated(Opcode));
2387 }
2388 
2390  const uint64_t F = MI.getDesc().TSFlags;
2391  return !((F >> HexagonII::PredicatedFalsePos) &
2393 }
2394 
2395 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2396  const uint64_t F = get(Opcode).TSFlags;
2397  // Make sure that the instruction is predicated.
2399  return !((F >> HexagonII::PredicatedFalsePos) &
2401 }
2402 
2403 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2404  const uint64_t F = get(Opcode).TSFlags;
2406 }
2407 
2408 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2409  const uint64_t F = get(Opcode).TSFlags;
2411 }
2412 
2413 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2414  const uint64_t F = get(Opcode).TSFlags;
2415  assert(get(Opcode).isBranch() &&
2416  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2417  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2418 }
2419 
2421  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2422  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2423  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2424  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2425 }
2426 
2428  switch (MI.getOpcode()) {
2429  // Byte
2430  case Hexagon::L2_loadrb_io:
2431  case Hexagon::L4_loadrb_ur:
2432  case Hexagon::L4_loadrb_ap:
2433  case Hexagon::L2_loadrb_pr:
2434  case Hexagon::L2_loadrb_pbr:
2435  case Hexagon::L2_loadrb_pi:
2436  case Hexagon::L2_loadrb_pci:
2437  case Hexagon::L2_loadrb_pcr:
2438  case Hexagon::L2_loadbsw2_io:
2439  case Hexagon::L4_loadbsw2_ur:
2440  case Hexagon::L4_loadbsw2_ap:
2441  case Hexagon::L2_loadbsw2_pr:
2442  case Hexagon::L2_loadbsw2_pbr:
2443  case Hexagon::L2_loadbsw2_pi:
2444  case Hexagon::L2_loadbsw2_pci:
2445  case Hexagon::L2_loadbsw2_pcr:
2446  case Hexagon::L2_loadbsw4_io:
2447  case Hexagon::L4_loadbsw4_ur:
2448  case Hexagon::L4_loadbsw4_ap:
2449  case Hexagon::L2_loadbsw4_pr:
2450  case Hexagon::L2_loadbsw4_pbr:
2451  case Hexagon::L2_loadbsw4_pi:
2452  case Hexagon::L2_loadbsw4_pci:
2453  case Hexagon::L2_loadbsw4_pcr:
2454  case Hexagon::L4_loadrb_rr:
2455  case Hexagon::L2_ploadrbt_io:
2456  case Hexagon::L2_ploadrbt_pi:
2457  case Hexagon::L2_ploadrbf_io:
2458  case Hexagon::L2_ploadrbf_pi:
2459  case Hexagon::L2_ploadrbtnew_io:
2460  case Hexagon::L2_ploadrbfnew_io:
2461  case Hexagon::L4_ploadrbt_rr:
2462  case Hexagon::L4_ploadrbf_rr:
2463  case Hexagon::L4_ploadrbtnew_rr:
2464  case Hexagon::L4_ploadrbfnew_rr:
2465  case Hexagon::L2_ploadrbtnew_pi:
2466  case Hexagon::L2_ploadrbfnew_pi:
2467  case Hexagon::L4_ploadrbt_abs:
2468  case Hexagon::L4_ploadrbf_abs:
2469  case Hexagon::L4_ploadrbtnew_abs:
2470  case Hexagon::L4_ploadrbfnew_abs:
2471  case Hexagon::L2_loadrbgp:
2472  // Half
2473  case Hexagon::L2_loadrh_io:
2474  case Hexagon::L4_loadrh_ur:
2475  case Hexagon::L4_loadrh_ap:
2476  case Hexagon::L2_loadrh_pr:
2477  case Hexagon::L2_loadrh_pbr:
2478  case Hexagon::L2_loadrh_pi:
2479  case Hexagon::L2_loadrh_pci:
2480  case Hexagon::L2_loadrh_pcr:
2481  case Hexagon::L4_loadrh_rr:
2482  case Hexagon::L2_ploadrht_io:
2483  case Hexagon::L2_ploadrht_pi:
2484  case Hexagon::L2_ploadrhf_io:
2485  case Hexagon::L2_ploadrhf_pi:
2486  case Hexagon::L2_ploadrhtnew_io:
2487  case Hexagon::L2_ploadrhfnew_io:
2488  case Hexagon::L4_ploadrht_rr:
2489  case Hexagon::L4_ploadrhf_rr:
2490  case Hexagon::L4_ploadrhtnew_rr:
2491  case Hexagon::L4_ploadrhfnew_rr:
2492  case Hexagon::L2_ploadrhtnew_pi:
2493  case Hexagon::L2_ploadrhfnew_pi:
2494  case Hexagon::L4_ploadrht_abs:
2495  case Hexagon::L4_ploadrhf_abs:
2496  case Hexagon::L4_ploadrhtnew_abs:
2497  case Hexagon::L4_ploadrhfnew_abs:
2498  case Hexagon::L2_loadrhgp:
2499  return true;
2500  default:
2501  return false;
2502  }
2503 }
2504 
2506  const uint64_t F = MI.getDesc().TSFlags;
2507  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2508 }
2509 
2511  switch (MI.getOpcode()) {
2512  case Hexagon::STriw_pred:
2513  case Hexagon::LDriw_pred:
2514  return true;
2515  default:
2516  return false;
2517  }
2518 }
2519 
2521  if (!MI.isBranch())
2522  return false;
2523 
2524  for (auto &Op : MI.operands())
2525  if (Op.isGlobal() || Op.isSymbol())
2526  return true;
2527  return false;
2528 }
2529 
2530 // Returns true when SU has a timing class TC1.
2532  unsigned SchedClass = MI.getDesc().getSchedClass();
2533  return is_TC1(SchedClass);
2534 }
2535 
2537  unsigned SchedClass = MI.getDesc().getSchedClass();
2538  return is_TC2(SchedClass);
2539 }
2540 
2542  unsigned SchedClass = MI.getDesc().getSchedClass();
2543  return is_TC2early(SchedClass);
2544 }
2545 
2547  unsigned SchedClass = MI.getDesc().getSchedClass();
2548  return is_TC4x(SchedClass);
2549 }
2550 
2551 // Schedule this ASAP.
2553  const MachineInstr &MI2) const {
2554  if (mayBeCurLoad(MI1)) {
2555  // if (result of SU is used in Next) return true;
2556  unsigned DstReg = MI1.getOperand(0).getReg();
2557  int N = MI2.getNumOperands();
2558  for (int I = 0; I < N; I++)
2559  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2560  return true;
2561  }
2562  if (mayBeNewStore(MI2))
2563  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2564  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2565  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2566  return true;
2567  return false;
2568 }
2569 
2571  const uint64_t V = getType(MI);
2573 }
2574 
2575 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2577  int Size = VT.getSizeInBits() / 8;
2578  if (Offset % Size != 0)
2579  return false;
2580  int Count = Offset / Size;
2581 
2582  switch (VT.getSimpleVT().SimpleTy) {
2583  // For scalars the auto-inc is s4
2584  case MVT::i8:
2585  case MVT::i16:
2586  case MVT::i32:
2587  case MVT::i64:
2588  case MVT::f32:
2589  case MVT::f64:
2590  case MVT::v2i16:
2591  case MVT::v2i32:
2592  case MVT::v4i8:
2593  case MVT::v4i16:
2594  case MVT::v8i8:
2595  return isInt<4>(Count);
2596  // For HVX vectors the auto-inc is s3
2597  case MVT::v64i8:
2598  case MVT::v32i16:
2599  case MVT::v16i32:
2600  case MVT::v8i64:
2601  case MVT::v128i8:
2602  case MVT::v64i16:
2603  case MVT::v32i32:
2604  case MVT::v16i64:
2605  return isInt<3>(Count);
2606  default:
2607  break;
2608  }
2609 
2610  llvm_unreachable("Not an valid type!");
2611 }
2612 
2613 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2614  const TargetRegisterInfo *TRI, bool Extend) const {
2615  // This function is to check whether the "Offset" is in the correct range of
2616  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2617  // inserted to calculate the final address. Due to this reason, the function
2618  // assumes that the "Offset" has correct alignment.
2619  // We used to assert if the offset was not properly aligned, however,
2620  // there are cases where a misaligned pointer recast can cause this
2621  // problem, and we need to allow for it. The front end warns of such
2622  // misaligns with respect to load size.
2623  switch (Opcode) {
2624  case Hexagon::PS_vstorerq_ai:
2625  case Hexagon::PS_vstorerw_ai:
2626  case Hexagon::PS_vstorerw_nt_ai:
2627  case Hexagon::PS_vloadrq_ai:
2628  case Hexagon::PS_vloadrw_ai:
2629  case Hexagon::PS_vloadrw_nt_ai:
2630  case Hexagon::V6_vL32b_ai:
2631  case Hexagon::V6_vS32b_ai:
2632  case Hexagon::V6_vL32b_nt_ai:
2633  case Hexagon::V6_vS32b_nt_ai:
2634  case Hexagon::V6_vL32Ub_ai:
2635  case Hexagon::V6_vS32Ub_ai: {
2636  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2637  assert(isPowerOf2_32(VectorSize));
2638  if (Offset & (VectorSize-1))
2639  return false;
2640  return isInt<4>(Offset >> Log2_32(VectorSize));
2641  }
2642 
2643  case Hexagon::J2_loop0i:
2644  case Hexagon::J2_loop1i:
2645  return isUInt<10>(Offset);
2646 
2647  case Hexagon::S4_storeirb_io:
2648  case Hexagon::S4_storeirbt_io:
2649  case Hexagon::S4_storeirbf_io:
2650  return isUInt<6>(Offset);
2651 
2652  case Hexagon::S4_storeirh_io:
2653  case Hexagon::S4_storeirht_io:
2654  case Hexagon::S4_storeirhf_io:
2655  return isShiftedUInt<6,1>(Offset);
2656 
2657  case Hexagon::S4_storeiri_io:
2658  case Hexagon::S4_storeirit_io:
2659  case Hexagon::S4_storeirif_io:
2660  return isShiftedUInt<6,2>(Offset);
2661  }
2662 
2663  if (Extend)
2664  return true;
2665 
2666  switch (Opcode) {
2667  case Hexagon::L2_loadri_io:
2668  case Hexagon::S2_storeri_io:
2669  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2670  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2671 
2672  case Hexagon::L2_loadrd_io:
2673  case Hexagon::S2_storerd_io:
2674  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2675  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2676 
2677  case Hexagon::L2_loadrh_io:
2678  case Hexagon::L2_loadruh_io:
2679  case Hexagon::S2_storerh_io:
2680  case Hexagon::S2_storerf_io:
2681  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2682  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2683 
2684  case Hexagon::L2_loadrb_io:
2685  case Hexagon::L2_loadrub_io:
2686  case Hexagon::S2_storerb_io:
2687  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2688  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2689 
2690  case Hexagon::A2_addi:
2691  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2692  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2693 
2694  case Hexagon::L4_iadd_memopw_io:
2695  case Hexagon::L4_isub_memopw_io:
2696  case Hexagon::L4_add_memopw_io:
2697  case Hexagon::L4_sub_memopw_io:
2698  case Hexagon::L4_and_memopw_io:
2699  case Hexagon::L4_or_memopw_io:
2700  return (0 <= Offset && Offset <= 255);
2701 
2702  case Hexagon::L4_iadd_memoph_io:
2703  case Hexagon::L4_isub_memoph_io:
2704  case Hexagon::L4_add_memoph_io:
2705  case Hexagon::L4_sub_memoph_io:
2706  case Hexagon::L4_and_memoph_io:
2707  case Hexagon::L4_or_memoph_io:
2708  return (0 <= Offset && Offset <= 127);
2709 
2710  case Hexagon::L4_iadd_memopb_io:
2711  case Hexagon::L4_isub_memopb_io:
2712  case Hexagon::L4_add_memopb_io:
2713  case Hexagon::L4_sub_memopb_io:
2714  case Hexagon::L4_and_memopb_io:
2715  case Hexagon::L4_or_memopb_io:
2716  return (0 <= Offset && Offset <= 63);
2717 
2718  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2719  // any size. Later pass knows how to handle it.
2720  case Hexagon::STriw_pred:
2721  case Hexagon::LDriw_pred:
2722  case Hexagon::STriw_ctr:
2723  case Hexagon::LDriw_ctr:
2724  return true;
2725 
2726  case Hexagon::PS_fi:
2727  case Hexagon::PS_fia:
2728  case Hexagon::INLINEASM:
2729  return true;
2730 
2731  case Hexagon::L2_ploadrbt_io:
2732  case Hexagon::L2_ploadrbf_io:
2733  case Hexagon::L2_ploadrubt_io:
2734  case Hexagon::L2_ploadrubf_io:
2735  case Hexagon::S2_pstorerbt_io:
2736  case Hexagon::S2_pstorerbf_io:
2737  return isUInt<6>(Offset);
2738 
2739  case Hexagon::L2_ploadrht_io:
2740  case Hexagon::L2_ploadrhf_io:
2741  case Hexagon::L2_ploadruht_io:
2742  case Hexagon::L2_ploadruhf_io:
2743  case Hexagon::S2_pstorerht_io:
2744  case Hexagon::S2_pstorerhf_io:
2745  return isShiftedUInt<6,1>(Offset);
2746 
2747  case Hexagon::L2_ploadrit_io:
2748  case Hexagon::L2_ploadrif_io:
2749  case Hexagon::S2_pstorerit_io:
2750  case Hexagon::S2_pstorerif_io:
2751  return isShiftedUInt<6,2>(Offset);
2752 
2753  case Hexagon::L2_ploadrdt_io:
2754  case Hexagon::L2_ploadrdf_io:
2755  case Hexagon::S2_pstorerdt_io:
2756  case Hexagon::S2_pstorerdf_io:
2757  return isShiftedUInt<6,3>(Offset);
2758  } // switch
2759 
2760  llvm_unreachable("No offset range is defined for this opcode. "
2761  "Please define it in the above switch statement!");
2762 }
2763 
2765  return isHVXVec(MI) && isAccumulator(MI);
2766 }
2767 
2769  const uint64_t F = get(MI.getOpcode()).TSFlags;
2770  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2771  return
2772  V == HexagonII::TypeCVI_VA ||
2774 }
2775 
2777  const MachineInstr &ConsMI) const {
2778  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2779  return true;
2780 
2781  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2782  return true;
2783 
2784  if (mayBeNewStore(ConsMI))
2785  return true;
2786 
2787  return false;
2788 }
2789 
2791  switch (MI.getOpcode()) {
2792  // Byte
2793  case Hexagon::L2_loadrub_io:
2794  case Hexagon::L4_loadrub_ur:
2795  case Hexagon::L4_loadrub_ap:
2796  case Hexagon::L2_loadrub_pr:
2797  case Hexagon::L2_loadrub_pbr:
2798  case Hexagon::L2_loadrub_pi:
2799  case Hexagon::L2_loadrub_pci:
2800  case Hexagon::L2_loadrub_pcr:
2801  case Hexagon::L2_loadbzw2_io:
2802  case Hexagon::L4_loadbzw2_ur:
2803  case Hexagon::L4_loadbzw2_ap:
2804  case Hexagon::L2_loadbzw2_pr:
2805  case Hexagon::L2_loadbzw2_pbr:
2806  case Hexagon::L2_loadbzw2_pi:
2807  case Hexagon::L2_loadbzw2_pci:
2808  case Hexagon::L2_loadbzw2_pcr:
2809  case Hexagon::L2_loadbzw4_io:
2810  case Hexagon::L4_loadbzw4_ur:
2811  case Hexagon::L4_loadbzw4_ap:
2812  case Hexagon::L2_loadbzw4_pr:
2813  case Hexagon::L2_loadbzw4_pbr:
2814  case Hexagon::L2_loadbzw4_pi:
2815  case Hexagon::L2_loadbzw4_pci:
2816  case Hexagon::L2_loadbzw4_pcr:
2817  case Hexagon::L4_loadrub_rr:
2818  case Hexagon::L2_ploadrubt_io:
2819  case Hexagon::L2_ploadrubt_pi:
2820  case Hexagon::L2_ploadrubf_io:
2821  case Hexagon::L2_ploadrubf_pi:
2822  case Hexagon::L2_ploadrubtnew_io:
2823  case Hexagon::L2_ploadrubfnew_io:
2824  case Hexagon::L4_ploadrubt_rr:
2825  case Hexagon::L4_ploadrubf_rr:
2826  case Hexagon::L4_ploadrubtnew_rr:
2827  case Hexagon::L4_ploadrubfnew_rr:
2828  case Hexagon::L2_ploadrubtnew_pi:
2829  case Hexagon::L2_ploadrubfnew_pi:
2830  case Hexagon::L4_ploadrubt_abs:
2831  case Hexagon::L4_ploadrubf_abs:
2832  case Hexagon::L4_ploadrubtnew_abs:
2833  case Hexagon::L4_ploadrubfnew_abs:
2834  case Hexagon::L2_loadrubgp:
2835  // Half
2836  case Hexagon::L2_loadruh_io:
2837  case Hexagon::L4_loadruh_ur:
2838  case Hexagon::L4_loadruh_ap:
2839  case Hexagon::L2_loadruh_pr:
2840  case Hexagon::L2_loadruh_pbr:
2841  case Hexagon::L2_loadruh_pi:
2842  case Hexagon::L2_loadruh_pci:
2843  case Hexagon::L2_loadruh_pcr:
2844  case Hexagon::L4_loadruh_rr:
2845  case Hexagon::L2_ploadruht_io:
2846  case Hexagon::L2_ploadruht_pi:
2847  case Hexagon::L2_ploadruhf_io:
2848  case Hexagon::L2_ploadruhf_pi:
2849  case Hexagon::L2_ploadruhtnew_io:
2850  case Hexagon::L2_ploadruhfnew_io:
2851  case Hexagon::L4_ploadruht_rr:
2852  case Hexagon::L4_ploadruhf_rr:
2853  case Hexagon::L4_ploadruhtnew_rr:
2854  case Hexagon::L4_ploadruhfnew_rr:
2855  case Hexagon::L2_ploadruhtnew_pi:
2856  case Hexagon::L2_ploadruhfnew_pi:
2857  case Hexagon::L4_ploadruht_abs:
2858  case Hexagon::L4_ploadruhf_abs:
2859  case Hexagon::L4_ploadruhtnew_abs:
2860  case Hexagon::L4_ploadruhfnew_abs:
2861  case Hexagon::L2_loadruhgp:
2862  return true;
2863  default:
2864  return false;
2865  }
2866 }
2867 
2868 // Add latency to instruction.
2870  const MachineInstr &MI2) const {
2871  if (isHVXVec(MI1) && isHVXVec(MI2))
2872  if (!isVecUsableNextPacket(MI1, MI2))
2873  return true;
2874  return false;
2875 }
2876 
2877 /// Get the base register and byte offset of a load/store instr.
2879  unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2880  const {
2881  unsigned AccessSize = 0;
2882  int OffsetVal = 0;
2883  BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2884  Offset = OffsetVal;
2885  return BaseReg != 0;
2886 }
2887 
2888 /// Can these instructions execute at the same time in a bundle.
2890  const MachineInstr &Second) const {
2891  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2892  const MachineOperand &Op = Second.getOperand(0);
2893  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2894  return true;
2895  }
2896  if (DisableNVSchedule)
2897  return false;
2898  if (mayBeNewStore(Second)) {
2899  // Make sure the definition of the first instruction is the value being
2900  // stored.
2901  const MachineOperand &Stored =
2902  Second.getOperand(Second.getNumOperands() - 1);
2903  if (!Stored.isReg())
2904  return false;
2905  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2906  const MachineOperand &Op = First.getOperand(i);
2907  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2908  return true;
2909  }
2910  }
2911  return false;
2912 }
2913 
2915  unsigned Opc = CallMI.getOpcode();
2916  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2917 }
2918 
2920  for (auto &I : *B)
2921  if (I.isEHLabel())
2922  return true;
2923  return false;
2924 }
2925 
2926 // Returns true if an instruction can be converted into a non-extended
2927 // equivalent instruction.
2929  short NonExtOpcode;
2930  // Check if the instruction has a register form that uses register in place
2931  // of the extended operand, if so return that as the non-extended form.
2932  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2933  return true;
2934 
2935  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2936  // Check addressing mode and retrieve non-ext equivalent instruction.
2937 
2938  switch (getAddrMode(MI)) {
2939  case HexagonII::Absolute:
2940  // Load/store with absolute addressing mode can be converted into
2941  // base+offset mode.
2942  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2943  break;
2945  // Load/store with base+offset addressing mode can be converted into
2946  // base+register offset addressing mode. However left shift operand should
2947  // be set to 0.
2948  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
2949  break;
2951  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
2952  break;
2953  default:
2954  return false;
2955  }
2956  if (NonExtOpcode < 0)
2957  return false;
2958  return true;
2959  }
2960  return false;
2961 }
2962 
2964  return Hexagon::getRealHWInstr(MI.getOpcode(),
2965  Hexagon::InstrType_Pseudo) >= 0;
2966 }
2967 
2969  const {
2971  while (I != E) {
2972  if (I->isBarrier())
2973  return true;
2974  ++I;
2975  }
2976  return false;
2977 }
2978 
2979 // Returns true, if a LD insn can be promoted to a cur load.
2981  const uint64_t F = MI.getDesc().TSFlags;
2983  Subtarget.hasV60TOps();
2984 }
2985 
2986 // Returns true, if a ST insn can be promoted to a new-value store.
2988  if (MI.mayStore() && !Subtarget.useNewValueStores())
2989  return false;
2990 
2991  const uint64_t F = MI.getDesc().TSFlags;
2993 }
2994 
2996  const MachineInstr &ConsMI) const {
2997  // There is no stall when ProdMI is not a V60 vector.
2998  if (!isHVXVec(ProdMI))
2999  return false;
3000 
3001  // There is no stall when ProdMI and ConsMI are not dependent.
3002  if (!isDependent(ProdMI, ConsMI))
3003  return false;
3004 
3005  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3006  // are scheduled in consecutive packets.
3007  if (isVecUsableNextPacket(ProdMI, ConsMI))
3008  return false;
3009 
3010  return true;
3011 }
3012 
3015  // There is no stall when I is not a V60 vector.
3016  if (!isHVXVec(MI))
3017  return false;
3018 
3020  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3021 
3022  if (!MII->isBundle())
3023  return producesStall(*MII, MI);
3024 
3025  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3026  const MachineInstr &J = *MII;
3027  if (producesStall(J, MI))
3028  return true;
3029  }
3030  return false;
3031 }
3032 
3034  unsigned PredReg) const {
3035  for (const MachineOperand &MO : MI.operands()) {
3036  // Predicate register must be explicitly defined.
3037  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3038  return false;
3039  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3040  return false;
3041  }
3042 
3043  // Hexagon Programmer's Reference says that decbin, memw_locked, and
3044  // memd_locked cannot be used as .new as well,
3045  // but we don't seem to have these instructions defined.
3046  return MI.getOpcode() != Hexagon::A4_tlbmatch;
3047 }
3048 
3049 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3050  return Opcode == Hexagon::J2_jumpt ||
3051  Opcode == Hexagon::J2_jumptpt ||
3052  Opcode == Hexagon::J2_jumpf ||
3053  Opcode == Hexagon::J2_jumpfpt ||
3054  Opcode == Hexagon::J2_jumptnew ||
3055  Opcode == Hexagon::J2_jumpfnew ||
3056  Opcode == Hexagon::J2_jumptnewpt ||
3057  Opcode == Hexagon::J2_jumpfnewpt;
3058 }
3059 
3061  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3062  return false;
3063  return !isPredicatedTrue(Cond[0].getImm());
3064 }
3065 
3067  const uint64_t F = MI.getDesc().TSFlags;
3069 }
3070 
3071 // Returns the base register in a memory access (load/store). The offset is
3072 // returned in Offset and the access size is returned in AccessSize.
3073 // If the base register has a subregister or the offset field does not contain
3074 // an immediate value, return 0.
3076  int &Offset, unsigned &AccessSize) const {
3077  // Return if it is not a base+offset type instruction or a MemOp.
3080  !isMemOp(MI) && !isPostIncrement(MI))
3081  return 0;
3082 
3083  AccessSize = getMemAccessSize(MI);
3084 
3085  unsigned BasePos = 0, OffsetPos = 0;
3086  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3087  return 0;
3088 
3089  // Post increment updates its EA after the mem access,
3090  // so we need to treat its offset as zero.
3091  if (isPostIncrement(MI)) {
3092  Offset = 0;
3093  } else {
3094  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3095  if (!OffsetOp.isImm())
3096  return 0;
3097  Offset = OffsetOp.getImm();
3098  }
3099 
3100  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3101  if (BaseOp.getSubReg() != 0)
3102  return 0;
3103  return BaseOp.getReg();
3104 }
3105 
3106 /// Return the position of the base and offset operands for this instruction.
3108  unsigned &BasePos, unsigned &OffsetPos) const {
3109  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3110  return false;
3111 
3112  // Deal with memops first.
3113  if (isMemOp(MI)) {
3114  BasePos = 0;
3115  OffsetPos = 1;
3116  } else if (MI.mayStore()) {
3117  BasePos = 0;
3118  OffsetPos = 1;
3119  } else if (MI.mayLoad()) {
3120  BasePos = 1;
3121  OffsetPos = 2;
3122  } else
3123  return false;
3124 
3125  if (isPredicated(MI)) {
3126  BasePos++;
3127  OffsetPos++;
3128  }
3129  if (isPostIncrement(MI)) {
3130  BasePos++;
3131  OffsetPos++;
3132  }
3133 
3134  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3135  return false;
3136 
3137  return true;
3138 }
3139 
3140 // Inserts branching instructions in reverse order of their occurrence.
3141 // e.g. jump_t t1 (i1)
3142 // jump t2 (i2)
3143 // Jumpers = {i2, i1}
3145  MachineBasicBlock& MBB) const {
3147  // If the block has no terminators, it just falls into the block after it.
3149  if (I == MBB.instr_begin())
3150  return Jumpers;
3151 
3152  // A basic block may looks like this:
3153  //
3154  // [ insn
3155  // EH_LABEL
3156  // insn
3157  // insn
3158  // insn
3159  // EH_LABEL
3160  // insn ]
3161  //
3162  // It has two succs but does not have a terminator
3163  // Don't know how to handle it.
3164  do {
3165  --I;
3166  if (I->isEHLabel())
3167  return Jumpers;
3168  } while (I != MBB.instr_begin());
3169 
3170  I = MBB.instr_end();
3171  --I;
3172 
3173  while (I->isDebugInstr()) {
3174  if (I == MBB.instr_begin())
3175  return Jumpers;
3176  --I;
3177  }
3178  if (!isUnpredicatedTerminator(*I))
3179  return Jumpers;
3180 
3181  // Get the last instruction in the block.
3182  MachineInstr *LastInst = &*I;
3183  Jumpers.push_back(LastInst);
3184  MachineInstr *SecondLastInst = nullptr;
3185  // Find one more terminator if present.
3186  do {
3187  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3188  if (!SecondLastInst) {
3189  SecondLastInst = &*I;
3190  Jumpers.push_back(SecondLastInst);
3191  } else // This is a third branch.
3192  return Jumpers;
3193  }
3194  if (I == MBB.instr_begin())
3195  break;
3196  --I;
3197  } while (true);
3198  return Jumpers;
3199 }
3200 
3201 // Returns Operand Index for the constant extended instruction.
3203  const uint64_t F = MI.getDesc().TSFlags;
3205 }
3206 
3207 // See if instruction could potentially be a duplex candidate.
3208 // If so, return its group. Zero otherwise.
3210  const MachineInstr &MI) const {
3211  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3212 
3213  switch (MI.getOpcode()) {
3214  default:
3215  return HexagonII::HCG_None;
3216  //
3217  // Compound pairs.
3218  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3219  // "Rd16=#U6 ; jump #r9:2"
3220  // "Rd16=Rs16 ; jump #r9:2"
3221  //
3222  case Hexagon::C2_cmpeq:
3223  case Hexagon::C2_cmpgt:
3224  case Hexagon::C2_cmpgtu:
3225  DstReg = MI.getOperand(0).getReg();
3226  Src1Reg = MI.getOperand(1).getReg();
3227  Src2Reg = MI.getOperand(2).getReg();
3228  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3229  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3230  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3231  return HexagonII::HCG_A;
3232  break;
3233  case Hexagon::C2_cmpeqi:
3234  case Hexagon::C2_cmpgti:
3235  case Hexagon::C2_cmpgtui:
3236  // P0 = cmp.eq(Rs,#u2)
3237  DstReg = MI.getOperand(0).getReg();
3238  SrcReg = MI.getOperand(1).getReg();
3239  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3240  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3241  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3242  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3243  (MI.getOperand(2).getImm() == -1)))
3244  return HexagonII::HCG_A;
3245  break;
3246  case Hexagon::A2_tfr:
3247  // Rd = Rs
3248  DstReg = MI.getOperand(0).getReg();
3249  SrcReg = MI.getOperand(1).getReg();
3250  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3251  return HexagonII::HCG_A;
3252  break;
3253  case Hexagon::A2_tfrsi:
3254  // Rd = #u6
3255  // Do not test for #u6 size since the const is getting extended
3256  // regardless and compound could be formed.
3257  DstReg = MI.getOperand(0).getReg();
3258  if (isIntRegForSubInst(DstReg))
3259  return HexagonII::HCG_A;
3260  break;
3261  case Hexagon::S2_tstbit_i:
3262  DstReg = MI.getOperand(0).getReg();
3263  Src1Reg = MI.getOperand(1).getReg();
3264  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3265  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3266  MI.getOperand(2).isImm() &&
3267  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3268  return HexagonII::HCG_A;
3269  break;
3270  // The fact that .new form is used pretty much guarantees
3271  // that predicate register will match. Nevertheless,
3272  // there could be some false positives without additional
3273  // checking.
3274  case Hexagon::J2_jumptnew:
3275  case Hexagon::J2_jumpfnew:
3276  case Hexagon::J2_jumptnewpt:
3277  case Hexagon::J2_jumpfnewpt:
3278  Src1Reg = MI.getOperand(0).getReg();
3279  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3280  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3281  return HexagonII::HCG_B;
3282  break;
3283  // Transfer and jump:
3284  // Rd=#U6 ; jump #r9:2
3285  // Rd=Rs ; jump #r9:2
3286  // Do not test for jump range here.
3287  case Hexagon::J2_jump:
3288  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3289  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3290  return HexagonII::HCG_C;
3291  }
3292 
3293  return HexagonII::HCG_None;
3294 }
3295 
3296 // Returns -1 when there is no opcode found.
3298  const MachineInstr &GB) const {
3301  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3302  (GB.getOpcode() != Hexagon::J2_jumptnew))
3303  return -1u;
3304  unsigned DestReg = GA.getOperand(0).getReg();
3305  if (!GB.readsRegister(DestReg))
3306  return -1u;
3307  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3308  return -1u;
3309  // The value compared against must be either u5 or -1.
3310  const MachineOperand &CmpOp = GA.getOperand(2);
3311  if (!CmpOp.isImm())
3312  return -1u;
3313  int V = CmpOp.getImm();
3314  if (V == -1)
3315  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3316  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3317  if (!isUInt<5>(V))
3318  return -1u;
3319  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3320  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3321 }
3322 
3323 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3324  enum Hexagon::PredSense inPredSense;
3325  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3326  Hexagon::PredSense_true;
3327  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3328  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3329  return CondOpcode;
3330 
3331  llvm_unreachable("Unexpected predicable instruction");
3332 }
3333 
3334 // Return the cur value instruction for a given store.
3336  switch (MI.getOpcode()) {
3337  default: llvm_unreachable("Unknown .cur type");
3338  case Hexagon::V6_vL32b_pi:
3339  return Hexagon::V6_vL32b_cur_pi;
3340  case Hexagon::V6_vL32b_ai:
3341  return Hexagon::V6_vL32b_cur_ai;
3342  case Hexagon::V6_vL32b_nt_pi:
3343  return Hexagon::V6_vL32b_nt_cur_pi;
3344  case Hexagon::V6_vL32b_nt_ai:
3345  return Hexagon::V6_vL32b_nt_cur_ai;
3346  }
3347  return 0;
3348 }
3349 
3350 // Return the regular version of the .cur instruction.
3352  switch (MI.getOpcode()) {
3353  default: llvm_unreachable("Unknown .cur type");
3354  case Hexagon::V6_vL32b_cur_pi:
3355  return Hexagon::V6_vL32b_pi;
3356  case Hexagon::V6_vL32b_cur_ai:
3357  return Hexagon::V6_vL32b_ai;
3358  case Hexagon::V6_vL32b_nt_cur_pi:
3359  return Hexagon::V6_vL32b_nt_pi;
3360  case Hexagon::V6_vL32b_nt_cur_ai:
3361  return Hexagon::V6_vL32b_nt_ai;
3362  }
3363  return 0;
3364 }
3365 
3366 // The diagram below shows the steps involved in the conversion of a predicated
3367 // store instruction to its .new predicated new-value form.
3368 //
3369 // Note: It doesn't include conditional new-value stores as they can't be
3370 // converted to .new predicate.
3371 //
3372 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3373 // ^ ^
3374 // / \ (not OK. it will cause new-value store to be
3375 // / X conditional on p0.new while R2 producer is
3376 // / \ on p0)
3377 // / \.
3378 // p.new store p.old NV store
3379 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3380 // ^ ^
3381 // \ /
3382 // \ /
3383 // \ /
3384 // p.old store
3385 // [if (p0)memw(R0+#0)=R2]
3386 //
3387 // The following set of instructions further explains the scenario where
3388 // conditional new-value store becomes invalid when promoted to .new predicate
3389 // form.
3390 //
3391 // { 1) if (p0) r0 = add(r1, r2)
3392 // 2) p0 = cmp.eq(r3, #0) }
3393 //
3394 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3395 // the first two instructions because in instr 1, r0 is conditional on old value
3396 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3397 // is not valid for new-value stores.
3398 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3399 // from the "Conditional Store" list. Because a predicated new value store
3400 // would NOT be promoted to a double dot new store. See diagram below:
3401 // This function returns yes for those stores that are predicated but not
3402 // yet promoted to predicate dot new instructions.
3403 //
3404 // +---------------------+
3405 // /-----| if (p0) memw(..)=r0 |---------\~
3406 // || +---------------------+ ||
3407 // promote || /\ /\ || promote
3408 // || /||\ /||\ ||
3409 // \||/ demote || \||/
3410 // \/ || || \/
3411 // +-------------------------+ || +-------------------------+
3412 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3413 // +-------------------------+ || +-------------------------+
3414 // || || ||
3415 // || demote \||/
3416 // promote || \/ NOT possible
3417 // || || /\~
3418 // \||/ || /||\~
3419 // \/ || ||
3420 // +-----------------------------+
3421 // | if (p0.new) memw(..)=r0.new |
3422 // +-----------------------------+
3423 // Double Dot New Store
3424 //
3425 // Returns the most basic instruction for the .new predicated instructions and
3426 // new-value stores.
3427 // For example, all of the following instructions will be converted back to the
3428 // same instruction:
3429 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3430 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3431 // 3) if (p0.new) memw(R0+#0) = R1 --->
3432 //
3433 // To understand the translation of instruction 1 to its original form, consider
3434 // a packet with 3 instructions.
3435 // { p0 = cmp.eq(R0,R1)
3436 // if (p0.new) R2 = add(R3, R4)
3437 // R5 = add (R3, R1)
3438 // }
3439 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3440 //
3441 // This instruction can be part of the previous packet only if both p0 and R2
3442 // are promoted to .new values. This promotion happens in steps, first
3443 // predicate register is promoted to .new and in the next iteration R2 is
3444 // promoted. Therefore, in case of dependence check failure (due to R5) during
3445 // next iteration, it should be converted back to its most basic form.
3446 
3447 // Return the new value instruction for a given store.
3449  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3450  if (NVOpcode >= 0) // Valid new-value store instruction.
3451  return NVOpcode;
3452 
3453  switch (MI.getOpcode()) {
3454  default:
3455  report_fatal_error(std::string("Unknown .new type: ") +
3456  std::to_string(MI.getOpcode()));
3457  case Hexagon::S4_storerb_ur:
3458  return Hexagon::S4_storerbnew_ur;
3459 
3460  case Hexagon::S2_storerb_pci:
3461  return Hexagon::S2_storerb_pci;
3462 
3463  case Hexagon::S2_storeri_pci:
3464  return Hexagon::S2_storeri_pci;
3465 
3466  case Hexagon::S2_storerh_pci:
3467  return Hexagon::S2_storerh_pci;
3468 
3469  case Hexagon::S2_storerd_pci:
3470  return Hexagon::S2_storerd_pci;
3471 
3472  case Hexagon::S2_storerf_pci:
3473  return Hexagon::S2_storerf_pci;
3474 
3475  case Hexagon::V6_vS32b_ai:
3476  return Hexagon::V6_vS32b_new_ai;
3477 
3478  case Hexagon::V6_vS32b_pi:
3479  return Hexagon::V6_vS32b_new_pi;
3480  }
3481  return 0;
3482 }
3483 
3484 // Returns the opcode to use when converting MI, which is a conditional jump,
3485 // into a conditional instruction which uses the .new value of the predicate.
3486 // We also use branch probabilities to add a hint to the jump.
3487 // If MBPI is null, all edges will be treated as equally likely for the
3488 // purposes of establishing a predication hint.
3490  const MachineBranchProbabilityInfo *MBPI) const {
3491  // We assume that block can have at most two successors.
3492  const MachineBasicBlock *Src = MI.getParent();
3493  const MachineOperand &BrTarget = MI.getOperand(1);
3494  bool Taken = false;
3495  const BranchProbability OneHalf(1, 2);
3496 
3497  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3498  const MachineBasicBlock *Dst) {
3499  if (MBPI)
3500  return MBPI->getEdgeProbability(Src, Dst);
3501  return BranchProbability(1, Src->succ_size());
3502  };
3503 
3504  if (BrTarget.isMBB()) {
3505  const MachineBasicBlock *Dst = BrTarget.getMBB();
3506  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3507  } else {
3508  // The branch target is not a basic block (most likely a function).
3509  // Since BPI only gives probabilities for targets that are basic blocks,
3510  // try to identify another target of this branch (potentially a fall-
3511  // -through) and check the probability of that target.
3512  //
3513  // The only handled branch combinations are:
3514  // - one conditional branch,
3515  // - one conditional branch followed by one unconditional branch.
3516  // Otherwise, assume not-taken.
3518  const MachineBasicBlock &B = *MI.getParent();
3519  bool SawCond = false, Bad = false;
3520  for (const MachineInstr &I : B) {
3521  if (!I.isBranch())
3522  continue;
3523  if (I.isConditionalBranch()) {
3524  SawCond = true;
3525  if (&I != &MI) {
3526  Bad = true;
3527  break;
3528  }
3529  }
3530  if (I.isUnconditionalBranch() && !SawCond) {
3531  Bad = true;
3532  break;
3533  }
3534  }
3535  if (!Bad) {
3537  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3538  if (NextIt == B.instr_end()) {
3539  // If this branch is the last, look for the fall-through block.
3540  for (const MachineBasicBlock *SB : B.successors()) {
3541  if (!B.isLayoutSuccessor(SB))
3542  continue;
3543  Taken = getEdgeProbability(Src, SB) < OneHalf;
3544  break;
3545  }
3546  } else {
3547  assert(NextIt->isUnconditionalBranch());
3548  // Find the first MBB operand and assume it's the target.
3549  const MachineBasicBlock *BT = nullptr;
3550  for (const MachineOperand &Op : NextIt->operands()) {
3551  if (!Op.isMBB())
3552  continue;
3553  BT = Op.getMBB();
3554  break;
3555  }
3556  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3557  }
3558  } // if (!Bad)
3559  }
3560 
3561  // The Taken flag should be set to something reasonable by this point.
3562 
3563  switch (MI.getOpcode()) {
3564  case Hexagon::J2_jumpt:
3565  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3566  case Hexagon::J2_jumpf:
3567  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3568 
3569  default:
3570  llvm_unreachable("Unexpected jump instruction.");
3571  }
3572 }
3573 
3574 // Return .new predicate version for an instruction.
3576  const MachineBranchProbabilityInfo *MBPI) const {
3577  switch (MI.getOpcode()) {
3578  // Condtional Jumps
3579  case Hexagon::J2_jumpt:
3580  case Hexagon::J2_jumpf:
3581  return getDotNewPredJumpOp(MI, MBPI);
3582  }
3583 
3584  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3585  if (NewOpcode >= 0)
3586  return NewOpcode;
3587  return 0;
3588 }
3589 
3591  int NewOp = MI.getOpcode();
3592  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3593  NewOp = Hexagon::getPredOldOpcode(NewOp);
3594  // All Hexagon architectures have prediction bits on dot-new branches,
3595  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3596  // to pick the right opcode when converting back to dot-old.
3597  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3598  switch (NewOp) {
3599  case Hexagon::J2_jumptpt:
3600  NewOp = Hexagon::J2_jumpt;
3601  break;
3602  case Hexagon::J2_jumpfpt:
3603  NewOp = Hexagon::J2_jumpf;
3604  break;
3605  case Hexagon::J2_jumprtpt:
3606  NewOp = Hexagon::J2_jumprt;
3607  break;
3608  case Hexagon::J2_jumprfpt:
3609  NewOp = Hexagon::J2_jumprf;
3610  break;
3611  }
3612  }
3613  assert(NewOp >= 0 &&
3614  "Couldn't change predicate new instruction to its old form.");
3615  }
3616 
3617  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3618  NewOp = Hexagon::getNonNVStore(NewOp);
3619  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3620  }
3621 
3622  if (Subtarget.hasV60TOps())
3623  return NewOp;
3624 
3625  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3626  switch (NewOp) {
3627  case Hexagon::J2_jumpfpt:
3628  return Hexagon::J2_jumpf;
3629  case Hexagon::J2_jumptpt:
3630  return Hexagon::J2_jumpt;
3631  case Hexagon::J2_jumprfpt:
3632  return Hexagon::J2_jumprf;
3633  case Hexagon::J2_jumprtpt:
3634  return Hexagon::J2_jumprt;
3635  }
3636  return NewOp;
3637 }
3638 
3639 // See if instruction could potentially be a duplex candidate.
3640 // If so, return its group. Zero otherwise.
3642  const MachineInstr &MI) const {
3643  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3644  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3645 
3646  switch (MI.getOpcode()) {
3647  default:
3648  return HexagonII::HSIG_None;
3649  //
3650  // Group L1:
3651  //
3652  // Rd = memw(Rs+#u4:2)
3653  // Rd = memub(Rs+#u4:0)
3654  case Hexagon::L2_loadri_io:
3655  DstReg = MI.getOperand(0).getReg();
3656  SrcReg = MI.getOperand(1).getReg();
3657  // Special case this one from Group L2.
3658  // Rd = memw(r29+#u5:2)
3659  if (isIntRegForSubInst(DstReg)) {
3660  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3661  HRI.getStackRegister() == SrcReg &&
3662  MI.getOperand(2).isImm() &&
3663  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3664  return HexagonII::HSIG_L2;
3665  // Rd = memw(Rs+#u4:2)
3666  if (isIntRegForSubInst(SrcReg) &&
3667  (MI.getOperand(2).isImm() &&
3668  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3669  return HexagonII::HSIG_L1;
3670  }
3671  break;
3672  case Hexagon::L2_loadrub_io:
3673  // Rd = memub(Rs+#u4:0)
3674  DstReg = MI.getOperand(0).getReg();
3675  SrcReg = MI.getOperand(1).getReg();
3676  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3677  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3678  return HexagonII::HSIG_L1;
3679  break;
3680  //
3681  // Group L2:
3682  //
3683  // Rd = memh/memuh(Rs+#u3:1)
3684  // Rd = memb(Rs+#u3:0)
3685  // Rd = memw(r29+#u5:2) - Handled above.
3686  // Rdd = memd(r29+#u5:3)
3687  // deallocframe
3688  // [if ([!]p0[.new])] dealloc_return
3689  // [if ([!]p0[.new])] jumpr r31
3690  case Hexagon::L2_loadrh_io:
3691  case Hexagon::L2_loadruh_io:
3692  // Rd = memh/memuh(Rs+#u3:1)
3693  DstReg = MI.getOperand(0).getReg();
3694  SrcReg = MI.getOperand(1).getReg();
3695  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3696  MI.getOperand(2).isImm() &&
3697  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3698  return HexagonII::HSIG_L2;
3699  break;
3700  case Hexagon::L2_loadrb_io:
3701  // Rd = memb(Rs+#u3:0)
3702  DstReg = MI.getOperand(0).getReg();
3703  SrcReg = MI.getOperand(1).getReg();
3704  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3705  MI.getOperand(2).isImm() &&
3706  isUInt<3>(MI.getOperand(2).getImm()))
3707  return HexagonII::HSIG_L2;
3708  break;
3709  case Hexagon::L2_loadrd_io:
3710  // Rdd = memd(r29+#u5:3)
3711  DstReg = MI.getOperand(0).getReg();
3712  SrcReg = MI.getOperand(1).getReg();
3713  if (isDblRegForSubInst(DstReg, HRI) &&
3714  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3715  HRI.getStackRegister() == SrcReg &&
3716  MI.getOperand(2).isImm() &&
3717  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3718  return HexagonII::HSIG_L2;
3719  break;
3720  // dealloc_return is not documented in Hexagon Manual, but marked
3721  // with A_SUBINSN attribute in iset_v4classic.py.
3722  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3723  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3724  case Hexagon::L4_return:
3725  case Hexagon::L2_deallocframe:
3726  return HexagonII::HSIG_L2;
3727  case Hexagon::EH_RETURN_JMPR:
3728  case Hexagon::PS_jmpret:
3729  case Hexagon::SL2_jumpr31:
3730  // jumpr r31
3731  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3732  DstReg = MI.getOperand(0).getReg();
3733  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3734  return HexagonII::HSIG_L2;
3735  break;
3736  case Hexagon::PS_jmprett:
3737  case Hexagon::PS_jmpretf:
3738  case Hexagon::PS_jmprettnewpt:
3739  case Hexagon::PS_jmpretfnewpt:
3740  case Hexagon::PS_jmprettnew:
3741  case Hexagon::PS_jmpretfnew:
3742  case Hexagon::SL2_jumpr31_t:
3743  case Hexagon::SL2_jumpr31_f:
3744  case Hexagon::SL2_jumpr31_tnew:
3745  DstReg = MI.getOperand(1).getReg();
3746  SrcReg = MI.getOperand(0).getReg();
3747  // [if ([!]p0[.new])] jumpr r31
3748  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3749  (Hexagon::P0 == SrcReg)) &&
3750  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3751  return HexagonII::HSIG_L2;
3752  break;
3753  case Hexagon::L4_return_t:
3754  case Hexagon::L4_return_f:
3755  case Hexagon::L4_return_tnew_pnt:
3756  case Hexagon::L4_return_fnew_pnt:
3757  case Hexagon::L4_return_tnew_pt:
3758  case Hexagon::L4_return_fnew_pt:
3759  // [if ([!]p0[.new])] dealloc_return
3760  SrcReg = MI.getOperand(0).getReg();
3761  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3762  return HexagonII::HSIG_L2;
3763  break;
3764  //
3765  // Group S1:
3766  //
3767  // memw(Rs+#u4:2) = Rt
3768  // memb(Rs+#u4:0) = Rt
3769  case Hexagon::S2_storeri_io:
3770  // Special case this one from Group S2.
3771  // memw(r29+#u5:2) = Rt
3772  Src1Reg = MI.getOperand(0).getReg();
3773  Src2Reg = MI.getOperand(2).getReg();
3774  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3775  isIntRegForSubInst(Src2Reg) &&
3776  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3777  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3778  return HexagonII::HSIG_S2;
3779  // memw(Rs+#u4:2) = Rt
3780  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3781  MI.getOperand(1).isImm() &&
3782  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3783  return HexagonII::HSIG_S1;
3784  break;
3785  case Hexagon::S2_storerb_io:
3786  // memb(Rs+#u4:0) = Rt
3787  Src1Reg = MI.getOperand(0).getReg();
3788  Src2Reg = MI.getOperand(2).getReg();
3789  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3790  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3791  return HexagonII::HSIG_S1;
3792  break;
3793  //
3794  // Group S2:
3795  //
3796  // memh(Rs+#u3:1) = Rt
3797  // memw(r29+#u5:2) = Rt
3798  // memd(r29+#s6:3) = Rtt
3799  // memw(Rs+#u4:2) = #U1
3800  // memb(Rs+#u4) = #U1
3801  // allocframe(#u5:3)
3802  case Hexagon::S2_storerh_io:
3803  // memh(Rs+#u3:1) = Rt
3804  Src1Reg = MI.getOperand(0).getReg();
3805  Src2Reg = MI.getOperand(2).getReg();
3806  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3807  MI.getOperand(1).isImm() &&
3808  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3809  return HexagonII::HSIG_S1;
3810  break;
3811  case Hexagon::S2_storerd_io:
3812  // memd(r29+#s6:3) = Rtt
3813  Src1Reg = MI.getOperand(0).getReg();
3814  Src2Reg = MI.getOperand(2).getReg();
3815  if (isDblRegForSubInst(Src2Reg, HRI) &&
3816  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3817  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3818  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3819  return HexagonII::HSIG_S2;
3820  break;
3821  case Hexagon::S4_storeiri_io:
3822  // memw(Rs+#u4:2) = #U1
3823  Src1Reg = MI.getOperand(0).getReg();
3824  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3825  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3826  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3827  return HexagonII::HSIG_S2;
3828  break;
3829  case Hexagon::S4_storeirb_io:
3830  // memb(Rs+#u4) = #U1
3831  Src1Reg = MI.getOperand(0).getReg();
3832  if (isIntRegForSubInst(Src1Reg) &&
3833  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3834  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3835  return HexagonII::HSIG_S2;
3836  break;
3837  case Hexagon::S2_allocframe:
3838  if (MI.getOperand(2).isImm() &&
3839  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3840  return HexagonII::HSIG_S1;
3841  break;
3842  //
3843  // Group A:
3844  //
3845  // Rx = add(Rx,#s7)
3846  // Rd = Rs
3847  // Rd = #u6
3848  // Rd = #-1
3849  // if ([!]P0[.new]) Rd = #0
3850  // Rd = add(r29,#u6:2)
3851  // Rx = add(Rx,Rs)
3852  // P0 = cmp.eq(Rs,#u2)
3853  // Rdd = combine(#0,Rs)
3854  // Rdd = combine(Rs,#0)
3855  // Rdd = combine(#u2,#U2)
3856  // Rd = add(Rs,#1)
3857  // Rd = add(Rs,#-1)
3858  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3859  // Rd = and(Rs,#1)
3860  case Hexagon::A2_addi:
3861  DstReg = MI.getOperand(0).getReg();
3862  SrcReg = MI.getOperand(1).getReg();
3863  if (isIntRegForSubInst(DstReg)) {
3864  // Rd = add(r29,#u6:2)
3865  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3866  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3867  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3868  return HexagonII::HSIG_A;
3869  // Rx = add(Rx,#s7)
3870  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3871  isInt<7>(MI.getOperand(2).getImm()))
3872  return HexagonII::HSIG_A;
3873  // Rd = add(Rs,#1)
3874  // Rd = add(Rs,#-1)
3875  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3876  ((MI.getOperand(2).getImm() == 1) ||
3877  (MI.getOperand(2).getImm() == -1)))
3878  return HexagonII::HSIG_A;
3879  }
3880  break;
3881  case Hexagon::A2_add:
3882  // Rx = add(Rx,Rs)
3883  DstReg = MI.getOperand(0).getReg();
3884  Src1Reg = MI.getOperand(1).getReg();
3885  Src2Reg = MI.getOperand(2).getReg();
3886  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3887  isIntRegForSubInst(Src2Reg))
3888  return HexagonII::HSIG_A;
3889  break;
3890  case Hexagon::A2_andir:
3891  // Same as zxtb.
3892  // Rd16=and(Rs16,#255)
3893  // Rd16=and(Rs16,#1)
3894  DstReg = MI.getOperand(0).getReg();
3895  SrcReg = MI.getOperand(1).getReg();
3896  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3897  MI.getOperand(2).isImm() &&
3898  ((MI.getOperand(2).getImm() == 1) ||
3899  (MI.getOperand(2).getImm() == 255)))
3900  return HexagonII::HSIG_A;
3901  break;
3902  case Hexagon::A2_tfr:
3903  // Rd = Rs
3904  DstReg = MI.getOperand(0).getReg();
3905  SrcReg = MI.getOperand(1).getReg();
3906  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3907  return HexagonII::HSIG_A;
3908  break;
3909  case Hexagon::A2_tfrsi:
3910  // Rd = #u6
3911  // Do not test for #u6 size since the const is getting extended
3912  // regardless and compound could be formed.
3913  // Rd = #-1
3914  DstReg = MI.getOperand(0).getReg();
3915  if (isIntRegForSubInst(DstReg))
3916  return HexagonII::HSIG_A;
3917  break;
3918  case Hexagon::C2_cmoveit:
3919  case Hexagon::C2_cmovenewit:
3920  case Hexagon::C2_cmoveif:
3921  case Hexagon::C2_cmovenewif:
3922  // if ([!]P0[.new]) Rd = #0
3923  // Actual form:
3924  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3925  DstReg = MI.getOperand(0).getReg();
3926  SrcReg = MI.getOperand(1).getReg();
3927  if (isIntRegForSubInst(DstReg) &&
3928  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3929  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3930  return HexagonII::HSIG_A;
3931  break;
3932  case Hexagon::C2_cmpeqi:
3933  // P0 = cmp.eq(Rs,#u2)
3934  DstReg = MI.getOperand(0).getReg();
3935  SrcReg = MI.getOperand(1).getReg();
3936  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3937  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3938  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3939  return HexagonII::HSIG_A;
3940  break;
3941  case Hexagon::A2_combineii:
3942  case Hexagon::A4_combineii:
3943  // Rdd = combine(#u2,#U2)
3944  DstReg = MI.getOperand(0).getReg();
3945  if (isDblRegForSubInst(DstReg, HRI) &&
3946  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3947  (MI.getOperand(1).isGlobal() &&
3948  isUInt<2>(MI.getOperand(1).getOffset()))) &&
3949  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3950  (MI.getOperand(2).isGlobal() &&
3951  isUInt<2>(MI.getOperand(2).getOffset()))))
3952  return HexagonII::HSIG_A;
3953  break;
3954  case Hexagon::A4_combineri:
3955  // Rdd = combine(Rs,#0)
3956  DstReg = MI.getOperand(0).getReg();
3957  SrcReg = MI.getOperand(1).getReg();
3958  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3959  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3960  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3961  return HexagonII::HSIG_A;
3962  break;
3963  case Hexagon::A4_combineir:
3964  // Rdd = combine(#0,Rs)
3965  DstReg = MI.getOperand(0).getReg();
3966  SrcReg = MI.getOperand(2).getReg();
3967  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3968  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3969  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3970  return HexagonII::HSIG_A;
3971  break;
3972  case Hexagon::A2_sxtb:
3973  case Hexagon::A2_sxth:
3974  case Hexagon::A2_zxtb:
3975  case Hexagon::A2_zxth:
3976  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3977  DstReg = MI.getOperand(0).getReg();
3978  SrcReg = MI.getOperand(1).getReg();
3979  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3980  return HexagonII::HSIG_A;
3981  break;
3982  }
3983 
3984  return HexagonII::HSIG_None;
3985 }
3986 
3988  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
3989 }
3990 
3992  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
3993  // Default to one cycle for no itinerary. However, an "empty" itinerary may
3994  // still have a MinLatency property, which getStageLatency checks.
3995  if (!ItinData)
3996  return getInstrLatency(ItinData, MI);
3997 
3998  if (MI.isTransient())
3999  return 0;
4000  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4001 }
4002 
4003 /// getOperandLatency - Compute and return the use operand latency of a given
4004 /// pair of def and use.
4005 /// In most cases, the static scheduling itinerary was enough to determine the
4006 /// operand latency. But it may not be possible for instructions with variable
4007 /// number of defs / uses.
4008 ///
4009 /// This is a raw interface to the itinerary that may be directly overriden by
4010 /// a target. Use computeOperandLatency to get the best estimate of latency.
4012  const MachineInstr &DefMI,
4013  unsigned DefIdx,
4014  const MachineInstr &UseMI,
4015  unsigned UseIdx) const {
4016  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4017 
4018  // Get DefIdx and UseIdx for super registers.
4019  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4020 
4021  if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
4022  if (DefMO.isImplicit()) {
4023  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4024  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4025  if (Idx != -1) {
4026  DefIdx = Idx;
4027  break;
4028  }
4029  }
4030  }
4031 
4032  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4033  if (UseMO.isImplicit()) {
4034  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4035  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4036  if (Idx != -1) {
4037  UseIdx = Idx;
4038  break;
4039  }
4040  }
4041  }
4042  }
4043 
4044  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4045  UseMI, UseIdx);
4046  if (!Latency)
4047  // We should never have 0 cycle latency between two instructions unless
4048  // they can be packetized together. However, this decision can't be made
4049  // here.
4050  Latency = 1;
4051  return Latency;
4052 }
4053 
4054 // inverts the predication logic.
4055 // p -> NotP
4056 // NotP -> P
4058  SmallVectorImpl<MachineOperand> &Cond) const {
4059  if (Cond.empty())
4060  return false;
4061  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4062  Cond[0].setImm(Opc);
4063  return true;
4064 }
4065 
4066 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4067  int InvPredOpcode;
4068  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4069  : Hexagon::getTruePredOpcode(Opc);
4070  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4071  return InvPredOpcode;
4072 
4073  llvm_unreachable("Unexpected predicated instruction");
4074 }
4075 
4076 // Returns the max value that doesn't need to be extended.
4078  const uint64_t F = MI.getDesc().TSFlags;
4079  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4081  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4083 
4084  if (isSigned) // if value is signed
4085  return ~(-1U << (bits - 1));
4086  else
4087  return ~(-1U << bits);
4088 }
4089 
4090 
4092  switch (MI.getOpcode()) {
4093  case Hexagon::L2_loadrbgp:
4094  case Hexagon::L2_loadrdgp:
4095  case Hexagon::L2_loadrhgp:
4096  case Hexagon::L2_loadrigp:
4097  case Hexagon::L2_loadrubgp:
4098  case Hexagon::L2_loadruhgp:
4099  case Hexagon::S2_storerbgp:
4100  case Hexagon::S2_storerbnewgp:
4101  case Hexagon::S2_storerhgp:
4102  case Hexagon::S2_storerhnewgp:
4103  case Hexagon::S2_storerigp:
4104  case Hexagon::S2_storerinewgp:
4105  case Hexagon::S2_storerdgp:
4106  case Hexagon::S2_storerfgp:
4107  return true;
4108  }
4109  const uint64_t F = MI.getDesc().TSFlags;
4110  unsigned addrMode =
4112  // Disallow any base+offset instruction. The assembler does not yet reorder
4113  // based up any zero offset instruction.
4114  return (addrMode == HexagonII::BaseRegOffset ||
4115  addrMode == HexagonII::BaseImmOffset ||
4116  addrMode == HexagonII::BaseLongOffset);
4117 }
4118 
4120  using namespace HexagonII;
4121 
4122  const uint64_t F = MI.getDesc().TSFlags;
4123  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4125  if (Size != 0)
4126  return Size;
4127 
4128  // Handle vector access sizes.
4129  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4130  switch (S) {
4132  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4133  default:
4134  llvm_unreachable("Unexpected instruction");
4135  }
4136 }
4137 
4138 // Returns the min value that doesn't need to be extended.
4140  const uint64_t F = MI.getDesc().TSFlags;
4141  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4143  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4145 
4146  if (isSigned) // if value is signed
4147  return -1U << (bits - 1);
4148  else
4149  return 0;
4150 }
4151 
4152 // Returns opcode of the non-extended equivalent instruction.
4154  // Check if the instruction has a register form that uses register in place
4155  // of the extended operand, if so return that as the non-extended form.
4156  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4157  if (NonExtOpcode >= 0)
4158  return NonExtOpcode;
4159 
4160  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4161  // Check addressing mode and retrieve non-ext equivalent instruction.
4162  switch (getAddrMode(MI)) {
4163  case HexagonII::Absolute:
4164  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4166  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4168  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4169 
4170  default:
4171  return -1;
4172  }
4173  }
4174  return -1;
4175 }
4176 
4178  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4179  if (Cond.empty())
4180  return false;
4181  assert(Cond.size() == 2);
4182  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4183  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4184  return false;
4185  }
4186  PredReg = Cond[1].getReg();
4187  PredRegPos = 1;
4188  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4189  PredRegFlags = 0;
4190  if (Cond[1].isImplicit())
4191  PredRegFlags = RegState::Implicit;
4192  if (Cond[1].isUndef())
4193  PredRegFlags |= RegState::Undef;
4194  return true;
4195 }
4196 
4198  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4199 }
4200 
4202  return Hexagon::getRegForm(MI.getOpcode());
4203 }
4204 
4205 // Return the number of bytes required to encode the instruction.
4206 // Hexagon instructions are fixed length, 4 bytes, unless they
4207 // use a constant extender, which requires another 4 bytes.
4208 // For debug instructions and prolog labels, return 0.
4210  if (MI.isDebugInstr() || MI.isPosition())
4211  return 0;
4212 
4213  unsigned Size = MI.getDesc().getSize();
4214  if (!Size)
4215  // Assume the default insn size in case it cannot be determined
4216  // for whatever reason.
4217  Size = HEXAGON_INSTR_SIZE;
4218 
4219  if (isConstExtended(MI) || isExtended(MI))
4220  Size += HEXAGON_INSTR_SIZE;
4221 
4222  // Try and compute number of instructions in asm.
4224  const MachineBasicBlock &MBB = *MI.getParent();
4225  const MachineFunction *MF = MBB.getParent();
4226  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4227 
4228  // Count the number of register definitions to find the asm string.
4229  unsigned NumDefs = 0;
4230  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4231  ++NumDefs)
4232  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4233 
4234  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4235  // Disassemble the AsmStr and approximate number of instructions.
4236  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4237  Size = getInlineAsmLength(AsmStr, *MAI);
4238  }
4239 
4240  return Size;
4241 }
4242 
4244  const uint64_t F = MI.getDesc().TSFlags;
4245  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4246 }
4247 
4249  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4250  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4251 
4252  return IS.getUnits();
4253 }
4254 
4255 // Calculate size of the basic block without debug instructions.
4257  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4258 }
4259 
4261  MachineBasicBlock::const_iterator BundleHead) const {
4262  assert(BundleHead->isBundle() && "Not a bundle header");
4263  auto MII = BundleHead.getInstrIterator();
4264  // Skip the bundle header.
4265  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4266 }
4267 
4268 /// immediateExtend - Changes the instruction in place to one using an immediate
4269 /// extender.
4271  assert((isExtendable(MI)||isConstExtended(MI)) &&
4272  "Instruction must be extendable");
4273  // Find which operand is extendable.
4274  short ExtOpNum = getCExtOpNum(MI);
4275  MachineOperand &MO = MI.getOperand(ExtOpNum);
4276  // This needs to be something we understand.
4277  assert((MO.isMBB() || MO.isImm()) &&
4278  "Branch with unknown extendable field type");
4279  // Mark given operand as extended.
4281 }
4282 
4284  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4285  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4286  << printMBBReference(*NewTarget);
4287  MI.dump(););
4288  assert(MI.isBranch());
4289  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4290  int TargetPos = MI.getNumOperands() - 1;
4291  // In general branch target is the last operand,
4292  // but some implicit defs added at the end might change it.
4293  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4294  --TargetPos;
4295  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4296  MI.getOperand(TargetPos).setMBB(NewTarget);
4298  NewOpcode = reversePrediction(NewOpcode);
4299  }
4300  MI.setDesc(get(NewOpcode));
4301  return true;
4302 }
4303 
4305  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4307  MachineBasicBlock &B = *A;
4309  DebugLoc DL = I->getDebugLoc();
4310  MachineInstr *NewMI;
4311 
4312  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4313  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4314  NewMI = BuildMI(B, I, DL, get(insn));
4315  LLVM_DEBUG(dbgs() << "\n"
4316  << getName(NewMI->getOpcode())
4317  << " Class: " << NewMI->getDesc().getSchedClass());
4318  NewMI->eraseFromParent();
4319  }
4320  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4321 }
4322 
4323 // inverts the predication logic.
4324 // p -> NotP
4325 // NotP -> P
4327  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4329  return true;
4330 }
4331 
4332 // Reverse the branch prediction.
4333 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4334  int PredRevOpcode = -1;
4335  if (isPredictedTaken(Opcode))
4336  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4337  else
4338  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4339  assert(PredRevOpcode > 0);
4340  return PredRevOpcode;
4341 }
4342 
4343 // TODO: Add more rigorous validation.
4345  const {
4346  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4347 }
4348 
4349 void HexagonInstrInfo::
4351  assert(MIB->isBundle());
4352  MachineOperand &Operand = MIB->getOperand(0);
4353  if (Operand.isImm())
4354  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4355  else
4356  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4357 }
4358 
4360  assert(MIB.isBundle());
4361  const MachineOperand &Operand = MIB.getOperand(0);
4362  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4363 }
4364 
4365 // Addressing mode relations.
4367  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4368 }
4369 
4371  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4372 }
4373 
4375  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4376 }
4377 
4379  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4380 }
4381 
4383  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4384 }
4385 
4387  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4388 }
4389 
4391  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4392 }
4393 
4395  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4396 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
void push_back(const T &Elt)
Definition: SmallVector.h:212
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:875
short changeAddrMode_rr_io(short Opc) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:997
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:479
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:161
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool isInlineAsm() const
Definition: MachineInstr.h:861
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
Check if the instruction or the bundle of instructions has store to stack slots.
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:932
demanded bits
MachineBasicBlock reference.
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:388
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:353
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:476
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:636
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:509
bool isEndLoopN(unsigned Opcode) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isBundle() const
Definition: MachineInstr.h:882
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
const RegList & Regs
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:503
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:475
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:566
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:666
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:540
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const char * getSeparatorString() const
Definition: MCAsmInfo.h:469
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_io_abs(short Opc) const
bool hasUncondBranch(const MachineBasicBlock *B) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:371
short changeAddrMode_abs_io(short Opc) const
unsigned getAddrMode(const MachineInstr &MI) const
int getNonDotCurOp(const MachineInstr &MI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
void setMBB(MachineBasicBlock *MBB)
bool isTC2Early(const MachineInstr &MI) const