LLVM  9.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Debug.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-instrinfo"
65 
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71 
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74  "packetization boundary."));
75 
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78 
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
81  cl::desc("Disable schedule adjustment for new value stores."));
82 
84  "enable-timing-class-latency", cl::Hidden, cl::init(false),
85  cl::desc("Enable timing class latency"));
86 
88  "enable-alu-forwarding", cl::Hidden, cl::init(true),
89  cl::desc("Enable vec alu forwarding"));
90 
92  "enable-acc-forwarding", cl::Hidden, cl::init(true),
93  cl::desc("Enable vec acc forwarding"));
94 
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97 
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
100  cl::desc("Use the DFA based hazard recognizer."));
101 
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113 
114 // Pin the vtable to this file.
115 void HexagonInstrInfo::anchor() {}
116 
118  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119  Subtarget(ST) {}
120 
121 static bool isIntRegForSubInst(unsigned Reg) {
122  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
123  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
124 }
125 
126 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
127  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
128  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
129 }
130 
131 /// Calculate number of instructions excluding the debug instructions.
134  unsigned Count = 0;
135  for (; MIB != MIE; ++MIB) {
136  if (!MIB->isDebugInstr())
137  ++Count;
138  }
139  return Count;
140 }
141 
142 /// Find the hardware loop instruction used to set-up the specified loop.
143 /// On Hexagon, we have two instructions used to set-up the hardware loop
144 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
145 /// to indicate the end of a loop.
147  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
148  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
149  unsigned LOOPi;
150  unsigned LOOPr;
151  if (EndLoopOp == Hexagon::ENDLOOP0) {
152  LOOPi = Hexagon::J2_loop0i;
153  LOOPr = Hexagon::J2_loop0r;
154  } else { // EndLoopOp == Hexagon::EndLOOP1
155  LOOPi = Hexagon::J2_loop1i;
156  LOOPr = Hexagon::J2_loop1r;
157  }
158 
159  // The loop set-up instruction will be in a predecessor block
160  for (MachineBasicBlock *PB : BB->predecessors()) {
161  // If this has been visited, already skip it.
162  if (!Visited.insert(PB).second)
163  continue;
164  if (PB == BB)
165  continue;
166  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
167  unsigned Opc = I->getOpcode();
168  if (Opc == LOOPi || Opc == LOOPr)
169  return &*I;
170  // We've reached a different loop, which means the loop01 has been
171  // removed.
172  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
173  return nullptr;
174  }
175  // Check the predecessors for the LOOP instruction.
176  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
177  return Loop;
178  }
179  return nullptr;
180 }
181 
182 /// Gather register def/uses from MI.
183 /// This treats possible (predicated) defs as actually happening ones
184 /// (conservatively).
185 static inline void parseOperands(const MachineInstr &MI,
187  Defs.clear();
188  Uses.clear();
189 
190  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
191  const MachineOperand &MO = MI.getOperand(i);
192 
193  if (!MO.isReg())
194  continue;
195 
196  unsigned Reg = MO.getReg();
197  if (!Reg)
198  continue;
199 
200  if (MO.isUse())
201  Uses.push_back(MO.getReg());
202 
203  if (MO.isDef())
204  Defs.push_back(MO.getReg());
205  }
206 }
207 
208 // Position dependent, so check twice for swap.
209 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
210  switch (Ga) {
212  default:
213  return false;
214  case HexagonII::HSIG_L1:
215  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
216  case HexagonII::HSIG_L2:
217  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
218  Gb == HexagonII::HSIG_A);
219  case HexagonII::HSIG_S1:
220  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
221  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
222  case HexagonII::HSIG_S2:
223  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
225  Gb == HexagonII::HSIG_A);
226  case HexagonII::HSIG_A:
227  return (Gb == HexagonII::HSIG_A);
229  return (Gb == HexagonII::HSIG_Compound);
230  }
231  return false;
232 }
233 
234 /// isLoadFromStackSlot - If the specified machine instruction is a direct
235 /// load from a stack slot, return the virtual or physical register number of
236 /// the destination along with the FrameIndex of the loaded stack slot. If
237 /// not, return 0. This predicate must return 0 if the instruction has
238 /// any side effects other than loading from the stack slot.
240  int &FrameIndex) const {
241  switch (MI.getOpcode()) {
242  default:
243  break;
244  case Hexagon::L2_loadri_io:
245  case Hexagon::L2_loadrd_io:
246  case Hexagon::V6_vL32b_ai:
247  case Hexagon::V6_vL32b_nt_ai:
248  case Hexagon::V6_vL32Ub_ai:
249  case Hexagon::LDriw_pred:
250  case Hexagon::LDriw_ctr:
251  case Hexagon::PS_vloadrq_ai:
252  case Hexagon::PS_vloadrw_ai:
253  case Hexagon::PS_vloadrw_nt_ai: {
254  const MachineOperand OpFI = MI.getOperand(1);
255  if (!OpFI.isFI())
256  return 0;
257  const MachineOperand OpOff = MI.getOperand(2);
258  if (!OpOff.isImm() || OpOff.getImm() != 0)
259  return 0;
260  FrameIndex = OpFI.getIndex();
261  return MI.getOperand(0).getReg();
262  }
263 
264  case Hexagon::L2_ploadrit_io:
265  case Hexagon::L2_ploadrif_io:
266  case Hexagon::L2_ploadrdt_io:
267  case Hexagon::L2_ploadrdf_io: {
268  const MachineOperand OpFI = MI.getOperand(2);
269  if (!OpFI.isFI())
270  return 0;
271  const MachineOperand OpOff = MI.getOperand(3);
272  if (!OpOff.isImm() || OpOff.getImm() != 0)
273  return 0;
274  FrameIndex = OpFI.getIndex();
275  return MI.getOperand(0).getReg();
276  }
277  }
278 
279  return 0;
280 }
281 
282 /// isStoreToStackSlot - If the specified machine instruction is a direct
283 /// store to a stack slot, return the virtual or physical register number of
284 /// the source reg along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than storing to the stack slot.
288  int &FrameIndex) const {
289  switch (MI.getOpcode()) {
290  default:
291  break;
292  case Hexagon::S2_storerb_io:
293  case Hexagon::S2_storerh_io:
294  case Hexagon::S2_storeri_io:
295  case Hexagon::S2_storerd_io:
296  case Hexagon::V6_vS32b_ai:
297  case Hexagon::V6_vS32Ub_ai:
298  case Hexagon::STriw_pred:
299  case Hexagon::STriw_ctr:
300  case Hexagon::PS_vstorerq_ai:
301  case Hexagon::PS_vstorerw_ai: {
302  const MachineOperand &OpFI = MI.getOperand(0);
303  if (!OpFI.isFI())
304  return 0;
305  const MachineOperand &OpOff = MI.getOperand(1);
306  if (!OpOff.isImm() || OpOff.getImm() != 0)
307  return 0;
308  FrameIndex = OpFI.getIndex();
309  return MI.getOperand(2).getReg();
310  }
311 
312  case Hexagon::S2_pstorerbt_io:
313  case Hexagon::S2_pstorerbf_io:
314  case Hexagon::S2_pstorerht_io:
315  case Hexagon::S2_pstorerhf_io:
316  case Hexagon::S2_pstorerit_io:
317  case Hexagon::S2_pstorerif_io:
318  case Hexagon::S2_pstorerdt_io:
319  case Hexagon::S2_pstorerdf_io: {
320  const MachineOperand &OpFI = MI.getOperand(1);
321  if (!OpFI.isFI())
322  return 0;
323  const MachineOperand &OpOff = MI.getOperand(2);
324  if (!OpOff.isImm() || OpOff.getImm() != 0)
325  return 0;
326  FrameIndex = OpFI.getIndex();
327  return MI.getOperand(3).getReg();
328  }
329  }
330 
331  return 0;
332 }
333 
334 /// This function checks if the instruction or bundle of instructions
335 /// has load from stack slot and returns frameindex and machine memory
336 /// operand of that instruction if true.
338  const MachineInstr &MI,
340  if (MI.isBundle()) {
341  const MachineBasicBlock *MBB = MI.getParent();
343  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
344  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
345  return true;
346  return false;
347  }
348 
349  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
350 }
351 
352 /// This function checks if the instruction or bundle of instructions
353 /// has store to stack slot and returns frameindex and machine memory
354 /// operand of that instruction if true.
356  const MachineInstr &MI,
358  if (MI.isBundle()) {
359  const MachineBasicBlock *MBB = MI.getParent();
361  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
362  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
363  return true;
364  return false;
365  }
366 
367  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
368 }
369 
370 /// This function can analyze one/two way branching only and should (mostly) be
371 /// called by target independent side.
372 /// First entry is always the opcode of the branching instruction, except when
373 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
374 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
375 /// e.g. Jump_c p will have
376 /// Cond[0] = Jump_c
377 /// Cond[1] = p
378 /// HW-loop ENDLOOP:
379 /// Cond[0] = ENDLOOP
380 /// Cond[1] = MBB
381 /// New value jump:
382 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
383 /// Cond[1] = R
384 /// Cond[2] = Imm
386  MachineBasicBlock *&TBB,
387  MachineBasicBlock *&FBB,
389  bool AllowModify) const {
390  TBB = nullptr;
391  FBB = nullptr;
392  Cond.clear();
393 
394  // If the block has no terminators, it just falls into the block after it.
396  if (I == MBB.instr_begin())
397  return false;
398 
399  // A basic block may looks like this:
400  //
401  // [ insn
402  // EH_LABEL
403  // insn
404  // insn
405  // insn
406  // EH_LABEL
407  // insn ]
408  //
409  // It has two succs but does not have a terminator
410  // Don't know how to handle it.
411  do {
412  --I;
413  if (I->isEHLabel())
414  // Don't analyze EH branches.
415  return true;
416  } while (I != MBB.instr_begin());
417 
418  I = MBB.instr_end();
419  --I;
420 
421  while (I->isDebugInstr()) {
422  if (I == MBB.instr_begin())
423  return false;
424  --I;
425  }
426 
427  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
428  I->getOperand(0).isMBB();
429  // Delete the J2_jump if it's equivalent to a fall-through.
430  if (AllowModify && JumpToBlock &&
431  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
432  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
433  I->eraseFromParent();
434  I = MBB.instr_end();
435  if (I == MBB.instr_begin())
436  return false;
437  --I;
438  }
439  if (!isUnpredicatedTerminator(*I))
440  return false;
441 
442  // Get the last instruction in the block.
443  MachineInstr *LastInst = &*I;
444  MachineInstr *SecondLastInst = nullptr;
445  // Find one more terminator if present.
446  while (true) {
447  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
448  if (!SecondLastInst)
449  SecondLastInst = &*I;
450  else
451  // This is a third branch.
452  return true;
453  }
454  if (I == MBB.instr_begin())
455  break;
456  --I;
457  }
458 
459  int LastOpcode = LastInst->getOpcode();
460  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
461  // If the branch target is not a basic block, it could be a tail call.
462  // (It is, if the target is a function.)
463  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
464  return true;
465  if (SecLastOpcode == Hexagon::J2_jump &&
466  !SecondLastInst->getOperand(0).isMBB())
467  return true;
468 
469  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
470  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
471 
472  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
473  return true;
474 
475  // If there is only one terminator instruction, process it.
476  if (LastInst && !SecondLastInst) {
477  if (LastOpcode == Hexagon::J2_jump) {
478  TBB = LastInst->getOperand(0).getMBB();
479  return false;
480  }
481  if (isEndLoopN(LastOpcode)) {
482  TBB = LastInst->getOperand(0).getMBB();
483  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
484  Cond.push_back(LastInst->getOperand(0));
485  return false;
486  }
487  if (LastOpcodeHasJMP_c) {
488  TBB = LastInst->getOperand(1).getMBB();
489  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490  Cond.push_back(LastInst->getOperand(0));
491  return false;
492  }
493  // Only supporting rr/ri versions of new-value jumps.
494  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
495  TBB = LastInst->getOperand(2).getMBB();
496  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
497  Cond.push_back(LastInst->getOperand(0));
498  Cond.push_back(LastInst->getOperand(1));
499  return false;
500  }
501  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
502  << " with one jump\n";);
503  // Otherwise, don't know what this is.
504  return true;
505  }
506 
507  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
508  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
509  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
510  if (!SecondLastInst->getOperand(1).isMBB())
511  return true;
512  TBB = SecondLastInst->getOperand(1).getMBB();
513  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
514  Cond.push_back(SecondLastInst->getOperand(0));
515  FBB = LastInst->getOperand(0).getMBB();
516  return false;
517  }
518 
519  // Only supporting rr/ri versions of new-value jumps.
520  if (SecLastOpcodeHasNVJump &&
521  (SecondLastInst->getNumExplicitOperands() == 3) &&
522  (LastOpcode == Hexagon::J2_jump)) {
523  TBB = SecondLastInst->getOperand(2).getMBB();
524  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
525  Cond.push_back(SecondLastInst->getOperand(0));
526  Cond.push_back(SecondLastInst->getOperand(1));
527  FBB = LastInst->getOperand(0).getMBB();
528  return false;
529  }
530 
531  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
532  // executed, so remove it.
533  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
534  TBB = SecondLastInst->getOperand(0).getMBB();
535  I = LastInst->getIterator();
536  if (AllowModify)
537  I->eraseFromParent();
538  return false;
539  }
540 
541  // If the block ends with an ENDLOOP, and J2_jump, handle it.
542  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
543  TBB = SecondLastInst->getOperand(0).getMBB();
544  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
545  Cond.push_back(SecondLastInst->getOperand(0));
546  FBB = LastInst->getOperand(0).getMBB();
547  return false;
548  }
549  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550  << " with two jumps";);
551  // Otherwise, can't handle this.
552  return true;
553 }
554 
556  int *BytesRemoved) const {
557  assert(!BytesRemoved && "code size not handled");
558 
559  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
561  unsigned Count = 0;
562  while (I != MBB.begin()) {
563  --I;
564  if (I->isDebugInstr())
565  continue;
566  // Only removing branches from end of MBB.
567  if (!I->isBranch())
568  return Count;
569  if (Count && (I->getOpcode() == Hexagon::J2_jump))
570  llvm_unreachable("Malformed basic block: unconditional branch not last");
571  MBB.erase(&MBB.back());
572  I = MBB.end();
573  ++Count;
574  }
575  return Count;
576 }
577 
579  MachineBasicBlock *TBB,
580  MachineBasicBlock *FBB,
582  const DebugLoc &DL,
583  int *BytesAdded) const {
584  unsigned BOpc = Hexagon::J2_jump;
585  unsigned BccOpc = Hexagon::J2_jumpt;
586  assert(validateBranchCond(Cond) && "Invalid branching condition");
587  assert(TBB && "insertBranch must not be told to insert a fallthrough");
588  assert(!BytesAdded && "code size not handled");
589 
590  // Check if reverseBranchCondition has asked to reverse this branch
591  // If we want to reverse the branch an odd number of times, we want
592  // J2_jumpf.
593  if (!Cond.empty() && Cond[0].isImm())
594  BccOpc = Cond[0].getImm();
595 
596  if (!FBB) {
597  if (Cond.empty()) {
598  // Due to a bug in TailMerging/CFG Optimization, we need to add a
599  // special case handling of a predicated jump followed by an
600  // unconditional jump. If not, Tail Merging and CFG Optimization go
601  // into an infinite loop.
602  MachineBasicBlock *NewTBB, *NewFBB;
604  auto Term = MBB.getFirstTerminator();
605  if (Term != MBB.end() && isPredicated(*Term) &&
606  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
607  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
609  removeBranch(MBB);
610  return insertBranch(MBB, TBB, nullptr, Cond, DL);
611  }
612  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
613  } else if (isEndLoopN(Cond[0].getImm())) {
614  int EndLoopOp = Cond[0].getImm();
615  assert(Cond[1].isMBB());
616  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
617  // Check for it, and change the BB target if needed.
619  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
620  VisitedBBs);
621  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
622  Loop->getOperand(0).setMBB(TBB);
623  // Add the ENDLOOP after the finding the LOOP0.
624  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
625  } else if (isNewValueJump(Cond[0].getImm())) {
626  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
627  // New value jump
628  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
629  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
630  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
631  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
632  << printMBBReference(MBB););
633  if (Cond[2].isReg()) {
634  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
635  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
637  } else if(Cond[2].isImm()) {
638  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
639  addImm(Cond[2].getImm()).addMBB(TBB);
640  } else
641  llvm_unreachable("Invalid condition for branching");
642  } else {
643  assert((Cond.size() == 2) && "Malformed cond vector");
644  const MachineOperand &RO = Cond[1];
645  unsigned Flags = getUndefRegState(RO.isUndef());
646  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
647  }
648  return 1;
649  }
650  assert((!Cond.empty()) &&
651  "Cond. cannot be empty when multiple branchings are required");
652  assert((!isNewValueJump(Cond[0].getImm())) &&
653  "NV-jump cannot be inserted with another branch");
654  // Special case for hardware loops. The condition is a basic block.
655  if (isEndLoopN(Cond[0].getImm())) {
656  int EndLoopOp = Cond[0].getImm();
657  assert(Cond[1].isMBB());
658  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659  // Check for it, and change the BB target if needed.
661  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
662  VisitedBBs);
663  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
664  Loop->getOperand(0).setMBB(TBB);
665  // Add the ENDLOOP after the finding the LOOP0.
666  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
667  } else {
668  const MachineOperand &RO = Cond[1];
669  unsigned Flags = getUndefRegState(RO.isUndef());
670  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
671  }
672  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
673 
674  return 2;
675 }
676 
677 /// Analyze the loop code to find the loop induction variable and compare used
678 /// to compute the number of iterations. Currently, we analyze loop that are
679 /// controlled using hardware loops. In this case, the induction variable
680 /// instruction is null. For all other cases, this function returns true, which
681 /// means we're unable to analyze it.
683  MachineInstr *&IndVarInst,
684  MachineInstr *&CmpInst) const {
685 
686  MachineBasicBlock *LoopEnd = L.getBottomBlock();
688  // We really "analyze" only hardware loops right now.
689  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
690  IndVarInst = nullptr;
691  CmpInst = &*I;
692  return false;
693  }
694  return true;
695 }
696 
697 /// Generate code to reduce the loop iteration by one and check if the loop is
698 /// finished. Return the value/register of the new loop count. this function
699 /// assumes the nth iteration is peeled first.
701  MachineInstr *IndVar, MachineInstr &Cmp,
704  unsigned Iter, unsigned MaxIter) const {
705  // We expect a hardware loop currently. This means that IndVar is set
706  // to null, and the compare is the ENDLOOP instruction.
707  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
708  && "Expecting a hardware loop");
709  MachineFunction *MF = MBB.getParent();
710  DebugLoc DL = Cmp.getDebugLoc();
712  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
713  Cmp.getOperand(0).getMBB(), VisitedBBs);
714  if (!Loop)
715  return 0;
716  // If the loop trip count is a compile-time value, then just change the
717  // value.
718  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
719  Loop->getOpcode() == Hexagon::J2_loop1i) {
720  int64_t Offset = Loop->getOperand(1).getImm();
721  if (Offset <= 1)
722  Loop->eraseFromParent();
723  else
724  Loop->getOperand(1).setImm(Offset - 1);
725  return Offset - 1;
726  }
727  // The loop trip count is a run-time value. We generate code to subtract
728  // one from the trip count, and update the loop instruction.
729  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
730  unsigned LoopCount = Loop->getOperand(1).getReg();
731  // Check if we're done with the loop.
732  unsigned LoopEnd = createVR(MF, MVT::i1);
733  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
734  addReg(LoopCount).addImm(1);
735  unsigned NewLoopCount = createVR(MF, MVT::i32);
736  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
737  addReg(LoopCount).addImm(-1);
738  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
739  // Update the previously generated instructions with the new loop counter.
741  E = PrevInsts.end(); I != E; ++I)
742  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
743  PrevInsts.clear();
744  PrevInsts.push_back(NewCmp);
745  PrevInsts.push_back(NewAdd);
746  // Insert the new loop instruction if this is the last time the loop is
747  // decremented.
748  if (Iter == MaxIter)
749  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
750  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
751  // Delete the old loop instruction.
752  if (Iter == 0)
753  Loop->eraseFromParent();
754  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
755  Cond.push_back(NewCmp->getOperand(0));
756  return NewLoopCount;
757 }
758 
760  unsigned NumCycles, unsigned ExtraPredCycles,
761  BranchProbability Probability) const {
762  return nonDbgBBSize(&MBB) <= 3;
763 }
764 
766  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
767  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
768  const {
769  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
770 }
771 
773  unsigned NumInstrs, BranchProbability Probability) const {
774  return NumInstrs <= 4;
775 }
776 
779  const DebugLoc &DL, unsigned DestReg,
780  unsigned SrcReg, bool KillSrc) const {
781  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
782  unsigned KillFlag = getKillRegState(KillSrc);
783 
784  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
785  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
786  .addReg(SrcReg, KillFlag);
787  return;
788  }
789  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
790  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
791  .addReg(SrcReg, KillFlag);
792  return;
793  }
794  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
795  // Map Pd = Ps to Pd = or(Ps, Ps).
796  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
797  .addReg(SrcReg).addReg(SrcReg, KillFlag);
798  return;
799  }
800  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
801  Hexagon::IntRegsRegClass.contains(SrcReg)) {
802  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
803  .addReg(SrcReg, KillFlag);
804  return;
805  }
806  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
807  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
808  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
809  .addReg(SrcReg, KillFlag);
810  return;
811  }
812  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
813  Hexagon::IntRegsRegClass.contains(SrcReg)) {
814  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
815  .addReg(SrcReg, KillFlag);
816  return;
817  }
818  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
819  Hexagon::IntRegsRegClass.contains(DestReg)) {
820  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
821  .addReg(SrcReg, KillFlag);
822  return;
823  }
824  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
825  Hexagon::PredRegsRegClass.contains(DestReg)) {
826  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
827  .addReg(SrcReg, KillFlag);
828  return;
829  }
830  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
831  Hexagon::IntRegsRegClass.contains(DestReg)) {
832  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
833  .addReg(SrcReg, KillFlag);
834  return;
835  }
836  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
837  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
838  addReg(SrcReg, KillFlag);
839  return;
840  }
841  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
842  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
843  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
844  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
845  .addReg(HiSrc, KillFlag)
846  .addReg(LoSrc, KillFlag);
847  return;
848  }
849  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
850  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
851  .addReg(SrcReg)
852  .addReg(SrcReg, KillFlag);
853  return;
854  }
855  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
856  Hexagon::HvxVRRegClass.contains(DestReg)) {
857  llvm_unreachable("Unimplemented pred to vec");
858  return;
859  }
860  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
861  Hexagon::HvxVRRegClass.contains(SrcReg)) {
862  llvm_unreachable("Unimplemented vec to pred");
863  return;
864  }
865 
866 #ifndef NDEBUG
867  // Show the invalid registers to ease debugging.
868  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
869  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
870 #endif
871  llvm_unreachable("Unimplemented");
872 }
873 
875  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
876  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
877  DebugLoc DL = MBB.findDebugLoc(I);
878  MachineFunction &MF = *MBB.getParent();
879  MachineFrameInfo &MFI = MF.getFrameInfo();
880  unsigned SlotAlign = MFI.getObjectAlignment(FI);
881  unsigned RegAlign = TRI->getSpillAlignment(*RC);
882  unsigned KillFlag = getKillRegState(isKill);
883  bool HasAlloca = MFI.hasVarSizedObjects();
884  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
885 
888  MFI.getObjectSize(FI), SlotAlign);
889 
890  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
891  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
892  .addFrameIndex(FI).addImm(0)
893  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
894  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
895  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
896  .addFrameIndex(FI).addImm(0)
897  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
898  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
899  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
900  .addFrameIndex(FI).addImm(0)
901  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
902  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
903  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
904  .addFrameIndex(FI).addImm(0)
905  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
906  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
907  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
908  .addFrameIndex(FI).addImm(0)
909  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
910  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
911  // If there are variable-sized objects, spills will not be aligned.
912  if (HasAlloca)
913  SlotAlign = HFI.getStackAlignment();
914  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
915  : Hexagon::V6_vS32b_ai;
918  MFI.getObjectSize(FI), SlotAlign);
919  BuildMI(MBB, I, DL, get(Opc))
920  .addFrameIndex(FI).addImm(0)
921  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
922  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
923  // If there are variable-sized objects, spills will not be aligned.
924  if (HasAlloca)
925  SlotAlign = HFI.getStackAlignment();
926  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
927  : Hexagon::PS_vstorerw_ai;
930  MFI.getObjectSize(FI), SlotAlign);
931  BuildMI(MBB, I, DL, get(Opc))
932  .addFrameIndex(FI).addImm(0)
933  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
934  } else {
935  llvm_unreachable("Unimplemented");
936  }
937 }
938 
940  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
941  int FI, const TargetRegisterClass *RC,
942  const TargetRegisterInfo *TRI) const {
943  DebugLoc DL = MBB.findDebugLoc(I);
944  MachineFunction &MF = *MBB.getParent();
945  MachineFrameInfo &MFI = MF.getFrameInfo();
946  unsigned SlotAlign = MFI.getObjectAlignment(FI);
947  unsigned RegAlign = TRI->getSpillAlignment(*RC);
948  bool HasAlloca = MFI.hasVarSizedObjects();
949  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
950 
953  MFI.getObjectSize(FI), SlotAlign);
954 
955  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
956  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
957  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
958  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
959  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
960  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
961  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
962  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
963  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
964  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
965  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
966  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
967  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
968  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
969  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
970  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
971  // If there are variable-sized objects, spills will not be aligned.
972  if (HasAlloca)
973  SlotAlign = HFI.getStackAlignment();
974  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
975  : Hexagon::V6_vL32b_ai;
978  MFI.getObjectSize(FI), SlotAlign);
979  BuildMI(MBB, I, DL, get(Opc), DestReg)
980  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
981  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
982  // If there are variable-sized objects, spills will not be aligned.
983  if (HasAlloca)
984  SlotAlign = HFI.getStackAlignment();
985  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
986  : Hexagon::PS_vloadrw_ai;
989  MFI.getObjectSize(FI), SlotAlign);
990  BuildMI(MBB, I, DL, get(Opc), DestReg)
991  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
992  } else {
993  llvm_unreachable("Can't store this register to stack slot");
994  }
995 }
996 
997 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
998  const MachineBasicBlock &B = *MI.getParent();
999  Regs.addLiveOuts(B);
1000  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1001  for (auto I = B.rbegin(); I != E; ++I)
1002  Regs.stepBackward(*I);
1003 }
1004 
1005 /// expandPostRAPseudo - This function is called for all pseudo instructions
1006 /// that remain after register allocation. Many pseudo instructions are
1007 /// created to help register allocation. This is the place to convert them
1008 /// into real instructions. The target can edit MI in place, or it can insert
1009 /// new instructions and erase MI. The function should return true if
1010 /// anything was changed.
1012  MachineBasicBlock &MBB = *MI.getParent();
1013  MachineFunction &MF = *MBB.getParent();
1015  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1016  DebugLoc DL = MI.getDebugLoc();
1017  unsigned Opc = MI.getOpcode();
1018 
1019  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1020  unsigned Mx = MI.getOperand(MxOp).getReg();
1021  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1022  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1023  .add(MI.getOperand((HasImm ? 5 : 4)));
1024  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1025  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1026  if (HasImm)
1027  MIB.add(MI.getOperand(4));
1028  MIB.addReg(CSx, RegState::Implicit);
1029  MBB.erase(MI);
1030  return true;
1031  };
1032 
1033  switch (Opc) {
1034  case TargetOpcode::COPY: {
1035  MachineOperand &MD = MI.getOperand(0);
1036  MachineOperand &MS = MI.getOperand(1);
1038  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1039  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1040  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1041  }
1042  MBB.erase(MBBI);
1043  return true;
1044  }
1045  case Hexagon::PS_aligna:
1046  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1047  .addReg(HRI.getFrameRegister())
1048  .addImm(-MI.getOperand(1).getImm());
1049  MBB.erase(MI);
1050  return true;
1051  case Hexagon::V6_vassignp: {
1052  unsigned SrcReg = MI.getOperand(1).getReg();
1053  unsigned DstReg = MI.getOperand(0).getReg();
1054  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1055  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1056  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1057  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1058  MBB.erase(MI);
1059  return true;
1060  }
1061  case Hexagon::V6_lo: {
1062  unsigned SrcReg = MI.getOperand(1).getReg();
1063  unsigned DstReg = MI.getOperand(0).getReg();
1064  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1065  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1066  MBB.erase(MI);
1067  MRI.clearKillFlags(SrcSubLo);
1068  return true;
1069  }
1070  case Hexagon::V6_hi: {
1071  unsigned SrcReg = MI.getOperand(1).getReg();
1072  unsigned DstReg = MI.getOperand(0).getReg();
1073  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1074  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1075  MBB.erase(MI);
1076  MRI.clearKillFlags(SrcSubHi);
1077  return true;
1078  }
1079  case Hexagon::PS_vstorerw_ai:
1080  case Hexagon::PS_vstorerwu_ai: {
1081  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1082  unsigned SrcReg = MI.getOperand(2).getReg();
1083  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1084  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1085  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1086  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1087 
1088  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1089  .add(MI.getOperand(0))
1090  .addImm(MI.getOperand(1).getImm())
1091  .addReg(SrcSubLo)
1092  .cloneMemRefs(MI);
1093  MI1New->getOperand(0).setIsKill(false);
1094  BuildMI(MBB, MI, DL, get(NewOpc))
1095  .add(MI.getOperand(0))
1096  // The Vectors are indexed in multiples of vector size.
1097  .addImm(MI.getOperand(1).getImm() + Offset)
1098  .addReg(SrcSubHi)
1099  .cloneMemRefs(MI);
1100  MBB.erase(MI);
1101  return true;
1102  }
1103  case Hexagon::PS_vloadrw_ai:
1104  case Hexagon::PS_vloadrwu_ai: {
1105  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1106  unsigned DstReg = MI.getOperand(0).getReg();
1107  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1108  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1109 
1110  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1111  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1112  .add(MI.getOperand(1))
1113  .addImm(MI.getOperand(2).getImm())
1114  .cloneMemRefs(MI);
1115  MI1New->getOperand(1).setIsKill(false);
1116  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1117  .add(MI.getOperand(1))
1118  // The Vectors are indexed in multiples of vector size.
1119  .addImm(MI.getOperand(2).getImm() + Offset)
1120  .cloneMemRefs(MI);
1121  MBB.erase(MI);
1122  return true;
1123  }
1124  case Hexagon::PS_true: {
1125  unsigned Reg = MI.getOperand(0).getReg();
1126  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1127  .addReg(Reg, RegState::Undef)
1128  .addReg(Reg, RegState::Undef);
1129  MBB.erase(MI);
1130  return true;
1131  }
1132  case Hexagon::PS_false: {
1133  unsigned Reg = MI.getOperand(0).getReg();
1134  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1135  .addReg(Reg, RegState::Undef)
1136  .addReg(Reg, RegState::Undef);
1137  MBB.erase(MI);
1138  return true;
1139  }
1140  case Hexagon::PS_qtrue: {
1141  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1142  .addReg(Hexagon::V0, RegState::Undef)
1143  .addReg(Hexagon::V0, RegState::Undef);
1144  MBB.erase(MI);
1145  return true;
1146  }
1147  case Hexagon::PS_qfalse: {
1148  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1149  .addReg(Hexagon::V0, RegState::Undef)
1150  .addReg(Hexagon::V0, RegState::Undef);
1151  MBB.erase(MI);
1152  return true;
1153  }
1154  case Hexagon::PS_vdd0: {
1155  unsigned Vd = MI.getOperand(0).getReg();
1156  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1157  .addReg(Vd, RegState::Undef)
1158  .addReg(Vd, RegState::Undef);
1159  MBB.erase(MI);
1160  return true;
1161  }
1162  case Hexagon::PS_vmulw: {
1163  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1164  unsigned DstReg = MI.getOperand(0).getReg();
1165  unsigned Src1Reg = MI.getOperand(1).getReg();
1166  unsigned Src2Reg = MI.getOperand(2).getReg();
1167  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1168  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1169  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1170  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1171  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1172  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1173  .addReg(Src1SubHi)
1174  .addReg(Src2SubHi);
1175  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1176  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1177  .addReg(Src1SubLo)
1178  .addReg(Src2SubLo);
1179  MBB.erase(MI);
1180  MRI.clearKillFlags(Src1SubHi);
1181  MRI.clearKillFlags(Src1SubLo);
1182  MRI.clearKillFlags(Src2SubHi);
1183  MRI.clearKillFlags(Src2SubLo);
1184  return true;
1185  }
1186  case Hexagon::PS_vmulw_acc: {
1187  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1188  unsigned DstReg = MI.getOperand(0).getReg();
1189  unsigned Src1Reg = MI.getOperand(1).getReg();
1190  unsigned Src2Reg = MI.getOperand(2).getReg();
1191  unsigned Src3Reg = MI.getOperand(3).getReg();
1192  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1193  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1194  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1195  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1196  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1197  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1198  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1199  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1200  .addReg(Src1SubHi)
1201  .addReg(Src2SubHi)
1202  .addReg(Src3SubHi);
1203  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1204  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1205  .addReg(Src1SubLo)
1206  .addReg(Src2SubLo)
1207  .addReg(Src3SubLo);
1208  MBB.erase(MI);
1209  MRI.clearKillFlags(Src1SubHi);
1210  MRI.clearKillFlags(Src1SubLo);
1211  MRI.clearKillFlags(Src2SubHi);
1212  MRI.clearKillFlags(Src2SubLo);
1213  MRI.clearKillFlags(Src3SubHi);
1214  MRI.clearKillFlags(Src3SubLo);
1215  return true;
1216  }
1217  case Hexagon::PS_pselect: {
1218  const MachineOperand &Op0 = MI.getOperand(0);
1219  const MachineOperand &Op1 = MI.getOperand(1);
1220  const MachineOperand &Op2 = MI.getOperand(2);
1221  const MachineOperand &Op3 = MI.getOperand(3);
1222  unsigned Rd = Op0.getReg();
1223  unsigned Pu = Op1.getReg();
1224  unsigned Rs = Op2.getReg();
1225  unsigned Rt = Op3.getReg();
1226  DebugLoc DL = MI.getDebugLoc();
1227  unsigned K1 = getKillRegState(Op1.isKill());
1228  unsigned K2 = getKillRegState(Op2.isKill());
1229  unsigned K3 = getKillRegState(Op3.isKill());
1230  if (Rd != Rs)
1231  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1232  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1233  .addReg(Rs, K2);
1234  if (Rd != Rt)
1235  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1236  .addReg(Pu, K1)
1237  .addReg(Rt, K3);
1238  MBB.erase(MI);
1239  return true;
1240  }
1241  case Hexagon::PS_vselect: {
1242  const MachineOperand &Op0 = MI.getOperand(0);
1243  const MachineOperand &Op1 = MI.getOperand(1);
1244  const MachineOperand &Op2 = MI.getOperand(2);
1245  const MachineOperand &Op3 = MI.getOperand(3);
1246  LivePhysRegs LiveAtMI(HRI);
1247  getLiveRegsAt(LiveAtMI, MI);
1248  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1249  unsigned PReg = Op1.getReg();
1250  assert(Op1.getSubReg() == 0);
1251  unsigned PState = getRegState(Op1);
1252 
1253  if (Op0.getReg() != Op2.getReg()) {
1254  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1255  : PState;
1256  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1257  .add(Op0)
1258  .addReg(PReg, S)
1259  .add(Op2);
1260  if (IsDestLive)
1261  T.addReg(Op0.getReg(), RegState::Implicit);
1262  IsDestLive = true;
1263  }
1264  if (Op0.getReg() != Op3.getReg()) {
1265  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1266  .add(Op0)
1267  .addReg(PReg, PState)
1268  .add(Op3);
1269  if (IsDestLive)
1270  T.addReg(Op0.getReg(), RegState::Implicit);
1271  }
1272  MBB.erase(MI);
1273  return true;
1274  }
1275  case Hexagon::PS_wselect: {
1276  MachineOperand &Op0 = MI.getOperand(0);
1277  MachineOperand &Op1 = MI.getOperand(1);
1278  MachineOperand &Op2 = MI.getOperand(2);
1279  MachineOperand &Op3 = MI.getOperand(3);
1280  LivePhysRegs LiveAtMI(HRI);
1281  getLiveRegsAt(LiveAtMI, MI);
1282  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1283  unsigned PReg = Op1.getReg();
1284  assert(Op1.getSubReg() == 0);
1285  unsigned PState = getRegState(Op1);
1286 
1287  if (Op0.getReg() != Op2.getReg()) {
1288  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1289  : PState;
1290  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1291  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1292  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1293  .add(Op0)
1294  .addReg(PReg, S)
1295  .addReg(SrcHi)
1296  .addReg(SrcLo);
1297  if (IsDestLive)
1298  T.addReg(Op0.getReg(), RegState::Implicit);
1299  IsDestLive = true;
1300  }
1301  if (Op0.getReg() != Op3.getReg()) {
1302  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1303  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1304  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1305  .add(Op0)
1306  .addReg(PReg, PState)
1307  .addReg(SrcHi)
1308  .addReg(SrcLo);
1309  if (IsDestLive)
1310  T.addReg(Op0.getReg(), RegState::Implicit);
1311  }
1312  MBB.erase(MI);
1313  return true;
1314  }
1315 
1316  case Hexagon::PS_tailcall_i:
1317  MI.setDesc(get(Hexagon::J2_jump));
1318  return true;
1319  case Hexagon::PS_tailcall_r:
1320  case Hexagon::PS_jmpret:
1321  MI.setDesc(get(Hexagon::J2_jumpr));
1322  return true;
1323  case Hexagon::PS_jmprett:
1324  MI.setDesc(get(Hexagon::J2_jumprt));
1325  return true;
1326  case Hexagon::PS_jmpretf:
1327  MI.setDesc(get(Hexagon::J2_jumprf));
1328  return true;
1329  case Hexagon::PS_jmprettnewpt:
1330  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1331  return true;
1332  case Hexagon::PS_jmpretfnewpt:
1333  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1334  return true;
1335  case Hexagon::PS_jmprettnew:
1336  MI.setDesc(get(Hexagon::J2_jumprtnew));
1337  return true;
1338  case Hexagon::PS_jmpretfnew:
1339  MI.setDesc(get(Hexagon::J2_jumprfnew));
1340  return true;
1341 
1342  case Hexagon::PS_loadrub_pci:
1343  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1344  case Hexagon::PS_loadrb_pci:
1345  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1346  case Hexagon::PS_loadruh_pci:
1347  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1348  case Hexagon::PS_loadrh_pci:
1349  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1350  case Hexagon::PS_loadri_pci:
1351  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1352  case Hexagon::PS_loadrd_pci:
1353  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1354  case Hexagon::PS_loadrub_pcr:
1355  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1356  case Hexagon::PS_loadrb_pcr:
1357  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1358  case Hexagon::PS_loadruh_pcr:
1359  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1360  case Hexagon::PS_loadrh_pcr:
1361  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1362  case Hexagon::PS_loadri_pcr:
1363  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1364  case Hexagon::PS_loadrd_pcr:
1365  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1366  case Hexagon::PS_storerb_pci:
1367  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1368  case Hexagon::PS_storerh_pci:
1369  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1370  case Hexagon::PS_storerf_pci:
1371  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1372  case Hexagon::PS_storeri_pci:
1373  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1374  case Hexagon::PS_storerd_pci:
1375  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1376  case Hexagon::PS_storerb_pcr:
1377  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1378  case Hexagon::PS_storerh_pcr:
1379  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1380  case Hexagon::PS_storerf_pcr:
1381  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1382  case Hexagon::PS_storeri_pcr:
1383  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1384  case Hexagon::PS_storerd_pcr:
1385  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1386  }
1387 
1388  return false;
1389 }
1390 
1393  MachineBasicBlock &MBB = *MI.getParent();
1394  const DebugLoc &DL = MI.getDebugLoc();
1395  unsigned Opc = MI.getOpcode();
1397 
1398  switch (Opc) {
1399  case Hexagon::V6_vgathermh_pseudo:
1400  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1401  .add(MI.getOperand(1))
1402  .add(MI.getOperand(2))
1403  .add(MI.getOperand(3));
1404  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1405  .add(MI.getOperand(0))
1406  .addImm(0)
1407  .addReg(Hexagon::VTMP);
1408  MBB.erase(MI);
1409  return First.getInstrIterator();
1410 
1411  case Hexagon::V6_vgathermw_pseudo:
1412  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1413  .add(MI.getOperand(1))
1414  .add(MI.getOperand(2))
1415  .add(MI.getOperand(3));
1416  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1417  .add(MI.getOperand(0))
1418  .addImm(0)
1419  .addReg(Hexagon::VTMP);
1420  MBB.erase(MI);
1421  return First.getInstrIterator();
1422 
1423  case Hexagon::V6_vgathermhw_pseudo:
1424  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1425  .add(MI.getOperand(1))
1426  .add(MI.getOperand(2))
1427  .add(MI.getOperand(3));
1428  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1429  .add(MI.getOperand(0))
1430  .addImm(0)
1431  .addReg(Hexagon::VTMP);
1432  MBB.erase(MI);
1433  return First.getInstrIterator();
1434 
1435  case Hexagon::V6_vgathermhq_pseudo:
1436  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1437  .add(MI.getOperand(1))
1438  .add(MI.getOperand(2))
1439  .add(MI.getOperand(3))
1440  .add(MI.getOperand(4));
1441  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1442  .add(MI.getOperand(0))
1443  .addImm(0)
1444  .addReg(Hexagon::VTMP);
1445  MBB.erase(MI);
1446  return First.getInstrIterator();
1447 
1448  case Hexagon::V6_vgathermwq_pseudo:
1449  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1450  .add(MI.getOperand(1))
1451  .add(MI.getOperand(2))
1452  .add(MI.getOperand(3))
1453  .add(MI.getOperand(4));
1454  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1455  .add(MI.getOperand(0))
1456  .addImm(0)
1457  .addReg(Hexagon::VTMP);
1458  MBB.erase(MI);
1459  return First.getInstrIterator();
1460 
1461  case Hexagon::V6_vgathermhwq_pseudo:
1462  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1463  .add(MI.getOperand(1))
1464  .add(MI.getOperand(2))
1465  .add(MI.getOperand(3))
1466  .add(MI.getOperand(4));
1467  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1468  .add(MI.getOperand(0))
1469  .addImm(0)
1470  .addReg(Hexagon::VTMP);
1471  MBB.erase(MI);
1472  return First.getInstrIterator();
1473  }
1474 
1475  return MI.getIterator();
1476 }
1477 
1478 // We indicate that we want to reverse the branch by
1479 // inserting the reversed branching opcode.
1481  SmallVectorImpl<MachineOperand> &Cond) const {
1482  if (Cond.empty())
1483  return true;
1484  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1485  unsigned opcode = Cond[0].getImm();
1486  //unsigned temp;
1487  assert(get(opcode).isBranch() && "Should be a branching condition.");
1488  if (isEndLoopN(opcode))
1489  return true;
1490  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1491  Cond[0].setImm(NewOpcode);
1492  return false;
1493 }
1494 
1497  DebugLoc DL;
1498  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1499 }
1500 
1502  return getAddrMode(MI) == HexagonII::PostInc;
1503 }
1504 
1505 // Returns true if an instruction is predicated irrespective of the predicate
1506 // sense. For example, all of the following will return true.
1507 // if (p0) R1 = add(R2, R3)
1508 // if (!p0) R1 = add(R2, R3)
1509 // if (p0.new) R1 = add(R2, R3)
1510 // if (!p0.new) R1 = add(R2, R3)
1511 // Note: New-value stores are not included here as in the current
1512 // implementation, we don't need to check their predicate sense.
1514  const uint64_t F = MI.getDesc().TSFlags;
1516 }
1517 
1519  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1520  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1521  isEndLoopN(Cond[0].getImm())) {
1522  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1523  return false;
1524  }
1525  int Opc = MI.getOpcode();
1526  assert (isPredicable(MI) && "Expected predicable instruction");
1527  bool invertJump = predOpcodeHasNot(Cond);
1528 
1529  // We have to predicate MI "in place", i.e. after this function returns,
1530  // MI will need to be transformed into a predicated form. To avoid com-
1531  // plicated manipulations with the operands (handling tied operands,
1532  // etc.), build a new temporary instruction, then overwrite MI with it.
1533 
1534  MachineBasicBlock &B = *MI.getParent();
1535  DebugLoc DL = MI.getDebugLoc();
1536  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1537  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1538  unsigned NOp = 0, NumOps = MI.getNumOperands();
1539  while (NOp < NumOps) {
1540  MachineOperand &Op = MI.getOperand(NOp);
1541  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1542  break;
1543  T.add(Op);
1544  NOp++;
1545  }
1546 
1547  unsigned PredReg, PredRegPos, PredRegFlags;
1548  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1549  (void)GotPredReg;
1550  assert(GotPredReg);
1551  T.addReg(PredReg, PredRegFlags);
1552  while (NOp < NumOps)
1553  T.add(MI.getOperand(NOp++));
1554 
1555  MI.setDesc(get(PredOpc));
1556  while (unsigned n = MI.getNumOperands())
1557  MI.RemoveOperand(n-1);
1558  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1559  MI.addOperand(T->getOperand(i));
1560 
1562  B.erase(TI);
1563 
1565  MRI.clearKillFlags(PredReg);
1566  return true;
1567 }
1568 
1570  ArrayRef<MachineOperand> Pred2) const {
1571  // TODO: Fix this
1572  return false;
1573 }
1574 
1576  std::vector<MachineOperand> &Pred) const {
1577  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1578 
1579  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1580  MachineOperand MO = MI.getOperand(oper);
1581  if (MO.isReg()) {
1582  if (!MO.isDef())
1583  continue;
1584  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1585  if (RC == &Hexagon::PredRegsRegClass) {
1586  Pred.push_back(MO);
1587  return true;
1588  }
1589  continue;
1590  } else if (MO.isRegMask()) {
1591  for (unsigned PR : Hexagon::PredRegsRegClass) {
1592  if (!MI.modifiesRegister(PR, &HRI))
1593  continue;
1594  Pred.push_back(MO);
1595  return true;
1596  }
1597  }
1598  }
1599  return false;
1600 }
1601 
1603  if (!MI.getDesc().isPredicable())
1604  return false;
1605 
1606  if (MI.isCall() || isTailCall(MI)) {
1607  if (!Subtarget.usePredicatedCalls())
1608  return false;
1609  }
1610 
1611  // HVX loads are not predicable on v60, but are on v62.
1612  if (!Subtarget.hasV62Ops()) {
1613  switch (MI.getOpcode()) {
1614  case Hexagon::V6_vL32b_ai:
1615  case Hexagon::V6_vL32b_pi:
1616  case Hexagon::V6_vL32b_ppu:
1617  case Hexagon::V6_vL32b_cur_ai:
1618  case Hexagon::V6_vL32b_cur_pi:
1619  case Hexagon::V6_vL32b_cur_ppu:
1620  case Hexagon::V6_vL32b_nt_ai:
1621  case Hexagon::V6_vL32b_nt_pi:
1622  case Hexagon::V6_vL32b_nt_ppu:
1623  case Hexagon::V6_vL32b_tmp_ai:
1624  case Hexagon::V6_vL32b_tmp_pi:
1625  case Hexagon::V6_vL32b_tmp_ppu:
1626  case Hexagon::V6_vL32b_nt_cur_ai:
1627  case Hexagon::V6_vL32b_nt_cur_pi:
1628  case Hexagon::V6_vL32b_nt_cur_ppu:
1629  case Hexagon::V6_vL32b_nt_tmp_ai:
1630  case Hexagon::V6_vL32b_nt_tmp_pi:
1631  case Hexagon::V6_vL32b_nt_tmp_ppu:
1632  return false;
1633  }
1634  }
1635  return true;
1636 }
1637 
1639  const MachineBasicBlock *MBB,
1640  const MachineFunction &MF) const {
1641  // Debug info is never a scheduling boundary. It's necessary to be explicit
1642  // due to the special treatment of IT instructions below, otherwise a
1643  // dbg_value followed by an IT will result in the IT instruction being
1644  // considered a scheduling hazard, which is wrong. It should be the actual
1645  // instruction preceding the dbg_value instruction(s), just like it is
1646  // when debug info is not present.
1647  if (MI.isDebugInstr())
1648  return false;
1649 
1650  // Throwing call is a boundary.
1651  if (MI.isCall()) {
1652  // Don't mess around with no return calls.
1653  if (doesNotReturn(MI))
1654  return true;
1655  // If any of the block's successors is a landing pad, this could be a
1656  // throwing call.
1657  for (auto I : MBB->successors())
1658  if (I->isEHPad())
1659  return true;
1660  }
1661 
1662  // Terminators and labels can't be scheduled around.
1663  if (MI.getDesc().isTerminator() || MI.isPosition())
1664  return true;
1665 
1666  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1667  return true;
1668 
1669  return false;
1670 }
1671 
1672 /// Measure the specified inline asm to determine an approximation of its
1673 /// length.
1674 /// Comments (which run till the next SeparatorString or newline) do not
1675 /// count as an instruction.
1676 /// Any other non-whitespace text is considered an instruction, with
1677 /// multiple instructions separated by SeparatorString or newlines.
1678 /// Variable-length instructions are not handled here; this function
1679 /// may be overloaded in the target code to do that.
1680 /// Hexagon counts the number of ##'s and adjust for that many
1681 /// constant exenders.
1682 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1683  const MCAsmInfo &MAI) const {
1684  StringRef AStr(Str);
1685  // Count the number of instructions in the asm.
1686  bool atInsnStart = true;
1687  unsigned Length = 0;
1688  for (; *Str; ++Str) {
1689  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1690  strlen(MAI.getSeparatorString())) == 0)
1691  atInsnStart = true;
1692  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1693  Length += MAI.getMaxInstLength();
1694  atInsnStart = false;
1695  }
1696  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1697  MAI.getCommentString().size()) == 0)
1698  atInsnStart = false;
1699  }
1700 
1701  // Add to size number of constant extenders seen * 4.
1702  StringRef Occ("##");
1703  Length += AStr.count(Occ)*4;
1704  return Length;
1705 }
1706 
1709  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1710  if (UseDFAHazardRec)
1711  return new HexagonHazardRecognizer(II, this, Subtarget);
1713 }
1714 
1715 /// For a comparison instruction, return the source registers in
1716 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1717 /// compares against in CmpValue. Return true if the comparison instruction
1718 /// can be analyzed.
1719 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1720  unsigned &SrcReg2, int &Mask,
1721  int &Value) const {
1722  unsigned Opc = MI.getOpcode();
1723 
1724  // Set mask and the first source register.
1725  switch (Opc) {
1726  case Hexagon::C2_cmpeq:
1727  case Hexagon::C2_cmpeqp:
1728  case Hexagon::C2_cmpgt:
1729  case Hexagon::C2_cmpgtp:
1730  case Hexagon::C2_cmpgtu:
1731  case Hexagon::C2_cmpgtup:
1732  case Hexagon::C4_cmpneq:
1733  case Hexagon::C4_cmplte:
1734  case Hexagon::C4_cmplteu:
1735  case Hexagon::C2_cmpeqi:
1736  case Hexagon::C2_cmpgti:
1737  case Hexagon::C2_cmpgtui:
1738  case Hexagon::C4_cmpneqi:
1739  case Hexagon::C4_cmplteui:
1740  case Hexagon::C4_cmpltei:
1741  SrcReg = MI.getOperand(1).getReg();
1742  Mask = ~0;
1743  break;
1744  case Hexagon::A4_cmpbeq:
1745  case Hexagon::A4_cmpbgt:
1746  case Hexagon::A4_cmpbgtu:
1747  case Hexagon::A4_cmpbeqi:
1748  case Hexagon::A4_cmpbgti:
1749  case Hexagon::A4_cmpbgtui:
1750  SrcReg = MI.getOperand(1).getReg();
1751  Mask = 0xFF;
1752  break;
1753  case Hexagon::A4_cmpheq:
1754  case Hexagon::A4_cmphgt:
1755  case Hexagon::A4_cmphgtu:
1756  case Hexagon::A4_cmpheqi:
1757  case Hexagon::A4_cmphgti:
1758  case Hexagon::A4_cmphgtui:
1759  SrcReg = MI.getOperand(1).getReg();
1760  Mask = 0xFFFF;
1761  break;
1762  }
1763 
1764  // Set the value/second source register.
1765  switch (Opc) {
1766  case Hexagon::C2_cmpeq:
1767  case Hexagon::C2_cmpeqp:
1768  case Hexagon::C2_cmpgt:
1769  case Hexagon::C2_cmpgtp:
1770  case Hexagon::C2_cmpgtu:
1771  case Hexagon::C2_cmpgtup:
1772  case Hexagon::A4_cmpbeq:
1773  case Hexagon::A4_cmpbgt:
1774  case Hexagon::A4_cmpbgtu:
1775  case Hexagon::A4_cmpheq:
1776  case Hexagon::A4_cmphgt:
1777  case Hexagon::A4_cmphgtu:
1778  case Hexagon::C4_cmpneq:
1779  case Hexagon::C4_cmplte:
1780  case Hexagon::C4_cmplteu:
1781  SrcReg2 = MI.getOperand(2).getReg();
1782  return true;
1783 
1784  case Hexagon::C2_cmpeqi:
1785  case Hexagon::C2_cmpgtui:
1786  case Hexagon::C2_cmpgti:
1787  case Hexagon::C4_cmpneqi:
1788  case Hexagon::C4_cmplteui:
1789  case Hexagon::C4_cmpltei:
1790  case Hexagon::A4_cmpbeqi:
1791  case Hexagon::A4_cmpbgti:
1792  case Hexagon::A4_cmpbgtui:
1793  case Hexagon::A4_cmpheqi:
1794  case Hexagon::A4_cmphgti:
1795  case Hexagon::A4_cmphgtui: {
1796  SrcReg2 = 0;
1797  const MachineOperand &Op2 = MI.getOperand(2);
1798  if (!Op2.isImm())
1799  return false;
1800  Value = MI.getOperand(2).getImm();
1801  return true;
1802  }
1803  }
1804 
1805  return false;
1806 }
1807 
1809  const MachineInstr &MI,
1810  unsigned *PredCost) const {
1811  return getInstrTimingClassLatency(ItinData, MI);
1812 }
1813 
1815  const TargetSubtargetInfo &STI) const {
1816  const InstrItineraryData *II = STI.getInstrItineraryData();
1817  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1818 }
1819 
1820 // Inspired by this pair:
1821 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1822 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1823 // Currently AA considers the addresses in these instructions to be aliasing.
1825  MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1826  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1828  return false;
1829 
1830  // Instructions that are pure loads, not loads and stores like memops are not
1831  // dependent.
1832  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1833  return true;
1834 
1835  // Get the base register in MIa.
1836  unsigned BasePosA, OffsetPosA;
1837  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1838  return false;
1839  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1840  unsigned BaseRegA = BaseA.getReg();
1841  unsigned BaseSubA = BaseA.getSubReg();
1842 
1843  // Get the base register in MIb.
1844  unsigned BasePosB, OffsetPosB;
1845  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1846  return false;
1847  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1848  unsigned BaseRegB = BaseB.getReg();
1849  unsigned BaseSubB = BaseB.getSubReg();
1850 
1851  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1852  return false;
1853 
1854  // Get the access sizes.
1855  unsigned SizeA = getMemAccessSize(MIa);
1856  unsigned SizeB = getMemAccessSize(MIb);
1857 
1858  // Get the offsets. Handle immediates only for now.
1859  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1860  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1861  if (!MIa.getOperand(OffsetPosA).isImm() ||
1862  !MIb.getOperand(OffsetPosB).isImm())
1863  return false;
1864  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1865  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1866 
1867  // This is a mem access with the same base register and known offsets from it.
1868  // Reason about it.
1869  if (OffsetA > OffsetB) {
1870  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1871  return SizeB <= OffDiff;
1872  }
1873  if (OffsetA < OffsetB) {
1874  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1875  return SizeA <= OffDiff;
1876  }
1877 
1878  return false;
1879 }
1880 
1881 /// If the instruction is an increment of a constant value, return the amount.
1883  int &Value) const {
1884  if (isPostIncrement(MI)) {
1885  unsigned BasePos = 0, OffsetPos = 0;
1886  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1887  return false;
1888  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1889  if (OffsetOp.isImm()) {
1890  Value = OffsetOp.getImm();
1891  return true;
1892  }
1893  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1894  const MachineOperand &AddOp = MI.getOperand(2);
1895  if (AddOp.isImm()) {
1896  Value = AddOp.getImm();
1897  return true;
1898  }
1899  }
1900 
1901  return false;
1902 }
1903 
1904 std::pair<unsigned, unsigned>
1906  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1907  TF & HexagonII::MO_Bitmasks);
1908 }
1909 
1912  using namespace HexagonII;
1913 
1914  static const std::pair<unsigned, const char*> Flags[] = {
1915  {MO_PCREL, "hexagon-pcrel"},
1916  {MO_GOT, "hexagon-got"},
1917  {MO_LO16, "hexagon-lo16"},
1918  {MO_HI16, "hexagon-hi16"},
1919  {MO_GPREL, "hexagon-gprel"},
1920  {MO_GDGOT, "hexagon-gdgot"},
1921  {MO_GDPLT, "hexagon-gdplt"},
1922  {MO_IE, "hexagon-ie"},
1923  {MO_IEGOT, "hexagon-iegot"},
1924  {MO_TPREL, "hexagon-tprel"}
1925  };
1926  return makeArrayRef(Flags);
1927 }
1928 
1931  using namespace HexagonII;
1932 
1933  static const std::pair<unsigned, const char*> Flags[] = {
1934  {HMOTF_ConstExtended, "hexagon-ext"}
1935  };
1936  return makeArrayRef(Flags);
1937 }
1938 
1941  const TargetRegisterClass *TRC;
1942  if (VT == MVT::i1) {
1943  TRC = &Hexagon::PredRegsRegClass;
1944  } else if (VT == MVT::i32 || VT == MVT::f32) {
1945  TRC = &Hexagon::IntRegsRegClass;
1946  } else if (VT == MVT::i64 || VT == MVT::f64) {
1947  TRC = &Hexagon::DoubleRegsRegClass;
1948  } else {
1949  llvm_unreachable("Cannot handle this register class");
1950  }
1951 
1952  unsigned NewReg = MRI.createVirtualRegister(TRC);
1953  return NewReg;
1954 }
1955 
1957  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1958 }
1959 
1961  const uint64_t F = MI.getDesc().TSFlags;
1963 }
1964 
1966  return getAddrMode(MI) == HexagonII::BaseImmOffset;
1967 }
1968 
1970  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
1971  !MI.getDesc().mayStore() &&
1972  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
1973  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
1974  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
1975 }
1976 
1977 // Return true if the instruction is a compund branch instruction.
1979  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1980 }
1981 
1982 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1983 // isFPImm and later getFPImm as well.
1985  const uint64_t F = MI.getDesc().TSFlags;
1987  if (isExtended) // Instruction must be extended.
1988  return true;
1989 
1990  unsigned isExtendable =
1992  if (!isExtendable)
1993  return false;
1994 
1995  if (MI.isCall())
1996  return false;
1997 
1998  short ExtOpNum = getCExtOpNum(MI);
1999  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2000  // Use MO operand flags to determine if MO
2001  // has the HMOTF_ConstExtended flag set.
2003  return true;
2004  // If this is a Machine BB address we are talking about, and it is
2005  // not marked as extended, say so.
2006  if (MO.isMBB())
2007  return false;
2008 
2009  // We could be using an instruction with an extendable immediate and shoehorn
2010  // a global address into it. If it is a global address it will be constant
2011  // extended. We do this for COMBINE.
2012  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2013  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2014  return true;
2015 
2016  // If the extendable operand is not 'Immediate' type, the instruction should
2017  // have 'isExtended' flag set.
2018  assert(MO.isImm() && "Extendable operand must be Immediate type");
2019 
2020  int MinValue = getMinValue(MI);
2021  int MaxValue = getMaxValue(MI);
2022  int ImmValue = MO.getImm();
2023 
2024  return (ImmValue < MinValue || ImmValue > MaxValue);
2025 }
2026 
2028  switch (MI.getOpcode()) {
2029  case Hexagon::L4_return:
2030  case Hexagon::L4_return_t:
2031  case Hexagon::L4_return_f:
2032  case Hexagon::L4_return_tnew_pnt:
2033  case Hexagon::L4_return_fnew_pnt:
2034  case Hexagon::L4_return_tnew_pt:
2035  case Hexagon::L4_return_fnew_pt:
2036  return true;
2037  }
2038  return false;
2039 }
2040 
2041 // Return true when ConsMI uses a register defined by ProdMI.
2043  const MachineInstr &ConsMI) const {
2044  if (!ProdMI.getDesc().getNumDefs())
2045  return false;
2046  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2047 
2052 
2053  parseOperands(ProdMI, DefsA, UsesA);
2054  parseOperands(ConsMI, DefsB, UsesB);
2055 
2056  for (auto &RegA : DefsA)
2057  for (auto &RegB : UsesB) {
2058  // True data dependency.
2059  if (RegA == RegB)
2060  return true;
2061 
2063  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2064  if (RegB == *SubRegs)
2065  return true;
2066 
2068  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2069  if (RegA == *SubRegs)
2070  return true;
2071  }
2072 
2073  return false;
2074 }
2075 
2076 // Returns true if the instruction is alread a .cur.
2078  switch (MI.getOpcode()) {
2079  case Hexagon::V6_vL32b_cur_pi:
2080  case Hexagon::V6_vL32b_cur_ai:
2081  return true;
2082  }
2083  return false;
2084 }
2085 
2086 // Returns true, if any one of the operands is a dot new
2087 // insn, whether it is predicated dot new or register dot new.
2089  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2090  return true;
2091 
2092  return false;
2093 }
2094 
2095 /// Symmetrical. See if these two instructions are fit for duplex pair.
2097  const MachineInstr &MIb) const {
2100  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2101 }
2102 
2104  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2105  return true;
2106 
2107  // Multiply
2108  unsigned SchedClass = MI.getDesc().getSchedClass();
2109  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2110 }
2111 
2112 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2113  return (Opcode == Hexagon::ENDLOOP0 ||
2114  Opcode == Hexagon::ENDLOOP1);
2115 }
2116 
2117 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2118  switch(OpType) {
2125  return true;
2126  default:
2127  return false;
2128  }
2129 }
2130 
2132  const MCInstrDesc &MID = MI.getDesc();
2133  const uint64_t F = MID.TSFlags;
2135  return true;
2136 
2137  // TODO: This is largely obsolete now. Will need to be removed
2138  // in consecutive patches.
2139  switch (MI.getOpcode()) {
2140  // PS_fi and PS_fia remain special cases.
2141  case Hexagon::PS_fi:
2142  case Hexagon::PS_fia:
2143  return true;
2144  default:
2145  return false;
2146  }
2147  return false;
2148 }
2149 
2150 // This returns true in two cases:
2151 // - The OP code itself indicates that this is an extended instruction.
2152 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2154  // First check if this is permanently extended op code.
2155  const uint64_t F = MI.getDesc().TSFlags;
2157  return true;
2158  // Use MO operand flags to determine if one of MI's operands
2159  // has HMOTF_ConstExtended flag set.
2160  for (const MachineOperand &MO : MI.operands())
2161  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2162  return true;
2163  return false;
2164 }
2165 
2167  unsigned Opcode = MI.getOpcode();
2168  const uint64_t F = get(Opcode).TSFlags;
2169  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2170 }
2171 
2172 // No V60 HVX VMEM with A_INDIRECT.
2174  const MachineInstr &J) const {
2175  if (!isHVXVec(I))
2176  return false;
2177  if (!I.mayLoad() && !I.mayStore())
2178  return false;
2179  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2180 }
2181 
2183  switch (MI.getOpcode()) {
2184  case Hexagon::J2_callr:
2185  case Hexagon::J2_callrf:
2186  case Hexagon::J2_callrt:
2187  case Hexagon::PS_call_nr:
2188  return true;
2189  }
2190  return false;
2191 }
2192 
2194  switch (MI.getOpcode()) {
2195  case Hexagon::L4_return:
2196  case Hexagon::L4_return_t:
2197  case Hexagon::L4_return_f:
2198  case Hexagon::L4_return_fnew_pnt:
2199  case Hexagon::L4_return_fnew_pt:
2200  case Hexagon::L4_return_tnew_pnt:
2201  case Hexagon::L4_return_tnew_pt:
2202  return true;
2203  }
2204  return false;
2205 }
2206 
2208  switch (MI.getOpcode()) {
2209  case Hexagon::J2_jumpr:
2210  case Hexagon::J2_jumprt:
2211  case Hexagon::J2_jumprf:
2212  case Hexagon::J2_jumprtnewpt:
2213  case Hexagon::J2_jumprfnewpt:
2214  case Hexagon::J2_jumprtnew:
2215  case Hexagon::J2_jumprfnew:
2216  return true;
2217  }
2218  return false;
2219 }
2220 
2221 // Return true if a given MI can accommodate given offset.
2222 // Use abs estimate as oppose to the exact number.
2223 // TODO: This will need to be changed to use MC level
2224 // definition of instruction extendable field size.
2226  unsigned offset) const {
2227  // This selection of jump instructions matches to that what
2228  // analyzeBranch can parse, plus NVJ.
2229  if (isNewValueJump(MI)) // r9:2
2230  return isInt<11>(offset);
2231 
2232  switch (MI.getOpcode()) {
2233  // Still missing Jump to address condition on register value.
2234  default:
2235  return false;
2236  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2237  case Hexagon::J2_call:
2238  case Hexagon::PS_call_nr:
2239  return isInt<24>(offset);
2240  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2241  case Hexagon::J2_jumpf:
2242  case Hexagon::J2_jumptnew:
2243  case Hexagon::J2_jumptnewpt:
2244  case Hexagon::J2_jumpfnew:
2245  case Hexagon::J2_jumpfnewpt:
2246  case Hexagon::J2_callt:
2247  case Hexagon::J2_callf:
2248  return isInt<17>(offset);
2249  case Hexagon::J2_loop0i:
2250  case Hexagon::J2_loop0iext:
2251  case Hexagon::J2_loop0r:
2252  case Hexagon::J2_loop0rext:
2253  case Hexagon::J2_loop1i:
2254  case Hexagon::J2_loop1iext:
2255  case Hexagon::J2_loop1r:
2256  case Hexagon::J2_loop1rext:
2257  return isInt<9>(offset);
2258  // TODO: Add all the compound branches here. Can we do this in Relation model?
2259  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2260  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2261  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2262  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2263  return isInt<11>(offset);
2264  }
2265 }
2266 
2268  const MachineInstr &ESMI) const {
2269  bool isLate = isLateResultInstr(LRMI);
2270  bool isEarly = isEarlySourceInstr(ESMI);
2271 
2272  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2273  LLVM_DEBUG(LRMI.dump());
2274  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2275  LLVM_DEBUG(ESMI.dump());
2276 
2277  if (isLate && isEarly) {
2278  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2279  return true;
2280  }
2281 
2282  return false;
2283 }
2284 
2286  switch (MI.getOpcode()) {
2287  case TargetOpcode::EXTRACT_SUBREG:
2288  case TargetOpcode::INSERT_SUBREG:
2289  case TargetOpcode::SUBREG_TO_REG:
2290  case TargetOpcode::REG_SEQUENCE:
2291  case TargetOpcode::IMPLICIT_DEF:
2292  case TargetOpcode::COPY:
2294  case TargetOpcode::PHI:
2295  return false;
2296  default:
2297  break;
2298  }
2299 
2300  unsigned SchedClass = MI.getDesc().getSchedClass();
2301  return !is_TC1(SchedClass);
2302 }
2303 
2305  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2306  // resource, but all operands can be received late like an ALU instruction.
2307  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2308 }
2309 
2311  unsigned Opcode = MI.getOpcode();
2312  return Opcode == Hexagon::J2_loop0i ||
2313  Opcode == Hexagon::J2_loop0r ||
2314  Opcode == Hexagon::J2_loop0iext ||
2315  Opcode == Hexagon::J2_loop0rext ||
2316  Opcode == Hexagon::J2_loop1i ||
2317  Opcode == Hexagon::J2_loop1r ||
2318  Opcode == Hexagon::J2_loop1iext ||
2319  Opcode == Hexagon::J2_loop1rext;
2320 }
2321 
2323  switch (MI.getOpcode()) {
2324  default: return false;
2325  case Hexagon::L4_iadd_memopw_io:
2326  case Hexagon::L4_isub_memopw_io:
2327  case Hexagon::L4_add_memopw_io:
2328  case Hexagon::L4_sub_memopw_io:
2329  case Hexagon::L4_and_memopw_io:
2330  case Hexagon::L4_or_memopw_io:
2331  case Hexagon::L4_iadd_memoph_io:
2332  case Hexagon::L4_isub_memoph_io:
2333  case Hexagon::L4_add_memoph_io:
2334  case Hexagon::L4_sub_memoph_io:
2335  case Hexagon::L4_and_memoph_io:
2336  case Hexagon::L4_or_memoph_io:
2337  case Hexagon::L4_iadd_memopb_io:
2338  case Hexagon::L4_isub_memopb_io:
2339  case Hexagon::L4_add_memopb_io:
2340  case Hexagon::L4_sub_memopb_io:
2341  case Hexagon::L4_and_memopb_io:
2342  case Hexagon::L4_or_memopb_io:
2343  case Hexagon::L4_ior_memopb_io:
2344  case Hexagon::L4_ior_memoph_io:
2345  case Hexagon::L4_ior_memopw_io:
2346  case Hexagon::L4_iand_memopb_io:
2347  case Hexagon::L4_iand_memoph_io:
2348  case Hexagon::L4_iand_memopw_io:
2349  return true;
2350  }
2351  return false;
2352 }
2353 
2355  const uint64_t F = MI.getDesc().TSFlags;
2357 }
2358 
2359 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2360  const uint64_t F = get(Opcode).TSFlags;
2362 }
2363 
2365  return isNewValueJump(MI) || isNewValueStore(MI);
2366 }
2367 
2369  return isNewValue(MI) && MI.isBranch();
2370 }
2371 
2372 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2373  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2374 }
2375 
2377  const uint64_t F = MI.getDesc().TSFlags;
2379 }
2380 
2381 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2382  const uint64_t F = get(Opcode).TSFlags;
2384 }
2385 
2386 // Returns true if a particular operand is extendable for an instruction.
2388  unsigned OperandNum) const {
2389  const uint64_t F = MI.getDesc().TSFlags;
2391  == OperandNum;
2392 }
2393 
2395  const uint64_t F = MI.getDesc().TSFlags;
2396  assert(isPredicated(MI));
2398 }
2399 
2400 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2401  const uint64_t F = get(Opcode).TSFlags;
2402  assert(isPredicated(Opcode));
2404 }
2405 
2407  const uint64_t F = MI.getDesc().TSFlags;
2408  return !((F >> HexagonII::PredicatedFalsePos) &
2410 }
2411 
2412 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2413  const uint64_t F = get(Opcode).TSFlags;
2414  // Make sure that the instruction is predicated.
2416  return !((F >> HexagonII::PredicatedFalsePos) &
2418 }
2419 
2420 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2421  const uint64_t F = get(Opcode).TSFlags;
2423 }
2424 
2425 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2426  const uint64_t F = get(Opcode).TSFlags;
2428 }
2429 
2430 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2431  const uint64_t F = get(Opcode).TSFlags;
2432  assert(get(Opcode).isBranch() &&
2433  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2434  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2435 }
2436 
2438  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2439  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2440  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2441  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2442 }
2443 
2445  switch (MI.getOpcode()) {
2446  // Byte
2447  case Hexagon::L2_loadrb_io:
2448  case Hexagon::L4_loadrb_ur:
2449  case Hexagon::L4_loadrb_ap:
2450  case Hexagon::L2_loadrb_pr:
2451  case Hexagon::L2_loadrb_pbr:
2452  case Hexagon::L2_loadrb_pi:
2453  case Hexagon::L2_loadrb_pci:
2454  case Hexagon::L2_loadrb_pcr:
2455  case Hexagon::L2_loadbsw2_io:
2456  case Hexagon::L4_loadbsw2_ur:
2457  case Hexagon::L4_loadbsw2_ap:
2458  case Hexagon::L2_loadbsw2_pr:
2459  case Hexagon::L2_loadbsw2_pbr:
2460  case Hexagon::L2_loadbsw2_pi:
2461  case Hexagon::L2_loadbsw2_pci:
2462  case Hexagon::L2_loadbsw2_pcr:
2463  case Hexagon::L2_loadbsw4_io:
2464  case Hexagon::L4_loadbsw4_ur:
2465  case Hexagon::L4_loadbsw4_ap:
2466  case Hexagon::L2_loadbsw4_pr:
2467  case Hexagon::L2_loadbsw4_pbr:
2468  case Hexagon::L2_loadbsw4_pi:
2469  case Hexagon::L2_loadbsw4_pci:
2470  case Hexagon::L2_loadbsw4_pcr:
2471  case Hexagon::L4_loadrb_rr:
2472  case Hexagon::L2_ploadrbt_io:
2473  case Hexagon::L2_ploadrbt_pi:
2474  case Hexagon::L2_ploadrbf_io:
2475  case Hexagon::L2_ploadrbf_pi:
2476  case Hexagon::L2_ploadrbtnew_io:
2477  case Hexagon::L2_ploadrbfnew_io:
2478  case Hexagon::L4_ploadrbt_rr:
2479  case Hexagon::L4_ploadrbf_rr:
2480  case Hexagon::L4_ploadrbtnew_rr:
2481  case Hexagon::L4_ploadrbfnew_rr:
2482  case Hexagon::L2_ploadrbtnew_pi:
2483  case Hexagon::L2_ploadrbfnew_pi:
2484  case Hexagon::L4_ploadrbt_abs:
2485  case Hexagon::L4_ploadrbf_abs:
2486  case Hexagon::L4_ploadrbtnew_abs:
2487  case Hexagon::L4_ploadrbfnew_abs:
2488  case Hexagon::L2_loadrbgp:
2489  // Half
2490  case Hexagon::L2_loadrh_io:
2491  case Hexagon::L4_loadrh_ur:
2492  case Hexagon::L4_loadrh_ap:
2493  case Hexagon::L2_loadrh_pr:
2494  case Hexagon::L2_loadrh_pbr:
2495  case Hexagon::L2_loadrh_pi:
2496  case Hexagon::L2_loadrh_pci:
2497  case Hexagon::L2_loadrh_pcr:
2498  case Hexagon::L4_loadrh_rr:
2499  case Hexagon::L2_ploadrht_io:
2500  case Hexagon::L2_ploadrht_pi:
2501  case Hexagon::L2_ploadrhf_io:
2502  case Hexagon::L2_ploadrhf_pi:
2503  case Hexagon::L2_ploadrhtnew_io:
2504  case Hexagon::L2_ploadrhfnew_io:
2505  case Hexagon::L4_ploadrht_rr:
2506  case Hexagon::L4_ploadrhf_rr:
2507  case Hexagon::L4_ploadrhtnew_rr:
2508  case Hexagon::L4_ploadrhfnew_rr:
2509  case Hexagon::L2_ploadrhtnew_pi:
2510  case Hexagon::L2_ploadrhfnew_pi:
2511  case Hexagon::L4_ploadrht_abs:
2512  case Hexagon::L4_ploadrhf_abs:
2513  case Hexagon::L4_ploadrhtnew_abs:
2514  case Hexagon::L4_ploadrhfnew_abs:
2515  case Hexagon::L2_loadrhgp:
2516  return true;
2517  default:
2518  return false;
2519  }
2520 }
2521 
2523  const uint64_t F = MI.getDesc().TSFlags;
2524  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2525 }
2526 
2528  switch (MI.getOpcode()) {
2529  case Hexagon::STriw_pred:
2530  case Hexagon::LDriw_pred:
2531  return true;
2532  default:
2533  return false;
2534  }
2535 }
2536 
2538  if (!MI.isBranch())
2539  return false;
2540 
2541  for (auto &Op : MI.operands())
2542  if (Op.isGlobal() || Op.isSymbol())
2543  return true;
2544  return false;
2545 }
2546 
2547 // Returns true when SU has a timing class TC1.
2549  unsigned SchedClass = MI.getDesc().getSchedClass();
2550  return is_TC1(SchedClass);
2551 }
2552 
2554  unsigned SchedClass = MI.getDesc().getSchedClass();
2555  return is_TC2(SchedClass);
2556 }
2557 
2559  unsigned SchedClass = MI.getDesc().getSchedClass();
2560  return is_TC2early(SchedClass);
2561 }
2562 
2564  unsigned SchedClass = MI.getDesc().getSchedClass();
2565  return is_TC4x(SchedClass);
2566 }
2567 
2568 // Schedule this ASAP.
2570  const MachineInstr &MI2) const {
2571  if (mayBeCurLoad(MI1)) {
2572  // if (result of SU is used in Next) return true;
2573  unsigned DstReg = MI1.getOperand(0).getReg();
2574  int N = MI2.getNumOperands();
2575  for (int I = 0; I < N; I++)
2576  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2577  return true;
2578  }
2579  if (mayBeNewStore(MI2))
2580  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2581  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2582  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2583  return true;
2584  return false;
2585 }
2586 
2588  const uint64_t V = getType(MI);
2590 }
2591 
2592 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2594  int Size = VT.getSizeInBits() / 8;
2595  if (Offset % Size != 0)
2596  return false;
2597  int Count = Offset / Size;
2598 
2599  switch (VT.getSimpleVT().SimpleTy) {
2600  // For scalars the auto-inc is s4
2601  case MVT::i8:
2602  case MVT::i16:
2603  case MVT::i32:
2604  case MVT::i64:
2605  case MVT::f32:
2606  case MVT::f64:
2607  case MVT::v2i16:
2608  case MVT::v2i32:
2609  case MVT::v4i8:
2610  case MVT::v4i16:
2611  case MVT::v8i8:
2612  return isInt<4>(Count);
2613  // For HVX vectors the auto-inc is s3
2614  case MVT::v64i8:
2615  case MVT::v32i16:
2616  case MVT::v16i32:
2617  case MVT::v8i64:
2618  case MVT::v128i8:
2619  case MVT::v64i16:
2620  case MVT::v32i32:
2621  case MVT::v16i64:
2622  return isInt<3>(Count);
2623  default:
2624  break;
2625  }
2626 
2627  llvm_unreachable("Not an valid type!");
2628 }
2629 
2630 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2631  const TargetRegisterInfo *TRI, bool Extend) const {
2632  // This function is to check whether the "Offset" is in the correct range of
2633  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2634  // inserted to calculate the final address. Due to this reason, the function
2635  // assumes that the "Offset" has correct alignment.
2636  // We used to assert if the offset was not properly aligned, however,
2637  // there are cases where a misaligned pointer recast can cause this
2638  // problem, and we need to allow for it. The front end warns of such
2639  // misaligns with respect to load size.
2640  switch (Opcode) {
2641  case Hexagon::PS_vstorerq_ai:
2642  case Hexagon::PS_vstorerw_ai:
2643  case Hexagon::PS_vstorerw_nt_ai:
2644  case Hexagon::PS_vloadrq_ai:
2645  case Hexagon::PS_vloadrw_ai:
2646  case Hexagon::PS_vloadrw_nt_ai:
2647  case Hexagon::V6_vL32b_ai:
2648  case Hexagon::V6_vS32b_ai:
2649  case Hexagon::V6_vL32b_nt_ai:
2650  case Hexagon::V6_vS32b_nt_ai:
2651  case Hexagon::V6_vL32Ub_ai:
2652  case Hexagon::V6_vS32Ub_ai: {
2653  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2654  assert(isPowerOf2_32(VectorSize));
2655  if (Offset & (VectorSize-1))
2656  return false;
2657  return isInt<4>(Offset >> Log2_32(VectorSize));
2658  }
2659 
2660  case Hexagon::J2_loop0i:
2661  case Hexagon::J2_loop1i:
2662  return isUInt<10>(Offset);
2663 
2664  case Hexagon::S4_storeirb_io:
2665  case Hexagon::S4_storeirbt_io:
2666  case Hexagon::S4_storeirbf_io:
2667  return isUInt<6>(Offset);
2668 
2669  case Hexagon::S4_storeirh_io:
2670  case Hexagon::S4_storeirht_io:
2671  case Hexagon::S4_storeirhf_io:
2672  return isShiftedUInt<6,1>(Offset);
2673 
2674  case Hexagon::S4_storeiri_io:
2675  case Hexagon::S4_storeirit_io:
2676  case Hexagon::S4_storeirif_io:
2677  return isShiftedUInt<6,2>(Offset);
2678  }
2679 
2680  if (Extend)
2681  return true;
2682 
2683  switch (Opcode) {
2684  case Hexagon::L2_loadri_io:
2685  case Hexagon::S2_storeri_io:
2686  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2687  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2688 
2689  case Hexagon::L2_loadrd_io:
2690  case Hexagon::S2_storerd_io:
2691  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2692  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2693 
2694  case Hexagon::L2_loadrh_io:
2695  case Hexagon::L2_loadruh_io:
2696  case Hexagon::S2_storerh_io:
2697  case Hexagon::S2_storerf_io:
2698  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2699  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2700 
2701  case Hexagon::L2_loadrb_io:
2702  case Hexagon::L2_loadrub_io:
2703  case Hexagon::S2_storerb_io:
2704  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2705  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2706 
2707  case Hexagon::A2_addi:
2708  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2709  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2710 
2711  case Hexagon::L4_iadd_memopw_io:
2712  case Hexagon::L4_isub_memopw_io:
2713  case Hexagon::L4_add_memopw_io:
2714  case Hexagon::L4_sub_memopw_io:
2715  case Hexagon::L4_and_memopw_io:
2716  case Hexagon::L4_or_memopw_io:
2717  return (0 <= Offset && Offset <= 255);
2718 
2719  case Hexagon::L4_iadd_memoph_io:
2720  case Hexagon::L4_isub_memoph_io:
2721  case Hexagon::L4_add_memoph_io:
2722  case Hexagon::L4_sub_memoph_io:
2723  case Hexagon::L4_and_memoph_io:
2724  case Hexagon::L4_or_memoph_io:
2725  return (0 <= Offset && Offset <= 127);
2726 
2727  case Hexagon::L4_iadd_memopb_io:
2728  case Hexagon::L4_isub_memopb_io:
2729  case Hexagon::L4_add_memopb_io:
2730  case Hexagon::L4_sub_memopb_io:
2731  case Hexagon::L4_and_memopb_io:
2732  case Hexagon::L4_or_memopb_io:
2733  return (0 <= Offset && Offset <= 63);
2734 
2735  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2736  // any size. Later pass knows how to handle it.
2737  case Hexagon::STriw_pred:
2738  case Hexagon::LDriw_pred:
2739  case Hexagon::STriw_ctr:
2740  case Hexagon::LDriw_ctr:
2741  return true;
2742 
2743  case Hexagon::PS_fi:
2744  case Hexagon::PS_fia:
2745  case Hexagon::INLINEASM:
2746  return true;
2747 
2748  case Hexagon::L2_ploadrbt_io:
2749  case Hexagon::L2_ploadrbf_io:
2750  case Hexagon::L2_ploadrubt_io:
2751  case Hexagon::L2_ploadrubf_io:
2752  case Hexagon::S2_pstorerbt_io:
2753  case Hexagon::S2_pstorerbf_io:
2754  return isUInt<6>(Offset);
2755 
2756  case Hexagon::L2_ploadrht_io:
2757  case Hexagon::L2_ploadrhf_io:
2758  case Hexagon::L2_ploadruht_io:
2759  case Hexagon::L2_ploadruhf_io:
2760  case Hexagon::S2_pstorerht_io:
2761  case Hexagon::S2_pstorerhf_io:
2762  return isShiftedUInt<6,1>(Offset);
2763 
2764  case Hexagon::L2_ploadrit_io:
2765  case Hexagon::L2_ploadrif_io:
2766  case Hexagon::S2_pstorerit_io:
2767  case Hexagon::S2_pstorerif_io:
2768  return isShiftedUInt<6,2>(Offset);
2769 
2770  case Hexagon::L2_ploadrdt_io:
2771  case Hexagon::L2_ploadrdf_io:
2772  case Hexagon::S2_pstorerdt_io:
2773  case Hexagon::S2_pstorerdf_io:
2774  return isShiftedUInt<6,3>(Offset);
2775  } // switch
2776 
2777  llvm_unreachable("No offset range is defined for this opcode. "
2778  "Please define it in the above switch statement!");
2779 }
2780 
2782  return isHVXVec(MI) && isAccumulator(MI);
2783 }
2784 
2786  const uint64_t F = get(MI.getOpcode()).TSFlags;
2787  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2788  return
2789  V == HexagonII::TypeCVI_VA ||
2791 }
2792 
2794  const MachineInstr &ConsMI) const {
2795  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2796  return true;
2797 
2798  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2799  return true;
2800 
2801  if (mayBeNewStore(ConsMI))
2802  return true;
2803 
2804  return false;
2805 }
2806 
2808  switch (MI.getOpcode()) {
2809  // Byte
2810  case Hexagon::L2_loadrub_io:
2811  case Hexagon::L4_loadrub_ur:
2812  case Hexagon::L4_loadrub_ap:
2813  case Hexagon::L2_loadrub_pr:
2814  case Hexagon::L2_loadrub_pbr:
2815  case Hexagon::L2_loadrub_pi:
2816  case Hexagon::L2_loadrub_pci:
2817  case Hexagon::L2_loadrub_pcr:
2818  case Hexagon::L2_loadbzw2_io:
2819  case Hexagon::L4_loadbzw2_ur:
2820  case Hexagon::L4_loadbzw2_ap:
2821  case Hexagon::L2_loadbzw2_pr:
2822  case Hexagon::L2_loadbzw2_pbr:
2823  case Hexagon::L2_loadbzw2_pi:
2824  case Hexagon::L2_loadbzw2_pci:
2825  case Hexagon::L2_loadbzw2_pcr:
2826  case Hexagon::L2_loadbzw4_io:
2827  case Hexagon::L4_loadbzw4_ur:
2828  case Hexagon::L4_loadbzw4_ap:
2829  case Hexagon::L2_loadbzw4_pr:
2830  case Hexagon::L2_loadbzw4_pbr:
2831  case Hexagon::L2_loadbzw4_pi:
2832  case Hexagon::L2_loadbzw4_pci:
2833  case Hexagon::L2_loadbzw4_pcr:
2834  case Hexagon::L4_loadrub_rr:
2835  case Hexagon::L2_ploadrubt_io:
2836  case Hexagon::L2_ploadrubt_pi:
2837  case Hexagon::L2_ploadrubf_io:
2838  case Hexagon::L2_ploadrubf_pi:
2839  case Hexagon::L2_ploadrubtnew_io:
2840  case Hexagon::L2_ploadrubfnew_io:
2841  case Hexagon::L4_ploadrubt_rr:
2842  case Hexagon::L4_ploadrubf_rr:
2843  case Hexagon::L4_ploadrubtnew_rr:
2844  case Hexagon::L4_ploadrubfnew_rr:
2845  case Hexagon::L2_ploadrubtnew_pi:
2846  case Hexagon::L2_ploadrubfnew_pi:
2847  case Hexagon::L4_ploadrubt_abs:
2848  case Hexagon::L4_ploadrubf_abs:
2849  case Hexagon::L4_ploadrubtnew_abs:
2850  case Hexagon::L4_ploadrubfnew_abs:
2851  case Hexagon::L2_loadrubgp:
2852  // Half
2853  case Hexagon::L2_loadruh_io:
2854  case Hexagon::L4_loadruh_ur:
2855  case Hexagon::L4_loadruh_ap:
2856  case Hexagon::L2_loadruh_pr:
2857  case Hexagon::L2_loadruh_pbr:
2858  case Hexagon::L2_loadruh_pi:
2859  case Hexagon::L2_loadruh_pci:
2860  case Hexagon::L2_loadruh_pcr:
2861  case Hexagon::L4_loadruh_rr:
2862  case Hexagon::L2_ploadruht_io:
2863  case Hexagon::L2_ploadruht_pi:
2864  case Hexagon::L2_ploadruhf_io:
2865  case Hexagon::L2_ploadruhf_pi:
2866  case Hexagon::L2_ploadruhtnew_io:
2867  case Hexagon::L2_ploadruhfnew_io:
2868  case Hexagon::L4_ploadruht_rr:
2869  case Hexagon::L4_ploadruhf_rr:
2870  case Hexagon::L4_ploadruhtnew_rr:
2871  case Hexagon::L4_ploadruhfnew_rr:
2872  case Hexagon::L2_ploadruhtnew_pi:
2873  case Hexagon::L2_ploadruhfnew_pi:
2874  case Hexagon::L4_ploadruht_abs:
2875  case Hexagon::L4_ploadruhf_abs:
2876  case Hexagon::L4_ploadruhtnew_abs:
2877  case Hexagon::L4_ploadruhfnew_abs:
2878  case Hexagon::L2_loadruhgp:
2879  return true;
2880  default:
2881  return false;
2882  }
2883 }
2884 
2885 // Add latency to instruction.
2887  const MachineInstr &MI2) const {
2888  if (isHVXVec(MI1) && isHVXVec(MI2))
2889  if (!isVecUsableNextPacket(MI1, MI2))
2890  return true;
2891  return false;
2892 }
2893 
2894 /// Get the base register and byte offset of a load/store instr.
2896  MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset,
2897  const TargetRegisterInfo *TRI) const {
2898  unsigned AccessSize = 0;
2899  BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2900  assert((!BaseOp || BaseOp->isReg()) &&
2901  "getMemOperandWithOffset only supports base "
2902  "operands of type register.");
2903  return BaseOp != nullptr;
2904 }
2905 
2906 /// Can these instructions execute at the same time in a bundle.
2908  const MachineInstr &Second) const {
2909  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2910  const MachineOperand &Op = Second.getOperand(0);
2911  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2912  return true;
2913  }
2914  if (DisableNVSchedule)
2915  return false;
2916  if (mayBeNewStore(Second)) {
2917  // Make sure the definition of the first instruction is the value being
2918  // stored.
2919  const MachineOperand &Stored =
2920  Second.getOperand(Second.getNumOperands() - 1);
2921  if (!Stored.isReg())
2922  return false;
2923  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2924  const MachineOperand &Op = First.getOperand(i);
2925  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2926  return true;
2927  }
2928  }
2929  return false;
2930 }
2931 
2933  unsigned Opc = CallMI.getOpcode();
2934  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2935 }
2936 
2938  for (auto &I : *B)
2939  if (I.isEHLabel())
2940  return true;
2941  return false;
2942 }
2943 
2944 // Returns true if an instruction can be converted into a non-extended
2945 // equivalent instruction.
2947  short NonExtOpcode;
2948  // Check if the instruction has a register form that uses register in place
2949  // of the extended operand, if so return that as the non-extended form.
2950  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2951  return true;
2952 
2953  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2954  // Check addressing mode and retrieve non-ext equivalent instruction.
2955 
2956  switch (getAddrMode(MI)) {
2957  case HexagonII::Absolute:
2958  // Load/store with absolute addressing mode can be converted into
2959  // base+offset mode.
2960  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2961  break;
2963  // Load/store with base+offset addressing mode can be converted into
2964  // base+register offset addressing mode. However left shift operand should
2965  // be set to 0.
2966  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
2967  break;
2969  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
2970  break;
2971  default:
2972  return false;
2973  }
2974  if (NonExtOpcode < 0)
2975  return false;
2976  return true;
2977  }
2978  return false;
2979 }
2980 
2982  return Hexagon::getRealHWInstr(MI.getOpcode(),
2983  Hexagon::InstrType_Pseudo) >= 0;
2984 }
2985 
2987  const {
2989  while (I != E) {
2990  if (I->isBarrier())
2991  return true;
2992  ++I;
2993  }
2994  return false;
2995 }
2996 
2997 // Returns true, if a LD insn can be promoted to a cur load.
2999  const uint64_t F = MI.getDesc().TSFlags;
3001  Subtarget.hasV60Ops();
3002 }
3003 
3004 // Returns true, if a ST insn can be promoted to a new-value store.
3006  if (MI.mayStore() && !Subtarget.useNewValueStores())
3007  return false;
3008 
3009  const uint64_t F = MI.getDesc().TSFlags;
3011 }
3012 
3014  const MachineInstr &ConsMI) const {
3015  // There is no stall when ProdMI is not a V60 vector.
3016  if (!isHVXVec(ProdMI))
3017  return false;
3018 
3019  // There is no stall when ProdMI and ConsMI are not dependent.
3020  if (!isDependent(ProdMI, ConsMI))
3021  return false;
3022 
3023  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3024  // are scheduled in consecutive packets.
3025  if (isVecUsableNextPacket(ProdMI, ConsMI))
3026  return false;
3027 
3028  return true;
3029 }
3030 
3033  // There is no stall when I is not a V60 vector.
3034  if (!isHVXVec(MI))
3035  return false;
3036 
3038  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3039 
3040  if (!MII->isBundle())
3041  return producesStall(*MII, MI);
3042 
3043  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3044  const MachineInstr &J = *MII;
3045  if (producesStall(J, MI))
3046  return true;
3047  }
3048  return false;
3049 }
3050 
3052  unsigned PredReg) const {
3053  for (const MachineOperand &MO : MI.operands()) {
3054  // Predicate register must be explicitly defined.
3055  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3056  return false;
3057  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3058  return false;
3059  }
3060 
3061  // Instruction that produce late predicate cannot be used as sources of
3062  // dot-new.
3063  switch (MI.getOpcode()) {
3064  case Hexagon::A4_addp_c:
3065  case Hexagon::A4_subp_c:
3066  case Hexagon::A4_tlbmatch:
3067  case Hexagon::A5_ACS:
3068  case Hexagon::F2_sfinvsqrta:
3069  case Hexagon::F2_sfrecipa:
3070  case Hexagon::J2_endloop0:
3071  case Hexagon::J2_endloop01:
3072  case Hexagon::J2_ploop1si:
3073  case Hexagon::J2_ploop1sr:
3074  case Hexagon::J2_ploop2si:
3075  case Hexagon::J2_ploop2sr:
3076  case Hexagon::J2_ploop3si:
3077  case Hexagon::J2_ploop3sr:
3078  case Hexagon::S2_cabacdecbin:
3079  case Hexagon::S2_storew_locked:
3080  case Hexagon::S4_stored_locked:
3081  return false;
3082  }
3083  return true;
3084 }
3085 
3086 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3087  return Opcode == Hexagon::J2_jumpt ||
3088  Opcode == Hexagon::J2_jumptpt ||
3089  Opcode == Hexagon::J2_jumpf ||
3090  Opcode == Hexagon::J2_jumpfpt ||
3091  Opcode == Hexagon::J2_jumptnew ||
3092  Opcode == Hexagon::J2_jumpfnew ||
3093  Opcode == Hexagon::J2_jumptnewpt ||
3094  Opcode == Hexagon::J2_jumpfnewpt;
3095 }
3096 
3098  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3099  return false;
3100  return !isPredicatedTrue(Cond[0].getImm());
3101 }
3102 
3104  const uint64_t F = MI.getDesc().TSFlags;
3106 }
3107 
3108 // Returns the base register in a memory access (load/store). The offset is
3109 // returned in Offset and the access size is returned in AccessSize.
3110 // If the base operand has a subregister or the offset field does not contain
3111 // an immediate value, return nullptr.
3113  int64_t &Offset,
3114  unsigned &AccessSize) const {
3115  // Return if it is not a base+offset type instruction or a MemOp.
3118  !isMemOp(MI) && !isPostIncrement(MI))
3119  return nullptr;
3120 
3121  AccessSize = getMemAccessSize(MI);
3122 
3123  unsigned BasePos = 0, OffsetPos = 0;
3124  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3125  return nullptr;
3126 
3127  // Post increment updates its EA after the mem access,
3128  // so we need to treat its offset as zero.
3129  if (isPostIncrement(MI)) {
3130  Offset = 0;
3131  } else {
3132  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3133  if (!OffsetOp.isImm())
3134  return nullptr;
3135  Offset = OffsetOp.getImm();
3136  }
3137 
3138  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3139  if (BaseOp.getSubReg() != 0)
3140  return nullptr;
3141  return &const_cast<MachineOperand&>(BaseOp);
3142 }
3143 
3144 /// Return the position of the base and offset operands for this instruction.
3146  unsigned &BasePos, unsigned &OffsetPos) const {
3147  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3148  return false;
3149 
3150  // Deal with memops first.
3151  if (isMemOp(MI)) {
3152  BasePos = 0;
3153  OffsetPos = 1;
3154  } else if (MI.mayStore()) {
3155  BasePos = 0;
3156  OffsetPos = 1;
3157  } else if (MI.mayLoad()) {
3158  BasePos = 1;
3159  OffsetPos = 2;
3160  } else
3161  return false;
3162 
3163  if (isPredicated(MI)) {
3164  BasePos++;
3165  OffsetPos++;
3166  }
3167  if (isPostIncrement(MI)) {
3168  BasePos++;
3169  OffsetPos++;
3170  }
3171 
3172  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3173  return false;
3174 
3175  return true;
3176 }
3177 
3178 // Inserts branching instructions in reverse order of their occurrence.
3179 // e.g. jump_t t1 (i1)
3180 // jump t2 (i2)
3181 // Jumpers = {i2, i1}
3183  MachineBasicBlock& MBB) const {
3185  // If the block has no terminators, it just falls into the block after it.
3187  if (I == MBB.instr_begin())
3188  return Jumpers;
3189 
3190  // A basic block may looks like this:
3191  //
3192  // [ insn
3193  // EH_LABEL
3194  // insn
3195  // insn
3196  // insn
3197  // EH_LABEL
3198  // insn ]
3199  //
3200  // It has two succs but does not have a terminator
3201  // Don't know how to handle it.
3202  do {
3203  --I;
3204  if (I->isEHLabel())
3205  return Jumpers;
3206  } while (I != MBB.instr_begin());
3207 
3208  I = MBB.instr_end();
3209  --I;
3210 
3211  while (I->isDebugInstr()) {
3212  if (I == MBB.instr_begin())
3213  return Jumpers;
3214  --I;
3215  }
3216  if (!isUnpredicatedTerminator(*I))
3217  return Jumpers;
3218 
3219  // Get the last instruction in the block.
3220  MachineInstr *LastInst = &*I;
3221  Jumpers.push_back(LastInst);
3222  MachineInstr *SecondLastInst = nullptr;
3223  // Find one more terminator if present.
3224  do {
3225  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3226  if (!SecondLastInst) {
3227  SecondLastInst = &*I;
3228  Jumpers.push_back(SecondLastInst);
3229  } else // This is a third branch.
3230  return Jumpers;
3231  }
3232  if (I == MBB.instr_begin())
3233  break;
3234  --I;
3235  } while (true);
3236  return Jumpers;
3237 }
3238 
3239 // Returns Operand Index for the constant extended instruction.
3241  const uint64_t F = MI.getDesc().TSFlags;
3243 }
3244 
3245 // See if instruction could potentially be a duplex candidate.
3246 // If so, return its group. Zero otherwise.
3248  const MachineInstr &MI) const {
3249  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3250 
3251  switch (MI.getOpcode()) {
3252  default:
3253  return HexagonII::HCG_None;
3254  //
3255  // Compound pairs.
3256  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3257  // "Rd16=#U6 ; jump #r9:2"
3258  // "Rd16=Rs16 ; jump #r9:2"
3259  //
3260  case Hexagon::C2_cmpeq:
3261  case Hexagon::C2_cmpgt:
3262  case Hexagon::C2_cmpgtu:
3263  DstReg = MI.getOperand(0).getReg();
3264  Src1Reg = MI.getOperand(1).getReg();
3265  Src2Reg = MI.getOperand(2).getReg();
3266  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3267  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3268  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3269  return HexagonII::HCG_A;
3270  break;
3271  case Hexagon::C2_cmpeqi:
3272  case Hexagon::C2_cmpgti:
3273  case Hexagon::C2_cmpgtui:
3274  // P0 = cmp.eq(Rs,#u2)
3275  DstReg = MI.getOperand(0).getReg();
3276  SrcReg = MI.getOperand(1).getReg();
3277  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3278  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3279  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3280  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3281  (MI.getOperand(2).getImm() == -1)))
3282  return HexagonII::HCG_A;
3283  break;
3284  case Hexagon::A2_tfr:
3285  // Rd = Rs
3286  DstReg = MI.getOperand(0).getReg();
3287  SrcReg = MI.getOperand(1).getReg();
3288  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3289  return HexagonII::HCG_A;
3290  break;
3291  case Hexagon::A2_tfrsi:
3292  // Rd = #u6
3293  // Do not test for #u6 size since the const is getting extended
3294  // regardless and compound could be formed.
3295  DstReg = MI.getOperand(0).getReg();
3296  if (isIntRegForSubInst(DstReg))
3297  return HexagonII::HCG_A;
3298  break;
3299  case Hexagon::S2_tstbit_i:
3300  DstReg = MI.getOperand(0).getReg();
3301  Src1Reg = MI.getOperand(1).getReg();
3302  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3303  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3304  MI.getOperand(2).isImm() &&
3305  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3306  return HexagonII::HCG_A;
3307  break;
3308  // The fact that .new form is used pretty much guarantees
3309  // that predicate register will match. Nevertheless,
3310  // there could be some false positives without additional
3311  // checking.
3312  case Hexagon::J2_jumptnew:
3313  case Hexagon::J2_jumpfnew:
3314  case Hexagon::J2_jumptnewpt:
3315  case Hexagon::J2_jumpfnewpt:
3316  Src1Reg = MI.getOperand(0).getReg();
3317  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3318  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3319  return HexagonII::HCG_B;
3320  break;
3321  // Transfer and jump:
3322  // Rd=#U6 ; jump #r9:2
3323  // Rd=Rs ; jump #r9:2
3324  // Do not test for jump range here.
3325  case Hexagon::J2_jump:
3326  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3327  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3328  return HexagonII::HCG_C;
3329  }
3330 
3331  return HexagonII::HCG_None;
3332 }
3333 
3334 // Returns -1 when there is no opcode found.
3336  const MachineInstr &GB) const {
3339  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3340  (GB.getOpcode() != Hexagon::J2_jumptnew))
3341  return -1u;
3342  unsigned DestReg = GA.getOperand(0).getReg();
3343  if (!GB.readsRegister(DestReg))
3344  return -1u;
3345  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3346  return -1u;
3347  // The value compared against must be either u5 or -1.
3348  const MachineOperand &CmpOp = GA.getOperand(2);
3349  if (!CmpOp.isImm())
3350  return -1u;
3351  int V = CmpOp.getImm();
3352  if (V == -1)
3353  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3354  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3355  if (!isUInt<5>(V))
3356  return -1u;
3357  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3358  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3359 }
3360 
3361 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3362  enum Hexagon::PredSense inPredSense;
3363  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3364  Hexagon::PredSense_true;
3365  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3366  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3367  return CondOpcode;
3368 
3369  llvm_unreachable("Unexpected predicable instruction");
3370 }
3371 
3372 // Return the cur value instruction for a given store.
3374  switch (MI.getOpcode()) {
3375  default: llvm_unreachable("Unknown .cur type");
3376  case Hexagon::V6_vL32b_pi:
3377  return Hexagon::V6_vL32b_cur_pi;
3378  case Hexagon::V6_vL32b_ai:
3379  return Hexagon::V6_vL32b_cur_ai;
3380  case Hexagon::V6_vL32b_nt_pi:
3381  return Hexagon::V6_vL32b_nt_cur_pi;
3382  case Hexagon::V6_vL32b_nt_ai:
3383  return Hexagon::V6_vL32b_nt_cur_ai;
3384  }
3385  return 0;
3386 }
3387 
3388 // Return the regular version of the .cur instruction.
3390  switch (MI.getOpcode()) {
3391  default: llvm_unreachable("Unknown .cur type");
3392  case Hexagon::V6_vL32b_cur_pi:
3393  return Hexagon::V6_vL32b_pi;
3394  case Hexagon::V6_vL32b_cur_ai:
3395  return Hexagon::V6_vL32b_ai;
3396  case Hexagon::V6_vL32b_nt_cur_pi:
3397  return Hexagon::V6_vL32b_nt_pi;
3398  case Hexagon::V6_vL32b_nt_cur_ai:
3399  return Hexagon::V6_vL32b_nt_ai;
3400  }
3401  return 0;
3402 }
3403 
3404 // The diagram below shows the steps involved in the conversion of a predicated
3405 // store instruction to its .new predicated new-value form.
3406 //
3407 // Note: It doesn't include conditional new-value stores as they can't be
3408 // converted to .new predicate.
3409 //
3410 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3411 // ^ ^
3412 // / \ (not OK. it will cause new-value store to be
3413 // / X conditional on p0.new while R2 producer is
3414 // / \ on p0)
3415 // / \.
3416 // p.new store p.old NV store
3417 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3418 // ^ ^
3419 // \ /
3420 // \ /
3421 // \ /
3422 // p.old store
3423 // [if (p0)memw(R0+#0)=R2]
3424 //
3425 // The following set of instructions further explains the scenario where
3426 // conditional new-value store becomes invalid when promoted to .new predicate
3427 // form.
3428 //
3429 // { 1) if (p0) r0 = add(r1, r2)
3430 // 2) p0 = cmp.eq(r3, #0) }
3431 //
3432 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3433 // the first two instructions because in instr 1, r0 is conditional on old value
3434 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3435 // is not valid for new-value stores.
3436 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3437 // from the "Conditional Store" list. Because a predicated new value store
3438 // would NOT be promoted to a double dot new store. See diagram below:
3439 // This function returns yes for those stores that are predicated but not
3440 // yet promoted to predicate dot new instructions.
3441 //
3442 // +---------------------+
3443 // /-----| if (p0) memw(..)=r0 |---------\~
3444 // || +---------------------+ ||
3445 // promote || /\ /\ || promote
3446 // || /||\ /||\ ||
3447 // \||/ demote || \||/
3448 // \/ || || \/
3449 // +-------------------------+ || +-------------------------+
3450 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3451 // +-------------------------+ || +-------------------------+
3452 // || || ||
3453 // || demote \||/
3454 // promote || \/ NOT possible
3455 // || || /\~
3456 // \||/ || /||\~
3457 // \/ || ||
3458 // +-----------------------------+
3459 // | if (p0.new) memw(..)=r0.new |
3460 // +-----------------------------+
3461 // Double Dot New Store
3462 //
3463 // Returns the most basic instruction for the .new predicated instructions and
3464 // new-value stores.
3465 // For example, all of the following instructions will be converted back to the
3466 // same instruction:
3467 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3468 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3469 // 3) if (p0.new) memw(R0+#0) = R1 --->
3470 //
3471 // To understand the translation of instruction 1 to its original form, consider
3472 // a packet with 3 instructions.
3473 // { p0 = cmp.eq(R0,R1)
3474 // if (p0.new) R2 = add(R3, R4)
3475 // R5 = add (R3, R1)
3476 // }
3477 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3478 //
3479 // This instruction can be part of the previous packet only if both p0 and R2
3480 // are promoted to .new values. This promotion happens in steps, first
3481 // predicate register is promoted to .new and in the next iteration R2 is
3482 // promoted. Therefore, in case of dependence check failure (due to R5) during
3483 // next iteration, it should be converted back to its most basic form.
3484 
3485 // Return the new value instruction for a given store.
3487  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3488  if (NVOpcode >= 0) // Valid new-value store instruction.
3489  return NVOpcode;
3490 
3491  switch (MI.getOpcode()) {
3492  default:
3493  report_fatal_error(std::string("Unknown .new type: ") +
3494  std::to_string(MI.getOpcode()));
3495  case Hexagon::S4_storerb_ur:
3496  return Hexagon::S4_storerbnew_ur;
3497 
3498  case Hexagon::S2_storerb_pci:
3499  return Hexagon::S2_storerb_pci;
3500 
3501  case Hexagon::S2_storeri_pci:
3502  return Hexagon::S2_storeri_pci;
3503 
3504  case Hexagon::S2_storerh_pci:
3505  return Hexagon::S2_storerh_pci;
3506 
3507  case Hexagon::S2_storerd_pci:
3508  return Hexagon::S2_storerd_pci;
3509 
3510  case Hexagon::S2_storerf_pci:
3511  return Hexagon::S2_storerf_pci;
3512 
3513  case Hexagon::V6_vS32b_ai:
3514  return Hexagon::V6_vS32b_new_ai;
3515 
3516  case Hexagon::V6_vS32b_pi:
3517  return Hexagon::V6_vS32b_new_pi;
3518  }
3519  return 0;
3520 }
3521 
3522 // Returns the opcode to use when converting MI, which is a conditional jump,
3523 // into a conditional instruction which uses the .new value of the predicate.
3524 // We also use branch probabilities to add a hint to the jump.
3525 // If MBPI is null, all edges will be treated as equally likely for the
3526 // purposes of establishing a predication hint.
3528  const MachineBranchProbabilityInfo *MBPI) const {
3529  // We assume that block can have at most two successors.
3530  const MachineBasicBlock *Src = MI.getParent();
3531  const MachineOperand &BrTarget = MI.getOperand(1);
3532  bool Taken = false;
3533  const BranchProbability OneHalf(1, 2);
3534 
3535  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3536  const MachineBasicBlock *Dst) {
3537  if (MBPI)
3538  return MBPI->getEdgeProbability(Src, Dst);
3539  return BranchProbability(1, Src->succ_size());
3540  };
3541 
3542  if (BrTarget.isMBB()) {
3543  const MachineBasicBlock *Dst = BrTarget.getMBB();
3544  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3545  } else {
3546  // The branch target is not a basic block (most likely a function).
3547  // Since BPI only gives probabilities for targets that are basic blocks,
3548  // try to identify another target of this branch (potentially a fall-
3549  // -through) and check the probability of that target.
3550  //
3551  // The only handled branch combinations are:
3552  // - one conditional branch,
3553  // - one conditional branch followed by one unconditional branch.
3554  // Otherwise, assume not-taken.
3556  const MachineBasicBlock &B = *MI.getParent();
3557  bool SawCond = false, Bad = false;
3558  for (const MachineInstr &I : B) {
3559  if (!I.isBranch())
3560  continue;
3561  if (I.isConditionalBranch()) {
3562  SawCond = true;
3563  if (&I != &MI) {
3564  Bad = true;
3565  break;
3566  }
3567  }
3568  if (I.isUnconditionalBranch() && !SawCond) {
3569  Bad = true;
3570  break;
3571  }
3572  }
3573  if (!Bad) {
3575  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3576  if (NextIt == B.instr_end()) {
3577  // If this branch is the last, look for the fall-through block.
3578  for (const MachineBasicBlock *SB : B.successors()) {
3579  if (!B.isLayoutSuccessor(SB))
3580  continue;
3581  Taken = getEdgeProbability(Src, SB) < OneHalf;
3582  break;
3583  }
3584  } else {
3585  assert(NextIt->isUnconditionalBranch());
3586  // Find the first MBB operand and assume it's the target.
3587  const MachineBasicBlock *BT = nullptr;
3588  for (const MachineOperand &Op : NextIt->operands()) {
3589  if (!Op.isMBB())
3590  continue;
3591  BT = Op.getMBB();
3592  break;
3593  }
3594  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3595  }
3596  } // if (!Bad)
3597  }
3598 
3599  // The Taken flag should be set to something reasonable by this point.
3600 
3601  switch (MI.getOpcode()) {
3602  case Hexagon::J2_jumpt:
3603  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3604  case Hexagon::J2_jumpf:
3605  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3606 
3607  default:
3608  llvm_unreachable("Unexpected jump instruction.");
3609  }
3610 }
3611 
3612 // Return .new predicate version for an instruction.
3614  const MachineBranchProbabilityInfo *MBPI) const {
3615  switch (MI.getOpcode()) {
3616  // Condtional Jumps
3617  case Hexagon::J2_jumpt:
3618  case Hexagon::J2_jumpf:
3619  return getDotNewPredJumpOp(MI, MBPI);
3620  }
3621 
3622  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3623  if (NewOpcode >= 0)
3624  return NewOpcode;
3625  return 0;
3626 }
3627 
3629  int NewOp = MI.getOpcode();
3630  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3631  NewOp = Hexagon::getPredOldOpcode(NewOp);
3632  // All Hexagon architectures have prediction bits on dot-new branches,
3633  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3634  // to pick the right opcode when converting back to dot-old.
3635  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3636  switch (NewOp) {
3637  case Hexagon::J2_jumptpt:
3638  NewOp = Hexagon::J2_jumpt;
3639  break;
3640  case Hexagon::J2_jumpfpt:
3641  NewOp = Hexagon::J2_jumpf;
3642  break;
3643  case Hexagon::J2_jumprtpt:
3644  NewOp = Hexagon::J2_jumprt;
3645  break;
3646  case Hexagon::J2_jumprfpt:
3647  NewOp = Hexagon::J2_jumprf;
3648  break;
3649  }
3650  }
3651  assert(NewOp >= 0 &&
3652  "Couldn't change predicate new instruction to its old form.");
3653  }
3654 
3655  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3656  NewOp = Hexagon::getNonNVStore(NewOp);
3657  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3658  }
3659 
3660  if (Subtarget.hasV60Ops())
3661  return NewOp;
3662 
3663  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3664  switch (NewOp) {
3665  case Hexagon::J2_jumpfpt:
3666  return Hexagon::J2_jumpf;
3667  case Hexagon::J2_jumptpt:
3668  return Hexagon::J2_jumpt;
3669  case Hexagon::J2_jumprfpt:
3670  return Hexagon::J2_jumprf;
3671  case Hexagon::J2_jumprtpt:
3672  return Hexagon::J2_jumprt;
3673  }
3674  return NewOp;
3675 }
3676 
3677 // See if instruction could potentially be a duplex candidate.
3678 // If so, return its group. Zero otherwise.
3680  const MachineInstr &MI) const {
3681  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3682  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3683 
3684  switch (MI.getOpcode()) {
3685  default:
3686  return HexagonII::HSIG_None;
3687  //
3688  // Group L1:
3689  //
3690  // Rd = memw(Rs+#u4:2)
3691  // Rd = memub(Rs+#u4:0)
3692  case Hexagon::L2_loadri_io:
3693  DstReg = MI.getOperand(0).getReg();
3694  SrcReg = MI.getOperand(1).getReg();
3695  // Special case this one from Group L2.
3696  // Rd = memw(r29+#u5:2)
3697  if (isIntRegForSubInst(DstReg)) {
3698  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3699  HRI.getStackRegister() == SrcReg &&
3700  MI.getOperand(2).isImm() &&
3701  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3702  return HexagonII::HSIG_L2;
3703  // Rd = memw(Rs+#u4:2)
3704  if (isIntRegForSubInst(SrcReg) &&
3705  (MI.getOperand(2).isImm() &&
3706  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3707  return HexagonII::HSIG_L1;
3708  }
3709  break;
3710  case Hexagon::L2_loadrub_io:
3711  // Rd = memub(Rs+#u4:0)
3712  DstReg = MI.getOperand(0).getReg();
3713  SrcReg = MI.getOperand(1).getReg();
3714  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3715  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3716  return HexagonII::HSIG_L1;
3717  break;
3718  //
3719  // Group L2:
3720  //
3721  // Rd = memh/memuh(Rs+#u3:1)
3722  // Rd = memb(Rs+#u3:0)
3723  // Rd = memw(r29+#u5:2) - Handled above.
3724  // Rdd = memd(r29+#u5:3)
3725  // deallocframe
3726  // [if ([!]p0[.new])] dealloc_return
3727  // [if ([!]p0[.new])] jumpr r31
3728  case Hexagon::L2_loadrh_io:
3729  case Hexagon::L2_loadruh_io:
3730  // Rd = memh/memuh(Rs+#u3:1)
3731  DstReg = MI.getOperand(0).getReg();
3732  SrcReg = MI.getOperand(1).getReg();
3733  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3734  MI.getOperand(2).isImm() &&
3735  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3736  return HexagonII::HSIG_L2;
3737  break;
3738  case Hexagon::L2_loadrb_io:
3739  // Rd = memb(Rs+#u3:0)
3740  DstReg = MI.getOperand(0).getReg();
3741  SrcReg = MI.getOperand(1).getReg();
3742  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3743  MI.getOperand(2).isImm() &&
3744  isUInt<3>(MI.getOperand(2).getImm()))
3745  return HexagonII::HSIG_L2;
3746  break;
3747  case Hexagon::L2_loadrd_io:
3748  // Rdd = memd(r29+#u5:3)
3749  DstReg = MI.getOperand(0).getReg();
3750  SrcReg = MI.getOperand(1).getReg();
3751  if (isDblRegForSubInst(DstReg, HRI) &&
3752  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3753  HRI.getStackRegister() == SrcReg &&
3754  MI.getOperand(2).isImm() &&
3755  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3756  return HexagonII::HSIG_L2;
3757  break;
3758  // dealloc_return is not documented in Hexagon Manual, but marked
3759  // with A_SUBINSN attribute in iset_v4classic.py.
3760  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3761  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3762  case Hexagon::L4_return:
3763  case Hexagon::L2_deallocframe:
3764  return HexagonII::HSIG_L2;
3765  case Hexagon::EH_RETURN_JMPR:
3766  case Hexagon::PS_jmpret:
3767  case Hexagon::SL2_jumpr31:
3768  // jumpr r31
3769  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3770  DstReg = MI.getOperand(0).getReg();
3771  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3772  return HexagonII::HSIG_L2;
3773  break;
3774  case Hexagon::PS_jmprett:
3775  case Hexagon::PS_jmpretf:
3776  case Hexagon::PS_jmprettnewpt:
3777  case Hexagon::PS_jmpretfnewpt:
3778  case Hexagon::PS_jmprettnew:
3779  case Hexagon::PS_jmpretfnew:
3780  case Hexagon::SL2_jumpr31_t:
3781  case Hexagon::SL2_jumpr31_f:
3782  case Hexagon::SL2_jumpr31_tnew:
3783  DstReg = MI.getOperand(1).getReg();
3784  SrcReg = MI.getOperand(0).getReg();
3785  // [if ([!]p0[.new])] jumpr r31
3786  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3787  (Hexagon::P0 == SrcReg)) &&
3788  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3789  return HexagonII::HSIG_L2;
3790  break;
3791  case Hexagon::L4_return_t:
3792  case Hexagon::L4_return_f:
3793  case Hexagon::L4_return_tnew_pnt:
3794  case Hexagon::L4_return_fnew_pnt:
3795  case Hexagon::L4_return_tnew_pt:
3796  case Hexagon::L4_return_fnew_pt:
3797  // [if ([!]p0[.new])] dealloc_return
3798  SrcReg = MI.getOperand(0).getReg();
3799  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3800  return HexagonII::HSIG_L2;
3801  break;
3802  //
3803  // Group S1:
3804  //
3805  // memw(Rs+#u4:2) = Rt
3806  // memb(Rs+#u4:0) = Rt
3807  case Hexagon::S2_storeri_io:
3808  // Special case this one from Group S2.
3809  // memw(r29+#u5:2) = Rt
3810  Src1Reg = MI.getOperand(0).getReg();
3811  Src2Reg = MI.getOperand(2).getReg();
3812  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3813  isIntRegForSubInst(Src2Reg) &&
3814  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3815  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3816  return HexagonII::HSIG_S2;
3817  // memw(Rs+#u4:2) = Rt
3818  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3819  MI.getOperand(1).isImm() &&
3820  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3821  return HexagonII::HSIG_S1;
3822  break;
3823  case Hexagon::S2_storerb_io:
3824  // memb(Rs+#u4:0) = Rt
3825  Src1Reg = MI.getOperand(0).getReg();
3826  Src2Reg = MI.getOperand(2).getReg();
3827  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3828  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3829  return HexagonII::HSIG_S1;
3830  break;
3831  //
3832  // Group S2:
3833  //
3834  // memh(Rs+#u3:1) = Rt
3835  // memw(r29+#u5:2) = Rt
3836  // memd(r29+#s6:3) = Rtt
3837  // memw(Rs+#u4:2) = #U1
3838  // memb(Rs+#u4) = #U1
3839  // allocframe(#u5:3)
3840  case Hexagon::S2_storerh_io:
3841  // memh(Rs+#u3:1) = Rt
3842  Src1Reg = MI.getOperand(0).getReg();
3843  Src2Reg = MI.getOperand(2).getReg();
3844  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3845  MI.getOperand(1).isImm() &&
3846  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3847  return HexagonII::HSIG_S1;
3848  break;
3849  case Hexagon::S2_storerd_io:
3850  // memd(r29+#s6:3) = Rtt
3851  Src1Reg = MI.getOperand(0).getReg();
3852  Src2Reg = MI.getOperand(2).getReg();
3853  if (isDblRegForSubInst(Src2Reg, HRI) &&
3854  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3855  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3856  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3857  return HexagonII::HSIG_S2;
3858  break;
3859  case Hexagon::S4_storeiri_io:
3860  // memw(Rs+#u4:2) = #U1
3861  Src1Reg = MI.getOperand(0).getReg();
3862  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3863  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3864  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3865  return HexagonII::HSIG_S2;
3866  break;
3867  case Hexagon::S4_storeirb_io:
3868  // memb(Rs+#u4) = #U1
3869  Src1Reg = MI.getOperand(0).getReg();
3870  if (isIntRegForSubInst(Src1Reg) &&
3871  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3872  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3873  return HexagonII::HSIG_S2;
3874  break;
3875  case Hexagon::S2_allocframe:
3876  if (MI.getOperand(2).isImm() &&
3877  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3878  return HexagonII::HSIG_S1;
3879  break;
3880  //
3881  // Group A:
3882  //
3883  // Rx = add(Rx,#s7)
3884  // Rd = Rs
3885  // Rd = #u6
3886  // Rd = #-1
3887  // if ([!]P0[.new]) Rd = #0
3888  // Rd = add(r29,#u6:2)
3889  // Rx = add(Rx,Rs)
3890  // P0 = cmp.eq(Rs,#u2)
3891  // Rdd = combine(#0,Rs)
3892  // Rdd = combine(Rs,#0)
3893  // Rdd = combine(#u2,#U2)
3894  // Rd = add(Rs,#1)
3895  // Rd = add(Rs,#-1)
3896  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3897  // Rd = and(Rs,#1)
3898  case Hexagon::A2_addi:
3899  DstReg = MI.getOperand(0).getReg();
3900  SrcReg = MI.getOperand(1).getReg();
3901  if (isIntRegForSubInst(DstReg)) {
3902  // Rd = add(r29,#u6:2)
3903  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3904  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3905  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3906  return HexagonII::HSIG_A;
3907  // Rx = add(Rx,#s7)
3908  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3909  isInt<7>(MI.getOperand(2).getImm()))
3910  return HexagonII::HSIG_A;
3911  // Rd = add(Rs,#1)
3912  // Rd = add(Rs,#-1)
3913  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3914  ((MI.getOperand(2).getImm() == 1) ||
3915  (MI.getOperand(2).getImm() == -1)))
3916  return HexagonII::HSIG_A;
3917  }
3918  break;
3919  case Hexagon::A2_add:
3920  // Rx = add(Rx,Rs)
3921  DstReg = MI.getOperand(0).getReg();
3922  Src1Reg = MI.getOperand(1).getReg();
3923  Src2Reg = MI.getOperand(2).getReg();
3924  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3925  isIntRegForSubInst(Src2Reg))
3926  return HexagonII::HSIG_A;
3927  break;
3928  case Hexagon::A2_andir:
3929  // Same as zxtb.
3930  // Rd16=and(Rs16,#255)
3931  // Rd16=and(Rs16,#1)
3932  DstReg = MI.getOperand(0).getReg();
3933  SrcReg = MI.getOperand(1).getReg();
3934  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3935  MI.getOperand(2).isImm() &&
3936  ((MI.getOperand(2).getImm() == 1) ||
3937  (MI.getOperand(2).getImm() == 255)))
3938  return HexagonII::HSIG_A;
3939  break;
3940  case Hexagon::A2_tfr:
3941  // Rd = Rs
3942  DstReg = MI.getOperand(0).getReg();
3943  SrcReg = MI.getOperand(1).getReg();
3944  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3945  return HexagonII::HSIG_A;
3946  break;
3947  case Hexagon::A2_tfrsi:
3948  // Rd = #u6
3949  // Do not test for #u6 size since the const is getting extended
3950  // regardless and compound could be formed.
3951  // Rd = #-1
3952  DstReg = MI.getOperand(0).getReg();
3953  if (isIntRegForSubInst(DstReg))
3954  return HexagonII::HSIG_A;
3955  break;
3956  case Hexagon::C2_cmoveit:
3957  case Hexagon::C2_cmovenewit:
3958  case Hexagon::C2_cmoveif:
3959  case Hexagon::C2_cmovenewif:
3960  // if ([!]P0[.new]) Rd = #0
3961  // Actual form:
3962  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3963  DstReg = MI.getOperand(0).getReg();
3964  SrcReg = MI.getOperand(1).getReg();
3965  if (isIntRegForSubInst(DstReg) &&
3966  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3967  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3968  return HexagonII::HSIG_A;
3969  break;
3970  case Hexagon::C2_cmpeqi:
3971  // P0 = cmp.eq(Rs,#u2)
3972  DstReg = MI.getOperand(0).getReg();
3973  SrcReg = MI.getOperand(1).getReg();
3974  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3975  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3976  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3977  return HexagonII::HSIG_A;
3978  break;
3979  case Hexagon::A2_combineii:
3980  case Hexagon::A4_combineii:
3981  // Rdd = combine(#u2,#U2)
3982  DstReg = MI.getOperand(0).getReg();
3983  if (isDblRegForSubInst(DstReg, HRI) &&
3984  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3985  (MI.getOperand(1).isGlobal() &&
3986  isUInt<2>(MI.getOperand(1).getOffset()))) &&
3987  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3988  (MI.getOperand(2).isGlobal() &&
3989  isUInt<2>(MI.getOperand(2).getOffset()))))
3990  return HexagonII::HSIG_A;
3991  break;
3992  case Hexagon::A4_combineri:
3993  // Rdd = combine(Rs,#0)
3994  DstReg = MI.getOperand(0).getReg();
3995  SrcReg = MI.getOperand(1).getReg();
3996  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3997  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3998  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3999  return HexagonII::HSIG_A;
4000  break;
4001  case Hexagon::A4_combineir:
4002  // Rdd = combine(#0,Rs)
4003  DstReg = MI.getOperand(0).getReg();
4004  SrcReg = MI.getOperand(2).getReg();
4005  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4006  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4007  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4008  return HexagonII::HSIG_A;
4009  break;
4010  case Hexagon::A2_sxtb:
4011  case Hexagon::A2_sxth:
4012  case Hexagon::A2_zxtb:
4013  case Hexagon::A2_zxth:
4014  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4015  DstReg = MI.getOperand(0).getReg();
4016  SrcReg = MI.getOperand(1).getReg();
4017  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4018  return HexagonII::HSIG_A;
4019  break;
4020  }
4021 
4022  return HexagonII::HSIG_None;
4023 }
4024 
4026  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4027 }
4028 
4030  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4031  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4032  // still have a MinLatency property, which getStageLatency checks.
4033  if (!ItinData)
4034  return getInstrLatency(ItinData, MI);
4035 
4036  if (MI.isTransient())
4037  return 0;
4038  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4039 }
4040 
4041 /// getOperandLatency - Compute and return the use operand latency of a given
4042 /// pair of def and use.
4043 /// In most cases, the static scheduling itinerary was enough to determine the
4044 /// operand latency. But it may not be possible for instructions with variable
4045 /// number of defs / uses.
4046 ///
4047 /// This is a raw interface to the itinerary that may be directly overriden by
4048 /// a target. Use computeOperandLatency to get the best estimate of latency.
4050  const MachineInstr &DefMI,
4051  unsigned DefIdx,
4052  const MachineInstr &UseMI,
4053  unsigned UseIdx) const {
4054  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4055 
4056  // Get DefIdx and UseIdx for super registers.
4057  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4058 
4059  if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
4060  if (DefMO.isImplicit()) {
4061  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4062  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4063  if (Idx != -1) {
4064  DefIdx = Idx;
4065  break;
4066  }
4067  }
4068  }
4069 
4070  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4071  if (UseMO.isImplicit()) {
4072  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4073  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4074  if (Idx != -1) {
4075  UseIdx = Idx;
4076  break;
4077  }
4078  }
4079  }
4080  }
4081 
4082  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4083  UseMI, UseIdx);
4084  if (!Latency)
4085  // We should never have 0 cycle latency between two instructions unless
4086  // they can be packetized together. However, this decision can't be made
4087  // here.
4088  Latency = 1;
4089  return Latency;
4090 }
4091 
4092 // inverts the predication logic.
4093 // p -> NotP
4094 // NotP -> P
4096  SmallVectorImpl<MachineOperand> &Cond) const {
4097  if (Cond.empty())
4098  return false;
4099  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4100  Cond[0].setImm(Opc);
4101  return true;
4102 }
4103 
4104 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4105  int InvPredOpcode;
4106  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4107  : Hexagon::getTruePredOpcode(Opc);
4108  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4109  return InvPredOpcode;
4110 
4111  llvm_unreachable("Unexpected predicated instruction");
4112 }
4113 
4114 // Returns the max value that doesn't need to be extended.
4116  const uint64_t F = MI.getDesc().TSFlags;
4117  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4119  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4121 
4122  if (isSigned) // if value is signed
4123  return ~(-1U << (bits - 1));
4124  else
4125  return ~(-1U << bits);
4126 }
4127 
4128 
4130  switch (MI.getOpcode()) {
4131  case Hexagon::L2_loadrbgp:
4132  case Hexagon::L2_loadrdgp:
4133  case Hexagon::L2_loadrhgp:
4134  case Hexagon::L2_loadrigp:
4135  case Hexagon::L2_loadrubgp:
4136  case Hexagon::L2_loadruhgp:
4137  case Hexagon::S2_storerbgp:
4138  case Hexagon::S2_storerbnewgp:
4139  case Hexagon::S2_storerhgp:
4140  case Hexagon::S2_storerhnewgp:
4141  case Hexagon::S2_storerigp:
4142  case Hexagon::S2_storerinewgp:
4143  case Hexagon::S2_storerdgp:
4144  case Hexagon::S2_storerfgp:
4145  return true;
4146  }
4147  const uint64_t F = MI.getDesc().TSFlags;
4148  unsigned addrMode =
4150  // Disallow any base+offset instruction. The assembler does not yet reorder
4151  // based up any zero offset instruction.
4152  return (addrMode == HexagonII::BaseRegOffset ||
4153  addrMode == HexagonII::BaseImmOffset ||
4154  addrMode == HexagonII::BaseLongOffset);
4155 }
4156 
4158  using namespace HexagonII;
4159 
4160  const uint64_t F = MI.getDesc().TSFlags;
4161  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4163  if (Size != 0)
4164  return Size;
4165 
4166  // Handle vector access sizes.
4167  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4168  switch (S) {
4170  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4171  default:
4172  llvm_unreachable("Unexpected instruction");
4173  }
4174 }
4175 
4176 // Returns the min value that doesn't need to be extended.
4178  const uint64_t F = MI.getDesc().TSFlags;
4179  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4181  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4183 
4184  if (isSigned) // if value is signed
4185  return -1U << (bits - 1);
4186  else
4187  return 0;
4188 }
4189 
4190 // Returns opcode of the non-extended equivalent instruction.
4192  // Check if the instruction has a register form that uses register in place
4193  // of the extended operand, if so return that as the non-extended form.
4194  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4195  if (NonExtOpcode >= 0)
4196  return NonExtOpcode;
4197 
4198  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4199  // Check addressing mode and retrieve non-ext equivalent instruction.
4200  switch (getAddrMode(MI)) {
4201  case HexagonII::Absolute:
4202  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4204  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4206  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4207 
4208  default:
4209  return -1;
4210  }
4211  }
4212  return -1;
4213 }
4214 
4216  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4217  if (Cond.empty())
4218  return false;
4219  assert(Cond.size() == 2);
4220  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4221  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4222  return false;
4223  }
4224  PredReg = Cond[1].getReg();
4225  PredRegPos = 1;
4226  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4227  PredRegFlags = 0;
4228  if (Cond[1].isImplicit())
4229  PredRegFlags = RegState::Implicit;
4230  if (Cond[1].isUndef())
4231  PredRegFlags |= RegState::Undef;
4232  return true;
4233 }
4234 
4236  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4237 }
4238 
4240  return Hexagon::getRegForm(MI.getOpcode());
4241 }
4242 
4243 // Return the number of bytes required to encode the instruction.
4244 // Hexagon instructions are fixed length, 4 bytes, unless they
4245 // use a constant extender, which requires another 4 bytes.
4246 // For debug instructions and prolog labels, return 0.
4248  if (MI.isDebugInstr() || MI.isPosition())
4249  return 0;
4250 
4251  unsigned Size = MI.getDesc().getSize();
4252  if (!Size)
4253  // Assume the default insn size in case it cannot be determined
4254  // for whatever reason.
4255  Size = HEXAGON_INSTR_SIZE;
4256 
4257  if (isConstExtended(MI) || isExtended(MI))
4258  Size += HEXAGON_INSTR_SIZE;
4259 
4260  // Try and compute number of instructions in asm.
4262  const MachineBasicBlock &MBB = *MI.getParent();
4263  const MachineFunction *MF = MBB.getParent();
4264  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4265 
4266  // Count the number of register definitions to find the asm string.
4267  unsigned NumDefs = 0;
4268  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4269  ++NumDefs)
4270  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4271 
4272  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4273  // Disassemble the AsmStr and approximate number of instructions.
4274  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4275  Size = getInlineAsmLength(AsmStr, *MAI);
4276  }
4277 
4278  return Size;
4279 }
4280 
4282  const uint64_t F = MI.getDesc().TSFlags;
4283  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4284 }
4285 
4287  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4288  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4289 
4290  return IS.getUnits();
4291 }
4292 
4293 // Calculate size of the basic block without debug instructions.
4295  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4296 }
4297 
4299  MachineBasicBlock::const_iterator BundleHead) const {
4300  assert(BundleHead->isBundle() && "Not a bundle header");
4301  auto MII = BundleHead.getInstrIterator();
4302  // Skip the bundle header.
4303  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4304 }
4305 
4306 /// immediateExtend - Changes the instruction in place to one using an immediate
4307 /// extender.
4309  assert((isExtendable(MI)||isConstExtended(MI)) &&
4310  "Instruction must be extendable");
4311  // Find which operand is extendable.
4312  short ExtOpNum = getCExtOpNum(MI);
4313  MachineOperand &MO = MI.getOperand(ExtOpNum);
4314  // This needs to be something we understand.
4315  assert((MO.isMBB() || MO.isImm()) &&
4316  "Branch with unknown extendable field type");
4317  // Mark given operand as extended.
4319 }
4320 
4322  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4323  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4324  << printMBBReference(*NewTarget);
4325  MI.dump(););
4326  assert(MI.isBranch());
4327  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4328  int TargetPos = MI.getNumOperands() - 1;
4329  // In general branch target is the last operand,
4330  // but some implicit defs added at the end might change it.
4331  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4332  --TargetPos;
4333  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4334  MI.getOperand(TargetPos).setMBB(NewTarget);
4336  NewOpcode = reversePrediction(NewOpcode);
4337  }
4338  MI.setDesc(get(NewOpcode));
4339  return true;
4340 }
4341 
4343  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4345  MachineBasicBlock &B = *A;
4347  DebugLoc DL = I->getDebugLoc();
4348  MachineInstr *NewMI;
4349 
4350  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4351  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4352  NewMI = BuildMI(B, I, DL, get(insn));
4353  LLVM_DEBUG(dbgs() << "\n"
4354  << getName(NewMI->getOpcode())
4355  << " Class: " << NewMI->getDesc().getSchedClass());
4356  NewMI->eraseFromParent();
4357  }
4358  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4359 }
4360 
4361 // inverts the predication logic.
4362 // p -> NotP
4363 // NotP -> P
4365  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4367  return true;
4368 }
4369 
4370 // Reverse the branch prediction.
4371 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4372  int PredRevOpcode = -1;
4373  if (isPredictedTaken(Opcode))
4374  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4375  else
4376  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4377  assert(PredRevOpcode > 0);
4378  return PredRevOpcode;
4379 }
4380 
4381 // TODO: Add more rigorous validation.
4383  const {
4384  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4385 }
4386 
4387 void HexagonInstrInfo::
4389  assert(MIB->isBundle());
4390  MachineOperand &Operand = MIB->getOperand(0);
4391  if (Operand.isImm())
4392  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4393  else
4394  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4395 }
4396 
4398  assert(MIB.isBundle());
4399  const MachineOperand &Operand = MIB.getOperand(0);
4400  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4401 }
4402 
4403 // Addressing mode relations.
4405  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4406 }
4407 
4409  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4410 }
4411 
4413  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4414 }
4415 
4417  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4418 }
4419 
4421  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4422 }
4423 
4425  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4426 }
4427 
4429  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4430 }
4431 
4433  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4434 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:635
short changeAddrMode_rr_io(short Opc) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
void push_back(const T &Elt)
Definition: SmallVector.h:211
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool isInlineAsm() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
demanded bits
MachineBasicBlock reference.
#define HEXAGON_INSTR_SIZE
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:398
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:457
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:666
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:662
bool isEndLoopN(unsigned Opcode) const
bool isBundle() const
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:656
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:622
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:693
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const char * getSeparatorString() const
Definition: MCAsmInfo.h:479
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const