LLVM  7.0.0svn
AMDGPUInstructionSelector.cpp
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1 //===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for
11 /// AMDGPU.
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
14 
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterBankInfo.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/Debug.h"
29 
30 #define DEBUG_TYPE "amdgpu-isel"
31 
32 using namespace llvm;
33 
35  const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
36  : InstructionSelector(), TII(*STI.getInstrInfo()),
37  TRI(*STI.getRegisterInfo()), RBI(RBI), AMDGPUASI(STI.getAMDGPUAS()) {}
38 
40 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
41  unsigned SubIdx) const {
42 
43  MachineInstr *MI = MO.getParent();
45  MachineFunction *MF = BB->getParent();
47  unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
48 
49  if (MO.isReg()) {
50  unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
51  unsigned Reg = MO.getReg();
52  BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
53  .addReg(Reg, 0, ComposedSubIdx);
54 
55  return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
56  MO.isKill(), MO.isDead(), MO.isUndef(),
57  MO.isEarlyClobber(), 0, MO.isDebug(),
58  MO.isInternalRead());
59  }
60 
61  assert(MO.isImm());
62 
63  APInt Imm(64, MO.getImm());
64 
65  switch (SubIdx) {
66  default:
67  llvm_unreachable("do not know to split immediate with this sub index.");
68  case AMDGPU::sub0:
69  return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
70  case AMDGPU::sub1:
71  return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
72  }
73 }
74 
75 bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
76  MachineBasicBlock *BB = I.getParent();
77  MachineFunction *MF = BB->getParent();
79  unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
80  unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
81  unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
82 
83  if (Size != 64)
84  return false;
85 
86  DebugLoc DL = I.getDebugLoc();
87 
88  MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
89  MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
90 
91  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
92  .add(Lo1)
93  .add(Lo2);
94 
95  MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
96  MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
97 
98  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
99  .add(Hi1)
100  .add(Hi2);
101 
102  BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
103  .addReg(DstLo)
104  .addImm(AMDGPU::sub0)
105  .addReg(DstHi)
106  .addImm(AMDGPU::sub1);
107 
108  for (MachineOperand &MO : I.explicit_operands()) {
110  continue;
111  RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
112  }
113 
114  I.eraseFromParent();
115  return true;
116 }
117 
118 bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
119  return selectG_ADD(I);
120 }
121 
122 bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
123  MachineBasicBlock *BB = I.getParent();
124  DebugLoc DL = I.getDebugLoc();
125 
126  // FIXME: Select store instruction based on address space
127  MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(AMDGPU::FLAT_STORE_DWORD))
128  .add(I.getOperand(1))
129  .add(I.getOperand(0))
130  .addImm(0) // offset
131  .addImm(0) // glc
132  .addImm(0); // slc
133 
134 
135  // Now that we selected an opcode, we need to constrain the register
136  // operands to use appropriate classes.
137  bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
138 
139  I.eraseFromParent();
140  return Ret;
141 }
142 
143 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
144  MachineBasicBlock *BB = I.getParent();
145  MachineFunction *MF = BB->getParent();
147  unsigned DstReg = I.getOperand(0).getReg();
148  unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
149 
150  if (Size == 32) {
151  I.setDesc(TII.get(AMDGPU::S_MOV_B32));
152  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
153  }
154 
155  assert(Size == 64);
156 
157  DebugLoc DL = I.getDebugLoc();
158  unsigned LoReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
159  unsigned HiReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
160  const APInt &Imm = I.getOperand(1).getCImm()->getValue();
161 
162  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), LoReg)
163  .addImm(Imm.trunc(32).getZExtValue());
164 
165  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg)
166  .addImm(Imm.ashr(32).getZExtValue());
167 
168  BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
169  .addReg(LoReg)
170  .addImm(AMDGPU::sub0)
171  .addReg(HiReg)
172  .addImm(AMDGPU::sub1);
173  // We can't call constrainSelectedInstRegOperands here, because it doesn't
174  // work for target independent opcodes
175  I.eraseFromParent();
176  return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
177 }
178 
179 static bool isConstant(const MachineInstr &MI) {
180  return MI.getOpcode() == TargetOpcode::G_CONSTANT;
181 }
182 
183 void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
184  const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
185 
186  const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
187 
188  assert(PtrMI);
189 
190  if (PtrMI->getOpcode() != TargetOpcode::G_GEP)
191  return;
192 
193  GEPInfo GEPInfo(*PtrMI);
194 
195  for (unsigned i = 1, e = 3; i < e; ++i) {
196  const MachineOperand &GEPOp = PtrMI->getOperand(i);
197  const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
198  assert(OpDef);
199  if (isConstant(*OpDef)) {
200  // FIXME: Is it possible to have multiple Imm parts? Maybe if we
201  // are lacking other optimizations.
202  assert(GEPInfo.Imm == 0);
203  GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
204  continue;
205  }
206  const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
207  if (OpBank->getID() == AMDGPU::SGPRRegBankID)
208  GEPInfo.SgprParts.push_back(GEPOp.getReg());
209  else
210  GEPInfo.VgprParts.push_back(GEPOp.getReg());
211  }
212 
213  AddrInfo.push_back(GEPInfo);
214  getAddrModeInfo(*PtrMI, MRI, AddrInfo);
215 }
216 
217 static bool isInstrUniform(const MachineInstr &MI) {
218  if (!MI.hasOneMemOperand())
219  return false;
220 
221  const MachineMemOperand *MMO = *MI.memoperands_begin();
222  const Value *Ptr = MMO->getValue();
223 
224  // UndefValue means this is a load of a kernel input. These are uniform.
225  // Sometimes LDS instructions have constant pointers.
226  // If Ptr is null, then that means this mem operand contains a
227  // PseudoSourceValue like GOT.
228  if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
229  isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
230  return true;
231 
233  return true;
234 
235  const Instruction *I = dyn_cast<Instruction>(Ptr);
236  return I && I->getMetadata("amdgpu.uniform");
237 }
238 
239 static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize) {
240 
241  if (LoadSize == 32)
242  return BaseOpcode;
243 
244  switch (BaseOpcode) {
245  case AMDGPU::S_LOAD_DWORD_IMM:
246  switch (LoadSize) {
247  case 64:
248  return AMDGPU::S_LOAD_DWORDX2_IMM;
249  case 128:
250  return AMDGPU::S_LOAD_DWORDX4_IMM;
251  case 256:
252  return AMDGPU::S_LOAD_DWORDX8_IMM;
253  case 512:
254  return AMDGPU::S_LOAD_DWORDX16_IMM;
255  }
256  break;
257  case AMDGPU::S_LOAD_DWORD_IMM_ci:
258  switch (LoadSize) {
259  case 64:
260  return AMDGPU::S_LOAD_DWORDX2_IMM_ci;
261  case 128:
262  return AMDGPU::S_LOAD_DWORDX4_IMM_ci;
263  case 256:
264  return AMDGPU::S_LOAD_DWORDX8_IMM_ci;
265  case 512:
266  return AMDGPU::S_LOAD_DWORDX16_IMM_ci;
267  }
268  break;
269  case AMDGPU::S_LOAD_DWORD_SGPR:
270  switch (LoadSize) {
271  case 64:
272  return AMDGPU::S_LOAD_DWORDX2_SGPR;
273  case 128:
274  return AMDGPU::S_LOAD_DWORDX4_SGPR;
275  case 256:
276  return AMDGPU::S_LOAD_DWORDX8_SGPR;
277  case 512:
278  return AMDGPU::S_LOAD_DWORDX16_SGPR;
279  }
280  break;
281  }
282  llvm_unreachable("Invalid base smrd opcode or size");
283 }
284 
285 bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
286  for (const GEPInfo &GEPInfo : AddrInfo) {
287  if (!GEPInfo.VgprParts.empty())
288  return true;
289  }
290  return false;
291 }
292 
293 bool AMDGPUInstructionSelector::selectSMRD(MachineInstr &I,
294  ArrayRef<GEPInfo> AddrInfo) const {
295 
296  if (!I.hasOneMemOperand())
297  return false;
298 
301  return false;
302 
303  if (!isInstrUniform(I))
304  return false;
305 
306  if (hasVgprParts(AddrInfo))
307  return false;
308 
309  MachineBasicBlock *BB = I.getParent();
310  MachineFunction *MF = BB->getParent();
311  const SISubtarget &Subtarget = MF->getSubtarget<SISubtarget>();
312  MachineRegisterInfo &MRI = MF->getRegInfo();
313  unsigned DstReg = I.getOperand(0).getReg();
314  const DebugLoc &DL = I.getDebugLoc();
315  unsigned Opcode;
316  unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
317 
318  if (!AddrInfo.empty() && AddrInfo[0].SgprParts.size() == 1) {
319 
320  const GEPInfo &GEPInfo = AddrInfo[0];
321 
322  unsigned PtrReg = GEPInfo.SgprParts[0];
323  int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(Subtarget, GEPInfo.Imm);
324  if (AMDGPU::isLegalSMRDImmOffset(Subtarget, GEPInfo.Imm)) {
325  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
326 
327  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
328  .addReg(PtrReg)
329  .addImm(EncodedImm)
330  .addImm(0); // glc
331  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
332  }
333 
334  if (Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS &&
335  isUInt<32>(EncodedImm)) {
336  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM_ci, LoadSize);
337  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
338  .addReg(PtrReg)
339  .addImm(EncodedImm)
340  .addImm(0); // glc
341  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
342  }
343 
344  if (isUInt<32>(GEPInfo.Imm)) {
345  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_SGPR, LoadSize);
346  unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
347  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), OffsetReg)
348  .addImm(GEPInfo.Imm);
349 
350  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
351  .addReg(PtrReg)
352  .addReg(OffsetReg)
353  .addImm(0); // glc
354  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
355  }
356  }
357 
358  unsigned PtrReg = I.getOperand(1).getReg();
359  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
360  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
361  .addReg(PtrReg)
362  .addImm(0)
363  .addImm(0); // glc
364  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
365 }
366 
367 
368 bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
369  MachineBasicBlock *BB = I.getParent();
370  MachineFunction *MF = BB->getParent();
371  MachineRegisterInfo &MRI = MF->getRegInfo();
372  DebugLoc DL = I.getDebugLoc();
373  unsigned DstReg = I.getOperand(0).getReg();
374  unsigned PtrReg = I.getOperand(1).getReg();
375  unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
376  unsigned Opcode;
377 
378  SmallVector<GEPInfo, 4> AddrInfo;
379 
380  getAddrModeInfo(I, MRI, AddrInfo);
381 
382  if (selectSMRD(I, AddrInfo)) {
383  I.eraseFromParent();
384  return true;
385  }
386 
387  switch (LoadSize) {
388  default:
389  llvm_unreachable("Load size not supported\n");
390  case 32:
391  Opcode = AMDGPU::FLAT_LOAD_DWORD;
392  break;
393  case 64:
394  Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
395  break;
396  }
397 
398  MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
399  .add(I.getOperand(0))
400  .addReg(PtrReg)
401  .addImm(0) // offset
402  .addImm(0) // glc
403  .addImm(0); // slc
404 
405  bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
406  I.eraseFromParent();
407  return Ret;
408 }
409 
411  CodeGenCoverage &CoverageInfo) const {
412 
414  return true;
415 
416  switch (I.getOpcode()) {
417  default:
418  break;
419  case TargetOpcode::G_ADD:
420  return selectG_ADD(I);
421  case TargetOpcode::G_CONSTANT:
422  return selectG_CONSTANT(I);
423  case TargetOpcode::G_GEP:
424  return selectG_GEP(I);
425  case TargetOpcode::G_LOAD:
426  return selectG_LOAD(I);
427  case TargetOpcode::G_STORE:
428  return selectG_STORE(I);
429  }
430  return false;
431 }
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:341
static bool isConstant(const MachineInstr &MI)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Generation getGeneration() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
unsigned getAddrSpace() const
AMDGPU specific subclass of TargetSubtarget.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:341
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
unsigned getReg() const
getReg - Returns the register number.
static bool isInstrUniform(const MachineInstr &MI)
unsigned getSubReg() const
AMDGPUAS getAMDGPUAS(const Module &M)
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:816
A debug info location.
Definition: DebugLoc.h:34
Address space for constant memory (VTX2)
Definition: AMDGPU.h:225
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isInternalRead() const
static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static unsigned getAddrSpace(StringRef R)
Definition: DataLayout.cpp:228
bool isEarlyClobber() const
bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
A description of a memory reference used in the backend.
This file declares the targeting of the InstructionSelector class for AMDGPU.
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
TargetRegisterInfo interface that is implemented by all hw codegen targets.
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:195
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:138
AMDGPUInstructionSelector(const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
const Value * getValue() const
Return the base address of the memory access.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:407
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:935
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:392
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:80
This class implements the register bank concept.
Definition: RegisterBank.h:29
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Class for arbitrary precision integers.
Definition: APInt.h:69
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Address space for 32-bit constant memory.
Definition: AMDGPU.h:228
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
const ConstantInt * getCImm() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
bool isImplicit() const