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AMDGPUInstructionSelector.cpp
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1 //===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for
11 /// AMDGPU.
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
14 
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterBankInfo.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
28 
29 #define DEBUG_TYPE "amdgpu-isel"
30 
31 using namespace llvm;
32 
34  const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
35  : InstructionSelector(), TII(*STI.getInstrInfo()),
36  TRI(*STI.getRegisterInfo()), RBI(RBI), AMDGPUASI(STI.getAMDGPUAS()) {}
37 
39 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
40  unsigned SubIdx) const {
41 
42  MachineInstr *MI = MO.getParent();
44  MachineFunction *MF = BB->getParent();
46  unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
47 
48  if (MO.isReg()) {
49  unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
50  unsigned Reg = MO.getReg();
51  BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
52  .addReg(Reg, 0, ComposedSubIdx);
53 
54  return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
55  MO.isKill(), MO.isDead(), MO.isUndef(),
56  MO.isEarlyClobber(), 0, MO.isDebug(),
57  MO.isInternalRead());
58  }
59 
60  assert(MO.isImm());
61 
62  APInt Imm(64, MO.getImm());
63 
64  switch (SubIdx) {
65  default:
66  llvm_unreachable("do not know to split immediate with this sub index.");
67  case AMDGPU::sub0:
68  return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
69  case AMDGPU::sub1:
70  return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
71  }
72 }
73 
74 bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
75  MachineBasicBlock *BB = I.getParent();
76  MachineFunction *MF = BB->getParent();
78  unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
79  unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
80  unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
81 
82  if (Size != 64)
83  return false;
84 
85  DebugLoc DL = I.getDebugLoc();
86 
87  MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
88  MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
89 
90  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
91  .add(Lo1)
92  .add(Lo2);
93 
94  MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
95  MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
96 
97  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
98  .add(Hi1)
99  .add(Hi2);
100 
101  BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
102  .addReg(DstLo)
103  .addImm(AMDGPU::sub0)
104  .addReg(DstHi)
105  .addImm(AMDGPU::sub1);
106 
107  for (MachineOperand &MO : I.explicit_operands()) {
109  continue;
110  RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
111  }
112 
113  I.eraseFromParent();
114  return true;
115 }
116 
117 bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
118  return selectG_ADD(I);
119 }
120 
121 bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
122  MachineBasicBlock *BB = I.getParent();
123  DebugLoc DL = I.getDebugLoc();
124 
125  // FIXME: Select store instruction based on address space
126  MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(AMDGPU::FLAT_STORE_DWORD))
127  .add(I.getOperand(1))
128  .add(I.getOperand(0))
129  .addImm(0) // offset
130  .addImm(0) // glc
131  .addImm(0); // slc
132 
133 
134  // Now that we selected an opcode, we need to constrain the register
135  // operands to use appropriate classes.
136  bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
137 
138  I.eraseFromParent();
139  return Ret;
140 }
141 
142 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
143  MachineBasicBlock *BB = I.getParent();
144  MachineFunction *MF = BB->getParent();
146  unsigned DstReg = I.getOperand(0).getReg();
147  unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
148 
149  if (Size == 32) {
150  I.setDesc(TII.get(AMDGPU::S_MOV_B32));
151  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
152  }
153 
154  assert(Size == 64);
155 
156  DebugLoc DL = I.getDebugLoc();
157  unsigned LoReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
158  unsigned HiReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
159  const APInt &Imm = I.getOperand(1).getCImm()->getValue();
160 
161  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), LoReg)
162  .addImm(Imm.trunc(32).getZExtValue());
163 
164  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg)
165  .addImm(Imm.ashr(32).getZExtValue());
166 
167  BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
168  .addReg(LoReg)
169  .addImm(AMDGPU::sub0)
170  .addReg(HiReg)
171  .addImm(AMDGPU::sub1);
172  // We can't call constrainSelectedInstRegOperands here, because it doesn't
173  // work for target independent opcodes
174  I.eraseFromParent();
175  return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
176 }
177 
178 static bool isConstant(const MachineInstr &MI) {
179  return MI.getOpcode() == TargetOpcode::G_CONSTANT;
180 }
181 
182 void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
183  const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
184 
185  const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
186 
187  assert(PtrMI);
188 
189  if (PtrMI->getOpcode() != TargetOpcode::G_GEP)
190  return;
191 
192  GEPInfo GEPInfo(*PtrMI);
193 
194  for (unsigned i = 1, e = 3; i < e; ++i) {
195  const MachineOperand &GEPOp = PtrMI->getOperand(i);
196  const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
197  assert(OpDef);
198  if (isConstant(*OpDef)) {
199  // FIXME: Is it possible to have multiple Imm parts? Maybe if we
200  // are lacking other optimizations.
201  assert(GEPInfo.Imm == 0);
202  GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
203  continue;
204  }
205  const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
206  if (OpBank->getID() == AMDGPU::SGPRRegBankID)
207  GEPInfo.SgprParts.push_back(GEPOp.getReg());
208  else
209  GEPInfo.VgprParts.push_back(GEPOp.getReg());
210  }
211 
212  AddrInfo.push_back(GEPInfo);
213  getAddrModeInfo(*PtrMI, MRI, AddrInfo);
214 }
215 
216 static bool isInstrUniform(const MachineInstr &MI) {
217  if (!MI.hasOneMemOperand())
218  return false;
219 
220  const MachineMemOperand *MMO = *MI.memoperands_begin();
221  const Value *Ptr = MMO->getValue();
222 
223  // UndefValue means this is a load of a kernel input. These are uniform.
224  // Sometimes LDS instructions have constant pointers.
225  // If Ptr is null, then that means this mem operand contains a
226  // PseudoSourceValue like GOT.
227  if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
228  isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
229  return true;
230 
231  const Instruction *I = dyn_cast<Instruction>(Ptr);
232  return I && I->getMetadata("amdgpu.uniform");
233 }
234 
235 static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize) {
236 
237  if (LoadSize == 32)
238  return BaseOpcode;
239 
240  switch (BaseOpcode) {
241  case AMDGPU::S_LOAD_DWORD_IMM:
242  switch (LoadSize) {
243  case 64:
244  return AMDGPU::S_LOAD_DWORDX2_IMM;
245  case 128:
246  return AMDGPU::S_LOAD_DWORDX4_IMM;
247  case 256:
248  return AMDGPU::S_LOAD_DWORDX8_IMM;
249  case 512:
250  return AMDGPU::S_LOAD_DWORDX16_IMM;
251  }
252  break;
253  case AMDGPU::S_LOAD_DWORD_IMM_ci:
254  switch (LoadSize) {
255  case 64:
256  return AMDGPU::S_LOAD_DWORDX2_IMM_ci;
257  case 128:
258  return AMDGPU::S_LOAD_DWORDX4_IMM_ci;
259  case 256:
260  return AMDGPU::S_LOAD_DWORDX8_IMM_ci;
261  case 512:
262  return AMDGPU::S_LOAD_DWORDX16_IMM_ci;
263  }
264  break;
265  case AMDGPU::S_LOAD_DWORD_SGPR:
266  switch (LoadSize) {
267  case 64:
268  return AMDGPU::S_LOAD_DWORDX2_SGPR;
269  case 128:
270  return AMDGPU::S_LOAD_DWORDX4_SGPR;
271  case 256:
272  return AMDGPU::S_LOAD_DWORDX8_SGPR;
273  case 512:
274  return AMDGPU::S_LOAD_DWORDX16_SGPR;
275  }
276  break;
277  }
278  llvm_unreachable("Invalid base smrd opcode or size");
279 }
280 
281 bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
282  for (const GEPInfo &GEPInfo : AddrInfo) {
283  if (!GEPInfo.VgprParts.empty())
284  return true;
285  }
286  return false;
287 }
288 
289 bool AMDGPUInstructionSelector::selectSMRD(MachineInstr &I,
290  ArrayRef<GEPInfo> AddrInfo) const {
291 
292  if (!I.hasOneMemOperand())
293  return false;
294 
295  if ((*I.memoperands_begin())->getAddrSpace() != AMDGPUASI.CONSTANT_ADDRESS)
296  return false;
297 
298  if (!isInstrUniform(I))
299  return false;
300 
301  if (hasVgprParts(AddrInfo))
302  return false;
303 
304  MachineBasicBlock *BB = I.getParent();
305  MachineFunction *MF = BB->getParent();
306  const SISubtarget &Subtarget = MF->getSubtarget<SISubtarget>();
307  MachineRegisterInfo &MRI = MF->getRegInfo();
308  unsigned DstReg = I.getOperand(0).getReg();
309  const DebugLoc &DL = I.getDebugLoc();
310  unsigned Opcode;
311  unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
312 
313  if (!AddrInfo.empty() && AddrInfo[0].SgprParts.size() == 1) {
314 
315  const GEPInfo &GEPInfo = AddrInfo[0];
316 
317  unsigned PtrReg = GEPInfo.SgprParts[0];
318  int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(Subtarget, GEPInfo.Imm);
319  if (AMDGPU::isLegalSMRDImmOffset(Subtarget, GEPInfo.Imm)) {
320  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
321 
322  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
323  .addReg(PtrReg)
324  .addImm(EncodedImm)
325  .addImm(0); // glc
326  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
327  }
328 
329  if (Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS &&
330  isUInt<32>(EncodedImm)) {
331  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM_ci, LoadSize);
332  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
333  .addReg(PtrReg)
334  .addImm(EncodedImm)
335  .addImm(0); // glc
336  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
337  }
338 
339  if (isUInt<32>(GEPInfo.Imm)) {
340  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_SGPR, LoadSize);
341  unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
342  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), OffsetReg)
343  .addImm(GEPInfo.Imm);
344 
345  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
346  .addReg(PtrReg)
347  .addReg(OffsetReg)
348  .addImm(0); // glc
349  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
350  }
351  }
352 
353  unsigned PtrReg = I.getOperand(1).getReg();
354  Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
355  MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
356  .addReg(PtrReg)
357  .addImm(0)
358  .addImm(0); // glc
359  return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
360 }
361 
362 
363 bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
364  MachineBasicBlock *BB = I.getParent();
365  MachineFunction *MF = BB->getParent();
366  MachineRegisterInfo &MRI = MF->getRegInfo();
367  DebugLoc DL = I.getDebugLoc();
368  unsigned DstReg = I.getOperand(0).getReg();
369  unsigned PtrReg = I.getOperand(1).getReg();
370  unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
371  unsigned Opcode;
372 
373  SmallVector<GEPInfo, 4> AddrInfo;
374 
375  getAddrModeInfo(I, MRI, AddrInfo);
376 
377  if (selectSMRD(I, AddrInfo)) {
378  I.eraseFromParent();
379  return true;
380  }
381 
382  switch (LoadSize) {
383  default:
384  llvm_unreachable("Load size not supported\n");
385  case 32:
386  Opcode = AMDGPU::FLAT_LOAD_DWORD;
387  break;
388  case 64:
389  Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
390  break;
391  }
392 
393  MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
394  .add(I.getOperand(0))
395  .addReg(PtrReg)
396  .addImm(0) // offset
397  .addImm(0) // glc
398  .addImm(0); // slc
399 
400  bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
401  I.eraseFromParent();
402  return Ret;
403 }
404 
406  CodeGenCoverage &CoverageInfo) const {
407 
409  return true;
410 
411  switch (I.getOpcode()) {
412  default:
413  break;
414  case TargetOpcode::G_ADD:
415  return selectG_ADD(I);
416  case TargetOpcode::G_CONSTANT:
417  return selectG_CONSTANT(I);
418  case TargetOpcode::G_GEP:
419  return selectG_GEP(I);
420  case TargetOpcode::G_LOAD:
421  return selectG_LOAD(I);
422  case TargetOpcode::G_STORE:
423  return selectG_STORE(I);
424  }
425  return false;
426 }
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:341
static bool isConstant(const MachineInstr &MI)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Generation getGeneration() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
AMDGPU specific subclass of TargetSubtarget.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:338
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
static bool isInstrUniform(const MachineInstr &MI)
unsigned getSubReg() const
AMDGPUAS getAMDGPUAS(const Module &M)
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:818
A debug info location.
Definition: DebugLoc.h:34
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isInternalRead() const
static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize)
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
bool isEarlyClobber() const
bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
A description of a memory reference used in the backend.
This file declares the targeting of the InstructionSelector class for AMDGPU.
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
TargetRegisterInfo interface that is implemented by all hw codegen targets.
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:194
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:138
AMDGPUInstructionSelector(const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
const Value * getValue() const
Return the base address of the memory access.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:404
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:935
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:389
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
This class implements the register bank concept.
Definition: RegisterBank.h:29
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Class for arbitrary precision integers.
Definition: APInt.h:69
Address space for constant memory (VTX2)
Definition: AMDGPU.h:225
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
const ConstantInt * getCImm() const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
bool isImplicit() const