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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 
21 #include "Mips.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <deque>
37 #include <string>
38 #include <utility>
39 #include <vector>
40 
41 namespace llvm {
42 
43 class Argument;
44 class CCState;
45 class CCValAssign;
46 class FastISel;
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFrameInfo;
50 class MachineInstr;
51 class MipsCCState;
52 class MipsFunctionInfo;
53 class MipsSubtarget;
54 class MipsTargetMachine;
55 class TargetLibraryInfo;
56 class TargetRegisterClass;
57 
58  namespace MipsISD {
59 
60  enum NodeType : unsigned {
61  // Start the numbering from where ISD NodeType finishes.
63 
64  // Jump and link (call)
66 
67  // Tail call
69 
70  // Get the Highest (63-48) 16 bits from a 64-bit immediate
72 
73  // Get the Higher (47-32) 16 bits from a 64-bit immediate
75 
76  // Get the High 16 bits from a 32/64-bit immediate
77  // No relation with Mips Hi register
78  Hi,
79 
80  // Get the Lower 16 bits from a 32/64-bit immediate
81  // No relation with Mips Lo register
82  Lo,
83 
84  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
86 
87  // Handle gp_rel (small data/bss sections) relocation.
89 
90  // Thread Pointer
92 
93  // Vector Floating Point Multiply and Subtract
94  FMS,
95 
96  // Floating Point Branch Conditional
98 
99  // Floating Point Compare
101 
102  // Floating point select
104 
105  // Node used to generate an MTC1 i32 to f64 instruction
107 
108  // Floating Point Conditional Moves
111 
112  // FP-to-int truncation node.
114 
115  // Return
117 
118  // Interrupt, exception, error trap Return
120 
121  // Software Exception Return.
123 
124  // Node used to extract integer from accumulator.
127 
128  // Node used to insert integers to accumulator.
130 
131  // Mult nodes.
134 
135  // MAdd/Sub nodes
140 
141  // DivRem(u)
146 
149 
151 
153 
155 
159 
160  // EXTR.W instrinsic nodes.
169 
170  // DPA.W intrinsic nodes.
193 
200 
201  // DSP shift nodes.
205 
206  // DSP setcc and select_cc nodes.
209 
210  // Vector comparisons.
211  // These take a vector and return a boolean.
216 
217  // These take a vector and return a vector bitmask.
223 
224  // Vector Shuffle with mask as an operand
225  VSHF, // Generic shuffle
226  SHF, // 4-element set shuffle.
227  ILVEV, // Interleave even elements
228  ILVOD, // Interleave odd elements
229  ILVL, // Interleave left elements
230  ILVR, // Interleave right elements
231  PCKEV, // Pack even elements
232  PCKOD, // Pack odd elements
233 
234  // Vector Lane Copy
235  INSVE, // Copy element from one vector to another
236 
237  // Combined (XOR (OR $a, $b), -1)
239 
240  // Extended vector element extraction
243 
244  // Load/Store Left/Right nodes.
253  };
254 
255  } // ene namespace MipsISD
256 
257  //===--------------------------------------------------------------------===//
258  // TargetLowering Implementation
259  //===--------------------------------------------------------------------===//
260 
262  bool isMicroMips;
263 
264  public:
265  explicit MipsTargetLowering(const MipsTargetMachine &TM,
266  const MipsSubtarget &STI);
267 
268  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
269  const MipsSubtarget &STI);
270 
271  /// createFastISel - This method returns a target specific FastISel object,
272  /// or null if the target does not support "fast" ISel.
274  const TargetLibraryInfo *libInfo) const override;
275 
276  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
277  return MVT::i32;
278  }
279 
280  bool isCheapToSpeculateCttz() const override;
281  bool isCheapToSpeculateCtlz() const override;
282 
283  /// Return the register type for a given MVT, ensuring vectors are treated
284  /// as a series of gpr sized integers.
285  MVT getRegisterTypeForCallingConv(LLVMContext &Context,
286  EVT VT) const override;
287 
288  /// Return the number of registers for a given MVT, ensuring vectors are
289  /// treated as a series of gpr sized integers.
290  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
291  EVT VT) const override;
292 
293  /// Break down vectors to the correct number of gpr sized integers.
294  unsigned getVectorTypeBreakdownForCallingConv(
295  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
296  unsigned &NumIntermediates, MVT &RegisterVT) const override;
297 
298  /// Return the correct alignment for the current calling convention.
300  DataLayout DL) const override {
301  if (ArgTy->isVectorTy())
302  return std::min(DL.getABITypeAlignment(ArgTy), 8U);
303  return DL.getABITypeAlignment(ArgTy);
304  }
305 
307  return ISD::SIGN_EXTEND;
308  }
309 
310  void LowerOperationWrapper(SDNode *N,
312  SelectionDAG &DAG) const override;
313 
314  /// LowerOperation - Provide custom lowering hooks for some operations.
315  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
316 
317  /// ReplaceNodeResults - Replace the results of node with an illegal result
318  /// type with new values built out of custom code.
319  ///
320  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
321  SelectionDAG &DAG) const override;
322 
323  /// getTargetNodeName - This method returns the name of a target specific
324  // DAG node.
325  const char *getTargetNodeName(unsigned Opcode) const override;
326 
327  /// getSetCCResultType - get the ISD::SETCC result ValueType
328  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
329  EVT VT) const override;
330 
331  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
332 
334  EmitInstrWithCustomInserter(MachineInstr &MI,
335  MachineBasicBlock *MBB) const override;
336 
337  void HandleByVal(CCState *, unsigned &, unsigned) const override;
338 
339  unsigned getRegisterByName(const char* RegName, EVT VT,
340  SelectionDAG &DAG) const override;
341 
342  /// If a physical register, this returns the register that receives the
343  /// exception address on entry to an EH pad.
344  unsigned
345  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
346  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
347  }
348 
349  /// If a physical register, this returns the register that receives the
350  /// exception typeid on entry to a landing pad.
351  unsigned
352  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
353  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
354  }
355 
356  /// Returns true if a cast between SrcAS and DestAS is a noop.
357  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
358  // Mips doesn't have any special address spaces so we just reserve
359  // the first 256 for software use (e.g. OpenCL) and treat casts
360  // between them as noops.
361  return SrcAS < 256 && DestAS < 256;
362  }
363 
364  bool isJumpTableRelative() const override {
365  return getTargetMachine().isPositionIndependent();
366  }
367 
368  CCAssignFn *CCAssignFnForCall() const;
369 
370  CCAssignFn *CCAssignFnForReturn() const;
371 
372  protected:
373  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
374 
375  // This method creates the following nodes, which are necessary for
376  // computing a local symbol's address:
377  //
378  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
379  template <class NodeTy>
380  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
381  bool IsN32OrN64) const {
382  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
383  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
384  getTargetNode(N, Ty, DAG, GOTFlag));
385  SDValue Load =
386  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
388  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
389  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
390  getTargetNode(N, Ty, DAG, LoFlag));
391  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
392  }
393 
394  // This method creates the following nodes, which are necessary for
395  // computing a global symbol's address:
396  //
397  // (load (wrapper $gp, %got(sym)))
398  template <class NodeTy>
399  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
400  unsigned Flag, SDValue Chain,
401  const MachinePointerInfo &PtrInfo) const {
402  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
403  getTargetNode(N, Ty, DAG, Flag));
404  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
405  }
406 
407  // This method creates the following nodes, which are necessary for
408  // computing a global symbol's address in large-GOT mode:
409  //
410  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
411  template <class NodeTy>
412  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
413  SelectionDAG &DAG, unsigned HiFlag,
414  unsigned LoFlag, SDValue Chain,
415  const MachinePointerInfo &PtrInfo) const {
416  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
417  getTargetNode(N, Ty, DAG, HiFlag));
418  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
419  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
420  getTargetNode(N, Ty, DAG, LoFlag));
421  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
422  }
423 
424  // This method creates the following nodes, which are necessary for
425  // computing a symbol's address in non-PIC mode:
426  //
427  // (add %hi(sym), %lo(sym))
428  //
429  // This method covers O32, N32 and N64 in sym32 mode.
430  template <class NodeTy>
431  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
432  SelectionDAG &DAG) const {
433  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
434  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
435  return DAG.getNode(ISD::ADD, DL, Ty,
436  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
437  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
438  }
439 
440  // This method creates the following nodes, which are necessary for
441  // computing a symbol's address in non-PIC mode for N64.
442  //
443  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
444  // 16), %lo(%sym))
445  //
446  // FIXME: This method is not efficent for (micro)MIPS64R6.
447  template <class NodeTy>
448  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
449  SelectionDAG &DAG) const {
450  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
451  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
452 
453  SDValue Highest =
454  DAG.getNode(MipsISD::Highest, DL, Ty,
455  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
456  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
457  SDValue HigherPart =
458  DAG.getNode(ISD::ADD, DL, Ty, Highest,
459  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
460  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
461  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
462  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
463  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
464  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
465 
466  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
467  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
468  }
469 
470  // This method creates the following nodes, which are necessary for
471  // computing a symbol's address using gp-relative addressing:
472  //
473  // (add $gp, %gp_rel(sym))
474  template <class NodeTy>
475  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
476  SelectionDAG &DAG, bool IsN64) const {
477  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
478  return DAG.getNode(
479  ISD::ADD, DL, Ty,
480  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
481  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
482  }
483 
484  /// This function fills Ops, which is the list of operands that will later
485  /// be used when a function call node is created. It also generates
486  /// copyToReg nodes to set up argument registers.
487  virtual void
488  getOpndList(SmallVectorImpl<SDValue> &Ops,
489  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
490  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
491  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
492  SDValue Chain) const;
493 
494  protected:
495  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
496  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
497 
498  // Subtarget Info
500  // Cache the ABI from the TargetMachine, we use it everywhere.
501  const MipsABIInfo &ABI;
502 
503  private:
504  // Create a TargetGlobalAddress node.
505  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
506  unsigned Flag) const;
507 
508  // Create a TargetExternalSymbol node.
509  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
510  unsigned Flag) const;
511 
512  // Create a TargetBlockAddress node.
513  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
514  unsigned Flag) const;
515 
516  // Create a TargetJumpTable node.
517  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
518  unsigned Flag) const;
519 
520  // Create a TargetConstantPool node.
521  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
522  unsigned Flag) const;
523 
524  // Lower Operand helpers
525  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
526  CallingConv::ID CallConv, bool isVarArg,
528  const SDLoc &dl, SelectionDAG &DAG,
529  SmallVectorImpl<SDValue> &InVals,
531 
532  // Lower Operand specifics
533  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
534  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
549  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
550  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
551  bool IsSRA) const;
552  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
554 
555  /// isEligibleForTailCallOptimization - Check whether the call is eligible
556  /// for tail call optimization.
557  virtual bool
558  isEligibleForTailCallOptimization(const CCState &CCInfo,
559  unsigned NextStackOffset,
560  const MipsFunctionInfo &FI) const = 0;
561 
562  /// copyByValArg - Copy argument registers which were used to pass a byval
563  /// argument to the stack. Create a stack frame object for the byval
564  /// argument.
565  void copyByValRegs(SDValue Chain, const SDLoc &DL,
566  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
567  const ISD::ArgFlagsTy &Flags,
568  SmallVectorImpl<SDValue> &InVals,
569  const Argument *FuncArg, unsigned FirstReg,
570  unsigned LastReg, const CCValAssign &VA,
571  MipsCCState &State) const;
572 
573  /// passByValArg - Pass a byval argument in registers or on stack.
574  void passByValArg(SDValue Chain, const SDLoc &DL,
575  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
576  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
578  unsigned FirstReg, unsigned LastReg,
579  const ISD::ArgFlagsTy &Flags, bool isLittle,
580  const CCValAssign &VA) const;
581 
582  /// writeVarArgRegs - Write variable function arguments passed in registers
583  /// to the stack. Also create a stack frame object for the first variable
584  /// argument.
585  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
586  const SDLoc &DL, SelectionDAG &DAG,
587  CCState &State) const;
588 
589  SDValue
590  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
592  const SDLoc &dl, SelectionDAG &DAG,
593  SmallVectorImpl<SDValue> &InVals) const override;
594 
595  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
596  SDValue Arg, const SDLoc &DL, bool IsTailCall,
597  SelectionDAG &DAG) const;
598 
600  SmallVectorImpl<SDValue> &InVals) const override;
601 
602  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
603  bool isVarArg,
605  LLVMContext &Context) const override;
606 
607  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
609  const SmallVectorImpl<SDValue> &OutVals,
610  const SDLoc &dl, SelectionDAG &DAG) const override;
611 
613  const SDLoc &DL, SelectionDAG &DAG) const;
614 
615  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
616 
617  // Inline asm support
618  ConstraintType getConstraintType(StringRef Constraint) const override;
619 
620  /// Examine constraint string and operand type and determine a weight value.
621  /// The operand object must already have been set up with the operand type.
622  ConstraintWeight getSingleConstraintMatchWeight(
623  AsmOperandInfo &info, const char *constraint) const override;
624 
625  /// This function parses registers that appear in inline-asm constraints.
626  /// It returns pair (0, 0) on failure.
627  std::pair<unsigned, const TargetRegisterClass *>
628  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
629 
630  std::pair<unsigned, const TargetRegisterClass *>
631  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
632  StringRef Constraint, MVT VT) const override;
633 
634  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
635  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
636  /// true it means one of the asm constraint of the inline asm instruction
637  /// being processed is 'm'.
638  void LowerAsmOperandForConstraint(SDValue Op,
639  std::string &Constraint,
640  std::vector<SDValue> &Ops,
641  SelectionDAG &DAG) const override;
642 
643  unsigned
644  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
645  if (ConstraintCode == "R")
647  else if (ConstraintCode == "ZC")
649  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
650  }
651 
652  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
653  Type *Ty, unsigned AS,
654  Instruction *I = nullptr) const override;
655 
656  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
657 
658  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
659  unsigned SrcAlign,
660  bool IsMemset, bool ZeroMemset,
661  bool MemcpyStrSrc,
662  MachineFunction &MF) const override;
663 
664  /// isFPImmLegal - Returns true if the target can instruction select the
665  /// specified FP immediate natively. If false, the legalizer will
666  /// materialize the FP immediate as a load from a constant pool.
667  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
668 
669  unsigned getJumpTableEncoding() const override;
670  bool useSoftFloat() const override;
671 
672  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
673  return true;
674  }
675 
676  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
677  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
678  MachineBasicBlock *BB,
679  unsigned Size, unsigned DstReg,
680  unsigned SrcRec) const;
681 
682  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
683  MachineBasicBlock *BB) const;
684  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
685  MachineBasicBlock *BB,
686  unsigned Size) const;
687  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
688  MachineBasicBlock *BB) const;
689  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
690  MachineBasicBlock *BB,
691  unsigned Size) const;
692  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
693  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
694  bool isFPCmp, unsigned Opc) const;
695  };
696 
697  /// Create MipsTargetLowering objects.
698  const MipsTargetLowering *
700  const MipsSubtarget &STI);
701  const MipsTargetLowering *
703  const MipsSubtarget &STI);
704 
705 namespace Mips {
706 
708  const TargetLibraryInfo *libInfo);
709 
710 } // end namespace Mips
711 
712 } // end namespace llvm
713 
714 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:829
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
const MipsSubtarget & Subtarget
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
Shift and rotation operations.
Definition: ISDOpcodes.h:380
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:836
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:60
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MipsABIInfo & ABI
Conversion operators.
Definition: ISDOpcodes.h:435
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.