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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 
20 #include "Mips.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/IR/Type.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <deque>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class Argument;
43 class CCState;
44 class CCValAssign;
45 class FastISel;
46 class FunctionLoweringInfo;
47 class MachineBasicBlock;
48 class MachineFrameInfo;
49 class MachineInstr;
50 class MipsCCState;
51 class MipsFunctionInfo;
52 class MipsSubtarget;
53 class MipsTargetMachine;
54 class TargetLibraryInfo;
55 class TargetRegisterClass;
56 
57  namespace MipsISD {
58 
59  enum NodeType : unsigned {
60  // Start the numbering from where ISD NodeType finishes.
62 
63  // Jump and link (call)
65 
66  // Tail call
68 
69  // Get the Highest (63-48) 16 bits from a 64-bit immediate
71 
72  // Get the Higher (47-32) 16 bits from a 64-bit immediate
74 
75  // Get the High 16 bits from a 32/64-bit immediate
76  // No relation with Mips Hi register
77  Hi,
78 
79  // Get the Lower 16 bits from a 32/64-bit immediate
80  // No relation with Mips Lo register
81  Lo,
82 
83  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
85 
86  // Get the High 16 bits from a 32-bit immediate for accessing TLS.
88 
89  // Handle gp_rel (small data/bss sections) relocation.
91 
92  // Thread Pointer
94 
95  // Vector Floating Point Multiply and Subtract
96  FMS,
97 
98  // Floating Point Branch Conditional
100 
101  // Floating Point Compare
103 
104  // Floating point select
106 
107  // Node used to generate an MTC1 i32 to f64 instruction
109 
110  // Floating Point Conditional Moves
113 
114  // FP-to-int truncation node.
116 
117  // Return
119 
120  // Interrupt, exception, error trap Return
122 
123  // Software Exception Return.
125 
126  // Node used to extract integer from accumulator.
129 
130  // Node used to insert integers to accumulator.
132 
133  // Mult nodes.
136 
137  // MAdd/Sub nodes
142 
143  // DivRem(u)
148 
151 
153 
155 
157 
161 
162  // EXTR.W instrinsic nodes.
171 
172  // DPA.W intrinsic nodes.
195 
202 
203  // DSP shift nodes.
207 
208  // DSP setcc and select_cc nodes.
211 
212  // Vector comparisons.
213  // These take a vector and return a boolean.
218 
219  // These take a vector and return a vector bitmask.
225 
226  // Vector Shuffle with mask as an operand
227  VSHF, // Generic shuffle
228  SHF, // 4-element set shuffle.
229  ILVEV, // Interleave even elements
230  ILVOD, // Interleave odd elements
231  ILVL, // Interleave left elements
232  ILVR, // Interleave right elements
233  PCKEV, // Pack even elements
234  PCKOD, // Pack odd elements
235 
236  // Vector Lane Copy
237  INSVE, // Copy element from one vector to another
238 
239  // Combined (XOR (OR $a, $b), -1)
241 
242  // Extended vector element extraction
245 
246  // Load/Store Left/Right nodes.
255  };
256 
257  } // ene namespace MipsISD
258 
259  //===--------------------------------------------------------------------===//
260  // TargetLowering Implementation
261  //===--------------------------------------------------------------------===//
262 
264  bool isMicroMips;
265 
266  public:
267  explicit MipsTargetLowering(const MipsTargetMachine &TM,
268  const MipsSubtarget &STI);
269 
270  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
271  const MipsSubtarget &STI);
272 
273  /// createFastISel - This method returns a target specific FastISel object,
274  /// or null if the target does not support "fast" ISel.
276  const TargetLibraryInfo *libInfo) const override;
277 
278  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
279  return MVT::i32;
280  }
281 
282  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
283  ISD::NodeType) const override;
284 
285  bool isCheapToSpeculateCttz() const override;
286  bool isCheapToSpeculateCtlz() const override;
287  bool shouldFoldConstantShiftPairToMask(const SDNode *N,
288  CombineLevel Level) const override;
289 
290  /// Return the register type for a given MVT, ensuring vectors are treated
291  /// as a series of gpr sized integers.
292  MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
293  EVT VT) const override;
294 
295  /// Return the number of registers for a given MVT, ensuring vectors are
296  /// treated as a series of gpr sized integers.
297  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
298  CallingConv::ID CC,
299  EVT VT) const override;
300 
301  /// Break down vectors to the correct number of gpr sized integers.
302  unsigned getVectorTypeBreakdownForCallingConv(
303  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
304  unsigned &NumIntermediates, MVT &RegisterVT) const override;
305 
306  /// Return the correct alignment for the current calling convention.
308  DataLayout DL) const override {
309  if (ArgTy->isVectorTy())
310  return std::min(DL.getABITypeAlignment(ArgTy), 8U);
311  return DL.getABITypeAlignment(ArgTy);
312  }
313 
315  return ISD::SIGN_EXTEND;
316  }
317 
318  void LowerOperationWrapper(SDNode *N,
320  SelectionDAG &DAG) const override;
321 
322  /// LowerOperation - Provide custom lowering hooks for some operations.
323  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
324 
325  /// ReplaceNodeResults - Replace the results of node with an illegal result
326  /// type with new values built out of custom code.
327  ///
328  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
329  SelectionDAG &DAG) const override;
330 
331  /// getTargetNodeName - This method returns the name of a target specific
332  // DAG node.
333  const char *getTargetNodeName(unsigned Opcode) const override;
334 
335  /// getSetCCResultType - get the ISD::SETCC result ValueType
336  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
337  EVT VT) const override;
338 
339  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
340 
342  EmitInstrWithCustomInserter(MachineInstr &MI,
343  MachineBasicBlock *MBB) const override;
344 
345  void AdjustInstrPostInstrSelection(MachineInstr &MI,
346  SDNode *Node) const override;
347 
348  void HandleByVal(CCState *, unsigned &, unsigned) const override;
349 
350  unsigned getRegisterByName(const char* RegName, EVT VT,
351  SelectionDAG &DAG) const override;
352 
353  /// If a physical register, this returns the register that receives the
354  /// exception address on entry to an EH pad.
355  unsigned
356  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
357  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
358  }
359 
360  /// If a physical register, this returns the register that receives the
361  /// exception typeid on entry to a landing pad.
362  unsigned
363  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
364  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
365  }
366 
367  /// Returns true if a cast between SrcAS and DestAS is a noop.
368  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
369  // Mips doesn't have any special address spaces so we just reserve
370  // the first 256 for software use (e.g. OpenCL) and treat casts
371  // between them as noops.
372  return SrcAS < 256 && DestAS < 256;
373  }
374 
375  bool isJumpTableRelative() const override {
376  return getTargetMachine().isPositionIndependent();
377  }
378 
379  CCAssignFn *CCAssignFnForCall() const;
380 
381  CCAssignFn *CCAssignFnForReturn() const;
382 
383  protected:
384  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
385 
386  // This method creates the following nodes, which are necessary for
387  // computing a local symbol's address:
388  //
389  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
390  template <class NodeTy>
391  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
392  bool IsN32OrN64) const {
393  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
394  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
395  getTargetNode(N, Ty, DAG, GOTFlag));
396  SDValue Load =
397  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
399  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
400  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
401  getTargetNode(N, Ty, DAG, LoFlag));
402  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
403  }
404 
405  // This method creates the following nodes, which are necessary for
406  // computing a global symbol's address:
407  //
408  // (load (wrapper $gp, %got(sym)))
409  template <class NodeTy>
410  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
411  unsigned Flag, SDValue Chain,
412  const MachinePointerInfo &PtrInfo) const {
413  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
414  getTargetNode(N, Ty, DAG, Flag));
415  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
416  }
417 
418  // This method creates the following nodes, which are necessary for
419  // computing a global symbol's address in large-GOT mode:
420  //
421  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
422  template <class NodeTy>
423  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
424  SelectionDAG &DAG, unsigned HiFlag,
425  unsigned LoFlag, SDValue Chain,
426  const MachinePointerInfo &PtrInfo) const {
427  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
428  getTargetNode(N, Ty, DAG, HiFlag));
429  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
430  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
431  getTargetNode(N, Ty, DAG, LoFlag));
432  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
433  }
434 
435  // This method creates the following nodes, which are necessary for
436  // computing a symbol's address in non-PIC mode:
437  //
438  // (add %hi(sym), %lo(sym))
439  //
440  // This method covers O32, N32 and N64 in sym32 mode.
441  template <class NodeTy>
442  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
443  SelectionDAG &DAG) const {
444  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
445  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
446  return DAG.getNode(ISD::ADD, DL, Ty,
447  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
448  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
449  }
450 
451  // This method creates the following nodes, which are necessary for
452  // computing a symbol's address in non-PIC mode for N64.
453  //
454  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
455  // 16), %lo(%sym))
456  //
457  // FIXME: This method is not efficent for (micro)MIPS64R6.
458  template <class NodeTy>
459  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
460  SelectionDAG &DAG) const {
461  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
462  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
463 
464  SDValue Highest =
465  DAG.getNode(MipsISD::Highest, DL, Ty,
466  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
468  SDValue HigherPart =
469  DAG.getNode(ISD::ADD, DL, Ty, Highest,
470  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
471  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
472  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
473  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
474  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
475  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
476 
477  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
478  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
479  }
480 
481  // This method creates the following nodes, which are necessary for
482  // computing a symbol's address using gp-relative addressing:
483  //
484  // (add $gp, %gp_rel(sym))
485  template <class NodeTy>
486  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
487  SelectionDAG &DAG, bool IsN64) const {
489  return DAG.getNode(
490  ISD::ADD, DL, Ty,
491  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
492  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
493  }
494 
495  /// This function fills Ops, which is the list of operands that will later
496  /// be used when a function call node is created. It also generates
497  /// copyToReg nodes to set up argument registers.
498  virtual void
499  getOpndList(SmallVectorImpl<SDValue> &Ops,
500  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
501  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
502  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
503  SDValue Chain) const;
504 
505  protected:
506  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
507  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
508 
509  // Subtarget Info
511  // Cache the ABI from the TargetMachine, we use it everywhere.
512  const MipsABIInfo &ABI;
513 
514  private:
515  // Create a TargetGlobalAddress node.
517  unsigned Flag) const;
518 
519  // Create a TargetExternalSymbol node.
521  unsigned Flag) const;
522 
523  // Create a TargetBlockAddress node.
525  unsigned Flag) const;
526 
527  // Create a TargetJumpTable node.
529  unsigned Flag) const;
530 
531  // Create a TargetConstantPool node.
533  unsigned Flag) const;
534 
535  // Lower Operand helpers
536  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
537  CallingConv::ID CallConv, bool isVarArg,
539  const SDLoc &dl, SelectionDAG &DAG,
540  SmallVectorImpl<SDValue> &InVals,
542 
543  // Lower Operand specifics
544  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
555  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
556  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
557  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
558  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
559  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
560  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
561  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
562  bool IsSRA) const;
563  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
564  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
565 
566  /// isEligibleForTailCallOptimization - Check whether the call is eligible
567  /// for tail call optimization.
568  virtual bool
569  isEligibleForTailCallOptimization(const CCState &CCInfo,
570  unsigned NextStackOffset,
571  const MipsFunctionInfo &FI) const = 0;
572 
573  /// copyByValArg - Copy argument registers which were used to pass a byval
574  /// argument to the stack. Create a stack frame object for the byval
575  /// argument.
576  void copyByValRegs(SDValue Chain, const SDLoc &DL,
577  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
578  const ISD::ArgFlagsTy &Flags,
579  SmallVectorImpl<SDValue> &InVals,
580  const Argument *FuncArg, unsigned FirstReg,
581  unsigned LastReg, const CCValAssign &VA,
582  MipsCCState &State) const;
583 
584  /// passByValArg - Pass a byval argument in registers or on stack.
585  void passByValArg(SDValue Chain, const SDLoc &DL,
586  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
587  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
589  unsigned FirstReg, unsigned LastReg,
590  const ISD::ArgFlagsTy &Flags, bool isLittle,
591  const CCValAssign &VA) const;
592 
593  /// writeVarArgRegs - Write variable function arguments passed in registers
594  /// to the stack. Also create a stack frame object for the first variable
595  /// argument.
596  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
597  const SDLoc &DL, SelectionDAG &DAG,
598  CCState &State) const;
599 
600  SDValue
601  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
603  const SDLoc &dl, SelectionDAG &DAG,
604  SmallVectorImpl<SDValue> &InVals) const override;
605 
606  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
607  SDValue Arg, const SDLoc &DL, bool IsTailCall,
608  SelectionDAG &DAG) const;
609 
611  SmallVectorImpl<SDValue> &InVals) const override;
612 
613  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
614  bool isVarArg,
616  LLVMContext &Context) const override;
617 
618  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
620  const SmallVectorImpl<SDValue> &OutVals,
621  const SDLoc &dl, SelectionDAG &DAG) const override;
622 
624  const SDLoc &DL, SelectionDAG &DAG) const;
625 
626  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
627 
628  // Inline asm support
629  ConstraintType getConstraintType(StringRef Constraint) const override;
630 
631  /// Examine constraint string and operand type and determine a weight value.
632  /// The operand object must already have been set up with the operand type.
633  ConstraintWeight getSingleConstraintMatchWeight(
634  AsmOperandInfo &info, const char *constraint) const override;
635 
636  /// This function parses registers that appear in inline-asm constraints.
637  /// It returns pair (0, 0) on failure.
638  std::pair<unsigned, const TargetRegisterClass *>
639  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
640 
641  std::pair<unsigned, const TargetRegisterClass *>
642  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
643  StringRef Constraint, MVT VT) const override;
644 
645  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
646  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
647  /// true it means one of the asm constraint of the inline asm instruction
648  /// being processed is 'm'.
649  void LowerAsmOperandForConstraint(SDValue Op,
650  std::string &Constraint,
651  std::vector<SDValue> &Ops,
652  SelectionDAG &DAG) const override;
653 
654  unsigned
655  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
656  if (ConstraintCode == "R")
658  else if (ConstraintCode == "ZC")
660  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
661  }
662 
663  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
664  Type *Ty, unsigned AS,
665  Instruction *I = nullptr) const override;
666 
667  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
668 
669  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
670  unsigned SrcAlign,
671  bool IsMemset, bool ZeroMemset,
672  bool MemcpyStrSrc,
673  const AttributeList &FuncAttributes) const override;
674 
675  /// isFPImmLegal - Returns true if the target can instruction select the
676  /// specified FP immediate natively. If false, the legalizer will
677  /// materialize the FP immediate as a load from a constant pool.
678  bool isFPImmLegal(const APFloat &Imm, EVT VT,
679  bool ForCodeSize) const override;
680 
681  unsigned getJumpTableEncoding() const override;
682  bool useSoftFloat() const override;
683 
684  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
685  return true;
686  }
687 
688  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
689  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
690  MachineBasicBlock *BB,
691  unsigned Size, unsigned DstReg,
692  unsigned SrcRec) const;
693 
694  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
695  MachineBasicBlock *BB) const;
696  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
697  MachineBasicBlock *BB,
698  unsigned Size) const;
699  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
700  MachineBasicBlock *BB) const;
701  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
702  MachineBasicBlock *BB,
703  unsigned Size) const;
704  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
705  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
706  bool isFPCmp, unsigned Opc) const;
707  MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
708  MachineBasicBlock *BB) const;
709  };
710 
711  /// Create MipsTargetLowering objects.
712  const MipsTargetLowering *
714  const MipsSubtarget &STI);
715  const MipsTargetLowering *
717  const MipsSubtarget &STI);
718 
719 namespace Mips {
720 
722  const TargetLibraryInfo *libInfo);
723 
724 } // end namespace Mips
725 
726 } // end namespace llvm
727 
728 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
LLVMContext & Context
const MipsSubtarget & Subtarget
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:84
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
Shift and rotation operations.
Definition: ISDOpcodes.h:434
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:467
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:51
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:404
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:47
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
This is an important base class in LLVM.
Definition: Constant.h:41
CombineLevel
Definition: DAGCombine.h:15
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:33
static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:37
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:746
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:920
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
uint32_t Size
Definition: Profile.cpp:46
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
const MipsABIInfo & ABI
Conversion operators.
Definition: ISDOpcodes.h:489
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.