LLVM 19.0.0git
MipsISelLowering.h
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1//===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Mips uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16
20#include "Mips.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/InlineAsm.h"
31#include "llvm/IR/Type.h"
33#include <algorithm>
34#include <deque>
35#include <utility>
36#include <vector>
37
38namespace llvm {
39
40class Argument;
41class FastISel;
42class FunctionLoweringInfo;
43class MachineBasicBlock;
44class MachineFrameInfo;
45class MachineInstr;
46class MipsCCState;
47class MipsFunctionInfo;
48class MipsSubtarget;
49class MipsTargetMachine;
50class TargetLibraryInfo;
51class TargetRegisterClass;
52
53 namespace MipsISD {
54
55 enum NodeType : unsigned {
56 // Start the numbering from where ISD NodeType finishes.
58
59 // Jump and link (call)
61
62 // Tail call
64
65 // Get the Highest (63-48) 16 bits from a 64-bit immediate
67
68 // Get the Higher (47-32) 16 bits from a 64-bit immediate
70
71 // Get the High 16 bits from a 32/64-bit immediate
72 // No relation with Mips Hi register
74
75 // Get the Lower 16 bits from a 32/64-bit immediate
76 // No relation with Mips Lo register
78
79 // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
81
82 // Get the High 16 bits from a 32-bit immediate for accessing TLS.
84
85 // Handle gp_rel (small data/bss sections) relocation.
87
88 // Thread Pointer
90
91 // Vector Floating Point Multiply and Subtract
93
94 // Floating Point Branch Conditional
96
97 // Floating Point Compare
99
100 // Floating point Abs
102
103 // Floating point select
105
106 // Node used to generate an MTC1 i32 to f64 instruction
108
109 // Floating Point Conditional Moves
112
113 // FP-to-int truncation node.
115
116 // Return
118
119 // Interrupt, exception, error trap Return
121
122 // Software Exception Return.
124
125 // Node used to extract integer from accumulator.
128
129 // Node used to insert integers to accumulator.
131
132 // Mult nodes.
135
136 // MAdd/Sub nodes
141
142 // DivRem(u)
147
150
152
154
156
160
161 // EXTR.W intrinsic nodes.
170
171 // DPA.W intrinsic nodes.
194
201
202 // DSP shift nodes.
206
207 // DSP setcc and select_cc nodes.
210
211 // Vector comparisons.
212 // These take a vector and return a boolean.
217
218 // These take a vector and return a vector bitmask.
224
225 // Vector Shuffle with mask as an operand
226 VSHF, // Generic shuffle
227 SHF, // 4-element set shuffle.
228 ILVEV, // Interleave even elements
229 ILVOD, // Interleave odd elements
230 ILVL, // Interleave left elements
231 ILVR, // Interleave right elements
232 PCKEV, // Pack even elements
233 PCKOD, // Pack odd elements
234
235 // Vector Lane Copy
236 INSVE, // Copy element from one vector to another
237
238 // Combined (XOR (OR $a, $b), -1)
240
241 // Extended vector element extraction
244
245 // Double select nodes for machines without conditional-move.
248
249 // Load/Store Left/Right nodes.
257 SDR
258 };
259
260 } // ene namespace MipsISD
261
262 //===--------------------------------------------------------------------===//
263 // TargetLowering Implementation
264 //===--------------------------------------------------------------------===//
265
267 bool isMicroMips;
268
269 public:
271 const MipsSubtarget &STI);
272
273 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
274 const MipsSubtarget &STI);
275
276 /// createFastISel - This method returns a target specific FastISel object,
277 /// or null if the target does not support "fast" ISel.
279 const TargetLibraryInfo *libInfo) const override;
280
281 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
282 return MVT::i32;
283 }
284
286 ISD::NodeType) const override;
287
288 bool isCheapToSpeculateCttz(Type *Ty) const override;
289 bool isCheapToSpeculateCtlz(Type *Ty) const override;
290 bool hasBitTest(SDValue X, SDValue Y) const override;
292 CombineLevel Level) const override;
293
294 /// Return the register type for a given MVT, ensuring vectors are treated
295 /// as a series of gpr sized integers.
297 EVT VT) const override;
298
299 /// Return the number of registers for a given MVT, ensuring vectors are
300 /// treated as a series of gpr sized integers.
303 EVT VT) const override;
304
305 /// Break down vectors to the correct number of gpr sized integers.
307 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
308 unsigned &NumIntermediates, MVT &RegisterVT) const override;
309
310 /// Return the correct alignment for the current calling convention.
312 const DataLayout &DL) const override {
313 const Align ABIAlign = DL.getABITypeAlign(ArgTy);
314 if (ArgTy->isVectorTy())
315 return std::min(ABIAlign, Align(8));
316 return ABIAlign;
317 }
318
320 return ISD::SIGN_EXTEND;
321 }
322
323 /// LowerOperation - Provide custom lowering hooks for some operations.
324 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
325
326 /// ReplaceNodeResults - Replace the results of node with an illegal result
327 /// type with new values built out of custom code.
328 ///
330 SelectionDAG &DAG) const override;
331
332 /// getTargetNodeName - This method returns the name of a target specific
333 // DAG node.
334 const char *getTargetNodeName(unsigned Opcode) const override;
335
336 /// getSetCCResultType - get the ISD::SETCC result ValueType
338 EVT VT) const override;
339
340 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
341
344 MachineBasicBlock *MBB) const override;
345
347 SDNode *Node) const override;
348
349 void HandleByVal(CCState *, unsigned &, Align) const override;
350
351 Register getRegisterByName(const char* RegName, LLT VT,
352 const MachineFunction &MF) const override;
353
354 /// If a physical register, this returns the register that receives the
355 /// exception address on entry to an EH pad.
357 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
358 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
359 }
360
361 /// If a physical register, this returns the register that receives the
362 /// exception typeid on entry to a landing pad.
364 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
365 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
366 }
367
368 bool isJumpTableRelative() const override {
370 }
371
373
375
376 protected:
377 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
378
379 // This method creates the following nodes, which are necessary for
380 // computing a local symbol's address:
381 //
382 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
383 template <class NodeTy>
384 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
385 bool IsN32OrN64) const {
386 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
387 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
388 getTargetNode(N, Ty, DAG, GOTFlag));
389 SDValue Load =
390 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
392 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
393 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
394 getTargetNode(N, Ty, DAG, LoFlag));
395 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
396 }
397
398 // This method creates the following nodes, which are necessary for
399 // computing a global symbol's address:
400 //
401 // (load (wrapper $gp, %got(sym)))
402 template <class NodeTy>
403 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
404 unsigned Flag, SDValue Chain,
405 const MachinePointerInfo &PtrInfo) const {
406 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
407 getTargetNode(N, Ty, DAG, Flag));
408 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
409 }
410
411 // This method creates the following nodes, which are necessary for
412 // computing a global symbol's address in large-GOT mode:
413 //
414 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
415 template <class NodeTy>
417 SelectionDAG &DAG, unsigned HiFlag,
418 unsigned LoFlag, SDValue Chain,
419 const MachinePointerInfo &PtrInfo) const {
421 getTargetNode(N, Ty, DAG, HiFlag));
422 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
424 getTargetNode(N, Ty, DAG, LoFlag));
425 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
426 }
427
428 // This method creates the following nodes, which are necessary for
429 // computing a symbol's address in non-PIC mode:
430 //
431 // (add %hi(sym), %lo(sym))
432 //
433 // This method covers O32, N32 and N64 in sym32 mode.
434 template <class NodeTy>
435 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
436 SelectionDAG &DAG) const {
437 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
438 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
439 return DAG.getNode(ISD::ADD, DL, Ty,
440 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
441 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
442 }
443
444 // This method creates the following nodes, which are necessary for
445 // computing a symbol's address in non-PIC mode for N64.
446 //
447 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
448 // 16), %lo(%sym))
449 //
450 // FIXME: This method is not efficent for (micro)MIPS64R6.
451 template <class NodeTy>
452 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
453 SelectionDAG &DAG) const {
454 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
455 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
456
457 SDValue Highest =
458 DAG.getNode(MipsISD::Highest, DL, Ty,
459 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
460 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
461 SDValue HigherPart =
462 DAG.getNode(ISD::ADD, DL, Ty, Highest,
463 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
464 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
465 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
466 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
467 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
468 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
469
470 return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
471 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
472 }
473
474 // This method creates the following nodes, which are necessary for
475 // computing a symbol's address using gp-relative addressing:
476 //
477 // (add $gp, %gp_rel(sym))
478 template <class NodeTy>
479 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
480 SelectionDAG &DAG, bool IsN64) const {
481 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
482 return DAG.getNode(
483 ISD::ADD, DL, Ty,
484 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
485 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
486 }
487
488 /// This function fills Ops, which is the list of operands that will later
489 /// be used when a function call node is created. It also generates
490 /// copyToReg nodes to set up argument registers.
491 virtual void
493 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
494 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
495 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
496 SDValue Chain) const;
497
498 protected:
501
502 // Subtarget Info
504 // Cache the ABI from the TargetMachine, we use it everywhere.
506
507 private:
508 // Create a TargetGlobalAddress node.
509 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
510 unsigned Flag) const;
511
512 // Create a TargetExternalSymbol node.
513 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
514 unsigned Flag) const;
515
516 // Create a TargetBlockAddress node.
517 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
518 unsigned Flag) const;
519
520 // Create a TargetJumpTable node.
521 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
522 unsigned Flag) const;
523
524 // Create a TargetConstantPool node.
525 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
526 unsigned Flag) const;
527
528 // Lower Operand helpers
529 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
530 CallingConv::ID CallConv, bool isVarArg,
532 const SDLoc &dl, SelectionDAG &DAG,
535
536 // Lower Operand specifics
537 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
543 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
544 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
549 SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
550 bool HasExtractInsert) const;
551 SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
552 bool HasExtractInsert) const;
553 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
554 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
555 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
556 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
557 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
558 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
559 bool IsSRA) const;
560 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
561 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
562
563 /// isEligibleForTailCallOptimization - Check whether the call is eligible
564 /// for tail call optimization.
565 virtual bool
566 isEligibleForTailCallOptimization(const CCState &CCInfo,
567 unsigned NextStackOffset,
568 const MipsFunctionInfo &FI) const = 0;
569
570 /// copyByValArg - Copy argument registers which were used to pass a byval
571 /// argument to the stack. Create a stack frame object for the byval
572 /// argument.
573 void copyByValRegs(SDValue Chain, const SDLoc &DL,
574 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
575 const ISD::ArgFlagsTy &Flags,
577 const Argument *FuncArg, unsigned FirstReg,
578 unsigned LastReg, const CCValAssign &VA,
579 MipsCCState &State) const;
580
581 /// passByValArg - Pass a byval argument in registers or on stack.
582 void passByValArg(SDValue Chain, const SDLoc &DL,
583 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
584 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
585 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
586 unsigned FirstReg, unsigned LastReg,
587 const ISD::ArgFlagsTy &Flags, bool isLittle,
588 const CCValAssign &VA) const;
589
590 /// writeVarArgRegs - Write variable function arguments passed in registers
591 /// to the stack. Also create a stack frame object for the first variable
592 /// argument.
593 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
594 const SDLoc &DL, SelectionDAG &DAG,
595 CCState &State) const;
596
597 SDValue
598 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
600 const SDLoc &dl, SelectionDAG &DAG,
601 SmallVectorImpl<SDValue> &InVals) const override;
602
603 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
604 SDValue Arg, const SDLoc &DL, bool IsTailCall,
605 SelectionDAG &DAG) const;
606
608 SmallVectorImpl<SDValue> &InVals) const override;
609
610 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
611 bool isVarArg,
613 LLVMContext &Context) const override;
614
615 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
617 const SmallVectorImpl<SDValue> &OutVals,
618 const SDLoc &dl, SelectionDAG &DAG) const override;
619
620 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
621 const SDLoc &DL, SelectionDAG &DAG) const;
622
623 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
624
625 // Inline asm support
626 ConstraintType getConstraintType(StringRef Constraint) const override;
627
628 /// Examine constraint string and operand type and determine a weight value.
629 /// The operand object must already have been set up with the operand type.
630 ConstraintWeight getSingleConstraintMatchWeight(
631 AsmOperandInfo &info, const char *constraint) const override;
632
633 /// This function parses registers that appear in inline-asm constraints.
634 /// It returns pair (0, 0) on failure.
635 std::pair<unsigned, const TargetRegisterClass *>
636 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
637
638 std::pair<unsigned, const TargetRegisterClass *>
639 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
640 StringRef Constraint, MVT VT) const override;
641
642 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
643 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
644 /// true it means one of the asm constraint of the inline asm instruction
645 /// being processed is 'm'.
646 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
647 std::vector<SDValue> &Ops,
648 SelectionDAG &DAG) const override;
649
651 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
652 if (ConstraintCode == "o")
654 if (ConstraintCode == "R")
656 if (ConstraintCode == "ZC")
658 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
659 }
660
661 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
662 Type *Ty, unsigned AS,
663 Instruction *I = nullptr) const override;
664
665 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
666
667 EVT getOptimalMemOpType(const MemOp &Op,
668 const AttributeList &FuncAttributes) const override;
669
670 /// isFPImmLegal - Returns true if the target can instruction select the
671 /// specified FP immediate natively. If false, the legalizer will
672 /// materialize the FP immediate as a load from a constant pool.
673 bool isFPImmLegal(const APFloat &Imm, EVT VT,
674 bool ForCodeSize) const override;
675
676 unsigned getJumpTableEncoding() const override;
677 bool useSoftFloat() const override;
678
679 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
680 return true;
681 }
682
683 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
684 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
685 MachineBasicBlock *BB,
686 unsigned Size, unsigned DstReg,
687 unsigned SrcRec) const;
688
689 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
690 MachineBasicBlock *BB) const;
691 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
692 MachineBasicBlock *BB,
693 unsigned Size) const;
694 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
695 MachineBasicBlock *BB) const;
696 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
697 MachineBasicBlock *BB,
698 unsigned Size) const;
699 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
700 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
701 bool isFPCmp, unsigned Opc) const;
702 MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
703 MachineBasicBlock *BB) const;
704 MachineBasicBlock *emitLDR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
705 MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
706 MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
707 MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
708 };
709
710 /// Create MipsTargetLowering objects.
711 const MipsTargetLowering *
712 createMips16TargetLowering(const MipsTargetMachine &TM,
713 const MipsSubtarget &STI);
714 const MipsTargetLowering *
715 createMipsSETargetLowering(const MipsTargetMachine &TM,
716 const MipsSubtarget &STI);
717
718namespace Mips {
719
720FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
721 const TargetLibraryInfo *libInfo);
722
723} // end namespace Mips
724
725} // end namespace llvm
726
727#endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
Function Alias Analysis Results
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Representation of each machine instruction.
Definition: MachineInstr.h:69
bool IsN64() const
Definition: MipsABIInfo.h:42
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
const MipsABIInfo & ABI
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
bool isJumpTableRelative() const override
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:554
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Provides information about what library functions are available for the current target.
const TargetMachine & getTargetMachine() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool isPositionIndependent() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1400
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1412
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
@ MO_GPREL
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
Definition: MipsBaseInfo.h:85
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Add
Sum of integers.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.