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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 
21 #include "Mips.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <deque>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class Argument;
43 class CCState;
44 class CCValAssign;
45 class FastISel;
46 class FunctionLoweringInfo;
47 class MachineBasicBlock;
48 class MachineFrameInfo;
49 class MachineInstr;
50 class MipsCCState;
51 class MipsFunctionInfo;
52 class MipsSubtarget;
53 class MipsTargetMachine;
54 class TargetLibraryInfo;
55 class TargetRegisterClass;
56 
57  namespace MipsISD {
58 
59  enum NodeType : unsigned {
60  // Start the numbering from where ISD NodeType finishes.
62 
63  // Jump and link (call)
65 
66  // Tail call
68 
69  // Get the Highest (63-48) 16 bits from a 64-bit immediate
71 
72  // Get the Higher (47-32) 16 bits from a 64-bit immediate
74 
75  // Get the High 16 bits from a 32/64-bit immediate
76  // No relation with Mips Hi register
77  Hi,
78 
79  // Get the Lower 16 bits from a 32/64-bit immediate
80  // No relation with Mips Lo register
81  Lo,
82 
83  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
85 
86  // Handle gp_rel (small data/bss sections) relocation.
88 
89  // Thread Pointer
91 
92  // Floating Point Branch Conditional
94 
95  // Floating Point Compare
97 
98  // Floating point select
100 
101  // Node used to generate an MTC1 i32 to f64 instruction
103 
104  // Floating Point Conditional Moves
107 
108  // FP-to-int truncation node.
110 
111  // Return
113 
114  // Interrupt, exception, error trap Return
116 
117  // Software Exception Return.
119 
120  // Node used to extract integer from accumulator.
123 
124  // Node used to insert integers to accumulator.
126 
127  // Mult nodes.
130 
131  // MAdd/Sub nodes
136 
137  // DivRem(u)
142 
145 
147 
149 
151 
155 
156  // EXTR.W instrinsic nodes.
165 
166  // DPA.W intrinsic nodes.
189 
196 
197  // DSP shift nodes.
201 
202  // DSP setcc and select_cc nodes.
205 
206  // Vector comparisons.
207  // These take a vector and return a boolean.
212 
213  // These take a vector and return a vector bitmask.
219 
220  // Vector Shuffle with mask as an operand
221  VSHF, // Generic shuffle
222  SHF, // 4-element set shuffle.
223  ILVEV, // Interleave even elements
224  ILVOD, // Interleave odd elements
225  ILVL, // Interleave left elements
226  ILVR, // Interleave right elements
227  PCKEV, // Pack even elements
228  PCKOD, // Pack odd elements
229 
230  // Vector Lane Copy
231  INSVE, // Copy element from one vector to another
232 
233  // Combined (XOR (OR $a, $b), -1)
235 
236  // Extended vector element extraction
239 
240  // Load/Store Left/Right nodes.
249  };
250 
251  } // ene namespace MipsISD
252 
253  //===--------------------------------------------------------------------===//
254  // TargetLowering Implementation
255  //===--------------------------------------------------------------------===//
256 
258  bool isMicroMips;
259 
260  public:
261  explicit MipsTargetLowering(const MipsTargetMachine &TM,
262  const MipsSubtarget &STI);
263 
264  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
265  const MipsSubtarget &STI);
266 
267  /// createFastISel - This method returns a target specific FastISel object,
268  /// or null if the target does not support "fast" ISel.
270  const TargetLibraryInfo *libInfo) const override;
271 
272  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
273  return MVT::i32;
274  }
275 
276  bool isCheapToSpeculateCttz() const override;
277  bool isCheapToSpeculateCtlz() const override;
278 
279  /// Return the register type for a given MVT, ensuring vectors are treated
280  /// as a series of gpr sized integers.
281  MVT getRegisterTypeForCallingConv(MVT VT) const override;
282 
283  /// Return the register type for a given MVT, ensuring vectors are treated
284  /// as a series of gpr sized integers.
285  MVT getRegisterTypeForCallingConv(LLVMContext &Context,
286  EVT VT) const override;
287 
288  /// Return the number of registers for a given MVT, ensuring vectors are
289  /// treated as a series of gpr sized integers.
290  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
291  EVT VT) const override;
292 
293  /// Break down vectors to the correct number of gpr sized integers.
294  unsigned getVectorTypeBreakdownForCallingConv(
295  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
296  unsigned &NumIntermediates, MVT &RegisterVT) const override;
297 
298  /// Return the correct alignment for the current calling convention.
300  DataLayout DL) const override {
301  if (ArgTy->isVectorTy())
302  return std::min(DL.getABITypeAlignment(ArgTy), 8U);
303  return DL.getABITypeAlignment(ArgTy);
304  }
305 
307  return ISD::SIGN_EXTEND;
308  }
309 
310  void LowerOperationWrapper(SDNode *N,
312  SelectionDAG &DAG) const override;
313 
314  /// LowerOperation - Provide custom lowering hooks for some operations.
315  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
316 
317  /// ReplaceNodeResults - Replace the results of node with an illegal result
318  /// type with new values built out of custom code.
319  ///
320  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
321  SelectionDAG &DAG) const override;
322 
323  /// getTargetNodeName - This method returns the name of a target specific
324  // DAG node.
325  const char *getTargetNodeName(unsigned Opcode) const override;
326 
327  /// getSetCCResultType - get the ISD::SETCC result ValueType
328  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
329  EVT VT) const override;
330 
331  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
332 
334  EmitInstrWithCustomInserter(MachineInstr &MI,
335  MachineBasicBlock *MBB) const override;
336 
337  void HandleByVal(CCState *, unsigned &, unsigned) const override;
338 
339  unsigned getRegisterByName(const char* RegName, EVT VT,
340  SelectionDAG &DAG) const override;
341 
342  /// If a physical register, this returns the register that receives the
343  /// exception address on entry to an EH pad.
344  unsigned
345  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
346  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
347  }
348 
349  /// If a physical register, this returns the register that receives the
350  /// exception typeid on entry to a landing pad.
351  unsigned
352  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
353  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
354  }
355 
356  /// Returns true if a cast between SrcAS and DestAS is a noop.
357  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
358  // Mips doesn't have any special address spaces so we just reserve
359  // the first 256 for software use (e.g. OpenCL) and treat casts
360  // between them as noops.
361  return SrcAS < 256 && DestAS < 256;
362  }
363 
364  bool isJumpTableRelative() const override {
365  return getTargetMachine().isPositionIndependent();
366  }
367 
368  protected:
369  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
370 
371  // This method creates the following nodes, which are necessary for
372  // computing a local symbol's address:
373  //
374  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
375  template <class NodeTy>
376  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
377  bool IsN32OrN64) const {
378  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
379  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
380  getTargetNode(N, Ty, DAG, GOTFlag));
381  SDValue Load =
382  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
384  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
385  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
386  getTargetNode(N, Ty, DAG, LoFlag));
387  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
388  }
389 
390  // This method creates the following nodes, which are necessary for
391  // computing a global symbol's address:
392  //
393  // (load (wrapper $gp, %got(sym)))
394  template <class NodeTy>
395  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
396  unsigned Flag, SDValue Chain,
397  const MachinePointerInfo &PtrInfo) const {
398  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
399  getTargetNode(N, Ty, DAG, Flag));
400  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
401  }
402 
403  // This method creates the following nodes, which are necessary for
404  // computing a global symbol's address in large-GOT mode:
405  //
406  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
407  template <class NodeTy>
408  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
409  SelectionDAG &DAG, unsigned HiFlag,
410  unsigned LoFlag, SDValue Chain,
411  const MachinePointerInfo &PtrInfo) const {
412  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
413  getTargetNode(N, Ty, DAG, HiFlag));
414  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
415  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
416  getTargetNode(N, Ty, DAG, LoFlag));
417  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
418  }
419 
420  // This method creates the following nodes, which are necessary for
421  // computing a symbol's address in non-PIC mode:
422  //
423  // (add %hi(sym), %lo(sym))
424  //
425  // This method covers O32, N32 and N64 in sym32 mode.
426  template <class NodeTy>
427  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
428  SelectionDAG &DAG) const {
429  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
430  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
431  return DAG.getNode(ISD::ADD, DL, Ty,
432  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
433  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
434  }
435 
436  // This method creates the following nodes, which are necessary for
437  // computing a symbol's address in non-PIC mode for N64.
438  //
439  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
440  // 16), %lo(%sym))
441  //
442  // FIXME: This method is not efficent for (micro)MIPS64R6.
443  template <class NodeTy>
444  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
445  SelectionDAG &DAG) const {
446  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
447  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
448 
449  SDValue Highest =
450  DAG.getNode(MipsISD::Highest, DL, Ty,
451  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
452  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
453  SDValue HigherPart =
454  DAG.getNode(ISD::ADD, DL, Ty, Highest,
455  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
456  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
457  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
458  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
459  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
460  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
461 
462  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
463  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
464  }
465 
466  // This method creates the following nodes, which are necessary for
467  // computing a symbol's address using gp-relative addressing:
468  //
469  // (add $gp, %gp_rel(sym))
470  template <class NodeTy>
471  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
472  SelectionDAG &DAG, bool IsN64) const {
473  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
474  return DAG.getNode(
475  ISD::ADD, DL, Ty,
476  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
477  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
478  }
479 
480  /// This function fills Ops, which is the list of operands that will later
481  /// be used when a function call node is created. It also generates
482  /// copyToReg nodes to set up argument registers.
483  virtual void
484  getOpndList(SmallVectorImpl<SDValue> &Ops,
485  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
486  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
487  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
488  SDValue Chain) const;
489 
490  protected:
491  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
492  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
493 
494  // Subtarget Info
496  // Cache the ABI from the TargetMachine, we use it everywhere.
497  const MipsABIInfo &ABI;
498 
499  private:
500  // Create a TargetGlobalAddress node.
501  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
502  unsigned Flag) const;
503 
504  // Create a TargetExternalSymbol node.
505  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
506  unsigned Flag) const;
507 
508  // Create a TargetBlockAddress node.
509  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
510  unsigned Flag) const;
511 
512  // Create a TargetJumpTable node.
513  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
514  unsigned Flag) const;
515 
516  // Create a TargetConstantPool node.
517  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
518  unsigned Flag) const;
519 
520  // Lower Operand helpers
521  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
522  CallingConv::ID CallConv, bool isVarArg,
524  const SDLoc &dl, SelectionDAG &DAG,
525  SmallVectorImpl<SDValue> &InVals,
527 
528  // Lower Operand specifics
529  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
530  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
531  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
532  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
533  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
534  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
545  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
546  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
547  bool IsSRA) const;
548  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
550 
551  /// isEligibleForTailCallOptimization - Check whether the call is eligible
552  /// for tail call optimization.
553  virtual bool
554  isEligibleForTailCallOptimization(const CCState &CCInfo,
555  unsigned NextStackOffset,
556  const MipsFunctionInfo &FI) const = 0;
557 
558  /// copyByValArg - Copy argument registers which were used to pass a byval
559  /// argument to the stack. Create a stack frame object for the byval
560  /// argument.
561  void copyByValRegs(SDValue Chain, const SDLoc &DL,
562  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
563  const ISD::ArgFlagsTy &Flags,
564  SmallVectorImpl<SDValue> &InVals,
565  const Argument *FuncArg, unsigned FirstReg,
566  unsigned LastReg, const CCValAssign &VA,
567  MipsCCState &State) const;
568 
569  /// passByValArg - Pass a byval argument in registers or on stack.
570  void passByValArg(SDValue Chain, const SDLoc &DL,
571  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
572  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
574  unsigned FirstReg, unsigned LastReg,
575  const ISD::ArgFlagsTy &Flags, bool isLittle,
576  const CCValAssign &VA) const;
577 
578  /// writeVarArgRegs - Write variable function arguments passed in registers
579  /// to the stack. Also create a stack frame object for the first variable
580  /// argument.
581  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
582  const SDLoc &DL, SelectionDAG &DAG,
583  CCState &State) const;
584 
585  SDValue
586  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
588  const SDLoc &dl, SelectionDAG &DAG,
589  SmallVectorImpl<SDValue> &InVals) const override;
590 
591  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
592  SDValue Arg, const SDLoc &DL, bool IsTailCall,
593  SelectionDAG &DAG) const;
594 
596  SmallVectorImpl<SDValue> &InVals) const override;
597 
598  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
599  bool isVarArg,
601  LLVMContext &Context) const override;
602 
603  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
605  const SmallVectorImpl<SDValue> &OutVals,
606  const SDLoc &dl, SelectionDAG &DAG) const override;
607 
609  const SDLoc &DL, SelectionDAG &DAG) const;
610 
611  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
612 
613  // Inline asm support
614  ConstraintType getConstraintType(StringRef Constraint) const override;
615 
616  /// Examine constraint string and operand type and determine a weight value.
617  /// The operand object must already have been set up with the operand type.
618  ConstraintWeight getSingleConstraintMatchWeight(
619  AsmOperandInfo &info, const char *constraint) const override;
620 
621  /// This function parses registers that appear in inline-asm constraints.
622  /// It returns pair (0, 0) on failure.
623  std::pair<unsigned, const TargetRegisterClass *>
624  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
625 
626  std::pair<unsigned, const TargetRegisterClass *>
627  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
628  StringRef Constraint, MVT VT) const override;
629 
630  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
631  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
632  /// true it means one of the asm constraint of the inline asm instruction
633  /// being processed is 'm'.
634  void LowerAsmOperandForConstraint(SDValue Op,
635  std::string &Constraint,
636  std::vector<SDValue> &Ops,
637  SelectionDAG &DAG) const override;
638 
639  unsigned
640  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
641  if (ConstraintCode == "R")
643  else if (ConstraintCode == "ZC")
645  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
646  }
647 
648  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
649  Type *Ty, unsigned AS,
650  Instruction *I = nullptr) const override;
651 
652  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
653 
654  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
655  unsigned SrcAlign,
656  bool IsMemset, bool ZeroMemset,
657  bool MemcpyStrSrc,
658  MachineFunction &MF) const override;
659 
660  /// isFPImmLegal - Returns true if the target can instruction select the
661  /// specified FP immediate natively. If false, the legalizer will
662  /// materialize the FP immediate as a load from a constant pool.
663  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
664 
665  unsigned getJumpTableEncoding() const override;
666  bool useSoftFloat() const override;
667 
668  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
669  return true;
670  }
671 
672  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
673  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
674  MachineBasicBlock *BB,
675  unsigned Size, unsigned DstReg,
676  unsigned SrcRec) const;
677 
678  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
679  unsigned Size, unsigned BinOpcode,
680  bool Nand = false) const;
681  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
682  MachineBasicBlock *BB,
683  unsigned Size,
684  unsigned BinOpcode,
685  bool Nand = false) const;
686  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
687  MachineBasicBlock *BB,
688  unsigned Size) const;
689  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
690  MachineBasicBlock *BB,
691  unsigned Size) const;
692  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
693  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
694  bool isFPCmp, unsigned Opc) const;
695  };
696 
697  /// Create MipsTargetLowering objects.
698  const MipsTargetLowering *
700  const MipsSubtarget &STI);
701  const MipsTargetLowering *
703  const MipsSubtarget &STI);
704 
705 namespace Mips {
706 
708  const TargetLibraryInfo *libInfo);
709 
710 } // end namespace Mips
711 
712 } // end namespace llvm
713 
714 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
const MipsSubtarget & Subtarget
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
Function Alias Analysis Results
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
Shift and rotation operations.
Definition: ISDOpcodes.h:380
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:449
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:387
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:724
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:843
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:60
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MipsABIInfo & ABI
Conversion operators.
Definition: ISDOpcodes.h:443
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.