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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 
21 #include "Mips.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <deque>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class Argument;
43 class CCState;
44 class CCValAssign;
45 class FastISel;
46 class FunctionLoweringInfo;
47 class MachineBasicBlock;
48 class MachineFrameInfo;
49 class MachineInstr;
50 class MipsCCState;
51 class MipsFunctionInfo;
52 class MipsSubtarget;
53 class MipsTargetMachine;
54 class TargetLibraryInfo;
55 class TargetRegisterClass;
56 
57  namespace MipsISD {
58 
59  enum NodeType : unsigned {
60  // Start the numbering from where ISD NodeType finishes.
62 
63  // Jump and link (call)
65 
66  // Tail call
68 
69  // Get the Highest (63-48) 16 bits from a 64-bit immediate
71 
72  // Get the Higher (47-32) 16 bits from a 64-bit immediate
74 
75  // Get the High 16 bits from a 32/64-bit immediate
76  // No relation with Mips Hi register
77  Hi,
78 
79  // Get the Lower 16 bits from a 32/64-bit immediate
80  // No relation with Mips Lo register
81  Lo,
82 
83  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
85 
86  // Handle gp_rel (small data/bss sections) relocation.
88 
89  // Thread Pointer
91 
92  // Floating Point Branch Conditional
94 
95  // Floating Point Compare
97 
98  // Floating point select
100 
101  // Node used to generate an MTC1 i32 to f64 instruction
103 
104  // Floating Point Conditional Moves
107 
108  // FP-to-int truncation node.
110 
111  // Return
113 
114  // Interrupt, exception, error trap Return
116 
117  // Software Exception Return.
119 
120  // Node used to extract integer from accumulator.
123 
124  // Node used to insert integers to accumulator.
126 
127  // Mult nodes.
130 
131  // MAdd/Sub nodes
136 
137  // DivRem(u)
142 
145 
147 
149 
151 
155 
156  // EXTR.W instrinsic nodes.
165 
166  // DPA.W intrinsic nodes.
189 
196 
197  // DSP shift nodes.
201 
202  // DSP setcc and select_cc nodes.
205 
206  // Vector comparisons.
207  // These take a vector and return a boolean.
212 
213  // These take a vector and return a vector bitmask.
219 
220  // Element-wise vector max/min.
225 
226  // Vector Shuffle with mask as an operand
227  VSHF, // Generic shuffle
228  SHF, // 4-element set shuffle.
229  ILVEV, // Interleave even elements
230  ILVOD, // Interleave odd elements
231  ILVL, // Interleave left elements
232  ILVR, // Interleave right elements
233  PCKEV, // Pack even elements
234  PCKOD, // Pack odd elements
235 
236  // Vector Lane Copy
237  INSVE, // Copy element from one vector to another
238 
239  // Combined (XOR (OR $a, $b), -1)
241 
242  // Extended vector element extraction
245 
246  // Load/Store Left/Right nodes.
255  };
256 
257  } // ene namespace MipsISD
258 
259  //===--------------------------------------------------------------------===//
260  // TargetLowering Implementation
261  //===--------------------------------------------------------------------===//
262 
264  bool isMicroMips;
265 
266  public:
267  explicit MipsTargetLowering(const MipsTargetMachine &TM,
268  const MipsSubtarget &STI);
269 
270  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
271  const MipsSubtarget &STI);
272 
273  /// createFastISel - This method returns a target specific FastISel object,
274  /// or null if the target does not support "fast" ISel.
276  const TargetLibraryInfo *libInfo) const override;
277 
278  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
279  return MVT::i32;
280  }
281 
282  bool isCheapToSpeculateCttz() const override;
283  bool isCheapToSpeculateCtlz() const override;
284 
285  /// Return the register type for a given MVT, ensuring vectors are treated
286  /// as a series of gpr sized integers.
287  MVT getRegisterTypeForCallingConv(MVT VT) const override;
288 
289  /// Return the register type for a given MVT, ensuring vectors are treated
290  /// as a series of gpr sized integers.
291  MVT getRegisterTypeForCallingConv(LLVMContext &Context,
292  EVT VT) const override;
293 
294  /// Return the number of registers for a given MVT, ensuring vectors are
295  /// treated as a series of gpr sized integers.
296  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
297  EVT VT) const override;
298 
299  /// Break down vectors to the correct number of gpr sized integers.
300  unsigned getVectorTypeBreakdownForCallingConv(
301  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
302  unsigned &NumIntermediates, MVT &RegisterVT) const override;
303 
304  /// Return the correct alignment for the current calling convention.
306  DataLayout DL) const override {
307  if (ArgTy->isVectorTy())
308  return std::min(DL.getABITypeAlignment(ArgTy), 8U);
309  return DL.getABITypeAlignment(ArgTy);
310  }
311 
313  return ISD::SIGN_EXTEND;
314  }
315 
316  void LowerOperationWrapper(SDNode *N,
318  SelectionDAG &DAG) const override;
319 
320  /// LowerOperation - Provide custom lowering hooks for some operations.
321  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
322 
323  /// ReplaceNodeResults - Replace the results of node with an illegal result
324  /// type with new values built out of custom code.
325  ///
326  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
327  SelectionDAG &DAG) const override;
328 
329  /// getTargetNodeName - This method returns the name of a target specific
330  // DAG node.
331  const char *getTargetNodeName(unsigned Opcode) const override;
332 
333  /// getSetCCResultType - get the ISD::SETCC result ValueType
334  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
335  EVT VT) const override;
336 
337  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
338 
340  EmitInstrWithCustomInserter(MachineInstr &MI,
341  MachineBasicBlock *MBB) const override;
342 
343  void HandleByVal(CCState *, unsigned &, unsigned) const override;
344 
345  unsigned getRegisterByName(const char* RegName, EVT VT,
346  SelectionDAG &DAG) const override;
347 
348  /// If a physical register, this returns the register that receives the
349  /// exception address on entry to an EH pad.
350  unsigned
351  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
352  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
353  }
354 
355  /// If a physical register, this returns the register that receives the
356  /// exception typeid on entry to a landing pad.
357  unsigned
358  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
359  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
360  }
361 
362  /// Returns true if a cast between SrcAS and DestAS is a noop.
363  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
364  // Mips doesn't have any special address spaces so we just reserve
365  // the first 256 for software use (e.g. OpenCL) and treat casts
366  // between them as noops.
367  return SrcAS < 256 && DestAS < 256;
368  }
369 
370  bool isJumpTableRelative() const override {
371  return getTargetMachine().isPositionIndependent();
372  }
373 
374  protected:
375  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
376 
377  // This method creates the following nodes, which are necessary for
378  // computing a local symbol's address:
379  //
380  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
381  template <class NodeTy>
382  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
383  bool IsN32OrN64) const {
384  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
385  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
386  getTargetNode(N, Ty, DAG, GOTFlag));
387  SDValue Load =
388  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
390  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
391  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
392  getTargetNode(N, Ty, DAG, LoFlag));
393  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
394  }
395 
396  // This method creates the following nodes, which are necessary for
397  // computing a global symbol's address:
398  //
399  // (load (wrapper $gp, %got(sym)))
400  template <class NodeTy>
401  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
402  unsigned Flag, SDValue Chain,
403  const MachinePointerInfo &PtrInfo) const {
404  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
405  getTargetNode(N, Ty, DAG, Flag));
406  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
407  }
408 
409  // This method creates the following nodes, which are necessary for
410  // computing a global symbol's address in large-GOT mode:
411  //
412  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
413  template <class NodeTy>
414  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
415  SelectionDAG &DAG, unsigned HiFlag,
416  unsigned LoFlag, SDValue Chain,
417  const MachinePointerInfo &PtrInfo) const {
418  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
419  getTargetNode(N, Ty, DAG, HiFlag));
420  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
421  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
422  getTargetNode(N, Ty, DAG, LoFlag));
423  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
424  }
425 
426  // This method creates the following nodes, which are necessary for
427  // computing a symbol's address in non-PIC mode:
428  //
429  // (add %hi(sym), %lo(sym))
430  //
431  // This method covers O32, N32 and N64 in sym32 mode.
432  template <class NodeTy>
433  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
434  SelectionDAG &DAG) const {
435  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
436  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
437  return DAG.getNode(ISD::ADD, DL, Ty,
438  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
439  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
440  }
441 
442  // This method creates the following nodes, which are necessary for
443  // computing a symbol's address in non-PIC mode for N64.
444  //
445  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
446  // 16), %lo(%sym))
447  //
448  // FIXME: This method is not efficent for (micro)MIPS64R6.
449  template <class NodeTy>
450  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
451  SelectionDAG &DAG) const {
452  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
453  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
454 
455  SDValue Highest =
456  DAG.getNode(MipsISD::Highest, DL, Ty,
457  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
458  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
459  SDValue HigherPart =
460  DAG.getNode(ISD::ADD, DL, Ty, Highest,
461  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
462  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
463  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
464  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
465  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
466  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
467 
468  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
469  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
470  }
471 
472  // This method creates the following nodes, which are necessary for
473  // computing a symbol's address using gp-relative addressing:
474  //
475  // (add $gp, %gp_rel(sym))
476  template <class NodeTy>
477  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
478  SelectionDAG &DAG, bool IsN64) const {
479  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
480  return DAG.getNode(
481  ISD::ADD, DL, Ty,
482  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
483  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
484  }
485 
486  /// This function fills Ops, which is the list of operands that will later
487  /// be used when a function call node is created. It also generates
488  /// copyToReg nodes to set up argument registers.
489  virtual void
490  getOpndList(SmallVectorImpl<SDValue> &Ops,
491  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
492  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
493  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
494  SDValue Chain) const;
495 
496  protected:
497  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
498  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
499 
500  // Subtarget Info
502  // Cache the ABI from the TargetMachine, we use it everywhere.
503  const MipsABIInfo &ABI;
504 
505  private:
506  // Create a TargetGlobalAddress node.
507  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
508  unsigned Flag) const;
509 
510  // Create a TargetExternalSymbol node.
511  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
512  unsigned Flag) const;
513 
514  // Create a TargetBlockAddress node.
515  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
516  unsigned Flag) const;
517 
518  // Create a TargetJumpTable node.
519  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
520  unsigned Flag) const;
521 
522  // Create a TargetConstantPool node.
523  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
524  unsigned Flag) const;
525 
526  // Lower Operand helpers
527  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
528  CallingConv::ID CallConv, bool isVarArg,
530  const SDLoc &dl, SelectionDAG &DAG,
531  SmallVectorImpl<SDValue> &InVals,
533 
534  // Lower Operand specifics
535  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
551  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
552  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
553  bool IsSRA) const;
554  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
555  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
556 
557  /// isEligibleForTailCallOptimization - Check whether the call is eligible
558  /// for tail call optimization.
559  virtual bool
560  isEligibleForTailCallOptimization(const CCState &CCInfo,
561  unsigned NextStackOffset,
562  const MipsFunctionInfo &FI) const = 0;
563 
564  /// copyByValArg - Copy argument registers which were used to pass a byval
565  /// argument to the stack. Create a stack frame object for the byval
566  /// argument.
567  void copyByValRegs(SDValue Chain, const SDLoc &DL,
568  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
569  const ISD::ArgFlagsTy &Flags,
570  SmallVectorImpl<SDValue> &InVals,
571  const Argument *FuncArg, unsigned FirstReg,
572  unsigned LastReg, const CCValAssign &VA,
573  MipsCCState &State) const;
574 
575  /// passByValArg - Pass a byval argument in registers or on stack.
576  void passByValArg(SDValue Chain, const SDLoc &DL,
577  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
578  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
580  unsigned FirstReg, unsigned LastReg,
581  const ISD::ArgFlagsTy &Flags, bool isLittle,
582  const CCValAssign &VA) const;
583 
584  /// writeVarArgRegs - Write variable function arguments passed in registers
585  /// to the stack. Also create a stack frame object for the first variable
586  /// argument.
587  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
588  const SDLoc &DL, SelectionDAG &DAG,
589  CCState &State) const;
590 
591  SDValue
592  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
594  const SDLoc &dl, SelectionDAG &DAG,
595  SmallVectorImpl<SDValue> &InVals) const override;
596 
597  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
598  SDValue Arg, const SDLoc &DL, bool IsTailCall,
599  SelectionDAG &DAG) const;
600 
602  SmallVectorImpl<SDValue> &InVals) const override;
603 
604  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
605  bool isVarArg,
607  LLVMContext &Context) const override;
608 
609  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
611  const SmallVectorImpl<SDValue> &OutVals,
612  const SDLoc &dl, SelectionDAG &DAG) const override;
613 
615  const SDLoc &DL, SelectionDAG &DAG) const;
616 
617  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
618 
619  // Inline asm support
620  ConstraintType getConstraintType(StringRef Constraint) const override;
621 
622  /// Examine constraint string and operand type and determine a weight value.
623  /// The operand object must already have been set up with the operand type.
624  ConstraintWeight getSingleConstraintMatchWeight(
625  AsmOperandInfo &info, const char *constraint) const override;
626 
627  /// This function parses registers that appear in inline-asm constraints.
628  /// It returns pair (0, 0) on failure.
629  std::pair<unsigned, const TargetRegisterClass *>
630  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
631 
632  std::pair<unsigned, const TargetRegisterClass *>
633  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
634  StringRef Constraint, MVT VT) const override;
635 
636  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
637  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
638  /// true it means one of the asm constraint of the inline asm instruction
639  /// being processed is 'm'.
640  void LowerAsmOperandForConstraint(SDValue Op,
641  std::string &Constraint,
642  std::vector<SDValue> &Ops,
643  SelectionDAG &DAG) const override;
644 
645  unsigned
646  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
647  if (ConstraintCode == "R")
649  else if (ConstraintCode == "ZC")
651  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
652  }
653 
654  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
655  Type *Ty, unsigned AS,
656  Instruction *I = nullptr) const override;
657 
658  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
659 
660  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
661  unsigned SrcAlign,
662  bool IsMemset, bool ZeroMemset,
663  bool MemcpyStrSrc,
664  MachineFunction &MF) const override;
665 
666  /// isFPImmLegal - Returns true if the target can instruction select the
667  /// specified FP immediate natively. If false, the legalizer will
668  /// materialize the FP immediate as a load from a constant pool.
669  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
670 
671  unsigned getJumpTableEncoding() const override;
672  bool useSoftFloat() const override;
673 
674  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
675  return true;
676  }
677 
678  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
679  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
680  MachineBasicBlock *BB,
681  unsigned Size, unsigned DstReg,
682  unsigned SrcRec) const;
683 
684  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
685  unsigned Size, unsigned BinOpcode,
686  bool Nand = false) const;
687  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
688  MachineBasicBlock *BB,
689  unsigned Size,
690  unsigned BinOpcode,
691  bool Nand = false) const;
692  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
693  MachineBasicBlock *BB,
694  unsigned Size) const;
695  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
696  MachineBasicBlock *BB,
697  unsigned Size) const;
698  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
699  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
700  bool isFPCmp, unsigned Opc) const;
701  };
702 
703  /// Create MipsTargetLowering objects.
704  const MipsTargetLowering *
706  const MipsSubtarget &STI);
707  const MipsTargetLowering *
709  const MipsSubtarget &STI);
710 
711 namespace Mips {
712 
714  const TargetLibraryInfo *libInfo);
715 
716 } // end namespace Mips
717 
718 } // end namespace llvm
719 
720 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
const MipsSubtarget & Subtarget
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
Function Alias Analysis Results
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
Shift and rotation operations.
Definition: ISDOpcodes.h:379
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:446
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:682
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:841
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:59
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MipsABIInfo & ABI
Conversion operators.
Definition: ISDOpcodes.h:442
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.