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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 
21 #include "Mips.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <deque>
37 #include <string>
38 #include <utility>
39 #include <vector>
40 
41 namespace llvm {
42 
43 class Argument;
44 class CCState;
45 class CCValAssign;
46 class FastISel;
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFrameInfo;
50 class MachineInstr;
51 class MipsCCState;
52 class MipsFunctionInfo;
53 class MipsSubtarget;
54 class MipsTargetMachine;
55 class TargetLibraryInfo;
56 class TargetRegisterClass;
57 
58  namespace MipsISD {
59 
60  enum NodeType : unsigned {
61  // Start the numbering from where ISD NodeType finishes.
63 
64  // Jump and link (call)
66 
67  // Tail call
69 
70  // Get the Highest (63-48) 16 bits from a 64-bit immediate
72 
73  // Get the Higher (47-32) 16 bits from a 64-bit immediate
75 
76  // Get the High 16 bits from a 32/64-bit immediate
77  // No relation with Mips Hi register
78  Hi,
79 
80  // Get the Lower 16 bits from a 32/64-bit immediate
81  // No relation with Mips Lo register
82  Lo,
83 
84  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
86 
87  // Get the High 16 bits from a 32-bit immediate for accessing TLS.
89 
90  // Handle gp_rel (small data/bss sections) relocation.
92 
93  // Thread Pointer
95 
96  // Vector Floating Point Multiply and Subtract
97  FMS,
98 
99  // Floating Point Branch Conditional
101 
102  // Floating Point Compare
104 
105  // Floating point select
107 
108  // Node used to generate an MTC1 i32 to f64 instruction
110 
111  // Floating Point Conditional Moves
114 
115  // FP-to-int truncation node.
117 
118  // Return
120 
121  // Interrupt, exception, error trap Return
123 
124  // Software Exception Return.
126 
127  // Node used to extract integer from accumulator.
130 
131  // Node used to insert integers to accumulator.
133 
134  // Mult nodes.
137 
138  // MAdd/Sub nodes
143 
144  // DivRem(u)
149 
152 
154 
156 
158 
162 
163  // EXTR.W instrinsic nodes.
172 
173  // DPA.W intrinsic nodes.
196 
203 
204  // DSP shift nodes.
208 
209  // DSP setcc and select_cc nodes.
212 
213  // Vector comparisons.
214  // These take a vector and return a boolean.
219 
220  // These take a vector and return a vector bitmask.
226 
227  // Vector Shuffle with mask as an operand
228  VSHF, // Generic shuffle
229  SHF, // 4-element set shuffle.
230  ILVEV, // Interleave even elements
231  ILVOD, // Interleave odd elements
232  ILVL, // Interleave left elements
233  ILVR, // Interleave right elements
234  PCKEV, // Pack even elements
235  PCKOD, // Pack odd elements
236 
237  // Vector Lane Copy
238  INSVE, // Copy element from one vector to another
239 
240  // Combined (XOR (OR $a, $b), -1)
242 
243  // Extended vector element extraction
246 
247  // Load/Store Left/Right nodes.
256  };
257 
258  } // ene namespace MipsISD
259 
260  //===--------------------------------------------------------------------===//
261  // TargetLowering Implementation
262  //===--------------------------------------------------------------------===//
263 
265  bool isMicroMips;
266 
267  public:
268  explicit MipsTargetLowering(const MipsTargetMachine &TM,
269  const MipsSubtarget &STI);
270 
271  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
272  const MipsSubtarget &STI);
273 
274  /// createFastISel - This method returns a target specific FastISel object,
275  /// or null if the target does not support "fast" ISel.
277  const TargetLibraryInfo *libInfo) const override;
278 
279  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
280  return MVT::i32;
281  }
282 
283  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
284  ISD::NodeType) const override;
285 
286  bool isCheapToSpeculateCttz() const override;
287  bool isCheapToSpeculateCtlz() const override;
288 
289  /// Return the register type for a given MVT, ensuring vectors are treated
290  /// as a series of gpr sized integers.
291  MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
292  EVT VT) const override;
293 
294  /// Return the number of registers for a given MVT, ensuring vectors are
295  /// treated as a series of gpr sized integers.
296  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
297  CallingConv::ID CC,
298  EVT VT) const override;
299 
300  /// Break down vectors to the correct number of gpr sized integers.
301  unsigned getVectorTypeBreakdownForCallingConv(
302  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
303  unsigned &NumIntermediates, MVT &RegisterVT) const override;
304 
305  /// Return the correct alignment for the current calling convention.
307  DataLayout DL) const override {
308  if (ArgTy->isVectorTy())
309  return std::min(DL.getABITypeAlignment(ArgTy), 8U);
310  return DL.getABITypeAlignment(ArgTy);
311  }
312 
314  return ISD::SIGN_EXTEND;
315  }
316 
317  void LowerOperationWrapper(SDNode *N,
319  SelectionDAG &DAG) const override;
320 
321  /// LowerOperation - Provide custom lowering hooks for some operations.
322  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
323 
324  /// ReplaceNodeResults - Replace the results of node with an illegal result
325  /// type with new values built out of custom code.
326  ///
327  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
328  SelectionDAG &DAG) const override;
329 
330  /// getTargetNodeName - This method returns the name of a target specific
331  // DAG node.
332  const char *getTargetNodeName(unsigned Opcode) const override;
333 
334  /// getSetCCResultType - get the ISD::SETCC result ValueType
335  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
336  EVT VT) const override;
337 
338  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
339 
341  EmitInstrWithCustomInserter(MachineInstr &MI,
342  MachineBasicBlock *MBB) const override;
343 
344  void HandleByVal(CCState *, unsigned &, unsigned) const override;
345 
346  unsigned getRegisterByName(const char* RegName, EVT VT,
347  SelectionDAG &DAG) const override;
348 
349  /// If a physical register, this returns the register that receives the
350  /// exception address on entry to an EH pad.
351  unsigned
352  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
353  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
354  }
355 
356  /// If a physical register, this returns the register that receives the
357  /// exception typeid on entry to a landing pad.
358  unsigned
359  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
360  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
361  }
362 
363  /// Returns true if a cast between SrcAS and DestAS is a noop.
364  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
365  // Mips doesn't have any special address spaces so we just reserve
366  // the first 256 for software use (e.g. OpenCL) and treat casts
367  // between them as noops.
368  return SrcAS < 256 && DestAS < 256;
369  }
370 
371  bool isJumpTableRelative() const override {
372  return getTargetMachine().isPositionIndependent();
373  }
374 
375  CCAssignFn *CCAssignFnForCall() const;
376 
377  CCAssignFn *CCAssignFnForReturn() const;
378 
379  protected:
380  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
381 
382  // This method creates the following nodes, which are necessary for
383  // computing a local symbol's address:
384  //
385  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
386  template <class NodeTy>
387  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
388  bool IsN32OrN64) const {
389  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
390  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
391  getTargetNode(N, Ty, DAG, GOTFlag));
392  SDValue Load =
393  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
395  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
396  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
397  getTargetNode(N, Ty, DAG, LoFlag));
398  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
399  }
400 
401  // This method creates the following nodes, which are necessary for
402  // computing a global symbol's address:
403  //
404  // (load (wrapper $gp, %got(sym)))
405  template <class NodeTy>
406  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
407  unsigned Flag, SDValue Chain,
408  const MachinePointerInfo &PtrInfo) const {
409  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
410  getTargetNode(N, Ty, DAG, Flag));
411  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
412  }
413 
414  // This method creates the following nodes, which are necessary for
415  // computing a global symbol's address in large-GOT mode:
416  //
417  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
418  template <class NodeTy>
419  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
420  SelectionDAG &DAG, unsigned HiFlag,
421  unsigned LoFlag, SDValue Chain,
422  const MachinePointerInfo &PtrInfo) const {
423  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
424  getTargetNode(N, Ty, DAG, HiFlag));
425  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
426  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
427  getTargetNode(N, Ty, DAG, LoFlag));
428  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
429  }
430 
431  // This method creates the following nodes, which are necessary for
432  // computing a symbol's address in non-PIC mode:
433  //
434  // (add %hi(sym), %lo(sym))
435  //
436  // This method covers O32, N32 and N64 in sym32 mode.
437  template <class NodeTy>
438  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
439  SelectionDAG &DAG) const {
440  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
441  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
442  return DAG.getNode(ISD::ADD, DL, Ty,
443  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
444  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
445  }
446 
447  // This method creates the following nodes, which are necessary for
448  // computing a symbol's address in non-PIC mode for N64.
449  //
450  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
451  // 16), %lo(%sym))
452  //
453  // FIXME: This method is not efficent for (micro)MIPS64R6.
454  template <class NodeTy>
455  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
456  SelectionDAG &DAG) const {
457  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
458  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
459 
460  SDValue Highest =
461  DAG.getNode(MipsISD::Highest, DL, Ty,
462  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
463  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
464  SDValue HigherPart =
465  DAG.getNode(ISD::ADD, DL, Ty, Highest,
466  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
467  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
468  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
469  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
470  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
471  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
472 
473  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
474  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
475  }
476 
477  // This method creates the following nodes, which are necessary for
478  // computing a symbol's address using gp-relative addressing:
479  //
480  // (add $gp, %gp_rel(sym))
481  template <class NodeTy>
482  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
483  SelectionDAG &DAG, bool IsN64) const {
484  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
485  return DAG.getNode(
486  ISD::ADD, DL, Ty,
487  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
488  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
489  }
490 
491  /// This function fills Ops, which is the list of operands that will later
492  /// be used when a function call node is created. It also generates
493  /// copyToReg nodes to set up argument registers.
494  virtual void
495  getOpndList(SmallVectorImpl<SDValue> &Ops,
496  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
497  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
498  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
499  SDValue Chain) const;
500 
501  protected:
502  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
503  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
504 
505  // Subtarget Info
507  // Cache the ABI from the TargetMachine, we use it everywhere.
508  const MipsABIInfo &ABI;
509 
510  private:
511  // Create a TargetGlobalAddress node.
512  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
513  unsigned Flag) const;
514 
515  // Create a TargetExternalSymbol node.
516  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
517  unsigned Flag) const;
518 
519  // Create a TargetBlockAddress node.
520  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
521  unsigned Flag) const;
522 
523  // Create a TargetJumpTable node.
524  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
525  unsigned Flag) const;
526 
527  // Create a TargetConstantPool node.
528  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
529  unsigned Flag) const;
530 
531  // Lower Operand helpers
532  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
533  CallingConv::ID CallConv, bool isVarArg,
535  const SDLoc &dl, SelectionDAG &DAG,
536  SmallVectorImpl<SDValue> &InVals,
538 
539  // Lower Operand specifics
540  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
555  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
556  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
557  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
558  bool IsSRA) const;
559  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
560  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
561 
562  /// isEligibleForTailCallOptimization - Check whether the call is eligible
563  /// for tail call optimization.
564  virtual bool
565  isEligibleForTailCallOptimization(const CCState &CCInfo,
566  unsigned NextStackOffset,
567  const MipsFunctionInfo &FI) const = 0;
568 
569  /// copyByValArg - Copy argument registers which were used to pass a byval
570  /// argument to the stack. Create a stack frame object for the byval
571  /// argument.
572  void copyByValRegs(SDValue Chain, const SDLoc &DL,
573  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
574  const ISD::ArgFlagsTy &Flags,
575  SmallVectorImpl<SDValue> &InVals,
576  const Argument *FuncArg, unsigned FirstReg,
577  unsigned LastReg, const CCValAssign &VA,
578  MipsCCState &State) const;
579 
580  /// passByValArg - Pass a byval argument in registers or on stack.
581  void passByValArg(SDValue Chain, const SDLoc &DL,
582  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
583  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
585  unsigned FirstReg, unsigned LastReg,
586  const ISD::ArgFlagsTy &Flags, bool isLittle,
587  const CCValAssign &VA) const;
588 
589  /// writeVarArgRegs - Write variable function arguments passed in registers
590  /// to the stack. Also create a stack frame object for the first variable
591  /// argument.
592  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
593  const SDLoc &DL, SelectionDAG &DAG,
594  CCState &State) const;
595 
596  SDValue
597  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
599  const SDLoc &dl, SelectionDAG &DAG,
600  SmallVectorImpl<SDValue> &InVals) const override;
601 
602  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
603  SDValue Arg, const SDLoc &DL, bool IsTailCall,
604  SelectionDAG &DAG) const;
605 
607  SmallVectorImpl<SDValue> &InVals) const override;
608 
609  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
610  bool isVarArg,
612  LLVMContext &Context) const override;
613 
614  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
616  const SmallVectorImpl<SDValue> &OutVals,
617  const SDLoc &dl, SelectionDAG &DAG) const override;
618 
620  const SDLoc &DL, SelectionDAG &DAG) const;
621 
622  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
623 
624  // Inline asm support
625  ConstraintType getConstraintType(StringRef Constraint) const override;
626 
627  /// Examine constraint string and operand type and determine a weight value.
628  /// The operand object must already have been set up with the operand type.
629  ConstraintWeight getSingleConstraintMatchWeight(
630  AsmOperandInfo &info, const char *constraint) const override;
631 
632  /// This function parses registers that appear in inline-asm constraints.
633  /// It returns pair (0, 0) on failure.
634  std::pair<unsigned, const TargetRegisterClass *>
635  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
636 
637  std::pair<unsigned, const TargetRegisterClass *>
638  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
639  StringRef Constraint, MVT VT) const override;
640 
641  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
642  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
643  /// true it means one of the asm constraint of the inline asm instruction
644  /// being processed is 'm'.
645  void LowerAsmOperandForConstraint(SDValue Op,
646  std::string &Constraint,
647  std::vector<SDValue> &Ops,
648  SelectionDAG &DAG) const override;
649 
650  unsigned
651  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
652  if (ConstraintCode == "R")
654  else if (ConstraintCode == "ZC")
656  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
657  }
658 
659  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
660  Type *Ty, unsigned AS,
661  Instruction *I = nullptr) const override;
662 
663  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
664 
665  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
666  unsigned SrcAlign,
667  bool IsMemset, bool ZeroMemset,
668  bool MemcpyStrSrc,
669  MachineFunction &MF) const override;
670 
671  /// isFPImmLegal - Returns true if the target can instruction select the
672  /// specified FP immediate natively. If false, the legalizer will
673  /// materialize the FP immediate as a load from a constant pool.
674  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
675 
676  unsigned getJumpTableEncoding() const override;
677  bool useSoftFloat() const override;
678 
679  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
680  return true;
681  }
682 
683  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
684  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
685  MachineBasicBlock *BB,
686  unsigned Size, unsigned DstReg,
687  unsigned SrcRec) const;
688 
689  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
690  MachineBasicBlock *BB) const;
691  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
692  MachineBasicBlock *BB,
693  unsigned Size) const;
694  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
695  MachineBasicBlock *BB) const;
696  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
697  MachineBasicBlock *BB,
698  unsigned Size) const;
699  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
700  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
701  bool isFPCmp, unsigned Opc) const;
702  };
703 
704  /// Create MipsTargetLowering objects.
705  const MipsTargetLowering *
707  const MipsSubtarget &STI);
708  const MipsTargetLowering *
710  const MipsSubtarget &STI);
711 
712 namespace Mips {
713 
715  const TargetLibraryInfo *libInfo);
716 
717 } // end namespace Mips
718 
719 } // end namespace llvm
720 
721 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:864
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
const MipsSubtarget & Subtarget
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
Shift and rotation operations.
Definition: ISDOpcodes.h:399
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:871
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
uint32_t Size
Definition: Profile.cpp:47
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MipsABIInfo & ABI
Conversion operators.
Definition: ISDOpcodes.h:454
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.