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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 
20 #include "Mips.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/IR/Type.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <deque>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class Argument;
43 class CCState;
44 class CCValAssign;
45 class FastISel;
46 class FunctionLoweringInfo;
47 class MachineBasicBlock;
48 class MachineFrameInfo;
49 class MachineInstr;
50 class MipsCCState;
51 class MipsFunctionInfo;
52 class MipsSubtarget;
53 class MipsTargetMachine;
54 class TargetLibraryInfo;
55 class TargetRegisterClass;
56 
57  namespace MipsISD {
58 
59  enum NodeType : unsigned {
60  // Start the numbering from where ISD NodeType finishes.
62 
63  // Jump and link (call)
65 
66  // Tail call
68 
69  // Get the Highest (63-48) 16 bits from a 64-bit immediate
71 
72  // Get the Higher (47-32) 16 bits from a 64-bit immediate
74 
75  // Get the High 16 bits from a 32/64-bit immediate
76  // No relation with Mips Hi register
77  Hi,
78 
79  // Get the Lower 16 bits from a 32/64-bit immediate
80  // No relation with Mips Lo register
81  Lo,
82 
83  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
85 
86  // Get the High 16 bits from a 32-bit immediate for accessing TLS.
88 
89  // Handle gp_rel (small data/bss sections) relocation.
91 
92  // Thread Pointer
94 
95  // Vector Floating Point Multiply and Subtract
96  FMS,
97 
98  // Floating Point Branch Conditional
100 
101  // Floating Point Compare
103 
104  // Floating point select
106 
107  // Node used to generate an MTC1 i32 to f64 instruction
109 
110  // Floating Point Conditional Moves
113 
114  // FP-to-int truncation node.
116 
117  // Return
119 
120  // Interrupt, exception, error trap Return
122 
123  // Software Exception Return.
125 
126  // Node used to extract integer from accumulator.
129 
130  // Node used to insert integers to accumulator.
132 
133  // Mult nodes.
136 
137  // MAdd/Sub nodes
142 
143  // DivRem(u)
148 
151 
153 
155 
157 
161 
162  // EXTR.W instrinsic nodes.
171 
172  // DPA.W intrinsic nodes.
195 
202 
203  // DSP shift nodes.
207 
208  // DSP setcc and select_cc nodes.
211 
212  // Vector comparisons.
213  // These take a vector and return a boolean.
218 
219  // These take a vector and return a vector bitmask.
225 
226  // Vector Shuffle with mask as an operand
227  VSHF, // Generic shuffle
228  SHF, // 4-element set shuffle.
229  ILVEV, // Interleave even elements
230  ILVOD, // Interleave odd elements
231  ILVL, // Interleave left elements
232  ILVR, // Interleave right elements
233  PCKEV, // Pack even elements
234  PCKOD, // Pack odd elements
235 
236  // Vector Lane Copy
237  INSVE, // Copy element from one vector to another
238 
239  // Combined (XOR (OR $a, $b), -1)
241 
242  // Extended vector element extraction
245 
246  // Load/Store Left/Right nodes.
255  };
256 
257  } // ene namespace MipsISD
258 
259  //===--------------------------------------------------------------------===//
260  // TargetLowering Implementation
261  //===--------------------------------------------------------------------===//
262 
264  bool isMicroMips;
265 
266  public:
267  explicit MipsTargetLowering(const MipsTargetMachine &TM,
268  const MipsSubtarget &STI);
269 
270  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
271  const MipsSubtarget &STI);
272 
273  /// createFastISel - This method returns a target specific FastISel object,
274  /// or null if the target does not support "fast" ISel.
276  const TargetLibraryInfo *libInfo) const override;
277 
278  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
279  return MVT::i32;
280  }
281 
282  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
283  ISD::NodeType) const override;
284 
285  bool isCheapToSpeculateCttz() const override;
286  bool isCheapToSpeculateCtlz() const override;
287  bool shouldFoldConstantShiftPairToMask(const SDNode *N,
288  CombineLevel Level) const override;
289 
290  /// Return the register type for a given MVT, ensuring vectors are treated
291  /// as a series of gpr sized integers.
292  MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
293  EVT VT) const override;
294 
295  /// Return the number of registers for a given MVT, ensuring vectors are
296  /// treated as a series of gpr sized integers.
297  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
298  CallingConv::ID CC,
299  EVT VT) const override;
300 
301  /// Break down vectors to the correct number of gpr sized integers.
302  unsigned getVectorTypeBreakdownForCallingConv(
303  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
304  unsigned &NumIntermediates, MVT &RegisterVT) const override;
305 
306  /// Return the correct alignment for the current calling convention.
308  DataLayout DL) const override {
309  const Align ABIAlign(DL.getABITypeAlignment(ArgTy));
310  if (ArgTy->isVectorTy())
311  return std::min(ABIAlign, Align(8));
312  return ABIAlign;
313  }
314 
316  return ISD::SIGN_EXTEND;
317  }
318 
319  void LowerOperationWrapper(SDNode *N,
321  SelectionDAG &DAG) const override;
322 
323  /// LowerOperation - Provide custom lowering hooks for some operations.
324  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
325 
326  /// ReplaceNodeResults - Replace the results of node with an illegal result
327  /// type with new values built out of custom code.
328  ///
329  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
330  SelectionDAG &DAG) const override;
331 
332  /// getTargetNodeName - This method returns the name of a target specific
333  // DAG node.
334  const char *getTargetNodeName(unsigned Opcode) const override;
335 
336  /// getSetCCResultType - get the ISD::SETCC result ValueType
337  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
338  EVT VT) const override;
339 
340  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
341 
343  EmitInstrWithCustomInserter(MachineInstr &MI,
344  MachineBasicBlock *MBB) const override;
345 
346  void AdjustInstrPostInstrSelection(MachineInstr &MI,
347  SDNode *Node) const override;
348 
349  void HandleByVal(CCState *, unsigned &, unsigned) const override;
350 
351  Register getRegisterByName(const char* RegName, EVT VT,
352  const MachineFunction &MF) const override;
353 
354  /// If a physical register, this returns the register that receives the
355  /// exception address on entry to an EH pad.
356  unsigned
357  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
358  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
359  }
360 
361  /// If a physical register, this returns the register that receives the
362  /// exception typeid on entry to a landing pad.
363  unsigned
364  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
365  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
366  }
367 
368  /// Returns true if a cast between SrcAS and DestAS is a noop.
369  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
370  // Mips doesn't have any special address spaces so we just reserve
371  // the first 256 for software use (e.g. OpenCL) and treat casts
372  // between them as noops.
373  return SrcAS < 256 && DestAS < 256;
374  }
375 
376  bool isJumpTableRelative() const override {
377  return getTargetMachine().isPositionIndependent();
378  }
379 
380  CCAssignFn *CCAssignFnForCall() const;
381 
382  CCAssignFn *CCAssignFnForReturn() const;
383 
384  protected:
385  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
386 
387  // This method creates the following nodes, which are necessary for
388  // computing a local symbol's address:
389  //
390  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
391  template <class NodeTy>
392  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
393  bool IsN32OrN64) const {
394  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
395  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
396  getTargetNode(N, Ty, DAG, GOTFlag));
397  SDValue Load =
398  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
400  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
401  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
402  getTargetNode(N, Ty, DAG, LoFlag));
403  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
404  }
405 
406  // This method creates the following nodes, which are necessary for
407  // computing a global symbol's address:
408  //
409  // (load (wrapper $gp, %got(sym)))
410  template <class NodeTy>
411  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
412  unsigned Flag, SDValue Chain,
413  const MachinePointerInfo &PtrInfo) const {
414  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
415  getTargetNode(N, Ty, DAG, Flag));
416  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
417  }
418 
419  // This method creates the following nodes, which are necessary for
420  // computing a global symbol's address in large-GOT mode:
421  //
422  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
423  template <class NodeTy>
424  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
425  SelectionDAG &DAG, unsigned HiFlag,
426  unsigned LoFlag, SDValue Chain,
427  const MachinePointerInfo &PtrInfo) const {
428  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
429  getTargetNode(N, Ty, DAG, HiFlag));
430  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
431  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
432  getTargetNode(N, Ty, DAG, LoFlag));
433  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
434  }
435 
436  // This method creates the following nodes, which are necessary for
437  // computing a symbol's address in non-PIC mode:
438  //
439  // (add %hi(sym), %lo(sym))
440  //
441  // This method covers O32, N32 and N64 in sym32 mode.
442  template <class NodeTy>
443  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
444  SelectionDAG &DAG) const {
445  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
446  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
447  return DAG.getNode(ISD::ADD, DL, Ty,
448  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
449  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
450  }
451 
452  // This method creates the following nodes, which are necessary for
453  // computing a symbol's address in non-PIC mode for N64.
454  //
455  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
456  // 16), %lo(%sym))
457  //
458  // FIXME: This method is not efficent for (micro)MIPS64R6.
459  template <class NodeTy>
460  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
461  SelectionDAG &DAG) const {
462  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
463  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
464 
465  SDValue Highest =
466  DAG.getNode(MipsISD::Highest, DL, Ty,
467  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
469  SDValue HigherPart =
470  DAG.getNode(ISD::ADD, DL, Ty, Highest,
471  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
472  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
473  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
474  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
475  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
476  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
477 
478  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
479  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
480  }
481 
482  // This method creates the following nodes, which are necessary for
483  // computing a symbol's address using gp-relative addressing:
484  //
485  // (add $gp, %gp_rel(sym))
486  template <class NodeTy>
487  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
488  SelectionDAG &DAG, bool IsN64) const {
490  return DAG.getNode(
491  ISD::ADD, DL, Ty,
492  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
493  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
494  }
495 
496  /// This function fills Ops, which is the list of operands that will later
497  /// be used when a function call node is created. It also generates
498  /// copyToReg nodes to set up argument registers.
499  virtual void
500  getOpndList(SmallVectorImpl<SDValue> &Ops,
501  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
502  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
503  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
504  SDValue Chain) const;
505 
506  protected:
507  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
508  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
509 
510  // Subtarget Info
512  // Cache the ABI from the TargetMachine, we use it everywhere.
513  const MipsABIInfo &ABI;
514 
515  private:
516  // Create a TargetGlobalAddress node.
518  unsigned Flag) const;
519 
520  // Create a TargetExternalSymbol node.
522  unsigned Flag) const;
523 
524  // Create a TargetBlockAddress node.
526  unsigned Flag) const;
527 
528  // Create a TargetJumpTable node.
530  unsigned Flag) const;
531 
532  // Create a TargetConstantPool node.
534  unsigned Flag) const;
535 
536  // Lower Operand helpers
537  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
538  CallingConv::ID CallConv, bool isVarArg,
540  const SDLoc &dl, SelectionDAG &DAG,
541  SmallVectorImpl<SDValue> &InVals,
543 
544  // Lower Operand specifics
545  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
555  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
556  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
557  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
558  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
559  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
560  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
561  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
562  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
563  bool IsSRA) const;
564  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
565  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
566 
567  /// isEligibleForTailCallOptimization - Check whether the call is eligible
568  /// for tail call optimization.
569  virtual bool
570  isEligibleForTailCallOptimization(const CCState &CCInfo,
571  unsigned NextStackOffset,
572  const MipsFunctionInfo &FI) const = 0;
573 
574  /// copyByValArg - Copy argument registers which were used to pass a byval
575  /// argument to the stack. Create a stack frame object for the byval
576  /// argument.
577  void copyByValRegs(SDValue Chain, const SDLoc &DL,
578  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
579  const ISD::ArgFlagsTy &Flags,
580  SmallVectorImpl<SDValue> &InVals,
581  const Argument *FuncArg, unsigned FirstReg,
582  unsigned LastReg, const CCValAssign &VA,
583  MipsCCState &State) const;
584 
585  /// passByValArg - Pass a byval argument in registers or on stack.
586  void passByValArg(SDValue Chain, const SDLoc &DL,
587  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
588  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
590  unsigned FirstReg, unsigned LastReg,
591  const ISD::ArgFlagsTy &Flags, bool isLittle,
592  const CCValAssign &VA) const;
593 
594  /// writeVarArgRegs - Write variable function arguments passed in registers
595  /// to the stack. Also create a stack frame object for the first variable
596  /// argument.
597  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
598  const SDLoc &DL, SelectionDAG &DAG,
599  CCState &State) const;
600 
601  SDValue
602  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
604  const SDLoc &dl, SelectionDAG &DAG,
605  SmallVectorImpl<SDValue> &InVals) const override;
606 
607  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
608  SDValue Arg, const SDLoc &DL, bool IsTailCall,
609  SelectionDAG &DAG) const;
610 
612  SmallVectorImpl<SDValue> &InVals) const override;
613 
614  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
615  bool isVarArg,
617  LLVMContext &Context) const override;
618 
619  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
621  const SmallVectorImpl<SDValue> &OutVals,
622  const SDLoc &dl, SelectionDAG &DAG) const override;
623 
625  const SDLoc &DL, SelectionDAG &DAG) const;
626 
627  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
628 
629  // Inline asm support
630  ConstraintType getConstraintType(StringRef Constraint) const override;
631 
632  /// Examine constraint string and operand type and determine a weight value.
633  /// The operand object must already have been set up with the operand type.
634  ConstraintWeight getSingleConstraintMatchWeight(
635  AsmOperandInfo &info, const char *constraint) const override;
636 
637  /// This function parses registers that appear in inline-asm constraints.
638  /// It returns pair (0, 0) on failure.
639  std::pair<unsigned, const TargetRegisterClass *>
640  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
641 
642  std::pair<unsigned, const TargetRegisterClass *>
643  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
644  StringRef Constraint, MVT VT) const override;
645 
646  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
647  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
648  /// true it means one of the asm constraint of the inline asm instruction
649  /// being processed is 'm'.
650  void LowerAsmOperandForConstraint(SDValue Op,
651  std::string &Constraint,
652  std::vector<SDValue> &Ops,
653  SelectionDAG &DAG) const override;
654 
655  unsigned
656  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
657  if (ConstraintCode == "o")
659  if (ConstraintCode == "R")
661  if (ConstraintCode == "ZC")
663  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
664  }
665 
666  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
667  Type *Ty, unsigned AS,
668  Instruction *I = nullptr) const override;
669 
670  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
671 
672  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
673  unsigned SrcAlign,
674  bool IsMemset, bool ZeroMemset,
675  bool MemcpyStrSrc,
676  const AttributeList &FuncAttributes) const override;
677 
678  /// isFPImmLegal - Returns true if the target can instruction select the
679  /// specified FP immediate natively. If false, the legalizer will
680  /// materialize the FP immediate as a load from a constant pool.
681  bool isFPImmLegal(const APFloat &Imm, EVT VT,
682  bool ForCodeSize) const override;
683 
684  unsigned getJumpTableEncoding() const override;
685  bool useSoftFloat() const override;
686 
687  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
688  return true;
689  }
690 
691  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
692  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
693  MachineBasicBlock *BB,
694  unsigned Size, unsigned DstReg,
695  unsigned SrcRec) const;
696 
697  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
698  MachineBasicBlock *BB) const;
699  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
700  MachineBasicBlock *BB,
701  unsigned Size) const;
702  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
703  MachineBasicBlock *BB) const;
704  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
705  MachineBasicBlock *BB,
706  unsigned Size) const;
707  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
708  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
709  bool isFPCmp, unsigned Opc) const;
710  MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
711  MachineBasicBlock *BB) const;
712  };
713 
714  /// Create MipsTargetLowering objects.
715  const MipsTargetLowering *
717  const MipsSubtarget &STI);
718  const MipsTargetLowering *
720  const MipsSubtarget &STI);
721 
722 namespace Mips {
723 
725  const TargetLibraryInfo *libInfo);
726 
727 } // end namespace Mips
728 
729 } // end namespace llvm
730 
731 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:921
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
LLVMContext & Context
const MipsSubtarget & Subtarget
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:84
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
Shift and rotation operations.
Definition: ISDOpcodes.h:449
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:477
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:51
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:414
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:47
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
This is an important base class in LLVM.
Definition: Constant.h:41
CombineLevel
Definition: DAGCombine.h:15
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:33
static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:37
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:755
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:928
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
uint32_t Size
Definition: Profile.cpp:46
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
const MipsABIInfo & ABI
Align getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
Conversion operators.
Definition: ISDOpcodes.h:504
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
static bool isMicroMips(const MCSubtargetInfo *STI)
This file describes how to lower LLVM code to machine code.