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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 
21 #include "Mips.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <deque>
37 #include <string>
38 #include <utility>
39 #include <vector>
40 
41 namespace llvm {
42 
43 class Argument;
44 class CCState;
45 class CCValAssign;
46 class FastISel;
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFrameInfo;
50 class MachineInstr;
51 class MipsCCState;
52 class MipsFunctionInfo;
53 class MipsSubtarget;
54 class MipsTargetMachine;
55 class TargetLibraryInfo;
56 class TargetRegisterClass;
57 
58  namespace MipsISD {
59 
60  enum NodeType : unsigned {
61  // Start the numbering from where ISD NodeType finishes.
63 
64  // Jump and link (call)
66 
67  // Tail call
69 
70  // Get the Highest (63-48) 16 bits from a 64-bit immediate
72 
73  // Get the Higher (47-32) 16 bits from a 64-bit immediate
75 
76  // Get the High 16 bits from a 32/64-bit immediate
77  // No relation with Mips Hi register
78  Hi,
79 
80  // Get the Lower 16 bits from a 32/64-bit immediate
81  // No relation with Mips Lo register
82  Lo,
83 
84  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
86 
87  // Handle gp_rel (small data/bss sections) relocation.
89 
90  // Thread Pointer
92 
93  // Floating Point Branch Conditional
95 
96  // Floating Point Compare
98 
99  // Floating point select
101 
102  // Node used to generate an MTC1 i32 to f64 instruction
104 
105  // Floating Point Conditional Moves
108 
109  // FP-to-int truncation node.
111 
112  // Return
114 
115  // Interrupt, exception, error trap Return
117 
118  // Software Exception Return.
120 
121  // Node used to extract integer from accumulator.
124 
125  // Node used to insert integers to accumulator.
127 
128  // Mult nodes.
131 
132  // MAdd/Sub nodes
137 
138  // DivRem(u)
143 
146 
148 
150 
152 
156 
157  // EXTR.W instrinsic nodes.
166 
167  // DPA.W intrinsic nodes.
190 
197 
198  // DSP shift nodes.
202 
203  // DSP setcc and select_cc nodes.
206 
207  // Vector comparisons.
208  // These take a vector and return a boolean.
213 
214  // These take a vector and return a vector bitmask.
220 
221  // Vector Shuffle with mask as an operand
222  VSHF, // Generic shuffle
223  SHF, // 4-element set shuffle.
224  ILVEV, // Interleave even elements
225  ILVOD, // Interleave odd elements
226  ILVL, // Interleave left elements
227  ILVR, // Interleave right elements
228  PCKEV, // Pack even elements
229  PCKOD, // Pack odd elements
230 
231  // Vector Lane Copy
232  INSVE, // Copy element from one vector to another
233 
234  // Combined (XOR (OR $a, $b), -1)
236 
237  // Extended vector element extraction
240 
241  // Load/Store Left/Right nodes.
250  };
251 
252  } // ene namespace MipsISD
253 
254  //===--------------------------------------------------------------------===//
255  // TargetLowering Implementation
256  //===--------------------------------------------------------------------===//
257 
259  bool isMicroMips;
260 
261  public:
262  explicit MipsTargetLowering(const MipsTargetMachine &TM,
263  const MipsSubtarget &STI);
264 
265  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
266  const MipsSubtarget &STI);
267 
268  /// createFastISel - This method returns a target specific FastISel object,
269  /// or null if the target does not support "fast" ISel.
271  const TargetLibraryInfo *libInfo) const override;
272 
273  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
274  return MVT::i32;
275  }
276 
277  bool isCheapToSpeculateCttz() const override;
278  bool isCheapToSpeculateCtlz() const override;
279 
280  /// Return the register type for a given MVT, ensuring vectors are treated
281  /// as a series of gpr sized integers.
282  MVT getRegisterTypeForCallingConv(MVT VT) const override;
283 
284  /// Return the register type for a given MVT, ensuring vectors are treated
285  /// as a series of gpr sized integers.
286  MVT getRegisterTypeForCallingConv(LLVMContext &Context,
287  EVT VT) const override;
288 
289  /// Return the number of registers for a given MVT, ensuring vectors are
290  /// treated as a series of gpr sized integers.
291  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
292  EVT VT) const override;
293 
294  /// Break down vectors to the correct number of gpr sized integers.
295  unsigned getVectorTypeBreakdownForCallingConv(
296  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
297  unsigned &NumIntermediates, MVT &RegisterVT) const override;
298 
299  /// Return the correct alignment for the current calling convention.
301  DataLayout DL) const override {
302  if (ArgTy->isVectorTy())
303  return std::min(DL.getABITypeAlignment(ArgTy), 8U);
304  return DL.getABITypeAlignment(ArgTy);
305  }
306 
308  return ISD::SIGN_EXTEND;
309  }
310 
311  void LowerOperationWrapper(SDNode *N,
313  SelectionDAG &DAG) const override;
314 
315  /// LowerOperation - Provide custom lowering hooks for some operations.
316  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
317 
318  /// ReplaceNodeResults - Replace the results of node with an illegal result
319  /// type with new values built out of custom code.
320  ///
321  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
322  SelectionDAG &DAG) const override;
323 
324  /// getTargetNodeName - This method returns the name of a target specific
325  // DAG node.
326  const char *getTargetNodeName(unsigned Opcode) const override;
327 
328  /// getSetCCResultType - get the ISD::SETCC result ValueType
329  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
330  EVT VT) const override;
331 
332  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
333 
335  EmitInstrWithCustomInserter(MachineInstr &MI,
336  MachineBasicBlock *MBB) const override;
337 
338  void HandleByVal(CCState *, unsigned &, unsigned) const override;
339 
340  unsigned getRegisterByName(const char* RegName, EVT VT,
341  SelectionDAG &DAG) const override;
342 
343  /// If a physical register, this returns the register that receives the
344  /// exception address on entry to an EH pad.
345  unsigned
346  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
347  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
348  }
349 
350  /// If a physical register, this returns the register that receives the
351  /// exception typeid on entry to a landing pad.
352  unsigned
353  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
354  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
355  }
356 
357  /// Returns true if a cast between SrcAS and DestAS is a noop.
358  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
359  // Mips doesn't have any special address spaces so we just reserve
360  // the first 256 for software use (e.g. OpenCL) and treat casts
361  // between them as noops.
362  return SrcAS < 256 && DestAS < 256;
363  }
364 
365  bool isJumpTableRelative() const override {
366  return getTargetMachine().isPositionIndependent();
367  }
368 
369  CCAssignFn *CCAssignFnForCall() const;
370 
371  CCAssignFn *CCAssignFnForReturn() const;
372 
373  protected:
374  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
375 
376  // This method creates the following nodes, which are necessary for
377  // computing a local symbol's address:
378  //
379  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
380  template <class NodeTy>
381  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
382  bool IsN32OrN64) const {
383  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
384  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
385  getTargetNode(N, Ty, DAG, GOTFlag));
386  SDValue Load =
387  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
389  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
390  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
391  getTargetNode(N, Ty, DAG, LoFlag));
392  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
393  }
394 
395  // This method creates the following nodes, which are necessary for
396  // computing a global symbol's address:
397  //
398  // (load (wrapper $gp, %got(sym)))
399  template <class NodeTy>
400  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
401  unsigned Flag, SDValue Chain,
402  const MachinePointerInfo &PtrInfo) const {
403  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
404  getTargetNode(N, Ty, DAG, Flag));
405  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
406  }
407 
408  // This method creates the following nodes, which are necessary for
409  // computing a global symbol's address in large-GOT mode:
410  //
411  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
412  template <class NodeTy>
413  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
414  SelectionDAG &DAG, unsigned HiFlag,
415  unsigned LoFlag, SDValue Chain,
416  const MachinePointerInfo &PtrInfo) const {
417  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
418  getTargetNode(N, Ty, DAG, HiFlag));
419  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
420  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
421  getTargetNode(N, Ty, DAG, LoFlag));
422  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
423  }
424 
425  // This method creates the following nodes, which are necessary for
426  // computing a symbol's address in non-PIC mode:
427  //
428  // (add %hi(sym), %lo(sym))
429  //
430  // This method covers O32, N32 and N64 in sym32 mode.
431  template <class NodeTy>
432  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
433  SelectionDAG &DAG) const {
434  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
435  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
436  return DAG.getNode(ISD::ADD, DL, Ty,
437  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
438  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
439  }
440 
441  // This method creates the following nodes, which are necessary for
442  // computing a symbol's address in non-PIC mode for N64.
443  //
444  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
445  // 16), %lo(%sym))
446  //
447  // FIXME: This method is not efficent for (micro)MIPS64R6.
448  template <class NodeTy>
449  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
450  SelectionDAG &DAG) const {
451  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
452  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
453 
454  SDValue Highest =
455  DAG.getNode(MipsISD::Highest, DL, Ty,
456  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
457  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
458  SDValue HigherPart =
459  DAG.getNode(ISD::ADD, DL, Ty, Highest,
460  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
461  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
462  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
463  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
464  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
465  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
466 
467  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
468  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
469  }
470 
471  // This method creates the following nodes, which are necessary for
472  // computing a symbol's address using gp-relative addressing:
473  //
474  // (add $gp, %gp_rel(sym))
475  template <class NodeTy>
476  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
477  SelectionDAG &DAG, bool IsN64) const {
478  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
479  return DAG.getNode(
480  ISD::ADD, DL, Ty,
481  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
482  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
483  }
484 
485  /// This function fills Ops, which is the list of operands that will later
486  /// be used when a function call node is created. It also generates
487  /// copyToReg nodes to set up argument registers.
488  virtual void
489  getOpndList(SmallVectorImpl<SDValue> &Ops,
490  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
491  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
492  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
493  SDValue Chain) const;
494 
495  protected:
496  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
497  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
498 
499  // Subtarget Info
501  // Cache the ABI from the TargetMachine, we use it everywhere.
502  const MipsABIInfo &ABI;
503 
504  private:
505  // Create a TargetGlobalAddress node.
506  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
507  unsigned Flag) const;
508 
509  // Create a TargetExternalSymbol node.
510  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
511  unsigned Flag) const;
512 
513  // Create a TargetBlockAddress node.
514  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
515  unsigned Flag) const;
516 
517  // Create a TargetJumpTable node.
518  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
519  unsigned Flag) const;
520 
521  // Create a TargetConstantPool node.
522  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
523  unsigned Flag) const;
524 
525  // Lower Operand helpers
526  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
527  CallingConv::ID CallConv, bool isVarArg,
529  const SDLoc &dl, SelectionDAG &DAG,
530  SmallVectorImpl<SDValue> &InVals,
532 
533  // Lower Operand specifics
534  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
550  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
551  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
552  bool IsSRA) const;
553  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
555 
556  /// isEligibleForTailCallOptimization - Check whether the call is eligible
557  /// for tail call optimization.
558  virtual bool
559  isEligibleForTailCallOptimization(const CCState &CCInfo,
560  unsigned NextStackOffset,
561  const MipsFunctionInfo &FI) const = 0;
562 
563  /// copyByValArg - Copy argument registers which were used to pass a byval
564  /// argument to the stack. Create a stack frame object for the byval
565  /// argument.
566  void copyByValRegs(SDValue Chain, const SDLoc &DL,
567  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
568  const ISD::ArgFlagsTy &Flags,
569  SmallVectorImpl<SDValue> &InVals,
570  const Argument *FuncArg, unsigned FirstReg,
571  unsigned LastReg, const CCValAssign &VA,
572  MipsCCState &State) const;
573 
574  /// passByValArg - Pass a byval argument in registers or on stack.
575  void passByValArg(SDValue Chain, const SDLoc &DL,
576  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
577  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
579  unsigned FirstReg, unsigned LastReg,
580  const ISD::ArgFlagsTy &Flags, bool isLittle,
581  const CCValAssign &VA) const;
582 
583  /// writeVarArgRegs - Write variable function arguments passed in registers
584  /// to the stack. Also create a stack frame object for the first variable
585  /// argument.
586  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
587  const SDLoc &DL, SelectionDAG &DAG,
588  CCState &State) const;
589 
590  SDValue
591  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
593  const SDLoc &dl, SelectionDAG &DAG,
594  SmallVectorImpl<SDValue> &InVals) const override;
595 
596  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
597  SDValue Arg, const SDLoc &DL, bool IsTailCall,
598  SelectionDAG &DAG) const;
599 
601  SmallVectorImpl<SDValue> &InVals) const override;
602 
603  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
604  bool isVarArg,
606  LLVMContext &Context) const override;
607 
608  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
610  const SmallVectorImpl<SDValue> &OutVals,
611  const SDLoc &dl, SelectionDAG &DAG) const override;
612 
614  const SDLoc &DL, SelectionDAG &DAG) const;
615 
616  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
617 
618  // Inline asm support
619  ConstraintType getConstraintType(StringRef Constraint) const override;
620 
621  /// Examine constraint string and operand type and determine a weight value.
622  /// The operand object must already have been set up with the operand type.
623  ConstraintWeight getSingleConstraintMatchWeight(
624  AsmOperandInfo &info, const char *constraint) const override;
625 
626  /// This function parses registers that appear in inline-asm constraints.
627  /// It returns pair (0, 0) on failure.
628  std::pair<unsigned, const TargetRegisterClass *>
629  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
630 
631  std::pair<unsigned, const TargetRegisterClass *>
632  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
633  StringRef Constraint, MVT VT) const override;
634 
635  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
636  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
637  /// true it means one of the asm constraint of the inline asm instruction
638  /// being processed is 'm'.
639  void LowerAsmOperandForConstraint(SDValue Op,
640  std::string &Constraint,
641  std::vector<SDValue> &Ops,
642  SelectionDAG &DAG) const override;
643 
644  unsigned
645  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
646  if (ConstraintCode == "R")
648  else if (ConstraintCode == "ZC")
650  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
651  }
652 
653  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
654  Type *Ty, unsigned AS,
655  Instruction *I = nullptr) const override;
656 
657  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
658 
659  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
660  unsigned SrcAlign,
661  bool IsMemset, bool ZeroMemset,
662  bool MemcpyStrSrc,
663  MachineFunction &MF) const override;
664 
665  /// isFPImmLegal - Returns true if the target can instruction select the
666  /// specified FP immediate natively. If false, the legalizer will
667  /// materialize the FP immediate as a load from a constant pool.
668  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
669 
670  unsigned getJumpTableEncoding() const override;
671  bool useSoftFloat() const override;
672 
673  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
674  return true;
675  }
676 
677  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
678  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
679  MachineBasicBlock *BB,
680  unsigned Size, unsigned DstReg,
681  unsigned SrcRec) const;
682 
683  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
684  unsigned Size, unsigned BinOpcode,
685  bool Nand = false) const;
686  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
687  MachineBasicBlock *BB,
688  unsigned Size,
689  unsigned BinOpcode,
690  bool Nand = false) const;
691  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
692  MachineBasicBlock *BB,
693  unsigned Size) const;
694  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
695  MachineBasicBlock *BB,
696  unsigned Size) const;
697  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
698  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
699  bool isFPCmp, unsigned Opc) const;
700  };
701 
702  /// Create MipsTargetLowering objects.
703  const MipsTargetLowering *
705  const MipsSubtarget &STI);
706  const MipsTargetLowering *
708  const MipsSubtarget &STI);
709 
710 namespace Mips {
711 
713  const TargetLibraryInfo *libInfo);
714 
715 } // end namespace Mips
716 
717 } // end namespace llvm
718 
719 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:837
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
const MipsSubtarget & Subtarget
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
Shift and rotation operations.
Definition: ISDOpcodes.h:380
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:447
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:212
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:724
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:844
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:60
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MipsABIInfo & ABI
Conversion operators.
Definition: ISDOpcodes.h:443
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.