LLVM  9.0.0svn
MipsFastISel.cpp
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1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the MIPS-specific support for the FastISel class.
11 /// Some of the target-specific code is generated by tablegen in the file
12 /// MipsGenFastISel.inc, which is #included here.
13 ///
14 //===----------------------------------------------------------------------===//
15 
18 #include "MipsCCState.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMachineFunction.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "llvm/ADT/APInt.h"
25 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/CodeGen/FastISel.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/Constant.h"
44 #include "llvm/IR/Constants.h"
45 #include "llvm/IR/DataLayout.h"
46 #include "llvm/IR/Function.h"
48 #include "llvm/IR/GlobalValue.h"
49 #include "llvm/IR/GlobalVariable.h"
50 #include "llvm/IR/InstrTypes.h"
51 #include "llvm/IR/Instruction.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/IntrinsicInst.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/User.h"
57 #include "llvm/IR/Value.h"
58 #include "llvm/MC/MCContext.h"
59 #include "llvm/MC/MCInstrDesc.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/MC/MCSymbol.h"
62 #include "llvm/Support/Casting.h"
63 #include "llvm/Support/Compiler.h"
64 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <array>
71 #include <cassert>
72 #include <cstdint>
73 
74 #define DEBUG_TYPE "mips-fastisel"
75 
76 using namespace llvm;
77 
79 
80 namespace {
81 
82 class MipsFastISel final : public FastISel {
83 
84  // All possible address modes.
85  class Address {
86  public:
87  using BaseKind = enum { RegBase, FrameIndexBase };
88 
89  private:
90  BaseKind Kind = RegBase;
91  union {
92  unsigned Reg;
93  int FI;
94  } Base;
95 
96  int64_t Offset = 0;
97 
98  const GlobalValue *GV = nullptr;
99 
100  public:
101  // Innocuous defaults for our address.
102  Address() { Base.Reg = 0; }
103 
104  void setKind(BaseKind K) { Kind = K; }
105  BaseKind getKind() const { return Kind; }
106  bool isRegBase() const { return Kind == RegBase; }
107  bool isFIBase() const { return Kind == FrameIndexBase; }
108 
109  void setReg(unsigned Reg) {
110  assert(isRegBase() && "Invalid base register access!");
111  Base.Reg = Reg;
112  }
113 
114  unsigned getReg() const {
115  assert(isRegBase() && "Invalid base register access!");
116  return Base.Reg;
117  }
118 
119  void setFI(unsigned FI) {
120  assert(isFIBase() && "Invalid base frame index access!");
121  Base.FI = FI;
122  }
123 
124  unsigned getFI() const {
125  assert(isFIBase() && "Invalid base frame index access!");
126  return Base.FI;
127  }
128 
129  void setOffset(int64_t Offset_) { Offset = Offset_; }
130  int64_t getOffset() const { return Offset; }
131  void setGlobalValue(const GlobalValue *G) { GV = G; }
132  const GlobalValue *getGlobalValue() { return GV; }
133  };
134 
135  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
136  /// make the right decision when generating code for different targets.
137  const TargetMachine &TM;
138  const MipsSubtarget *Subtarget;
139  const TargetInstrInfo &TII;
140  const TargetLowering &TLI;
141  MipsFunctionInfo *MFI;
142 
143  // Convenience variables to avoid some queries.
145 
146  bool fastLowerArguments() override;
147  bool fastLowerCall(CallLoweringInfo &CLI) override;
148  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
149 
150  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
151  // floating point but not reject doing fast-isel in other
152  // situations
153 
154 private:
155  // Selection routines.
156  bool selectLogicalOp(const Instruction *I);
157  bool selectLoad(const Instruction *I);
158  bool selectStore(const Instruction *I);
159  bool selectBranch(const Instruction *I);
160  bool selectSelect(const Instruction *I);
161  bool selectCmp(const Instruction *I);
162  bool selectFPExt(const Instruction *I);
163  bool selectFPTrunc(const Instruction *I);
164  bool selectFPToInt(const Instruction *I, bool IsSigned);
165  bool selectRet(const Instruction *I);
166  bool selectTrunc(const Instruction *I);
167  bool selectIntExt(const Instruction *I);
168  bool selectShift(const Instruction *I);
169  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
170 
171  // Utility helper routines.
172  bool isTypeLegal(Type *Ty, MVT &VT);
173  bool isTypeSupported(Type *Ty, MVT &VT);
174  bool isLoadTypeLegal(Type *Ty, MVT &VT);
175  bool computeAddress(const Value *Obj, Address &Addr);
176  bool computeCallAddress(const Value *V, Address &Addr);
177  void simplifyAddress(Address &Addr);
178 
179  // Emit helper routines.
180  bool emitCmp(unsigned DestReg, const CmpInst *CI);
181  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
182  unsigned Alignment = 0);
183  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
184  MachineMemOperand *MMO = nullptr);
185  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
186  unsigned Alignment = 0);
187  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
189 
190  bool IsZExt);
191  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
192 
193  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
195  unsigned DestReg);
196  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
197  unsigned DestReg);
198 
199  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
200 
201  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
202  const Value *RHS);
203 
204  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
205  unsigned materializeGV(const GlobalValue *GV, MVT VT);
206  unsigned materializeInt(const Constant *C, MVT VT);
207  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
208  unsigned materializeExternalCallSym(MCSymbol *Syn);
209 
210  MachineInstrBuilder emitInst(unsigned Opc) {
211  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
212  }
213 
214  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
215  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
216  DstReg);
217  }
218 
219  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
220  unsigned MemReg, int64_t MemOffset) {
221  return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
222  }
223 
224  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
225  unsigned MemReg, int64_t MemOffset) {
226  return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
227  }
228 
229  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
230  const TargetRegisterClass *RC,
231  unsigned Op0, bool Op0IsKill,
232  unsigned Op1, bool Op1IsKill);
233 
234  // for some reason, this default is not generated by tablegen
235  // so we explicitly generate it here.
236  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
237  unsigned Op0, bool Op0IsKill, uint64_t imm1,
238  uint64_t imm2, unsigned Op3, bool Op3IsKill) {
239  return 0;
240  }
241 
242  // Call handling routines.
243 private:
244  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
245  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
246  unsigned &NumBytes);
247  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
248 
249  const MipsABIInfo &getABI() const {
250  return static_cast<const MipsTargetMachine &>(TM).getABI();
251  }
252 
253 public:
254  // Backend specific FastISel code.
255  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
256  const TargetLibraryInfo *libInfo)
257  : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
258  Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
259  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
260  MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
261  Context = &funcInfo.Fn->getContext();
262  UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
263  }
264 
265  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
266  unsigned fastMaterializeConstant(const Constant *C) override;
267  bool fastSelectInstruction(const Instruction *I) override;
268 
269 #include "MipsGenFastISel.inc"
270 };
271 
272 } // end anonymous namespace
273 
274 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
275  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
277 
278 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
279  CCValAssign::LocInfo LocInfo,
280  ISD::ArgFlagsTy ArgFlags, CCState &State) {
281  llvm_unreachable("should not be called");
282 }
283 
284 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
285  CCValAssign::LocInfo LocInfo,
286  ISD::ArgFlagsTy ArgFlags, CCState &State) {
287  llvm_unreachable("should not be called");
288 }
289 
290 #include "MipsGenCallingConv.inc"
291 
292 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
293  return CC_MipsO32;
294 }
295 
296 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
297  const Value *LHS, const Value *RHS) {
298  // Canonicalize immediates to the RHS first.
299  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
300  std::swap(LHS, RHS);
301 
302  unsigned Opc;
303  switch (ISDOpc) {
304  case ISD::AND:
305  Opc = Mips::AND;
306  break;
307  case ISD::OR:
308  Opc = Mips::OR;
309  break;
310  case ISD::XOR:
311  Opc = Mips::XOR;
312  break;
313  default:
314  llvm_unreachable("unexpected opcode");
315  }
316 
317  unsigned LHSReg = getRegForValue(LHS);
318  if (!LHSReg)
319  return 0;
320 
321  unsigned RHSReg;
322  if (const auto *C = dyn_cast<ConstantInt>(RHS))
323  RHSReg = materializeInt(C, MVT::i32);
324  else
325  RHSReg = getRegForValue(RHS);
326  if (!RHSReg)
327  return 0;
328 
329  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
330  if (!ResultReg)
331  return 0;
332 
333  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
334  return ResultReg;
335 }
336 
337 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
338  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
339  "Alloca should always return a pointer.");
340 
342  FuncInfo.StaticAllocaMap.find(AI);
343 
344  if (SI != FuncInfo.StaticAllocaMap.end()) {
345  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
346  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
347  ResultReg)
348  .addFrameIndex(SI->second)
349  .addImm(0);
350  return ResultReg;
351  }
352 
353  return 0;
354 }
355 
356 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
357  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
358  return 0;
359  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
360  const ConstantInt *CI = cast<ConstantInt>(C);
361  return materialize32BitInt(CI->getZExtValue(), RC);
362 }
363 
364 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
365  const TargetRegisterClass *RC) {
366  unsigned ResultReg = createResultReg(RC);
367 
368  if (isInt<16>(Imm)) {
369  unsigned Opc = Mips::ADDiu;
370  emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
371  return ResultReg;
372  } else if (isUInt<16>(Imm)) {
373  emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
374  return ResultReg;
375  }
376  unsigned Lo = Imm & 0xFFFF;
377  unsigned Hi = (Imm >> 16) & 0xFFFF;
378  if (Lo) {
379  // Both Lo and Hi have nonzero bits.
380  unsigned TmpReg = createResultReg(RC);
381  emitInst(Mips::LUi, TmpReg).addImm(Hi);
382  emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
383  } else {
384  emitInst(Mips::LUi, ResultReg).addImm(Hi);
385  }
386  return ResultReg;
387 }
388 
389 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
390  if (UnsupportedFPMode)
391  return 0;
392  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
393  if (VT == MVT::f32) {
394  const TargetRegisterClass *RC = &Mips::FGR32RegClass;
395  unsigned DestReg = createResultReg(RC);
396  unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
397  emitInst(Mips::MTC1, DestReg).addReg(TempReg);
398  return DestReg;
399  } else if (VT == MVT::f64) {
400  const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
401  unsigned DestReg = createResultReg(RC);
402  unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
403  unsigned TempReg2 =
404  materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
405  emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
406  return DestReg;
407  }
408  return 0;
409 }
410 
411 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
412  // For now 32-bit only.
413  if (VT != MVT::i32)
414  return 0;
415  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
416  unsigned DestReg = createResultReg(RC);
417  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
418  bool IsThreadLocal = GVar && GVar->isThreadLocal();
419  // TLS not supported at this time.
420  if (IsThreadLocal)
421  return 0;
422  emitInst(Mips::LW, DestReg)
423  .addReg(MFI->getGlobalBaseReg())
424  .addGlobalAddress(GV, 0, MipsII::MO_GOT);
425  if ((GV->hasInternalLinkage() ||
426  (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
427  unsigned TempReg = createResultReg(RC);
428  emitInst(Mips::ADDiu, TempReg)
429  .addReg(DestReg)
430  .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
431  DestReg = TempReg;
432  }
433  return DestReg;
434 }
435 
436 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
437  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
438  unsigned DestReg = createResultReg(RC);
439  emitInst(Mips::LW, DestReg)
440  .addReg(MFI->getGlobalBaseReg())
441  .addSym(Sym, MipsII::MO_GOT);
442  return DestReg;
443 }
444 
445 // Materialize a constant into a register, and return the register
446 // number (or zero if we failed to handle it).
447 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
448  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
449 
450  // Only handle simple types.
451  if (!CEVT.isSimple())
452  return 0;
453  MVT VT = CEVT.getSimpleVT();
454 
455  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
456  return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
457  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
458  return materializeGV(GV, VT);
459  else if (isa<ConstantInt>(C))
460  return materializeInt(C, VT);
461 
462  return 0;
463 }
464 
465 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
466  const User *U = nullptr;
467  unsigned Opcode = Instruction::UserOp1;
468  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
469  // Don't walk into other basic blocks unless the object is an alloca from
470  // another block, otherwise it may not have a virtual register assigned.
471  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
472  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
473  Opcode = I->getOpcode();
474  U = I;
475  }
476  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
477  Opcode = C->getOpcode();
478  U = C;
479  }
480  switch (Opcode) {
481  default:
482  break;
483  case Instruction::BitCast:
484  // Look through bitcasts.
485  return computeAddress(U->getOperand(0), Addr);
486  case Instruction::GetElementPtr: {
487  Address SavedAddr = Addr;
488  int64_t TmpOffset = Addr.getOffset();
489  // Iterate through the GEP folding the constants into offsets where
490  // we can.
492  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
493  ++i, ++GTI) {
494  const Value *Op = *i;
495  if (StructType *STy = GTI.getStructTypeOrNull()) {
496  const StructLayout *SL = DL.getStructLayout(STy);
497  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
498  TmpOffset += SL->getElementOffset(Idx);
499  } else {
500  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
501  while (true) {
502  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
503  // Constant-offset addressing.
504  TmpOffset += CI->getSExtValue() * S;
505  break;
506  }
507  if (canFoldAddIntoGEP(U, Op)) {
508  // A compatible add with a constant operand. Fold the constant.
509  ConstantInt *CI =
510  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
511  TmpOffset += CI->getSExtValue() * S;
512  // Iterate on the other operand.
513  Op = cast<AddOperator>(Op)->getOperand(0);
514  continue;
515  }
516  // Unsupported
517  goto unsupported_gep;
518  }
519  }
520  }
521  // Try to grab the base operand now.
522  Addr.setOffset(TmpOffset);
523  if (computeAddress(U->getOperand(0), Addr))
524  return true;
525  // We failed, restore everything and try the other options.
526  Addr = SavedAddr;
527  unsupported_gep:
528  break;
529  }
530  case Instruction::Alloca: {
531  const AllocaInst *AI = cast<AllocaInst>(Obj);
533  FuncInfo.StaticAllocaMap.find(AI);
534  if (SI != FuncInfo.StaticAllocaMap.end()) {
535  Addr.setKind(Address::FrameIndexBase);
536  Addr.setFI(SI->second);
537  return true;
538  }
539  break;
540  }
541  }
542  Addr.setReg(getRegForValue(Obj));
543  return Addr.getReg() != 0;
544 }
545 
546 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
547  const User *U = nullptr;
548  unsigned Opcode = Instruction::UserOp1;
549 
550  if (const auto *I = dyn_cast<Instruction>(V)) {
551  // Check if the value is defined in the same basic block. This information
552  // is crucial to know whether or not folding an operand is valid.
553  if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
554  Opcode = I->getOpcode();
555  U = I;
556  }
557  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
558  Opcode = C->getOpcode();
559  U = C;
560  }
561 
562  switch (Opcode) {
563  default:
564  break;
565  case Instruction::BitCast:
566  // Look past bitcasts if its operand is in the same BB.
567  return computeCallAddress(U->getOperand(0), Addr);
568  break;
569  case Instruction::IntToPtr:
570  // Look past no-op inttoptrs if its operand is in the same BB.
571  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
572  TLI.getPointerTy(DL))
573  return computeCallAddress(U->getOperand(0), Addr);
574  break;
575  case Instruction::PtrToInt:
576  // Look past no-op ptrtoints if its operand is in the same BB.
577  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
578  return computeCallAddress(U->getOperand(0), Addr);
579  break;
580  }
581 
582  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
583  Addr.setGlobalValue(GV);
584  return true;
585  }
586 
587  // If all else fails, try to materialize the value in a register.
588  if (!Addr.getGlobalValue()) {
589  Addr.setReg(getRegForValue(V));
590  return Addr.getReg() != 0;
591  }
592 
593  return false;
594 }
595 
596 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
597  EVT evt = TLI.getValueType(DL, Ty, true);
598  // Only handle simple types.
599  if (evt == MVT::Other || !evt.isSimple())
600  return false;
601  VT = evt.getSimpleVT();
602 
603  // Handle all legal types, i.e. a register that will directly hold this
604  // value.
605  return TLI.isTypeLegal(VT);
606 }
607 
608 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
609  if (Ty->isVectorTy())
610  return false;
611 
612  if (isTypeLegal(Ty, VT))
613  return true;
614 
615  // If this is a type than can be sign or zero-extended to a basic operation
616  // go ahead and accept it now.
617  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
618  return true;
619 
620  return false;
621 }
622 
623 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
624  if (isTypeLegal(Ty, VT))
625  return true;
626  // We will extend this in a later patch:
627  // If this is a type than can be sign or zero-extended to a basic operation
628  // go ahead and accept it now.
629  if (VT == MVT::i8 || VT == MVT::i16)
630  return true;
631  return false;
632 }
633 
634 // Because of how EmitCmp is called with fast-isel, you can
635 // end up with redundant "andi" instructions after the sequences emitted below.
636 // We should try and solve this issue in the future.
637 //
638 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
639  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
640  bool IsUnsigned = CI->isUnsigned();
641  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
642  if (LeftReg == 0)
643  return false;
644  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
645  if (RightReg == 0)
646  return false;
648 
649  switch (P) {
650  default:
651  return false;
652  case CmpInst::ICMP_EQ: {
653  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
654  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
655  emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
656  break;
657  }
658  case CmpInst::ICMP_NE: {
659  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
660  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
661  emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
662  break;
663  }
664  case CmpInst::ICMP_UGT:
665  emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
666  break;
667  case CmpInst::ICMP_ULT:
668  emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
669  break;
670  case CmpInst::ICMP_UGE: {
671  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
672  emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
673  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
674  break;
675  }
676  case CmpInst::ICMP_ULE: {
677  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
678  emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
679  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
680  break;
681  }
682  case CmpInst::ICMP_SGT:
683  emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
684  break;
685  case CmpInst::ICMP_SLT:
686  emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
687  break;
688  case CmpInst::ICMP_SGE: {
689  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
690  emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
691  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
692  break;
693  }
694  case CmpInst::ICMP_SLE: {
695  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
696  emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
697  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
698  break;
699  }
700  case CmpInst::FCMP_OEQ:
701  case CmpInst::FCMP_UNE:
702  case CmpInst::FCMP_OLT:
703  case CmpInst::FCMP_OLE:
704  case CmpInst::FCMP_OGT:
705  case CmpInst::FCMP_OGE: {
706  if (UnsupportedFPMode)
707  return false;
708  bool IsFloat = Left->getType()->isFloatTy();
709  bool IsDouble = Left->getType()->isDoubleTy();
710  if (!IsFloat && !IsDouble)
711  return false;
712  unsigned Opc, CondMovOpc;
713  switch (P) {
714  case CmpInst::FCMP_OEQ:
715  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
716  CondMovOpc = Mips::MOVT_I;
717  break;
718  case CmpInst::FCMP_UNE:
719  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
720  CondMovOpc = Mips::MOVF_I;
721  break;
722  case CmpInst::FCMP_OLT:
723  Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
724  CondMovOpc = Mips::MOVT_I;
725  break;
726  case CmpInst::FCMP_OLE:
727  Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
728  CondMovOpc = Mips::MOVT_I;
729  break;
730  case CmpInst::FCMP_OGT:
731  Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
732  CondMovOpc = Mips::MOVF_I;
733  break;
734  case CmpInst::FCMP_OGE:
735  Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
736  CondMovOpc = Mips::MOVF_I;
737  break;
738  default:
739  llvm_unreachable("Only switching of a subset of CCs.");
740  }
741  unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
742  unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
743  emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744  emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
745  emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
746  .addReg(RightReg);
747  emitInst(CondMovOpc, ResultReg)
748  .addReg(RegWithOne)
749  .addReg(Mips::FCC0)
750  .addReg(RegWithZero);
751  break;
752  }
753  }
754  return true;
755 }
756 
757 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
758  unsigned Alignment) {
759  //
760  // more cases will be handled here in following patches.
761  //
762  unsigned Opc;
763  switch (VT.SimpleTy) {
764  case MVT::i32:
765  ResultReg = createResultReg(&Mips::GPR32RegClass);
766  Opc = Mips::LW;
767  break;
768  case MVT::i16:
769  ResultReg = createResultReg(&Mips::GPR32RegClass);
770  Opc = Mips::LHu;
771  break;
772  case MVT::i8:
773  ResultReg = createResultReg(&Mips::GPR32RegClass);
774  Opc = Mips::LBu;
775  break;
776  case MVT::f32:
777  if (UnsupportedFPMode)
778  return false;
779  ResultReg = createResultReg(&Mips::FGR32RegClass);
780  Opc = Mips::LWC1;
781  break;
782  case MVT::f64:
783  if (UnsupportedFPMode)
784  return false;
785  ResultReg = createResultReg(&Mips::AFGR64RegClass);
786  Opc = Mips::LDC1;
787  break;
788  default:
789  return false;
790  }
791  if (Addr.isRegBase()) {
792  simplifyAddress(Addr);
793  emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
794  return true;
795  }
796  if (Addr.isFIBase()) {
797  unsigned FI = Addr.getFI();
798  unsigned Align = 4;
799  int64_t Offset = Addr.getOffset();
800  MachineFrameInfo &MFI = MF->getFrameInfo();
801  MachineMemOperand *MMO = MF->getMachineMemOperand(
803  MFI.getObjectSize(FI), Align);
804  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
805  .addFrameIndex(FI)
806  .addImm(Offset)
807  .addMemOperand(MMO);
808  return true;
809  }
810  return false;
811 }
812 
813 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
814  unsigned Alignment) {
815  //
816  // more cases will be handled here in following patches.
817  //
818  unsigned Opc;
819  switch (VT.SimpleTy) {
820  case MVT::i8:
821  Opc = Mips::SB;
822  break;
823  case MVT::i16:
824  Opc = Mips::SH;
825  break;
826  case MVT::i32:
827  Opc = Mips::SW;
828  break;
829  case MVT::f32:
830  if (UnsupportedFPMode)
831  return false;
832  Opc = Mips::SWC1;
833  break;
834  case MVT::f64:
835  if (UnsupportedFPMode)
836  return false;
837  Opc = Mips::SDC1;
838  break;
839  default:
840  return false;
841  }
842  if (Addr.isRegBase()) {
843  simplifyAddress(Addr);
844  emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
845  return true;
846  }
847  if (Addr.isFIBase()) {
848  unsigned FI = Addr.getFI();
849  unsigned Align = 4;
850  int64_t Offset = Addr.getOffset();
851  MachineFrameInfo &MFI = MF->getFrameInfo();
852  MachineMemOperand *MMO = MF->getMachineMemOperand(
854  MFI.getObjectSize(FI), Align);
855  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
856  .addReg(SrcReg)
857  .addFrameIndex(FI)
858  .addImm(Offset)
859  .addMemOperand(MMO);
860  return true;
861  }
862  return false;
863 }
864 
865 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
866  MVT VT;
867  if (!isTypeSupported(I->getType(), VT))
868  return false;
869 
870  unsigned ResultReg;
871  switch (I->getOpcode()) {
872  default:
873  llvm_unreachable("Unexpected instruction.");
874  case Instruction::And:
875  ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
876  break;
877  case Instruction::Or:
878  ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
879  break;
880  case Instruction::Xor:
881  ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
882  break;
883  }
884 
885  if (!ResultReg)
886  return false;
887 
888  updateValueMap(I, ResultReg);
889  return true;
890 }
891 
892 bool MipsFastISel::selectLoad(const Instruction *I) {
893  // Atomic loads need special handling.
894  if (cast<LoadInst>(I)->isAtomic())
895  return false;
896 
897  // Verify we have a legal type before going any further.
898  MVT VT;
899  if (!isLoadTypeLegal(I->getType(), VT))
900  return false;
901 
902  // See if we can handle this address.
903  Address Addr;
904  if (!computeAddress(I->getOperand(0), Addr))
905  return false;
906 
907  unsigned ResultReg;
908  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
909  return false;
910  updateValueMap(I, ResultReg);
911  return true;
912 }
913 
914 bool MipsFastISel::selectStore(const Instruction *I) {
915  Value *Op0 = I->getOperand(0);
916  unsigned SrcReg = 0;
917 
918  // Atomic stores need special handling.
919  if (cast<StoreInst>(I)->isAtomic())
920  return false;
921 
922  // Verify we have a legal type before going any further.
923  MVT VT;
924  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
925  return false;
926 
927  // Get the value to be stored into a register.
928  SrcReg = getRegForValue(Op0);
929  if (SrcReg == 0)
930  return false;
931 
932  // See if we can handle this address.
933  Address Addr;
934  if (!computeAddress(I->getOperand(1), Addr))
935  return false;
936 
937  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
938  return false;
939  return true;
940 }
941 
942 // This can cause a redundant sltiu to be generated.
943 // FIXME: try and eliminate this in a future patch.
944 bool MipsFastISel::selectBranch(const Instruction *I) {
945  const BranchInst *BI = cast<BranchInst>(I);
946  MachineBasicBlock *BrBB = FuncInfo.MBB;
947  //
948  // TBB is the basic block for the case where the comparison is true.
949  // FBB is the basic block for the case where the comparison is false.
950  // if (cond) goto TBB
951  // goto FBB
952  // TBB:
953  //
954  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
955  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
956  // For now, just try the simplest case where it's fed by a compare.
957  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
958  MVT CIMVT =
959  TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT();
960  if (CIMVT == MVT::i1)
961  return false;
962 
963  unsigned CondReg = getRegForValue(CI);
964  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
965  .addReg(CondReg)
966  .addMBB(TBB);
967  finishCondBranch(BI->getParent(), TBB, FBB);
968  return true;
969  }
970  return false;
971 }
972 
973 bool MipsFastISel::selectCmp(const Instruction *I) {
974  const CmpInst *CI = cast<CmpInst>(I);
975  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
976  if (!emitCmp(ResultReg, CI))
977  return false;
978  updateValueMap(I, ResultReg);
979  return true;
980 }
981 
982 // Attempt to fast-select a floating-point extend instruction.
983 bool MipsFastISel::selectFPExt(const Instruction *I) {
984  if (UnsupportedFPMode)
985  return false;
986  Value *Src = I->getOperand(0);
987  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
988  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
989 
990  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
991  return false;
992 
993  unsigned SrcReg =
994  getRegForValue(Src); // this must be a 32bit floating point register class
995  // maybe we should handle this differently
996  if (!SrcReg)
997  return false;
998 
999  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1000  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1001  updateValueMap(I, DestReg);
1002  return true;
1003 }
1004 
1005 bool MipsFastISel::selectSelect(const Instruction *I) {
1006  assert(isa<SelectInst>(I) && "Expected a select instruction.");
1007 
1008  LLVM_DEBUG(dbgs() << "selectSelect\n");
1009 
1010  MVT VT;
1011  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1012  LLVM_DEBUG(
1013  dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1014  return false;
1015  }
1016 
1017  unsigned CondMovOpc;
1018  const TargetRegisterClass *RC;
1019 
1020  if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1021  CondMovOpc = Mips::MOVN_I_I;
1022  RC = &Mips::GPR32RegClass;
1023  } else if (VT == MVT::f32) {
1024  CondMovOpc = Mips::MOVN_I_S;
1025  RC = &Mips::FGR32RegClass;
1026  } else if (VT == MVT::f64) {
1027  CondMovOpc = Mips::MOVN_I_D32;
1028  RC = &Mips::AFGR64RegClass;
1029  } else
1030  return false;
1031 
1032  const SelectInst *SI = cast<SelectInst>(I);
1033  const Value *Cond = SI->getCondition();
1034  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1035  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1036  unsigned CondReg = getRegForValue(Cond);
1037 
1038  if (!Src1Reg || !Src2Reg || !CondReg)
1039  return false;
1040 
1041  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1042  if (!ZExtCondReg)
1043  return false;
1044 
1045  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1046  return false;
1047 
1048  unsigned ResultReg = createResultReg(RC);
1049  unsigned TempReg = createResultReg(RC);
1050 
1051  if (!ResultReg || !TempReg)
1052  return false;
1053 
1054  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1055  emitInst(CondMovOpc, ResultReg)
1056  .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1057  updateValueMap(I, ResultReg);
1058  return true;
1059 }
1060 
1061 // Attempt to fast-select a floating-point truncate instruction.
1062 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1063  if (UnsupportedFPMode)
1064  return false;
1065  Value *Src = I->getOperand(0);
1066  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1067  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1068 
1069  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1070  return false;
1071 
1072  unsigned SrcReg = getRegForValue(Src);
1073  if (!SrcReg)
1074  return false;
1075 
1076  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1077  if (!DestReg)
1078  return false;
1079 
1080  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1081  updateValueMap(I, DestReg);
1082  return true;
1083 }
1084 
1085 // Attempt to fast-select a floating-point-to-integer conversion.
1086 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1087  if (UnsupportedFPMode)
1088  return false;
1089  MVT DstVT, SrcVT;
1090  if (!IsSigned)
1091  return false; // We don't handle this case yet. There is no native
1092  // instruction for this but it can be synthesized.
1093  Type *DstTy = I->getType();
1094  if (!isTypeLegal(DstTy, DstVT))
1095  return false;
1096 
1097  if (DstVT != MVT::i32)
1098  return false;
1099 
1100  Value *Src = I->getOperand(0);
1101  Type *SrcTy = Src->getType();
1102  if (!isTypeLegal(SrcTy, SrcVT))
1103  return false;
1104 
1105  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1106  return false;
1107 
1108  unsigned SrcReg = getRegForValue(Src);
1109  if (SrcReg == 0)
1110  return false;
1111 
1112  // Determine the opcode for the conversion, which takes place
1113  // entirely within FPRs.
1114  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1115  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1116  unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1117 
1118  // Generate the convert.
1119  emitInst(Opc, TempReg).addReg(SrcReg);
1120  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1121 
1122  updateValueMap(I, DestReg);
1123  return true;
1124 }
1125 
1126 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1127  SmallVectorImpl<MVT> &OutVTs,
1128  unsigned &NumBytes) {
1129  CallingConv::ID CC = CLI.CallConv;
1131  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1132  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1133  // Get a count of how many bytes are to be pushed on the stack.
1134  NumBytes = CCInfo.getNextStackOffset();
1135  // This is the minimum argument area used for A0-A3.
1136  if (NumBytes < 16)
1137  NumBytes = 16;
1138 
1139  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1140  // Process the args.
1141  MVT firstMVT;
1142  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1143  CCValAssign &VA = ArgLocs[i];
1144  const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1145  MVT ArgVT = OutVTs[VA.getValNo()];
1146 
1147  if (i == 0) {
1148  firstMVT = ArgVT;
1149  if (ArgVT == MVT::f32) {
1150  VA.convertToReg(Mips::F12);
1151  } else if (ArgVT == MVT::f64) {
1152  VA.convertToReg(Mips::D6);
1153  }
1154  } else if (i == 1) {
1155  if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1156  if (ArgVT == MVT::f32) {
1157  VA.convertToReg(Mips::F14);
1158  } else if (ArgVT == MVT::f64) {
1159  VA.convertToReg(Mips::D7);
1160  }
1161  }
1162  }
1163  if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1164  (ArgVT == MVT::i8)) &&
1165  VA.isMemLoc()) {
1166  switch (VA.getLocMemOffset()) {
1167  case 0:
1168  VA.convertToReg(Mips::A0);
1169  break;
1170  case 4:
1171  VA.convertToReg(Mips::A1);
1172  break;
1173  case 8:
1174  VA.convertToReg(Mips::A2);
1175  break;
1176  case 12:
1177  VA.convertToReg(Mips::A3);
1178  break;
1179  default:
1180  break;
1181  }
1182  }
1183  unsigned ArgReg = getRegForValue(ArgVal);
1184  if (!ArgReg)
1185  return false;
1186 
1187  // Handle arg promotion: SExt, ZExt, AExt.
1188  switch (VA.getLocInfo()) {
1189  case CCValAssign::Full:
1190  break;
1191  case CCValAssign::AExt:
1192  case CCValAssign::SExt: {
1193  MVT DestVT = VA.getLocVT();
1194  MVT SrcVT = ArgVT;
1195  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1196  if (!ArgReg)
1197  return false;
1198  break;
1199  }
1200  case CCValAssign::ZExt: {
1201  MVT DestVT = VA.getLocVT();
1202  MVT SrcVT = ArgVT;
1203  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1204  if (!ArgReg)
1205  return false;
1206  break;
1207  }
1208  default:
1209  llvm_unreachable("Unknown arg promotion!");
1210  }
1211 
1212  // Now copy/store arg to correct locations.
1213  if (VA.isRegLoc() && !VA.needsCustom()) {
1214  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1215  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1216  CLI.OutRegs.push_back(VA.getLocReg());
1217  } else if (VA.needsCustom()) {
1218  llvm_unreachable("Mips does not use custom args.");
1219  return false;
1220  } else {
1221  //
1222  // FIXME: This path will currently return false. It was copied
1223  // from the AArch64 port and should be essentially fine for Mips too.
1224  // The work to finish up this path will be done in a follow-on patch.
1225  //
1226  assert(VA.isMemLoc() && "Assuming store on stack.");
1227  // Don't emit stores for undef values.
1228  if (isa<UndefValue>(ArgVal))
1229  continue;
1230 
1231  // Need to store on the stack.
1232  // FIXME: This alignment is incorrect but this path is disabled
1233  // for now (will return false). We need to determine the right alignment
1234  // based on the normal alignment for the underlying machine type.
1235  //
1236  unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1237 
1238  unsigned BEAlign = 0;
1239  if (ArgSize < 8 && !Subtarget->isLittle())
1240  BEAlign = 8 - ArgSize;
1241 
1242  Address Addr;
1243  Addr.setKind(Address::RegBase);
1244  Addr.setReg(Mips::SP);
1245  Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1246 
1247  unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1248  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1249  MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1250  MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1251  (void)(MMO);
1252  // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1253  return false; // can't store on the stack yet.
1254  }
1255  }
1256 
1257  return true;
1258 }
1259 
1260 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1261  unsigned NumBytes) {
1262  CallingConv::ID CC = CLI.CallConv;
1263  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1264  if (RetVT != MVT::isVoid) {
1266  MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1267 
1268  CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1269  CLI.Symbol ? CLI.Symbol->getName().data()
1270  : nullptr);
1271 
1272  // Only handle a single return value.
1273  if (RVLocs.size() != 1)
1274  return false;
1275  // Copy all of the result registers out of their specified physreg.
1276  MVT CopyVT = RVLocs[0].getValVT();
1277  // Special handling for extended integers.
1278  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1279  CopyVT = MVT::i32;
1280 
1281  unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1282  if (!ResultReg)
1283  return false;
1284  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1285  TII.get(TargetOpcode::COPY),
1286  ResultReg).addReg(RVLocs[0].getLocReg());
1287  CLI.InRegs.push_back(RVLocs[0].getLocReg());
1288 
1289  CLI.ResultReg = ResultReg;
1290  CLI.NumResultRegs = 1;
1291  }
1292  return true;
1293 }
1294 
1295 bool MipsFastISel::fastLowerArguments() {
1296  LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1297 
1298  if (!FuncInfo.CanLowerReturn) {
1299  LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1300  return false;
1301  }
1302 
1303  const Function *F = FuncInfo.Fn;
1304  if (F->isVarArg()) {
1305  LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1306  return false;
1307  }
1308 
1309  CallingConv::ID CC = F->getCallingConv();
1310  if (CC != CallingConv::C) {
1311  LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1312  return false;
1313  }
1314 
1315  std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1316  Mips::A3}};
1317  std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1318  std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1319  auto NextGPR32 = GPR32ArgRegs.begin();
1320  auto NextFGR32 = FGR32ArgRegs.begin();
1321  auto NextAFGR64 = AFGR64ArgRegs.begin();
1322 
1323  struct AllocatedReg {
1324  const TargetRegisterClass *RC;
1325  unsigned Reg;
1326  AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1327  : RC(RC), Reg(Reg) {}
1328  };
1329 
1330  // Only handle simple cases. i.e. All arguments are directly mapped to
1331  // registers of the appropriate type.
1332  SmallVector<AllocatedReg, 4> Allocation;
1333  for (const auto &FormalArg : F->args()) {
1334  if (FormalArg.hasAttribute(Attribute::InReg) ||
1335  FormalArg.hasAttribute(Attribute::StructRet) ||
1336  FormalArg.hasAttribute(Attribute::ByVal)) {
1337  LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1338  return false;
1339  }
1340 
1341  Type *ArgTy = FormalArg.getType();
1342  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1343  LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1344  return false;
1345  }
1346 
1347  EVT ArgVT = TLI.getValueType(DL, ArgTy);
1348  LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1349  << ArgVT.getEVTString() << "\n");
1350  if (!ArgVT.isSimple()) {
1351  LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1352  return false;
1353  }
1354 
1355  switch (ArgVT.getSimpleVT().SimpleTy) {
1356  case MVT::i1:
1357  case MVT::i8:
1358  case MVT::i16:
1359  if (!FormalArg.hasAttribute(Attribute::SExt) &&
1360  !FormalArg.hasAttribute(Attribute::ZExt)) {
1361  // It must be any extend, this shouldn't happen for clang-generated IR
1362  // so just fall back on SelectionDAG.
1363  LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1364  return false;
1365  }
1366 
1367  if (NextGPR32 == GPR32ArgRegs.end()) {
1368  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1369  return false;
1370  }
1371 
1372  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1373  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1374 
1375  // Allocating any GPR32 prohibits further use of floating point arguments.
1376  NextFGR32 = FGR32ArgRegs.end();
1377  NextAFGR64 = AFGR64ArgRegs.end();
1378  break;
1379 
1380  case MVT::i32:
1381  if (FormalArg.hasAttribute(Attribute::ZExt)) {
1382  // The O32 ABI does not permit a zero-extended i32.
1383  LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1384  return false;
1385  }
1386 
1387  if (NextGPR32 == GPR32ArgRegs.end()) {
1388  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1389  return false;
1390  }
1391 
1392  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1393  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1394 
1395  // Allocating any GPR32 prohibits further use of floating point arguments.
1396  NextFGR32 = FGR32ArgRegs.end();
1397  NextAFGR64 = AFGR64ArgRegs.end();
1398  break;
1399 
1400  case MVT::f32:
1401  if (UnsupportedFPMode) {
1402  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1403  return false;
1404  }
1405  if (NextFGR32 == FGR32ArgRegs.end()) {
1406  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1407  return false;
1408  }
1409  LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1410  Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1411  // Allocating an FGR32 also allocates the super-register AFGR64, and
1412  // ABI rules require us to skip the corresponding GPR32.
1413  if (NextGPR32 != GPR32ArgRegs.end())
1414  NextGPR32++;
1415  if (NextAFGR64 != AFGR64ArgRegs.end())
1416  NextAFGR64++;
1417  break;
1418 
1419  case MVT::f64:
1420  if (UnsupportedFPMode) {
1421  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1422  return false;
1423  }
1424  if (NextAFGR64 == AFGR64ArgRegs.end()) {
1425  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1426  return false;
1427  }
1428  LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1429  Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1430  // Allocating an FGR32 also allocates the super-register AFGR64, and
1431  // ABI rules require us to skip the corresponding GPR32 pair.
1432  if (NextGPR32 != GPR32ArgRegs.end())
1433  NextGPR32++;
1434  if (NextGPR32 != GPR32ArgRegs.end())
1435  NextGPR32++;
1436  if (NextFGR32 != FGR32ArgRegs.end())
1437  NextFGR32++;
1438  break;
1439 
1440  default:
1441  LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1442  return false;
1443  }
1444  }
1445 
1446  for (const auto &FormalArg : F->args()) {
1447  unsigned ArgNo = FormalArg.getArgNo();
1448  unsigned SrcReg = Allocation[ArgNo].Reg;
1449  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1450  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1451  // Without this, EmitLiveInCopies may eliminate the livein if its only
1452  // use is a bitcast (which isn't turned into an instruction).
1453  unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1454  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1455  TII.get(TargetOpcode::COPY), ResultReg)
1456  .addReg(DstReg, getKillRegState(true));
1457  updateValueMap(&FormalArg, ResultReg);
1458  }
1459 
1460  // Calculate the size of the incoming arguments area.
1461  // We currently reject all the cases where this would be non-zero.
1462  unsigned IncomingArgSizeInBytes = 0;
1463 
1464  // Account for the reserved argument area on ABI's that have one (O32).
1465  // It seems strange to do this on the caller side but it's necessary in
1466  // SelectionDAG's implementation.
1467  IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1468  IncomingArgSizeInBytes);
1469 
1470  MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1471  false);
1472 
1473  return true;
1474 }
1475 
1476 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1477  CallingConv::ID CC = CLI.CallConv;
1478  bool IsTailCall = CLI.IsTailCall;
1479  bool IsVarArg = CLI.IsVarArg;
1480  const Value *Callee = CLI.Callee;
1481  MCSymbol *Symbol = CLI.Symbol;
1482 
1483  // Do not handle FastCC.
1484  if (CC == CallingConv::Fast)
1485  return false;
1486 
1487  // Allow SelectionDAG isel to handle tail calls.
1488  if (IsTailCall)
1489  return false;
1490 
1491  // Let SDISel handle vararg functions.
1492  if (IsVarArg)
1493  return false;
1494 
1495  // FIXME: Only handle *simple* calls for now.
1496  MVT RetVT;
1497  if (CLI.RetTy->isVoidTy())
1498  RetVT = MVT::isVoid;
1499  else if (!isTypeSupported(CLI.RetTy, RetVT))
1500  return false;
1501 
1502  for (auto Flag : CLI.OutFlags)
1503  if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1504  return false;
1505 
1506  // Set up the argument vectors.
1507  SmallVector<MVT, 16> OutVTs;
1508  OutVTs.reserve(CLI.OutVals.size());
1509 
1510  for (auto *Val : CLI.OutVals) {
1511  MVT VT;
1512  if (!isTypeLegal(Val->getType(), VT) &&
1513  !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1514  return false;
1515 
1516  // We don't handle vector parameters yet.
1517  if (VT.isVector() || VT.getSizeInBits() > 64)
1518  return false;
1519 
1520  OutVTs.push_back(VT);
1521  }
1522 
1523  Address Addr;
1524  if (!computeCallAddress(Callee, Addr))
1525  return false;
1526 
1527  // Handle the arguments now that we've gotten them.
1528  unsigned NumBytes;
1529  if (!processCallArgs(CLI, OutVTs, NumBytes))
1530  return false;
1531 
1532  if (!Addr.getGlobalValue())
1533  return false;
1534 
1535  // Issue the call.
1536  unsigned DestAddress;
1537  if (Symbol)
1538  DestAddress = materializeExternalCallSym(Symbol);
1539  else
1540  DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1541  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1542  MachineInstrBuilder MIB =
1543  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1544  Mips::RA).addReg(Mips::T9);
1545 
1546  // Add implicit physical register uses to the call.
1547  for (auto Reg : CLI.OutRegs)
1549 
1550  // Add a register mask with the call-preserved registers.
1551  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1552  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1553 
1554  CLI.Call = MIB;
1555 
1556  if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1557  // Attach callee address to the instruction, let asm printer emit
1558  // .reloc R_MIPS_JALR.
1559  if (Symbol)
1560  MIB.addSym(Symbol, MipsII::MO_JALR);
1561  else
1562  MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
1563  Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
1564  }
1565 
1566  // Finish off the call including any return values.
1567  return finishCall(CLI, RetVT, NumBytes);
1568 }
1569 
1570 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1571  switch (II->getIntrinsicID()) {
1572  default:
1573  return false;
1574  case Intrinsic::bswap: {
1575  Type *RetTy = II->getCalledFunction()->getReturnType();
1576 
1577  MVT VT;
1578  if (!isTypeSupported(RetTy, VT))
1579  return false;
1580 
1581  unsigned SrcReg = getRegForValue(II->getOperand(0));
1582  if (SrcReg == 0)
1583  return false;
1584  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1585  if (DestReg == 0)
1586  return false;
1587  if (VT == MVT::i16) {
1588  if (Subtarget->hasMips32r2()) {
1589  emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1590  updateValueMap(II, DestReg);
1591  return true;
1592  } else {
1593  unsigned TempReg[3];
1594  for (int i = 0; i < 3; i++) {
1595  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1596  if (TempReg[i] == 0)
1597  return false;
1598  }
1599  emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1600  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1601  emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1602  emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1603  updateValueMap(II, DestReg);
1604  return true;
1605  }
1606  } else if (VT == MVT::i32) {
1607  if (Subtarget->hasMips32r2()) {
1608  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1609  emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1610  emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1611  updateValueMap(II, DestReg);
1612  return true;
1613  } else {
1614  unsigned TempReg[8];
1615  for (int i = 0; i < 8; i++) {
1616  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1617  if (TempReg[i] == 0)
1618  return false;
1619  }
1620 
1621  emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1622  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1623  emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1624  emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1625 
1626  emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1627  emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1628 
1629  emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1630  emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1631  emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1632  updateValueMap(II, DestReg);
1633  return true;
1634  }
1635  }
1636  return false;
1637  }
1638  case Intrinsic::memcpy:
1639  case Intrinsic::memmove: {
1640  const auto *MTI = cast<MemTransferInst>(II);
1641  // Don't handle volatile.
1642  if (MTI->isVolatile())
1643  return false;
1644  if (!MTI->getLength()->getType()->isIntegerTy(32))
1645  return false;
1646  const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1647  return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1648  }
1649  case Intrinsic::memset: {
1650  const MemSetInst *MSI = cast<MemSetInst>(II);
1651  // Don't handle volatile.
1652  if (MSI->isVolatile())
1653  return false;
1654  if (!MSI->getLength()->getType()->isIntegerTy(32))
1655  return false;
1656  return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1657  }
1658  }
1659  return false;
1660 }
1661 
1662 bool MipsFastISel::selectRet(const Instruction *I) {
1663  const Function &F = *I->getParent()->getParent();
1664  const ReturnInst *Ret = cast<ReturnInst>(I);
1665 
1666  LLVM_DEBUG(dbgs() << "selectRet\n");
1667 
1668  if (!FuncInfo.CanLowerReturn)
1669  return false;
1670 
1671  // Build a list of return value registers.
1672  SmallVector<unsigned, 4> RetRegs;
1673 
1674  if (Ret->getNumOperands() > 0) {
1676 
1677  // Do not handle FastCC.
1678  if (CC == CallingConv::Fast)
1679  return false;
1680 
1682  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1683 
1684  // Analyze operands of the call, assigning locations to each operand.
1686  MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1687  I->getContext());
1688  CCAssignFn *RetCC = RetCC_Mips;
1689  CCInfo.AnalyzeReturn(Outs, RetCC);
1690 
1691  // Only handle a single return value for now.
1692  if (ValLocs.size() != 1)
1693  return false;
1694 
1695  CCValAssign &VA = ValLocs[0];
1696  const Value *RV = Ret->getOperand(0);
1697 
1698  // Don't bother handling odd stuff for now.
1699  if ((VA.getLocInfo() != CCValAssign::Full) &&
1700  (VA.getLocInfo() != CCValAssign::BCvt))
1701  return false;
1702 
1703  // Only handle register returns for now.
1704  if (!VA.isRegLoc())
1705  return false;
1706 
1707  unsigned Reg = getRegForValue(RV);
1708  if (Reg == 0)
1709  return false;
1710 
1711  unsigned SrcReg = Reg + VA.getValNo();
1712  unsigned DestReg = VA.getLocReg();
1713  // Avoid a cross-class copy. This is very unlikely.
1714  if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1715  return false;
1716 
1717  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1718  if (!RVEVT.isSimple())
1719  return false;
1720 
1721  if (RVEVT.isVector())
1722  return false;
1723 
1724  MVT RVVT = RVEVT.getSimpleVT();
1725  if (RVVT == MVT::f128)
1726  return false;
1727 
1728  // Do not handle FGR64 returns for now.
1729  if (RVVT == MVT::f64 && UnsupportedFPMode) {
1730  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1731  return false;
1732  }
1733 
1734  MVT DestVT = VA.getValVT();
1735  // Special handling for extended integers.
1736  if (RVVT != DestVT) {
1737  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1738  return false;
1739 
1740  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1741  bool IsZExt = Outs[0].Flags.isZExt();
1742  SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1743  if (SrcReg == 0)
1744  return false;
1745  }
1746  }
1747 
1748  // Make the copy.
1749  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1750  TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1751 
1752  // Add register to return instruction.
1753  RetRegs.push_back(VA.getLocReg());
1754  }
1755  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1756  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1757  MIB.addReg(RetRegs[i], RegState::Implicit);
1758  return true;
1759 }
1760 
1761 bool MipsFastISel::selectTrunc(const Instruction *I) {
1762  // The high bits for a type smaller than the register size are assumed to be
1763  // undefined.
1764  Value *Op = I->getOperand(0);
1765 
1766  EVT SrcVT, DestVT;
1767  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1768  DestVT = TLI.getValueType(DL, I->getType(), true);
1769 
1770  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1771  return false;
1772  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1773  return false;
1774 
1775  unsigned SrcReg = getRegForValue(Op);
1776  if (!SrcReg)
1777  return false;
1778 
1779  // Because the high bits are undefined, a truncate doesn't generate
1780  // any code.
1781  updateValueMap(I, SrcReg);
1782  return true;
1783 }
1784 
1785 bool MipsFastISel::selectIntExt(const Instruction *I) {
1786  Type *DestTy = I->getType();
1787  Value *Src = I->getOperand(0);
1788  Type *SrcTy = Src->getType();
1789 
1790  bool isZExt = isa<ZExtInst>(I);
1791  unsigned SrcReg = getRegForValue(Src);
1792  if (!SrcReg)
1793  return false;
1794 
1795  EVT SrcEVT, DestEVT;
1796  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1797  DestEVT = TLI.getValueType(DL, DestTy, true);
1798  if (!SrcEVT.isSimple())
1799  return false;
1800  if (!DestEVT.isSimple())
1801  return false;
1802 
1803  MVT SrcVT = SrcEVT.getSimpleVT();
1804  MVT DestVT = DestEVT.getSimpleVT();
1805  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1806 
1807  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1808  return false;
1809  updateValueMap(I, ResultReg);
1810  return true;
1811 }
1812 
1813 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1814  unsigned DestReg) {
1815  unsigned ShiftAmt;
1816  switch (SrcVT.SimpleTy) {
1817  default:
1818  return false;
1819  case MVT::i8:
1820  ShiftAmt = 24;
1821  break;
1822  case MVT::i16:
1823  ShiftAmt = 16;
1824  break;
1825  }
1826  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1827  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1828  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1829  return true;
1830 }
1831 
1832 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1833  unsigned DestReg) {
1834  switch (SrcVT.SimpleTy) {
1835  default:
1836  return false;
1837  case MVT::i8:
1838  emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1839  break;
1840  case MVT::i16:
1841  emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1842  break;
1843  }
1844  return true;
1845 }
1846 
1847 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1848  unsigned DestReg) {
1849  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1850  return false;
1851  if (Subtarget->hasMips32r2())
1852  return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1853  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1854 }
1855 
1856 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1857  unsigned DestReg) {
1858  int64_t Imm;
1859 
1860  switch (SrcVT.SimpleTy) {
1861  default:
1862  return false;
1863  case MVT::i1:
1864  Imm = 1;
1865  break;
1866  case MVT::i8:
1867  Imm = 0xff;
1868  break;
1869  case MVT::i16:
1870  Imm = 0xffff;
1871  break;
1872  }
1873 
1874  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1875  return true;
1876 }
1877 
1878 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1879  unsigned DestReg, bool IsZExt) {
1880  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1881  // DestVT are odd things, so test to make sure that they are both types we can
1882  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1883  // bail out to SelectionDAG.
1884  if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1885  ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1886  return false;
1887  if (IsZExt)
1888  return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1889  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1890 }
1891 
1892 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1893  bool isZExt) {
1894  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1895  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1896  return Success ? DestReg : 0;
1897 }
1898 
1899 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1900  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1901  if (!DestEVT.isSimple())
1902  return false;
1903 
1904  MVT DestVT = DestEVT.getSimpleVT();
1905  if (DestVT != MVT::i32)
1906  return false;
1907 
1908  unsigned DivOpc;
1909  switch (ISDOpcode) {
1910  default:
1911  return false;
1912  case ISD::SDIV:
1913  case ISD::SREM:
1914  DivOpc = Mips::SDIV;
1915  break;
1916  case ISD::UDIV:
1917  case ISD::UREM:
1918  DivOpc = Mips::UDIV;
1919  break;
1920  }
1921 
1922  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1923  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1924  if (!Src0Reg || !Src1Reg)
1925  return false;
1926 
1927  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1928  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1929 
1930  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1931  if (!ResultReg)
1932  return false;
1933 
1934  unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1935  ? Mips::MFHI
1936  : Mips::MFLO;
1937  emitInst(MFOpc, ResultReg);
1938 
1939  updateValueMap(I, ResultReg);
1940  return true;
1941 }
1942 
1943 bool MipsFastISel::selectShift(const Instruction *I) {
1944  MVT RetVT;
1945 
1946  if (!isTypeSupported(I->getType(), RetVT))
1947  return false;
1948 
1949  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1950  if (!ResultReg)
1951  return false;
1952 
1953  unsigned Opcode = I->getOpcode();
1954  const Value *Op0 = I->getOperand(0);
1955  unsigned Op0Reg = getRegForValue(Op0);
1956  if (!Op0Reg)
1957  return false;
1958 
1959  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1960  if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1961  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1962  if (!TempReg)
1963  return false;
1964 
1965  MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1966  bool IsZExt = Opcode == Instruction::LShr;
1967  if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1968  return false;
1969 
1970  Op0Reg = TempReg;
1971  }
1972 
1973  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1974  uint64_t ShiftVal = C->getZExtValue();
1975 
1976  switch (Opcode) {
1977  default:
1978  llvm_unreachable("Unexpected instruction.");
1979  case Instruction::Shl:
1980  Opcode = Mips::SLL;
1981  break;
1982  case Instruction::AShr:
1983  Opcode = Mips::SRA;
1984  break;
1985  case Instruction::LShr:
1986  Opcode = Mips::SRL;
1987  break;
1988  }
1989 
1990  emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1991  updateValueMap(I, ResultReg);
1992  return true;
1993  }
1994 
1995  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1996  if (!Op1Reg)
1997  return false;
1998 
1999  switch (Opcode) {
2000  default:
2001  llvm_unreachable("Unexpected instruction.");
2002  case Instruction::Shl:
2003  Opcode = Mips::SLLV;
2004  break;
2005  case Instruction::AShr:
2006  Opcode = Mips::SRAV;
2007  break;
2008  case Instruction::LShr:
2009  Opcode = Mips::SRLV;
2010  break;
2011  }
2012 
2013  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2014  updateValueMap(I, ResultReg);
2015  return true;
2016 }
2017 
2018 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2019  switch (I->getOpcode()) {
2020  default:
2021  break;
2022  case Instruction::Load:
2023  return selectLoad(I);
2024  case Instruction::Store:
2025  return selectStore(I);
2026  case Instruction::SDiv:
2027  if (!selectBinaryOp(I, ISD::SDIV))
2028  return selectDivRem(I, ISD::SDIV);
2029  return true;
2030  case Instruction::UDiv:
2031  if (!selectBinaryOp(I, ISD::UDIV))
2032  return selectDivRem(I, ISD::UDIV);
2033  return true;
2034  case Instruction::SRem:
2035  if (!selectBinaryOp(I, ISD::SREM))
2036  return selectDivRem(I, ISD::SREM);
2037  return true;
2038  case Instruction::URem:
2039  if (!selectBinaryOp(I, ISD::UREM))
2040  return selectDivRem(I, ISD::UREM);
2041  return true;
2042  case Instruction::Shl:
2043  case Instruction::LShr:
2044  case Instruction::AShr:
2045  return selectShift(I);
2046  case Instruction::And:
2047  case Instruction::Or:
2048  case Instruction::Xor:
2049  return selectLogicalOp(I);
2050  case Instruction::Br:
2051  return selectBranch(I);
2052  case Instruction::Ret:
2053  return selectRet(I);
2054  case Instruction::Trunc:
2055  return selectTrunc(I);
2056  case Instruction::ZExt:
2057  case Instruction::SExt:
2058  return selectIntExt(I);
2059  case Instruction::FPTrunc:
2060  return selectFPTrunc(I);
2061  case Instruction::FPExt:
2062  return selectFPExt(I);
2063  case Instruction::FPToSI:
2064  return selectFPToInt(I, /*isSigned*/ true);
2065  case Instruction::FPToUI:
2066  return selectFPToInt(I, /*isSigned*/ false);
2067  case Instruction::ICmp:
2068  case Instruction::FCmp:
2069  return selectCmp(I);
2070  case Instruction::Select:
2071  return selectSelect(I);
2072  }
2073  return false;
2074 }
2075 
2076 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2077  bool IsUnsigned) {
2078  unsigned VReg = getRegForValue(V);
2079  if (VReg == 0)
2080  return 0;
2081  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2082 
2083  if (VMVT == MVT::i1)
2084  return 0;
2085 
2086  if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2087  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2088  if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2089  return 0;
2090  VReg = TempReg;
2091  }
2092  return VReg;
2093 }
2094 
2095 void MipsFastISel::simplifyAddress(Address &Addr) {
2096  if (!isInt<16>(Addr.getOffset())) {
2097  unsigned TempReg =
2098  materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2099  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2100  emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2101  Addr.setReg(DestReg);
2102  Addr.setOffset(0);
2103  }
2104 }
2105 
2106 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2107  const TargetRegisterClass *RC,
2108  unsigned Op0, bool Op0IsKill,
2109  unsigned Op1, bool Op1IsKill) {
2110  // We treat the MUL instruction in a special way because it clobbers
2111  // the HI0 & LO0 registers. The TableGen definition of this instruction can
2112  // mark these registers only as implicitly defined. As a result, the
2113  // register allocator runs out of registers when this instruction is
2114  // followed by another instruction that defines the same registers too.
2115  // We can fix this by explicitly marking those registers as dead.
2116  if (MachineInstOpcode == Mips::MUL) {
2117  unsigned ResultReg = createResultReg(RC);
2118  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2119  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2120  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2121  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2122  .addReg(Op0, getKillRegState(Op0IsKill))
2123  .addReg(Op1, getKillRegState(Op1IsKill))
2126  return ResultReg;
2127  }
2128 
2129  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2130  Op1IsKill);
2131 }
2132 
2133 namespace llvm {
2134 
2136  const TargetLibraryInfo *libInfo) {
2137  return new MipsFastISel(funcInfo, libInfo);
2138 }
2139 
2140 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
uint64_t CallInst * C
Return a value (possibly void), from a function.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:636
bool hasLocalLinkage() const
Definition: GlobalValue.h:435
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isVector() const
Return true if this is a vector value type.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
const MipsInstrInfo * getInstrInfo() const override
const Value * getTrueValue() const
unsigned less or equal
Definition: InstrTypes.h:672
unsigned less than
Definition: InstrTypes.h:671
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:652
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:705
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:662
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
void reserve(size_type N)
Definition: SmallVector.h:368
Value * getLength() const
op_iterator op_begin()
Definition: User.h:229
bool isMemLoc() const
bool needsCustom() const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
SI optimize exec mask operations pre RA
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:531
A description of a memory reference used in the backend.
This class represents the LLVM &#39;select&#39; instruction.
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
Class to represent struct types.
Definition: DerivedTypes.h:232
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isUnsigned() const
Definition: InstrTypes.h:822
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:653
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:888
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:119
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Value * getOperand(unsigned i) const
Definition: User.h:169
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
TargetInstrInfo - Interface to description of machine instruction set.
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:146
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV)...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
op_iterator op_end()
Definition: User.h:231
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const Value * getCondition() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
Extended Value Type.
Definition: ValueTypes.h:33
size_t size() const
Definition: SmallVector.h:52
static bool isAtomic(Instruction *I)
bool isVolatile() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:673
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:50
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:650
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:37
unsigned getNumOperands() const
Definition: User.h:191
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
const DataFlowGraph & G
Definition: RDFGraph.cpp:210
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:675
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:2057
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
signed less or equal
Definition: InstrTypes.h:676
amdgpu Simplify well known AMD library false FunctionCallee Callee
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
This file defines the FastISel class.
const MipsTargetLowering * getTargetLowering() const override
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
const Value * getFalseValue() const
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:721
unsigned getNumArgOperands() const
Definition: InstrTypes.h:1153
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
cl::opt< bool > EmitJalrReloc
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:553
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:644
unsigned getLocMemOffset() const
unsigned greater or equal
Definition: InstrTypes.h:670
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1201
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
bool isRegLoc() const
const unsigned Kind
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:649
LLVM Value Representation.
Definition: Value.h:72
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned greater than
Definition: InstrTypes.h:669
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
APInt bitcastToAPInt() const
Definition: APFloat.h:1093
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:156
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
#define LLVM_DEBUG(X)
Definition: Debug.h:122
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:651
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:149
bool isFP64bit() const
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void convertToReg(unsigned RegNo)
iterator_range< arg_iterator > args()
Definition: Function.h:688
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:217
signed greater or equal
Definition: InstrTypes.h:674
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:220
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
an instruction to allocate memory on the stack
Definition: Instructions.h:59
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:94
gep_type_iterator gep_type_begin(const User *GEP)