LLVM  7.0.0svn
MipsFastISel.cpp
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1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
14 ///
15 //===----------------------------------------------------------------------===//
16 
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/FastISel.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/CallingConv.h"
44 #include "llvm/IR/Constant.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DataLayout.h"
47 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalValue.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/InstrTypes.h"
52 #include "llvm/IR/Instruction.h"
53 #include "llvm/IR/Instructions.h"
54 #include "llvm/IR/IntrinsicInst.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/IR/Type.h"
57 #include "llvm/IR/User.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCInstrDesc.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/MC/MCSymbol.h"
62 #include "llvm/Support/Casting.h"
63 #include "llvm/Support/Compiler.h"
64 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <array>
71 #include <cassert>
72 #include <cstdint>
73 
74 #define DEBUG_TYPE "mips-fastisel"
75 
76 using namespace llvm;
77 
78 namespace {
79 
80 class MipsFastISel final : public FastISel {
81 
82  // All possible address modes.
83  class Address {
84  public:
85  using BaseKind = enum { RegBase, FrameIndexBase };
86 
87  private:
88  BaseKind Kind = RegBase;
89  union {
90  unsigned Reg;
91  int FI;
92  } Base;
93 
94  int64_t Offset = 0;
95 
96  const GlobalValue *GV = nullptr;
97 
98  public:
99  // Innocuous defaults for our address.
100  Address() { Base.Reg = 0; }
101 
102  void setKind(BaseKind K) { Kind = K; }
103  BaseKind getKind() const { return Kind; }
104  bool isRegBase() const { return Kind == RegBase; }
105  bool isFIBase() const { return Kind == FrameIndexBase; }
106 
107  void setReg(unsigned Reg) {
108  assert(isRegBase() && "Invalid base register access!");
109  Base.Reg = Reg;
110  }
111 
112  unsigned getReg() const {
113  assert(isRegBase() && "Invalid base register access!");
114  return Base.Reg;
115  }
116 
117  void setFI(unsigned FI) {
118  assert(isFIBase() && "Invalid base frame index access!");
119  Base.FI = FI;
120  }
121 
122  unsigned getFI() const {
123  assert(isFIBase() && "Invalid base frame index access!");
124  return Base.FI;
125  }
126 
127  void setOffset(int64_t Offset_) { Offset = Offset_; }
128  int64_t getOffset() const { return Offset; }
129  void setGlobalValue(const GlobalValue *G) { GV = G; }
130  const GlobalValue *getGlobalValue() { return GV; }
131  };
132 
133  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
134  /// make the right decision when generating code for different targets.
135  const TargetMachine &TM;
136  const MipsSubtarget *Subtarget;
137  const TargetInstrInfo &TII;
138  const TargetLowering &TLI;
139  MipsFunctionInfo *MFI;
140 
141  // Convenience variables to avoid some queries.
143 
144  bool fastLowerArguments() override;
145  bool fastLowerCall(CallLoweringInfo &CLI) override;
146  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
147 
148  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
149  // floating point but not reject doing fast-isel in other
150  // situations
151 
152 private:
153  // Selection routines.
154  bool selectLogicalOp(const Instruction *I);
155  bool selectLoad(const Instruction *I);
156  bool selectStore(const Instruction *I);
157  bool selectBranch(const Instruction *I);
158  bool selectSelect(const Instruction *I);
159  bool selectCmp(const Instruction *I);
160  bool selectFPExt(const Instruction *I);
161  bool selectFPTrunc(const Instruction *I);
162  bool selectFPToInt(const Instruction *I, bool IsSigned);
163  bool selectRet(const Instruction *I);
164  bool selectTrunc(const Instruction *I);
165  bool selectIntExt(const Instruction *I);
166  bool selectShift(const Instruction *I);
167  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
168 
169  // Utility helper routines.
170  bool isTypeLegal(Type *Ty, MVT &VT);
171  bool isTypeSupported(Type *Ty, MVT &VT);
172  bool isLoadTypeLegal(Type *Ty, MVT &VT);
173  bool computeAddress(const Value *Obj, Address &Addr);
174  bool computeCallAddress(const Value *V, Address &Addr);
175  void simplifyAddress(Address &Addr);
176 
177  // Emit helper routines.
178  bool emitCmp(unsigned DestReg, const CmpInst *CI);
179  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
180  unsigned Alignment = 0);
181  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
182  MachineMemOperand *MMO = nullptr);
183  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
184  unsigned Alignment = 0);
185  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
186  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 
188  bool IsZExt);
189  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 
191  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
192  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
193  unsigned DestReg);
194  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
195  unsigned DestReg);
196 
197  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
198 
199  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
200  const Value *RHS);
201 
202  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
203  unsigned materializeGV(const GlobalValue *GV, MVT VT);
204  unsigned materializeInt(const Constant *C, MVT VT);
205  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
206  unsigned materializeExternalCallSym(MCSymbol *Syn);
207 
208  MachineInstrBuilder emitInst(unsigned Opc) {
209  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
210  }
211 
212  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
213  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
214  DstReg);
215  }
216 
217  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
218  unsigned MemReg, int64_t MemOffset) {
219  return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
220  }
221 
222  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
223  unsigned MemReg, int64_t MemOffset) {
224  return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
225  }
226 
227  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
228  const TargetRegisterClass *RC,
229  unsigned Op0, bool Op0IsKill,
230  unsigned Op1, bool Op1IsKill);
231 
232  // for some reason, this default is not generated by tablegen
233  // so we explicitly generate it here.
234  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
235  unsigned Op0, bool Op0IsKill, uint64_t imm1,
236  uint64_t imm2, unsigned Op3, bool Op3IsKill) {
237  return 0;
238  }
239 
240  // Call handling routines.
241 private:
242  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
243  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
244  unsigned &NumBytes);
245  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
246 
247  const MipsABIInfo &getABI() const {
248  return static_cast<const MipsTargetMachine &>(TM).getABI();
249  }
250 
251 public:
252  // Backend specific FastISel code.
253  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
254  const TargetLibraryInfo *libInfo)
255  : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
256  Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
257  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
258  MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
259  Context = &funcInfo.Fn->getContext();
260  UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
261  }
262 
263  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
264  unsigned fastMaterializeConstant(const Constant *C) override;
265  bool fastSelectInstruction(const Instruction *I) override;
266 
267 #include "MipsGenFastISel.inc"
268 };
269 
270 } // end anonymous namespace
271 
272 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
273  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
275 
276 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
277  CCValAssign::LocInfo LocInfo,
278  ISD::ArgFlagsTy ArgFlags, CCState &State) {
279  llvm_unreachable("should not be called");
280 }
281 
282 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
283  CCValAssign::LocInfo LocInfo,
284  ISD::ArgFlagsTy ArgFlags, CCState &State) {
285  llvm_unreachable("should not be called");
286 }
287 
288 #include "MipsGenCallingConv.inc"
289 
290 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
291  return CC_MipsO32;
292 }
293 
294 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
295  const Value *LHS, const Value *RHS) {
296  // Canonicalize immediates to the RHS first.
297  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
298  std::swap(LHS, RHS);
299 
300  unsigned Opc;
301  switch (ISDOpc) {
302  case ISD::AND:
303  Opc = Mips::AND;
304  break;
305  case ISD::OR:
306  Opc = Mips::OR;
307  break;
308  case ISD::XOR:
309  Opc = Mips::XOR;
310  break;
311  default:
312  llvm_unreachable("unexpected opcode");
313  }
314 
315  unsigned LHSReg = getRegForValue(LHS);
316  if (!LHSReg)
317  return 0;
318 
319  unsigned RHSReg;
320  if (const auto *C = dyn_cast<ConstantInt>(RHS))
321  RHSReg = materializeInt(C, MVT::i32);
322  else
323  RHSReg = getRegForValue(RHS);
324  if (!RHSReg)
325  return 0;
326 
327  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
328  if (!ResultReg)
329  return 0;
330 
331  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
332  return ResultReg;
333 }
334 
335 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
336  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
337  "Alloca should always return a pointer.");
338 
340  FuncInfo.StaticAllocaMap.find(AI);
341 
342  if (SI != FuncInfo.StaticAllocaMap.end()) {
343  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
344  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
345  ResultReg)
346  .addFrameIndex(SI->second)
347  .addImm(0);
348  return ResultReg;
349  }
350 
351  return 0;
352 }
353 
354 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
355  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
356  return 0;
357  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
358  const ConstantInt *CI = cast<ConstantInt>(C);
359  return materialize32BitInt(CI->getZExtValue(), RC);
360 }
361 
362 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
363  const TargetRegisterClass *RC) {
364  unsigned ResultReg = createResultReg(RC);
365 
366  if (isInt<16>(Imm)) {
367  unsigned Opc = Mips::ADDiu;
368  emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
369  return ResultReg;
370  } else if (isUInt<16>(Imm)) {
371  emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
372  return ResultReg;
373  }
374  unsigned Lo = Imm & 0xFFFF;
375  unsigned Hi = (Imm >> 16) & 0xFFFF;
376  if (Lo) {
377  // Both Lo and Hi have nonzero bits.
378  unsigned TmpReg = createResultReg(RC);
379  emitInst(Mips::LUi, TmpReg).addImm(Hi);
380  emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
381  } else {
382  emitInst(Mips::LUi, ResultReg).addImm(Hi);
383  }
384  return ResultReg;
385 }
386 
387 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
388  if (UnsupportedFPMode)
389  return 0;
390  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
391  if (VT == MVT::f32) {
392  const TargetRegisterClass *RC = &Mips::FGR32RegClass;
393  unsigned DestReg = createResultReg(RC);
394  unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
395  emitInst(Mips::MTC1, DestReg).addReg(TempReg);
396  return DestReg;
397  } else if (VT == MVT::f64) {
398  const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
399  unsigned DestReg = createResultReg(RC);
400  unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
401  unsigned TempReg2 =
402  materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
403  emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
404  return DestReg;
405  }
406  return 0;
407 }
408 
409 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
410  // For now 32-bit only.
411  if (VT != MVT::i32)
412  return 0;
413  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
414  unsigned DestReg = createResultReg(RC);
415  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
416  bool IsThreadLocal = GVar && GVar->isThreadLocal();
417  // TLS not supported at this time.
418  if (IsThreadLocal)
419  return 0;
420  emitInst(Mips::LW, DestReg)
421  .addReg(MFI->getGlobalBaseReg())
422  .addGlobalAddress(GV, 0, MipsII::MO_GOT);
423  if ((GV->hasInternalLinkage() ||
424  (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
425  unsigned TempReg = createResultReg(RC);
426  emitInst(Mips::ADDiu, TempReg)
427  .addReg(DestReg)
428  .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
429  DestReg = TempReg;
430  }
431  return DestReg;
432 }
433 
434 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
435  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
436  unsigned DestReg = createResultReg(RC);
437  emitInst(Mips::LW, DestReg)
438  .addReg(MFI->getGlobalBaseReg())
439  .addSym(Sym, MipsII::MO_GOT);
440  return DestReg;
441 }
442 
443 // Materialize a constant into a register, and return the register
444 // number (or zero if we failed to handle it).
445 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
446  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
447 
448  // Only handle simple types.
449  if (!CEVT.isSimple())
450  return 0;
451  MVT VT = CEVT.getSimpleVT();
452 
453  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
454  return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
455  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
456  return materializeGV(GV, VT);
457  else if (isa<ConstantInt>(C))
458  return materializeInt(C, VT);
459 
460  return 0;
461 }
462 
463 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
464  const User *U = nullptr;
465  unsigned Opcode = Instruction::UserOp1;
466  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
467  // Don't walk into other basic blocks unless the object is an alloca from
468  // another block, otherwise it may not have a virtual register assigned.
469  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
470  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
471  Opcode = I->getOpcode();
472  U = I;
473  }
474  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
475  Opcode = C->getOpcode();
476  U = C;
477  }
478  switch (Opcode) {
479  default:
480  break;
481  case Instruction::BitCast:
482  // Look through bitcasts.
483  return computeAddress(U->getOperand(0), Addr);
484  case Instruction::GetElementPtr: {
485  Address SavedAddr = Addr;
486  int64_t TmpOffset = Addr.getOffset();
487  // Iterate through the GEP folding the constants into offsets where
488  // we can.
490  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
491  ++i, ++GTI) {
492  const Value *Op = *i;
493  if (StructType *STy = GTI.getStructTypeOrNull()) {
494  const StructLayout *SL = DL.getStructLayout(STy);
495  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
496  TmpOffset += SL->getElementOffset(Idx);
497  } else {
498  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
499  while (true) {
500  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
501  // Constant-offset addressing.
502  TmpOffset += CI->getSExtValue() * S;
503  break;
504  }
505  if (canFoldAddIntoGEP(U, Op)) {
506  // A compatible add with a constant operand. Fold the constant.
507  ConstantInt *CI =
508  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
509  TmpOffset += CI->getSExtValue() * S;
510  // Iterate on the other operand.
511  Op = cast<AddOperator>(Op)->getOperand(0);
512  continue;
513  }
514  // Unsupported
515  goto unsupported_gep;
516  }
517  }
518  }
519  // Try to grab the base operand now.
520  Addr.setOffset(TmpOffset);
521  if (computeAddress(U->getOperand(0), Addr))
522  return true;
523  // We failed, restore everything and try the other options.
524  Addr = SavedAddr;
525  unsupported_gep:
526  break;
527  }
528  case Instruction::Alloca: {
529  const AllocaInst *AI = cast<AllocaInst>(Obj);
531  FuncInfo.StaticAllocaMap.find(AI);
532  if (SI != FuncInfo.StaticAllocaMap.end()) {
533  Addr.setKind(Address::FrameIndexBase);
534  Addr.setFI(SI->second);
535  return true;
536  }
537  break;
538  }
539  }
540  Addr.setReg(getRegForValue(Obj));
541  return Addr.getReg() != 0;
542 }
543 
544 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
545  const User *U = nullptr;
546  unsigned Opcode = Instruction::UserOp1;
547 
548  if (const auto *I = dyn_cast<Instruction>(V)) {
549  // Check if the value is defined in the same basic block. This information
550  // is crucial to know whether or not folding an operand is valid.
551  if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
552  Opcode = I->getOpcode();
553  U = I;
554  }
555  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
556  Opcode = C->getOpcode();
557  U = C;
558  }
559 
560  switch (Opcode) {
561  default:
562  break;
563  case Instruction::BitCast:
564  // Look past bitcasts if its operand is in the same BB.
565  return computeCallAddress(U->getOperand(0), Addr);
566  break;
567  case Instruction::IntToPtr:
568  // Look past no-op inttoptrs if its operand is in the same BB.
569  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
570  TLI.getPointerTy(DL))
571  return computeCallAddress(U->getOperand(0), Addr);
572  break;
573  case Instruction::PtrToInt:
574  // Look past no-op ptrtoints if its operand is in the same BB.
575  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
576  return computeCallAddress(U->getOperand(0), Addr);
577  break;
578  }
579 
580  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
581  Addr.setGlobalValue(GV);
582  return true;
583  }
584 
585  // If all else fails, try to materialize the value in a register.
586  if (!Addr.getGlobalValue()) {
587  Addr.setReg(getRegForValue(V));
588  return Addr.getReg() != 0;
589  }
590 
591  return false;
592 }
593 
594 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
595  EVT evt = TLI.getValueType(DL, Ty, true);
596  // Only handle simple types.
597  if (evt == MVT::Other || !evt.isSimple())
598  return false;
599  VT = evt.getSimpleVT();
600 
601  // Handle all legal types, i.e. a register that will directly hold this
602  // value.
603  return TLI.isTypeLegal(VT);
604 }
605 
606 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
607  if (Ty->isVectorTy())
608  return false;
609 
610  if (isTypeLegal(Ty, VT))
611  return true;
612 
613  // If this is a type than can be sign or zero-extended to a basic operation
614  // go ahead and accept it now.
615  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
616  return true;
617 
618  return false;
619 }
620 
621 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
622  if (isTypeLegal(Ty, VT))
623  return true;
624  // We will extend this in a later patch:
625  // If this is a type than can be sign or zero-extended to a basic operation
626  // go ahead and accept it now.
627  if (VT == MVT::i8 || VT == MVT::i16)
628  return true;
629  return false;
630 }
631 
632 // Because of how EmitCmp is called with fast-isel, you can
633 // end up with redundant "andi" instructions after the sequences emitted below.
634 // We should try and solve this issue in the future.
635 //
636 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
637  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
638  bool IsUnsigned = CI->isUnsigned();
639  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
640  if (LeftReg == 0)
641  return false;
642  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
643  if (RightReg == 0)
644  return false;
646 
647  switch (P) {
648  default:
649  return false;
650  case CmpInst::ICMP_EQ: {
651  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
652  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
653  emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
654  break;
655  }
656  case CmpInst::ICMP_NE: {
657  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
658  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
659  emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
660  break;
661  }
662  case CmpInst::ICMP_UGT:
663  emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
664  break;
665  case CmpInst::ICMP_ULT:
666  emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
667  break;
668  case CmpInst::ICMP_UGE: {
669  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
670  emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
671  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
672  break;
673  }
674  case CmpInst::ICMP_ULE: {
675  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
676  emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
677  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
678  break;
679  }
680  case CmpInst::ICMP_SGT:
681  emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
682  break;
683  case CmpInst::ICMP_SLT:
684  emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
685  break;
686  case CmpInst::ICMP_SGE: {
687  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
688  emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
689  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
690  break;
691  }
692  case CmpInst::ICMP_SLE: {
693  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
694  emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
695  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
696  break;
697  }
698  case CmpInst::FCMP_OEQ:
699  case CmpInst::FCMP_UNE:
700  case CmpInst::FCMP_OLT:
701  case CmpInst::FCMP_OLE:
702  case CmpInst::FCMP_OGT:
703  case CmpInst::FCMP_OGE: {
704  if (UnsupportedFPMode)
705  return false;
706  bool IsFloat = Left->getType()->isFloatTy();
707  bool IsDouble = Left->getType()->isDoubleTy();
708  if (!IsFloat && !IsDouble)
709  return false;
710  unsigned Opc, CondMovOpc;
711  switch (P) {
712  case CmpInst::FCMP_OEQ:
713  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
714  CondMovOpc = Mips::MOVT_I;
715  break;
716  case CmpInst::FCMP_UNE:
717  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
718  CondMovOpc = Mips::MOVF_I;
719  break;
720  case CmpInst::FCMP_OLT:
721  Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
722  CondMovOpc = Mips::MOVT_I;
723  break;
724  case CmpInst::FCMP_OLE:
725  Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
726  CondMovOpc = Mips::MOVT_I;
727  break;
728  case CmpInst::FCMP_OGT:
729  Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
730  CondMovOpc = Mips::MOVF_I;
731  break;
732  case CmpInst::FCMP_OGE:
733  Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
734  CondMovOpc = Mips::MOVF_I;
735  break;
736  default:
737  llvm_unreachable("Only switching of a subset of CCs.");
738  }
739  unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
740  unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
741  emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
742  emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
743  emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
744  .addReg(RightReg);
745  emitInst(CondMovOpc, ResultReg)
746  .addReg(RegWithOne)
747  .addReg(Mips::FCC0)
748  .addReg(RegWithZero);
749  break;
750  }
751  }
752  return true;
753 }
754 
755 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
756  unsigned Alignment) {
757  //
758  // more cases will be handled here in following patches.
759  //
760  unsigned Opc;
761  switch (VT.SimpleTy) {
762  case MVT::i32:
763  ResultReg = createResultReg(&Mips::GPR32RegClass);
764  Opc = Mips::LW;
765  break;
766  case MVT::i16:
767  ResultReg = createResultReg(&Mips::GPR32RegClass);
768  Opc = Mips::LHu;
769  break;
770  case MVT::i8:
771  ResultReg = createResultReg(&Mips::GPR32RegClass);
772  Opc = Mips::LBu;
773  break;
774  case MVT::f32:
775  if (UnsupportedFPMode)
776  return false;
777  ResultReg = createResultReg(&Mips::FGR32RegClass);
778  Opc = Mips::LWC1;
779  break;
780  case MVT::f64:
781  if (UnsupportedFPMode)
782  return false;
783  ResultReg = createResultReg(&Mips::AFGR64RegClass);
784  Opc = Mips::LDC1;
785  break;
786  default:
787  return false;
788  }
789  if (Addr.isRegBase()) {
790  simplifyAddress(Addr);
791  emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
792  return true;
793  }
794  if (Addr.isFIBase()) {
795  unsigned FI = Addr.getFI();
796  unsigned Align = 4;
797  int64_t Offset = Addr.getOffset();
798  MachineFrameInfo &MFI = MF->getFrameInfo();
799  MachineMemOperand *MMO = MF->getMachineMemOperand(
801  MFI.getObjectSize(FI), Align);
802  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
803  .addFrameIndex(FI)
804  .addImm(Offset)
805  .addMemOperand(MMO);
806  return true;
807  }
808  return false;
809 }
810 
811 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
812  unsigned Alignment) {
813  //
814  // more cases will be handled here in following patches.
815  //
816  unsigned Opc;
817  switch (VT.SimpleTy) {
818  case MVT::i8:
819  Opc = Mips::SB;
820  break;
821  case MVT::i16:
822  Opc = Mips::SH;
823  break;
824  case MVT::i32:
825  Opc = Mips::SW;
826  break;
827  case MVT::f32:
828  if (UnsupportedFPMode)
829  return false;
830  Opc = Mips::SWC1;
831  break;
832  case MVT::f64:
833  if (UnsupportedFPMode)
834  return false;
835  Opc = Mips::SDC1;
836  break;
837  default:
838  return false;
839  }
840  if (Addr.isRegBase()) {
841  simplifyAddress(Addr);
842  emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
843  return true;
844  }
845  if (Addr.isFIBase()) {
846  unsigned FI = Addr.getFI();
847  unsigned Align = 4;
848  int64_t Offset = Addr.getOffset();
849  MachineFrameInfo &MFI = MF->getFrameInfo();
850  MachineMemOperand *MMO = MF->getMachineMemOperand(
852  MFI.getObjectSize(FI), Align);
853  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
854  .addReg(SrcReg)
855  .addFrameIndex(FI)
856  .addImm(Offset)
857  .addMemOperand(MMO);
858  return true;
859  }
860  return false;
861 }
862 
863 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
864  MVT VT;
865  if (!isTypeSupported(I->getType(), VT))
866  return false;
867 
868  unsigned ResultReg;
869  switch (I->getOpcode()) {
870  default:
871  llvm_unreachable("Unexpected instruction.");
872  case Instruction::And:
873  ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
874  break;
875  case Instruction::Or:
876  ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
877  break;
878  case Instruction::Xor:
879  ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
880  break;
881  }
882 
883  if (!ResultReg)
884  return false;
885 
886  updateValueMap(I, ResultReg);
887  return true;
888 }
889 
890 bool MipsFastISel::selectLoad(const Instruction *I) {
891  // Atomic loads need special handling.
892  if (cast<LoadInst>(I)->isAtomic())
893  return false;
894 
895  // Verify we have a legal type before going any further.
896  MVT VT;
897  if (!isLoadTypeLegal(I->getType(), VT))
898  return false;
899 
900  // See if we can handle this address.
901  Address Addr;
902  if (!computeAddress(I->getOperand(0), Addr))
903  return false;
904 
905  unsigned ResultReg;
906  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
907  return false;
908  updateValueMap(I, ResultReg);
909  return true;
910 }
911 
912 bool MipsFastISel::selectStore(const Instruction *I) {
913  Value *Op0 = I->getOperand(0);
914  unsigned SrcReg = 0;
915 
916  // Atomic stores need special handling.
917  if (cast<StoreInst>(I)->isAtomic())
918  return false;
919 
920  // Verify we have a legal type before going any further.
921  MVT VT;
922  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
923  return false;
924 
925  // Get the value to be stored into a register.
926  SrcReg = getRegForValue(Op0);
927  if (SrcReg == 0)
928  return false;
929 
930  // See if we can handle this address.
931  Address Addr;
932  if (!computeAddress(I->getOperand(1), Addr))
933  return false;
934 
935  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
936  return false;
937  return true;
938 }
939 
940 // This can cause a redundant sltiu to be generated.
941 // FIXME: try and eliminate this in a future patch.
942 bool MipsFastISel::selectBranch(const Instruction *I) {
943  const BranchInst *BI = cast<BranchInst>(I);
944  MachineBasicBlock *BrBB = FuncInfo.MBB;
945  //
946  // TBB is the basic block for the case where the comparison is true.
947  // FBB is the basic block for the case where the comparison is false.
948  // if (cond) goto TBB
949  // goto FBB
950  // TBB:
951  //
952  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
953  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
954  // For now, just try the simplest case where it's fed by a compare.
955  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
956  unsigned CondReg = getRegForValue(CI);
957  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
958  .addReg(CondReg)
959  .addMBB(TBB);
960  finishCondBranch(BI->getParent(), TBB, FBB);
961  return true;
962  }
963  return false;
964 }
965 
966 bool MipsFastISel::selectCmp(const Instruction *I) {
967  const CmpInst *CI = cast<CmpInst>(I);
968  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
969  if (!emitCmp(ResultReg, CI))
970  return false;
971  updateValueMap(I, ResultReg);
972  return true;
973 }
974 
975 // Attempt to fast-select a floating-point extend instruction.
976 bool MipsFastISel::selectFPExt(const Instruction *I) {
977  if (UnsupportedFPMode)
978  return false;
979  Value *Src = I->getOperand(0);
980  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
981  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
982 
983  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
984  return false;
985 
986  unsigned SrcReg =
987  getRegForValue(Src); // this must be a 32bit floating point register class
988  // maybe we should handle this differently
989  if (!SrcReg)
990  return false;
991 
992  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
993  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
994  updateValueMap(I, DestReg);
995  return true;
996 }
997 
998 bool MipsFastISel::selectSelect(const Instruction *I) {
999  assert(isa<SelectInst>(I) && "Expected a select instruction.");
1000 
1001  LLVM_DEBUG(dbgs() << "selectSelect\n");
1002 
1003  MVT VT;
1004  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1005  LLVM_DEBUG(
1006  dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1007  return false;
1008  }
1009 
1010  unsigned CondMovOpc;
1011  const TargetRegisterClass *RC;
1012 
1013  if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1014  CondMovOpc = Mips::MOVN_I_I;
1015  RC = &Mips::GPR32RegClass;
1016  } else if (VT == MVT::f32) {
1017  CondMovOpc = Mips::MOVN_I_S;
1018  RC = &Mips::FGR32RegClass;
1019  } else if (VT == MVT::f64) {
1020  CondMovOpc = Mips::MOVN_I_D32;
1021  RC = &Mips::AFGR64RegClass;
1022  } else
1023  return false;
1024 
1025  const SelectInst *SI = cast<SelectInst>(I);
1026  const Value *Cond = SI->getCondition();
1027  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1028  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1029  unsigned CondReg = getRegForValue(Cond);
1030 
1031  if (!Src1Reg || !Src2Reg || !CondReg)
1032  return false;
1033 
1034  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1035  if (!ZExtCondReg)
1036  return false;
1037 
1038  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1039  return false;
1040 
1041  unsigned ResultReg = createResultReg(RC);
1042  unsigned TempReg = createResultReg(RC);
1043 
1044  if (!ResultReg || !TempReg)
1045  return false;
1046 
1047  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1048  emitInst(CondMovOpc, ResultReg)
1049  .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1050  updateValueMap(I, ResultReg);
1051  return true;
1052 }
1053 
1054 // Attempt to fast-select a floating-point truncate instruction.
1055 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1056  if (UnsupportedFPMode)
1057  return false;
1058  Value *Src = I->getOperand(0);
1059  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1060  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1061 
1062  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1063  return false;
1064 
1065  unsigned SrcReg = getRegForValue(Src);
1066  if (!SrcReg)
1067  return false;
1068 
1069  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1070  if (!DestReg)
1071  return false;
1072 
1073  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1074  updateValueMap(I, DestReg);
1075  return true;
1076 }
1077 
1078 // Attempt to fast-select a floating-point-to-integer conversion.
1079 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1080  if (UnsupportedFPMode)
1081  return false;
1082  MVT DstVT, SrcVT;
1083  if (!IsSigned)
1084  return false; // We don't handle this case yet. There is no native
1085  // instruction for this but it can be synthesized.
1086  Type *DstTy = I->getType();
1087  if (!isTypeLegal(DstTy, DstVT))
1088  return false;
1089 
1090  if (DstVT != MVT::i32)
1091  return false;
1092 
1093  Value *Src = I->getOperand(0);
1094  Type *SrcTy = Src->getType();
1095  if (!isTypeLegal(SrcTy, SrcVT))
1096  return false;
1097 
1098  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1099  return false;
1100 
1101  unsigned SrcReg = getRegForValue(Src);
1102  if (SrcReg == 0)
1103  return false;
1104 
1105  // Determine the opcode for the conversion, which takes place
1106  // entirely within FPRs.
1107  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1108  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1109  unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1110 
1111  // Generate the convert.
1112  emitInst(Opc, TempReg).addReg(SrcReg);
1113  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1114 
1115  updateValueMap(I, DestReg);
1116  return true;
1117 }
1118 
1119 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1120  SmallVectorImpl<MVT> &OutVTs,
1121  unsigned &NumBytes) {
1122  CallingConv::ID CC = CLI.CallConv;
1124  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1125  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1126  // Get a count of how many bytes are to be pushed on the stack.
1127  NumBytes = CCInfo.getNextStackOffset();
1128  // This is the minimum argument area used for A0-A3.
1129  if (NumBytes < 16)
1130  NumBytes = 16;
1131 
1132  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1133  // Process the args.
1134  MVT firstMVT;
1135  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1136  CCValAssign &VA = ArgLocs[i];
1137  const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1138  MVT ArgVT = OutVTs[VA.getValNo()];
1139 
1140  if (i == 0) {
1141  firstMVT = ArgVT;
1142  if (ArgVT == MVT::f32) {
1143  VA.convertToReg(Mips::F12);
1144  } else if (ArgVT == MVT::f64) {
1145  VA.convertToReg(Mips::D6);
1146  }
1147  } else if (i == 1) {
1148  if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1149  if (ArgVT == MVT::f32) {
1150  VA.convertToReg(Mips::F14);
1151  } else if (ArgVT == MVT::f64) {
1152  VA.convertToReg(Mips::D7);
1153  }
1154  }
1155  }
1156  if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1157  (ArgVT == MVT::i8)) &&
1158  VA.isMemLoc()) {
1159  switch (VA.getLocMemOffset()) {
1160  case 0:
1161  VA.convertToReg(Mips::A0);
1162  break;
1163  case 4:
1164  VA.convertToReg(Mips::A1);
1165  break;
1166  case 8:
1167  VA.convertToReg(Mips::A2);
1168  break;
1169  case 12:
1170  VA.convertToReg(Mips::A3);
1171  break;
1172  default:
1173  break;
1174  }
1175  }
1176  unsigned ArgReg = getRegForValue(ArgVal);
1177  if (!ArgReg)
1178  return false;
1179 
1180  // Handle arg promotion: SExt, ZExt, AExt.
1181  switch (VA.getLocInfo()) {
1182  case CCValAssign::Full:
1183  break;
1184  case CCValAssign::AExt:
1185  case CCValAssign::SExt: {
1186  MVT DestVT = VA.getLocVT();
1187  MVT SrcVT = ArgVT;
1188  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1189  if (!ArgReg)
1190  return false;
1191  break;
1192  }
1193  case CCValAssign::ZExt: {
1194  MVT DestVT = VA.getLocVT();
1195  MVT SrcVT = ArgVT;
1196  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1197  if (!ArgReg)
1198  return false;
1199  break;
1200  }
1201  default:
1202  llvm_unreachable("Unknown arg promotion!");
1203  }
1204 
1205  // Now copy/store arg to correct locations.
1206  if (VA.isRegLoc() && !VA.needsCustom()) {
1207  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1208  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1209  CLI.OutRegs.push_back(VA.getLocReg());
1210  } else if (VA.needsCustom()) {
1211  llvm_unreachable("Mips does not use custom args.");
1212  return false;
1213  } else {
1214  //
1215  // FIXME: This path will currently return false. It was copied
1216  // from the AArch64 port and should be essentially fine for Mips too.
1217  // The work to finish up this path will be done in a follow-on patch.
1218  //
1219  assert(VA.isMemLoc() && "Assuming store on stack.");
1220  // Don't emit stores for undef values.
1221  if (isa<UndefValue>(ArgVal))
1222  continue;
1223 
1224  // Need to store on the stack.
1225  // FIXME: This alignment is incorrect but this path is disabled
1226  // for now (will return false). We need to determine the right alignment
1227  // based on the normal alignment for the underlying machine type.
1228  //
1229  unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1230 
1231  unsigned BEAlign = 0;
1232  if (ArgSize < 8 && !Subtarget->isLittle())
1233  BEAlign = 8 - ArgSize;
1234 
1235  Address Addr;
1236  Addr.setKind(Address::RegBase);
1237  Addr.setReg(Mips::SP);
1238  Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1239 
1240  unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1241  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1242  MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1243  MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1244  (void)(MMO);
1245  // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1246  return false; // can't store on the stack yet.
1247  }
1248  }
1249 
1250  return true;
1251 }
1252 
1253 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1254  unsigned NumBytes) {
1255  CallingConv::ID CC = CLI.CallConv;
1256  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1257  if (RetVT != MVT::isVoid) {
1259  MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1260 
1261  CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1262  CLI.Symbol ? CLI.Symbol->getName().data()
1263  : nullptr);
1264 
1265  // Only handle a single return value.
1266  if (RVLocs.size() != 1)
1267  return false;
1268  // Copy all of the result registers out of their specified physreg.
1269  MVT CopyVT = RVLocs[0].getValVT();
1270  // Special handling for extended integers.
1271  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1272  CopyVT = MVT::i32;
1273 
1274  unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1275  if (!ResultReg)
1276  return false;
1277  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1278  TII.get(TargetOpcode::COPY),
1279  ResultReg).addReg(RVLocs[0].getLocReg());
1280  CLI.InRegs.push_back(RVLocs[0].getLocReg());
1281 
1282  CLI.ResultReg = ResultReg;
1283  CLI.NumResultRegs = 1;
1284  }
1285  return true;
1286 }
1287 
1288 bool MipsFastISel::fastLowerArguments() {
1289  LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1290 
1291  if (!FuncInfo.CanLowerReturn) {
1292  LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1293  return false;
1294  }
1295 
1296  const Function *F = FuncInfo.Fn;
1297  if (F->isVarArg()) {
1298  LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1299  return false;
1300  }
1301 
1302  CallingConv::ID CC = F->getCallingConv();
1303  if (CC != CallingConv::C) {
1304  LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1305  return false;
1306  }
1307 
1308  std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1309  Mips::A3}};
1310  std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1311  std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1312  auto NextGPR32 = GPR32ArgRegs.begin();
1313  auto NextFGR32 = FGR32ArgRegs.begin();
1314  auto NextAFGR64 = AFGR64ArgRegs.begin();
1315 
1316  struct AllocatedReg {
1317  const TargetRegisterClass *RC;
1318  unsigned Reg;
1319  AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1320  : RC(RC), Reg(Reg) {}
1321  };
1322 
1323  // Only handle simple cases. i.e. All arguments are directly mapped to
1324  // registers of the appropriate type.
1325  SmallVector<AllocatedReg, 4> Allocation;
1326  for (const auto &FormalArg : F->args()) {
1327  if (FormalArg.hasAttribute(Attribute::InReg) ||
1328  FormalArg.hasAttribute(Attribute::StructRet) ||
1329  FormalArg.hasAttribute(Attribute::ByVal)) {
1330  LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1331  return false;
1332  }
1333 
1334  Type *ArgTy = FormalArg.getType();
1335  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1336  LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1337  return false;
1338  }
1339 
1340  EVT ArgVT = TLI.getValueType(DL, ArgTy);
1341  LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1342  << ArgVT.getEVTString() << "\n");
1343  if (!ArgVT.isSimple()) {
1344  LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1345  return false;
1346  }
1347 
1348  switch (ArgVT.getSimpleVT().SimpleTy) {
1349  case MVT::i1:
1350  case MVT::i8:
1351  case MVT::i16:
1352  if (!FormalArg.hasAttribute(Attribute::SExt) &&
1353  !FormalArg.hasAttribute(Attribute::ZExt)) {
1354  // It must be any extend, this shouldn't happen for clang-generated IR
1355  // so just fall back on SelectionDAG.
1356  LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1357  return false;
1358  }
1359 
1360  if (NextGPR32 == GPR32ArgRegs.end()) {
1361  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1362  return false;
1363  }
1364 
1365  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1366  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1367 
1368  // Allocating any GPR32 prohibits further use of floating point arguments.
1369  NextFGR32 = FGR32ArgRegs.end();
1370  NextAFGR64 = AFGR64ArgRegs.end();
1371  break;
1372 
1373  case MVT::i32:
1374  if (FormalArg.hasAttribute(Attribute::ZExt)) {
1375  // The O32 ABI does not permit a zero-extended i32.
1376  LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1377  return false;
1378  }
1379 
1380  if (NextGPR32 == GPR32ArgRegs.end()) {
1381  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1382  return false;
1383  }
1384 
1385  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1386  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1387 
1388  // Allocating any GPR32 prohibits further use of floating point arguments.
1389  NextFGR32 = FGR32ArgRegs.end();
1390  NextAFGR64 = AFGR64ArgRegs.end();
1391  break;
1392 
1393  case MVT::f32:
1394  if (UnsupportedFPMode) {
1395  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1396  return false;
1397  }
1398  if (NextFGR32 == FGR32ArgRegs.end()) {
1399  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1400  return false;
1401  }
1402  LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1403  Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1404  // Allocating an FGR32 also allocates the super-register AFGR64, and
1405  // ABI rules require us to skip the corresponding GPR32.
1406  if (NextGPR32 != GPR32ArgRegs.end())
1407  NextGPR32++;
1408  if (NextAFGR64 != AFGR64ArgRegs.end())
1409  NextAFGR64++;
1410  break;
1411 
1412  case MVT::f64:
1413  if (UnsupportedFPMode) {
1414  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1415  return false;
1416  }
1417  if (NextAFGR64 == AFGR64ArgRegs.end()) {
1418  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1419  return false;
1420  }
1421  LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1422  Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1423  // Allocating an FGR32 also allocates the super-register AFGR64, and
1424  // ABI rules require us to skip the corresponding GPR32 pair.
1425  if (NextGPR32 != GPR32ArgRegs.end())
1426  NextGPR32++;
1427  if (NextGPR32 != GPR32ArgRegs.end())
1428  NextGPR32++;
1429  if (NextFGR32 != FGR32ArgRegs.end())
1430  NextFGR32++;
1431  break;
1432 
1433  default:
1434  LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1435  return false;
1436  }
1437  }
1438 
1439  for (const auto &FormalArg : F->args()) {
1440  unsigned ArgNo = FormalArg.getArgNo();
1441  unsigned SrcReg = Allocation[ArgNo].Reg;
1442  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1443  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1444  // Without this, EmitLiveInCopies may eliminate the livein if its only
1445  // use is a bitcast (which isn't turned into an instruction).
1446  unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1447  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1448  TII.get(TargetOpcode::COPY), ResultReg)
1449  .addReg(DstReg, getKillRegState(true));
1450  updateValueMap(&FormalArg, ResultReg);
1451  }
1452 
1453  // Calculate the size of the incoming arguments area.
1454  // We currently reject all the cases where this would be non-zero.
1455  unsigned IncomingArgSizeInBytes = 0;
1456 
1457  // Account for the reserved argument area on ABI's that have one (O32).
1458  // It seems strange to do this on the caller side but it's necessary in
1459  // SelectionDAG's implementation.
1460  IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1461  IncomingArgSizeInBytes);
1462 
1463  MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1464  false);
1465 
1466  return true;
1467 }
1468 
1469 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1470  CallingConv::ID CC = CLI.CallConv;
1471  bool IsTailCall = CLI.IsTailCall;
1472  bool IsVarArg = CLI.IsVarArg;
1473  const Value *Callee = CLI.Callee;
1474  MCSymbol *Symbol = CLI.Symbol;
1475 
1476  // Do not handle FastCC.
1477  if (CC == CallingConv::Fast)
1478  return false;
1479 
1480  // Allow SelectionDAG isel to handle tail calls.
1481  if (IsTailCall)
1482  return false;
1483 
1484  // Let SDISel handle vararg functions.
1485  if (IsVarArg)
1486  return false;
1487 
1488  // FIXME: Only handle *simple* calls for now.
1489  MVT RetVT;
1490  if (CLI.RetTy->isVoidTy())
1491  RetVT = MVT::isVoid;
1492  else if (!isTypeSupported(CLI.RetTy, RetVT))
1493  return false;
1494 
1495  for (auto Flag : CLI.OutFlags)
1496  if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1497  return false;
1498 
1499  // Set up the argument vectors.
1500  SmallVector<MVT, 16> OutVTs;
1501  OutVTs.reserve(CLI.OutVals.size());
1502 
1503  for (auto *Val : CLI.OutVals) {
1504  MVT VT;
1505  if (!isTypeLegal(Val->getType(), VT) &&
1506  !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1507  return false;
1508 
1509  // We don't handle vector parameters yet.
1510  if (VT.isVector() || VT.getSizeInBits() > 64)
1511  return false;
1512 
1513  OutVTs.push_back(VT);
1514  }
1515 
1516  Address Addr;
1517  if (!computeCallAddress(Callee, Addr))
1518  return false;
1519 
1520  // Handle the arguments now that we've gotten them.
1521  unsigned NumBytes;
1522  if (!processCallArgs(CLI, OutVTs, NumBytes))
1523  return false;
1524 
1525  if (!Addr.getGlobalValue())
1526  return false;
1527 
1528  // Issue the call.
1529  unsigned DestAddress;
1530  if (Symbol)
1531  DestAddress = materializeExternalCallSym(Symbol);
1532  else
1533  DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1534  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1535  MachineInstrBuilder MIB =
1536  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1537  Mips::RA).addReg(Mips::T9);
1538 
1539  // Add implicit physical register uses to the call.
1540  for (auto Reg : CLI.OutRegs)
1542 
1543  // Add a register mask with the call-preserved registers.
1544  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1545  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1546 
1547  CLI.Call = MIB;
1548 
1549  // Finish off the call including any return values.
1550  return finishCall(CLI, RetVT, NumBytes);
1551 }
1552 
1553 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1554  switch (II->getIntrinsicID()) {
1555  default:
1556  return false;
1557  case Intrinsic::bswap: {
1558  Type *RetTy = II->getCalledFunction()->getReturnType();
1559 
1560  MVT VT;
1561  if (!isTypeSupported(RetTy, VT))
1562  return false;
1563 
1564  unsigned SrcReg = getRegForValue(II->getOperand(0));
1565  if (SrcReg == 0)
1566  return false;
1567  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1568  if (DestReg == 0)
1569  return false;
1570  if (VT == MVT::i16) {
1571  if (Subtarget->hasMips32r2()) {
1572  emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1573  updateValueMap(II, DestReg);
1574  return true;
1575  } else {
1576  unsigned TempReg[3];
1577  for (int i = 0; i < 3; i++) {
1578  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1579  if (TempReg[i] == 0)
1580  return false;
1581  }
1582  emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1583  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1584  emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1585  emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1586  updateValueMap(II, DestReg);
1587  return true;
1588  }
1589  } else if (VT == MVT::i32) {
1590  if (Subtarget->hasMips32r2()) {
1591  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1592  emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1593  emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1594  updateValueMap(II, DestReg);
1595  return true;
1596  } else {
1597  unsigned TempReg[8];
1598  for (int i = 0; i < 8; i++) {
1599  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1600  if (TempReg[i] == 0)
1601  return false;
1602  }
1603 
1604  emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1605  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1606  emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1607  emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1608 
1609  emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1610  emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1611 
1612  emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1613  emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1614  emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1615  updateValueMap(II, DestReg);
1616  return true;
1617  }
1618  }
1619  return false;
1620  }
1621  case Intrinsic::memcpy:
1622  case Intrinsic::memmove: {
1623  const auto *MTI = cast<MemTransferInst>(II);
1624  // Don't handle volatile.
1625  if (MTI->isVolatile())
1626  return false;
1627  if (!MTI->getLength()->getType()->isIntegerTy(32))
1628  return false;
1629  const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1630  return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1631  }
1632  case Intrinsic::memset: {
1633  const MemSetInst *MSI = cast<MemSetInst>(II);
1634  // Don't handle volatile.
1635  if (MSI->isVolatile())
1636  return false;
1637  if (!MSI->getLength()->getType()->isIntegerTy(32))
1638  return false;
1639  return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1640  }
1641  }
1642  return false;
1643 }
1644 
1645 bool MipsFastISel::selectRet(const Instruction *I) {
1646  const Function &F = *I->getParent()->getParent();
1647  const ReturnInst *Ret = cast<ReturnInst>(I);
1648 
1649  LLVM_DEBUG(dbgs() << "selectRet\n");
1650 
1651  if (!FuncInfo.CanLowerReturn)
1652  return false;
1653 
1654  // Build a list of return value registers.
1655  SmallVector<unsigned, 4> RetRegs;
1656 
1657  if (Ret->getNumOperands() > 0) {
1659 
1660  // Do not handle FastCC.
1661  if (CC == CallingConv::Fast)
1662  return false;
1663 
1665  GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1666 
1667  // Analyze operands of the call, assigning locations to each operand.
1669  MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1670  I->getContext());
1671  CCAssignFn *RetCC = RetCC_Mips;
1672  CCInfo.AnalyzeReturn(Outs, RetCC);
1673 
1674  // Only handle a single return value for now.
1675  if (ValLocs.size() != 1)
1676  return false;
1677 
1678  CCValAssign &VA = ValLocs[0];
1679  const Value *RV = Ret->getOperand(0);
1680 
1681  // Don't bother handling odd stuff for now.
1682  if ((VA.getLocInfo() != CCValAssign::Full) &&
1683  (VA.getLocInfo() != CCValAssign::BCvt))
1684  return false;
1685 
1686  // Only handle register returns for now.
1687  if (!VA.isRegLoc())
1688  return false;
1689 
1690  unsigned Reg = getRegForValue(RV);
1691  if (Reg == 0)
1692  return false;
1693 
1694  unsigned SrcReg = Reg + VA.getValNo();
1695  unsigned DestReg = VA.getLocReg();
1696  // Avoid a cross-class copy. This is very unlikely.
1697  if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1698  return false;
1699 
1700  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1701  if (!RVEVT.isSimple())
1702  return false;
1703 
1704  if (RVEVT.isVector())
1705  return false;
1706 
1707  MVT RVVT = RVEVT.getSimpleVT();
1708  if (RVVT == MVT::f128)
1709  return false;
1710 
1711  // Do not handle FGR64 returns for now.
1712  if (RVVT == MVT::f64 && UnsupportedFPMode) {
1713  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1714  return false;
1715  }
1716 
1717  MVT DestVT = VA.getValVT();
1718  // Special handling for extended integers.
1719  if (RVVT != DestVT) {
1720  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1721  return false;
1722 
1723  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1724  bool IsZExt = Outs[0].Flags.isZExt();
1725  SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1726  if (SrcReg == 0)
1727  return false;
1728  }
1729  }
1730 
1731  // Make the copy.
1732  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1733  TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1734 
1735  // Add register to return instruction.
1736  RetRegs.push_back(VA.getLocReg());
1737  }
1738  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1739  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1740  MIB.addReg(RetRegs[i], RegState::Implicit);
1741  return true;
1742 }
1743 
1744 bool MipsFastISel::selectTrunc(const Instruction *I) {
1745  // The high bits for a type smaller than the register size are assumed to be
1746  // undefined.
1747  Value *Op = I->getOperand(0);
1748 
1749  EVT SrcVT, DestVT;
1750  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1751  DestVT = TLI.getValueType(DL, I->getType(), true);
1752 
1753  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1754  return false;
1755  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1756  return false;
1757 
1758  unsigned SrcReg = getRegForValue(Op);
1759  if (!SrcReg)
1760  return false;
1761 
1762  // Because the high bits are undefined, a truncate doesn't generate
1763  // any code.
1764  updateValueMap(I, SrcReg);
1765  return true;
1766 }
1767 
1768 bool MipsFastISel::selectIntExt(const Instruction *I) {
1769  Type *DestTy = I->getType();
1770  Value *Src = I->getOperand(0);
1771  Type *SrcTy = Src->getType();
1772 
1773  bool isZExt = isa<ZExtInst>(I);
1774  unsigned SrcReg = getRegForValue(Src);
1775  if (!SrcReg)
1776  return false;
1777 
1778  EVT SrcEVT, DestEVT;
1779  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1780  DestEVT = TLI.getValueType(DL, DestTy, true);
1781  if (!SrcEVT.isSimple())
1782  return false;
1783  if (!DestEVT.isSimple())
1784  return false;
1785 
1786  MVT SrcVT = SrcEVT.getSimpleVT();
1787  MVT DestVT = DestEVT.getSimpleVT();
1788  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1789 
1790  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1791  return false;
1792  updateValueMap(I, ResultReg);
1793  return true;
1794 }
1795 
1796 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1797  unsigned DestReg) {
1798  unsigned ShiftAmt;
1799  switch (SrcVT.SimpleTy) {
1800  default:
1801  return false;
1802  case MVT::i8:
1803  ShiftAmt = 24;
1804  break;
1805  case MVT::i16:
1806  ShiftAmt = 16;
1807  break;
1808  }
1809  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1810  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1811  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1812  return true;
1813 }
1814 
1815 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1816  unsigned DestReg) {
1817  switch (SrcVT.SimpleTy) {
1818  default:
1819  return false;
1820  case MVT::i8:
1821  emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1822  break;
1823  case MVT::i16:
1824  emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1825  break;
1826  }
1827  return true;
1828 }
1829 
1830 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1831  unsigned DestReg) {
1832  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1833  return false;
1834  if (Subtarget->hasMips32r2())
1835  return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1836  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1837 }
1838 
1839 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1840  unsigned DestReg) {
1841  int64_t Imm;
1842 
1843  switch (SrcVT.SimpleTy) {
1844  default:
1845  return false;
1846  case MVT::i1:
1847  Imm = 1;
1848  break;
1849  case MVT::i8:
1850  Imm = 0xff;
1851  break;
1852  case MVT::i16:
1853  Imm = 0xffff;
1854  break;
1855  }
1856 
1857  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1858  return true;
1859 }
1860 
1861 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1862  unsigned DestReg, bool IsZExt) {
1863  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1864  // DestVT are odd things, so test to make sure that they are both types we can
1865  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1866  // bail out to SelectionDAG.
1867  if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1868  ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1869  return false;
1870  if (IsZExt)
1871  return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1872  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1873 }
1874 
1875 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1876  bool isZExt) {
1877  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1878  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1879  return Success ? DestReg : 0;
1880 }
1881 
1882 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1883  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1884  if (!DestEVT.isSimple())
1885  return false;
1886 
1887  MVT DestVT = DestEVT.getSimpleVT();
1888  if (DestVT != MVT::i32)
1889  return false;
1890 
1891  unsigned DivOpc;
1892  switch (ISDOpcode) {
1893  default:
1894  return false;
1895  case ISD::SDIV:
1896  case ISD::SREM:
1897  DivOpc = Mips::SDIV;
1898  break;
1899  case ISD::UDIV:
1900  case ISD::UREM:
1901  DivOpc = Mips::UDIV;
1902  break;
1903  }
1904 
1905  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1906  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1907  if (!Src0Reg || !Src1Reg)
1908  return false;
1909 
1910  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1911  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1912 
1913  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1914  if (!ResultReg)
1915  return false;
1916 
1917  unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1918  ? Mips::MFHI
1919  : Mips::MFLO;
1920  emitInst(MFOpc, ResultReg);
1921 
1922  updateValueMap(I, ResultReg);
1923  return true;
1924 }
1925 
1926 bool MipsFastISel::selectShift(const Instruction *I) {
1927  MVT RetVT;
1928 
1929  if (!isTypeSupported(I->getType(), RetVT))
1930  return false;
1931 
1932  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1933  if (!ResultReg)
1934  return false;
1935 
1936  unsigned Opcode = I->getOpcode();
1937  const Value *Op0 = I->getOperand(0);
1938  unsigned Op0Reg = getRegForValue(Op0);
1939  if (!Op0Reg)
1940  return false;
1941 
1942  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1943  if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1944  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1945  if (!TempReg)
1946  return false;
1947 
1948  MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1949  bool IsZExt = Opcode == Instruction::LShr;
1950  if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1951  return false;
1952 
1953  Op0Reg = TempReg;
1954  }
1955 
1956  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1957  uint64_t ShiftVal = C->getZExtValue();
1958 
1959  switch (Opcode) {
1960  default:
1961  llvm_unreachable("Unexpected instruction.");
1962  case Instruction::Shl:
1963  Opcode = Mips::SLL;
1964  break;
1965  case Instruction::AShr:
1966  Opcode = Mips::SRA;
1967  break;
1968  case Instruction::LShr:
1969  Opcode = Mips::SRL;
1970  break;
1971  }
1972 
1973  emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1974  updateValueMap(I, ResultReg);
1975  return true;
1976  }
1977 
1978  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1979  if (!Op1Reg)
1980  return false;
1981 
1982  switch (Opcode) {
1983  default:
1984  llvm_unreachable("Unexpected instruction.");
1985  case Instruction::Shl:
1986  Opcode = Mips::SLLV;
1987  break;
1988  case Instruction::AShr:
1989  Opcode = Mips::SRAV;
1990  break;
1991  case Instruction::LShr:
1992  Opcode = Mips::SRLV;
1993  break;
1994  }
1995 
1996  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1997  updateValueMap(I, ResultReg);
1998  return true;
1999 }
2000 
2001 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2002  switch (I->getOpcode()) {
2003  default:
2004  break;
2005  case Instruction::Load:
2006  return selectLoad(I);
2007  case Instruction::Store:
2008  return selectStore(I);
2009  case Instruction::SDiv:
2010  if (!selectBinaryOp(I, ISD::SDIV))
2011  return selectDivRem(I, ISD::SDIV);
2012  return true;
2013  case Instruction::UDiv:
2014  if (!selectBinaryOp(I, ISD::UDIV))
2015  return selectDivRem(I, ISD::UDIV);
2016  return true;
2017  case Instruction::SRem:
2018  if (!selectBinaryOp(I, ISD::SREM))
2019  return selectDivRem(I, ISD::SREM);
2020  return true;
2021  case Instruction::URem:
2022  if (!selectBinaryOp(I, ISD::UREM))
2023  return selectDivRem(I, ISD::UREM);
2024  return true;
2025  case Instruction::Shl:
2026  case Instruction::LShr:
2027  case Instruction::AShr:
2028  return selectShift(I);
2029  case Instruction::And:
2030  case Instruction::Or:
2031  case Instruction::Xor:
2032  return selectLogicalOp(I);
2033  case Instruction::Br:
2034  return selectBranch(I);
2035  case Instruction::Ret:
2036  return selectRet(I);
2037  case Instruction::Trunc:
2038  return selectTrunc(I);
2039  case Instruction::ZExt:
2040  case Instruction::SExt:
2041  return selectIntExt(I);
2042  case Instruction::FPTrunc:
2043  return selectFPTrunc(I);
2044  case Instruction::FPExt:
2045  return selectFPExt(I);
2046  case Instruction::FPToSI:
2047  return selectFPToInt(I, /*isSigned*/ true);
2048  case Instruction::FPToUI:
2049  return selectFPToInt(I, /*isSigned*/ false);
2050  case Instruction::ICmp:
2051  case Instruction::FCmp:
2052  return selectCmp(I);
2053  case Instruction::Select:
2054  return selectSelect(I);
2055  }
2056  return false;
2057 }
2058 
2059 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2060  bool IsUnsigned) {
2061  unsigned VReg = getRegForValue(V);
2062  if (VReg == 0)
2063  return 0;
2064  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2065 
2066  if (VMVT == MVT::i1)
2067  return 0;
2068 
2069  if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2070  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2071  if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2072  return 0;
2073  VReg = TempReg;
2074  }
2075  return VReg;
2076 }
2077 
2078 void MipsFastISel::simplifyAddress(Address &Addr) {
2079  if (!isInt<16>(Addr.getOffset())) {
2080  unsigned TempReg =
2081  materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2082  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2083  emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2084  Addr.setReg(DestReg);
2085  Addr.setOffset(0);
2086  }
2087 }
2088 
2089 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2090  const TargetRegisterClass *RC,
2091  unsigned Op0, bool Op0IsKill,
2092  unsigned Op1, bool Op1IsKill) {
2093  // We treat the MUL instruction in a special way because it clobbers
2094  // the HI0 & LO0 registers. The TableGen definition of this instruction can
2095  // mark these registers only as implicitly defined. As a result, the
2096  // register allocator runs out of registers when this instruction is
2097  // followed by another instruction that defines the same registers too.
2098  // We can fix this by explicitly marking those registers as dead.
2099  if (MachineInstOpcode == Mips::MUL) {
2100  unsigned ResultReg = createResultReg(RC);
2101  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2102  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2103  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2104  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2105  .addReg(Op0, getKillRegState(Op0IsKill))
2106  .addReg(Op1, getKillRegState(Op1IsKill))
2109  return ResultReg;
2110  }
2111 
2112  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2113  Op1IsKill);
2114 }
2115 
2116 namespace llvm {
2117 
2119  const TargetLibraryInfo *libInfo) {
2120  return new MipsFastISel(funcInfo, libInfo);
2121 }
2122 
2123 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:163
uint64_t CallInst * C
Return a value (possibly void), from a function.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
Function * getCalledFunction() const
Return the function called, or null if this is an indirect function invocation.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:875
bool hasLocalLinkage() const
Definition: GlobalValue.h:435
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1556
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
bool isVector() const
Return true if this is a vector value type.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
const MipsInstrInfo * getInstrInfo() const override
const Value * getTrueValue() const
unsigned less or equal
Definition: InstrTypes.h:911
unsigned less than
Definition: InstrTypes.h:910
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:891
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:714
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:901
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
void reserve(size_type N)
Definition: SmallVector.h:377
Value * getLength() const
op_iterator op_begin()
Definition: User.h:230
bool isMemLoc() const
bool needsCustom() const
SI optimize exec mask operations pre RA
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:521
A description of a memory reference used in the backend.
This class represents the LLVM &#39;select&#39; instruction.
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:97
Class to represent struct types.
Definition: DerivedTypes.h:201
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isUnsigned() const
Definition: InstrTypes.h:1060
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:892
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:885
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:120
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
amdgpu Simplify well known AMD library false Value * Callee
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Value * getOperand(unsigned i) const
Definition: User.h:170
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
Value * getOperand(unsigned i_nocapture) const
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:147
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV)...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:155
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:149
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
op_iterator op_end()
Definition: User.h:232
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:885
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
const MachineInstrBuilder & addFrameIndex(int Idx) const
const Value * getCondition() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
Extended Value Type.
Definition: ValueTypes.h:34
static bool isAtomic(Instruction *I)
bool isVolatile() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:912
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:299
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:51
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:889
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
unsigned getNumOperands() const
Definition: User.h:192
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:914
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:2029
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:224
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
signed less or equal
Definition: InstrTypes.h:915
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
This file defines the FastISel class.
const MipsTargetLowering * getTargetLowering() const override
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
const Value * getFalseValue() const
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:147
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:959
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:543
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:653
unsigned getLocMemOffset() const
unsigned getNumArgOperands() const
Return the number of call arguments.
unsigned greater or equal
Definition: InstrTypes.h:909
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
bool isRegLoc() const
const unsigned Kind
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void GetReturnInfo(Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:888
LLVM Value Representation.
Definition: Value.h:73
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned greater than
Definition: InstrTypes.h:908
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:47
APInt bitcastToAPInt() const
Definition: APFloat.h:1094
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
#define LLVM_DEBUG(X)
Definition: Debug.h:119
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:890
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
bool isFP64bit() const
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void convertToReg(unsigned RegNo)
iterator_range< arg_iterator > args()
Definition: Function.h:675
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:218
signed greater or equal
Definition: InstrTypes.h:913
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:221
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:67
an instruction to allocate memory on the stack
Definition: Instructions.h:60
gep_type_iterator gep_type_begin(const User *GEP)