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MipsFastISel.cpp
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1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
14 ///
15 //===----------------------------------------------------------------------===//
16 
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/FastISel.h"
43 #include "llvm/IR/Attributes.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constant.h"
46 #include "llvm/IR/Constants.h"
47 #include "llvm/IR/DataLayout.h"
48 #include "llvm/IR/Function.h"
50 #include "llvm/IR/GlobalValue.h"
51 #include "llvm/IR/GlobalVariable.h"
52 #include "llvm/IR/InstrTypes.h"
53 #include "llvm/IR/Instruction.h"
54 #include "llvm/IR/Instructions.h"
55 #include "llvm/IR/IntrinsicInst.h"
56 #include "llvm/IR/Operator.h"
57 #include "llvm/IR/Type.h"
58 #include "llvm/IR/User.h"
59 #include "llvm/IR/Value.h"
60 #include "llvm/MC/MCInstrDesc.h"
61 #include "llvm/MC/MCRegisterInfo.h"
62 #include "llvm/MC/MCSymbol.h"
63 #include "llvm/Support/Casting.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <cassert>
71 #include <cstdint>
72 
73 #define DEBUG_TYPE "mips-fastisel"
74 
75 using namespace llvm;
76 
77 namespace {
78 
79 class MipsFastISel final : public FastISel {
80 
81  // All possible address modes.
82  class Address {
83  public:
84  using BaseKind = enum { RegBase, FrameIndexBase };
85 
86  private:
87  BaseKind Kind = RegBase;
88  union {
89  unsigned Reg;
90  int FI;
91  } Base;
92 
93  int64_t Offset = 0;
94 
95  const GlobalValue *GV = nullptr;
96 
97  public:
98  // Innocuous defaults for our address.
99  Address() { Base.Reg = 0; }
100 
101  void setKind(BaseKind K) { Kind = K; }
102  BaseKind getKind() const { return Kind; }
103  bool isRegBase() const { return Kind == RegBase; }
104  bool isFIBase() const { return Kind == FrameIndexBase; }
105 
106  void setReg(unsigned Reg) {
107  assert(isRegBase() && "Invalid base register access!");
108  Base.Reg = Reg;
109  }
110 
111  unsigned getReg() const {
112  assert(isRegBase() && "Invalid base register access!");
113  return Base.Reg;
114  }
115 
116  void setFI(unsigned FI) {
117  assert(isFIBase() && "Invalid base frame index access!");
118  Base.FI = FI;
119  }
120 
121  unsigned getFI() const {
122  assert(isFIBase() && "Invalid base frame index access!");
123  return Base.FI;
124  }
125 
126  void setOffset(int64_t Offset_) { Offset = Offset_; }
127  int64_t getOffset() const { return Offset; }
128  void setGlobalValue(const GlobalValue *G) { GV = G; }
129  const GlobalValue *getGlobalValue() { return GV; }
130  };
131 
132  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
133  /// make the right decision when generating code for different targets.
134  const TargetMachine &TM;
135  const MipsSubtarget *Subtarget;
136  const TargetInstrInfo &TII;
137  const TargetLowering &TLI;
138  MipsFunctionInfo *MFI;
139 
140  // Convenience variables to avoid some queries.
142 
143  bool fastLowerArguments() override;
144  bool fastLowerCall(CallLoweringInfo &CLI) override;
145  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
146 
147  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
148  // floating point but not reject doing fast-isel in other
149  // situations
150 
151 private:
152  // Selection routines.
153  bool selectLogicalOp(const Instruction *I);
154  bool selectLoad(const Instruction *I);
155  bool selectStore(const Instruction *I);
156  bool selectBranch(const Instruction *I);
157  bool selectSelect(const Instruction *I);
158  bool selectCmp(const Instruction *I);
159  bool selectFPExt(const Instruction *I);
160  bool selectFPTrunc(const Instruction *I);
161  bool selectFPToInt(const Instruction *I, bool IsSigned);
162  bool selectRet(const Instruction *I);
163  bool selectTrunc(const Instruction *I);
164  bool selectIntExt(const Instruction *I);
165  bool selectShift(const Instruction *I);
166  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
167 
168  // Utility helper routines.
169  bool isTypeLegal(Type *Ty, MVT &VT);
170  bool isTypeSupported(Type *Ty, MVT &VT);
171  bool isLoadTypeLegal(Type *Ty, MVT &VT);
172  bool computeAddress(const Value *Obj, Address &Addr);
173  bool computeCallAddress(const Value *V, Address &Addr);
174  void simplifyAddress(Address &Addr);
175 
176  // Emit helper routines.
177  bool emitCmp(unsigned DestReg, const CmpInst *CI);
178  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
179  unsigned Alignment = 0);
180  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
181  MachineMemOperand *MMO = nullptr);
182  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
183  unsigned Alignment = 0);
184  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
185  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
186 
187  bool IsZExt);
188  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 
190  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
191  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192  unsigned DestReg);
193  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
194  unsigned DestReg);
195 
196  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
197 
198  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
199  const Value *RHS);
200 
201  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
202  unsigned materializeGV(const GlobalValue *GV, MVT VT);
203  unsigned materializeInt(const Constant *C, MVT VT);
204  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
205  unsigned materializeExternalCallSym(MCSymbol *Syn);
206 
207  MachineInstrBuilder emitInst(unsigned Opc) {
208  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
209  }
210 
211  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
212  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
213  DstReg);
214  }
215 
216  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
217  unsigned MemReg, int64_t MemOffset) {
218  return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
219  }
220 
221  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
222  unsigned MemReg, int64_t MemOffset) {
223  return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
224  }
225 
226  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
227  const TargetRegisterClass *RC,
228  unsigned Op0, bool Op0IsKill,
229  unsigned Op1, bool Op1IsKill);
230 
231  // for some reason, this default is not generated by tablegen
232  // so we explicitly generate it here.
233  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
234  unsigned Op0, bool Op0IsKill, uint64_t imm1,
235  uint64_t imm2, unsigned Op3, bool Op3IsKill) {
236  return 0;
237  }
238 
239  // Call handling routines.
240 private:
241  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
242  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
243  unsigned &NumBytes);
244  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
245 
246  const MipsABIInfo &getABI() const {
247  return static_cast<const MipsTargetMachine &>(TM).getABI();
248  }
249 
250 public:
251  // Backend specific FastISel code.
252  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
253  const TargetLibraryInfo *libInfo)
254  : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
255  Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
256  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
257  MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
258  Context = &funcInfo.Fn->getContext();
259  UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
260  }
261 
262  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
263  unsigned fastMaterializeConstant(const Constant *C) override;
264  bool fastSelectInstruction(const Instruction *I) override;
265 
266 #include "MipsGenFastISel.inc"
267 };
268 
269 } // end anonymous namespace
270 
271 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
272  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
274 
275 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
276  CCValAssign::LocInfo LocInfo,
277  ISD::ArgFlagsTy ArgFlags, CCState &State) {
278  llvm_unreachable("should not be called");
279 }
280 
281 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
282  CCValAssign::LocInfo LocInfo,
283  ISD::ArgFlagsTy ArgFlags, CCState &State) {
284  llvm_unreachable("should not be called");
285 }
286 
287 #include "MipsGenCallingConv.inc"
288 
289 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
290  return CC_MipsO32;
291 }
292 
293 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
294  const Value *LHS, const Value *RHS) {
295  // Canonicalize immediates to the RHS first.
296  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
297  std::swap(LHS, RHS);
298 
299  unsigned Opc;
300  switch (ISDOpc) {
301  case ISD::AND:
302  Opc = Mips::AND;
303  break;
304  case ISD::OR:
305  Opc = Mips::OR;
306  break;
307  case ISD::XOR:
308  Opc = Mips::XOR;
309  break;
310  default:
311  llvm_unreachable("unexpected opcode");
312  }
313 
314  unsigned LHSReg = getRegForValue(LHS);
315  if (!LHSReg)
316  return 0;
317 
318  unsigned RHSReg;
319  if (const auto *C = dyn_cast<ConstantInt>(RHS))
320  RHSReg = materializeInt(C, MVT::i32);
321  else
322  RHSReg = getRegForValue(RHS);
323  if (!RHSReg)
324  return 0;
325 
326  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
327  if (!ResultReg)
328  return 0;
329 
330  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
331  return ResultReg;
332 }
333 
334 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
335  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
336  "Alloca should always return a pointer.");
337 
339  FuncInfo.StaticAllocaMap.find(AI);
340 
341  if (SI != FuncInfo.StaticAllocaMap.end()) {
342  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
343  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
344  ResultReg)
345  .addFrameIndex(SI->second)
346  .addImm(0);
347  return ResultReg;
348  }
349 
350  return 0;
351 }
352 
353 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
354  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
355  return 0;
356  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
357  const ConstantInt *CI = cast<ConstantInt>(C);
358  return materialize32BitInt(CI->getZExtValue(), RC);
359 }
360 
361 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
362  const TargetRegisterClass *RC) {
363  unsigned ResultReg = createResultReg(RC);
364 
365  if (isInt<16>(Imm)) {
366  unsigned Opc = Mips::ADDiu;
367  emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
368  return ResultReg;
369  } else if (isUInt<16>(Imm)) {
370  emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
371  return ResultReg;
372  }
373  unsigned Lo = Imm & 0xFFFF;
374  unsigned Hi = (Imm >> 16) & 0xFFFF;
375  if (Lo) {
376  // Both Lo and Hi have nonzero bits.
377  unsigned TmpReg = createResultReg(RC);
378  emitInst(Mips::LUi, TmpReg).addImm(Hi);
379  emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
380  } else {
381  emitInst(Mips::LUi, ResultReg).addImm(Hi);
382  }
383  return ResultReg;
384 }
385 
386 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
387  if (UnsupportedFPMode)
388  return 0;
389  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
390  if (VT == MVT::f32) {
391  const TargetRegisterClass *RC = &Mips::FGR32RegClass;
392  unsigned DestReg = createResultReg(RC);
393  unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
394  emitInst(Mips::MTC1, DestReg).addReg(TempReg);
395  return DestReg;
396  } else if (VT == MVT::f64) {
397  const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
398  unsigned DestReg = createResultReg(RC);
399  unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
400  unsigned TempReg2 =
401  materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
402  emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
403  return DestReg;
404  }
405  return 0;
406 }
407 
408 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
409  // For now 32-bit only.
410  if (VT != MVT::i32)
411  return 0;
412  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
413  unsigned DestReg = createResultReg(RC);
414  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
415  bool IsThreadLocal = GVar && GVar->isThreadLocal();
416  // TLS not supported at this time.
417  if (IsThreadLocal)
418  return 0;
419  emitInst(Mips::LW, DestReg)
420  .addReg(MFI->getGlobalBaseReg())
421  .addGlobalAddress(GV, 0, MipsII::MO_GOT);
422  if ((GV->hasInternalLinkage() ||
423  (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
424  unsigned TempReg = createResultReg(RC);
425  emitInst(Mips::ADDiu, TempReg)
426  .addReg(DestReg)
427  .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
428  DestReg = TempReg;
429  }
430  return DestReg;
431 }
432 
433 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
434  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
435  unsigned DestReg = createResultReg(RC);
436  emitInst(Mips::LW, DestReg)
437  .addReg(MFI->getGlobalBaseReg())
438  .addSym(Sym, MipsII::MO_GOT);
439  return DestReg;
440 }
441 
442 // Materialize a constant into a register, and return the register
443 // number (or zero if we failed to handle it).
444 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
445  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
446 
447  // Only handle simple types.
448  if (!CEVT.isSimple())
449  return 0;
450  MVT VT = CEVT.getSimpleVT();
451 
452  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
453  return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
454  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
455  return materializeGV(GV, VT);
456  else if (isa<ConstantInt>(C))
457  return materializeInt(C, VT);
458 
459  return 0;
460 }
461 
462 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
463  const User *U = nullptr;
464  unsigned Opcode = Instruction::UserOp1;
465  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
466  // Don't walk into other basic blocks unless the object is an alloca from
467  // another block, otherwise it may not have a virtual register assigned.
468  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
469  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
470  Opcode = I->getOpcode();
471  U = I;
472  }
473  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
474  Opcode = C->getOpcode();
475  U = C;
476  }
477  switch (Opcode) {
478  default:
479  break;
480  case Instruction::BitCast:
481  // Look through bitcasts.
482  return computeAddress(U->getOperand(0), Addr);
483  case Instruction::GetElementPtr: {
484  Address SavedAddr = Addr;
485  int64_t TmpOffset = Addr.getOffset();
486  // Iterate through the GEP folding the constants into offsets where
487  // we can.
489  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
490  ++i, ++GTI) {
491  const Value *Op = *i;
492  if (StructType *STy = GTI.getStructTypeOrNull()) {
493  const StructLayout *SL = DL.getStructLayout(STy);
494  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
495  TmpOffset += SL->getElementOffset(Idx);
496  } else {
497  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
498  while (true) {
499  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
500  // Constant-offset addressing.
501  TmpOffset += CI->getSExtValue() * S;
502  break;
503  }
504  if (canFoldAddIntoGEP(U, Op)) {
505  // A compatible add with a constant operand. Fold the constant.
506  ConstantInt *CI =
507  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
508  TmpOffset += CI->getSExtValue() * S;
509  // Iterate on the other operand.
510  Op = cast<AddOperator>(Op)->getOperand(0);
511  continue;
512  }
513  // Unsupported
514  goto unsupported_gep;
515  }
516  }
517  }
518  // Try to grab the base operand now.
519  Addr.setOffset(TmpOffset);
520  if (computeAddress(U->getOperand(0), Addr))
521  return true;
522  // We failed, restore everything and try the other options.
523  Addr = SavedAddr;
524  unsupported_gep:
525  break;
526  }
527  case Instruction::Alloca: {
528  const AllocaInst *AI = cast<AllocaInst>(Obj);
530  FuncInfo.StaticAllocaMap.find(AI);
531  if (SI != FuncInfo.StaticAllocaMap.end()) {
532  Addr.setKind(Address::FrameIndexBase);
533  Addr.setFI(SI->second);
534  return true;
535  }
536  break;
537  }
538  }
539  Addr.setReg(getRegForValue(Obj));
540  return Addr.getReg() != 0;
541 }
542 
543 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
544  const User *U = nullptr;
545  unsigned Opcode = Instruction::UserOp1;
546 
547  if (const auto *I = dyn_cast<Instruction>(V)) {
548  // Check if the value is defined in the same basic block. This information
549  // is crucial to know whether or not folding an operand is valid.
550  if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
551  Opcode = I->getOpcode();
552  U = I;
553  }
554  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
555  Opcode = C->getOpcode();
556  U = C;
557  }
558 
559  switch (Opcode) {
560  default:
561  break;
562  case Instruction::BitCast:
563  // Look past bitcasts if its operand is in the same BB.
564  return computeCallAddress(U->getOperand(0), Addr);
565  break;
566  case Instruction::IntToPtr:
567  // Look past no-op inttoptrs if its operand is in the same BB.
568  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
569  TLI.getPointerTy(DL))
570  return computeCallAddress(U->getOperand(0), Addr);
571  break;
572  case Instruction::PtrToInt:
573  // Look past no-op ptrtoints if its operand is in the same BB.
574  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
575  return computeCallAddress(U->getOperand(0), Addr);
576  break;
577  }
578 
579  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
580  Addr.setGlobalValue(GV);
581  return true;
582  }
583 
584  // If all else fails, try to materialize the value in a register.
585  if (!Addr.getGlobalValue()) {
586  Addr.setReg(getRegForValue(V));
587  return Addr.getReg() != 0;
588  }
589 
590  return false;
591 }
592 
593 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
594  EVT evt = TLI.getValueType(DL, Ty, true);
595  // Only handle simple types.
596  if (evt == MVT::Other || !evt.isSimple())
597  return false;
598  VT = evt.getSimpleVT();
599 
600  // Handle all legal types, i.e. a register that will directly hold this
601  // value.
602  return TLI.isTypeLegal(VT);
603 }
604 
605 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
606  if (Ty->isVectorTy())
607  return false;
608 
609  if (isTypeLegal(Ty, VT))
610  return true;
611 
612  // If this is a type than can be sign or zero-extended to a basic operation
613  // go ahead and accept it now.
614  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
615  return true;
616 
617  return false;
618 }
619 
620 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
621  if (isTypeLegal(Ty, VT))
622  return true;
623  // We will extend this in a later patch:
624  // If this is a type than can be sign or zero-extended to a basic operation
625  // go ahead and accept it now.
626  if (VT == MVT::i8 || VT == MVT::i16)
627  return true;
628  return false;
629 }
630 
631 // Because of how EmitCmp is called with fast-isel, you can
632 // end up with redundant "andi" instructions after the sequences emitted below.
633 // We should try and solve this issue in the future.
634 //
635 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
636  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
637  bool IsUnsigned = CI->isUnsigned();
638  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
639  if (LeftReg == 0)
640  return false;
641  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
642  if (RightReg == 0)
643  return false;
645 
646  switch (P) {
647  default:
648  return false;
649  case CmpInst::ICMP_EQ: {
650  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
651  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
652  emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
653  break;
654  }
655  case CmpInst::ICMP_NE: {
656  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
657  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
658  emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
659  break;
660  }
661  case CmpInst::ICMP_UGT:
662  emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
663  break;
664  case CmpInst::ICMP_ULT:
665  emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
666  break;
667  case CmpInst::ICMP_UGE: {
668  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
669  emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
670  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
671  break;
672  }
673  case CmpInst::ICMP_ULE: {
674  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
675  emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
676  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
677  break;
678  }
679  case CmpInst::ICMP_SGT:
680  emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
681  break;
682  case CmpInst::ICMP_SLT:
683  emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
684  break;
685  case CmpInst::ICMP_SGE: {
686  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
687  emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
688  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
689  break;
690  }
691  case CmpInst::ICMP_SLE: {
692  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
693  emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
694  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
695  break;
696  }
697  case CmpInst::FCMP_OEQ:
698  case CmpInst::FCMP_UNE:
699  case CmpInst::FCMP_OLT:
700  case CmpInst::FCMP_OLE:
701  case CmpInst::FCMP_OGT:
702  case CmpInst::FCMP_OGE: {
703  if (UnsupportedFPMode)
704  return false;
705  bool IsFloat = Left->getType()->isFloatTy();
706  bool IsDouble = Left->getType()->isDoubleTy();
707  if (!IsFloat && !IsDouble)
708  return false;
709  unsigned Opc, CondMovOpc;
710  switch (P) {
711  case CmpInst::FCMP_OEQ:
712  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
713  CondMovOpc = Mips::MOVT_I;
714  break;
715  case CmpInst::FCMP_UNE:
716  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
717  CondMovOpc = Mips::MOVF_I;
718  break;
719  case CmpInst::FCMP_OLT:
720  Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
721  CondMovOpc = Mips::MOVT_I;
722  break;
723  case CmpInst::FCMP_OLE:
724  Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
725  CondMovOpc = Mips::MOVT_I;
726  break;
727  case CmpInst::FCMP_OGT:
728  Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
729  CondMovOpc = Mips::MOVF_I;
730  break;
731  case CmpInst::FCMP_OGE:
732  Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
733  CondMovOpc = Mips::MOVF_I;
734  break;
735  default:
736  llvm_unreachable("Only switching of a subset of CCs.");
737  }
738  unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
739  unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
740  emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
741  emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
742  emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
743  .addReg(RightReg);
744  emitInst(CondMovOpc, ResultReg)
745  .addReg(RegWithOne)
746  .addReg(Mips::FCC0)
747  .addReg(RegWithZero);
748  break;
749  }
750  }
751  return true;
752 }
753 
754 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
755  unsigned Alignment) {
756  //
757  // more cases will be handled here in following patches.
758  //
759  unsigned Opc;
760  switch (VT.SimpleTy) {
761  case MVT::i32:
762  ResultReg = createResultReg(&Mips::GPR32RegClass);
763  Opc = Mips::LW;
764  break;
765  case MVT::i16:
766  ResultReg = createResultReg(&Mips::GPR32RegClass);
767  Opc = Mips::LHu;
768  break;
769  case MVT::i8:
770  ResultReg = createResultReg(&Mips::GPR32RegClass);
771  Opc = Mips::LBu;
772  break;
773  case MVT::f32:
774  if (UnsupportedFPMode)
775  return false;
776  ResultReg = createResultReg(&Mips::FGR32RegClass);
777  Opc = Mips::LWC1;
778  break;
779  case MVT::f64:
780  if (UnsupportedFPMode)
781  return false;
782  ResultReg = createResultReg(&Mips::AFGR64RegClass);
783  Opc = Mips::LDC1;
784  break;
785  default:
786  return false;
787  }
788  if (Addr.isRegBase()) {
789  simplifyAddress(Addr);
790  emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
791  return true;
792  }
793  if (Addr.isFIBase()) {
794  unsigned FI = Addr.getFI();
795  unsigned Align = 4;
796  int64_t Offset = Addr.getOffset();
797  MachineFrameInfo &MFI = MF->getFrameInfo();
798  MachineMemOperand *MMO = MF->getMachineMemOperand(
800  MFI.getObjectSize(FI), Align);
801  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
802  .addFrameIndex(FI)
803  .addImm(Offset)
804  .addMemOperand(MMO);
805  return true;
806  }
807  return false;
808 }
809 
810 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
811  unsigned Alignment) {
812  //
813  // more cases will be handled here in following patches.
814  //
815  unsigned Opc;
816  switch (VT.SimpleTy) {
817  case MVT::i8:
818  Opc = Mips::SB;
819  break;
820  case MVT::i16:
821  Opc = Mips::SH;
822  break;
823  case MVT::i32:
824  Opc = Mips::SW;
825  break;
826  case MVT::f32:
827  if (UnsupportedFPMode)
828  return false;
829  Opc = Mips::SWC1;
830  break;
831  case MVT::f64:
832  if (UnsupportedFPMode)
833  return false;
834  Opc = Mips::SDC1;
835  break;
836  default:
837  return false;
838  }
839  if (Addr.isRegBase()) {
840  simplifyAddress(Addr);
841  emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
842  return true;
843  }
844  if (Addr.isFIBase()) {
845  unsigned FI = Addr.getFI();
846  unsigned Align = 4;
847  int64_t Offset = Addr.getOffset();
848  MachineFrameInfo &MFI = MF->getFrameInfo();
849  MachineMemOperand *MMO = MF->getMachineMemOperand(
851  MFI.getObjectSize(FI), Align);
852  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
853  .addReg(SrcReg)
854  .addFrameIndex(FI)
855  .addImm(Offset)
856  .addMemOperand(MMO);
857  return true;
858  }
859  return false;
860 }
861 
862 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
863  MVT VT;
864  if (!isTypeSupported(I->getType(), VT))
865  return false;
866 
867  unsigned ResultReg;
868  switch (I->getOpcode()) {
869  default:
870  llvm_unreachable("Unexpected instruction.");
871  case Instruction::And:
872  ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
873  break;
874  case Instruction::Or:
875  ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
876  break;
877  case Instruction::Xor:
878  ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
879  break;
880  }
881 
882  if (!ResultReg)
883  return false;
884 
885  updateValueMap(I, ResultReg);
886  return true;
887 }
888 
889 bool MipsFastISel::selectLoad(const Instruction *I) {
890  // Atomic loads need special handling.
891  if (cast<LoadInst>(I)->isAtomic())
892  return false;
893 
894  // Verify we have a legal type before going any further.
895  MVT VT;
896  if (!isLoadTypeLegal(I->getType(), VT))
897  return false;
898 
899  // See if we can handle this address.
900  Address Addr;
901  if (!computeAddress(I->getOperand(0), Addr))
902  return false;
903 
904  unsigned ResultReg;
905  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
906  return false;
907  updateValueMap(I, ResultReg);
908  return true;
909 }
910 
911 bool MipsFastISel::selectStore(const Instruction *I) {
912  Value *Op0 = I->getOperand(0);
913  unsigned SrcReg = 0;
914 
915  // Atomic stores need special handling.
916  if (cast<StoreInst>(I)->isAtomic())
917  return false;
918 
919  // Verify we have a legal type before going any further.
920  MVT VT;
921  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
922  return false;
923 
924  // Get the value to be stored into a register.
925  SrcReg = getRegForValue(Op0);
926  if (SrcReg == 0)
927  return false;
928 
929  // See if we can handle this address.
930  Address Addr;
931  if (!computeAddress(I->getOperand(1), Addr))
932  return false;
933 
934  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
935  return false;
936  return true;
937 }
938 
939 // This can cause a redundant sltiu to be generated.
940 // FIXME: try and eliminate this in a future patch.
941 bool MipsFastISel::selectBranch(const Instruction *I) {
942  const BranchInst *BI = cast<BranchInst>(I);
943  MachineBasicBlock *BrBB = FuncInfo.MBB;
944  //
945  // TBB is the basic block for the case where the comparison is true.
946  // FBB is the basic block for the case where the comparison is false.
947  // if (cond) goto TBB
948  // goto FBB
949  // TBB:
950  //
951  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
952  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
953  BI->getCondition();
954  // For now, just try the simplest case where it's fed by a compare.
955  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
956  unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
957  if (!emitCmp(CondReg, CI))
958  return false;
959  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
960  .addReg(CondReg)
961  .addMBB(TBB);
962  finishCondBranch(BI->getParent(), TBB, FBB);
963  return true;
964  }
965  return false;
966 }
967 
968 bool MipsFastISel::selectCmp(const Instruction *I) {
969  const CmpInst *CI = cast<CmpInst>(I);
970  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
971  if (!emitCmp(ResultReg, CI))
972  return false;
973  updateValueMap(I, ResultReg);
974  return true;
975 }
976 
977 // Attempt to fast-select a floating-point extend instruction.
978 bool MipsFastISel::selectFPExt(const Instruction *I) {
979  if (UnsupportedFPMode)
980  return false;
981  Value *Src = I->getOperand(0);
982  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
983  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
984 
985  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
986  return false;
987 
988  unsigned SrcReg =
989  getRegForValue(Src); // this must be a 32bit floating point register class
990  // maybe we should handle this differently
991  if (!SrcReg)
992  return false;
993 
994  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
995  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
996  updateValueMap(I, DestReg);
997  return true;
998 }
999 
1000 bool MipsFastISel::selectSelect(const Instruction *I) {
1001  assert(isa<SelectInst>(I) && "Expected a select instruction.");
1002 
1003  DEBUG(dbgs() << "selectSelect\n");
1004 
1005  MVT VT;
1006  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1007  DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1008  return false;
1009  }
1010 
1011  unsigned CondMovOpc;
1012  const TargetRegisterClass *RC;
1013 
1014  if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1015  CondMovOpc = Mips::MOVN_I_I;
1016  RC = &Mips::GPR32RegClass;
1017  } else if (VT == MVT::f32) {
1018  CondMovOpc = Mips::MOVN_I_S;
1019  RC = &Mips::FGR32RegClass;
1020  } else if (VT == MVT::f64) {
1021  CondMovOpc = Mips::MOVN_I_D32;
1022  RC = &Mips::AFGR64RegClass;
1023  } else
1024  return false;
1025 
1026  const SelectInst *SI = cast<SelectInst>(I);
1027  const Value *Cond = SI->getCondition();
1028  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1029  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1030  unsigned CondReg = getRegForValue(Cond);
1031 
1032  if (!Src1Reg || !Src2Reg || !CondReg)
1033  return false;
1034 
1035  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1036  if (!ZExtCondReg)
1037  return false;
1038 
1039  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1040  return false;
1041 
1042  unsigned ResultReg = createResultReg(RC);
1043  unsigned TempReg = createResultReg(RC);
1044 
1045  if (!ResultReg || !TempReg)
1046  return false;
1047 
1048  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1049  emitInst(CondMovOpc, ResultReg)
1050  .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1051  updateValueMap(I, ResultReg);
1052  return true;
1053 }
1054 
1055 // Attempt to fast-select a floating-point truncate instruction.
1056 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1057  if (UnsupportedFPMode)
1058  return false;
1059  Value *Src = I->getOperand(0);
1060  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1061  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1062 
1063  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1064  return false;
1065 
1066  unsigned SrcReg = getRegForValue(Src);
1067  if (!SrcReg)
1068  return false;
1069 
1070  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1071  if (!DestReg)
1072  return false;
1073 
1074  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1075  updateValueMap(I, DestReg);
1076  return true;
1077 }
1078 
1079 // Attempt to fast-select a floating-point-to-integer conversion.
1080 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1081  if (UnsupportedFPMode)
1082  return false;
1083  MVT DstVT, SrcVT;
1084  if (!IsSigned)
1085  return false; // We don't handle this case yet. There is no native
1086  // instruction for this but it can be synthesized.
1087  Type *DstTy = I->getType();
1088  if (!isTypeLegal(DstTy, DstVT))
1089  return false;
1090 
1091  if (DstVT != MVT::i32)
1092  return false;
1093 
1094  Value *Src = I->getOperand(0);
1095  Type *SrcTy = Src->getType();
1096  if (!isTypeLegal(SrcTy, SrcVT))
1097  return false;
1098 
1099  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1100  return false;
1101 
1102  unsigned SrcReg = getRegForValue(Src);
1103  if (SrcReg == 0)
1104  return false;
1105 
1106  // Determine the opcode for the conversion, which takes place
1107  // entirely within FPRs.
1108  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1109  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1110  unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1111 
1112  // Generate the convert.
1113  emitInst(Opc, TempReg).addReg(SrcReg);
1114  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1115 
1116  updateValueMap(I, DestReg);
1117  return true;
1118 }
1119 
1120 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1121  SmallVectorImpl<MVT> &OutVTs,
1122  unsigned &NumBytes) {
1123  CallingConv::ID CC = CLI.CallConv;
1125  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1126  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1127  // Get a count of how many bytes are to be pushed on the stack.
1128  NumBytes = CCInfo.getNextStackOffset();
1129  // This is the minimum argument area used for A0-A3.
1130  if (NumBytes < 16)
1131  NumBytes = 16;
1132 
1133  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1134  // Process the args.
1135  MVT firstMVT;
1136  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1137  CCValAssign &VA = ArgLocs[i];
1138  const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1139  MVT ArgVT = OutVTs[VA.getValNo()];
1140 
1141  if (i == 0) {
1142  firstMVT = ArgVT;
1143  if (ArgVT == MVT::f32) {
1144  VA.convertToReg(Mips::F12);
1145  } else if (ArgVT == MVT::f64) {
1146  VA.convertToReg(Mips::D6);
1147  }
1148  } else if (i == 1) {
1149  if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1150  if (ArgVT == MVT::f32) {
1151  VA.convertToReg(Mips::F14);
1152  } else if (ArgVT == MVT::f64) {
1153  VA.convertToReg(Mips::D7);
1154  }
1155  }
1156  }
1157  if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1158  (ArgVT == MVT::i8)) &&
1159  VA.isMemLoc()) {
1160  switch (VA.getLocMemOffset()) {
1161  case 0:
1162  VA.convertToReg(Mips::A0);
1163  break;
1164  case 4:
1165  VA.convertToReg(Mips::A1);
1166  break;
1167  case 8:
1168  VA.convertToReg(Mips::A2);
1169  break;
1170  case 12:
1171  VA.convertToReg(Mips::A3);
1172  break;
1173  default:
1174  break;
1175  }
1176  }
1177  unsigned ArgReg = getRegForValue(ArgVal);
1178  if (!ArgReg)
1179  return false;
1180 
1181  // Handle arg promotion: SExt, ZExt, AExt.
1182  switch (VA.getLocInfo()) {
1183  case CCValAssign::Full:
1184  break;
1185  case CCValAssign::AExt:
1186  case CCValAssign::SExt: {
1187  MVT DestVT = VA.getLocVT();
1188  MVT SrcVT = ArgVT;
1189  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1190  if (!ArgReg)
1191  return false;
1192  break;
1193  }
1194  case CCValAssign::ZExt: {
1195  MVT DestVT = VA.getLocVT();
1196  MVT SrcVT = ArgVT;
1197  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1198  if (!ArgReg)
1199  return false;
1200  break;
1201  }
1202  default:
1203  llvm_unreachable("Unknown arg promotion!");
1204  }
1205 
1206  // Now copy/store arg to correct locations.
1207  if (VA.isRegLoc() && !VA.needsCustom()) {
1208  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1209  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1210  CLI.OutRegs.push_back(VA.getLocReg());
1211  } else if (VA.needsCustom()) {
1212  llvm_unreachable("Mips does not use custom args.");
1213  return false;
1214  } else {
1215  //
1216  // FIXME: This path will currently return false. It was copied
1217  // from the AArch64 port and should be essentially fine for Mips too.
1218  // The work to finish up this path will be done in a follow-on patch.
1219  //
1220  assert(VA.isMemLoc() && "Assuming store on stack.");
1221  // Don't emit stores for undef values.
1222  if (isa<UndefValue>(ArgVal))
1223  continue;
1224 
1225  // Need to store on the stack.
1226  // FIXME: This alignment is incorrect but this path is disabled
1227  // for now (will return false). We need to determine the right alignment
1228  // based on the normal alignment for the underlying machine type.
1229  //
1230  unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1231 
1232  unsigned BEAlign = 0;
1233  if (ArgSize < 8 && !Subtarget->isLittle())
1234  BEAlign = 8 - ArgSize;
1235 
1236  Address Addr;
1237  Addr.setKind(Address::RegBase);
1238  Addr.setReg(Mips::SP);
1239  Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1240 
1241  unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1242  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1243  MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1244  MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1245  (void)(MMO);
1246  // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1247  return false; // can't store on the stack yet.
1248  }
1249  }
1250 
1251  return true;
1252 }
1253 
1254 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1255  unsigned NumBytes) {
1256  CallingConv::ID CC = CLI.CallConv;
1257  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1258  if (RetVT != MVT::isVoid) {
1260  MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1261 
1262  CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1263  CLI.Symbol ? CLI.Symbol->getName().data()
1264  : nullptr);
1265 
1266  // Only handle a single return value.
1267  if (RVLocs.size() != 1)
1268  return false;
1269  // Copy all of the result registers out of their specified physreg.
1270  MVT CopyVT = RVLocs[0].getValVT();
1271  // Special handling for extended integers.
1272  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1273  CopyVT = MVT::i32;
1274 
1275  unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1276  if (!ResultReg)
1277  return false;
1278  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1279  TII.get(TargetOpcode::COPY),
1280  ResultReg).addReg(RVLocs[0].getLocReg());
1281  CLI.InRegs.push_back(RVLocs[0].getLocReg());
1282 
1283  CLI.ResultReg = ResultReg;
1284  CLI.NumResultRegs = 1;
1285  }
1286  return true;
1287 }
1288 
1289 bool MipsFastISel::fastLowerArguments() {
1290  DEBUG(dbgs() << "fastLowerArguments\n");
1291 
1292  if (!FuncInfo.CanLowerReturn) {
1293  DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1294  return false;
1295  }
1296 
1297  const Function *F = FuncInfo.Fn;
1298  if (F->isVarArg()) {
1299  DEBUG(dbgs() << ".. gave up (varargs)\n");
1300  return false;
1301  }
1302 
1303  CallingConv::ID CC = F->getCallingConv();
1304  if (CC != CallingConv::C) {
1305  DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1306  return false;
1307  }
1308 
1309  const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
1310  Mips::A3};
1311  const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
1312  const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
1313  ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
1314  ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
1315  ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
1316 
1317  struct AllocatedReg {
1318  const TargetRegisterClass *RC;
1319  unsigned Reg;
1320  AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1321  : RC(RC), Reg(Reg) {}
1322  };
1323 
1324  // Only handle simple cases. i.e. All arguments are directly mapped to
1325  // registers of the appropriate type.
1327  for (const auto &FormalArg : F->args()) {
1328  if (FormalArg.hasAttribute(Attribute::InReg) ||
1329  FormalArg.hasAttribute(Attribute::StructRet) ||
1330  FormalArg.hasAttribute(Attribute::ByVal)) {
1331  DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1332  return false;
1333  }
1334 
1335  Type *ArgTy = FormalArg.getType();
1336  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1337  DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1338  return false;
1339  }
1340 
1341  EVT ArgVT = TLI.getValueType(DL, ArgTy);
1342  DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1343  << ArgVT.getEVTString() << "\n");
1344  if (!ArgVT.isSimple()) {
1345  DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1346  return false;
1347  }
1348 
1349  switch (ArgVT.getSimpleVT().SimpleTy) {
1350  case MVT::i1:
1351  case MVT::i8:
1352  case MVT::i16:
1353  if (!FormalArg.hasAttribute(Attribute::SExt) &&
1354  !FormalArg.hasAttribute(Attribute::ZExt)) {
1355  // It must be any extend, this shouldn't happen for clang-generated IR
1356  // so just fall back on SelectionDAG.
1357  DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1358  return false;
1359  }
1360 
1361  if (NextGPR32 == GPR32ArgRegs.end()) {
1362  DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1363  return false;
1364  }
1365 
1366  DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1367  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1368 
1369  // Allocating any GPR32 prohibits further use of floating point arguments.
1370  NextFGR32 = FGR32ArgRegs.end();
1371  NextAFGR64 = AFGR64ArgRegs.end();
1372  break;
1373 
1374  case MVT::i32:
1375  if (FormalArg.hasAttribute(Attribute::ZExt)) {
1376  // The O32 ABI does not permit a zero-extended i32.
1377  DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1378  return false;
1379  }
1380 
1381  if (NextGPR32 == GPR32ArgRegs.end()) {
1382  DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1383  return false;
1384  }
1385 
1386  DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1387  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1388 
1389  // Allocating any GPR32 prohibits further use of floating point arguments.
1390  NextFGR32 = FGR32ArgRegs.end();
1391  NextAFGR64 = AFGR64ArgRegs.end();
1392  break;
1393 
1394  case MVT::f32:
1395  if (UnsupportedFPMode) {
1396  DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1397  return false;
1398  }
1399  if (NextFGR32 == FGR32ArgRegs.end()) {
1400  DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1401  return false;
1402  }
1403  DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1404  Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1405  // Allocating an FGR32 also allocates the super-register AFGR64, and
1406  // ABI rules require us to skip the corresponding GPR32.
1407  if (NextGPR32 != GPR32ArgRegs.end())
1408  NextGPR32++;
1409  if (NextAFGR64 != AFGR64ArgRegs.end())
1410  NextAFGR64++;
1411  break;
1412 
1413  case MVT::f64:
1414  if (UnsupportedFPMode) {
1415  DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1416  return false;
1417  }
1418  if (NextAFGR64 == AFGR64ArgRegs.end()) {
1419  DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1420  return false;
1421  }
1422  DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1423  Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1424  // Allocating an FGR32 also allocates the super-register AFGR64, and
1425  // ABI rules require us to skip the corresponding GPR32 pair.
1426  if (NextGPR32 != GPR32ArgRegs.end())
1427  NextGPR32++;
1428  if (NextGPR32 != GPR32ArgRegs.end())
1429  NextGPR32++;
1430  if (NextFGR32 != FGR32ArgRegs.end())
1431  NextFGR32++;
1432  break;
1433 
1434  default:
1435  DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1436  return false;
1437  }
1438  }
1439 
1440  for (const auto &FormalArg : F->args()) {
1441  unsigned ArgNo = FormalArg.getArgNo();
1442  unsigned SrcReg = Allocation[ArgNo].Reg;
1443  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1444  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1445  // Without this, EmitLiveInCopies may eliminate the livein if its only
1446  // use is a bitcast (which isn't turned into an instruction).
1447  unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1448  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1449  TII.get(TargetOpcode::COPY), ResultReg)
1450  .addReg(DstReg, getKillRegState(true));
1451  updateValueMap(&FormalArg, ResultReg);
1452  }
1453 
1454  // Calculate the size of the incoming arguments area.
1455  // We currently reject all the cases where this would be non-zero.
1456  unsigned IncomingArgSizeInBytes = 0;
1457 
1458  // Account for the reserved argument area on ABI's that have one (O32).
1459  // It seems strange to do this on the caller side but it's necessary in
1460  // SelectionDAG's implementation.
1461  IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1462  IncomingArgSizeInBytes);
1463 
1464  MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1465  false);
1466 
1467  return true;
1468 }
1469 
1470 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1471  CallingConv::ID CC = CLI.CallConv;
1472  bool IsTailCall = CLI.IsTailCall;
1473  bool IsVarArg = CLI.IsVarArg;
1474  const Value *Callee = CLI.Callee;
1475  MCSymbol *Symbol = CLI.Symbol;
1476 
1477  // Do not handle FastCC.
1478  if (CC == CallingConv::Fast)
1479  return false;
1480 
1481  // Allow SelectionDAG isel to handle tail calls.
1482  if (IsTailCall)
1483  return false;
1484 
1485  // Let SDISel handle vararg functions.
1486  if (IsVarArg)
1487  return false;
1488 
1489  // FIXME: Only handle *simple* calls for now.
1490  MVT RetVT;
1491  if (CLI.RetTy->isVoidTy())
1492  RetVT = MVT::isVoid;
1493  else if (!isTypeSupported(CLI.RetTy, RetVT))
1494  return false;
1495 
1496  for (auto Flag : CLI.OutFlags)
1497  if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1498  return false;
1499 
1500  // Set up the argument vectors.
1501  SmallVector<MVT, 16> OutVTs;
1502  OutVTs.reserve(CLI.OutVals.size());
1503 
1504  for (auto *Val : CLI.OutVals) {
1505  MVT VT;
1506  if (!isTypeLegal(Val->getType(), VT) &&
1507  !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1508  return false;
1509 
1510  // We don't handle vector parameters yet.
1511  if (VT.isVector() || VT.getSizeInBits() > 64)
1512  return false;
1513 
1514  OutVTs.push_back(VT);
1515  }
1516 
1517  Address Addr;
1518  if (!computeCallAddress(Callee, Addr))
1519  return false;
1520 
1521  // Handle the arguments now that we've gotten them.
1522  unsigned NumBytes;
1523  if (!processCallArgs(CLI, OutVTs, NumBytes))
1524  return false;
1525 
1526  if (!Addr.getGlobalValue())
1527  return false;
1528 
1529  // Issue the call.
1530  unsigned DestAddress;
1531  if (Symbol)
1532  DestAddress = materializeExternalCallSym(Symbol);
1533  else
1534  DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1535  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1536  MachineInstrBuilder MIB =
1537  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1538  Mips::RA).addReg(Mips::T9);
1539 
1540  // Add implicit physical register uses to the call.
1541  for (auto Reg : CLI.OutRegs)
1543 
1544  // Add a register mask with the call-preserved registers.
1545  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1546  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1547 
1548  CLI.Call = MIB;
1549 
1550  // Finish off the call including any return values.
1551  return finishCall(CLI, RetVT, NumBytes);
1552 }
1553 
1554 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1555  switch (II->getIntrinsicID()) {
1556  default:
1557  return false;
1558  case Intrinsic::bswap: {
1559  Type *RetTy = II->getCalledFunction()->getReturnType();
1560 
1561  MVT VT;
1562  if (!isTypeSupported(RetTy, VT))
1563  return false;
1564 
1565  unsigned SrcReg = getRegForValue(II->getOperand(0));
1566  if (SrcReg == 0)
1567  return false;
1568  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1569  if (DestReg == 0)
1570  return false;
1571  if (VT == MVT::i16) {
1572  if (Subtarget->hasMips32r2()) {
1573  emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1574  updateValueMap(II, DestReg);
1575  return true;
1576  } else {
1577  unsigned TempReg[3];
1578  for (int i = 0; i < 3; i++) {
1579  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1580  if (TempReg[i] == 0)
1581  return false;
1582  }
1583  emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1584  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1585  emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1586  emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1587  updateValueMap(II, DestReg);
1588  return true;
1589  }
1590  } else if (VT == MVT::i32) {
1591  if (Subtarget->hasMips32r2()) {
1592  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1593  emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1594  emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1595  updateValueMap(II, DestReg);
1596  return true;
1597  } else {
1598  unsigned TempReg[8];
1599  for (int i = 0; i < 8; i++) {
1600  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1601  if (TempReg[i] == 0)
1602  return false;
1603  }
1604 
1605  emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1606  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1607  emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1608  emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1609 
1610  emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1611  emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1612 
1613  emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1614  emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1615  emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1616  updateValueMap(II, DestReg);
1617  return true;
1618  }
1619  }
1620  return false;
1621  }
1622  case Intrinsic::memcpy:
1623  case Intrinsic::memmove: {
1624  const auto *MTI = cast<MemTransferInst>(II);
1625  // Don't handle volatile.
1626  if (MTI->isVolatile())
1627  return false;
1628  if (!MTI->getLength()->getType()->isIntegerTy(32))
1629  return false;
1630  const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1631  return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1632  }
1633  case Intrinsic::memset: {
1634  const MemSetInst *MSI = cast<MemSetInst>(II);
1635  // Don't handle volatile.
1636  if (MSI->isVolatile())
1637  return false;
1638  if (!MSI->getLength()->getType()->isIntegerTy(32))
1639  return false;
1640  return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1641  }
1642  }
1643  return false;
1644 }
1645 
1646 bool MipsFastISel::selectRet(const Instruction *I) {
1647  const Function &F = *I->getParent()->getParent();
1648  const ReturnInst *Ret = cast<ReturnInst>(I);
1649 
1650  DEBUG(dbgs() << "selectRet\n");
1651 
1652  if (!FuncInfo.CanLowerReturn)
1653  return false;
1654 
1655  // Build a list of return value registers.
1656  SmallVector<unsigned, 4> RetRegs;
1657 
1658  if (Ret->getNumOperands() > 0) {
1660 
1661  // Do not handle FastCC.
1662  if (CC == CallingConv::Fast)
1663  return false;
1664 
1666  GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1667 
1668  // Analyze operands of the call, assigning locations to each operand.
1670  MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1671  I->getContext());
1672  CCAssignFn *RetCC = RetCC_Mips;
1673  CCInfo.AnalyzeReturn(Outs, RetCC);
1674 
1675  // Only handle a single return value for now.
1676  if (ValLocs.size() != 1)
1677  return false;
1678 
1679  CCValAssign &VA = ValLocs[0];
1680  const Value *RV = Ret->getOperand(0);
1681 
1682  // Don't bother handling odd stuff for now.
1683  if ((VA.getLocInfo() != CCValAssign::Full) &&
1684  (VA.getLocInfo() != CCValAssign::BCvt))
1685  return false;
1686 
1687  // Only handle register returns for now.
1688  if (!VA.isRegLoc())
1689  return false;
1690 
1691  unsigned Reg = getRegForValue(RV);
1692  if (Reg == 0)
1693  return false;
1694 
1695  unsigned SrcReg = Reg + VA.getValNo();
1696  unsigned DestReg = VA.getLocReg();
1697  // Avoid a cross-class copy. This is very unlikely.
1698  if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1699  return false;
1700 
1701  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1702  if (!RVEVT.isSimple())
1703  return false;
1704 
1705  if (RVEVT.isVector())
1706  return false;
1707 
1708  MVT RVVT = RVEVT.getSimpleVT();
1709  if (RVVT == MVT::f128)
1710  return false;
1711 
1712  // Do not handle FGR64 returns for now.
1713  if (RVVT == MVT::f64 && UnsupportedFPMode) {
1714  DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1715  return false;
1716  }
1717 
1718  MVT DestVT = VA.getValVT();
1719  // Special handling for extended integers.
1720  if (RVVT != DestVT) {
1721  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1722  return false;
1723 
1724  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1725  bool IsZExt = Outs[0].Flags.isZExt();
1726  SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1727  if (SrcReg == 0)
1728  return false;
1729  }
1730  }
1731 
1732  // Make the copy.
1733  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1734  TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1735 
1736  // Add register to return instruction.
1737  RetRegs.push_back(VA.getLocReg());
1738  }
1739  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1740  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1741  MIB.addReg(RetRegs[i], RegState::Implicit);
1742  return true;
1743 }
1744 
1745 bool MipsFastISel::selectTrunc(const Instruction *I) {
1746  // The high bits for a type smaller than the register size are assumed to be
1747  // undefined.
1748  Value *Op = I->getOperand(0);
1749 
1750  EVT SrcVT, DestVT;
1751  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1752  DestVT = TLI.getValueType(DL, I->getType(), true);
1753 
1754  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1755  return false;
1756  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1757  return false;
1758 
1759  unsigned SrcReg = getRegForValue(Op);
1760  if (!SrcReg)
1761  return false;
1762 
1763  // Because the high bits are undefined, a truncate doesn't generate
1764  // any code.
1765  updateValueMap(I, SrcReg);
1766  return true;
1767 }
1768 
1769 bool MipsFastISel::selectIntExt(const Instruction *I) {
1770  Type *DestTy = I->getType();
1771  Value *Src = I->getOperand(0);
1772  Type *SrcTy = Src->getType();
1773 
1774  bool isZExt = isa<ZExtInst>(I);
1775  unsigned SrcReg = getRegForValue(Src);
1776  if (!SrcReg)
1777  return false;
1778 
1779  EVT SrcEVT, DestEVT;
1780  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1781  DestEVT = TLI.getValueType(DL, DestTy, true);
1782  if (!SrcEVT.isSimple())
1783  return false;
1784  if (!DestEVT.isSimple())
1785  return false;
1786 
1787  MVT SrcVT = SrcEVT.getSimpleVT();
1788  MVT DestVT = DestEVT.getSimpleVT();
1789  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1790 
1791  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1792  return false;
1793  updateValueMap(I, ResultReg);
1794  return true;
1795 }
1796 
1797 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1798  unsigned DestReg) {
1799  unsigned ShiftAmt;
1800  switch (SrcVT.SimpleTy) {
1801  default:
1802  return false;
1803  case MVT::i8:
1804  ShiftAmt = 24;
1805  break;
1806  case MVT::i16:
1807  ShiftAmt = 16;
1808  break;
1809  }
1810  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1811  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1812  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1813  return true;
1814 }
1815 
1816 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1817  unsigned DestReg) {
1818  switch (SrcVT.SimpleTy) {
1819  default:
1820  return false;
1821  case MVT::i8:
1822  emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1823  break;
1824  case MVT::i16:
1825  emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1826  break;
1827  }
1828  return true;
1829 }
1830 
1831 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1832  unsigned DestReg) {
1833  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1834  return false;
1835  if (Subtarget->hasMips32r2())
1836  return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1837  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1838 }
1839 
1840 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1841  unsigned DestReg) {
1842  int64_t Imm;
1843 
1844  switch (SrcVT.SimpleTy) {
1845  default:
1846  return false;
1847  case MVT::i1:
1848  Imm = 1;
1849  break;
1850  case MVT::i8:
1851  Imm = 0xff;
1852  break;
1853  case MVT::i16:
1854  Imm = 0xffff;
1855  break;
1856  }
1857 
1858  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1859  return true;
1860 }
1861 
1862 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1863  unsigned DestReg, bool IsZExt) {
1864  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1865  // DestVT are odd things, so test to make sure that they are both types we can
1866  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1867  // bail out to SelectionDAG.
1868  if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1869  ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1870  return false;
1871  if (IsZExt)
1872  return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1873  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1874 }
1875 
1876 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1877  bool isZExt) {
1878  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1879  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1880  return Success ? DestReg : 0;
1881 }
1882 
1883 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1884  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1885  if (!DestEVT.isSimple())
1886  return false;
1887 
1888  MVT DestVT = DestEVT.getSimpleVT();
1889  if (DestVT != MVT::i32)
1890  return false;
1891 
1892  unsigned DivOpc;
1893  switch (ISDOpcode) {
1894  default:
1895  return false;
1896  case ISD::SDIV:
1897  case ISD::SREM:
1898  DivOpc = Mips::SDIV;
1899  break;
1900  case ISD::UDIV:
1901  case ISD::UREM:
1902  DivOpc = Mips::UDIV;
1903  break;
1904  }
1905 
1906  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1907  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1908  if (!Src0Reg || !Src1Reg)
1909  return false;
1910 
1911  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1912  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1913 
1914  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1915  if (!ResultReg)
1916  return false;
1917 
1918  unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1919  ? Mips::MFHI
1920  : Mips::MFLO;
1921  emitInst(MFOpc, ResultReg);
1922 
1923  updateValueMap(I, ResultReg);
1924  return true;
1925 }
1926 
1927 bool MipsFastISel::selectShift(const Instruction *I) {
1928  MVT RetVT;
1929 
1930  if (!isTypeSupported(I->getType(), RetVT))
1931  return false;
1932 
1933  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1934  if (!ResultReg)
1935  return false;
1936 
1937  unsigned Opcode = I->getOpcode();
1938  const Value *Op0 = I->getOperand(0);
1939  unsigned Op0Reg = getRegForValue(Op0);
1940  if (!Op0Reg)
1941  return false;
1942 
1943  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1944  if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1945  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1946  if (!TempReg)
1947  return false;
1948 
1949  MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1950  bool IsZExt = Opcode == Instruction::LShr;
1951  if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1952  return false;
1953 
1954  Op0Reg = TempReg;
1955  }
1956 
1957  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1958  uint64_t ShiftVal = C->getZExtValue();
1959 
1960  switch (Opcode) {
1961  default:
1962  llvm_unreachable("Unexpected instruction.");
1963  case Instruction::Shl:
1964  Opcode = Mips::SLL;
1965  break;
1966  case Instruction::AShr:
1967  Opcode = Mips::SRA;
1968  break;
1969  case Instruction::LShr:
1970  Opcode = Mips::SRL;
1971  break;
1972  }
1973 
1974  emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1975  updateValueMap(I, ResultReg);
1976  return true;
1977  }
1978 
1979  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1980  if (!Op1Reg)
1981  return false;
1982 
1983  switch (Opcode) {
1984  default:
1985  llvm_unreachable("Unexpected instruction.");
1986  case Instruction::Shl:
1987  Opcode = Mips::SLLV;
1988  break;
1989  case Instruction::AShr:
1990  Opcode = Mips::SRAV;
1991  break;
1992  case Instruction::LShr:
1993  Opcode = Mips::SRLV;
1994  break;
1995  }
1996 
1997  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1998  updateValueMap(I, ResultReg);
1999  return true;
2000 }
2001 
2002 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2003  switch (I->getOpcode()) {
2004  default:
2005  break;
2006  case Instruction::Load:
2007  return selectLoad(I);
2008  case Instruction::Store:
2009  return selectStore(I);
2010  case Instruction::SDiv:
2011  if (!selectBinaryOp(I, ISD::SDIV))
2012  return selectDivRem(I, ISD::SDIV);
2013  return true;
2014  case Instruction::UDiv:
2015  if (!selectBinaryOp(I, ISD::UDIV))
2016  return selectDivRem(I, ISD::UDIV);
2017  return true;
2018  case Instruction::SRem:
2019  if (!selectBinaryOp(I, ISD::SREM))
2020  return selectDivRem(I, ISD::SREM);
2021  return true;
2022  case Instruction::URem:
2023  if (!selectBinaryOp(I, ISD::UREM))
2024  return selectDivRem(I, ISD::UREM);
2025  return true;
2026  case Instruction::Shl:
2027  case Instruction::LShr:
2028  case Instruction::AShr:
2029  return selectShift(I);
2030  case Instruction::And:
2031  case Instruction::Or:
2032  case Instruction::Xor:
2033  return selectLogicalOp(I);
2034  case Instruction::Br:
2035  return selectBranch(I);
2036  case Instruction::Ret:
2037  return selectRet(I);
2038  case Instruction::Trunc:
2039  return selectTrunc(I);
2040  case Instruction::ZExt:
2041  case Instruction::SExt:
2042  return selectIntExt(I);
2043  case Instruction::FPTrunc:
2044  return selectFPTrunc(I);
2045  case Instruction::FPExt:
2046  return selectFPExt(I);
2047  case Instruction::FPToSI:
2048  return selectFPToInt(I, /*isSigned*/ true);
2049  case Instruction::FPToUI:
2050  return selectFPToInt(I, /*isSigned*/ false);
2051  case Instruction::ICmp:
2052  case Instruction::FCmp:
2053  return selectCmp(I);
2054  case Instruction::Select:
2055  return selectSelect(I);
2056  }
2057  return false;
2058 }
2059 
2060 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2061  bool IsUnsigned) {
2062  unsigned VReg = getRegForValue(V);
2063  if (VReg == 0)
2064  return 0;
2065  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2066  if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2067  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2068  if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2069  return 0;
2070  VReg = TempReg;
2071  }
2072  return VReg;
2073 }
2074 
2075 void MipsFastISel::simplifyAddress(Address &Addr) {
2076  if (!isInt<16>(Addr.getOffset())) {
2077  unsigned TempReg =
2078  materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2079  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2080  emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2081  Addr.setReg(DestReg);
2082  Addr.setOffset(0);
2083  }
2084 }
2085 
2086 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2087  const TargetRegisterClass *RC,
2088  unsigned Op0, bool Op0IsKill,
2089  unsigned Op1, bool Op1IsKill) {
2090  // We treat the MUL instruction in a special way because it clobbers
2091  // the HI0 & LO0 registers. The TableGen definition of this instruction can
2092  // mark these registers only as implicitly defined. As a result, the
2093  // register allocator runs out of registers when this instruction is
2094  // followed by another instruction that defines the same registers too.
2095  // We can fix this by explicitly marking those registers as dead.
2096  if (MachineInstOpcode == Mips::MUL) {
2097  unsigned ResultReg = createResultReg(RC);
2098  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2099  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2100  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2101  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2102  .addReg(Op0, getKillRegState(Op0IsKill))
2103  .addReg(Op1, getKillRegState(Op1IsKill))
2106  return ResultReg;
2107  }
2108 
2109  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2110  Op1IsKill);
2111 }
2112 
2113 namespace llvm {
2114 
2116  const TargetLibraryInfo *libInfo) {
2117  return new MipsFastISel(funcInfo, libInfo);
2118 }
2119 
2120 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:158
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
uint64_t CallInst * C
Return a value (possibly void), from a function.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:843
bool hasLocalLinkage() const
Definition: GlobalValue.h:427
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
bool isVector() const
Return true if this is a vector value type.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
const MipsInstrInfo * getInstrInfo() const override
const Value * getTrueValue() const
unsigned less or equal
Definition: InstrTypes.h:879
unsigned less than
Definition: InstrTypes.h:878
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:859
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:728
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:869
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:677
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
void reserve(size_type N)
Definition: SmallVector.h:380
Value * getLength() const
op_iterator op_begin()
Definition: User.h:214
bool isMemLoc() const
bool needsCustom() const
SI optimize exec mask operations pre RA
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:491
A description of a memory reference used in the backend.
This class represents the LLVM &#39;select&#39; instruction.
const HexagonInstrInfo * TII
unsigned getNumArgOperands() const
Return the number of call arguments.
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:97
Class to represent struct types.
Definition: DerivedTypes.h:201
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isUnsigned() const
Determine if this instruction is using an unsigned comparison.
Definition: InstrTypes.h:1000
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:860
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:862
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:120
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
amdgpu Simplify well known AMD library false Value * Callee
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Value * getOperand(unsigned i) const
Definition: User.h:154
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
Local Stack Slot Allocation
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:147
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV)...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:150
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:149
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
op_iterator op_end()
Definition: User.h:216
bool hasInternalLinkage() const
Definition: GlobalValue.h:425
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:144
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:853
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:120
const MachineInstrBuilder & addFrameIndex(int Idx) const
const Value * getCondition() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
Extended Value Type.
Definition: ValueTypes.h:34
static bool isAtomic(Instruction *I)
bool isVolatile() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:880
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:294
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:51
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:857
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
unsigned getNumOperands() const
Definition: User.h:176
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
iterator end() const
Definition: ArrayRef.h:138
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:882
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:1846
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
signed less or equal
Definition: InstrTypes.h:883
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
This file defines the FastISel class.
const MipsTargetLowering * getTargetLowering() const override
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
const Value * getFalseValue() const
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Function * getCalledFunction() const
Return the function called, or null if this is an indirect function invocation.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:927
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:513
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:656
unsigned getLocMemOffset() const
unsigned greater or equal
Definition: InstrTypes.h:877
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:338
bool isRegLoc() const
const unsigned Kind
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void GetReturnInfo(Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:856
LLVM Value Representation.
Definition: Value.h:73
bool useSoftFloat() const
#define DEBUG(X)
Definition: Debug.h:118
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:238
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned greater than
Definition: InstrTypes.h:876
APInt bitcastToAPInt() const
Definition: APFloat.h:1094
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:858
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
bool isFP64bit() const
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void convertToReg(unsigned RegNo)
iterator_range< arg_iterator > args()
Definition: Function.h:621
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:215
signed greater or equal
Definition: InstrTypes.h:881
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:218
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
an instruction to allocate memory on the stack
Definition: Instructions.h:60
gep_type_iterator gep_type_begin(const User *GEP)