LLVM  6.0.0svn
Classes | Public Types | Public Member Functions | List of all members
llvm::TargetLowering Class Reference

This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively. More...

#include "llvm/CodeGen/TargetLowering.h"

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Classes

struct  AsmOperandInfo
 This contains information for each constraint that we are lowering. More...
 
struct  CallLoweringInfo
 This structure contains all information that is necessary for lowering calls. More...
 
struct  DAGCombinerInfo
 
struct  TargetLoweringOpt
 A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetLowering to its clients that want to combine. More...
 

Public Types

enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
using AsmOperandInfoVector = std::vector< AsmOperandInfo >
 
- Public Types inherited from llvm::TargetLoweringBase
enum  LegalizeAction : uint8_t {
  Legal, Promote, Expand, LibCall,
  Custom
}
 This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...
 
enum  LegalizeTypeAction : uint8_t {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector,
  TypePromoteFloat
}
 This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
enum  AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg }
 Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...
 
enum  MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom }
 Enum that specifies when a multiplication should be expanded. More...
 
enum  ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 }
 Reciprocal estimate status values used by the functions below. More...
 
using LegalizeKind = std::pair< LegalizeTypeAction, EVT >
 LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More...
 
using ArgListTy = std::vector< ArgListEntry >
 

Public Member Functions

 TargetLowering (const TargetLowering &)=delete
 
TargetLoweringoperator= (const TargetLowering &)=delete
 
 TargetLowering (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF. More...
 
bool isPositionIndependent () const
 
virtual bool getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More...
 
virtual bool getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More...
 
virtual unsigned getJumpTableEncoding () const
 Return the entry encoding for a jump table in the current function. More...
 
virtual const MCExprLowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
 
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
 Returns relocation base for the given PIC jumptable. More...
 
virtual const MCExprgetPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
 This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More...
 
virtual bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const
 Return true if folding a constant offset with the given GlobalAddress is legal. More...
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 Check whether a given call node is in tail position within its function. More...
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
 Soften the operands of a comparison. More...
 
std::pair< SDValue, SDValuemakeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
 Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. More...
 
bool ShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
 Check to see if the specified operand of the specified instruction is a constant integer. More...
 
virtual bool targetShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
 
bool ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const
 Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. More...
 
bool SimplifyDemandedBits (SDNode *User, unsigned OpIdx, const APInt &Demanded, DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const
 Helper for SimplifyDemandedBits that can simplify an operation with multiple uses. More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
 Look at Op. More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) const
 Helper wrapper around SimplifyDemandedBits. More...
 
virtual void computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
 Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. More...
 
virtual void computeKnownBitsForFrameIndex (const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
 Determine which of the bits of FrameIndex FIOp are known to be 0. More...
 
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
 This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. More...
 
bool isConstTrueVal (const SDNode *N) const
 Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More...
 
bool isConstFalseVal (const SDNode *N) const
 Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More...
 
SDValue getConstTrueVal (SelectionDAG &DAG, EVT VT, const SDLoc &DL) const
 Return a constant of type VT that contains a true value that respects getBooleanContents() More...
 
bool isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool Signed) const
 Return if N is a True value when extended to VT. More...
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
 Try to simplify a setcc built with the specified operands and cc. More...
 
virtual SDValue unwrapAddress (SDValue N) const
 
virtual bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
 Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More...
 
virtual SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
 This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More...
 
virtual bool isDesirableToCommuteWithShift (const SDNode *N) const
 Return true if it is profitable to move a following shift through this. More...
 
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate (ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
 
virtual bool isTypeDesirableForOp (unsigned, EVT VT) const
 Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More...
 
virtual bool isDesirableToTransformToIntegerOp (unsigned, EVT) const
 Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More...
 
virtual bool IsDesirableToPromoteOp (SDValue, EVT &) const
 This method query the target whether it is beneficial for dag combiner to promote the specified node. More...
 
virtual bool supportSwiftError () const
 Return true if the target supports swifterror attribute. More...
 
virtual bool supportSplitCSR (MachineFunction *MF) const
 Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies. More...
 
virtual void initializeSplitCSR (MachineBasicBlock *Entry) const
 Perform necessary initialization to handle a subset of CSRs explicitly via copies. More...
 
virtual void insertCopiesSplitCSR (MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const
 Insert explicit copies in entry and exit blocks. More...
 
virtual SDValue LowerFormalArguments (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
 This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. More...
 
std::pair< SDValue, SDValueLowerCallTo (CallLoweringInfo &CLI) const
 This function lowers an abstract call to a function into an actual call. More...
 
virtual SDValue LowerCall (CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
 This hook must be implemented to lower calls into the specified DAG. More...
 
virtual void HandleByVal (CCState *, unsigned &, unsigned) const
 Target-specific cleanup for formal ByVal parameters. More...
 
virtual bool CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
 This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. More...
 
virtual SDValue LowerReturn (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
 This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. More...
 
virtual bool isUsedByReturnOnly (SDNode *, SDValue &) const
 Return true if result of the specified node is used by a return node only. More...
 
virtual bool mayBeEmittedAsTailCall (const CallInst *) const
 Return true if the target may be able emit the call instruction as a tail call. More...
 
virtual const chargetClearCacheBuiltinName () const
 Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call. More...
 
virtual unsigned getRegisterByName (const char *RegName, EVT VT, SelectionDAG &DAG) const
 Return the register ID of the name passed in. More...
 
virtual EVT getTypeForExtReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const
 Return the type that should be used to zero or sign extend a zeroext/signext integer return value. More...
 
virtual bool functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
 For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. More...
 
virtual const MCPhysReggetScratchRegisters (CallingConv::ID CC) const
 Returns a 0 terminated array of registers that can be safely used as scratch registers. More...
 
virtual SDValue prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
 This callback is used to prepare for a volatile or atomic load. More...
 
virtual MachineMemOperand::Flags getMMOFlags (const Instruction &I) const
 This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. More...
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More...
 
virtual SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const
 This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. More...
 
virtual void ReplaceNodeResults (SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
 This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. More...
 
virtual const chargetTargetNodeName (unsigned Opcode) const
 This method returns the name of a target specific DAG node. More...
 
virtual FastISelcreateFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const
 This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More...
 
bool verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const
 
virtual bool ExpandInlineAsm (CallInst *) const
 This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More...
 
virtual AsmOperandInfoVector ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
 Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More...
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 Examine constraint type and operand type and determine a weight value. More...
 
virtual ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const
 Examine constraint string and operand type and determine a weight value. More...
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
 Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More...
 
virtual ConstraintType getConstraintType (StringRef Constraint) const
 Given a constraint, return the type of constraint it is for this target. More...
 
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
 Given a physical register constraint (e.g. More...
 
virtual unsigned getInlineAsmMemConstraint (StringRef ConstraintCode) const
 
virtual const charLowerXConstraint (EVT ConstraintVT) const
 Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More...
 
virtual void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
 Lower the specified operand into the Ops vector. More...
 
SDValue BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode *> *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...
 
SDValue BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode *> *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...
 
virtual SDValue BuildSDIVPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode *> *Created) const
 Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. More...
 
virtual unsigned combineRepeatedFPDivisors () const
 Indicate whether this target prefers to combine FDIVs with the same divisor. More...
 
virtual SDValue getSqrtEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
 Hooks for building estimates in place of slower divisions and square roots. More...
 
virtual SDValue getRecipEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
 Return a reciprocal estimate value for the input operand. More...
 
bool expandMUL_LOHI (unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result. More...
 
bool expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 Expand a MUL into two nodes. More...
 
bool expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
 Expand float(f32) to SINT(i64) conversion. More...
 
SDValue scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const
 Turn load of vector type into a load of the individual elements. More...
 
SDValue scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const
 
std::pair< SDValue, SDValueexpandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const
 Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors. More...
 
SDValue expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const
 Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors. More...
 
SDValue IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const
 Increments memory address Addr according to the type of the value DataVT that should be stored. More...
 
SDValue getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Idx) const
 Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base address of VecPtr. More...
 
virtual MachineBasicBlockEmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const
 This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More...
 
virtual void AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const
 This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More...
 
virtual bool useLoadStackGuardNode () const
 If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More...
 
virtual SDValue LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
 Lower TLS global address SDNode for target independent emulated TLS model. More...
 
SDValue lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const
 
- Public Member Functions inherited from llvm::TargetLoweringBase
virtual void markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const
 
 TargetLoweringBase (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF. More...
 
 TargetLoweringBase (const TargetLoweringBase &)=delete
 
TargetLoweringBaseoperator= (const TargetLoweringBase &)=delete
 
virtual ~TargetLoweringBase ()=default
 
const TargetMachinegetTargetMachine () const
 
virtual bool useSoftFloat () const
 
MVT getPointerTy (const DataLayout &DL, uint32_t AS=0) const
 Return the pointer type for the given address space, defaults to the pointer type from the data layout. More...
 
MVT getFrameIndexTy (const DataLayout &DL) const
 Return the type for frame index, which is determined by the alloca address space specified through the data layout. More...
 
virtual MVT getFenceOperandTy (const DataLayout &DL) const
 Return the type for operands of fence. More...
 
virtual MVT getScalarShiftAmountTy (const DataLayout &, EVT) const
 EVT is not used in-tree, but is used by out-of-tree target. More...
 
EVT getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const
 
virtual MVT getVectorIdxTy (const DataLayout &DL) const
 Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction (EVT VT) const
 Return the preferred vector type legalization action. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
virtual bool isIntDivCheap (EVT VT, AttributeList Attr) const
 Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More...
 
virtual bool hasStandaloneRem (EVT VT) const
 Return true if the target can handle a standalone remainder operation. More...
 
virtual bool isFsqrtCheap (SDValue X, SelectionDAG &DAG) const
 Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More...
 
int getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
 Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More...
 
int getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
 Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More...
 
int getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
 Return the refinement step count for a square root of the given type based on the function's attributes. More...
 
int getDivRefinementSteps (EVT VT, MachineFunction &MF) const
 Return the refinement step count for a division of the given type based on the function's attributes. More...
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths () const
 Returns map of slow types for division or remainder with corresponding fast types. More...
 
bool isJumpExpensive () const
 Return true if Flow Control is an expensive operation that should be avoided. More...
 
bool isPredictableSelectExpensive () const
 Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More...
 
virtual BranchProbability getPredictableBranchThreshold () const
 If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More...
 
virtual bool isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT) const
 Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More...
 
virtual bool isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT) const
 Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) More...
 
virtual bool storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
 Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More...
 
virtual bool mergeStoresAfterLegalization () const
 Allow store merging after legalization in addition to before legalization. More...
 
virtual bool canMergeStoresTo (unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
 Returns if it's reasonable to merge stores to MemVT size. More...
 
virtual bool isCheapToSpeculateCttz () const
 Return true if it is cheap to speculate a call to intrinsic cttz. More...
 
virtual bool isCheapToSpeculateCtlz () const
 Return true if it is cheap to speculate a call to intrinsic ctlz. More...
 
virtual bool isCtlzFast () const
 Return true if ctlz instruction is fast. More...
 
virtual bool hasBitPreservingFPLogic (EVT VT) const
 Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More...
 
virtual bool isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
 Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More...
 
virtual bool isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
 Return if the target supports combining a chain like: More...
 
virtual bool convertSetCCLogicToBitwiseLogic (EVT VT) const
 Use bitwise logic to make pairs of compares more efficient. More...
 
virtual MVT hasFastEqualityCompare (unsigned NumBits) const
 Return the preferred operand type if the target has a quick way to compare integer values of the given size. More...
 
virtual bool hasAndNotCompare (SDValue Y) const
 Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More...
 
virtual bool hasAndNot (SDValue X) const
 Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More...
 
bool enableExtLdPromotion () const
 Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More...
 
virtual bool canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const
 Return true if the target can combine store(extractelement VectorTy, Idx). More...
 
bool hasFloatingPointExceptions () const
 Return true if target supports floating point exceptions. More...
 
virtual bool enableAggressiveFMAFusion (EVT VT) const
 Return true if target always beneficiates from combining into FMA for a given value type. More...
 
virtual EVT getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
 Return the ValueType of the result of SETCC operations. More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 Return the ValueType for comparison libcalls. More...
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More...
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 Some scheduler, e.g. More...
 
virtual const TargetRegisterClassgetRegClassFor (MVT VT) const
 Return the register class that should be used for the specified value type. More...
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 Return the 'representative' register class for the specified value type. More...
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 Return the cost of the 'representative' register class for the specified value type. More...
 
bool isTypeLegal (EVT VT) const
 Return true if the target has native support for the specified value type. More...
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More...
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Vector types are broken down into some number of legal first class types. More...
 
virtual unsigned getVectorTypeBreakdownForCallingConv (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More...
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const
 Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More...
 
virtual bool isFPImmLegal (const APFloat &, EVT) const
 Returns true if the target can instruction select the specified FP immediate natively. More...
 
virtual bool isShuffleMaskLegal (ArrayRef< int >, EVT) const
 Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More...
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 Returns true if the operation can trap for the value type. More...
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 Similar to isShuffleMaskLegal. More...
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering. More...
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal using promotion. More...
 
bool isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More...
 
bool isOperationCustom (unsigned Op, EVT VT) const
 Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More...
 
bool areJTsAllowed (const Function *Fn) const
 Return true if lowering to a jump table is allowed. More...
 
bool rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
 Check whether the range [Low,High] fits in a machine word. More...
 
bool isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
 Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. More...
 
bool isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
 Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. More...
 
bool isOperationExpand (unsigned Op, EVT VT) const
 Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More...
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal on this target. More...
 
bool isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal or custom on this target. More...
 
LegalizeAction getTruncStoreAction (EVT ValVT, EVT MemVT) const
 Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation is legal on this target. More...
 
bool isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation has solution on this target. More...
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 If the action for this operation is to promote, this method returns the ValueType to promote to. More...
 
EVT getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the EVT corresponding to this LLVM type. More...
 
MVT getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
virtual unsigned getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
 Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 Return the number of registers that this ValueType will eventually require. More...
 
virtual MVT getRegisterTypeForCallingConv (MVT VT) const
 Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More...
 
virtual MVT getRegisterTypeForCallingConv (LLVMContext &Context, EVT VT) const
 
virtual unsigned getNumRegistersForCallingConv (LLVMContext &Context, EVT VT) const
 Certain targets require unusual breakdowns of certain types. More...
 
virtual unsigned getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const
 Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type. More...
 
virtual bool ShouldShrinkFPConstant (EVT) const
 If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More...
 
virtual bool shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
 
bool hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
 When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More...
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 If true, the target has custom DAG combine transformations that it can perform for the specified node. More...
 
unsigned getGatherAllAliasesMaxDepth () const
 
virtual unsigned getVaListSizeInBits (const DataLayout &DL) const
 Returns the size of the platform's va_list object. More...
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxExpandSizeMemcmp (bool OptSize) const
 Get maximum # of load operations permitted for memcmp. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
 Determine if the target supports unaligned memory accesses. More...
 
bool allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
 Return true if the target supports a memory access of this type for the given address space and alignment. More...
 
virtual EVT getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
 Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More...
 
virtual bool isSafeMemOpType (MVT) const
 Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More...
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
unsigned getMinimumJumpTableEntries () const
 Return lower limit for number of blocks in a jump table. More...
 
unsigned getMinimumJumpTableDensity (bool OptForSize) const
 Return lower limit of the density in a jump table. More...
 
unsigned getMaximumJumpTableSize () const
 Return upper limit for number of entries in a jump table. More...
 
virtual bool isJumpTableRelative () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
virtual unsigned getExceptionPointerRegister (const Constant *PersonalityFn) const
 If a physical register, this returns the register that receives the exception address on entry to an EH pad. More...
 
virtual unsigned getExceptionSelectorRegister (const Constant *PersonalityFn) const
 If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More...
 
virtual bool needsFixedCatchObjects () const
 
unsigned getJumpBufSize () const
 Returns the target's jmp_buf size in bytes (if never set, the default is 200) More...
 
unsigned getJumpBufAlignment () const
 Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More...
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
virtual unsigned getPrefLoopAlignment (MachineLoop *ML=nullptr) const
 Return the preferred loop alignment. More...
 
virtual ValuegetIRStackGuard (IRBuilder<> &IRB) const
 If the target has a standard location for the stack protector guard, returns the address of that location. More...
 
virtual void insertSSPDeclarations (Module &M) const
 Inserts necessary declarations for SSP (stack protection) purpose. More...
 
virtual ValuegetSDagStackGuard (const Module &M) const
 Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More...
 
virtual ValuegetSSPStackGuardCheck (const Module &M) const
 If the target has a standard stack protection check function that performs validation and error handling, returns the function. More...
 
virtual ValuegetSafeStackPointerLocation (IRBuilder<> &IRB) const
 Returns the target-specific address of the unsafe stack pointer. More...
 
virtual StringRef getStackProbeSymbolName (MachineFunction &MF) const
 Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More...
 
virtual bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
virtual bool isCheapAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More...
 
virtual bool shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const
 Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More...
 
virtual void emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const
 
virtual bool shouldExpandAtomicStoreInIR (StoreInst *SI) const
 Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More...
 
virtual bool shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
 Returns true if arguments should be sign-extended in lib calls. More...
 
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR (LoadInst *LI) const
 Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More...
 
virtual bool shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const
 Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a load-linked/store-conditional sequence (through emitLoadLinked() and emitStoreConditional()). More...
 
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR (AtomicRMWInst *) const
 Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More...
 
virtual LoadInstlowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
 On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More...
 
virtual ISD::NodeType getExtendForAtomicOps () const
 Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More...
 
virtual bool shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
 Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More...
 
virtual bool convertSelectOfConstantsToMath (EVT VT) const
 Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More...
 
virtual bool getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
 CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More...
 
virtual bool isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
 Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...
 
virtual int getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool isLegalICmpImmediate (int64_t) const
 Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...
 
virtual bool isLegalAddImmediate (int64_t) const
 Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More...
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More...
 
virtual bool isCommutativeBinOp (unsigned Opcode) const
 Returns true if the opcode is a commutative binary operation. More...
 
virtual bool isTruncateFree (Type *FromTy, Type *ToTy) const
 Return true if it's free to truncate a value of type FromTy to type ToTy. More...
 
virtual bool allowTruncateForTailCall (Type *FromTy, Type *ToTy) const
 Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More...
 
virtual bool isTruncateFree (EVT FromVT, EVT ToVT) const
 
virtual bool isProfitableToHoist (Instruction *I) const
 
bool isExtFree (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
bool isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const
 Return true if Load and Ext can form an ExtLoad. More...
 
virtual bool isZExtFree (Type *FromTy, Type *ToTy) const
 Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More...
 
virtual bool isZExtFree (EVT FromTy, EVT ToTy) const
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More...
 
virtual unsigned getMaxSupportedInterleaveFactor () const
 Get the maximum supported factor for interleaved memory accesses. More...
 
virtual bool lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
 Lower an interleaved load to target specific intrinsics. More...
 
virtual bool lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
 Lower an interleaved store to target specific intrinsics. More...
 
virtual bool isZExtFree (SDValue Val, EVT VT2) const
 Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More...
 
virtual bool isFPExtFree (EVT DestVT, EVT SrcVT) const
 Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More...
 
virtual bool isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const
 Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More...
 
virtual bool isVectorLoadExtDesirable (SDValue ExtVal) const
 Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More...
 
virtual bool isFNegFree (EVT VT) const
 Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFAbsFree (EVT VT) const
 Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFMAFasterThanFMulAndFAdd (EVT) const
 Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More...
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 Return true if it's profitable to narrow operations of type VT1 to VT2. More...
 
virtual bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
 Return true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
virtual bool isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const
 Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. More...
 
virtual bool aggressivelyPreferBuildVectorSources (EVT VecVT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const chargetLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 Override the default CondCode to be used to test the result of the comparison libcall against zero. More...
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 Get the CondCode that's to be used to test the result of the comparison libcall against zero. More...
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
virtual void finalizeLowering (MachineFunction &MF) const
 Execute target specific actions to finalize target lowering. More...
 
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< int, MVTgetTypeLegalizationCost (const DataLayout &DL, Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 
unsigned getMaxAtomicSizeInBitsSupported () const
 Returns the maximum atomic operation size (in bits) supported by the backend. More...
 
unsigned getMinCmpXchgSizeInBits () const
 Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More...
 
virtual bool shouldInsertFencesForAtomic (const Instruction *I) const
 Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More...
 
virtual ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
 Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More...
 
virtual ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
 Perform a store-conditional operation to Addr. More...
 
virtual InstructionemitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
 Inserts in the IR a target-specific intrinsic specifying a fence. More...
 
virtual InstructionemitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
 

Additional Inherited Members

- Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType getExtendForContent (BooleanContent Content)
 
- Protected Member Functions inherited from llvm::TargetLoweringBase
void initActions ()
 Initialize all of the actions to default values. More...
 
ValuegetDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const
 
void setBooleanContents (BooleanContent Ty)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanVectorContents (BooleanContent Ty)
 Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More...
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More...
 
void setUseUnderscoreLongJmp (bool Val)
 Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More...
 
void setMinimumJumpTableEntries (unsigned Val)
 Indicate the minimum number of blocks to generate jump tables. More...
 
void setMaximumJumpTableSize (unsigned)
 Indicate the maximum number of entries in jump tables. More...
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More...
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 Tells the code generator that the target has BitExtract instructions. More...
 
void setJumpIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More...
 
void setHasFloatingPointExceptions (bool FPExceptions=true)
 Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More...
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 Add the specified register class as an available regclass for the specified value type. More...
 
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
 Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More...
 
void computeRegisterProperties (const TargetRegisterInfo *TRI)
 Once all of the register classes are added, this allows us to compute derived properties we expose. More...
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 Indicate that the specified operation does not work with the specified type and indicate what to do about it. More...
 
void setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More...
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More...
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More...
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More...
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More...
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More...
 
void setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 Convenience method to set an operation to Promote and specify the type in a single call. More...
 
void setTargetDAGCombine (ISD::NodeType NT)
 Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More...
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More...
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 Set the target's preferred function alignment. More...
 
void setPrefLoopAlignment (unsigned Align)
 Set the target's preferred loop alignment. More...
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
 Set the maximum atomic operation size supported by the backend. More...
 
void setMinCmpXchgSizeInBits (unsigned SizeInBits)
 
virtual bool isExtFreeImpl (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
bool isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
 Return true if the value types that can be represented by the specified register class are all legal. More...
 
MachineBasicBlockemitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
 Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More...
 
- Protected Attributes inherited from llvm::TargetLoweringBase
ValueTypeActionImpl ValueTypeActions
 
unsigned GatherAllAliasesMaxDepth
 Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More...
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More...
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More...
 
unsigned MaxLoadsPerMemcmp
 
unsigned MaxLoadsPerMemcmpOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute. More...
 
bool PredictableSelectIsExpensive
 Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More...
 
bool EnableExtLdPromotion
 

Detailed Description

This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively.

This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.

Definition at line 2508 of file TargetLowering.h.

Member Typedef Documentation

◆ AsmOperandInfoVector

Definition at line 3257 of file TargetLowering.h.

Member Enumeration Documentation

◆ ConstraintType

Enumerator
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 3201 of file TargetLowering.h.

◆ ConstraintWeight

Enumerator
CW_Invalid 
CW_Okay 
CW_Good 
CW_Better 
CW_Best 
CW_SpecificReg 
CW_Register 
CW_Memory 
CW_Constant 
CW_Default 

Definition at line 3209 of file TargetLowering.h.

Constructor & Destructor Documentation

◆ TargetLowering() [1/2]

llvm::TargetLowering::TargetLowering ( const TargetLowering )
delete

◆ TargetLowering() [2/2]

TargetLowering::TargetLowering ( const TargetMachine TM)
explicit

NOTE: The TargetMachine owns TLOF.

Definition at line 40 of file TargetLowering.cpp.

Member Function Documentation

◆ AdjustInstrPostInstrSelection()

void TargetLowering::AdjustInstrPostInstrSelection ( MachineInstr MI,
SDNode Node 
) const
virtual

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 290 of file SelectionDAGISel.cpp.

References assert(), and llvm::MachineInstr::hasPostISelHook().

Referenced by llvm::InstrEmitter::EmitDbgValue().

◆ BuildSDIV()

SDValue TargetLowering::BuildSDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode *> *  Created 
) const

◆ BuildSDIVPow2()

SDValue TargetLowering::BuildSDIVPow2 ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
std::vector< SDNode *> *  Created 
) const
virtual

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.

If the target returns an empty SDValue, LLVM assumes SDIV is expensive and replaces it with a series of other integer operations.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 2963 of file TargetLowering.cpp.

References llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), and llvm::TargetLoweringBase::isIntDivCheap().

Referenced by combineShuffleOfSplat().

◆ BuildUDIV()

SDValue TargetLowering::BuildUDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode *> *  Created 
) const

◆ CanLowerReturn()

virtual bool llvm::TargetLowering::CanLowerReturn ( CallingConv::ID  ,
MachineFunction ,
bool  ,
const SmallVectorImpl< ISD::OutputArg > &  ,
LLVMContext  
) const
inlinevirtual

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers.

If false is returned, an sret-demotion is performed.

Reimplemented in llvm::SystemZTargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.

Definition at line 3040 of file TargetLowering.h.

Referenced by llvm::FastISel::lowerCallTo().

◆ combineRepeatedFPDivisors()

virtual unsigned llvm::TargetLowering::combineRepeatedFPDivisors ( ) const
inlinevirtual

Indicate whether this target prefers to combine FDIVs with the same divisor.

If the transform should never be done, return zero. If the transform should be done, return the minimum number of divisor uses that must exist.

Reimplemented in llvm::NVPTXTargetLowering.

Definition at line 3342 of file TargetLowering.h.

Referenced by isFMulNegTwo().

◆ ComputeConstraintToUse()

void TargetLowering::ComputeConstraintToUse ( AsmOperandInfo OpInfo,
SDValue  Op,
SelectionDAG DAG = nullptr 
) const
virtual

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

Definition at line 2898 of file TargetLowering.cpp.

References assert(), llvm::TargetLowering::AsmOperandInfo::CallOperandVal, ChooseConstraint(), llvm::InlineAsm::ConstraintInfo::Codes, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintType, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, getConstraintType(), and LowerXConstraint().

Referenced by createVirtualRegs(), IsNonLocalValue(), and IsOperandAMemoryOperand().

◆ computeKnownBitsForFrameIndex()

void TargetLowering::computeKnownBitsForFrameIndex ( const SDValue  FIOp,
KnownBits Known,
const APInt DemandedElts,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
virtual

Determine which of the bits of FrameIndex FIOp are known to be 0.

Default implementation computes low bits based on alignment information. This should preserve known bits passed into it.

Reimplemented in llvm::SITargetLowering.

Definition at line 1291 of file TargetLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::SelectionDAG::InferPtrAlignment(), llvm::Log2_32(), llvm::APInt::setLowBits(), and llvm::KnownBits::Zero.

Referenced by llvm::SelectionDAG::computeKnownBits(), and llvm::SITargetLowering::computeKnownBitsForFrameIndex().

◆ computeKnownBitsForTargetNode()

void TargetLowering::computeKnownBitsForTargetNode ( const SDValue  Op,
KnownBits Known,
const APInt DemandedElts,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
virtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Determine which of the bits specified in Mask are known to be either zero or one and return them in the Known.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::LanaiTargetLowering, and llvm::SparcTargetLowering.

Definition at line 1277 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::SDValue::getOpcode(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::KnownBits::resetAll().

Referenced by llvm::SelectionDAG::computeKnownBits().

◆ ComputeNumSignBitsForTargetNode()

unsigned TargetLowering::ComputeNumSignBitsForTargetNode ( SDValue  Op,
const APInt DemandedElts,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
virtual

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

The DemandedElts argument allows us to only collect the minimum sign bits that are shared by the requested vector elements.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1306 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::SDValue::getOpcode(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::ComputeNumSignBits().

◆ createFastISel()

virtual FastISel* llvm::TargetLowering::createFastISel ( FunctionLoweringInfo ,
const TargetLibraryInfo  
) const
inlinevirtual

This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::MipsTargetLowering.

Definition at line 3181 of file TargetLowering.h.

Referenced by preassignSwiftErrorRegs().

◆ EmitInstrWithCustomInserter()

MachineBasicBlock * TargetLowering::EmitInstrWithCustomInserter ( MachineInstr MI,
MachineBasicBlock MBB 
) const
virtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.

These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::MipsTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::SITargetLowering, llvm::MSP430TargetLowering, llvm::XCoreTargetLowering, llvm::AVRTargetLowering, llvm::SparcTargetLowering, llvm::BPFTargetLowering, llvm::MipsSETargetLowering, llvm::R600TargetLowering, and llvm::Mips16TargetLowering.

Definition at line 280 of file SelectionDAGISel.cpp.

References llvm::dbgs(), and llvm_unreachable.

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), and INITIALIZE_PASS().

◆ expandFP_TO_SINT()

bool TargetLowering::expandFP_TO_SINT ( SDNode N,
SDValue Result,
SelectionDAG DAG 
) const

◆ ExpandInlineAsm()

virtual bool llvm::TargetLowering::ExpandInlineAsm ( CallInst ) const
inlinevirtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.

This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3197 of file TargetLowering.h.

◆ expandMUL()

bool TargetLowering::expandMUL ( SDNode N,
SDValue Lo,
SDValue Hi,
EVT  HiLoVT,
SelectionDAG DAG,
MulExpansionKind  Kind,
SDValue  LL = SDValue(),
SDValue  LH = SDValue(),
SDValue  RL = SDValue(),
SDValue  RH = SDValue() 
) const

Expand a MUL into two nodes.

One that computes the high bits of the result and one that computes the low bits.

Parameters
HiLoVTThe value type to use for the Lo and Hi nodes.
LLLow bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LHHigh bits of the LHS of the MUL. See LL for meaning.
RLLow bits of the RHS of the MUL. See LL for meaning
RHHigh bits of the RHS of the MUL. See LL for meaning.
Returns
true if the node has been expanded. false if it has not

Definition at line 3296 of file TargetLowering.cpp.

References assert(), expandMUL_LOHI(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), Kind, N, and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by getExpandedMinMaxOps().

◆ expandMUL_LOHI()

bool TargetLowering::expandMUL_LOHI ( unsigned  Opcode,
EVT  VT,
SDLoc  dl,
SDValue  LHS,
SDValue  RHS,
SmallVectorImpl< SDValue > &  Result,
EVT  HiLoVT,
SelectionDAG DAG,
MulExpansionKind  Kind,
SDValue  LL = SDValue(),
SDValue  LH = SDValue(),
SDValue  RL = SDValue(),
SDValue  RH = SDValue() 
) const

Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result.

Parameters
ResultA vector that will be filled with the parts of the result in little-endian order.
LLLow bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LHHigh bits of the LHS of the MUL. See LL for meaning.
RLLow bits of the RHS of the MUL. See LL for meaning
RHHigh bits of the RHS of the MUL. See LL for meaning.
Returns
true if the node has been expanded, false if it has not

Definition at line 3126 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::Always, assert(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::APInt::getHighBitsSet(), llvm::APInt::getMaxValue(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelectCC(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::MipsISD::Hi, llvm::MVT::i32, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::MipsISD::Lo, llvm::SelectionDAG::MaskedValueIsZero(), Merge, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SETLT, llvm::ISD::SHL, Signed, llvm::ISD::SMUL_LOHI, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UMUL_LOHI, and llvm::ISD::ZERO_EXTEND.

Referenced by expandMUL().

◆ expandUnalignedLoad()

std::pair< SDValue, SDValue > TargetLowering::expandUnalignedLoad ( LoadSDNode LD,
SelectionDAG DAG 
) const

Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.

Definition at line 3465 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::CreateStackTemporary(), llvm::ISD::EXTLOAD, llvm::ISD::FP_EXTEND, llvm::ISD::FrameIndex, llvm::MemSDNode::getAAInfo(), llvm::LSBaseSDNode::getAddressingMode(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTruncStore(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::MipsISD::Hi, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MipsISD::Lo, llvm::SPII::Load, llvm::ISD::LOAD, llvm::MinAlign(), llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), scalarizeVectorLoad(), llvm::ISD::SHL, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by emitRemovedIntrinsicError(), llvm::NVPTXTargetLowering::LowerOperation(), and llvm::AMDGPUTargetLowering::performLoadCombine().

◆ expandUnalignedStore()

SDValue TargetLowering::expandUnalignedStore ( StoreSDNode ST,
SelectionDAG DAG 
) const

Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.

Definition at line 3615 of file TargetLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::CreateStackTemporary(), llvm::ISD::EXTLOAD, llvm::ISD::FrameIndex, llvm::MemSDNode::getAAInfo(), llvm::LSBaseSDNode::getAddressingMode(), llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getHalfSizedIntegerVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTruncStore(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::MipsISD::Hi, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MipsISD::Lo, llvm::SPII::Load, llvm::MinAlign(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), scalarizeVectorStore(), llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::STORE, llvm::ISD::TokenFactor, and llvm::ISD::UNINDEXED.

Referenced by getFPTernOp(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::AMDGPUTargetLowering::performStoreCombine(), and llvm::R600TargetLowering::ReplaceNodeResults().

◆ functionArgumentNeedsConsecutiveRegisters()

virtual bool llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters ( Type Ty,
CallingConv::ID  CallConv,
bool  isVarArg 
) const
inlinevirtual

For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.

Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 3107 of file TargetLowering.h.

Referenced by llvm::FastISel::lowerCallTo().

◆ getClearCacheBuiltinName()

virtual const char* llvm::TargetLowering::getClearCacheBuiltinName ( ) const
inlinevirtual

Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3079 of file TargetLowering.h.

Referenced by getUnderlyingArgReg().

◆ getConstraintType()

TargetLowering::ConstraintType TargetLowering::getConstraintType ( StringRef  Constraint) const
virtual

◆ getConstTrueVal()

SDValue TargetLowering::getConstTrueVal ( SelectionDAG DAG,
EVT  VT,
const SDLoc DL 
) const

◆ getInlineAsmMemConstraint()

virtual unsigned llvm::TargetLowering::getInlineAsmMemConstraint ( StringRef  ConstraintCode) const
inlinevirtual

◆ getJumpTableEncoding()

unsigned TargetLowering::getJumpTableEncoding ( ) const
virtual

◆ getMMOFlags()

virtual MachineMemOperand::Flags llvm::TargetLowering::getMMOFlags ( const Instruction I) const
inlinevirtual

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.

The default implementation does nothing.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 3133 of file TargetLowering.h.

References llvm::MachineMemOperand::MONone, and Results.

Referenced by hasOnlySelectUsers().

◆ getMultipleConstraintMatchWeight()

TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight ( AsmOperandInfo info,
int  maIndex 
) const
virtual

Examine constraint type and operand type and determine a weight value.

The operand object must already have been set up with the operand type.

This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 2759 of file TargetLowering.cpp.

References llvm::c_str(), llvm::InlineAsm::ConstraintInfo::Codes, CW_Invalid, for(), getSingleConstraintMatchWeight(), and llvm::InlineAsm::ConstraintInfo::multipleAlternatives.

Referenced by ParseConstraints().

◆ getPICJumpTableRelocBase()

SDValue TargetLowering::getPICJumpTableRelocBase ( SDValue  Table,
SelectionDAG DAG 
) const
virtual

◆ getPICJumpTableRelocBaseExpr()

const MCExpr * TargetLowering::getPICJumpTableRelocBaseExpr ( const MachineFunction MF,
unsigned  JTI,
MCContext Ctx 
) const
virtual

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 314 of file TargetLowering.cpp.

References llvm::MCSymbolRefExpr::create(), and llvm::MachineFunction::getJTISymbol().

Referenced by llvm::AsmPrinter::EmitJumpTableInfo(), llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr().

◆ getPostIndexedAddressParts()

virtual bool llvm::TargetLowering::getPostIndexedAddressParts ( SDNode ,
SDNode ,
SDValue ,
SDValue ,
ISD::MemIndexedMode ,
SelectionDAG  
) const
inlinevirtual

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented in llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::AVRTargetLowering.

Definition at line 2533 of file TargetLowering.h.

Referenced by canFoldInAddressingMode().

◆ getPreIndexedAddressParts()

virtual bool llvm::TargetLowering::getPreIndexedAddressParts ( SDNode ,
SDValue ,
SDValue ,
ISD::MemIndexedMode ,
SelectionDAG  
) const
inlinevirtual

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::AVRTargetLowering.

Definition at line 2523 of file TargetLowering.h.

Referenced by canFoldInAddressingMode().

◆ getRecipEstimate()

virtual SDValue llvm::TargetLowering::getRecipEstimate ( SDValue  Operand,
SelectionDAG DAG,
int  Enabled,
int &  RefinementSteps 
) const
inlinevirtual

Return a reciprocal estimate value for the input operand.

Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 3380 of file TargetLowering.h.

References llvm::MipsISD::Hi, Kind, llvm::ARM_MB::LD, llvm::MipsISD::Lo, llvm::BitmaskEnumDetail::Mask(), MI, and llvm::ARM_MB::ST.

Referenced by combineShuffleOfSplat().

◆ getRegForInlineAsmConstraint()

std::pair< unsigned, const TargetRegisterClass * > TargetLowering::getRegForInlineAsmConstraint ( const TargetRegisterInfo TRI,
StringRef  Constraint,
MVT  VT 
) const
virtual

Given a physical register constraint (e.g.

{edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::AVRTargetLowering, llvm::MSP430TargetLowering, llvm::LanaiTargetLowering, llvm::SparcTargetLowering, and llvm::BPFTargetLowering.

Definition at line 2492 of file TargetLowering.cpp.

References assert(), llvm::StringRef::data(), E, llvm::StringRef::empty(), llvm::StringRef::end(), llvm::TargetRegisterInfo::getRegAsmName(), I, llvm::TargetLoweringBase::isLegalRC(), llvm::TargetRegisterInfo::isTypeLegalForClass(), llvm::TargetRegisterInfo::regclasses(), and llvm::StringRef::size().

Referenced by getEstimate(), llvm::BPFTargetLowering::getRegForInlineAsmConstraint(), llvm::SparcTargetLowering::getRegForInlineAsmConstraint(), llvm::LanaiTargetLowering::getRegForInlineAsmConstraint(), llvm::MSP430TargetLowering::getRegForInlineAsmConstraint(), llvm::AVRTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::NVPTXTargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::XCoreTargetLowering::isLegalAddressingMode(), ParseConstraints(), parsePhysicalReg(), patchMatchingInput(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().

◆ getRegisterByName()

virtual unsigned llvm::TargetLowering::getRegisterByName ( const char RegName,
EVT  VT,
SelectionDAG DAG 
) const
inlinevirtual

Return the register ID of the name passed in.

Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::MipsTargetLowering, llvm::SITargetLowering, llvm::AVRTargetLowering, llvm::SparcTargetLowering, and llvm::LanaiTargetLowering.

Definition at line 3086 of file TargetLowering.h.

References llvm::report_fatal_error().

Referenced by llvm::SelectionDAGISel::IsLegalToFold().

◆ getScratchRegisters()

virtual const MCPhysReg* llvm::TargetLowering::getScratchRegisters ( CallingConv::ID  CC) const
inlinevirtual

Returns a 0 terminated array of registers that can be safely used as scratch registers.

Reimplemented in llvm::PPCTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 3114 of file TargetLowering.h.

Referenced by llvm::InstrEmitter::EmitDbgValue(), llvm::FastISel::selectPatchpoint(), and llvm::FastISel::selectStackmap().

◆ getSingleConstraintMatchWeight()

TargetLowering::ConstraintWeight TargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo info,
const char constraint 
) const
virtual

◆ getSqrtEstimate()

virtual SDValue llvm::TargetLowering::getSqrtEstimate ( SDValue  Operand,
SelectionDAG DAG,
int  Enabled,
int &  RefinementSteps,
bool UseOneConstNR,
bool  Reciprocal 
) const
inlinevirtual

Hooks for building estimates in place of slower divisions and square roots.

Return either a square root or its reciprocal estimate value for the input operand. Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. The boolean UseOneConstNR output is used to select a Newton-Raphson algorithm implementation that uses either one or two constants. The boolean Reciprocal is used to select whether the estimate is for the square root of the input operand or the reciprocal of its square root. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Reimplemented in llvm::NVPTXTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 3364 of file TargetLowering.h.

Referenced by combineShuffleOfSplat().

◆ getTargetNodeName()

const char * TargetLowering::getTargetNodeName ( unsigned  Opcode) const
virtual

◆ getTypeForExtReturn()

virtual EVT llvm::TargetLowering::getTypeForExtReturn ( LLVMContext Context,
EVT  VT,
ISD::NodeType   
) const
inlinevirtual

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

FIXME: Some C calling conventions require the return type to be promoted, but this is not true all the time, e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Definition at line 3097 of file TargetLowering.h.

References llvm::EVT::bitsLT(), and llvm::MVT::i32.

Referenced by findUnwindDestinations().

◆ getVectorElementPointer()

SDValue TargetLowering::getVectorElementPointer ( SelectionDAG DAG,
SDValue  VecPtr,
EVT  VecVT,
SDValue  Idx 
) const

Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base address of VecPtr.

If Idx is out of bounds the returned pointer is unspecified, but will be within the vector bounds.

Definition at line 3800 of file TargetLowering.cpp.

References llvm::ISD::ADD, assert(), clampDynamicVectorIndex(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getZExtOrTrunc(), and llvm::ISD::MUL.

◆ HandleByVal()

virtual void llvm::TargetLowering::HandleByVal ( CCState ,
unsigned ,
unsigned   
) const
inlinevirtual

Target-specific cleanup for formal ByVal parameters.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 3035 of file TargetLowering.h.

Referenced by llvm::CCState::HandleByVal().

◆ IncrementMemoryAddress()

SDValue TargetLowering::IncrementMemoryAddress ( SDValue  Addr,
SDValue  Mask,
const SDLoc DL,
EVT  DataVT,
SelectionDAG DAG,
bool  IsCompressedMemory 
) const

Increments memory address Addr according to the type of the value DataVT that should be stored.

If the data is stored in compressed form, the memory address should be incremented according to the number of the stored elements. This number is equal to the number of '1's bits in the Mask. DataVT is a vector type. Mask is a vector value. DataVT and Mask have the same number of vector elements.

Definition at line 3749 of file TargetLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::CTPOP, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::i32, llvm::ISD::MUL, and llvm::ISD::ZERO_EXTEND.

Referenced by ConvertSelectToConcatVector().

◆ initializeSplitCSR()

virtual void llvm::TargetLowering::initializeSplitCSR ( MachineBasicBlock Entry) const
inlinevirtual

Perform necessary initialization to handle a subset of CSRs explicitly via copies.

This function is called at the beginning of instruction selection.

Reimplemented in llvm::PPCTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 2832 of file TargetLowering.h.

References llvm_unreachable.

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

◆ insertCopiesSplitCSR()

virtual void llvm::TargetLowering::insertCopiesSplitCSR ( MachineBasicBlock Entry,
const SmallVectorImpl< MachineBasicBlock *> &  Exits 
) const
inlinevirtual

Insert explicit copies in entry and exit blocks.

We copy a subset of CSRs to virtual registers in the entry block, and copy them back to physical registers in the exit blocks. This function is called at the end of instruction selection.

Reimplemented in llvm::PPCTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 2840 of file TargetLowering.h.

References llvm_unreachable.

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

◆ isConstFalseVal()

bool TargetLowering::isConstFalseVal ( const SDNode N) const

◆ isConstTrueVal()

bool TargetLowering::isConstTrueVal ( const SDNode N) const

◆ isDesirableToCombineBuildVectorToShuffleTruncate()

virtual bool llvm::TargetLowering::isDesirableToCombineBuildVectorToShuffleTruncate ( ArrayRef< int >  ShuffleMask,
EVT  SrcVT,
EVT  TruncVT 
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 2788 of file TargetLowering.h.

◆ isDesirableToCommuteWithShift()

virtual bool llvm::TargetLowering::isDesirableToCommuteWithShift ( const SDNode N) const
inlinevirtual

Return true if it is profitable to move a following shift through this.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2775 of file TargetLowering.h.

Referenced by calculateByteProvider().

◆ IsDesirableToPromoteOp()

virtual bool llvm::TargetLowering::IsDesirableToPromoteOp ( SDValue  ,
EVT  
) const
inlinevirtual

This method query the target whether it is beneficial for dag combiner to promote the specified node.

If true, it should return the desired promotion type by reference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2813 of file TargetLowering.h.

Referenced by matchBinaryPredicate().

◆ isDesirableToTransformToIntegerOp()

virtual bool llvm::TargetLowering::isDesirableToTransformToIntegerOp ( unsigned  ,
EVT   
) const
inlinevirtual

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type.

e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2805 of file TargetLowering.h.

Referenced by ShrinkLoadReplaceStoreWithStore().

◆ isExtendedTrueVal()

bool TargetLowering::isExtendedTrueVal ( const ConstantSDNode N,
EVT  VT,
bool  Signed 
) const

◆ isGAPlusOffset()

bool TargetLowering::isGAPlusOffset ( SDNode N,
const GlobalValue *&  GA,
int64_t &  Offset 
) const
virtual

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2333 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().

Referenced by isConsecutiveLSLoc(), llvm::X86TargetLowering::isGAPlusOffset(), and isWordAligned().

◆ isInTailCallPosition()

bool TargetLowering::isInTailCallPosition ( SelectionDAG DAG,
SDNode Node,
SDValue Chain 
) const

Check whether a given call node is in tail position within its function.

If so, it sets Chain to the input chain of the tail call.

Definition at line 53 of file TargetLowering.cpp.

References F(), llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::AttributeList::hasAttribute(), isUsedByReturnOnly(), llvm::NoAlias, and llvm::AttributeList::ReturnIndex.

Referenced by llvm::XCoreTargetLowering::EmitInstrWithCustomInserter().

◆ isOffsetFoldingLegal()

bool TargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode GA) const
virtual

◆ isPositionIndependent()

bool TargetLowering::isPositionIndependent ( ) const

◆ isTypeDesirableForOp()

virtual bool llvm::TargetLowering::isTypeDesirableForOp ( unsigned  ,
EVT  VT 
) const
inlinevirtual

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.

e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented in llvm::X86TargetLowering, and llvm::SITargetLowering.

Definition at line 2797 of file TargetLowering.h.

Referenced by calculateByteProvider(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), matchBinaryPredicate(), SimplifyDemandedBits(), simplifyDivRem(), and SimplifySetCC().

◆ isUsedByReturnOnly()

virtual bool llvm::TargetLowering::isUsedByReturnOnly ( SDNode ,
SDValue  
) const
inlinevirtual

Return true if result of the specified node is used by a return node only.

It also compute and return the input chain for the tail call.

This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.

Definition at line 3066 of file TargetLowering.h.

Referenced by isInTailCallPosition().

◆ LowerAsmOperandForConstraint()

void TargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG DAG 
) const
virtual

◆ LowerCall()

virtual SDValue llvm::TargetLowering::LowerCall ( CallLoweringInfo ,
SmallVectorImpl< SDValue > &   
) const
inlinevirtual

This hook must be implemented to lower calls into the specified DAG.

The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.

Reimplemented in llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, llvm::AMDGPUTargetLowering, llvm::HexagonTargetLowering, and llvm::SparcTargetLowering.

Definition at line 3029 of file TargetLowering.h.

References llvm_unreachable.

◆ LowerCallTo()

std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo CLI) const

This function lowers an abstract call to a function into an actual call.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall.

This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 8034 of file SelectionDAGBuilder.cpp.

References llvm::MCID::Add, llvm::ISD::ADD, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::TargetLoweringBase::ArgListEntry::Alignment, llvm::ISD::ANY_EXTEND, llvm::SmallVectorImpl< T >::append(), llvm::AMDGPU::HSAMD::Kernel::Key::Args, llvm::ISD::InputArg::ArgVT, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::TargetLowering::CallLoweringInfo::CallConv, llvm::TargetLowering::CallLoweringInfo::Chain, llvm::ComputeValueVTs(), llvm::MachineFrameInfo::CreateStackObject(), llvm::TargetLowering::CallLoweringInfo::CS, llvm::TargetLowering::CallLoweringInfo::DAG, llvm::TargetLowering::CallLoweringInfo::DL, E, llvm::SmallVectorBase::empty(), llvm::ISD::InputArg::Flags, llvm::ISD::OutputArg::Flags, llvm::TargetLowering::CallLoweringInfo::getArgs(), llvm::SelectionDAG::getConstant(), llvm::Type::getContext(), getCopyFromParts(), getCopyToParts(), llvm::SelectionDAG::getDataLayout(), llvm::PointerType::getElementType(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getInstruction(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::Type::getPointerTo(), getReturnAttrs(), llvm::GetReturnInfo(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::PointerType::getUnqual(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::Type::getVoidTy(), llvm::SelectionDAG::getVTList(), I, llvm::TargetLowering::CallLoweringInfo::Ins, llvm::TargetLowering::CallLoweringInfo::InVals, llvm::TargetLoweringBase::ArgListEntry::IsByVal, llvm::TargetLoweringBase::ArgListEntry::IsInReg, llvm::TargetLowering::CallLoweringInfo::IsInReg, llvm::TargetLoweringBase::ArgListEntry::IsNest, llvm::TargetLowering::CallLoweringInfo::IsPostTypeLegalization, llvm::TargetLoweringBase::ArgListEntry::IsReturned, llvm::TargetLowering::CallLoweringInfo::IsReturnValueUsed, llvm::TargetLoweringBase::ArgListEntry::IsSExt, llvm::TargetLoweringBase::ArgListEntry::IsSRet, llvm::TargetLoweringBase::ArgListEntry::IsSwiftError, llvm::TargetLoweringBase::ArgListEntry::IsSwiftSelf, llvm::TargetLowering::CallLoweringInfo::IsTailCall, llvm::TargetLowering::CallLoweringInfo::IsVarArg, llvm::EVT::isVector(), llvm::TargetLoweringBase::ArgListEntry::IsZExt, llvm::ISD::MERGE_VALUES, llvm::TargetLoweringBase::ArgListEntry::Node, llvm::TargetLowering::CallLoweringInfo::NumFixedArgs, llvm::MVT::Other, llvm::TargetLowering::CallLoweringInfo::Outs, llvm::TargetLowering::CallLoweringInfo::OutVals, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::TargetLowering::CallLoweringInfo::RetSExt, llvm::TargetLowering::CallLoweringInfo::RetTy, llvm::TargetLowering::CallLoweringInfo::RetZExt, llvm::ISD::ArgFlagsTy::setInReg(), llvm::SDNodeFlags::setNoUnsignedWrap(), llvm::SelectionDAG::setRoot(), llvm::ISD::ArgFlagsTy::setSExt(), llvm::ISD::ArgFlagsTy::setSplit(), llvm::ISD::ArgFlagsTy::setSwiftError(), llvm::ISD::ArgFlagsTy::setZExt(), llvm::ISD::SIGN_EXTEND, llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::TokenFactor, llvm::TargetLoweringBase::ArgListEntry::Ty, llvm::ISD::InputArg::Used, llvm::RegsForValue::ValueVTs, llvm::ISD::InputArg::VT, llvm::CallingConv::X86_VectorCall, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), getDivRemArgList(), getExpandedMinMaxOps(), llvm::ARMTargetLowering::getJumpTableEncoding(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getSetCCResultType(), getUnderlyingArgReg(), isCalleeLoad(), isWordAligned(), LowerADDC_ADDE_SUBC_SUBE(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerFSINCOS(), llvm::SelectionDAGBuilder::lowerInvokable(), LowerMULH(), LowerToTLSEmulatedModel(), LowerVectorINT_TO_FP(), makeLibCall(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ lowerCmpEqZeroToCtlzSrl()

SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl ( SDValue  Op,
SelectionDAG DAG 
) const

◆ LowerCustomJumpTableEntry()

virtual const MCExpr* llvm::TargetLowering::LowerCustomJumpTableEntry ( const MachineJumpTableInfo ,
const MachineBasicBlock ,
unsigned  ,
MCContext  
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 2546 of file TargetLowering.h.

References llvm::isInTailCallPosition(), llvm_unreachable, and MRI.

Referenced by llvm::AsmPrinter::EmitJumpTableInfo().

◆ LowerFormalArguments()

virtual SDValue llvm::TargetLowering::LowerFormalArguments ( SDValue  ,
CallingConv::ID  ,
bool  ,
const SmallVectorImpl< ISD::InputArg > &  ,
const SDLoc ,
SelectionDAG ,
SmallVectorImpl< SDValue > &   
) const
inlinevirtual

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG.

The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.

Reimplemented in llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::SparcTargetLowering, and llvm::R600TargetLowering.

Definition at line 2855 of file TargetLowering.h.

References llvm_unreachable.

◆ LowerOperation()

SDValue TargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG DAG 
) const
virtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.

If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::NVPTXTargetLowering, llvm::MipsTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::AMDGPUTargetLowering, llvm::HexagonTargetLowering, llvm::XCoreTargetLowering, llvm::AVRTargetLowering, llvm::MSP430TargetLowering, llvm::LanaiTargetLowering, llvm::ARCTargetLowering, llvm::SparcTargetLowering, llvm::MipsSETargetLowering, llvm::BPFTargetLowering, llvm::RISCVTargetLowering, and llvm::R600TargetLowering.

Definition at line 8376 of file SelectionDAGBuilder.cpp.

References llvm_unreachable.

Referenced by getExpandedMinMaxOps().

◆ LowerOperationWrapper()

void TargetLowering::LowerOperationWrapper ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
virtual

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types.

It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::X86TargetLowering, llvm::SystemZTargetLowering, and llvm::MipsTargetLowering.

Definition at line 8369 of file SelectionDAGBuilder.cpp.

References llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

◆ LowerReturn()

virtual SDValue llvm::TargetLowering::LowerReturn ( SDValue  ,
CallingConv::ID  ,
bool  ,
const SmallVectorImpl< ISD::OutputArg > &  ,
const SmallVectorImpl< SDValue > &  ,
const SDLoc ,
SelectionDAG  
) const
inlinevirtual

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG.

The implementation should return the resulting token chain value.

Reimplemented in llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::AMDGPUTargetLowering, and llvm::SparcTargetLowering.

Definition at line 3052 of file TargetLowering.h.

References llvm_unreachable.

Referenced by findUnwindDestinations().

◆ LowerToTLSEmulatedModel()

SDValue TargetLowering::LowerToTLSEmulatedModel ( const GlobalAddressSDNode GA,
SelectionDAG DAG 
) const
virtual

◆ LowerXConstraint()

const char * TargetLowering::LowerXConstraint ( EVT  ConstraintVT) const
virtual

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

This returns null if there is no replacement to make.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2414 of file TargetLowering.cpp.

References llvm::EVT::isFloatingPoint(), and llvm::EVT::isInteger().

Referenced by ComputeConstraintToUse(), and llvm::X86TargetLowering::LowerXConstraint().

◆ makeLibCall()

std::pair< SDValue, SDValue > TargetLowering::makeLibCall ( SelectionDAG DAG,
RTLIB::Libcall  LC,
EVT  RetVT,
ArrayRef< SDValue Ops,
bool  isSigned,
const SDLoc dl,
bool  doesNotReturn = false,
bool  isReturnValueUsed = true 
) const

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

It is an error to pass RTLIB::UNKNOWN_LIBCALL as LC.

Definition at line 119 of file TargetLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, Callee, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExternalSymbol(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::ArgListEntry::IsSExt, llvm::TargetLoweringBase::ArgListEntry::IsZExt, LowerCallTo(), llvm::TargetLoweringBase::ArgListEntry::Node, llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setSExtResult(), llvm::TargetLowering::CallLoweringInfo::setZExtResult(), llvm::TargetLoweringBase::shouldSignExtendTypeInLibCall(), llvm::ArrayRef< T >::size(), and llvm::TargetLoweringBase::ArgListEntry::Ty.

Referenced by getAArch64XALUOOp(), getDivRemArgList(), getExpandedMinMaxOps(), GetFPLibCall(), LowerPREFETCH(), LowerUMULO_SMULO(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), softenSetCCOperands(), and llvm::SelectionDAGBuilder::visitSPDescriptorFailure().

◆ mayBeEmittedAsTailCall()

virtual bool llvm::TargetLowering::mayBeEmittedAsTailCall ( const CallInst ) const
inlinevirtual

Return true if the target may be able emit the call instruction as a tail call.

This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.

Reimplemented in llvm::SystemZTargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.

Definition at line 3073 of file TargetLowering.h.

◆ operator=()

TargetLowering& llvm::TargetLowering::operator= ( const TargetLowering )
delete

◆ parametersInCSRMatch()

bool TargetLowering::parametersInCSRMatch ( const MachineRegisterInfo MRI,
const uint32_t CallerPreservedMask,
const SmallVectorImpl< CCValAssign > &  ArgLocs,
const SmallVectorImpl< SDValue > &  OutVals 
) const

Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function.

This needs to be checked for tail call eligibility.

Definition at line 74 of file TargetLowering.cpp.

References llvm::MachineOperand::clobbersPhysReg(), llvm::ISD::CopyFromReg, E, llvm::MachineRegisterInfo::getLiveInPhysReg(), llvm::CCValAssign::getLocReg(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getReg(), I, llvm::CCValAssign::isRegLoc(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by llvm::SITargetLowering::isEligibleForTailCallOptimization(), MatchingStackOffset(), and mayTailCallThisCC().

◆ ParseConstraints()

TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints ( const DataLayout DL,
const TargetRegisterInfo TRI,
ImmutableCallSite  CS 
) const
virtual

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values.

If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

Information about all of the constraints.

Definition at line 2555 of file TargetLowering.cpp.

References assert(), llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, llvm::dyn_cast(), llvm::IntegerType::get(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getArgument(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getCalledValue(), llvm::Type::getContext(), llvm::PointerType::getElementType(), llvm::MVT::getIntegerVT(), getMultipleConstraintMatchWeight(), llvm::DataLayout::getPointerSizeInBits(), getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::Value::getType(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getType(), llvm::DataLayout::getTypeSizeInBits(), llvm::MVT::getVT(), llvm::InlineAsm::ConstraintInfo::hasMatchingInput(), llvm::InlineAsm::isClobber, llvm::InlineAsm::ConstraintInfo::isIndirect, llvm::InlineAsm::isInput, llvm::MVT::isInteger(), llvm::InlineAsm::isOutput, llvm::Type::isSingleValueType(), llvm::Type::isSized(), llvm::Type::isVoidTy(), llvm::InlineAsm::ConstraintInfo::MatchingInput, llvm::InlineAsm::ConstraintInfo::multipleAlternatives, llvm::MVT::Other, llvm::InlineAsm::ParseConstraints(), llvm::report_fatal_error(), llvm::InlineAsm::ConstraintInfo::selectAlternative(), and llvm::InlineAsm::ConstraintInfo::Type.

Referenced by createVirtualRegs(), IsNonLocalValue(), and IsOperandAMemoryOperand().

◆ PerformDAGCombine()

SDValue TargetLowering::PerformDAGCombine ( SDNode N,
DAGCombinerInfo DCI 
) const
virtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::MipsTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::AMDGPUTargetLowering, llvm::LanaiTargetLowering, llvm::MipsSETargetLowering, and llvm::R600TargetLowering.

Definition at line 2360 of file TargetLowering.cpp.

Referenced by matchBinaryPredicate().

◆ prepareVolatileOrAtomicLoad()

virtual SDValue llvm::TargetLowering::prepareVolatileOrAtomicLoad ( SDValue  Chain,
const SDLoc DL,
SelectionDAG DAG 
) const
inlinevirtual

This callback is used to prepare for a volatile or atomic load.

It takes a chain node as input and returns the chain for the load itself.

Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Definition at line 3125 of file TargetLowering.h.

Referenced by getUniformBase(), and hasOnlySelectUsers().

◆ ReplaceNodeResults()

virtual void llvm::TargetLowering::ReplaceNodeResults ( SDNode ,
SmallVectorImpl< SDValue > &  ,
SelectionDAG  
) const
inlinevirtual

This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.

If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::MipsTargetLowering, llvm::ARMTargetLowering, llvm::SITargetLowering, llvm::SparcTargetLowering, llvm::AMDGPUTargetLowering, llvm::XCoreTargetLowering, llvm::AVRTargetLowering, and llvm::R600TargetLowering.

Definition at line 3170 of file TargetLowering.h.

References llvm_unreachable.

◆ scalarizeVectorLoad()

SDValue TargetLowering::scalarizeVectorLoad ( LoadSDNode LD,
SelectionDAG DAG 
) const

◆ scalarizeVectorStore()

SDValue TargetLowering::scalarizeVectorStore ( StoreSDNode ST,
SelectionDAG DAG 
) const

◆ ShrinkDemandedConstant()

bool TargetLowering::ShrinkDemandedConstant ( SDValue  Op,
const APInt Demanded,
TargetLoweringOpt TLO 
) const

Check to see if the specified operand of the specified instruction is a constant integer.

If the specified instruction has a constant integer operand and there are bits set in that constant that are not demanded, then clear those bits and return true.

If so, check to see if there are any bits set in the constant that are not demanded. If so, shrink the constant and return true.

Definition at line 345 of file TargetLowering.cpp.

References llvm::ISD::AND, C, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::APInt::isSubsetOf(), llvm::TargetLowering::TargetLoweringOpt::New, llvm::ISD::OR, targetShrinkDemandedConstant(), and llvm::ISD::XOR.

Referenced by combineSelect(), and SimplifyDemandedBits().

◆ ShrinkDemandedOp()

bool TargetLowering::ShrinkDemandedOp ( SDValue  Op,
unsigned  BitWidth,
const APInt Demanded,
TargetLoweringOpt TLO 
) const

◆ SimplifyDemandedBits() [1/3]

bool TargetLowering::SimplifyDemandedBits ( SDNode User,
unsigned  OpIdx,
const APInt Demanded,
DAGCombinerInfo DCI,
TargetLoweringOpt TLO 
) const

Helper for SimplifyDemandedBits that can simplify an operation with multiple uses.

This function simplifies operand OpIdx of User and then updates User with the simplified version. No other uses of OpIdx are updated. If User is the only user of OpIdx, this function behaves exactly like function SimplifyDemandedBits declared below except that it also updates the DAG by calling DCI.CommitTargetLoweringOpt.

Definition at line 433 of file TargetLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::TargetLoweringOpt::New, llvm::TargetLowering::TargetLoweringOpt::Old, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SelectionDAG::UpdateNodeOperands().

Referenced by combineSelect(), matchBinaryPredicate(), llvm::ARMTargetLowering::PerformDAGCombine(), SimplifyDemandedBits(), and simplifyI24().

◆ SimplifyDemandedBits() [2/3]

bool TargetLowering::SimplifyDemandedBits ( SDValue  Op,
const APInt DemandedMask,
KnownBits Known,
TargetLoweringOpt TLO,
unsigned  Depth = 0,
bool  AssumeSingleUse = false 
) const

Look at Op.

At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask. AssumeSingleUse When this parameter is true, this function will attempt to simplify Op even if there are multiple uses. Callers are responsible for correctly updating the DAG based on the results of this function, because simply replacing replacing TLO.Old with TLO.New will be incorrect when this parameter is true and TLO.Old has multiple uses.

At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of Known bits for the expression (used to simplify the caller). The Known bits may only be accurate for those bits in the DemandedMask.

Definition at line 503 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertZext, llvm::SDNodeIterator::begin(), llvm::ISD::BITCAST, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::SelectionDAG::computeKnownBits(), llvm::ISD::Constant, llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::dyn_cast(), E, llvm::SDNodeIterator::end(), llvm::MVT::f128, llvm::ISD::FGETSIGN, llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), llvm::KnownBits::getBitWidth(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getFlags(), llvm::APInt::getHiBits(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLoBits(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSignMask(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNodeFlags::hasExact(), llvm::SDNodeFlags::hasNoSignedWrap(), llvm::SDNodeFlags::hasNoUnsignedWrap(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), I, llvm::MVT::i32, llvm::tgtok::In, llvm::ConstantSDNode::isAllOnesValue(), llvm::isBitwiseNot(), llvm::ISD::isBuildVectorAllZeros(), llvm::isConstOrConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::isIntN(), llvm::isNullConstant(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isSimple(), isTypeDesirableForOp(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), LLVM_FALLTHROUGH, llvm::Log2(), llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::MUL, N, llvm::KnownBits::One, llvm::SDNode::ops(), llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setAllBits(), llvm::APInt::setBit(), llvm::ISD::SETCC, llvm::SDNodeFlags::setExact(), llvm::APInt::setLowBits(), llvm::ISD::SETLT, llvm::SDNodeFlags::setNoSignedWrap(), llvm::SDNodeFlags::setNoUnsignedWrap(), llvm::APInt::setSignBit(), llvm::ISD::SHL, llvm::APInt::shl(), ShrinkDemandedConstant(), ShrinkDemandedOp(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, SimplifyDemandedBits(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::KnownBits::trunc(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::APInt::zext().

◆ SimplifyDemandedBits() [3/3]

bool TargetLowering::SimplifyDemandedBits ( SDValue  Op,
const APInt DemandedMask,
DAGCombinerInfo DCI 
) const

◆ SimplifySetCC()

SDValue TargetLowering::SimplifySetCC ( EVT  VT,
SDValue  N0,
SDValue  N1,
ISD::CondCode  Cond,
bool  foldBooleans,
DAGCombinerInfo DCI,
const SDLoc dl 
) const

Try to simplify a setcc built with the specified operands and cc.

If it is unable to simplify it, return a null SDValue.

Definition at line 1471 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertZext, llvm::EVT::bitsGT(), llvm::EVT::bitsLE(), llvm::EVT::bitsLT(), C, llvm::ISD::Constant, llvm::APInt::countTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FNEG, llvm::SelectionDAG::FoldSetCC(), llvm::APInt::getActiveBits(), llvm::MemSDNode::getAlignment(), llvm::APInt::getAllOnesValue(), llvm::LoadSDNode::getBasePtr(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::MemSDNode::getChain(), llvm::TargetLoweringBase::getCondCodeAction(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::APInt::getHighBitsSet(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::APInt::getMaxValue(), llvm::MemSDNode::getMemoryVT(), llvm::APInt::getMinSignedBits(), llvm::APInt::getMinValue(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::APInt::getNumSignBits(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::ISD::getSetCCSwappedOperands(), llvm::APInt::getSExtValue(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::getUnorderedFlavor(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i1, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::TargetLoweringBase::isCondCodeLegal(), isConstFalseVal(), isExtendedTrueVal(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isLegalICmpImmediate(), llvm::DataLayout::isLittleEndian(), llvm::APInt::isNullValue(), llvm::APInt::isOneValue(), llvm::TargetLoweringBase::isOperationLegal(), llvm::EVT::isRound(), llvm::ISD::isSignedIntSetCC(), llvm::APInt::isSubsetOf(), llvm::ISD::isTrueWhenEqual(), isTypeDesirableForOp(), llvm::TargetLoweringBase::isTypeLegal(), llvm::LSBaseSDNode::isUnindexed(), llvm::MemSDNode::isVolatile(), llvm::TargetLoweringBase::Legal, llvm_unreachable, llvm::Log2_32(), llvm::Log2_32_Ceil(), llvm::APInt::lshr(), llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::MinAlign(), llvm::ISD::NON_EXTLOAD, llvm::RISCVFenceField::O, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETFALSE2, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETTRUE2, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, Signed, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.

Referenced by combineShuffleOfSplat(), and getExpandedMinMaxOps().

◆ softenSetCCOperands()

void TargetLowering::softenSetCCOperands ( SelectionDAG DAG,
EVT  VT,
SDValue NewLHS,
SDValue NewRHS,
ISD::CondCode CCCode,
const SDLoc dl 
) const

◆ supportSplitCSR()

virtual bool llvm::TargetLowering::supportSplitCSR ( MachineFunction MF) const
inlinevirtual

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.

Reimplemented in llvm::PPCTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 2825 of file TargetLowering.h.

Referenced by getComparePred(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ supportSwiftError()

virtual bool llvm::TargetLowering::supportSwiftError ( ) const
inlinevirtual

◆ targetShrinkDemandedConstant()

virtual bool llvm::TargetLowering::targetShrinkDemandedConstant ( SDValue  Op,
const APInt Demanded,
TargetLoweringOpt TLO 
) const
inlinevirtual

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2627 of file TargetLowering.h.

References llvm::Depth.

Referenced by ShrinkDemandedConstant().

◆ unwrapAddress()

virtual SDValue llvm::TargetLowering::unwrapAddress ( SDValue  N) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 2748 of file TargetLowering.h.

References N.

Referenced by llvm::BaseIndexOffset::match().

◆ useLoadStackGuardNode()

virtual bool llvm::TargetLowering::useLoadStackGuardNode ( ) const
inlinevirtual

◆ verifyReturnAddressArgumentIsConstant()

bool TargetLowering::verifyReturnAddressArgumentIsConstant ( SDValue  Op,
SelectionDAG DAG 
) const

The documentation for this class was generated from the following files: