LLVM  7.0.0svn
MipsISelLowering.cpp
Go to the documentation of this file.
1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsISelLowering.h"
19 #include "MipsCCState.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMachineFunction.h"
22 #include "MipsRegisterInfo.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "MipsTargetObjectFile.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/ADT/StringSwitch.h"
51 #include "llvm/IR/CallingConv.h"
52 #include "llvm/IR/Constants.h"
53 #include "llvm/IR/DataLayout.h"
54 #include "llvm/IR/DebugLoc.h"
55 #include "llvm/IR/DerivedTypes.h"
56 #include "llvm/IR/Function.h"
57 #include "llvm/IR/GlobalValue.h"
58 #include "llvm/IR/Type.h"
59 #include "llvm/IR/Value.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
64 #include "llvm/Support/Compiler.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78 
79 using namespace llvm;
80 
81 #define DEBUG_TYPE "mips-lower"
82 
83 STATISTIC(NumTailCalls, "Number of tail calls");
84 
85 static cl::opt<bool>
86 LargeGOT("mxgot", cl::Hidden,
87  cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88 
89 static cl::opt<bool>
90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91  cl::desc("MIPS: Don't trap on integer division by zero."),
92  cl::init(false));
93 
94 static const MCPhysReg Mips64DPRegs[8] = {
95  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
96  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
97 };
98 
99 // If I is a shifted mask, set the size (Size) and the first bit of the
100 // mask (Pos), and return true.
101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
103  if (!isShiftedMask_64(I))
104  return false;
105 
106  Size = countPopulation(I);
107  Pos = countTrailingZeros(I);
108  return true;
109 }
110 
111 // The MIPS MSA ABI passes vector arguments in the integer register set.
112 // The number of integer registers used is dependant on the ABI used.
114  EVT VT) const {
115  if (VT.isVector()) {
116  if (Subtarget.isABI_O32()) {
117  return MVT::i32;
118  } else {
119  return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
120  }
121  }
122  return MipsTargetLowering::getRegisterType(Context, VT);
123 }
124 
126  EVT VT) const {
127  if (VT.isVector())
128  return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
129  1U);
130  return MipsTargetLowering::getNumRegisters(Context, VT);
131 }
132 
134  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
135  unsigned &NumIntermediates, MVT &RegisterVT) const {
136  // Break down vector types to either 2 i64s or 4 i32s.
137  RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
138  IntermediateVT = RegisterVT;
139  NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
140  ? VT.getVectorNumElements()
141  : VT.getSizeInBits() / RegisterVT.getSizeInBits();
142 
143  return NumIntermediates;
144 }
145 
148  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
149 }
150 
151 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
152  SelectionDAG &DAG,
153  unsigned Flag) const {
154  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
155 }
156 
157 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
158  SelectionDAG &DAG,
159  unsigned Flag) const {
160  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
161 }
162 
163 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
164  SelectionDAG &DAG,
165  unsigned Flag) const {
166  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
167 }
168 
169 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
170  SelectionDAG &DAG,
171  unsigned Flag) const {
172  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
173 }
174 
175 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
176  SelectionDAG &DAG,
177  unsigned Flag) const {
178  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
179  N->getOffset(), Flag);
180 }
181 
182 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
183  switch ((MipsISD::NodeType)Opcode) {
184  case MipsISD::FIRST_NUMBER: break;
185  case MipsISD::JmpLink: return "MipsISD::JmpLink";
186  case MipsISD::TailCall: return "MipsISD::TailCall";
187  case MipsISD::Highest: return "MipsISD::Highest";
188  case MipsISD::Higher: return "MipsISD::Higher";
189  case MipsISD::Hi: return "MipsISD::Hi";
190  case MipsISD::Lo: return "MipsISD::Lo";
191  case MipsISD::GotHi: return "MipsISD::GotHi";
192  case MipsISD::GPRel: return "MipsISD::GPRel";
193  case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
194  case MipsISD::Ret: return "MipsISD::Ret";
195  case MipsISD::ERet: return "MipsISD::ERet";
196  case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
197  case MipsISD::FMS: return "MipsISD::FMS";
198  case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
199  case MipsISD::FPCmp: return "MipsISD::FPCmp";
200  case MipsISD::FSELECT: return "MipsISD::FSELECT";
201  case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
202  case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
203  case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
204  case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
205  case MipsISD::MFHI: return "MipsISD::MFHI";
206  case MipsISD::MFLO: return "MipsISD::MFLO";
207  case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
208  case MipsISD::Mult: return "MipsISD::Mult";
209  case MipsISD::Multu: return "MipsISD::Multu";
210  case MipsISD::MAdd: return "MipsISD::MAdd";
211  case MipsISD::MAddu: return "MipsISD::MAddu";
212  case MipsISD::MSub: return "MipsISD::MSub";
213  case MipsISD::MSubu: return "MipsISD::MSubu";
214  case MipsISD::DivRem: return "MipsISD::DivRem";
215  case MipsISD::DivRemU: return "MipsISD::DivRemU";
216  case MipsISD::DivRem16: return "MipsISD::DivRem16";
217  case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
218  case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
219  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
220  case MipsISD::Wrapper: return "MipsISD::Wrapper";
221  case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
222  case MipsISD::Sync: return "MipsISD::Sync";
223  case MipsISD::Ext: return "MipsISD::Ext";
224  case MipsISD::Ins: return "MipsISD::Ins";
225  case MipsISD::CIns: return "MipsISD::CIns";
226  case MipsISD::LWL: return "MipsISD::LWL";
227  case MipsISD::LWR: return "MipsISD::LWR";
228  case MipsISD::SWL: return "MipsISD::SWL";
229  case MipsISD::SWR: return "MipsISD::SWR";
230  case MipsISD::LDL: return "MipsISD::LDL";
231  case MipsISD::LDR: return "MipsISD::LDR";
232  case MipsISD::SDL: return "MipsISD::SDL";
233  case MipsISD::SDR: return "MipsISD::SDR";
234  case MipsISD::EXTP: return "MipsISD::EXTP";
235  case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
236  case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
237  case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
238  case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
239  case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
240  case MipsISD::SHILO: return "MipsISD::SHILO";
241  case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
242  case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
243  case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
244  case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
245  case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
246  case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
247  case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
248  case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
249  case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
250  case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
251  case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
252  case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
253  case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
254  case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
255  case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
256  case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
257  case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
258  case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
259  case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
260  case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
261  case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
262  case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
263  case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
264  case MipsISD::MULT: return "MipsISD::MULT";
265  case MipsISD::MULTU: return "MipsISD::MULTU";
266  case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
267  case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
268  case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
269  case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
270  case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
271  case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
272  case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
273  case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
274  case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
275  case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
276  case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
277  case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
278  case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
279  case MipsISD::VCEQ: return "MipsISD::VCEQ";
280  case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
281  case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
282  case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
283  case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
284  case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
285  case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
286  case MipsISD::VNOR: return "MipsISD::VNOR";
287  case MipsISD::VSHF: return "MipsISD::VSHF";
288  case MipsISD::SHF: return "MipsISD::SHF";
289  case MipsISD::ILVEV: return "MipsISD::ILVEV";
290  case MipsISD::ILVOD: return "MipsISD::ILVOD";
291  case MipsISD::ILVL: return "MipsISD::ILVL";
292  case MipsISD::ILVR: return "MipsISD::ILVR";
293  case MipsISD::PCKEV: return "MipsISD::PCKEV";
294  case MipsISD::PCKOD: return "MipsISD::PCKOD";
295  case MipsISD::INSVE: return "MipsISD::INSVE";
296  }
297  return nullptr;
298 }
299 
301  const MipsSubtarget &STI)
302  : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
303  // Mips does not have i1 type, so use i32 for
304  // setcc operations results (slt, sgt, ...).
307  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
308  // does. Integer booleans still use 0 and 1.
309  if (Subtarget.hasMips32r6())
312 
313  // Load extented operations for i1 types must be promoted
314  for (MVT VT : MVT::integer_valuetypes()) {
318  }
319 
320  // MIPS doesn't have extending float->double load/store. Set LoadExtAction
321  // for f32, f16
322  for (MVT VT : MVT::fp_valuetypes()) {
325  }
326 
327  // Set LoadExtAction for f16 vectors to Expand
328  for (MVT VT : MVT::fp_vector_valuetypes()) {
329  MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
330  if (F16VT.isValid())
331  setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
332  }
333 
336 
338 
339  // Used by legalize types to correctly generate the setcc result.
340  // Without this, every float setcc comes with a AND/OR with the result,
341  // we don't want this, since the fpcmp result goes to a flag register,
342  // which is used implicitly by brcond and select operations.
344 
345  // Mips Custom Operations
361 
362  if (Subtarget.isGP64bit()) {
375  }
376 
377  if (!Subtarget.isGP64bit()) {
381  }
382 
384  if (Subtarget.isGP64bit())
386 
395 
396  // Operations not directly supported by Mips.
410  if (Subtarget.hasCnMips()) {
413  } else {
416  }
423 
424  if (!Subtarget.hasMips32r2())
426 
427  if (!Subtarget.hasMips64r2())
429 
446 
447  // Lower f16 conversion operations into library calls
452 
454 
459 
460  // Use the default for now
463 
464  if (!Subtarget.isGP64bit()) {
467  }
468 
469  if (!Subtarget.hasMips32r2()) {
472  }
473 
474  // MIPS16 lacks MIPS32's clz and clo instructions.
477  if (!Subtarget.hasMips64())
479 
480  if (!Subtarget.hasMips32r2())
482  if (!Subtarget.hasMips64r2())
484 
485  if (Subtarget.isGP64bit()) {
490  }
491 
493 
503 
504  if (ABI.IsO32()) {
505  // These libcalls are not available in 32-bit.
506  setLibcallName(RTLIB::SHL_I128, nullptr);
507  setLibcallName(RTLIB::SRL_I128, nullptr);
508  setLibcallName(RTLIB::SRA_I128, nullptr);
509  }
510 
512 
513  // The arguments on the stack are defined in terms of 4-byte slots on O32
514  // and 8-byte slots on N32/N64.
515  setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
516 
517  setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
518 
519  MaxStoresPerMemcpy = 16;
520 
521  isMicroMips = Subtarget.inMicroMipsMode();
522 }
523 
525  const MipsSubtarget &STI) {
526  if (STI.inMips16Mode())
527  return createMips16TargetLowering(TM, STI);
528 
529  return createMipsSETargetLowering(TM, STI);
530 }
531 
532 // Create a fast isel object.
533 FastISel *
535  const TargetLibraryInfo *libInfo) const {
536  const MipsTargetMachine &TM =
537  static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
538 
539  // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
540  bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
543 
544  // Disable if either of the following is true:
545  // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
546  if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
547  UseFastISel = false;
548 
549  return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
550 }
551 
553  EVT VT) const {
554  if (!VT.isVector())
555  return MVT::i32;
557 }
558 
561  const MipsSubtarget &Subtarget) {
562  if (DCI.isBeforeLegalizeOps())
563  return SDValue();
564 
565  EVT Ty = N->getValueType(0);
566  unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
567  unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
568  unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
570  SDLoc DL(N);
571 
572  SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
573  N->getOperand(0), N->getOperand(1));
574  SDValue InChain = DAG.getEntryNode();
575  SDValue InGlue = DivRem;
576 
577  // insert MFLO
578  if (N->hasAnyUseOfValue(0)) {
579  SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
580  InGlue);
581  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
582  InChain = CopyFromLo.getValue(1);
583  InGlue = CopyFromLo.getValue(2);
584  }
585 
586  // insert MFHI
587  if (N->hasAnyUseOfValue(1)) {
588  SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
589  HI, Ty, InGlue);
590  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
591  }
592 
593  return SDValue();
594 }
595 
597  switch (CC) {
598  default: llvm_unreachable("Unknown fp condition code!");
599  case ISD::SETEQ:
600  case ISD::SETOEQ: return Mips::FCOND_OEQ;
601  case ISD::SETUNE: return Mips::FCOND_UNE;
602  case ISD::SETLT:
603  case ISD::SETOLT: return Mips::FCOND_OLT;
604  case ISD::SETGT:
605  case ISD::SETOGT: return Mips::FCOND_OGT;
606  case ISD::SETLE:
607  case ISD::SETOLE: return Mips::FCOND_OLE;
608  case ISD::SETGE:
609  case ISD::SETOGE: return Mips::FCOND_OGE;
610  case ISD::SETULT: return Mips::FCOND_ULT;
611  case ISD::SETULE: return Mips::FCOND_ULE;
612  case ISD::SETUGT: return Mips::FCOND_UGT;
613  case ISD::SETUGE: return Mips::FCOND_UGE;
614  case ISD::SETUO: return Mips::FCOND_UN;
615  case ISD::SETO: return Mips::FCOND_OR;
616  case ISD::SETNE:
617  case ISD::SETONE: return Mips::FCOND_ONE;
618  case ISD::SETUEQ: return Mips::FCOND_UEQ;
619  }
620 }
621 
622 /// This function returns true if the floating point conditional branches and
623 /// conditional moves which use condition code CC should be inverted.
625  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
626  return false;
627 
628  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
629  "Illegal Condition Code");
630 
631  return true;
632 }
633 
634 // Creates and returns an FPCmp node from a setcc node.
635 // Returns Op if setcc is not a floating point comparison.
636 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
637  // must be a SETCC node
638  if (Op.getOpcode() != ISD::SETCC)
639  return Op;
640 
641  SDValue LHS = Op.getOperand(0);
642 
643  if (!LHS.getValueType().isFloatingPoint())
644  return Op;
645 
646  SDValue RHS = Op.getOperand(1);
647  SDLoc DL(Op);
648 
649  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
650  // node if necessary.
651  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
652 
653  return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
654  DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
655 }
656 
657 // Creates and returns a CMovFPT/F node.
659  SDValue False, const SDLoc &DL) {
660  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
661  bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
662  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
663 
664  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
665  True.getValueType(), True, FCC0, False, Cond);
666 }
667 
670  const MipsSubtarget &Subtarget) {
671  if (DCI.isBeforeLegalizeOps())
672  return SDValue();
673 
674  SDValue SetCC = N->getOperand(0);
675 
676  if ((SetCC.getOpcode() != ISD::SETCC) ||
677  !SetCC.getOperand(0).getValueType().isInteger())
678  return SDValue();
679 
680  SDValue False = N->getOperand(2);
681  EVT FalseTy = False.getValueType();
682 
683  if (!FalseTy.isInteger())
684  return SDValue();
685 
686  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
687 
688  // If the RHS (False) is 0, we swap the order of the operands
689  // of ISD::SELECT (obviously also inverting the condition) so that we can
690  // take advantage of conditional moves using the $0 register.
691  // Example:
692  // return (a != 0) ? x : 0;
693  // load $reg, x
694  // movz $reg, $0, a
695  if (!FalseC)
696  return SDValue();
697 
698  const SDLoc DL(N);
699 
700  if (!FalseC->getZExtValue()) {
701  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
702  SDValue True = N->getOperand(1);
703 
704  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
705  SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
706 
707  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
708  }
709 
710  // If both operands are integer constants there's a possibility that we
711  // can do some interesting optimizations.
712  SDValue True = N->getOperand(1);
713  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
714 
715  if (!TrueC || !True.getValueType().isInteger())
716  return SDValue();
717 
718  // We'll also ignore MVT::i64 operands as this optimizations proves
719  // to be ineffective because of the required sign extensions as the result
720  // of a SETCC operator is always MVT::i32 for non-vector types.
721  if (True.getValueType() == MVT::i64)
722  return SDValue();
723 
724  int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
725 
726  // 1) (a < x) ? y : y-1
727  // slti $reg1, a, x
728  // addiu $reg2, $reg1, y-1
729  if (Diff == 1)
730  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
731 
732  // 2) (a < x) ? y-1 : y
733  // slti $reg1, a, x
734  // xor $reg1, $reg1, 1
735  // addiu $reg2, $reg1, y-1
736  if (Diff == -1) {
737  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
738  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
739  SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
740  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
741  }
742 
743  // Could not optimize.
744  return SDValue();
745 }
746 
749  const MipsSubtarget &Subtarget) {
750  if (DCI.isBeforeLegalizeOps())
751  return SDValue();
752 
753  SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
754 
755  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
756  if (!FalseC || FalseC->getZExtValue())
757  return SDValue();
758 
759  // Since RHS (False) is 0, we swap the order of the True/False operands
760  // (obviously also inverting the condition) so that we can
761  // take advantage of conditional moves using the $0 register.
762  // Example:
763  // return (a != 0) ? x : 0;
764  // load $reg, x
765  // movz $reg, $0, a
766  unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
768 
769  SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
770  return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
771  ValueIfFalse, FCC, ValueIfTrue, Glue);
772 }
773 
776  const MipsSubtarget &Subtarget) {
777  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
778  return SDValue();
779 
780  SDValue FirstOperand = N->getOperand(0);
781  unsigned FirstOperandOpc = FirstOperand.getOpcode();
782  SDValue Mask = N->getOperand(1);
783  EVT ValTy = N->getValueType(0);
784  SDLoc DL(N);
785 
786  uint64_t Pos = 0, SMPos, SMSize;
787  ConstantSDNode *CN;
788  SDValue NewOperand;
789  unsigned Opc;
790 
791  // Op's second operand must be a shifted mask.
792  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
793  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
794  return SDValue();
795 
796  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
797  // Pattern match EXT.
798  // $dst = and ((sra or srl) $src , pos), (2**size - 1)
799  // => ext $dst, $src, pos, size
800 
801  // The second operand of the shift must be an immediate.
802  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
803  return SDValue();
804 
805  Pos = CN->getZExtValue();
806 
807  // Return if the shifted mask does not start at bit 0 or the sum of its size
808  // and Pos exceeds the word's size.
809  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
810  return SDValue();
811 
812  Opc = MipsISD::Ext;
813  NewOperand = FirstOperand.getOperand(0);
814  } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
815  // Pattern match CINS.
816  // $dst = and (shl $src , pos), mask
817  // => cins $dst, $src, pos, size
818  // mask is a shifted mask with consecutive 1's, pos = shift amount,
819  // size = population count.
820 
821  // The second operand of the shift must be an immediate.
822  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
823  return SDValue();
824 
825  Pos = CN->getZExtValue();
826 
827  if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
828  Pos + SMSize > ValTy.getSizeInBits())
829  return SDValue();
830 
831  NewOperand = FirstOperand.getOperand(0);
832  // SMSize is 'location' (position) in this case, not size.
833  SMSize--;
834  Opc = MipsISD::CIns;
835  } else {
836  // Pattern match EXT.
837  // $dst = and $src, (2**size - 1) , if size > 16
838  // => ext $dst, $src, pos, size , pos = 0
839 
840  // If the mask is <= 0xffff, andi can be used instead.
841  if (CN->getZExtValue() <= 0xffff)
842  return SDValue();
843 
844  // Return if the mask doesn't start at position 0.
845  if (SMPos)
846  return SDValue();
847 
848  Opc = MipsISD::Ext;
849  NewOperand = FirstOperand;
850  }
851  return DAG.getNode(Opc, DL, ValTy, NewOperand,
852  DAG.getConstant(Pos, DL, MVT::i32),
853  DAG.getConstant(SMSize, DL, MVT::i32));
854 }
855 
858  const MipsSubtarget &Subtarget) {
859  // Pattern match INS.
860  // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
861  // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
862  // => ins $dst, $src, size, pos, $src1
863  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
864  return SDValue();
865 
866  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
867  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
868  ConstantSDNode *CN, *CN1;
869 
870  // See if Op's first operand matches (and $src1 , mask0).
871  if (And0.getOpcode() != ISD::AND)
872  return SDValue();
873 
874  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
875  !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
876  return SDValue();
877 
878  // See if Op's second operand matches (and (shl $src, pos), mask1).
879  if (And1.getOpcode() == ISD::AND &&
880  And1.getOperand(0).getOpcode() == ISD::SHL) {
881 
882  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
883  !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
884  return SDValue();
885 
886  // The shift masks must have the same position and size.
887  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
888  return SDValue();
889 
890  SDValue Shl = And1.getOperand(0);
891 
892  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
893  return SDValue();
894 
895  unsigned Shamt = CN->getZExtValue();
896 
897  // Return if the shift amount and the first bit position of mask are not the
898  // same.
899  EVT ValTy = N->getValueType(0);
900  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
901  return SDValue();
902 
903  SDLoc DL(N);
904  return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
905  DAG.getConstant(SMPos0, DL, MVT::i32),
906  DAG.getConstant(SMSize0, DL, MVT::i32),
907  And0.getOperand(0));
908  } else {
909  // Pattern match DINS.
910  // $dst = or (and $src, mask0), mask1
911  // where mask0 = ((1 << SMSize0) -1) << SMPos0
912  // => dins $dst, $src, pos, size
913  if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
914  ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
915  (SMSize0 + SMPos0 <= 32))) {
916  // Check if AND instruction has constant as argument
917  bool isConstCase = And1.getOpcode() != ISD::AND;
918  if (And1.getOpcode() == ISD::AND) {
919  if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
920  return SDValue();
921  } else {
922  if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
923  return SDValue();
924  }
925  // Don't generate INS if constant OR operand doesn't fit into bits
926  // cleared by constant AND operand.
927  if (CN->getSExtValue() & CN1->getSExtValue())
928  return SDValue();
929 
930  SDLoc DL(N);
931  EVT ValTy = N->getOperand(0)->getValueType(0);
932  SDValue Const1;
933  SDValue SrlX;
934  if (!isConstCase) {
935  Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
936  SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
937  }
938  return DAG.getNode(
939  MipsISD::Ins, DL, N->getValueType(0),
940  isConstCase
941  ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
942  : SrlX,
943  DAG.getConstant(SMPos0, DL, MVT::i32),
944  DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
945  : SMSize0,
946  DL, MVT::i32),
947  And0->getOperand(0));
948 
949  }
950  return SDValue();
951  }
952 }
953 
955  const MipsSubtarget &Subtarget) {
956  // ROOTNode must have a multiplication as an operand for the match to be
957  // successful.
958  if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
959  ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
960  return SDValue();
961 
962  // We don't handle vector types here.
963  if (ROOTNode->getValueType(0).isVector())
964  return SDValue();
965 
966  // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
967  // arithmetic. E.g.
968  // (add (mul a b) c) =>
969  // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
970  // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
971  // or
972  // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
973  //
974  // The overhead of setting up the Hi/Lo registers and reassembling the
975  // result makes this a dubious optimzation for MIPS64. The core of the
976  // problem is that Hi/Lo contain the upper and lower 32 bits of the
977  // operand and result.
978  //
979  // It requires a chain of 4 add/mul for MIPS64R2 to get better code
980  // density than doing it naively, 5 for MIPS64. Additionally, using
981  // madd/msub on MIPS64 requires the operands actually be 32 bit sign
982  // extended operands, not true 64 bit values.
983  //
984  // FIXME: For the moment, disable this completely for MIPS64.
985  if (Subtarget.hasMips64())
986  return SDValue();
987 
988  SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
989  ? ROOTNode->getOperand(0)
990  : ROOTNode->getOperand(1);
991 
992  SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
993  ? ROOTNode->getOperand(1)
994  : ROOTNode->getOperand(0);
995 
996  // Transform this to a MADD only if the user of this node is the add.
997  // If there are other users of the mul, this function returns here.
998  if (!Mult.hasOneUse())
999  return SDValue();
1000 
1001  // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1002  // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1003  // of the multiply must have 32 or more sign bits, otherwise we cannot
1004  // perform this optimization. We have to check this here as we're performing
1005  // this optimization pre-legalization.
1006  SDValue MultLHS = Mult->getOperand(0);
1007  SDValue MultRHS = Mult->getOperand(1);
1008 
1009  bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1010  MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1011  bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1012  MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1013 
1014  if (!IsSigned && !IsUnsigned)
1015  return SDValue();
1016 
1017  // Initialize accumulator.
1018  SDLoc DL(ROOTNode);
1019  SDValue TopHalf;
1020  SDValue BottomHalf;
1021  BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1022  CurDAG.getIntPtrConstant(0, DL));
1023 
1024  TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1025  CurDAG.getIntPtrConstant(1, DL));
1026  SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1027  BottomHalf,
1028  TopHalf);
1029 
1030  // Create MipsMAdd(u) / MipsMSub(u) node.
1031  bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1032  unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1033  : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1034  SDValue MAddOps[3] = {
1035  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1036  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1037  EVT VTs[2] = {MVT::i32, MVT::i32};
1038  SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1039 
1040  SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1041  SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1042  SDValue Combined =
1043  CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1044  return Combined;
1045 }
1046 
1049  const MipsSubtarget &Subtarget) {
1050  // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1051  if (DCI.isBeforeLegalizeOps()) {
1052  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1053  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1054  return performMADD_MSUBCombine(N, DAG, Subtarget);
1055 
1056  return SDValue();
1057  }
1058 
1059  return SDValue();
1060 }
1061 
1064  const MipsSubtarget &Subtarget) {
1065  // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1066  if (DCI.isBeforeLegalizeOps()) {
1067  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1068  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1069  return performMADD_MSUBCombine(N, DAG, Subtarget);
1070 
1071  return SDValue();
1072  }
1073 
1074  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1075  SDValue Add = N->getOperand(1);
1076 
1077  if (Add.getOpcode() != ISD::ADD)
1078  return SDValue();
1079 
1080  SDValue Lo = Add.getOperand(1);
1081 
1082  if ((Lo.getOpcode() != MipsISD::Lo) ||
1084  return SDValue();
1085 
1086  EVT ValTy = N->getValueType(0);
1087  SDLoc DL(N);
1088 
1089  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1090  Add.getOperand(0));
1091  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1092 }
1093 
1096  const MipsSubtarget &Subtarget) {
1097  // Pattern match CINS.
1098  // $dst = shl (and $src , imm), pos
1099  // => cins $dst, $src, pos, size
1100 
1101  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1102  return SDValue();
1103 
1104  SDValue FirstOperand = N->getOperand(0);
1105  unsigned FirstOperandOpc = FirstOperand.getOpcode();
1106  SDValue SecondOperand = N->getOperand(1);
1107  EVT ValTy = N->getValueType(0);
1108  SDLoc DL(N);
1109 
1110  uint64_t Pos = 0, SMPos, SMSize;
1111  ConstantSDNode *CN;
1112  SDValue NewOperand;
1113 
1114  // The second operand of the shift must be an immediate.
1115  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1116  return SDValue();
1117 
1118  Pos = CN->getZExtValue();
1119 
1120  if (Pos >= ValTy.getSizeInBits())
1121  return SDValue();
1122 
1123  if (FirstOperandOpc != ISD::AND)
1124  return SDValue();
1125 
1126  // AND's second operand must be a shifted mask.
1127  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1128  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1129  return SDValue();
1130 
1131  // Return if the shifted mask does not start at bit 0 or the sum of its size
1132  // and Pos exceeds the word's size.
1133  if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1134  return SDValue();
1135 
1136  NewOperand = FirstOperand.getOperand(0);
1137  // SMSize is 'location' (position) in this case, not size.
1138  SMSize--;
1139 
1140  return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1141  DAG.getConstant(Pos, DL, MVT::i32),
1142  DAG.getConstant(SMSize, DL, MVT::i32));
1143 }
1144 
1146  const {
1147  SelectionDAG &DAG = DCI.DAG;
1148  unsigned Opc = N->getOpcode();
1149 
1150  switch (Opc) {
1151  default: break;
1152  case ISD::SDIVREM:
1153  case ISD::UDIVREM:
1154  return performDivRemCombine(N, DAG, DCI, Subtarget);
1155  case ISD::SELECT:
1156  return performSELECTCombine(N, DAG, DCI, Subtarget);
1157  case MipsISD::CMovFP_F:
1158  case MipsISD::CMovFP_T:
1159  return performCMovFPCombine(N, DAG, DCI, Subtarget);
1160  case ISD::AND:
1161  return performANDCombine(N, DAG, DCI, Subtarget);
1162  case ISD::OR:
1163  return performORCombine(N, DAG, DCI, Subtarget);
1164  case ISD::ADD:
1165  return performADDCombine(N, DAG, DCI, Subtarget);
1166  case ISD::SHL:
1167  return performSHLCombine(N, DAG, DCI, Subtarget);
1168  case ISD::SUB:
1169  return performSUBCombine(N, DAG, DCI, Subtarget);
1170  }
1171 
1172  return SDValue();
1173 }
1174 
1176  return Subtarget.hasMips32();
1177 }
1178 
1180  return Subtarget.hasMips32();
1181 }
1182 
1183 void
1186  SelectionDAG &DAG) const {
1187  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1188 
1189  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1190  Results.push_back(Res.getValue(I));
1191 }
1192 
1193 void
1196  SelectionDAG &DAG) const {
1197  return LowerOperationWrapper(N, Results, DAG);
1198 }
1199 
1202 {
1203  switch (Op.getOpcode())
1204  {
1205  case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1206  case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1207  case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1208  case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1209  case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1210  case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1211  case ISD::SELECT: return lowerSELECT(Op, DAG);
1212  case ISD::SETCC: return lowerSETCC(Op, DAG);
1213  case ISD::VASTART: return lowerVASTART(Op, DAG);
1214  case ISD::VAARG: return lowerVAARG(Op, DAG);
1215  case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1216  case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1217  case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1218  case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1219  case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1220  case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1221  case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1222  case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1223  case ISD::LOAD: return lowerLOAD(Op, DAG);
1224  case ISD::STORE: return lowerSTORE(Op, DAG);
1225  case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1226  case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1227  }
1228  return SDValue();
1229 }
1230 
1231 //===----------------------------------------------------------------------===//
1232 // Lower helper functions
1233 //===----------------------------------------------------------------------===//
1234 
1235 // addLiveIn - This helper function adds the specified physical register to the
1236 // MachineFunction as a live in value. It also creates a corresponding
1237 // virtual register for it.
1238 static unsigned
1239 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1240 {
1241  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1242  MF.getRegInfo().addLiveIn(PReg, VReg);
1243  return VReg;
1244 }
1245 
1247  MachineBasicBlock &MBB,
1248  const TargetInstrInfo &TII,
1249  bool Is64Bit, bool IsMicroMips) {
1250  if (NoZeroDivCheck)
1251  return &MBB;
1252 
1253  // Insert instruction "teq $divisor_reg, $zero, 7".
1255  MachineInstrBuilder MIB;
1256  MachineOperand &Divisor = MI.getOperand(2);
1257  MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1258  TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1259  .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1260  .addReg(Mips::ZERO)
1261  .addImm(7);
1262 
1263  // Use the 32-bit sub-register if this is a 64-bit division.
1264  if (Is64Bit)
1265  MIB->getOperand(0).setSubReg(Mips::sub_32);
1266 
1267  // Clear Divisor's kill flag.
1268  Divisor.setIsKill(false);
1269 
1270  // We would normally delete the original instruction here but in this case
1271  // we only needed to inject an additional instruction rather than replace it.
1272 
1273  return &MBB;
1274 }
1275 
1278  MachineBasicBlock *BB) const {
1279  switch (MI.getOpcode()) {
1280  default:
1281  llvm_unreachable("Unexpected instr type to insert");
1282  case Mips::ATOMIC_LOAD_ADD_I8:
1283  return emitAtomicBinaryPartword(MI, BB, 1);
1284  case Mips::ATOMIC_LOAD_ADD_I16:
1285  return emitAtomicBinaryPartword(MI, BB, 2);
1286  case Mips::ATOMIC_LOAD_ADD_I32:
1287  return emitAtomicBinary(MI, BB);
1288  case Mips::ATOMIC_LOAD_ADD_I64:
1289  return emitAtomicBinary(MI, BB);
1290 
1291  case Mips::ATOMIC_LOAD_AND_I8:
1292  return emitAtomicBinaryPartword(MI, BB, 1);
1293  case Mips::ATOMIC_LOAD_AND_I16:
1294  return emitAtomicBinaryPartword(MI, BB, 2);
1295  case Mips::ATOMIC_LOAD_AND_I32:
1296  return emitAtomicBinary(MI, BB);
1297  case Mips::ATOMIC_LOAD_AND_I64:
1298  return emitAtomicBinary(MI, BB);
1299 
1300  case Mips::ATOMIC_LOAD_OR_I8:
1301  return emitAtomicBinaryPartword(MI, BB, 1);
1302  case Mips::ATOMIC_LOAD_OR_I16:
1303  return emitAtomicBinaryPartword(MI, BB, 2);
1304  case Mips::ATOMIC_LOAD_OR_I32:
1305  return emitAtomicBinary(MI, BB);
1306  case Mips::ATOMIC_LOAD_OR_I64:
1307  return emitAtomicBinary(MI, BB);
1308 
1309  case Mips::ATOMIC_LOAD_XOR_I8:
1310  return emitAtomicBinaryPartword(MI, BB, 1);
1311  case Mips::ATOMIC_LOAD_XOR_I16:
1312  return emitAtomicBinaryPartword(MI, BB, 2);
1313  case Mips::ATOMIC_LOAD_XOR_I32:
1314  return emitAtomicBinary(MI, BB);
1315  case Mips::ATOMIC_LOAD_XOR_I64:
1316  return emitAtomicBinary(MI, BB);
1317 
1318  case Mips::ATOMIC_LOAD_NAND_I8:
1319  return emitAtomicBinaryPartword(MI, BB, 1);
1320  case Mips::ATOMIC_LOAD_NAND_I16:
1321  return emitAtomicBinaryPartword(MI, BB, 2);
1322  case Mips::ATOMIC_LOAD_NAND_I32:
1323  return emitAtomicBinary(MI, BB);
1324  case Mips::ATOMIC_LOAD_NAND_I64:
1325  return emitAtomicBinary(MI, BB);
1326 
1327  case Mips::ATOMIC_LOAD_SUB_I8:
1328  return emitAtomicBinaryPartword(MI, BB, 1);
1329  case Mips::ATOMIC_LOAD_SUB_I16:
1330  return emitAtomicBinaryPartword(MI, BB, 2);
1331  case Mips::ATOMIC_LOAD_SUB_I32:
1332  return emitAtomicBinary(MI, BB);
1333  case Mips::ATOMIC_LOAD_SUB_I64:
1334  return emitAtomicBinary(MI, BB);
1335 
1336  case Mips::ATOMIC_SWAP_I8:
1337  return emitAtomicBinaryPartword(MI, BB, 1);
1338  case Mips::ATOMIC_SWAP_I16:
1339  return emitAtomicBinaryPartword(MI, BB, 2);
1340  case Mips::ATOMIC_SWAP_I32:
1341  return emitAtomicBinary(MI, BB);
1342  case Mips::ATOMIC_SWAP_I64:
1343  return emitAtomicBinary(MI, BB);
1344 
1345  case Mips::ATOMIC_CMP_SWAP_I8:
1346  return emitAtomicCmpSwapPartword(MI, BB, 1);
1347  case Mips::ATOMIC_CMP_SWAP_I16:
1348  return emitAtomicCmpSwapPartword(MI, BB, 2);
1349  case Mips::ATOMIC_CMP_SWAP_I32:
1350  return emitAtomicCmpSwap(MI, BB);
1351  case Mips::ATOMIC_CMP_SWAP_I64:
1352  return emitAtomicCmpSwap(MI, BB);
1353  case Mips::PseudoSDIV:
1354  case Mips::PseudoUDIV:
1355  case Mips::DIV:
1356  case Mips::DIVU:
1357  case Mips::MOD:
1358  case Mips::MODU:
1359  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1360  false);
1361  case Mips::SDIV_MM_Pseudo:
1362  case Mips::UDIV_MM_Pseudo:
1363  case Mips::SDIV_MM:
1364  case Mips::UDIV_MM:
1365  case Mips::DIV_MMR6:
1366  case Mips::DIVU_MMR6:
1367  case Mips::MOD_MMR6:
1368  case Mips::MODU_MMR6:
1369  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1370  case Mips::PseudoDSDIV:
1371  case Mips::PseudoDUDIV:
1372  case Mips::DDIV:
1373  case Mips::DDIVU:
1374  case Mips::DMOD:
1375  case Mips::DMODU:
1376  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1377 
1378  case Mips::PseudoSELECT_I:
1379  case Mips::PseudoSELECT_I64:
1380  case Mips::PseudoSELECT_S:
1381  case Mips::PseudoSELECT_D32:
1382  case Mips::PseudoSELECT_D64:
1383  return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1384  case Mips::PseudoSELECTFP_F_I:
1385  case Mips::PseudoSELECTFP_F_I64:
1386  case Mips::PseudoSELECTFP_F_S:
1387  case Mips::PseudoSELECTFP_F_D32:
1388  case Mips::PseudoSELECTFP_F_D64:
1389  return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1390  case Mips::PseudoSELECTFP_T_I:
1391  case Mips::PseudoSELECTFP_T_I64:
1392  case Mips::PseudoSELECTFP_T_S:
1393  case Mips::PseudoSELECTFP_T_D32:
1394  case Mips::PseudoSELECTFP_T_D64:
1395  return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1396  }
1397 }
1398 
1399 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1400 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1402 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1403  MachineBasicBlock *BB) const {
1404 
1405  MachineFunction *MF = BB->getParent();
1406  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1408  DebugLoc DL = MI.getDebugLoc();
1409 
1410  unsigned AtomicOp;
1411  switch (MI.getOpcode()) {
1412  case Mips::ATOMIC_LOAD_ADD_I32:
1413  AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1414  break;
1415  case Mips::ATOMIC_LOAD_SUB_I32:
1416  AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1417  break;
1418  case Mips::ATOMIC_LOAD_AND_I32:
1419  AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1420  break;
1421  case Mips::ATOMIC_LOAD_OR_I32:
1422  AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1423  break;
1424  case Mips::ATOMIC_LOAD_XOR_I32:
1425  AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1426  break;
1427  case Mips::ATOMIC_LOAD_NAND_I32:
1428  AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1429  break;
1430  case Mips::ATOMIC_SWAP_I32:
1431  AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1432  break;
1433  case Mips::ATOMIC_LOAD_ADD_I64:
1434  AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1435  break;
1436  case Mips::ATOMIC_LOAD_SUB_I64:
1437  AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1438  break;
1439  case Mips::ATOMIC_LOAD_AND_I64:
1440  AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1441  break;
1442  case Mips::ATOMIC_LOAD_OR_I64:
1443  AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1444  break;
1445  case Mips::ATOMIC_LOAD_XOR_I64:
1446  AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1447  break;
1448  case Mips::ATOMIC_LOAD_NAND_I64:
1449  AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1450  break;
1451  case Mips::ATOMIC_SWAP_I64:
1452  AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1453  break;
1454  default:
1455  llvm_unreachable("Unknown pseudo atomic for replacement!");
1456  }
1457 
1458  unsigned OldVal = MI.getOperand(0).getReg();
1459  unsigned Ptr = MI.getOperand(1).getReg();
1460  unsigned Incr = MI.getOperand(2).getReg();
1461  unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1462 
1464 
1465  // The scratch registers here with the EarlyClobber | Define | Implicit
1466  // flags is used to persuade the register allocator and the machine
1467  // verifier to accept the usage of this register. This has to be a real
1468  // register which has an UNDEF value but is dead after the instruction which
1469  // is unique among the registers chosen for the instruction.
1470 
1471  // The EarlyClobber flag has the semantic properties that the operand it is
1472  // attached to is clobbered before the rest of the inputs are read. Hence it
1473  // must be unique among the operands to the instruction.
1474  // The Define flag is needed to coerce the machine verifier that an Undef
1475  // value isn't a problem.
1476  // The Dead flag is needed as the value in scratch isn't used by any other
1477  // instruction. Kill isn't used as Dead is more precise.
1478  // The implicit flag is here due to the interaction between the other flags
1479  // and the machine verifier.
1480 
1481  // For correctness purpose, a new pseudo is introduced here. We need this
1482  // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1483  // that is spread over >1 basic blocks. A register allocator which
1484  // introduces (or any codegen infact) a store, can violate the expectations
1485  // of the hardware.
1486  //
1487  // An atomic read-modify-write sequence starts with a linked load
1488  // instruction and ends with a store conditional instruction. The atomic
1489  // read-modify-write sequence fails if any of the following conditions
1490  // occur between the execution of ll and sc:
1491  // * A coherent store is completed by another process or coherent I/O
1492  // module into the block of synchronizable physical memory containing
1493  // the word. The size and alignment of the block is
1494  // implementation-dependent.
1495  // * A coherent store is executed between an LL and SC sequence on the
1496  // same processor to the block of synchornizable physical memory
1497  // containing the word.
1498  //
1499 
1500  unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1501  unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1502 
1503  BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1504  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1505 
1506  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1507  .addReg(OldVal, RegState::Define | RegState::EarlyClobber)
1508  .addReg(PtrCopy)
1509  .addReg(IncrCopy)
1512 
1513  MI.eraseFromParent();
1514 
1515  return BB;
1516 }
1517 
1518 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1519  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1520  unsigned SrcReg) const {
1522  const DebugLoc &DL = MI.getDebugLoc();
1523 
1524  if (Subtarget.hasMips32r2() && Size == 1) {
1525  BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1526  return BB;
1527  }
1528 
1529  if (Subtarget.hasMips32r2() && Size == 2) {
1530  BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1531  return BB;
1532  }
1533 
1534  MachineFunction *MF = BB->getParent();
1535  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1537  unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1538 
1539  assert(Size < 32);
1540  int64_t ShiftImm = 32 - (Size * 8);
1541 
1542  BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1543  BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1544 
1545  return BB;
1546 }
1547 
1548 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1549  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1550  assert((Size == 1 || Size == 2) &&
1551  "Unsupported size for EmitAtomicBinaryPartial.");
1552 
1553  MachineFunction *MF = BB->getParent();
1554  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1556  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1557  const TargetRegisterClass *RCp =
1558  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1560  DebugLoc DL = MI.getDebugLoc();
1561 
1562  unsigned Dest = MI.getOperand(0).getReg();
1563  unsigned Ptr = MI.getOperand(1).getReg();
1564  unsigned Incr = MI.getOperand(2).getReg();
1565 
1566  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1567  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1568  unsigned Mask = RegInfo.createVirtualRegister(RC);
1569  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1570  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1571  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1572  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1573  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1574  unsigned Scratch = RegInfo.createVirtualRegister(RC);
1575  unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
1576  unsigned Scratch3 = RegInfo.createVirtualRegister(RC);
1577 
1578  unsigned AtomicOp = 0;
1579  switch (MI.getOpcode()) {
1580  case Mips::ATOMIC_LOAD_NAND_I8:
1581  AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1582  break;
1583  case Mips::ATOMIC_LOAD_NAND_I16:
1584  AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1585  break;
1586  case Mips::ATOMIC_SWAP_I8:
1587  AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1588  break;
1589  case Mips::ATOMIC_SWAP_I16:
1590  AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1591  break;
1592  case Mips::ATOMIC_LOAD_ADD_I8:
1593  AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1594  break;
1595  case Mips::ATOMIC_LOAD_ADD_I16:
1596  AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1597  break;
1598  case Mips::ATOMIC_LOAD_SUB_I8:
1599  AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1600  break;
1601  case Mips::ATOMIC_LOAD_SUB_I16:
1602  AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1603  break;
1604  case Mips::ATOMIC_LOAD_AND_I8:
1605  AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1606  break;
1607  case Mips::ATOMIC_LOAD_AND_I16:
1608  AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1609  break;
1610  case Mips::ATOMIC_LOAD_OR_I8:
1611  AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1612  break;
1613  case Mips::ATOMIC_LOAD_OR_I16:
1614  AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1615  break;
1616  case Mips::ATOMIC_LOAD_XOR_I8:
1617  AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1618  break;
1619  case Mips::ATOMIC_LOAD_XOR_I16:
1620  AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1621  break;
1622  default:
1623  llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1624  }
1625 
1626  // insert new blocks after the current block
1627  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1628  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1630  MF->insert(It, exitMBB);
1631 
1632  // Transfer the remainder of BB and its successor edges to exitMBB.
1633  exitMBB->splice(exitMBB->begin(), BB,
1634  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1635  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1636 
1637  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1638 
1639  // thisMBB:
1640  // addiu masklsb2,$0,-4 # 0xfffffffc
1641  // and alignedaddr,ptr,masklsb2
1642  // andi ptrlsb2,ptr,3
1643  // sll shiftamt,ptrlsb2,3
1644  // ori maskupper,$0,255 # 0xff
1645  // sll mask,maskupper,shiftamt
1646  // nor mask2,$0,mask
1647  // sll incr2,incr,shiftamt
1648 
1649  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1650  BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1651  .addReg(ABI.GetNullPtr()).addImm(-4);
1652  BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1653  .addReg(Ptr).addReg(MaskLSB2);
1654  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1655  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1656  if (Subtarget.isLittle()) {
1657  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1658  } else {
1659  unsigned Off = RegInfo.createVirtualRegister(RC);
1660  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1661  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1662  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1663  }
1664  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1665  .addReg(Mips::ZERO).addImm(MaskImm);
1666  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1667  .addReg(MaskUpper).addReg(ShiftAmt);
1668  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1669  BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1670 
1671 
1672  // The purposes of the flags on the scratch registers is explained in
1673  // emitAtomicBinary. In summary, we need a scratch register which is going to
1674  // be undef, that is unique among registers chosen for the instruction.
1675 
1676  BuildMI(BB, DL, TII->get(AtomicOp))
1677  .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1678  .addReg(AlignedAddr)
1679  .addReg(Incr2)
1680  .addReg(Mask)
1681  .addReg(Mask2)
1682  .addReg(ShiftAmt)
1689 
1690  MI.eraseFromParent(); // The instruction is gone now.
1691 
1692  return exitMBB;
1693 }
1694 
1695 // Lower atomic compare and swap to a pseudo instruction, taking care to
1696 // define a scratch register for the pseudo instruction's expansion. The
1697 // instruction is expanded after the register allocator as to prevent
1698 // the insertion of stores between the linked load and the store conditional.
1699 
1701 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1702  MachineBasicBlock *BB) const {
1703 
1704  assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1705  MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1706  "Unsupported atomic psseudo for EmitAtomicCmpSwap.");
1707 
1708  const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1709 
1710  MachineFunction *MF = BB->getParent();
1712  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1714  DebugLoc DL = MI.getDebugLoc();
1715 
1716  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1717  ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1718  : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1719  unsigned Dest = MI.getOperand(0).getReg();
1720  unsigned Ptr = MI.getOperand(1).getReg();
1721  unsigned OldVal = MI.getOperand(2).getReg();
1722  unsigned NewVal = MI.getOperand(3).getReg();
1723 
1724  unsigned Scratch = MRI.createVirtualRegister(RC);
1726 
1727  // We need to create copies of the various registers and kill them at the
1728  // atomic pseudo. If the copies are not made, when the atomic is expanded
1729  // after fast register allocation, the spills will end up outside of the
1730  // blocks that their values are defined in, causing livein errors.
1731 
1732  unsigned DestCopy = MRI.createVirtualRegister(MRI.getRegClass(Dest));
1733  unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1734  unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1735  unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1736 
1737  BuildMI(*BB, II, DL, TII->get(Mips::COPY), DestCopy).addReg(Dest);
1738  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1739  BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1740  BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1741 
1742  // The purposes of the flags on the scratch registers is explained in
1743  // emitAtomicBinary. In summary, we need a scratch register which is going to
1744  // be undef, that is unique among registers chosen for the instruction.
1745 
1746  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1747  .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1748  .addReg(PtrCopy, RegState::Kill)
1749  .addReg(OldValCopy, RegState::Kill)
1750  .addReg(NewValCopy, RegState::Kill)
1753 
1754  MI.eraseFromParent(); // The instruction is gone now.
1755 
1756  return BB;
1757 }
1758 
1759 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1760  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1761  assert((Size == 1 || Size == 2) &&
1762  "Unsupported size for EmitAtomicCmpSwapPartial.");
1763 
1764  MachineFunction *MF = BB->getParent();
1765  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1767  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1768  const TargetRegisterClass *RCp =
1769  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1771  DebugLoc DL = MI.getDebugLoc();
1772 
1773  unsigned Dest = MI.getOperand(0).getReg();
1774  unsigned Ptr = MI.getOperand(1).getReg();
1775  unsigned CmpVal = MI.getOperand(2).getReg();
1776  unsigned NewVal = MI.getOperand(3).getReg();
1777 
1778  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1779  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1780  unsigned Mask = RegInfo.createVirtualRegister(RC);
1781  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1782  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1783  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1784  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1785  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1786  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1787  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1788  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1789  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1790  ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1791  : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1792 
1793  // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1794  // flags are used to coerce the register allocator and the machine verifier to
1795  // accept the usage of these registers.
1796  // The EarlyClobber flag has the semantic properties that the operand it is
1797  // attached to is clobbered before the rest of the inputs are read. Hence it
1798  // must be unique among the operands to the instruction.
1799  // The Define flag is needed to coerce the machine verifier that an Undef
1800  // value isn't a problem.
1801  // The Dead flag is needed as the value in scratch isn't used by any other
1802  // instruction. Kill isn't used as Dead is more precise.
1803  unsigned Scratch = RegInfo.createVirtualRegister(RC);
1804  unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
1805 
1806  // insert new blocks after the current block
1807  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1808  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1810  MF->insert(It, exitMBB);
1811 
1812  // Transfer the remainder of BB and its successor edges to exitMBB.
1813  exitMBB->splice(exitMBB->begin(), BB,
1814  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1815  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1816 
1817  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1818 
1819  // thisMBB:
1820  // addiu masklsb2,$0,-4 # 0xfffffffc
1821  // and alignedaddr,ptr,masklsb2
1822  // andi ptrlsb2,ptr,3
1823  // xori ptrlsb2,ptrlsb2,3 # Only for BE
1824  // sll shiftamt,ptrlsb2,3
1825  // ori maskupper,$0,255 # 0xff
1826  // sll mask,maskupper,shiftamt
1827  // nor mask2,$0,mask
1828  // andi maskedcmpval,cmpval,255
1829  // sll shiftedcmpval,maskedcmpval,shiftamt
1830  // andi maskednewval,newval,255
1831  // sll shiftednewval,maskednewval,shiftamt
1832  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1833  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1834  .addReg(ABI.GetNullPtr()).addImm(-4);
1835  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1836  .addReg(Ptr).addReg(MaskLSB2);
1837  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1838  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1839  if (Subtarget.isLittle()) {
1840  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1841  } else {
1842  unsigned Off = RegInfo.createVirtualRegister(RC);
1843  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1844  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1845  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1846  }
1847  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1848  .addReg(Mips::ZERO).addImm(MaskImm);
1849  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1850  .addReg(MaskUpper).addReg(ShiftAmt);
1851  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1852  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1853  .addReg(CmpVal).addImm(MaskImm);
1854  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1855  .addReg(MaskedCmpVal).addReg(ShiftAmt);
1856  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1857  .addReg(NewVal).addImm(MaskImm);
1858  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1859  .addReg(MaskedNewVal).addReg(ShiftAmt);
1860 
1861  // The purposes of the flags on the scratch registers are explained in
1862  // emitAtomicBinary. In summary, we need a scratch register which is going to
1863  // be undef, that is unique among the register chosen for the instruction.
1864 
1865  BuildMI(BB, DL, TII->get(AtomicOp))
1866  .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1867  .addReg(AlignedAddr)
1868  .addReg(Mask)
1869  .addReg(ShiftedCmpVal)
1870  .addReg(Mask2)
1871  .addReg(ShiftedNewVal)
1872  .addReg(ShiftAmt)
1877 
1878  MI.eraseFromParent(); // The instruction is gone now.
1879 
1880  return exitMBB;
1881 }
1882 
1883 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1884  // The first operand is the chain, the second is the condition, the third is
1885  // the block to branch to if the condition is true.
1886  SDValue Chain = Op.getOperand(0);
1887  SDValue Dest = Op.getOperand(2);
1888  SDLoc DL(Op);
1889 
1891  SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1892 
1893  // Return if flag is not set by a floating point comparison.
1894  if (CondRes.getOpcode() != MipsISD::FPCmp)
1895  return Op;
1896 
1897  SDValue CCNode = CondRes.getOperand(2);
1898  Mips::CondCode CC =
1899  (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1900  unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1901  SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1902  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1903  return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1904  FCC0, Dest, CondRes);
1905 }
1906 
1907 SDValue MipsTargetLowering::
1908 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1909 {
1911  SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1912 
1913  // Return if flag is not set by a floating point comparison.
1914  if (Cond.getOpcode() != MipsISD::FPCmp)
1915  return Op;
1916 
1917  return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1918  SDLoc(Op));
1919 }
1920 
1921 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1923  SDValue Cond = createFPCmp(DAG, Op);
1924 
1925  assert(Cond.getOpcode() == MipsISD::FPCmp &&
1926  "Floating point operand expected.");
1927 
1928  SDLoc DL(Op);
1929  SDValue True = DAG.getConstant(1, DL, MVT::i32);
1930  SDValue False = DAG.getConstant(0, DL, MVT::i32);
1931 
1932  return createCMovFP(DAG, Cond, True, False, DL);
1933 }
1934 
1935 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1936  SelectionDAG &DAG) const {
1937  EVT Ty = Op.getValueType();
1938  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1939  const GlobalValue *GV = N->getGlobal();
1940 
1941  if (!isPositionIndependent()) {
1942  const MipsTargetObjectFile *TLOF =
1943  static_cast<const MipsTargetObjectFile *>(
1945  const GlobalObject *GO = GV->getBaseObject();
1946  if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
1947  // %gp_rel relocation
1948  return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
1949 
1950  // %hi/%lo relocation
1951  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1952  // %highest/%higher/%hi/%lo relocation
1953  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1954  }
1955 
1956  // Every other architecture would use shouldAssumeDSOLocal in here, but
1957  // mips is special.
1958  // * In PIC code mips requires got loads even for local statics!
1959  // * To save on got entries, for local statics the got entry contains the
1960  // page and an additional add instruction takes care of the low bits.
1961  // * It is legal to access a hidden symbol with a non hidden undefined,
1962  // so one cannot guarantee that all access to a hidden symbol will know
1963  // it is hidden.
1964  // * Mips linkers don't support creating a page and a full got entry for
1965  // the same symbol.
1966  // * Given all that, we have to use a full got entry for hidden symbols :-(
1967  if (GV->hasLocalLinkage())
1968  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1969 
1970  if (LargeGOT)
1971  return getAddrGlobalLargeGOT(
1973  DAG.getEntryNode(),
1974  MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1975 
1976  return getAddrGlobal(
1977  N, SDLoc(N), Ty, DAG,
1979  DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1980 }
1981 
1982 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1983  SelectionDAG &DAG) const {
1984  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1985  EVT Ty = Op.getValueType();
1986 
1987  if (!isPositionIndependent())
1988  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1989  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1990 
1991  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1992 }
1993 
1994 SDValue MipsTargetLowering::
1995 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1996 {
1997  // If the relocation model is PIC, use the General Dynamic TLS Model or
1998  // Local Dynamic TLS model, otherwise use the Initial Exec or
1999  // Local Exec TLS Model.
2000 
2001  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2002  if (DAG.getTarget().useEmulatedTLS())
2003  return LowerToTLSEmulatedModel(GA, DAG);
2004 
2005  SDLoc DL(GA);
2006  const GlobalValue *GV = GA->getGlobal();
2007  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2008 
2010 
2011  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2012  // General Dynamic and Local Dynamic TLS Model.
2013  unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2014  : MipsII::MO_TLSGD;
2015 
2016  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2017  SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2018  getGlobalReg(DAG, PtrVT), TGA);
2019  unsigned PtrSize = PtrVT.getSizeInBits();
2020  IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2021 
2022  SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2023 
2024  ArgListTy Args;
2025  ArgListEntry Entry;
2026  Entry.Node = Argument;
2027  Entry.Ty = PtrTy;
2028  Args.push_back(Entry);
2029 
2031  CLI.setDebugLoc(DL)
2032  .setChain(DAG.getEntryNode())
2033  .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2034  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2035 
2036  SDValue Ret = CallResult.first;
2037 
2038  if (model != TLSModel::LocalDynamic)
2039  return Ret;
2040 
2041  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2043  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2044  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2046  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2047  SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2048  return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2049  }
2050 
2051  SDValue Offset;
2052  if (model == TLSModel::InitialExec) {
2053  // Initial Exec TLS Model
2054  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2056  TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2057  TGA);
2058  Offset =
2059  DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2060  } else {
2061  // Local Exec TLS Model
2062  assert(model == TLSModel::LocalExec);
2063  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2065  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2067  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2068  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2069  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2070  }
2071 
2073  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2074 }
2075 
2076 SDValue MipsTargetLowering::
2077 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2078 {
2079  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2080  EVT Ty = Op.getValueType();
2081 
2082  if (!isPositionIndependent())
2083  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2084  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2085 
2086  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2087 }
2088 
2089 SDValue MipsTargetLowering::
2090 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2091 {
2092  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2093  EVT Ty = Op.getValueType();
2094 
2095  if (!isPositionIndependent()) {
2096  const MipsTargetObjectFile *TLOF =
2097  static_cast<const MipsTargetObjectFile *>(
2099 
2100  if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2101  getTargetMachine()))
2102  // %gp_rel relocation
2103  return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2104 
2105  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2106  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2107  }
2108 
2109  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2110 }
2111 
2112 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2113  MachineFunction &MF = DAG.getMachineFunction();
2114  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2115 
2116  SDLoc DL(Op);
2117  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2118  getPointerTy(MF.getDataLayout()));
2119 
2120  // vastart just stores the address of the VarArgsFrameIndex slot into the
2121  // memory location argument.
2122  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2123  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2124  MachinePointerInfo(SV));
2125 }
2126 
2127 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2128  SDNode *Node = Op.getNode();
2129  EVT VT = Node->getValueType(0);
2130  SDValue Chain = Node->getOperand(0);
2131  SDValue VAListPtr = Node->getOperand(1);
2132  unsigned Align = Node->getConstantOperandVal(3);
2133  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2134  SDLoc DL(Node);
2135  unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2136 
2137  SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2138  VAListPtr, MachinePointerInfo(SV));
2139  SDValue VAList = VAListLoad;
2140 
2141  // Re-align the pointer if necessary.
2142  // It should only ever be necessary for 64-bit types on O32 since the minimum
2143  // argument alignment is the same as the maximum type alignment for N32/N64.
2144  //
2145  // FIXME: We currently align too often. The code generator doesn't notice
2146  // when the pointer is still aligned from the last va_arg (or pair of
2147  // va_args for the i64 on O32 case).
2148  if (Align > getMinStackArgumentAlignment()) {
2149  assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2150 
2151  VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2152  DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2153 
2154  VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2155  DAG.getConstant(-(int64_t)Align, DL,
2156  VAList.getValueType()));
2157  }
2158 
2159  // Increment the pointer, VAList, to the next vaarg.
2160  auto &TD = DAG.getDataLayout();
2161  unsigned ArgSizeInBytes =
2162  TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2163  SDValue Tmp3 =
2164  DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2165  DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2166  DL, VAList.getValueType()));
2167  // Store the incremented VAList to the legalized pointer
2168  Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2169  MachinePointerInfo(SV));
2170 
2171  // In big-endian mode we must adjust the pointer when the load size is smaller
2172  // than the argument slot size. We must also reduce the known alignment to
2173  // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2174  // the correct half of the slot, and reduce the alignment from 8 (slot
2175  // alignment) down to 4 (type alignment).
2176  if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2177  unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2178  VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2179  DAG.getIntPtrConstant(Adjustment, DL));
2180  }
2181  // Load the actual argument out of the pointer VAList
2182  return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2183 }
2184 
2186  bool HasExtractInsert) {
2187  EVT TyX = Op.getOperand(0).getValueType();
2188  EVT TyY = Op.getOperand(1).getValueType();
2189  SDLoc DL(Op);
2190  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2191  SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2192  SDValue Res;
2193 
2194  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2195  // to i32.
2196  SDValue X = (TyX == MVT::f32) ?
2197  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2199  Const1);
2200  SDValue Y = (TyY == MVT::f32) ?
2201  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2203  Const1);
2204 
2205  if (HasExtractInsert) {
2206  // ext E, Y, 31, 1 ; extract bit31 of Y
2207  // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2208  SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2209  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2210  } else {
2211  // sll SllX, X, 1
2212  // srl SrlX, SllX, 1
2213  // srl SrlY, Y, 31
2214  // sll SllY, SrlX, 31
2215  // or Or, SrlX, SllY
2216  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2217  SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2218  SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2219  SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2220  Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2221  }
2222 
2223  if (TyX == MVT::f32)
2224  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2225 
2227  Op.getOperand(0),
2228  DAG.getConstant(0, DL, MVT::i32));
2229  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2230 }
2231 
2233  bool HasExtractInsert) {
2234  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2235  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2236  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2237  SDLoc DL(Op);
2238  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2239 
2240  // Bitcast to integer nodes.
2241  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2242  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2243 
2244  if (HasExtractInsert) {
2245  // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2246  // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2247  SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2248  DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2249 
2250  if (WidthX > WidthY)
2251  E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2252  else if (WidthY > WidthX)
2253  E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2254 
2255  SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2256  DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2257  X);
2258  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2259  }
2260 
2261  // (d)sll SllX, X, 1
2262  // (d)srl SrlX, SllX, 1
2263  // (d)srl SrlY, Y, width(Y)-1
2264  // (d)sll SllY, SrlX, width(Y)-1
2265  // or Or, SrlX, SllY
2266  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2267  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2268  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2269  DAG.getConstant(WidthY - 1, DL, MVT::i32));
2270 
2271  if (WidthX > WidthY)
2272  SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2273  else if (WidthY > WidthX)
2274  SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2275 
2276  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2277  DAG.getConstant(WidthX - 1, DL, MVT::i32));
2278  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2279  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2280 }
2281 
2282 SDValue
2283 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2284  if (Subtarget.isGP64bit())
2285  return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2286 
2287  return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2288 }
2289 
2290 SDValue MipsTargetLowering::
2291 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2292  // check the depth
2293  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2294  "Frame address can only be determined for current frame.");
2295 
2297  MFI.setFrameAddressIsTaken(true);
2298  EVT VT = Op.getValueType();
2299  SDLoc DL(Op);
2300  SDValue FrameAddr = DAG.getCopyFromReg(
2301  DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2302  return FrameAddr;
2303 }
2304 
2305 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2306  SelectionDAG &DAG) const {
2308  return SDValue();
2309 
2310  // check the depth
2311  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2312  "Return address can be determined only for current frame.");
2313 
2314  MachineFunction &MF = DAG.getMachineFunction();
2315  MachineFrameInfo &MFI = MF.getFrameInfo();
2316  MVT VT = Op.getSimpleValueType();
2317  unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2318  MFI.setReturnAddressIsTaken(true);
2319 
2320  // Return RA, which contains the return address. Mark it an implicit live-in.
2321  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2322  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2323 }
2324 
2325 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2326 // generated from __builtin_eh_return (offset, handler)
2327 // The effect of this is to adjust the stack pointer by "offset"
2328 // and then branch to "handler".
2329 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2330  const {
2331  MachineFunction &MF = DAG.getMachineFunction();
2332  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2333 
2334  MipsFI->setCallsEhReturn();
2335  SDValue Chain = Op.getOperand(0);
2336  SDValue Offset = Op.getOperand(1);
2337  SDValue Handler = Op.getOperand(2);
2338  SDLoc DL(Op);
2339  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2340 
2341  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2342  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2343  unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2344  unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2345  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2346  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2347  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2348  DAG.getRegister(OffsetReg, Ty),
2349  DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2350  Chain.getValue(1));
2351 }
2352 
2353 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2354  SelectionDAG &DAG) const {
2355  // FIXME: Need pseudo-fence for 'singlethread' fences
2356  // FIXME: Set SType for weaker fences where supported/appropriate.
2357  unsigned SType = 0;
2358  SDLoc DL(Op);
2359  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2360  DAG.getConstant(SType, DL, MVT::i32));
2361 }
2362 
2363 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2364  SelectionDAG &DAG) const {
2365  SDLoc DL(Op);
2367 
2368  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2369  SDValue Shamt = Op.getOperand(2);
2370  // if shamt < (VT.bits):
2371  // lo = (shl lo, shamt)
2372  // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2373  // else:
2374  // lo = 0
2375  // hi = (shl lo, shamt[4:0])
2376  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2377  DAG.getConstant(-1, DL, MVT::i32));
2378  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2379  DAG.getConstant(1, DL, VT));
2380  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2381  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2382  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2383  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2384  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2385  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2386  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2387  DAG.getConstant(0, DL, VT), ShiftLeftLo);
2388  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2389 
2390  SDValue Ops[2] = {Lo, Hi};
2391  return DAG.getMergeValues(Ops, DL);
2392 }
2393 
2394 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2395  bool IsSRA) const {
2396  SDLoc DL(Op);
2397  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2398  SDValue Shamt = Op.getOperand(2);
2400 
2401  // if shamt < (VT.bits):
2402  // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2403  // if isSRA:
2404  // hi = (sra hi, shamt)
2405  // else:
2406  // hi = (srl hi, shamt)
2407  // else:
2408  // if isSRA:
2409  // lo = (sra hi, shamt[4:0])
2410  // hi = (sra hi, 31)
2411  // else:
2412  // lo = (srl hi, shamt[4:0])
2413  // hi = 0
2414  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2415  DAG.getConstant(-1, DL, MVT::i32));
2416  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2417  DAG.getConstant(1, DL, VT));
2418  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2419  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2420  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2421  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2422  DL, VT, Hi, Shamt);
2423  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2424  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2425  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2426  DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2427  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2428  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2429  IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2430 
2431  SDValue Ops[2] = {Lo, Hi};
2432  return DAG.getMergeValues(Ops, DL);
2433 }
2434 
2435 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2436  SDValue Chain, SDValue Src, unsigned Offset) {
2437  SDValue Ptr = LD->getBasePtr();
2438  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2439  EVT BasePtrVT = Ptr.getValueType();
2440  SDLoc DL(LD);
2441  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2442 
2443  if (Offset)
2444  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2445  DAG.getConstant(Offset, DL, BasePtrVT));
2446 
2447  SDValue Ops[] = { Chain, Ptr, Src };
2448  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2449  LD->getMemOperand());
2450 }
2451 
2452 // Expand an unaligned 32 or 64-bit integer load node.
2454  LoadSDNode *LD = cast<LoadSDNode>(Op);
2455  EVT MemVT = LD->getMemoryVT();
2456 
2458  return Op;
2459 
2460  // Return if load is aligned or if MemVT is neither i32 nor i64.
2461  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2462  ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2463  return SDValue();
2464 
2465  bool IsLittle = Subtarget.isLittle();
2466  EVT VT = Op.getValueType();
2467  ISD::LoadExtType ExtType = LD->getExtensionType();
2468  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2469 
2470  assert((VT == MVT::i32) || (VT == MVT::i64));
2471 
2472  // Expand
2473  // (set dst, (i64 (load baseptr)))
2474  // to
2475  // (set tmp, (ldl (add baseptr, 7), undef))
2476  // (set dst, (ldr baseptr, tmp))
2477  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2478  SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2479  IsLittle ? 7 : 0);
2480  return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2481  IsLittle ? 0 : 7);
2482  }
2483 
2484  SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2485  IsLittle ? 3 : 0);
2486  SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2487  IsLittle ? 0 : 3);
2488 
2489  // Expand
2490  // (set dst, (i32 (load baseptr))) or
2491  // (set dst, (i64 (sextload baseptr))) or
2492  // (set dst, (i64 (extload baseptr)))
2493  // to
2494  // (set tmp, (lwl (add baseptr, 3), undef))
2495  // (set dst, (lwr baseptr, tmp))
2496  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2497  (ExtType == ISD::EXTLOAD))
2498  return LWR;
2499 
2500  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2501 
2502  // Expand
2503  // (set dst, (i64 (zextload baseptr)))
2504  // to
2505  // (set tmp0, (lwl (add baseptr, 3), undef))
2506  // (set tmp1, (lwr baseptr, tmp0))
2507  // (set tmp2, (shl tmp1, 32))
2508  // (set dst, (srl tmp2, 32))
2509  SDLoc DL(LD);
2510  SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2511  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2512  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2513  SDValue Ops[] = { SRL, LWR.getValue(1) };
2514  return DAG.getMergeValues(Ops, DL);
2515 }
2516 
2517 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2518  SDValue Chain, unsigned Offset) {
2519  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2520  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2521  SDLoc DL(SD);
2522  SDVTList VTList = DAG.getVTList(MVT::Other);
2523 
2524  if (Offset)
2525  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2526  DAG.getConstant(Offset, DL, BasePtrVT));
2527 
2528  SDValue Ops[] = { Chain, Value, Ptr };
2529  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2530  SD->getMemOperand());
2531 }
2532 
2533 // Expand an unaligned 32 or 64-bit integer store node.
2535  bool IsLittle) {
2536  SDValue Value = SD->getValue(), Chain = SD->getChain();
2537  EVT VT = Value.getValueType();
2538 
2539  // Expand
2540  // (store val, baseptr) or
2541  // (truncstore val, baseptr)
2542  // to
2543  // (swl val, (add baseptr, 3))
2544  // (swr val, baseptr)
2545  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2546  SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2547  IsLittle ? 3 : 0);
2548  return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2549  }
2550 
2551  assert(VT == MVT::i64);
2552 
2553  // Expand
2554  // (store val, baseptr)
2555  // to
2556  // (sdl val, (add baseptr, 7))
2557  // (sdr val, baseptr)
2558  SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2559  return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2560 }
2561 
2562 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2564  SDValue Val = SD->getValue();
2565 
2566  if (Val.getOpcode() != ISD::FP_TO_SINT)
2567  return SDValue();
2568 
2570  SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2571  Val.getOperand(0));
2572  return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2573  SD->getPointerInfo(), SD->getAlignment(),
2574  SD->getMemOperand()->getFlags());
2575 }
2576 
2578  StoreSDNode *SD = cast<StoreSDNode>(Op);
2579  EVT MemVT = SD->getMemoryVT();
2580 
2581  // Lower unaligned integer stores.
2583  (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2584  ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2585  return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2586 
2587  return lowerFP_TO_SINT_STORE(SD, DAG);
2588 }
2589 
2590 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2591  SelectionDAG &DAG) const {
2592 
2593  // Return a fixed StackObject with offset 0 which points to the old stack
2594  // pointer.
2596  EVT ValTy = Op->getValueType(0);
2597  int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2598  return DAG.getFrameIndex(FI, ValTy);
2599 }
2600 
2601 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2602  SelectionDAG &DAG) const {
2604  SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2605  Op.getOperand(0));
2606  return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2607 }
2608 
2609 //===----------------------------------------------------------------------===//
2610 // Calling Convention Implementation
2611 //===----------------------------------------------------------------------===//
2612 
2613 //===----------------------------------------------------------------------===//
2614 // TODO: Implement a generic logic using tblgen that can support this.
2615 // Mips O32 ABI rules:
2616 // ---
2617 // i32 - Passed in A0, A1, A2, A3 and stack
2618 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2619 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2620 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2621 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2622 // not used, it must be shadowed. If only A3 is available, shadow it and
2623 // go to stack.
2624 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2625 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2626 // with the remainder spilled to the stack.
2627 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2628 // spilling the remainder to the stack.
2629 //
2630 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2631 //===----------------------------------------------------------------------===//
2632 
2633 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2634  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2635  CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2636  const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2637  State.getMachineFunction().getSubtarget());
2638 
2639  static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2640 
2641  const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2642 
2643  static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2644 
2645  static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2646 
2647  // Do not process byval args here.
2648  if (ArgFlags.isByVal())
2649  return true;
2650 
2651  // Promote i8 and i16
2652  if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2653  if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2654  LocVT = MVT::i32;
2655  if (ArgFlags.isSExt())
2656  LocInfo = CCValAssign::SExtUpper;
2657  else if (ArgFlags.isZExt())
2658  LocInfo = CCValAssign::ZExtUpper;
2659  else
2660  LocInfo = CCValAssign::AExtUpper;
2661  }
2662  }
2663 
2664  // Promote i8 and i16
2665  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2666  LocVT = MVT::i32;
2667  if (ArgFlags.isSExt())
2668  LocInfo = CCValAssign::SExt;
2669  else if (ArgFlags.isZExt())
2670  LocInfo = CCValAssign::ZExt;
2671  else
2672  LocInfo = CCValAssign::AExt;
2673  }
2674 
2675  unsigned Reg;
2676 
2677  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2678  // is true: function is vararg, argument is 3rd or higher, there is previous
2679  // argument which is not f32 or f64.
2680  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2681  State.getFirstUnallocated(F32Regs) != ValNo;
2682  unsigned OrigAlign = ArgFlags.getOrigAlign();
2683  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2684  bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2685 
2686  // The MIPS vector ABI for floats passes them in a pair of registers
2687  if (ValVT == MVT::i32 && isVectorFloat) {
2688  // This is the start of an vector that was scalarized into an unknown number
2689  // of components. It doesn't matter how many there are. Allocate one of the
2690  // notional 8 byte aligned registers which map onto the argument stack, and
2691  // shadow the register lost to alignment requirements.
2692  if (ArgFlags.isSplit()) {
2693  Reg = State.AllocateReg(FloatVectorIntRegs);
2694  if (Reg == Mips::A2)
2695  State.AllocateReg(Mips::A1);
2696  else if (Reg == 0)
2697  State.AllocateReg(Mips::A3);
2698  } else {
2699  // If we're an intermediate component of the split, we can just attempt to
2700  // allocate a register directly.
2701  Reg = State.AllocateReg(IntRegs);
2702  }
2703  } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2704  Reg = State.AllocateReg(IntRegs);
2705  // If this is the first part of an i64 arg,
2706  // the allocated register must be either A0 or A2.
2707  if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2708  Reg = State.AllocateReg(IntRegs);
2709  LocVT = MVT::i32;
2710  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2711  // Allocate int register and shadow next int register. If first
2712  // available register is Mips::A1 or Mips::A3, shadow it too.
2713  Reg = State.AllocateReg(IntRegs);
2714  if (Reg == Mips::A1 || Reg == Mips::A3)
2715  Reg = State.AllocateReg(IntRegs);
2716  State.AllocateReg(IntRegs);
2717  LocVT = MVT::i32;
2718  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2719  // we are guaranteed to find an available float register
2720  if (ValVT == MVT::f32) {
2721  Reg = State.AllocateReg(F32Regs);
2722  // Shadow int register
2723  State.AllocateReg(IntRegs);
2724  } else {
2725  Reg = State.AllocateReg(F64Regs);
2726  // Shadow int registers
2727  unsigned Reg2 = State.AllocateReg(IntRegs);
2728  if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2729  State.AllocateReg(IntRegs);
2730  State.AllocateReg(IntRegs);
2731  }
2732  } else
2733  llvm_unreachable("Cannot handle this ValVT.");
2734 
2735  if (!Reg) {
2736  unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2737  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2738  } else
2739  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2740 
2741  return false;
2742 }
2743 
2744 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2745  MVT LocVT, CCValAssign::LocInfo LocInfo,
2746  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2747  static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2748 
2749  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2750 }
2751 
2752 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2753  MVT LocVT, CCValAssign::LocInfo LocInfo,
2754  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2755  static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2756 
2757  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2758 }
2759 
2760 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2761  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2763 
2764 #include "MipsGenCallingConv.inc"
2765 
2767  return CC_Mips;
2768  }
2769 
2771  return RetCC_Mips;
2772  }
2773 //===----------------------------------------------------------------------===//
2774 // Call Calling Convention Implementation
2775 //===----------------------------------------------------------------------===//
2776 
2777 // Return next O32 integer argument register.
2778 static unsigned getNextIntArgReg(unsigned Reg) {
2779  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2780  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2781 }
2782 
2783 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2784  SDValue Chain, SDValue Arg,
2785  const SDLoc &DL, bool IsTailCall,
2786  SelectionDAG &DAG) const {
2787  if (!IsTailCall) {
2788  SDValue PtrOff =
2789  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2790  DAG.getIntPtrConstant(Offset, DL));
2791  return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2792  }
2793 
2795  int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2796  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2797  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2798  /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2799 }
2800 
2803  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2804  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2805  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2806  SDValue Chain) const {
2807  // Insert node "GP copy globalreg" before call to function.
2808  //
2809  // R_MIPS_CALL* operators (emitted when non-internal functions are called
2810  // in PIC mode) allow symbols to be resolved via lazy binding.
2811  // The lazy binding stub requires GP to point to the GOT.
2812  // Note that we don't need GP to point to the GOT for indirect calls
2813  // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2814  // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2815  // used for the function (that is, Mips linker doesn't generate lazy binding
2816  // stub for a function whose address is taken in the program).
2817  if (IsPICCall && !InternalLinkage && IsCallReloc) {
2818  unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2819  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2820  RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2821  }
2822 
2823  // Build a sequence of copy-to-reg nodes chained together with token
2824  // chain and flag operands which copy the outgoing args into registers.
2825  // The InFlag in necessary since all emitted instructions must be
2826  // stuck together.
2827  SDValue InFlag;
2828 
2829  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2830  Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2831  RegsToPass[i].second, InFlag);
2832  InFlag = Chain.getValue(1);
2833  }
2834 
2835  // Add argument registers to the end of the list so that they are
2836  // known live into the call.
2837  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2838  Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2839  RegsToPass[i].second.getValueType()));
2840 
2841  // Add a register mask operand representing the call-preserved registers.
2843  const uint32_t *Mask =
2845  assert(Mask && "Missing call preserved mask for calling convention");
2846  if (Subtarget.inMips16HardFloat()) {
2847  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2848  StringRef Sym = G->getGlobal()->getName();
2849  Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2850  if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2852  }
2853  }
2854  }
2855  Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2856 
2857  if (InFlag.getNode())
2858  Ops.push_back(InFlag);
2859 }
2860 
2861 /// LowerCall - functions arguments are copied from virtual regs to
2862 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2863 SDValue
2864 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2865  SmallVectorImpl<SDValue> &InVals) const {
2866  SelectionDAG &DAG = CLI.DAG;
2867  SDLoc DL = CLI.DL;
2869  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2871  SDValue Chain = CLI.Chain;
2872  SDValue Callee = CLI.Callee;
2873  bool &IsTailCall = CLI.IsTailCall;
2874  CallingConv::ID CallConv = CLI.CallConv;
2875  bool IsVarArg = CLI.IsVarArg;
2876 
2877  MachineFunction &MF = DAG.getMachineFunction();
2878  MachineFrameInfo &MFI = MF.getFrameInfo();
2880  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2881  bool IsPIC = isPositionIndependent();
2882 
2883  // Analyze operands of the call, assigning locations to each operand.
2885  MipsCCState CCInfo(
2886  CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2888 
2889  const ExternalSymbolSDNode *ES =
2890  dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
2891 
2892  // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
2893  // is during the lowering of a call with a byval argument which produces
2894  // a call to memcpy. For the O32 case, this causes the caller to allocate
2895  // stack space for the reserved argument area for the callee, then recursively
2896  // again for the memcpy call. In the NEWABI case, this doesn't occur as those
2897  // ABIs mandate that the callee allocates the reserved argument area. We do
2898  // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
2899  //
2900  // If the callee has a byval argument and memcpy is used, we are mandated
2901  // to already have produced a reserved argument area for the callee for O32.
2902  // Therefore, the reserved argument area can be reused for both calls.
2903  //
2904  // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
2905  // present, as we have yet to hook that node onto the chain.
2906  //
2907  // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
2908  // case. GCC does a similar trick, in that wherever possible, it calculates
2909  // the maximum out going argument area (including the reserved area), and
2910  // preallocates the stack space on entrance to the caller.
2911  //
2912  // FIXME: We should do the same for efficency and space.
2913 
2914  // Note: The check on the calling convention below must match
2915  // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
2916  bool MemcpyInByVal = ES &&
2917  StringRef(ES->getSymbol()) == StringRef("memcpy") &&
2918  CallConv != CallingConv::Fast &&
2919  Chain.getOpcode() == ISD::CALLSEQ_START;
2920 
2921  // Allocate the reserved argument area. It seems strange to do this from the
2922  // caller side but removing it breaks the frame size calculation.
2923  unsigned ReservedArgArea =
2924  MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
2925  CCInfo.AllocateStack(ReservedArgArea, 1);
2926 
2927  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
2928  ES ? ES->getSymbol() : nullptr);
2929 
2930  // Get a count of how many bytes are to be pushed on the stack.
2931  unsigned NextStackOffset = CCInfo.getNextStackOffset();
2932 
2933  // Check if it's really possible to do a tail call. Restrict it to functions
2934  // that are part of this compilation unit.
2935  bool InternalLinkage = false;
2936  if (IsTailCall) {
2937  IsTailCall = isEligibleForTailCallOptimization(
2938  CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2939  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2940  InternalLinkage = G->getGlobal()->hasInternalLinkage();
2941  IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
2942  G->getGlobal()->hasPrivateLinkage() ||
2943  G->getGlobal()->hasHiddenVisibility() ||
2944  G->getGlobal()->hasProtectedVisibility());
2945  }
2946  }
2947  if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
2948  report_fatal_error("failed to perform tail call elimination on a call "
2949  "site marked musttail");
2950 
2951  if (IsTailCall)
2952  ++NumTailCalls;
2953 
2954  // Chain is the output chain of the last Load/Store or CopyToReg node.
2955  // ByValChain is the output chain of the last Memcpy node created for copying
2956  // byval arguments to the stack.
2957  unsigned StackAlignment = TFL->getStackAlignment();
2958  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
2959  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2960 
2961  if (!(IsTailCall || MemcpyInByVal))
2962  Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
2963 
2964  SDValue StackPtr =
2965  DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2966  getPointerTy(DAG.getDataLayout()));
2967 
2968  std::deque<std::pair<unsigned, SDValue>> RegsToPass;
2969  SmallVector<SDValue, 8> MemOpChains;
2970 
2971  CCInfo.rewindByValRegsInfo();
2972 
2973  // Walk the register/memloc assignments, inserting copies/loads.
2974  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2975  SDValue Arg = OutVals[i];
2976  CCValAssign &VA = ArgLocs[i];
2977  MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2978  ISD::ArgFlagsTy Flags = Outs[i].Flags;
2979  bool UseUpperBits = false;
2980 
2981  // ByVal Arg.
2982  if (Flags.isByVal()) {
2983  unsigned FirstByValReg, LastByValReg;
2984  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2985  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2986 
2987  assert(Flags.getByValSize() &&
2988  "ByVal args of size 0 should have been ignored by front-end.");
2989  assert(ByValIdx < CCInfo.getInRegsParamsCount());
2990  assert(!IsTailCall &&
2991  "Do not tail-call optimize if there is a byval argument.");
2992  passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2993  FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2994  VA);
2995  CCInfo.nextInRegsParam();
2996  continue;
2997  }
2998 
2999  // Promote the value if needed.
3000  switch (VA.getLocInfo()) {
3001  default:
3002  llvm_unreachable("Unknown loc info!");
3003  case CCValAssign::Full:
3004  if (VA.isRegLoc()) {
3005  if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3006  (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3007  (ValVT == MVT::i64 && LocVT == MVT::f64))
3008  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3009  else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3011  Arg, DAG.getConstant(0, DL, MVT::i32));
3013  Arg, DAG.getConstant(1, DL, MVT::i32));
3014  if (!Subtarget.isLittle())
3015  std::swap(Lo, Hi);
3016  unsigned LocRegLo = VA.getLocReg();
3017  unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3018  RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3019  RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3020  continue;
3021  }
3022  }
3023  break;
3024  case CCValAssign::BCvt:
3025  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3026  break;
3028  UseUpperBits = true;
3030  case CCValAssign::SExt:
3031  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3032  break;
3034  UseUpperBits = true;
3036  case CCValAssign::ZExt:
3037  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3038  break;
3040  UseUpperBits = true;
3042  case CCValAssign::AExt:
3043  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3044  break;
3045  }
3046 
3047  if (UseUpperBits) {
3048  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3049  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3050  Arg = DAG.getNode(
3051  ISD::SHL, DL, VA.getLocVT(), Arg,
3052  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3053  }
3054 
3055  // Arguments that can be passed on register must be kept at
3056  // RegsToPass vector
3057  if (VA.isRegLoc()) {
3058  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3059  continue;
3060  }
3061 
3062  // Register can't get to this point...
3063  assert(VA.isMemLoc());
3064 
3065  // emit ISD::STORE whichs stores the
3066  // parameter value to a stack Location
3067  MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3068  Chain, Arg, DL, IsTailCall, DAG));
3069  }
3070 
3071  // Transform all store nodes into one single node because all store
3072  // nodes are independent of each other.
3073  if (!MemOpChains.empty())
3074  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3075 
3076  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3077  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3078  // node so that legalize doesn't hack it.
3079 
3080  EVT Ty = Callee.getValueType();
3081  bool GlobalOrExternal = false, IsCallReloc = false;
3082 
3083  // The long-calls feature is ignored in case of PIC.
3084  // While we do not support -mshared / -mno-shared properly,
3085  // ignore long-calls in case of -mabicalls too.
3086  if (!Subtarget.isABICalls() && !IsPIC) {
3087  // If the function should be called using "long call",
3088  // get its address into a register to prevent using
3089  // of the `jal` instruction for the direct call.
3090  if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3091  if (Subtarget.useLongCalls())
3092  Callee = Subtarget.hasSym32()
3093  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3094  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3095  } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3096  bool UseLongCalls = Subtarget.useLongCalls();
3097  // If the function has long-call/far/near attribute
3098  // it overrides command line switch pased to the backend.
3099  if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3100  if (F->hasFnAttribute("long-call"))
3101  UseLongCalls = true;
3102  else if (F->hasFnAttribute("short-call"))
3103  UseLongCalls = false;
3104  }
3105  if (UseLongCalls)
3106  Callee = Subtarget.hasSym32()
3107  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3108  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3109  }
3110  }
3111 
3112  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3113  if (IsPIC) {
3114  const GlobalValue *Val = G->getGlobal();
3115  InternalLinkage = Val->hasInternalLinkage();
3116 
3117  if (InternalLinkage)
3118  Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3119  else if (LargeGOT) {
3120  Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3121  MipsII::MO_CALL_LO16, Chain,
3122  FuncInfo->callPtrInfo(Val));
3123  IsCallReloc = true;
3124  } else {
3125  Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3126  FuncInfo->callPtrInfo(Val));
3127  IsCallReloc = true;
3128  }
3129  } else
3130  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3131  getPointerTy(DAG.getDataLayout()), 0,
3133  GlobalOrExternal = true;
3134  }
3135  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3136  const char *Sym = S->getSymbol();
3137 
3138  if (!IsPIC) // static
3139  Callee = DAG.getTargetExternalSymbol(
3141  else if (LargeGOT) {
3142  Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3143  MipsII::MO_CALL_LO16, Chain,
3144  FuncInfo->callPtrInfo(Sym));
3145  IsCallReloc = true;
3146  } else { // PIC
3147  Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3148  FuncInfo->callPtrInfo(Sym));
3149  IsCallReloc = true;
3150  }
3151 
3152  GlobalOrExternal = true;
3153  }
3154 
3155  SmallVector<SDValue, 8> Ops(1, Chain);
3156  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3157 
3158  getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3159  IsCallReloc, CLI, Callee, Chain);
3160 
3161  if (IsTailCall) {
3163  return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3164  }
3165 
3166  Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3167  SDValue InFlag = Chain.getValue(1);
3168 
3169  // Create the CALLSEQ_END node in the case of where it is not a call to
3170  // memcpy.
3171  if (!(MemcpyInByVal)) {
3172  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3173  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3174  InFlag = Chain.getValue(1);
3175  }
3176 
3177  // Handle result values, copying them out of physregs into vregs that we
3178  // return.
3179  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3180  InVals, CLI);
3181 }
3182 
3183 /// LowerCallResult - Lower the result values of a call into the
3184 /// appropriate copies out of appropriate physical registers.
3185 SDValue MipsTargetLowering::LowerCallResult(
3186  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3187  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3188  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3189  TargetLowering::CallLoweringInfo &CLI) const {
3190  // Assign locations to each value returned by this call.
3192  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3193  *DAG.getContext());
3194 
3195  const ExternalSymbolSDNode *ES =
3196  dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3197  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3198  ES ? ES->getSymbol() : nullptr);
3199 
3200  // Copy all of the result registers out of their specified physreg.
3201  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3202  CCValAssign &VA = RVLocs[i];
3203  assert(VA.isRegLoc() && "Can only return in registers!");
3204 
3205  SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3206  RVLocs[i].getLocVT(), InFlag);
3207  Chain = Val.getValue(1);
3208  InFlag = Val.getValue(2);
3209 
3210  if (VA.isUpperBitsInLoc()) {
3211  unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3212  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3213  unsigned Shift =
3215  Val = DAG.getNode(
3216  Shift, DL, VA.getLocVT(), Val,
3217  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3218  }
3219 
3220  switch (VA.getLocInfo()) {
3221  default:
3222  llvm_unreachable("Unknown loc info!");
3223  case CCValAssign::Full:
3224  break;
3225  case CCValAssign::BCvt:
3226  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3227  break;
3228  case CCValAssign::AExt:
3230  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3231  break;
3232  case CCValAssign::ZExt:
3234  Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3235  DAG.getValueType(VA.getValVT()));
3236  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3237  break;
3238  case CCValAssign::SExt:
3240  Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3241  DAG.getValueType(VA.getValVT()));
3242  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3243  break;
3244  }
3245 
3246  InVals.push_back(Val);
3247  }
3248 
3249  return Chain;
3250 }
3251 
3253  EVT ArgVT, const SDLoc &DL,
3254  SelectionDAG &DAG) {
3255  MVT LocVT = VA.getLocVT();
3256  EVT ValVT = VA.getValVT();
3257 
3258  // Shift into the upper bits if necessary.
3259  switch (VA.getLocInfo()) {
3260  default:
3261  break;
3264  case CCValAssign::ZExtUpper: {
3265  unsigned ValSizeInBits = ArgVT.getSizeInBits();
3266  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3267  unsigned Opcode =
3269  Val = DAG.getNode(
3270  Opcode, DL, VA.getLocVT(), Val,
3271  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3272  break;
3273  }
3274  }
3275 
3276  // If this is an value smaller than the argument slot size (32-bit for O32,
3277  // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3278  // size. Extract the value and insert any appropriate assertions regarding
3279  // sign/zero extension.
3280  switch (VA.getLocInfo()) {
3281  default:
3282  llvm_unreachable("Unknown loc info!");
3283  case CCValAssign::Full:
3284  break;
3286  case CCValAssign::AExt:
3287  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3288  break;
3290  case CCValAssign::SExt:
3291  Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3292  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3293  break;
3295  case CCValAssign::ZExt:
3296  Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3297  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3298  break;
3299  case CCValAssign::BCvt:
3300  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3301  break;
3302  }
3303 
3304  return Val;
3305 }
3306 
3307 //===----------------------------------------------------------------------===//
3308 // Formal Arguments Calling Convention Implementation
3309 //===----------------------------------------------------------------------===//
3310 /// LowerFormalArguments - transform physical registers into virtual registers
3311 /// and generate load operations for arguments places on the stack.
3312 SDValue MipsTargetLowering::LowerFormalArguments(
3313  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3314  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3315  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3316  MachineFunction &MF = DAG.getMachineFunction();
3317  MachineFrameInfo &MFI = MF.getFrameInfo();
3318  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3319 
3320  MipsFI->setVarArgsFrameIndex(0);
3321 
3322  // Used with vargs to acumulate store chains.
3323  std::vector<SDValue> OutChains;
3324 
3325  // Assign locations to all of the incoming arguments.
3327  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3328  *DAG.getContext());
3329  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3330  const Function &Func = DAG.getMachineFunction().getFunction();
3331  Function::const_arg_iterator FuncArg = Func.arg_begin();
3332 
3333  if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3335  "Functions with the interrupt attribute cannot have arguments!");
3336 
3337  CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3338  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3339  CCInfo.getInRegsParamsCount() > 0);
3340 
3341  unsigned CurArgIdx = 0;
3342  CCInfo.rewindByValRegsInfo();
3343 
3344  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3345  CCValAssign &VA = ArgLocs[i];
3346  if (Ins[i].isOrigArg()) {
3347  std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3348  CurArgIdx = Ins[i].getOrigArgIndex();
3349  }
3350  EVT ValVT = VA.getValVT();
3351  ISD::ArgFlagsTy Flags = Ins[i].Flags;
3352  bool IsRegLoc = VA.isRegLoc();
3353 
3354  if (Flags.isByVal()) {
3355  assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3356  unsigned FirstByValReg, LastByValReg;
3357  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3358  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3359 
3360  assert(Flags.getByValSize() &&
3361  "ByVal args of size 0 should have been ignored by front-end.");
3362  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3363  copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3364  FirstByValReg, LastByValReg, VA, CCInfo);
3365  CCInfo.nextInRegsParam();
3366  continue;
3367  }
3368 
3369  // Arguments stored on registers
3370  if (IsRegLoc) {
3371  MVT RegVT = VA.getLocVT();
3372  unsigned ArgReg = VA.getLocReg();
3373  const TargetRegisterClass *RC = getRegClassFor(RegVT);
3374 
3375  // Transform the arguments stored on
3376  // physical registers into virtual ones
3377  unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3378  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3379 
3380  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3381 
3382  // Handle floating point arguments passed in integer registers and
3383  // long double arguments passed in floating point registers.
3384  if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3385  (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3386  (RegVT == MVT::f64 && ValVT == MVT::i64))
3387  ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3388  else if (ABI.IsO32() && RegVT == MVT::i32 &&
3389  ValVT == MVT::f64) {
3390  unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3391  getNextIntArgReg(ArgReg), RC);
3392  SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3393  if (!Subtarget.isLittle())
3394  std::swap(ArgValue, ArgValue2);
3395  ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3396  ArgValue, ArgValue2);
3397  }
3398 
3399  InVals.push_back(ArgValue);
3400  } else { // VA.isRegLoc()
3401  MVT LocVT = VA.getLocVT();
3402 
3403  if (ABI.IsO32()) {
3404  // We ought to be able to use LocVT directly but O32 sets it to i32
3405  // when allocating floating point values to integer registers.
3406  // This shouldn't influence how we load the value into registers unless
3407  // we are targeting softfloat.
3409  LocVT = VA.getValVT();
3410  }
3411 
3412  // sanity check
3413  assert(VA.isMemLoc());
3414 
3415  // The stack pointer offset is relative to the caller stack frame.
3416  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3417  VA.getLocMemOffset(), true);
3418 
3419  // Create load nodes to retrieve arguments from the stack
3420  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3421  SDValue ArgValue = DAG.getLoad(
3422  LocVT, DL, Chain, FIN,
3424  OutChains.push_back(ArgValue.getValue(1));
3425 
3426  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3427 
3428  InVals.push_back(ArgValue);
3429  }
3430  }
3431 
3432  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3433  // The mips ABIs for returning structs by value requires that we copy
3434  // the sret argument into $v0 for the return. Save the argument into
3435  // a virtual register so that we can access it from the return points.
3436  if (Ins[i].Flags.isSRet()) {
3437  unsigned Reg = MipsFI->getSRetReturnReg();
3438  if (!Reg) {
3439  Reg = MF.getRegInfo().createVirtualRegister(
3441  MipsFI->setSRetReturnReg(Reg);
3442  }
3443  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3444  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3445  break;
3446  }
3447  }
3448 
3449  if (IsVarArg)
3450  writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3451 
3452  // All stores are grouped in one node to allow the matching between
3453  // the size of Ins and InVals. This only happens when on varg functions
3454  if (!OutChains.empty()) {
3455  OutChains.push_back(Chain);
3456  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3457  }
3458 
3459  return Chain;
3460 }
3461 
3462 //===----------------------------------------------------------------------===//
3463 // Return Value Calling Convention Implementation
3464 //===----------------------------------------------------------------------===//
3465 
3466 bool
3467 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3468  MachineFunction &MF, bool IsVarArg,
3469  const SmallVectorImpl<ISD::OutputArg> &Outs,
3470  LLVMContext &Context) const {
3472  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3473  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3474 }
3475 
3476 bool
3477 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3478  if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3479  return true;
3480 
3481  return IsSigned;
3482 }
3483 
3484 SDValue
3485 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3486  const SDLoc &DL,
3487  SelectionDAG &DAG) const {
3488  MachineFunction &MF = DAG.getMachineFunction();
3489  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3490 
3491  MipsFI->setISR();
3492 
3493  return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3494 }
3495 
3496 SDValue
3497 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3498  bool IsVarArg,
3499  const SmallVectorImpl<ISD::OutputArg> &Outs,
3500  const SmallVectorImpl<SDValue> &OutVals,
3501  const SDLoc &DL, SelectionDAG &DAG) const {
3502  // CCValAssign - represent the assignment of
3503  // the return value to a location
3505  MachineFunction &MF = DAG.getMachineFunction();
3506 
3507  // CCState - Info about the registers and stack slot.
3508  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3509 
3510  // Analyze return values.
3511  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3512 
3513  SDValue Flag;
3514  SmallVector<SDValue, 4> RetOps(1, Chain);
3515 
3516  // Copy the result values into the output registers.
3517  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3518  SDValue Val = OutVals[i];
3519  CCValAssign &VA = RVLocs[i];
3520  assert(VA.isRegLoc() && "Can only return in registers!");
3521  bool UseUpperBits = false;
3522 
3523  switch (VA.getLocInfo()) {
3524  default:
3525  llvm_unreachable("Unknown loc info!");
3526  case CCValAssign::Full:
3527  break;
3528  case CCValAssign::BCvt:
3529  Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3530  break;
3532  UseUpperBits = true;
3534  case CCValAssign::AExt:
3535  Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3536  break;
3538  UseUpperBits = true;
3540  case CCValAssign::ZExt:
3541  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3542  break;
3544  UseUpperBits = true;
3546  case CCValAssign::SExt:
3547  Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3548  break;
3549  }
3550 
3551  if (UseUpperBits) {
3552  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3553  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3554  Val = DAG.getNode(
3555  ISD::SHL, DL, VA.getLocVT(), Val,
3556  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3557  }
3558 
3559  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3560 
3561  // Guarantee that all emitted copies are stuck together with flags.
3562  Flag = Chain.getValue(1);
3563  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3564  }
3565 
3566  // The mips ABIs for returning structs by value requires that we copy
3567  // the sret argument into $v0 for the return. We saved the argument into
3568  // a virtual register in the entry block, so now we copy the value out
3569  // and into $v0.
3570  if (MF.getFunction().hasStructRetAttr()) {
3571  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3572  unsigned Reg = MipsFI->getSRetReturnReg();
3573 
3574  if (!Reg)
3575  llvm_unreachable("sret virtual register not created in the entry block");
3576  SDValue Val =
3577  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3578  unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3579 
3580  Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3581  Flag = Chain.getValue(1);
3582  RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3583  }
3584 
3585  RetOps[0] = Chain; // Update chain.
3586 
3587  // Add the flag if we have it.
3588  if (Flag.getNode())
3589  RetOps.push_back(Flag);
3590 
3591  // ISRs must use "eret".
3592  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3593  return LowerInterruptReturn(RetOps, DL, DAG);
3594 
3595  // Standard return on Mips is a "jr $ra"
3596  return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3597 }
3598 
3599 //===----------------------------------------------------------------------===//
3600 // Mips Inline Assembly Support
3601 //===----------------------------------------------------------------------===//
3602 
3603 /// getConstraintType - Given a constraint letter, return the type of
3604 /// constraint it is for this target.
3606 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3607  // Mips specific constraints
3608  // GCC config/mips/constraints.md
3609  //
3610  // 'd' : An address register. Equivalent to r
3611  // unless generating MIPS16 code.
3612  // 'y' : Equivalent to r; retained for
3613  // backwards compatibility.
3614  // 'c' : A register suitable for use in an indirect
3615  // jump. This will always be $25 for -mabicalls.
3616  // 'l' : The lo register. 1 word storage.
3617  // 'x' : The hilo register pair. Double word storage.
3618  if (Constraint.size() == 1) {
3619  switch (Constraint[0]) {
3620  default : break;
3621  case 'd':
3622  case 'y':
3623  case 'f':
3624  case 'c':
3625  case 'l':
3626  case 'x':
3627  return C_RegisterClass;
3628  case 'R':
3629  return C_Memory;
3630  }
3631  }
3632 
3633  if (Constraint == "ZC")
3634  return C_Memory;
3635 
3636  return TargetLowering::getConstraintType(Constraint);
3637 }
3638 
3639 /// Examine constraint type and operand type and determine a weight value.
3640 /// This object must already have been set up with the operand type
3641 /// and the current alternative constraint selected.
3643 MipsTargetLowering::getSingleConstraintMatchWeight(
3644  AsmOperandInfo &info, const char *constraint) const {
3645  ConstraintWeight weight = CW_Invalid;
3646  Value *CallOperandVal = info.CallOperandVal;
3647  // If we don't have a value, we can't do a match,
3648  // but allow it at the lowest weight.
3649  if (!CallOperandVal)
3650  return CW_Default;
3651  Type *type = CallOperandVal->getType();
3652  // Look at the constraint type.
3653  switch (*constraint) {
3654  default:
3655  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3656  break;
3657  case 'd':
3658  case 'y':
3659  if (type->isIntegerTy())
3660  weight = CW_Register;
3661  break;
3662  case 'f': // FPU or MSA register
3663  if (Subtarget.hasMSA() && type->isVectorTy() &&
3664  cast<VectorType>(type)->getBitWidth() == 128)
3665  weight = CW_Register;
3666  else if (type->isFloatTy())
3667  weight = CW_Register;
3668  break;
3669  case 'c': // $25 for indirect jumps
3670  case 'l': // lo register
3671  case 'x': // hilo register pair
3672  if (type->isIntegerTy())
3673  weight = CW_SpecificReg;
3674  break;
3675  case 'I': // signed 16 bit immediate
3676  case 'J': // integer zero
3677  case 'K': // unsigned 16 bit immediate
3678  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3679  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3680  case 'O': // signed 15 bit immediate (+- 16383)
3681  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3682  if (isa<ConstantInt>(CallOperandVal))
3683  weight = CW_Constant;
3684  break;
3685  case 'R':
3686  weight = CW_Memory;
3687  break;
3688  }
3689  return weight;
3690 }
3691 
3692 /// This is a helper function to parse a physical register string and split it
3693 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3694 /// that is returned indicates whether parsing was successful. The second flag
3695 /// is true if the numeric part exists.
3696 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3697  unsigned long long &Reg) {
3698  if (C.front() != '{' || C.back() != '}')
3699  return std::make_pair(false, false);
3700 
3701  // Search for the first numeric character.
3702  StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3703  I = std::find_if(B, E, isdigit);
3704 
3705  Prefix = StringRef(B, I - B);
3706 
3707  // The second flag is set to false if no numeric characters were found.
3708  if (I == E)
3709  return std::make_pair(true, false);
3710 
3711  // Parse the numeric characters.
3712  return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3713  true);
3714 }
3715 
3716 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3717 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3718  const TargetRegisterInfo *TRI =
3720  const TargetRegisterClass *RC;
3721  StringRef Prefix;
3722  unsigned long long Reg;
3723 
3724  std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3725 
3726  if (!R.first)
3727  return std::make_pair(0U, nullptr);
3728 
3729  if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3730  // No numeric characters follow "hi" or "lo".
3731  if (R.second)
3732  return std::make_pair(0U, nullptr);
3733 
3734  RC = TRI->getRegClass(Prefix == "hi" ?
3735  Mips::HI32RegClassID : Mips::LO32RegClassID);
3736  return std::make_pair(*(RC->begin()), RC);
3737  } else if (Prefix.startswith("$msa")) {
3738  // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3739 
3740  // No numeric characters follow the name.
3741  if (R.second)
3742  return std::make_pair(0U, nullptr);
3743 
3745  .Case("$msair", Mips::MSAIR)
3746  .Case("$msacsr", Mips::MSACSR)
3747  .Case("$msaaccess", Mips::MSAAccess)
3748  .Case("$msasave", Mips::MSASave)
3749  .Case("$msamodify", Mips::MSAModify)
3750  .Case("$msarequest", Mips::MSARequest)
3751  .Case("$msamap", Mips::MSAMap)
3752  .Case("$msaunmap", Mips::MSAUnmap)
3753  .Default(0);
3754 
3755  if (!Reg)
3756  return std::make_pair(0U, nullptr);
3757 
3758  RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3759  return std::make_pair(Reg, RC);
3760  }
3761 
3762  if (!R.second)
3763  return std::make_pair(0U, nullptr);
3764 
3765  if (Prefix == "$f") { // Parse $f0-$f31.
3766  // If the size of FP registers is 64-bit or Reg is an even number, select
3767  // the 64-bit register class. Otherwise, select the 32-bit register class.
3768  if (VT == MVT::Other)
3769  VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3770 
3771  RC = getRegClassFor(VT);
3772 
3773  if (RC == &Mips::AFGR64RegClass) {
3774  assert(Reg % 2 == 0);
3775  Reg >>= 1;
3776  }
3777  } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3778  RC = TRI->getRegClass(Mips::FCCRegClassID);
3779  else if (Prefix == "$w") { // Parse $w0-$w31.
3780  RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3781  } else { // Parse $0-$31.
3782  assert(Prefix == "$");
3783  RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3784  }
3785 
3786  assert(Reg < RC->getNumRegs());
3787  return std::make_pair(*(RC->begin() + Reg), RC);
3788 }
3789 
3790 /// Given a register class constraint, like 'r', if this corresponds directly
3791 /// to an LLVM register class, return a register of 0 and the register class
3792 /// pointer.
3793 std::pair<unsigned, const TargetRegisterClass *>
3794 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3795  StringRef Constraint,
3796  MVT VT) const {
3797  if (Constraint.size() == 1) {
3798  switch (Constraint[0]) {
3799  case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3800  case 'y': // Same as 'r'. Exists for compatibility.
3801  case 'r':
3802  if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3803  if (Subtarget.inMips16Mode())
3804  return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3805  return std::make_pair(0U, &Mips::GPR32RegClass);
3806  }
3807  if (VT == MVT::i64 && !Subtarget.isGP64bit())
3808  return std::make_pair(0U, &Mips::GPR32RegClass);
3809  if (VT == MVT::i64 && Subtarget.isGP64bit())
3810  return std::make_pair(0U, &Mips::GPR64RegClass);
3811  // This will generate an error message
3812  return std::make_pair(0U, nullptr);
3813  case 'f': // FPU or MSA register
3814  if (VT == MVT::v16i8)
3815  return std::make_pair(0U, &Mips::MSA128BRegClass);
3816  else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3817  return std::make_pair(0U, &Mips::MSA128HRegClass);
3818  else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3819  return std::make_pair(0U, &Mips::MSA128WRegClass);
3820  else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3821  return std::make_pair(0U, &Mips::MSA128DRegClass);
3822  else if (VT == MVT::f32)
3823  return std::make_pair(0U, &Mips::FGR32RegClass);
3824  else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3825  if (Subtarget.isFP64bit())
3826  return std::make_pair(0U, &Mips::FGR64RegClass);
3827  return std::make_pair(0U, &Mips::AFGR64RegClass);
3828  }
3829  break;
3830  case 'c': // register suitable for indirect jump
3831  if (VT == MVT::i32)
3832  return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3833  if (VT == MVT::i64)
3834  return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3835  // This will generate an error message
3836  return std::make_pair(0U, nullptr);
3837  case 'l': // use the `lo` register to store values
3838  // that are no bigger than a word
3839  if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3840  return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3841  return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3842  case 'x': // use the concatenated `hi` and `lo` registers
3843  // to store doubleword values
3844  // Fixme: Not triggering the use of both hi and low
3845  // This will generate an error message
3846  return std::make_pair(0U, nullptr);
3847  }
3848  }
3849 
3850  std::pair<unsigned, const TargetRegisterClass *> R;
3851  R = parseRegForInlineAsmConstraint(Constraint, VT);
3852 
3853  if (R.second)
3854  return R;
3855 
3856  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3857 }
3858 
3859 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3860 /// vector. If it is invalid, don't add anything to Ops.
3861 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3862  std::string &Constraint,
3863  std::vector<SDValue>&Ops,
3864  SelectionDAG &DAG) const {
3865  SDLoc DL(Op);
3866  SDValue Result;
3867 
3868  // Only support length 1 constraints for now.
3869  if (Constraint.length() > 1) return;
3870 
3871  char ConstraintLetter = Constraint[0];
3872  switch (ConstraintLetter) {
3873  default: break; // This will fall through to the generic implementation
3874  case 'I': // Signed 16 bit constant
3875  // If this fails, the parent routine will give an error
3876  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3877  EVT Type = Op.getValueType();
3878  int64_t Val = C->getSExtValue();
3879  if (isInt<16>(Val)) {
3880  Result = DAG.getTargetConstant(Val, DL, Type);
3881  break;
3882  }
3883  }
3884  return;
3885  case 'J': // integer zero
3886  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3887  EVT Type = Op.getValueType();
3888  int64_t Val = C->getZExtValue();
3889  if (Val == 0) {
3890  Result = DAG.getTargetConstant(0, DL, Type);
3891  break;
3892  }
3893  }
3894  return;
3895  case 'K': // unsigned 16 bit immediate
3896  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3897  EVT Type = Op.getValueType();
3898  uint64_t Val = (uint64_t)C->getZExtValue();
3899  if (isUInt<16>(Val)) {
3900  Result = DAG.getTargetConstant(Val, DL, Type);
3901  break;
3902  }
3903  }
3904  return;
3905  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3906  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3907  EVT Type = Op.getValueType();
3908  int64_t Val = C->getSExtValue();
3909  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3910  Result = DAG.getTargetConstant(Val, DL, Type);
3911  break;
3912  }
3913  }
3914  return;
3915  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3916  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3917  EVT Type = Op.getValueType();
3918  int64_t Val = C->getSExtValue();
3919  if ((Val >= -65535) && (Val <= -1)) {
3920  Result = DAG.getTargetConstant(Val, DL, Type);
3921  break;
3922  }
3923  }
3924  return;
3925  case 'O': // signed 15 bit immediate
3926  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3927  EVT Type = Op.getValueType();
3928  int64_t Val = C->getSExtValue();
3929  if ((isInt<15>(Val))) {
3930  Result = DAG.getTargetConstant(Val, DL, Type);
3931  break;
3932  }
3933  }
3934  return;
3935  case 'P': // immediate in the range of 1 to 65535 (inclusive)
3936  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3937  EVT Type = Op.getValueType();
3938  int64_t Val = C->getSExtValue();
3939  if ((Val <= 65535) && (Val >= 1)) {
3940  Result = DAG.getTargetConstant(Val, DL, Type);
3941  break;
3942  }
3943  }
3944  return;
3945  }
3946 
3947  if (Result.getNode()) {
3948  Ops.push_back(Result);
3949  return;
3950  }
3951 
3952  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3953 }
3954 
3955 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3956  const AddrMode &AM, Type *Ty,
3957  unsigned AS, Instruction *I) const {
3958  // No global is ever allowed as a base.
3959  if (AM.BaseGV)
3960  return false;
3961 
3962  switch (AM.Scale) {
3963  case 0: // "r+i" or just "i", depending on HasBaseReg.
3964  break;
3965  case 1:
3966  if (!AM.HasBaseReg) // allow "r+i".
3967  break;
3968  return false; // disallow "r+r" or "r+r+i".
3969  default:
3970  return false;
3971  }
3972 
3973  return true;
3974 }
3975 
3976 bool
3977 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3978  // The Mips target isn't yet aware of offsets.
3979  return false;
3980 }
3981 
3982 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3983  unsigned SrcAlign,
3984  bool IsMemset, bool ZeroMemset,
3985  bool MemcpyStrSrc,
3986  MachineFunction &MF) const {
3987  if (Subtarget.hasMips64())
3988  return MVT::i64;
3989 
3990  return MVT::i32;
3991 }
3992 
3993 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3994  if (VT != MVT::f32 && VT != MVT::f64)
3995  return false;
3996  if (Imm.isNegZero())
3997  return false;
3998  return Imm.isZero();
3999 }
4000 
4001 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4002 
4003  // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4004  if (ABI.IsN64() && isPositionIndependent())
4006 
4008 }
4009 
4010 bool MipsTargetLowering::useSoftFloat() const {
4011  return Subtarget.useSoftFloat();
4012 }
4013 
4014 void MipsTargetLowering::copyByValRegs(
4015  SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4016  SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4017  SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4018  unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4019  MipsCCState &State) const {
4020  MachineFunction &MF = DAG.getMachineFunction();
4021  MachineFrameInfo &MFI = MF.getFrameInfo();
4022  unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4023  unsigned NumRegs = LastReg - FirstReg;
4024  unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4025  unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4026  int FrameObjOffset;
4027  ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4028 
4029  if (RegAreaSize)
4030  FrameObjOffset =
4032  (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4033  else
4034  FrameObjOffset = VA.getLocMemOffset();
4035 
4036  // Create frame object.
4037  EVT PtrTy = getPointerTy(DAG.getDataLayout());
4038  // Make the fixed object stored to mutable so that the load instructions
4039  // referencing it have their memory dependencies added.
4040  // Set the frame object as isAliased which clears the underlying objects
4041  // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4042  // stores as dependencies for loads referencing this fixed object.
4043  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4044  SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4045  InVals.push_back(FIN);
4046 
4047  if (!NumRegs)
4048  return;
4049 
4050  // Copy arg registers.
4051  MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4052  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4053 
4054  for (unsigned I = 0; I < NumRegs; ++I) {
4055  unsigned ArgReg = ByValArgRegs[FirstReg + I];
4056  unsigned VReg = addLiveIn(MF, ArgReg, RC);
4057  unsigned Offset = I * GPRSizeInBytes;
4058  SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4059  DAG.getConstant(Offset, DL, PtrTy));
4060  SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4061  StorePtr, MachinePointerInfo(FuncArg, Offset));
4062  OutChains.push_back(Store);
4063  }
4064 }
4065 
4066 // Copy byVal arg to registers and stack.
4067 void MipsTargetLowering::passByValArg(
4068  SDValue Chain, const SDLoc &DL,
4069  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4070  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4071  MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4072  unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4073  const CCValAssign &VA) const {
4074  unsigned ByValSizeInBytes = Flags.getByValSize();
4075  unsigned OffsetInBytes = 0; // From beginning of struct
4076  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4077  unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4078  EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4079  RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4080  unsigned NumRegs = LastReg - FirstReg;
4081 
4082  if (NumRegs) {
4084  bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4085  unsigned I = 0;
4086 
4087  // Copy words to registers.
4088  for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4089  SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4090  DAG.getConstant(OffsetInBytes, DL, PtrTy));
4091  SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4092  MachinePointerInfo(), Alignment);
4093  MemOpChains.push_back(LoadVal.getValue(1));
4094  unsigned ArgReg = ArgRegs[FirstReg + I];
4095  RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4096  }
4097 
4098  // Return if the struct has been fully copied.
4099  if (ByValSizeInBytes == OffsetInBytes)
4100  return;
4101 
4102  // Copy the remainder of the byval argument with sub-word loads and shifts.
4103  if (LeftoverBytes) {
4104  SDValue Val;
4105 
4106  for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4107  OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4108  unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4109 
4110  if (RemainingSizeInBytes < LoadSizeInBytes)
4111  continue;
4112 
4113  // Load subword.
4114  SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4115  DAG.getConstant(OffsetInBytes, DL,
4116  PtrTy));
4117  SDValue LoadVal = DAG.getExtLoad(
4118  ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4119  MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4120  MemOpChains.push_back(LoadVal.getValue(1));
4121 
4122  // Shift the loaded value.
4123  unsigned Shamt;
4124 
4125  if (isLittle)
4126  Shamt = TotalBytesLoaded * 8;
4127  else
4128  Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4129 
4130  SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4131  DAG.getConstant(Shamt, DL, MVT::i32));
4132 
4133  if (Val.getNode())
4134  Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4135  else
4136  Val = Shift;
4137 
4138  OffsetInBytes += LoadSizeInBytes;
4139  TotalBytesLoaded += LoadSizeInBytes;
4140  Alignment = std::min(Alignment, LoadSizeInBytes);
4141  }
4142 
4143  unsigned ArgReg = ArgRegs[FirstReg + I];
4144  RegsToPass.push_back(std::make_pair(ArgReg, Val));
4145  return;
4146  }
4147  }
4148 
4149  // Copy remainder of byval arg to it with memcpy.
4150  unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4151  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4152  DAG.getConstant(OffsetInBytes, DL, PtrTy));
4153  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4154  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4155  Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4156  DAG.getConstant(MemCpySize, DL, PtrTy),
4157  Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4158  /*isTailCall=*/false,
4160  MemOpChains.push_back(Chain);
4161 }
4162 
4163 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4164  SDValue Chain, const SDLoc &DL,
4165  SelectionDAG &DAG,
4166  CCState &State) const {
4168  unsigned Idx = State.getFirstUnallocated(ArgRegs);
4169  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4170  MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4171  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4172  MachineFunction &MF = DAG.getMachineFunction();
4173  MachineFrameInfo &MFI = MF.getFrameInfo();
4174  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4175 
4176  // Offset of the first variable argument from stack pointer.
4177  int VaArgOffset;
4178 
4179  if (ArgRegs.size() == Idx)
4180  VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4181  else {
4182  VaArgOffset =
4184  (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4185  }
4186 
4187  // Record the frame index of the first variable argument
4188  // which is a value necessary to VASTART.
4189  int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4190  MipsFI->setVarArgsFrameIndex(FI);
4191 
4192  // Copy the integer registers that have not been used for argument passing
4193  // to the argument register save area. For O32, the save area is allocated
4194  // in the caller's stack frame, while for N32/64, it is allocated in the
4195  // callee's stack frame.
4196  for (unsigned I = Idx; I < ArgRegs.size();
4197  ++I, VaArgOffset += RegSizeInBytes) {
4198  unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4199  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4200  FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4201  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4202  SDValue Store =
4203  DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4204  cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4205  (Value *)nullptr);
4206  OutChains.push_back(Store);
4207  }
4208 }
4209 
4210 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4211  unsigned Align) const {
4213 
4214  assert(Size && "Byval argument's size shouldn't be 0.");
4215 
4216  Align = std::min(Align, TFL->getStackAlignment());
4217 
4218  unsigned FirstReg = 0;
4219  unsigned NumRegs = 0;
4220 
4221  if (State->getCallingConv() != CallingConv::Fast) {
4222  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4223  ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4224  // FIXME: The O32 case actually describes no shadow registers.
4225  const MCPhysReg *ShadowRegs =
4226  ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4227 
4228  // We used to check the size as well but we can't do that anymore since
4229  // CCState::HandleByVal() rounds up the size after calling this function.
4230  assert(!(Align % RegSizeInBytes) &&
4231  "Byval argument's alignment should be a multiple of"
4232  "RegSizeInBytes.");
4233 
4234  FirstReg = State->getFirstUnallocated(IntArgRegs);
4235 
4236  // If Align > RegSizeInBytes, the first arg register must be even.
4237  // FIXME: This condition happens to do the right thing but it's not the
4238  // right way to test it. We want to check that the stack frame offset
4239  // of the register is aligned.
4240  if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4241  State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4242  ++FirstReg;
4243  }
4244 
4245  // Mark the registers allocated.
4246  Size = alignTo(Size, RegSizeInBytes);
4247  for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4248  Size -= RegSizeInBytes, ++I, ++NumRegs)
4249  State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4250  }
4251 
4252  State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4253 }
4254 
4255 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4256  MachineBasicBlock *BB,
4257  bool isFPCmp,
4258  unsigned Opc) const {
4260  "Subtarget already supports SELECT nodes with the use of"
4261  "conditional-move instructions.");
4262 
4263  const TargetInstrInfo *TII =
4265  DebugLoc DL = MI.getDebugLoc();
4266 
4267  // To "insert" a SELECT instruction, we actually have to insert the
4268  // diamond control-flow pattern. The incoming instruction knows the
4269  // destination vreg to set, the condition code register to branch on, the
4270  // true/false values to select between, and a branch opcode to use.
4271  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4273 
4274  // thisMBB:
4275  // ...
4276  // TrueVal = ...
4277  // setcc r1, r2, r3
4278  // bNE r1, r0, copy1MBB
4279  // fallthrough --> copy0MBB
4280  MachineBasicBlock *thisMBB = BB;
4281  MachineFunction *F = BB->getParent();
4282  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4283  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4284  F->insert(It, copy0MBB);
4285  F->insert(It, sinkMBB);
4286 
4287  // Transfer the remainder of BB and its successor edges to sinkMBB.
4288  sinkMBB->splice(sinkMBB->begin(), BB,
4289  std::next(MachineBasicBlock::iterator(MI)), BB->end());
4290  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4291 
4292  // Next, add the true and fallthrough blocks as its successors.
4293  BB->addSuccessor(copy0MBB);
4294  BB->addSuccessor(sinkMBB);
4295 
4296  if (isFPCmp) {
4297  // bc1[tf] cc, sinkMBB
4298  BuildMI(BB, DL, TII->get(Opc))
4299  .addReg(MI.getOperand(1).getReg())
4300  .addMBB(sinkMBB);
4301  } else {
4302  // bne rs, $0, sinkMBB
4303  BuildMI(BB, DL, TII->get(Opc))
4304  .addReg(MI.getOperand(1).getReg())
4305  .addReg(Mips::ZERO)
4306  .addMBB(sinkMBB);
4307  }
4308 
4309  // copy0MBB:
4310  // %FalseValue = ...
4311  // # fallthrough to sinkMBB
4312  BB = copy0MBB;
4313 
4314  // Update machine-CFG edges
4315  BB->addSuccessor(sinkMBB);
4316 
4317  // sinkMBB:
4318  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4319  // ...
4320  BB = sinkMBB;
4321 
4322  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4323  .addReg(MI.getOperand(2).getReg())
4324  .addMBB(thisMBB)
4325  .addReg(MI.getOperand(3).getReg())
4326  .addMBB(copy0MBB);
4327 
4328  MI.eraseFromParent(); // The pseudo instruction is gone now.
4329 
4330  return BB;
4331 }
4332 
4333 // FIXME? Maybe this could be a TableGen attribute on some registers and
4334 // this table could be generated automatically from RegInfo.
4335 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4336  SelectionDAG &DAG) const {
4337  // Named registers is expected to be fairly rare. For now, just support $28
4338  // since the linux kernel uses it.
4339  if (Subtarget.isGP64bit()) {
4340  unsigned Reg = StringSwitch<unsigned>(RegName)
4341  .Case("$28", Mips::GP_64)
4342  .Default(0);
4343  if (Reg)
4344  return Reg;
4345  } else {
4346  unsigned Reg = StringSwitch<unsigned>(RegName)
4347  .Case("$28", Mips::GP)
4348  .Default(0);
4349  if (Reg)
4350  return Reg;
4351  }
4352  report_fatal_error("Invalid register name global variable");
4353 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type.
bool isABICalls() const
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:539
bool inMips16HardFloat() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
bool isZero() const
Definition: APFloat.h:1143
const GlobalValue * getGlobal() const
static const MCPhysReg IntRegs[32]
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:951
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:849
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MipsSubtarget & Subtarget
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:611
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
static MVT getVectorVT(MVT VT, unsigned NumElements)
iterator begin() const
begin/end - Return all of the registers in this class.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool inMips16Mode() const