LLVM  6.0.0svn
MipsISelLowering.cpp
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1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
17 #include "MipsCCState.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/ADT/StringSwitch.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/Support/Debug.h"
40 #include <cctype>
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "mips-lower"
45 
46 STATISTIC(NumTailCalls, "Number of tail calls");
47 
48 static cl::opt<bool>
49 LargeGOT("mxgot", cl::Hidden,
50  cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51 
52 static cl::opt<bool>
53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54  cl::desc("MIPS: Don't trap on integer division by zero."),
55  cl::init(false));
56 
57 static const MCPhysReg Mips64DPRegs[8] = {
58  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60 };
61 
62 // If I is a shifted mask, set the size (Size) and the first bit of the
63 // mask (Pos), and return true.
64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66  if (!isShiftedMask_64(I))
67  return false;
68 
69  Size = countPopulation(I);
70  Pos = countTrailingZeros(I);
71  return true;
72 }
73 
74 // The MIPS MSA ABI passes vector arguments in the integer register set.
75 // The number of integer registers used is dependant on the ABI used.
77  if (VT.isVector() && Subtarget.hasMSA())
78  return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
80 }
81 
83  EVT VT) const {
84  if (VT.isVector()) {
85  if (Subtarget.isABI_O32()) {
86  return MVT::i32;
87  } else {
88  return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
89  }
90  }
91  return MipsTargetLowering::getRegisterType(Context, VT);
92 }
93 
95  EVT VT) const {
96  if (VT.isVector())
97  return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
98  1U);
99  return MipsTargetLowering::getNumRegisters(Context, VT);
100 }
101 
103  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
104  unsigned &NumIntermediates, MVT &RegisterVT) const {
105 
106  // Break down vector types to either 2 i64s or 4 i32s.
107  RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
108  IntermediateVT = RegisterVT;
109  NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
110  ? VT.getVectorNumElements()
111  : VT.getSizeInBits() / RegisterVT.getSizeInBits();
112 
113  return NumIntermediates;
114 }
115 
118  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
119 }
120 
121 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
122  SelectionDAG &DAG,
123  unsigned Flag) const {
124  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
125 }
126 
127 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
128  SelectionDAG &DAG,
129  unsigned Flag) const {
130  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
131 }
132 
133 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
134  SelectionDAG &DAG,
135  unsigned Flag) const {
136  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
137 }
138 
139 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
140  SelectionDAG &DAG,
141  unsigned Flag) const {
142  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
143 }
144 
145 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
146  SelectionDAG &DAG,
147  unsigned Flag) const {
148  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
149  N->getOffset(), Flag);
150 }
151 
152 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
153  switch ((MipsISD::NodeType)Opcode) {
154  case MipsISD::FIRST_NUMBER: break;
155  case MipsISD::JmpLink: return "MipsISD::JmpLink";
156  case MipsISD::TailCall: return "MipsISD::TailCall";
157  case MipsISD::Highest: return "MipsISD::Highest";
158  case MipsISD::Higher: return "MipsISD::Higher";
159  case MipsISD::Hi: return "MipsISD::Hi";
160  case MipsISD::Lo: return "MipsISD::Lo";
161  case MipsISD::GotHi: return "MipsISD::GotHi";
162  case MipsISD::GPRel: return "MipsISD::GPRel";
163  case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
164  case MipsISD::Ret: return "MipsISD::Ret";
165  case MipsISD::ERet: return "MipsISD::ERet";
166  case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
167  case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
168  case MipsISD::FPCmp: return "MipsISD::FPCmp";
169  case MipsISD::FSELECT: return "MipsISD::FSELECT";
170  case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
171  case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
172  case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
173  case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
174  case MipsISD::MFHI: return "MipsISD::MFHI";
175  case MipsISD::MFLO: return "MipsISD::MFLO";
176  case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
177  case MipsISD::Mult: return "MipsISD::Mult";
178  case MipsISD::Multu: return "MipsISD::Multu";
179  case MipsISD::MAdd: return "MipsISD::MAdd";
180  case MipsISD::MAddu: return "MipsISD::MAddu";
181  case MipsISD::MSub: return "MipsISD::MSub";
182  case MipsISD::MSubu: return "MipsISD::MSubu";
183  case MipsISD::DivRem: return "MipsISD::DivRem";
184  case MipsISD::DivRemU: return "MipsISD::DivRemU";
185  case MipsISD::DivRem16: return "MipsISD::DivRem16";
186  case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
187  case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
188  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
189  case MipsISD::Wrapper: return "MipsISD::Wrapper";
190  case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
191  case MipsISD::Sync: return "MipsISD::Sync";
192  case MipsISD::Ext: return "MipsISD::Ext";
193  case MipsISD::Ins: return "MipsISD::Ins";
194  case MipsISD::CIns: return "MipsISD::CIns";
195  case MipsISD::LWL: return "MipsISD::LWL";
196  case MipsISD::LWR: return "MipsISD::LWR";
197  case MipsISD::SWL: return "MipsISD::SWL";
198  case MipsISD::SWR: return "MipsISD::SWR";
199  case MipsISD::LDL: return "MipsISD::LDL";
200  case MipsISD::LDR: return "MipsISD::LDR";
201  case MipsISD::SDL: return "MipsISD::SDL";
202  case MipsISD::SDR: return "MipsISD::SDR";
203  case MipsISD::EXTP: return "MipsISD::EXTP";
204  case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
205  case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
206  case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
207  case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
208  case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
209  case MipsISD::SHILO: return "MipsISD::SHILO";
210  case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
211  case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
212  case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
213  case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
214  case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
215  case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
216  case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
217  case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
218  case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
219  case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
220  case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
221  case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
222  case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
223  case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
224  case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
225  case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
226  case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
227  case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
228  case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
229  case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
230  case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
231  case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
232  case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
233  case MipsISD::MULT: return "MipsISD::MULT";
234  case MipsISD::MULTU: return "MipsISD::MULTU";
235  case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
236  case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
237  case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
238  case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
239  case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
240  case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
241  case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
242  case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
243  case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
244  case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
245  case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
246  case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
247  case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
248  case MipsISD::VCEQ: return "MipsISD::VCEQ";
249  case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
250  case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
251  case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
252  case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
253  case MipsISD::VSMAX: return "MipsISD::VSMAX";
254  case MipsISD::VSMIN: return "MipsISD::VSMIN";
255  case MipsISD::VUMAX: return "MipsISD::VUMAX";
256  case MipsISD::VUMIN: return "MipsISD::VUMIN";
257  case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
258  case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
259  case MipsISD::VNOR: return "MipsISD::VNOR";
260  case MipsISD::VSHF: return "MipsISD::VSHF";
261  case MipsISD::SHF: return "MipsISD::SHF";
262  case MipsISD::ILVEV: return "MipsISD::ILVEV";
263  case MipsISD::ILVOD: return "MipsISD::ILVOD";
264  case MipsISD::ILVL: return "MipsISD::ILVL";
265  case MipsISD::ILVR: return "MipsISD::ILVR";
266  case MipsISD::PCKEV: return "MipsISD::PCKEV";
267  case MipsISD::PCKOD: return "MipsISD::PCKOD";
268  case MipsISD::INSVE: return "MipsISD::INSVE";
269  }
270  return nullptr;
271 }
272 
274  const MipsSubtarget &STI)
275  : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
276  // Mips does not have i1 type, so use i32 for
277  // setcc operations results (slt, sgt, ...).
280  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
281  // does. Integer booleans still use 0 and 1.
282  if (Subtarget.hasMips32r6())
285 
286  // Load extented operations for i1 types must be promoted
287  for (MVT VT : MVT::integer_valuetypes()) {
291  }
292 
293  // MIPS doesn't have extending float->double load/store. Set LoadExtAction
294  // for f32, f16
295  for (MVT VT : MVT::fp_valuetypes()) {
298  }
299 
300  // Set LoadExtAction for f16 vectors to Expand
301  for (MVT VT : MVT::fp_vector_valuetypes()) {
302  MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
303  if (F16VT.isValid())
304  setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
305  }
306 
309 
311 
312  // Used by legalize types to correctly generate the setcc result.
313  // Without this, every float setcc comes with a AND/OR with the result,
314  // we don't want this, since the fpcmp result goes to a flag register,
315  // which is used implicitly by brcond and select operations.
317 
318  // Mips Custom Operations
334 
335  if (Subtarget.isGP64bit()) {
348  }
349 
350  if (!Subtarget.isGP64bit()) {
354  }
355 
357  if (Subtarget.isGP64bit())
359 
368 
369  if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) {
372  }
373 
380 
381  // Operations not directly supported by Mips.
395  if (Subtarget.hasCnMips()) {
398  } else {
401  }
408 
409  if (!Subtarget.hasMips32r2())
411 
412  if (!Subtarget.hasMips64r2())
414 
431 
432  // Lower f16 conversion operations into library calls
437 
439 
444 
445  // Use the default for now
448 
449  if (!Subtarget.isGP64bit()) {
452  }
453 
454 
455  if (!Subtarget.hasMips32r2()) {
458  }
459 
460  // MIPS16 lacks MIPS32's clz and clo instructions.
463  if (!Subtarget.hasMips64())
465 
466  if (!Subtarget.hasMips32r2())
468  if (!Subtarget.hasMips64r2())
470 
471  if (Subtarget.isGP64bit()) {
476  }
477 
479 
489 
490  if (ABI.IsO32()) {
491  // These libcalls are not available in 32-bit.
492  setLibcallName(RTLIB::SHL_I128, nullptr);
493  setLibcallName(RTLIB::SRL_I128, nullptr);
494  setLibcallName(RTLIB::SRA_I128, nullptr);
495  }
496 
498 
499  // The arguments on the stack are defined in terms of 4-byte slots on O32
500  // and 8-byte slots on N32/N64.
501  setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
502 
503  setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
504 
505  MaxStoresPerMemcpy = 16;
506 
507  isMicroMips = Subtarget.inMicroMipsMode();
508 }
509 
511  const MipsSubtarget &STI) {
512  if (STI.inMips16Mode())
513  return llvm::createMips16TargetLowering(TM, STI);
514 
515  return llvm::createMipsSETargetLowering(TM, STI);
516 }
517 
518 // Create a fast isel object.
519 FastISel *
521  const TargetLibraryInfo *libInfo) const {
522  const MipsTargetMachine &TM =
523  static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
524 
525  // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
526  bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
529 
530  // Disable if either of the following is true:
531  // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
532  if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
533  UseFastISel = false;
534 
535  return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
536 }
537 
539  EVT VT) const {
540  if (!VT.isVector())
541  return MVT::i32;
543 }
544 
547  const MipsSubtarget &Subtarget) {
548  if (DCI.isBeforeLegalizeOps())
549  return SDValue();
550 
551  EVT Ty = N->getValueType(0);
552  unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
553  unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
554  unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
556  SDLoc DL(N);
557 
558  SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
559  N->getOperand(0), N->getOperand(1));
560  SDValue InChain = DAG.getEntryNode();
561  SDValue InGlue = DivRem;
562 
563  // insert MFLO
564  if (N->hasAnyUseOfValue(0)) {
565  SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
566  InGlue);
567  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
568  InChain = CopyFromLo.getValue(1);
569  InGlue = CopyFromLo.getValue(2);
570  }
571 
572  // insert MFHI
573  if (N->hasAnyUseOfValue(1)) {
574  SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
575  HI, Ty, InGlue);
576  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
577  }
578 
579  return SDValue();
580 }
581 
583  switch (CC) {
584  default: llvm_unreachable("Unknown fp condition code!");
585  case ISD::SETEQ:
586  case ISD::SETOEQ: return Mips::FCOND_OEQ;
587  case ISD::SETUNE: return Mips::FCOND_UNE;
588  case ISD::SETLT:
589  case ISD::SETOLT: return Mips::FCOND_OLT;
590  case ISD::SETGT:
591  case ISD::SETOGT: return Mips::FCOND_OGT;
592  case ISD::SETLE:
593  case ISD::SETOLE: return Mips::FCOND_OLE;
594  case ISD::SETGE:
595  case ISD::SETOGE: return Mips::FCOND_OGE;
596  case ISD::SETULT: return Mips::FCOND_ULT;
597  case ISD::SETULE: return Mips::FCOND_ULE;
598  case ISD::SETUGT: return Mips::FCOND_UGT;
599  case ISD::SETUGE: return Mips::FCOND_UGE;
600  case ISD::SETUO: return Mips::FCOND_UN;
601  case ISD::SETO: return Mips::FCOND_OR;
602  case ISD::SETNE:
603  case ISD::SETONE: return Mips::FCOND_ONE;
604  case ISD::SETUEQ: return Mips::FCOND_UEQ;
605  }
606 }
607 
608 
609 /// This function returns true if the floating point conditional branches and
610 /// conditional moves which use condition code CC should be inverted.
612  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
613  return false;
614 
615  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
616  "Illegal Condition Code");
617 
618  return true;
619 }
620 
621 // Creates and returns an FPCmp node from a setcc node.
622 // Returns Op if setcc is not a floating point comparison.
623 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
624  // must be a SETCC node
625  if (Op.getOpcode() != ISD::SETCC)
626  return Op;
627 
628  SDValue LHS = Op.getOperand(0);
629 
630  if (!LHS.getValueType().isFloatingPoint())
631  return Op;
632 
633  SDValue RHS = Op.getOperand(1);
634  SDLoc DL(Op);
635 
636  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
637  // node if necessary.
638  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
639 
640  return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
641  DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
642 }
643 
644 // Creates and returns a CMovFPT/F node.
646  SDValue False, const SDLoc &DL) {
647  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
648  bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
649  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
650 
651  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
652  True.getValueType(), True, FCC0, False, Cond);
653 }
654 
657  const MipsSubtarget &Subtarget) {
658  if (DCI.isBeforeLegalizeOps())
659  return SDValue();
660 
661  SDValue SetCC = N->getOperand(0);
662 
663  if ((SetCC.getOpcode() != ISD::SETCC) ||
664  !SetCC.getOperand(0).getValueType().isInteger())
665  return SDValue();
666 
667  SDValue False = N->getOperand(2);
668  EVT FalseTy = False.getValueType();
669 
670  if (!FalseTy.isInteger())
671  return SDValue();
672 
673  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
674 
675  // If the RHS (False) is 0, we swap the order of the operands
676  // of ISD::SELECT (obviously also inverting the condition) so that we can
677  // take advantage of conditional moves using the $0 register.
678  // Example:
679  // return (a != 0) ? x : 0;
680  // load $reg, x
681  // movz $reg, $0, a
682  if (!FalseC)
683  return SDValue();
684 
685  const SDLoc DL(N);
686 
687  if (!FalseC->getZExtValue()) {
688  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
689  SDValue True = N->getOperand(1);
690 
691  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
692  SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
693 
694  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
695  }
696 
697  // If both operands are integer constants there's a possibility that we
698  // can do some interesting optimizations.
699  SDValue True = N->getOperand(1);
700  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
701 
702  if (!TrueC || !True.getValueType().isInteger())
703  return SDValue();
704 
705  // We'll also ignore MVT::i64 operands as this optimizations proves
706  // to be ineffective because of the required sign extensions as the result
707  // of a SETCC operator is always MVT::i32 for non-vector types.
708  if (True.getValueType() == MVT::i64)
709  return SDValue();
710 
711  int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
712 
713  // 1) (a < x) ? y : y-1
714  // slti $reg1, a, x
715  // addiu $reg2, $reg1, y-1
716  if (Diff == 1)
717  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
718 
719  // 2) (a < x) ? y-1 : y
720  // slti $reg1, a, x
721  // xor $reg1, $reg1, 1
722  // addiu $reg2, $reg1, y-1
723  if (Diff == -1) {
724  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
725  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
726  SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
727  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
728  }
729 
730  // Couldn't optimize.
731  return SDValue();
732 }
733 
736  const MipsSubtarget &Subtarget) {
737  if (DCI.isBeforeLegalizeOps())
738  return SDValue();
739 
740  SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
741 
742  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
743  if (!FalseC || FalseC->getZExtValue())
744  return SDValue();
745 
746  // Since RHS (False) is 0, we swap the order of the True/False operands
747  // (obviously also inverting the condition) so that we can
748  // take advantage of conditional moves using the $0 register.
749  // Example:
750  // return (a != 0) ? x : 0;
751  // load $reg, x
752  // movz $reg, $0, a
753  unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
755 
756  SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
757  return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
758  ValueIfFalse, FCC, ValueIfTrue, Glue);
759 }
760 
763  const MipsSubtarget &Subtarget) {
764  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
765  return SDValue();
766 
767  SDValue FirstOperand = N->getOperand(0);
768  unsigned FirstOperandOpc = FirstOperand.getOpcode();
769  SDValue Mask = N->getOperand(1);
770  EVT ValTy = N->getValueType(0);
771  SDLoc DL(N);
772 
773  uint64_t Pos = 0, SMPos, SMSize;
774  ConstantSDNode *CN;
775  SDValue NewOperand;
776  unsigned Opc;
777 
778  // Op's second operand must be a shifted mask.
779  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
780  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
781  return SDValue();
782 
783  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
784  // Pattern match EXT.
785  // $dst = and ((sra or srl) $src , pos), (2**size - 1)
786  // => ext $dst, $src, pos, size
787 
788  // The second operand of the shift must be an immediate.
789  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
790  return SDValue();
791 
792  Pos = CN->getZExtValue();
793 
794  // Return if the shifted mask does not start at bit 0 or the sum of its size
795  // and Pos exceeds the word's size.
796  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
797  return SDValue();
798 
799  Opc = MipsISD::Ext;
800  NewOperand = FirstOperand.getOperand(0);
801  } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
802  // Pattern match CINS.
803  // $dst = and (shl $src , pos), mask
804  // => cins $dst, $src, pos, size
805  // mask is a shifted mask with consecutive 1's, pos = shift amount,
806  // size = population count.
807 
808  // The second operand of the shift must be an immediate.
809  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
810  return SDValue();
811 
812  Pos = CN->getZExtValue();
813 
814  if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
815  Pos + SMSize > ValTy.getSizeInBits())
816  return SDValue();
817 
818  NewOperand = FirstOperand.getOperand(0);
819  // SMSize is 'location' (position) in this case, not size.
820  SMSize--;
821  Opc = MipsISD::CIns;
822  } else {
823  // Pattern match EXT.
824  // $dst = and $src, (2**size - 1) , if size > 16
825  // => ext $dst, $src, pos, size , pos = 0
826 
827  // If the mask is <= 0xffff, andi can be used instead.
828  if (CN->getZExtValue() <= 0xffff)
829  return SDValue();
830 
831  // Return if the mask doesn't start at position 0.
832  if (SMPos)
833  return SDValue();
834 
835  Opc = MipsISD::Ext;
836  NewOperand = FirstOperand;
837  }
838  return DAG.getNode(Opc, DL, ValTy, NewOperand,
839  DAG.getConstant(Pos, DL, MVT::i32),
840  DAG.getConstant(SMSize, DL, MVT::i32));
841 }
842 
845  const MipsSubtarget &Subtarget) {
846  // Pattern match INS.
847  // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
848  // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
849  // => ins $dst, $src, size, pos, $src1
850  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
851  return SDValue();
852 
853  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
854  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
855  ConstantSDNode *CN, *CN1;
856 
857  // See if Op's first operand matches (and $src1 , mask0).
858  if (And0.getOpcode() != ISD::AND)
859  return SDValue();
860 
861  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
862  !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
863  return SDValue();
864 
865  // See if Op's second operand matches (and (shl $src, pos), mask1).
866  if (And1.getOpcode() == ISD::AND &&
867  And1.getOperand(0).getOpcode() == ISD::SHL) {
868 
869  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
870  !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
871  return SDValue();
872 
873  // The shift masks must have the same position and size.
874  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
875  return SDValue();
876 
877  SDValue Shl = And1.getOperand(0);
878 
879  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
880  return SDValue();
881 
882  unsigned Shamt = CN->getZExtValue();
883 
884  // Return if the shift amount and the first bit position of mask are not the
885  // same.
886  EVT ValTy = N->getValueType(0);
887  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
888  return SDValue();
889 
890  SDLoc DL(N);
891  return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
892  DAG.getConstant(SMPos0, DL, MVT::i32),
893  DAG.getConstant(SMSize0, DL, MVT::i32),
894  And0.getOperand(0));
895  } else {
896  // Pattern match DINS.
897  // $dst = or (and $src, mask0), mask1
898  // where mask0 = ((1 << SMSize0) -1) << SMPos0
899  // => dins $dst, $src, pos, size
900  if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
901  ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
902  (SMSize0 + SMPos0 <= 32))) {
903  // Check if AND instruction has constant as argument
904  bool isConstCase = And1.getOpcode() != ISD::AND;
905  if (And1.getOpcode() == ISD::AND) {
906  if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
907  return SDValue();
908  } else {
909  if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
910  return SDValue();
911  }
912  // Don't generate INS if constant OR operand doesn't fit into bits
913  // cleared by constant AND operand.
914  if (CN->getSExtValue() & CN1->getSExtValue())
915  return SDValue();
916 
917  SDLoc DL(N);
918  EVT ValTy = N->getOperand(0)->getValueType(0);
919  SDValue Const1;
920  SDValue SrlX;
921  if (!isConstCase) {
922  Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
923  SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
924  }
925  return DAG.getNode(
926  MipsISD::Ins, DL, N->getValueType(0),
927  isConstCase
928  ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
929  : SrlX,
930  DAG.getConstant(SMPos0, DL, MVT::i32),
931  DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
932  : SMSize0,
933  DL, MVT::i32),
934  And0->getOperand(0));
935 
936  }
937  return SDValue();
938  }
939 }
940 
942  const MipsSubtarget &Subtarget) {
943  // ROOTNode must have a multiplication as an operand for the match to be
944  // successful.
945  if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
946  ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
947  return SDValue();
948 
949  // We don't handle vector types here.
950  if (ROOTNode->getValueType(0).isVector())
951  return SDValue();
952 
953  // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
954  // arithmetic. E.g.
955  // (add (mul a b) c) =>
956  // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
957  // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
958  // or
959  // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
960  //
961  // The overhead of setting up the Hi/Lo registers and reassembling the
962  // result makes this a dubious optimzation for MIPS64. The core of the
963  // problem is that Hi/Lo contain the upper and lower 32 bits of the
964  // operand and result.
965  //
966  // It requires a chain of 4 add/mul for MIPS64R2 to get better code
967  // density than doing it naively, 5 for MIPS64. Additionally, using
968  // madd/msub on MIPS64 requires the operands actually be 32 bit sign
969  // extended operands, not true 64 bit values.
970  //
971  // FIXME: For the moment, disable this completely for MIPS64.
972  if (Subtarget.hasMips64())
973  return SDValue();
974 
975  SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
976  ? ROOTNode->getOperand(0)
977  : ROOTNode->getOperand(1);
978 
979  SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
980  ? ROOTNode->getOperand(1)
981  : ROOTNode->getOperand(0);
982 
983  // Transform this to a MADD only if the user of this node is the add.
984  // If there are other users of the mul, this function returns here.
985  if (!Mult.hasOneUse())
986  return SDValue();
987 
988  // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
989  // must be in canonical form, i.e. sign extended. For MIPS32, the operands
990  // of the multiply must have 32 or more sign bits, otherwise we cannot
991  // perform this optimization. We have to check this here as we're performing
992  // this optimization pre-legalization.
993  SDValue MultLHS = Mult->getOperand(0);
994  SDValue MultRHS = Mult->getOperand(1);
995 
996  bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
997  MultRHS->getOpcode() == ISD::SIGN_EXTEND;
998  bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
999  MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1000 
1001  if (!IsSigned && !IsUnsigned)
1002  return SDValue();
1003 
1004  // Initialize accumulator.
1005  SDLoc DL(ROOTNode);
1006  SDValue TopHalf;
1007  SDValue BottomHalf;
1008  BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1009  CurDAG.getIntPtrConstant(0, DL));
1010 
1011  TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1012  CurDAG.getIntPtrConstant(1, DL));
1013  SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1014  BottomHalf,
1015  TopHalf);
1016 
1017  // Create MipsMAdd(u) / MipsMSub(u) node.
1018  bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1019  unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1020  : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1021  SDValue MAddOps[3] = {
1022  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1023  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1024  EVT VTs[2] = {MVT::i32, MVT::i32};
1025  SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1026 
1027  SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1028  SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1029  SDValue Combined =
1030  CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1031  return Combined;
1032 }
1033 
1036  const MipsSubtarget &Subtarget) {
1037  // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1038  if (DCI.isBeforeLegalizeOps()) {
1039  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1040  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1041  return performMADD_MSUBCombine(N, DAG, Subtarget);
1042 
1043  return SDValue();
1044  }
1045 
1046  return SDValue();
1047 }
1048 
1051  const MipsSubtarget &Subtarget) {
1052  // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1053  if (DCI.isBeforeLegalizeOps()) {
1054  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1055  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1056  return performMADD_MSUBCombine(N, DAG, Subtarget);
1057 
1058  return SDValue();
1059  }
1060 
1061  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1062  SDValue Add = N->getOperand(1);
1063 
1064  if (Add.getOpcode() != ISD::ADD)
1065  return SDValue();
1066 
1067  SDValue Lo = Add.getOperand(1);
1068 
1069  if ((Lo.getOpcode() != MipsISD::Lo) ||
1071  return SDValue();
1072 
1073  EVT ValTy = N->getValueType(0);
1074  SDLoc DL(N);
1075 
1076  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1077  Add.getOperand(0));
1078  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1079 }
1080 
1083  const MipsSubtarget &Subtarget) {
1084  SDValue N0 = N->getOperand(0);
1085  EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1086 
1087  if (N0.getOpcode() != ISD::TRUNCATE)
1088  return SDValue();
1089 
1090  if (N0.getOperand(0).getOpcode() != ISD::AssertZext)
1091  return SDValue();
1092 
1093  // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x))
1094  // if the type of the extension of the innermost AssertZext node is
1095  // smaller from that of the outermost node, eg:
1096  // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
1097  // -> (trunc:i32 (AssertZext X, i8))
1098  SDValue WiderAssertZext = N0.getOperand(0);
1099  EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT();
1100 
1101  if (NarrowerVT.bitsLT(WiderVT)) {
1102  SDValue NewAssertZext = DAG.getNode(
1103  ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(),
1104  WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT));
1105  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0),
1106  NewAssertZext);
1107  }
1108 
1109  return SDValue();
1110 }
1111 
1112 
1115  const MipsSubtarget &Subtarget) {
1116  // Pattern match CINS.
1117  // $dst = shl (and $src , imm), pos
1118  // => cins $dst, $src, pos, size
1119 
1120  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1121  return SDValue();
1122 
1123  SDValue FirstOperand = N->getOperand(0);
1124  unsigned FirstOperandOpc = FirstOperand.getOpcode();
1125  SDValue SecondOperand = N->getOperand(1);
1126  EVT ValTy = N->getValueType(0);
1127  SDLoc DL(N);
1128 
1129  uint64_t Pos = 0, SMPos, SMSize;
1130  ConstantSDNode *CN;
1131  SDValue NewOperand;
1132 
1133  // The second operand of the shift must be an immediate.
1134  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1135  return SDValue();
1136 
1137  Pos = CN->getZExtValue();
1138 
1139  if (Pos >= ValTy.getSizeInBits())
1140  return SDValue();
1141 
1142  if (FirstOperandOpc != ISD::AND)
1143  return SDValue();
1144 
1145  // AND's second operand must be a shifted mask.
1146  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1147  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1148  return SDValue();
1149 
1150  // Return if the shifted mask does not start at bit 0 or the sum of its size
1151  // and Pos exceeds the word's size.
1152  if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1153  return SDValue();
1154 
1155  NewOperand = FirstOperand.getOperand(0);
1156  // SMSize is 'location' (position) in this case, not size.
1157  SMSize--;
1158 
1159  return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1160  DAG.getConstant(Pos, DL, MVT::i32),
1161  DAG.getConstant(SMSize, DL, MVT::i32));
1162 }
1163 
1165  const {
1166  SelectionDAG &DAG = DCI.DAG;
1167  unsigned Opc = N->getOpcode();
1168 
1169  switch (Opc) {
1170  default: break;
1171  case ISD::SDIVREM:
1172  case ISD::UDIVREM:
1173  return performDivRemCombine(N, DAG, DCI, Subtarget);
1174  case ISD::SELECT:
1175  return performSELECTCombine(N, DAG, DCI, Subtarget);
1176  case MipsISD::CMovFP_F:
1177  case MipsISD::CMovFP_T:
1178  return performCMovFPCombine(N, DAG, DCI, Subtarget);
1179  case ISD::AND:
1180  return performANDCombine(N, DAG, DCI, Subtarget);
1181  case ISD::OR:
1182  return performORCombine(N, DAG, DCI, Subtarget);
1183  case ISD::ADD:
1184  return performADDCombine(N, DAG, DCI, Subtarget);
1185  case ISD::AssertZext:
1186  return performAssertZextCombine(N, DAG, DCI, Subtarget);
1187  case ISD::SHL:
1188  return performSHLCombine(N, DAG, DCI, Subtarget);
1189  case ISD::SUB:
1190  return performSUBCombine(N, DAG, DCI, Subtarget);
1191  }
1192 
1193  return SDValue();
1194 }
1195 
1197  return Subtarget.hasMips32();
1198 }
1199 
1201  return Subtarget.hasMips32();
1202 }
1203 
1204 void
1207  SelectionDAG &DAG) const {
1208  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1209 
1210  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1211  Results.push_back(Res.getValue(I));
1212 }
1213 
1214 void
1217  SelectionDAG &DAG) const {
1218  return LowerOperationWrapper(N, Results, DAG);
1219 }
1220 
1223 {
1224  switch (Op.getOpcode())
1225  {
1226  case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1227  case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1228  case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1229  case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1230  case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1231  case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1232  case ISD::SELECT: return lowerSELECT(Op, DAG);
1233  case ISD::SETCC: return lowerSETCC(Op, DAG);
1234  case ISD::VASTART: return lowerVASTART(Op, DAG);
1235  case ISD::VAARG: return lowerVAARG(Op, DAG);
1236  case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1237  case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1238  case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1239  case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1240  case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1241  case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1242  case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1243  case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1244  case ISD::LOAD: return lowerLOAD(Op, DAG);
1245  case ISD::STORE: return lowerSTORE(Op, DAG);
1246  case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1247  case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1248  }
1249  return SDValue();
1250 }
1251 
1252 //===----------------------------------------------------------------------===//
1253 // Lower helper functions
1254 //===----------------------------------------------------------------------===//
1255 
1256 // addLiveIn - This helper function adds the specified physical register to the
1257 // MachineFunction as a live in value. It also creates a corresponding
1258 // virtual register for it.
1259 static unsigned
1260 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1261 {
1262  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1263  MF.getRegInfo().addLiveIn(PReg, VReg);
1264  return VReg;
1265 }
1266 
1268  MachineBasicBlock &MBB,
1269  const TargetInstrInfo &TII,
1270  bool Is64Bit, bool IsMicroMips) {
1271  if (NoZeroDivCheck)
1272  return &MBB;
1273 
1274  // Insert instruction "teq $divisor_reg, $zero, 7".
1276  MachineInstrBuilder MIB;
1277  MachineOperand &Divisor = MI.getOperand(2);
1278  MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1279  TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1280  .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1281  .addReg(Mips::ZERO)
1282  .addImm(7);
1283 
1284  // Use the 32-bit sub-register if this is a 64-bit division.
1285  if (Is64Bit)
1286  MIB->getOperand(0).setSubReg(Mips::sub_32);
1287 
1288  // Clear Divisor's kill flag.
1289  Divisor.setIsKill(false);
1290 
1291  // We would normally delete the original instruction here but in this case
1292  // we only needed to inject an additional instruction rather than replace it.
1293 
1294  return &MBB;
1295 }
1296 
1299  MachineBasicBlock *BB) const {
1300  switch (MI.getOpcode()) {
1301  default:
1302  llvm_unreachable("Unexpected instr type to insert");
1303  case Mips::ATOMIC_LOAD_ADD_I8:
1304  return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1305  case Mips::ATOMIC_LOAD_ADD_I16:
1306  return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1307  case Mips::ATOMIC_LOAD_ADD_I32:
1308  return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
1309  case Mips::ATOMIC_LOAD_ADD_I64:
1310  return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
1311 
1312  case Mips::ATOMIC_LOAD_AND_I8:
1313  return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1314  case Mips::ATOMIC_LOAD_AND_I16:
1315  return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1316  case Mips::ATOMIC_LOAD_AND_I32:
1317  return emitAtomicBinary(MI, BB, 4, Mips::AND);
1318  case Mips::ATOMIC_LOAD_AND_I64:
1319  return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1320 
1321  case Mips::ATOMIC_LOAD_OR_I8:
1322  return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1323  case Mips::ATOMIC_LOAD_OR_I16:
1324  return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1325  case Mips::ATOMIC_LOAD_OR_I32:
1326  return emitAtomicBinary(MI, BB, 4, Mips::OR);
1327  case Mips::ATOMIC_LOAD_OR_I64:
1328  return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1329 
1330  case Mips::ATOMIC_LOAD_XOR_I8:
1331  return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1332  case Mips::ATOMIC_LOAD_XOR_I16:
1333  return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1334  case Mips::ATOMIC_LOAD_XOR_I32:
1335  return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1336  case Mips::ATOMIC_LOAD_XOR_I64:
1337  return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1338 
1339  case Mips::ATOMIC_LOAD_NAND_I8:
1340  return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1341  case Mips::ATOMIC_LOAD_NAND_I16:
1342  return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1343  case Mips::ATOMIC_LOAD_NAND_I32:
1344  return emitAtomicBinary(MI, BB, 4, 0, true);
1345  case Mips::ATOMIC_LOAD_NAND_I64:
1346  return emitAtomicBinary(MI, BB, 8, 0, true);
1347 
1348  case Mips::ATOMIC_LOAD_SUB_I8:
1349  return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1350  case Mips::ATOMIC_LOAD_SUB_I16:
1351  return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1352  case Mips::ATOMIC_LOAD_SUB_I32:
1353  return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1354  case Mips::ATOMIC_LOAD_SUB_I64:
1355  return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1356 
1357  case Mips::ATOMIC_SWAP_I8:
1358  return emitAtomicBinaryPartword(MI, BB, 1, 0);
1359  case Mips::ATOMIC_SWAP_I16:
1360  return emitAtomicBinaryPartword(MI, BB, 2, 0);
1361  case Mips::ATOMIC_SWAP_I32:
1362  return emitAtomicBinary(MI, BB, 4, 0);
1363  case Mips::ATOMIC_SWAP_I64:
1364  return emitAtomicBinary(MI, BB, 8, 0);
1365 
1366  case Mips::ATOMIC_CMP_SWAP_I8:
1367  return emitAtomicCmpSwapPartword(MI, BB, 1);
1368  case Mips::ATOMIC_CMP_SWAP_I16:
1369  return emitAtomicCmpSwapPartword(MI, BB, 2);
1370  case Mips::ATOMIC_CMP_SWAP_I32:
1371  return emitAtomicCmpSwap(MI, BB, 4);
1372  case Mips::ATOMIC_CMP_SWAP_I64:
1373  return emitAtomicCmpSwap(MI, BB, 8);
1374  case Mips::PseudoSDIV:
1375  case Mips::PseudoUDIV:
1376  case Mips::DIV:
1377  case Mips::DIVU:
1378  case Mips::MOD:
1379  case Mips::MODU:
1380  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1381  false);
1382  case Mips::SDIV_MM_Pseudo:
1383  case Mips::UDIV_MM_Pseudo:
1384  case Mips::SDIV_MM:
1385  case Mips::UDIV_MM:
1386  case Mips::DIV_MMR6:
1387  case Mips::DIVU_MMR6:
1388  case Mips::MOD_MMR6:
1389  case Mips::MODU_MMR6:
1390  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1391  case Mips::PseudoDSDIV:
1392  case Mips::PseudoDUDIV:
1393  case Mips::DDIV:
1394  case Mips::DDIVU:
1395  case Mips::DMOD:
1396  case Mips::DMODU:
1397  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1398  case Mips::DDIV_MM64R6:
1399  case Mips::DDIVU_MM64R6:
1400  case Mips::DMOD_MM64R6:
1401  case Mips::DMODU_MM64R6:
1402  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
1403 
1404  case Mips::PseudoSELECT_I:
1405  case Mips::PseudoSELECT_I64:
1406  case Mips::PseudoSELECT_S:
1407  case Mips::PseudoSELECT_D32:
1408  case Mips::PseudoSELECT_D64:
1409  return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1410  case Mips::PseudoSELECTFP_F_I:
1411  case Mips::PseudoSELECTFP_F_I64:
1412  case Mips::PseudoSELECTFP_F_S:
1413  case Mips::PseudoSELECTFP_F_D32:
1414  case Mips::PseudoSELECTFP_F_D64:
1415  return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1416  case Mips::PseudoSELECTFP_T_I:
1417  case Mips::PseudoSELECTFP_T_I64:
1418  case Mips::PseudoSELECTFP_T_S:
1419  case Mips::PseudoSELECTFP_T_D32:
1420  case Mips::PseudoSELECTFP_T_D64:
1421  return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1422  }
1423 }
1424 
1425 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1426 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1427 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1428  MachineBasicBlock *BB,
1429  unsigned Size,
1430  unsigned BinOpcode,
1431  bool Nand) const {
1432  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1433 
1434  MachineFunction *MF = BB->getParent();
1435  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1436  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1438  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1439  DebugLoc DL = MI.getDebugLoc();
1440  unsigned LL, SC, AND, NOR, ZERO, BEQ;
1441 
1442  if (Size == 4) {
1443  if (isMicroMips) {
1444  LL = Mips::LL_MM;
1445  SC = Mips::SC_MM;
1446  } else {
1447  LL = Subtarget.hasMips32r6()
1448  ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1449  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1450  SC = Subtarget.hasMips32r6()
1451  ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1452  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1453  }
1454 
1455  AND = Mips::AND;
1456  NOR = Mips::NOR;
1457  ZERO = Mips::ZERO;
1458  BEQ = Mips::BEQ;
1459  } else {
1460  LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1461  SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1462  AND = Mips::AND64;
1463  NOR = Mips::NOR64;
1464  ZERO = Mips::ZERO_64;
1465  BEQ = Mips::BEQ64;
1466  }
1467 
1468  unsigned OldVal = MI.getOperand(0).getReg();
1469  unsigned Ptr = MI.getOperand(1).getReg();
1470  unsigned Incr = MI.getOperand(2).getReg();
1471 
1472  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1473  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1474  unsigned Success = RegInfo.createVirtualRegister(RC);
1475 
1476  // insert new blocks after the current block
1477  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1478  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1479  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1481  MF->insert(It, loopMBB);
1482  MF->insert(It, exitMBB);
1483 
1484  // Transfer the remainder of BB and its successor edges to exitMBB.
1485  exitMBB->splice(exitMBB->begin(), BB,
1486  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1487  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1488 
1489  // thisMBB:
1490  // ...
1491  // fallthrough --> loopMBB
1492  BB->addSuccessor(loopMBB);
1493  loopMBB->addSuccessor(loopMBB);
1494  loopMBB->addSuccessor(exitMBB);
1495 
1496  // loopMBB:
1497  // ll oldval, 0(ptr)
1498  // <binop> storeval, oldval, incr
1499  // sc success, storeval, 0(ptr)
1500  // beq success, $0, loopMBB
1501  BB = loopMBB;
1502  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1503  if (Nand) {
1504  // and andres, oldval, incr
1505  // nor storeval, $0, andres
1506  BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1507  BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1508  } else if (BinOpcode) {
1509  // <binop> storeval, oldval, incr
1510  BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1511  } else {
1512  StoreVal = Incr;
1513  }
1514  BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1515  BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1516 
1517  MI.eraseFromParent(); // The instruction is gone now.
1518 
1519  return exitMBB;
1520 }
1521 
1522 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1523  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1524  unsigned SrcReg) const {
1526  const DebugLoc &DL = MI.getDebugLoc();
1527 
1528  if (Subtarget.hasMips32r2() && Size == 1) {
1529  BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1530  return BB;
1531  }
1532 
1533  if (Subtarget.hasMips32r2() && Size == 2) {
1534  BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1535  return BB;
1536  }
1537 
1538  MachineFunction *MF = BB->getParent();
1539  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1541  unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1542 
1543  assert(Size < 32);
1544  int64_t ShiftImm = 32 - (Size * 8);
1545 
1546  BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1547  BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1548 
1549  return BB;
1550 }
1551 
1552 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1553  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1554  bool Nand) const {
1555  assert((Size == 1 || Size == 2) &&
1556  "Unsupported size for EmitAtomicBinaryPartial.");
1557 
1558  MachineFunction *MF = BB->getParent();
1559  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1561  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1562  const TargetRegisterClass *RCp =
1563  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1565  DebugLoc DL = MI.getDebugLoc();
1566 
1567  unsigned Dest = MI.getOperand(0).getReg();
1568  unsigned Ptr = MI.getOperand(1).getReg();
1569  unsigned Incr = MI.getOperand(2).getReg();
1570 
1571  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1572  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1573  unsigned Mask = RegInfo.createVirtualRegister(RC);
1574  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1575  unsigned NewVal = RegInfo.createVirtualRegister(RC);
1576  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1577  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1578  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1579  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1580  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1581  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1582  unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1583  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1584  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1585  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1586  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1587  unsigned Success = RegInfo.createVirtualRegister(RC);
1588 
1589  unsigned LL, SC;
1590  if (isMicroMips) {
1591  LL = Mips::LL_MM;
1592  SC = Mips::SC_MM;
1593  } else {
1594  LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1595  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1596  SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1597  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1598  }
1599 
1600  // insert new blocks after the current block
1601  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1602  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1603  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1604  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1606  MF->insert(It, loopMBB);
1607  MF->insert(It, sinkMBB);
1608  MF->insert(It, exitMBB);
1609 
1610  // Transfer the remainder of BB and its successor edges to exitMBB.
1611  exitMBB->splice(exitMBB->begin(), BB,
1612  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1613  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1614 
1615  BB->addSuccessor(loopMBB);
1616  loopMBB->addSuccessor(loopMBB);
1617  loopMBB->addSuccessor(sinkMBB);
1618  sinkMBB->addSuccessor(exitMBB);
1619 
1620  // thisMBB:
1621  // addiu masklsb2,$0,-4 # 0xfffffffc
1622  // and alignedaddr,ptr,masklsb2
1623  // andi ptrlsb2,ptr,3
1624  // sll shiftamt,ptrlsb2,3
1625  // ori maskupper,$0,255 # 0xff
1626  // sll mask,maskupper,shiftamt
1627  // nor mask2,$0,mask
1628  // sll incr2,incr,shiftamt
1629 
1630  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1631  BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1632  .addReg(ABI.GetNullPtr()).addImm(-4);
1633  BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1634  .addReg(Ptr).addReg(MaskLSB2);
1635  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1636  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1637  if (Subtarget.isLittle()) {
1638  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1639  } else {
1640  unsigned Off = RegInfo.createVirtualRegister(RC);
1641  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1642  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1643  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1644  }
1645  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1646  .addReg(Mips::ZERO).addImm(MaskImm);
1647  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1648  .addReg(MaskUpper).addReg(ShiftAmt);
1649  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1650  BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1651 
1652  // atomic.load.binop
1653  // loopMBB:
1654  // ll oldval,0(alignedaddr)
1655  // binop binopres,oldval,incr2
1656  // and newval,binopres,mask
1657  // and maskedoldval0,oldval,mask2
1658  // or storeval,maskedoldval0,newval
1659  // sc success,storeval,0(alignedaddr)
1660  // beq success,$0,loopMBB
1661 
1662  // atomic.swap
1663  // loopMBB:
1664  // ll oldval,0(alignedaddr)
1665  // and newval,incr2,mask
1666  // and maskedoldval0,oldval,mask2
1667  // or storeval,maskedoldval0,newval
1668  // sc success,storeval,0(alignedaddr)
1669  // beq success,$0,loopMBB
1670 
1671  BB = loopMBB;
1672  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1673  if (Nand) {
1674  // and andres, oldval, incr2
1675  // nor binopres, $0, andres
1676  // and newval, binopres, mask
1677  BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1678  BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1679  .addReg(Mips::ZERO).addReg(AndRes);
1680  BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1681  } else if (BinOpcode) {
1682  // <binop> binopres, oldval, incr2
1683  // and newval, binopres, mask
1684  BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1685  BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1686  } else { // atomic.swap
1687  // and newval, incr2, mask
1688  BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1689  }
1690 
1691  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1692  .addReg(OldVal).addReg(Mask2);
1693  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1694  .addReg(MaskedOldVal0).addReg(NewVal);
1695  BuildMI(BB, DL, TII->get(SC), Success)
1696  .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1697  BuildMI(BB, DL, TII->get(Mips::BEQ))
1698  .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1699 
1700  // sinkMBB:
1701  // and maskedoldval1,oldval,mask
1702  // srl srlres,maskedoldval1,shiftamt
1703  // sign_extend dest,srlres
1704  BB = sinkMBB;
1705 
1706  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1707  .addReg(OldVal).addReg(Mask);
1708  BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1709  .addReg(MaskedOldVal1).addReg(ShiftAmt);
1710  BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1711 
1712  MI.eraseFromParent(); // The instruction is gone now.
1713 
1714  return exitMBB;
1715 }
1716 
1717 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1718  MachineBasicBlock *BB,
1719  unsigned Size) const {
1720  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1721 
1722  MachineFunction *MF = BB->getParent();
1723  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1724  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1726  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1727  DebugLoc DL = MI.getDebugLoc();
1728  unsigned LL, SC, ZERO, BNE, BEQ;
1729 
1730  if (Size == 4) {
1731  if (isMicroMips) {
1732  LL = Mips::LL_MM;
1733  SC = Mips::SC_MM;
1734  } else {
1735  LL = Subtarget.hasMips32r6()
1736  ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1737  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1738  SC = Subtarget.hasMips32r6()
1739  ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1740  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1741  }
1742 
1743  ZERO = Mips::ZERO;
1744  BNE = Mips::BNE;
1745  BEQ = Mips::BEQ;
1746  } else {
1747  LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1748  SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1749  ZERO = Mips::ZERO_64;
1750  BNE = Mips::BNE64;
1751  BEQ = Mips::BEQ64;
1752  }
1753 
1754  unsigned Dest = MI.getOperand(0).getReg();
1755  unsigned Ptr = MI.getOperand(1).getReg();
1756  unsigned OldVal = MI.getOperand(2).getReg();
1757  unsigned NewVal = MI.getOperand(3).getReg();
1758 
1759  unsigned Success = RegInfo.createVirtualRegister(RC);
1760 
1761  // insert new blocks after the current block
1762  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1763  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1764  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1765  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1767  MF->insert(It, loop1MBB);
1768  MF->insert(It, loop2MBB);
1769  MF->insert(It, exitMBB);
1770 
1771  // Transfer the remainder of BB and its successor edges to exitMBB.
1772  exitMBB->splice(exitMBB->begin(), BB,
1773  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1774  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1775 
1776  // thisMBB:
1777  // ...
1778  // fallthrough --> loop1MBB
1779  BB->addSuccessor(loop1MBB);
1780  loop1MBB->addSuccessor(exitMBB);
1781  loop1MBB->addSuccessor(loop2MBB);
1782  loop2MBB->addSuccessor(loop1MBB);
1783  loop2MBB->addSuccessor(exitMBB);
1784 
1785  // loop1MBB:
1786  // ll dest, 0(ptr)
1787  // bne dest, oldval, exitMBB
1788  BB = loop1MBB;
1789  BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1790  BuildMI(BB, DL, TII->get(BNE))
1791  .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1792 
1793  // loop2MBB:
1794  // sc success, newval, 0(ptr)
1795  // beq success, $0, loop1MBB
1796  BB = loop2MBB;
1797  BuildMI(BB, DL, TII->get(SC), Success)
1798  .addReg(NewVal).addReg(Ptr).addImm(0);
1799  BuildMI(BB, DL, TII->get(BEQ))
1800  .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1801 
1802  MI.eraseFromParent(); // The instruction is gone now.
1803 
1804  return exitMBB;
1805 }
1806 
1807 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1808  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1809  assert((Size == 1 || Size == 2) &&
1810  "Unsupported size for EmitAtomicCmpSwapPartial.");
1811 
1812  MachineFunction *MF = BB->getParent();
1813  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1815  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1816  const TargetRegisterClass *RCp =
1817  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1819  DebugLoc DL = MI.getDebugLoc();
1820 
1821  unsigned Dest = MI.getOperand(0).getReg();
1822  unsigned Ptr = MI.getOperand(1).getReg();
1823  unsigned CmpVal = MI.getOperand(2).getReg();
1824  unsigned NewVal = MI.getOperand(3).getReg();
1825 
1826  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1827  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1828  unsigned Mask = RegInfo.createVirtualRegister(RC);
1829  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1830  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1831  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1832  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1833  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1834  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1835  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1836  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1837  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1838  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1839  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1840  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1841  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1842  unsigned Success = RegInfo.createVirtualRegister(RC);
1843  unsigned LL, SC;
1844 
1845  if (isMicroMips) {
1846  LL = Mips::LL_MM;
1847  SC = Mips::SC_MM;
1848  } else {
1849  LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1850  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1851  SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1852  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1853  }
1854 
1855  // insert new blocks after the current block
1856  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1857  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1858  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1859  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1860  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1862  MF->insert(It, loop1MBB);
1863  MF->insert(It, loop2MBB);
1864  MF->insert(It, sinkMBB);
1865  MF->insert(It, exitMBB);
1866 
1867  // Transfer the remainder of BB and its successor edges to exitMBB.
1868  exitMBB->splice(exitMBB->begin(), BB,
1869  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1870  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1871 
1872  BB->addSuccessor(loop1MBB);
1873  loop1MBB->addSuccessor(sinkMBB);
1874  loop1MBB->addSuccessor(loop2MBB);
1875  loop2MBB->addSuccessor(loop1MBB);
1876  loop2MBB->addSuccessor(sinkMBB);
1877  sinkMBB->addSuccessor(exitMBB);
1878 
1879  // FIXME: computation of newval2 can be moved to loop2MBB.
1880  // thisMBB:
1881  // addiu masklsb2,$0,-4 # 0xfffffffc
1882  // and alignedaddr,ptr,masklsb2
1883  // andi ptrlsb2,ptr,3
1884  // xori ptrlsb2,ptrlsb2,3 # Only for BE
1885  // sll shiftamt,ptrlsb2,3
1886  // ori maskupper,$0,255 # 0xff
1887  // sll mask,maskupper,shiftamt
1888  // nor mask2,$0,mask
1889  // andi maskedcmpval,cmpval,255
1890  // sll shiftedcmpval,maskedcmpval,shiftamt
1891  // andi maskednewval,newval,255
1892  // sll shiftednewval,maskednewval,shiftamt
1893  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1894  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1895  .addReg(ABI.GetNullPtr()).addImm(-4);
1896  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1897  .addReg(Ptr).addReg(MaskLSB2);
1898  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1899  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1900  if (Subtarget.isLittle()) {
1901  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1902  } else {
1903  unsigned Off = RegInfo.createVirtualRegister(RC);
1904  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1905  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1906  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1907  }
1908  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1909  .addReg(Mips::ZERO).addImm(MaskImm);
1910  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1911  .addReg(MaskUpper).addReg(ShiftAmt);
1912  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1913  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1914  .addReg(CmpVal).addImm(MaskImm);
1915  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1916  .addReg(MaskedCmpVal).addReg(ShiftAmt);
1917  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1918  .addReg(NewVal).addImm(MaskImm);
1919  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1920  .addReg(MaskedNewVal).addReg(ShiftAmt);
1921 
1922  // loop1MBB:
1923  // ll oldval,0(alginedaddr)
1924  // and maskedoldval0,oldval,mask
1925  // bne maskedoldval0,shiftedcmpval,sinkMBB
1926  BB = loop1MBB;
1927  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1928  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1929  .addReg(OldVal).addReg(Mask);
1930  BuildMI(BB, DL, TII->get(Mips::BNE))
1931  .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1932 
1933  // loop2MBB:
1934  // and maskedoldval1,oldval,mask2
1935  // or storeval,maskedoldval1,shiftednewval
1936  // sc success,storeval,0(alignedaddr)
1937  // beq success,$0,loop1MBB
1938  BB = loop2MBB;
1939  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1940  .addReg(OldVal).addReg(Mask2);
1941  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1942  .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1943  BuildMI(BB, DL, TII->get(SC), Success)
1944  .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1945  BuildMI(BB, DL, TII->get(Mips::BEQ))
1946  .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1947 
1948  // sinkMBB:
1949  // srl srlres,maskedoldval0,shiftamt
1950  // sign_extend dest,srlres
1951  BB = sinkMBB;
1952 
1953  BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1954  .addReg(MaskedOldVal0).addReg(ShiftAmt);
1955  BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1956 
1957  MI.eraseFromParent(); // The instruction is gone now.
1958 
1959  return exitMBB;
1960 }
1961 
1962 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1963  // The first operand is the chain, the second is the condition, the third is
1964  // the block to branch to if the condition is true.
1965  SDValue Chain = Op.getOperand(0);
1966  SDValue Dest = Op.getOperand(2);
1967  SDLoc DL(Op);
1968 
1970  SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1971 
1972  // Return if flag is not set by a floating point comparison.
1973  if (CondRes.getOpcode() != MipsISD::FPCmp)
1974  return Op;
1975 
1976  SDValue CCNode = CondRes.getOperand(2);
1977  Mips::CondCode CC =
1978  (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1979  unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1980  SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1981  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1982  return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1983  FCC0, Dest, CondRes);
1984 }
1985 
1986 SDValue MipsTargetLowering::
1987 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1988 {
1990  SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1991 
1992  // Return if flag is not set by a floating point comparison.
1993  if (Cond.getOpcode() != MipsISD::FPCmp)
1994  return Op;
1995 
1996  return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1997  SDLoc(Op));
1998 }
1999 
2000 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2002  SDValue Cond = createFPCmp(DAG, Op);
2003 
2004  assert(Cond.getOpcode() == MipsISD::FPCmp &&
2005  "Floating point operand expected.");
2006 
2007  SDLoc DL(Op);
2008  SDValue True = DAG.getConstant(1, DL, MVT::i32);
2009  SDValue False = DAG.getConstant(0, DL, MVT::i32);
2010 
2011  return createCMovFP(DAG, Cond, True, False, DL);
2012 }
2013 
2014 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2015  SelectionDAG &DAG) const {
2016  EVT Ty = Op.getValueType();
2017  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2018  const GlobalValue *GV = N->getGlobal();
2019 
2020  if (!isPositionIndependent()) {
2021  const MipsTargetObjectFile *TLOF =
2022  static_cast<const MipsTargetObjectFile *>(
2024  const GlobalObject *GO = GV->getBaseObject();
2025  if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2026  // %gp_rel relocation
2027  return getAddrGPRel(N, SDLoc(N), Ty, DAG);
2028 
2029  // %hi/%lo relocation
2030  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2031  // %highest/%higher/%hi/%lo relocation
2032  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2033  }
2034 
2035  // Every other architecture would use shouldAssumeDSOLocal in here, but
2036  // mips is special.
2037  // * In PIC code mips requires got loads even for local statics!
2038  // * To save on got entries, for local statics the got entry contains the
2039  // page and an additional add instruction takes care of the low bits.
2040  // * It is legal to access a hidden symbol with a non hidden undefined,
2041  // so one cannot guarantee that all access to a hidden symbol will know
2042  // it is hidden.
2043  // * Mips linkers don't support creating a page and a full got entry for
2044  // the same symbol.
2045  // * Given all that, we have to use a full got entry for hidden symbols :-(
2046  if (GV->hasLocalLinkage())
2047  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2048 
2049  if (LargeGOT)
2050  return getAddrGlobalLargeGOT(
2052  DAG.getEntryNode(),
2053  MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2054 
2055  return getAddrGlobal(
2056  N, SDLoc(N), Ty, DAG,
2058  DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2059 }
2060 
2061 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2062  SelectionDAG &DAG) const {
2063  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2064  EVT Ty = Op.getValueType();
2065 
2066  if (!isPositionIndependent())
2067  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2068  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2069 
2070  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2071 }
2072 
2073 SDValue MipsTargetLowering::
2074 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2075 {
2076  // If the relocation model is PIC, use the General Dynamic TLS Model or
2077  // Local Dynamic TLS model, otherwise use the Initial Exec or
2078  // Local Exec TLS Model.
2079 
2080  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2081  if (DAG.getTarget().Options.EmulatedTLS)
2082  return LowerToTLSEmulatedModel(GA, DAG);
2083 
2084  SDLoc DL(GA);
2085  const GlobalValue *GV = GA->getGlobal();
2086  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2087 
2089 
2090  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2091  // General Dynamic and Local Dynamic TLS Model.
2092  unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2093  : MipsII::MO_TLSGD;
2094 
2095  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2096  SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2097  getGlobalReg(DAG, PtrVT), TGA);
2098  unsigned PtrSize = PtrVT.getSizeInBits();
2099  IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2100 
2101  SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2102 
2103  ArgListTy Args;
2104  ArgListEntry Entry;
2105  Entry.Node = Argument;
2106  Entry.Ty = PtrTy;
2107  Args.push_back(Entry);
2108 
2110  CLI.setDebugLoc(DL)
2111  .setChain(DAG.getEntryNode())
2112  .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2113  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2114 
2115  SDValue Ret = CallResult.first;
2116 
2117  if (model != TLSModel::LocalDynamic)
2118  return Ret;
2119 
2120  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2122  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2123  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2125  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2126  SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2127  return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2128  }
2129 
2130  SDValue Offset;
2131  if (model == TLSModel::InitialExec) {
2132  // Initial Exec TLS Model
2133  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2135  TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2136  TGA);
2137  Offset =
2138  DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2139  } else {
2140  // Local Exec TLS Model
2141  assert(model == TLSModel::LocalExec);
2142  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2144  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2146  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2147  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2148  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2149  }
2150 
2152  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2153 }
2154 
2155 SDValue MipsTargetLowering::
2156 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2157 {
2158  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2159  EVT Ty = Op.getValueType();
2160 
2161  if (!isPositionIndependent())
2162  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2163  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2164 
2165  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2166 }
2167 
2168 SDValue MipsTargetLowering::
2169 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2170 {
2171  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2172  EVT Ty = Op.getValueType();
2173 
2174  if (!isPositionIndependent()) {
2175  const MipsTargetObjectFile *TLOF =
2176  static_cast<const MipsTargetObjectFile *>(
2178 
2179  if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2180  getTargetMachine()))
2181  // %gp_rel relocation
2182  return getAddrGPRel(N, SDLoc(N), Ty, DAG);
2183 
2184  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2185  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2186  }
2187 
2188  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2189 }
2190 
2191 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2192  MachineFunction &MF = DAG.getMachineFunction();
2193  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2194 
2195  SDLoc DL(Op);
2196  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2197  getPointerTy(MF.getDataLayout()));
2198 
2199  // vastart just stores the address of the VarArgsFrameIndex slot into the
2200  // memory location argument.
2201  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2202  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2203  MachinePointerInfo(SV));
2204 }
2205 
2206 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2207  SDNode *Node = Op.getNode();
2208  EVT VT = Node->getValueType(0);
2209  SDValue Chain = Node->getOperand(0);
2210  SDValue VAListPtr = Node->getOperand(1);
2211  unsigned Align = Node->getConstantOperandVal(3);
2212  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2213  SDLoc DL(Node);
2214  unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2215 
2216  SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2217  VAListPtr, MachinePointerInfo(SV));
2218  SDValue VAList = VAListLoad;
2219 
2220  // Re-align the pointer if necessary.
2221  // It should only ever be necessary for 64-bit types on O32 since the minimum
2222  // argument alignment is the same as the maximum type alignment for N32/N64.
2223  //
2224  // FIXME: We currently align too often. The code generator doesn't notice
2225  // when the pointer is still aligned from the last va_arg (or pair of
2226  // va_args for the i64 on O32 case).
2227  if (Align > getMinStackArgumentAlignment()) {
2228  assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2229 
2230  VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2231  DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2232 
2233  VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2234  DAG.getConstant(-(int64_t)Align, DL,
2235  VAList.getValueType()));
2236  }
2237 
2238  // Increment the pointer, VAList, to the next vaarg.
2239  auto &TD = DAG.getDataLayout();
2240  unsigned ArgSizeInBytes =
2241  TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2242  SDValue Tmp3 =
2243  DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2244  DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2245  DL, VAList.getValueType()));
2246  // Store the incremented VAList to the legalized pointer
2247  Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2248  MachinePointerInfo(SV));
2249 
2250  // In big-endian mode we must adjust the pointer when the load size is smaller
2251  // than the argument slot size. We must also reduce the known alignment to
2252  // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2253  // the correct half of the slot, and reduce the alignment from 8 (slot
2254  // alignment) down to 4 (type alignment).
2255  if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2256  unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2257  VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2258  DAG.getIntPtrConstant(Adjustment, DL));
2259  }
2260  // Load the actual argument out of the pointer VAList
2261  return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2262 }
2263 
2265  bool HasExtractInsert) {
2266  EVT TyX = Op.getOperand(0).getValueType();
2267  EVT TyY = Op.getOperand(1).getValueType();
2268  SDLoc DL(Op);
2269  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2270  SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2271  SDValue Res;
2272 
2273  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2274  // to i32.
2275  SDValue X = (TyX == MVT::f32) ?
2276  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2278  Const1);
2279  SDValue Y = (TyY == MVT::f32) ?
2280  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2282  Const1);
2283 
2284  if (HasExtractInsert) {
2285  // ext E, Y, 31, 1 ; extract bit31 of Y
2286  // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2287  SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2288  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2289  } else {
2290  // sll SllX, X, 1
2291  // srl SrlX, SllX, 1
2292  // srl SrlY, Y, 31
2293  // sll SllY, SrlX, 31
2294  // or Or, SrlX, SllY
2295  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2296  SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2297  SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2298  SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2299  Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2300  }
2301 
2302  if (TyX == MVT::f32)
2303  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2304 
2306  Op.getOperand(0),
2307  DAG.getConstant(0, DL, MVT::i32));
2308  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2309 }
2310 
2312  bool HasExtractInsert) {
2313  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2314  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2315  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2316  SDLoc DL(Op);
2317  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2318 
2319  // Bitcast to integer nodes.
2320  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2321  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2322 
2323  if (HasExtractInsert) {
2324  // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2325  // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2326  SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2327  DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2328 
2329  if (WidthX > WidthY)
2330  E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2331  else if (WidthY > WidthX)
2332  E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2333 
2334  SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2335  DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2336  X);
2337  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2338  }
2339 
2340  // (d)sll SllX, X, 1
2341  // (d)srl SrlX, SllX, 1
2342  // (d)srl SrlY, Y, width(Y)-1
2343  // (d)sll SllY, SrlX, width(Y)-1
2344  // or Or, SrlX, SllY
2345  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2346  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2347  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2348  DAG.getConstant(WidthY - 1, DL, MVT::i32));
2349 
2350  if (WidthX > WidthY)
2351  SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2352  else if (WidthY > WidthX)
2353  SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2354 
2355  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2356  DAG.getConstant(WidthX - 1, DL, MVT::i32));
2357  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2358  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2359 }
2360 
2361 SDValue
2362 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2363  if (Subtarget.isGP64bit())
2364  return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2365 
2366  return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2367 }
2368 
2369 SDValue MipsTargetLowering::
2370 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2371  // check the depth
2372  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2373  "Frame address can only be determined for current frame.");
2374 
2376  MFI.setFrameAddressIsTaken(true);
2377  EVT VT = Op.getValueType();
2378  SDLoc DL(Op);
2379  SDValue FrameAddr = DAG.getCopyFromReg(
2380  DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2381  return FrameAddr;
2382 }
2383 
2384 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2385  SelectionDAG &DAG) const {
2387  return SDValue();
2388 
2389  // check the depth
2390  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2391  "Return address can be determined only for current frame.");
2392 
2393  MachineFunction &MF = DAG.getMachineFunction();
2394  MachineFrameInfo &MFI = MF.getFrameInfo();
2395  MVT VT = Op.getSimpleValueType();
2396  unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2397  MFI.setReturnAddressIsTaken(true);
2398 
2399  // Return RA, which contains the return address. Mark it an implicit live-in.
2400  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2401  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2402 }
2403 
2404 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2405 // generated from __builtin_eh_return (offset, handler)
2406 // The effect of this is to adjust the stack pointer by "offset"
2407 // and then branch to "handler".
2408 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2409  const {
2410  MachineFunction &MF = DAG.getMachineFunction();
2411  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2412 
2413  MipsFI->setCallsEhReturn();
2414  SDValue Chain = Op.getOperand(0);
2415  SDValue Offset = Op.getOperand(1);
2416  SDValue Handler = Op.getOperand(2);
2417  SDLoc DL(Op);
2418  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2419 
2420  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2421  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2422  unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2423  unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2424  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2425  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2426  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2427  DAG.getRegister(OffsetReg, Ty),
2428  DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2429  Chain.getValue(1));
2430 }
2431 
2432 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2433  SelectionDAG &DAG) const {
2434  // FIXME: Need pseudo-fence for 'singlethread' fences
2435  // FIXME: Set SType for weaker fences where supported/appropriate.
2436  unsigned SType = 0;
2437  SDLoc DL(Op);
2438  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2439  DAG.getConstant(SType, DL, MVT::i32));
2440 }
2441 
2442 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2443  SelectionDAG &DAG) const {
2444  SDLoc DL(Op);
2446 
2447  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2448  SDValue Shamt = Op.getOperand(2);
2449  // if shamt < (VT.bits):
2450  // lo = (shl lo, shamt)
2451  // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2452  // else:
2453  // lo = 0
2454  // hi = (shl lo, shamt[4:0])
2455  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2456  DAG.getConstant(-1, DL, MVT::i32));
2457  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2458  DAG.getConstant(1, DL, VT));
2459  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2460  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2461  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2462  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2463  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2464  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2465  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2466  DAG.getConstant(0, DL, VT), ShiftLeftLo);
2467  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2468 
2469  SDValue Ops[2] = {Lo, Hi};
2470  return DAG.getMergeValues(Ops, DL);
2471 }
2472 
2473 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2474  bool IsSRA) const {
2475  SDLoc DL(Op);
2476  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2477  SDValue Shamt = Op.getOperand(2);
2479 
2480  // if shamt < (VT.bits):
2481  // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2482  // if isSRA:
2483  // hi = (sra hi, shamt)
2484  // else:
2485  // hi = (srl hi, shamt)
2486  // else:
2487  // if isSRA:
2488  // lo = (sra hi, shamt[4:0])
2489  // hi = (sra hi, 31)
2490  // else:
2491  // lo = (srl hi, shamt[4:0])
2492  // hi = 0
2493  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2494  DAG.getConstant(-1, DL, MVT::i32));
2495  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2496  DAG.getConstant(1, DL, VT));
2497  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2498  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2499  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2500  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2501  DL, VT, Hi, Shamt);
2502  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2503  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2504  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2505  DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2506  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2507  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2508  IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2509 
2510  SDValue Ops[2] = {Lo, Hi};
2511  return DAG.getMergeValues(Ops, DL);
2512 }
2513 
2514 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2515  SDValue Chain, SDValue Src, unsigned Offset) {
2516  SDValue Ptr = LD->getBasePtr();
2517  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2518  EVT BasePtrVT = Ptr.getValueType();
2519  SDLoc DL(LD);
2520  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2521 
2522  if (Offset)
2523  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2524  DAG.getConstant(Offset, DL, BasePtrVT));
2525 
2526  SDValue Ops[] = { Chain, Ptr, Src };
2527  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2528  LD->getMemOperand());
2529 }
2530 
2531 // Expand an unaligned 32 or 64-bit integer load node.
2533  LoadSDNode *LD = cast<LoadSDNode>(Op);
2534  EVT MemVT = LD->getMemoryVT();
2535 
2537  return Op;
2538 
2539  // Return if load is aligned or if MemVT is neither i32 nor i64.
2540  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2541  ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2542  return SDValue();
2543 
2544  bool IsLittle = Subtarget.isLittle();
2545  EVT VT = Op.getValueType();
2546  ISD::LoadExtType ExtType = LD->getExtensionType();
2547  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2548 
2549  assert((VT == MVT::i32) || (VT == MVT::i64));
2550 
2551  // Expand
2552  // (set dst, (i64 (load baseptr)))
2553  // to
2554  // (set tmp, (ldl (add baseptr, 7), undef))
2555  // (set dst, (ldr baseptr, tmp))
2556  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2557  SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2558  IsLittle ? 7 : 0);
2559  return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2560  IsLittle ? 0 : 7);
2561  }
2562 
2563  SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2564  IsLittle ? 3 : 0);
2565  SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2566  IsLittle ? 0 : 3);
2567 
2568  // Expand
2569  // (set dst, (i32 (load baseptr))) or
2570  // (set dst, (i64 (sextload baseptr))) or
2571  // (set dst, (i64 (extload baseptr)))
2572  // to
2573  // (set tmp, (lwl (add baseptr, 3), undef))
2574  // (set dst, (lwr baseptr, tmp))
2575  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2576  (ExtType == ISD::EXTLOAD))
2577  return LWR;
2578 
2579  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2580 
2581  // Expand
2582  // (set dst, (i64 (zextload baseptr)))
2583  // to
2584  // (set tmp0, (lwl (add baseptr, 3), undef))
2585  // (set tmp1, (lwr baseptr, tmp0))
2586  // (set tmp2, (shl tmp1, 32))
2587  // (set dst, (srl tmp2, 32))
2588  SDLoc DL(LD);
2589  SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2590  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2591  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2592  SDValue Ops[] = { SRL, LWR.getValue(1) };
2593  return DAG.getMergeValues(Ops, DL);
2594 }
2595 
2596 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2597  SDValue Chain, unsigned Offset) {
2598  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2599  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2600  SDLoc DL(SD);
2601  SDVTList VTList = DAG.getVTList(MVT::Other);
2602 
2603  if (Offset)
2604  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2605  DAG.getConstant(Offset, DL, BasePtrVT));
2606 
2607  SDValue Ops[] = { Chain, Value, Ptr };
2608  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2609  SD->getMemOperand());
2610 }
2611 
2612 // Expand an unaligned 32 or 64-bit integer store node.
2614  bool IsLittle) {
2615  SDValue Value = SD->getValue(), Chain = SD->getChain();
2616  EVT VT = Value.getValueType();
2617 
2618  // Expand
2619  // (store val, baseptr) or
2620  // (truncstore val, baseptr)
2621  // to
2622  // (swl val, (add baseptr, 3))
2623  // (swr val, baseptr)
2624  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2625  SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2626  IsLittle ? 3 : 0);
2627  return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2628  }
2629 
2630  assert(VT == MVT::i64);
2631 
2632  // Expand
2633  // (store val, baseptr)
2634  // to
2635  // (sdl val, (add baseptr, 7))
2636  // (sdr val, baseptr)
2637  SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2638  return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2639 }
2640 
2641 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2643  SDValue Val = SD->getValue();
2644 
2645  if (Val.getOpcode() != ISD::FP_TO_SINT)
2646  return SDValue();
2647 
2649  SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2650  Val.getOperand(0));
2651  return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2652  SD->getPointerInfo(), SD->getAlignment(),
2653  SD->getMemOperand()->getFlags());
2654 }
2655 
2657  StoreSDNode *SD = cast<StoreSDNode>(Op);
2658  EVT MemVT = SD->getMemoryVT();
2659 
2660  // Lower unaligned integer stores.
2662  (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2663  ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2664  return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2665 
2666  return lowerFP_TO_SINT_STORE(SD, DAG);
2667 }
2668 
2669 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2670  SelectionDAG &DAG) const {
2671 
2672  // Return a fixed StackObject with offset 0 which points to the old stack
2673  // pointer.
2675  EVT ValTy = Op->getValueType(0);
2676  int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2677  return DAG.getFrameIndex(FI, ValTy);
2678 }
2679 
2680 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2681  SelectionDAG &DAG) const {
2683  SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2684  Op.getOperand(0));
2685  return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2686 }
2687 
2688 //===----------------------------------------------------------------------===//
2689 // Calling Convention Implementation
2690 //===----------------------------------------------------------------------===//
2691 
2692 //===----------------------------------------------------------------------===//
2693 // TODO: Implement a generic logic using tblgen that can support this.
2694 // Mips O32 ABI rules:
2695 // ---
2696 // i32 - Passed in A0, A1, A2, A3 and stack
2697 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2698 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2699 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2700 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2701 // not used, it must be shadowed. If only A3 is available, shadow it and
2702 // go to stack.
2703 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2704 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2705 // with the remainder spilled to the stack.
2706 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2707 // spilling the remainder to the stack.
2708 //
2709 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2710 //===----------------------------------------------------------------------===//
2711 
2712 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2713  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2714  CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2715  const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2716  State.getMachineFunction().getSubtarget());
2717 
2718  static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2719 
2720  const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2721 
2722  static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2723 
2724  static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2725 
2726  // Do not process byval args here.
2727  if (ArgFlags.isByVal())
2728  return true;
2729 
2730  // Promote i8 and i16
2731  if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2732  if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2733  LocVT = MVT::i32;
2734  if (ArgFlags.isSExt())
2735  LocInfo = CCValAssign::SExtUpper;
2736  else if (ArgFlags.isZExt())
2737  LocInfo = CCValAssign::ZExtUpper;
2738  else
2739  LocInfo = CCValAssign::AExtUpper;
2740  }
2741  }
2742 
2743  // Promote i8 and i16
2744  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2745  LocVT = MVT::i32;
2746  if (ArgFlags.isSExt())
2747  LocInfo = CCValAssign::SExt;
2748  else if (ArgFlags.isZExt())
2749  LocInfo = CCValAssign::ZExt;
2750  else
2751  LocInfo = CCValAssign::AExt;
2752  }
2753 
2754  unsigned Reg;
2755 
2756  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2757  // is true: function is vararg, argument is 3rd or higher, there is previous
2758  // argument which is not f32 or f64.
2759  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2760  State.getFirstUnallocated(F32Regs) != ValNo;
2761  unsigned OrigAlign = ArgFlags.getOrigAlign();
2762  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2763  bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2764 
2765  // The MIPS vector ABI for floats passes them in a pair of registers
2766  if (ValVT == MVT::i32 && isVectorFloat) {
2767  // This is the start of an vector that was scalarized into an unknown number
2768  // of components. It doesn't matter how many there are. Allocate one of the
2769  // notional 8 byte aligned registers which map onto the argument stack, and
2770  // shadow the register lost to alignment requirements.
2771  if (ArgFlags.isSplit()) {
2772  Reg = State.AllocateReg(FloatVectorIntRegs);
2773  if (Reg == Mips::A2)
2774  State.AllocateReg(Mips::A1);
2775  else if (Reg == 0)
2776  State.AllocateReg(Mips::A3);
2777  } else {
2778  // If we're an intermediate component of the split, we can just attempt to
2779  // allocate a register directly.
2780  Reg = State.AllocateReg(IntRegs);
2781  }
2782  } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2783  Reg = State.AllocateReg(IntRegs);
2784  // If this is the first part of an i64 arg,
2785  // the allocated register must be either A0 or A2.
2786  if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2787  Reg = State.AllocateReg(IntRegs);
2788  LocVT = MVT::i32;
2789  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2790  // Allocate int register and shadow next int register. If first
2791  // available register is Mips::A1 or Mips::A3, shadow it too.
2792  Reg = State.AllocateReg(IntRegs);
2793  if (Reg == Mips::A1 || Reg == Mips::A3)
2794  Reg = State.AllocateReg(IntRegs);
2795  State.AllocateReg(IntRegs);
2796  LocVT = MVT::i32;
2797  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2798  // we are guaranteed to find an available float register
2799  if (ValVT == MVT::f32) {
2800  Reg = State.AllocateReg(F32Regs);
2801  // Shadow int register
2802  State.AllocateReg(IntRegs);
2803  } else {
2804  Reg = State.AllocateReg(F64Regs);
2805  // Shadow int registers
2806  unsigned Reg2 = State.AllocateReg(IntRegs);
2807  if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2808  State.AllocateReg(IntRegs);
2809  State.AllocateReg(IntRegs);
2810  }
2811  } else
2812  llvm_unreachable("Cannot handle this ValVT.");
2813 
2814  if (!Reg) {
2815  unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2816  OrigAlign);
2817  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2818  } else
2819  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2820 
2821  return false;
2822 }
2823 
2824 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2825  MVT LocVT, CCValAssign::LocInfo LocInfo,
2826  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2827  static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2828 
2829  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2830 }
2831 
2832 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2833  MVT LocVT, CCValAssign::LocInfo LocInfo,
2834  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2835  static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2836 
2837  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2838 }
2839 
2840 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2841  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2843 
2844 #include "MipsGenCallingConv.inc"
2845 
2846 //===----------------------------------------------------------------------===//
2847 // Call Calling Convention Implementation
2848 //===----------------------------------------------------------------------===//
2849 
2850 // Return next O32 integer argument register.
2851 static unsigned getNextIntArgReg(unsigned Reg) {
2852  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2853  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2854 }
2855 
2856 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2857  SDValue Chain, SDValue Arg,
2858  const SDLoc &DL, bool IsTailCall,
2859  SelectionDAG &DAG) const {
2860  if (!IsTailCall) {
2861  SDValue PtrOff =
2862  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2863  DAG.getIntPtrConstant(Offset, DL));
2864  return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2865  }
2866 
2868  int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2869  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2870  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2871  /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2872 }
2873 
2876  std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2877  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2878  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2879  SDValue Chain) const {
2880  // Insert node "GP copy globalreg" before call to function.
2881  //
2882  // R_MIPS_CALL* operators (emitted when non-internal functions are called
2883  // in PIC mode) allow symbols to be resolved via lazy binding.
2884  // The lazy binding stub requires GP to point to the GOT.
2885  // Note that we don't need GP to point to the GOT for indirect calls
2886  // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2887  // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2888  // used for the function (that is, Mips linker doesn't generate lazy binding
2889  // stub for a function whose address is taken in the program).
2890  if (IsPICCall && !InternalLinkage && IsCallReloc) {
2891  unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2892  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2893  RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2894  }
2895 
2896  // Build a sequence of copy-to-reg nodes chained together with token
2897  // chain and flag operands which copy the outgoing args into registers.
2898  // The InFlag in necessary since all emitted instructions must be
2899  // stuck together.
2900  SDValue InFlag;
2901 
2902  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2903  Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2904  RegsToPass[i].second, InFlag);
2905  InFlag = Chain.getValue(1);
2906  }
2907 
2908  // Add argument registers to the end of the list so that they are
2909  // known live into the call.
2910  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2911  Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2912  RegsToPass[i].second.getValueType()));
2913 
2914  // Add a register mask operand representing the call-preserved registers.
2916  const uint32_t *Mask =
2918  assert(Mask && "Missing call preserved mask for calling convention");
2919  if (Subtarget.inMips16HardFloat()) {
2920  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2921  llvm::StringRef Sym = G->getGlobal()->getName();
2922  Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2923  if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2925  }
2926  }
2927  }
2928  Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2929 
2930  if (InFlag.getNode())
2931  Ops.push_back(InFlag);
2932 }
2933 
2934 /// LowerCall - functions arguments are copied from virtual regs to
2935 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2936 SDValue
2937 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2938  SmallVectorImpl<SDValue> &InVals) const {
2939  SelectionDAG &DAG = CLI.DAG;
2940  SDLoc DL = CLI.DL;
2942  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2944  SDValue Chain = CLI.Chain;
2945  SDValue Callee = CLI.Callee;
2946  bool &IsTailCall = CLI.IsTailCall;
2947  CallingConv::ID CallConv = CLI.CallConv;
2948  bool IsVarArg = CLI.IsVarArg;
2949 
2950  MachineFunction &MF = DAG.getMachineFunction();
2951  MachineFrameInfo &MFI = MF.getFrameInfo();
2953  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2954  bool IsPIC = isPositionIndependent();
2955 
2956  // Analyze operands of the call, assigning locations to each operand.
2958  MipsCCState CCInfo(
2959  CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2961 
2962  // Allocate the reserved argument area. It seems strange to do this from the
2963  // caller side but removing it breaks the frame size calculation.
2964  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2965 
2966  const ExternalSymbolSDNode *ES =
2967  dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
2968  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
2969  ES ? ES->getSymbol() : nullptr);
2970 
2971  // Get a count of how many bytes are to be pushed on the stack.
2972  unsigned NextStackOffset = CCInfo.getNextStackOffset();
2973 
2974  // Check if it's really possible to do a tail call. Restrict it to functions
2975  // that are part of this compilation unit.
2976  bool InternalLinkage = false;
2977  if (IsTailCall) {
2978  IsTailCall = isEligibleForTailCallOptimization(
2979  CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2980  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2981  InternalLinkage = G->getGlobal()->hasInternalLinkage();
2982  IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
2983  G->getGlobal()->hasPrivateLinkage() ||
2984  G->getGlobal()->hasHiddenVisibility() ||
2985  G->getGlobal()->hasProtectedVisibility());
2986  }
2987  }
2988  if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2989  report_fatal_error("failed to perform tail call elimination on a call "
2990  "site marked musttail");
2991 
2992  if (IsTailCall)
2993  ++NumTailCalls;
2994 
2995  // Chain is the output chain of the last Load/Store or CopyToReg node.
2996  // ByValChain is the output chain of the last Memcpy node created for copying
2997  // byval arguments to the stack.
2998  unsigned StackAlignment = TFL->getStackAlignment();
2999  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3000  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3001 
3002  if (!IsTailCall)
3003  Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3004 
3005  SDValue StackPtr =
3006  DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3007  getPointerTy(DAG.getDataLayout()));
3008 
3009  std::deque< std::pair<unsigned, SDValue> > RegsToPass;
3010  SmallVector<SDValue, 8> MemOpChains;
3011 
3012  CCInfo.rewindByValRegsInfo();
3013 
3014  // Walk the register/memloc assignments, inserting copies/loads.
3015  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3016  SDValue Arg = OutVals[i];
3017  CCValAssign &VA = ArgLocs[i];
3018  MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3019  ISD::ArgFlagsTy Flags = Outs[i].Flags;
3020  bool UseUpperBits = false;
3021 
3022  // ByVal Arg.
3023  if (Flags.isByVal()) {
3024  unsigned FirstByValReg, LastByValReg;
3025  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3026  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3027 
3028  assert(Flags.getByValSize() &&
3029  "ByVal args of size 0 should have been ignored by front-end.");
3030  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3031  assert(!IsTailCall &&
3032  "Do not tail-call optimize if there is a byval argument.");
3033  passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3034  FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3035  VA);
3036  CCInfo.nextInRegsParam();
3037  continue;
3038  }
3039 
3040  // Promote the value if needed.
3041  switch (VA.getLocInfo()) {
3042  default:
3043  llvm_unreachable("Unknown loc info!");
3044  case CCValAssign::Full:
3045  if (VA.isRegLoc()) {
3046  if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3047  (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3048  (ValVT == MVT::i64 && LocVT == MVT::f64))
3049  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3050  else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3052  Arg, DAG.getConstant(0, DL, MVT::i32));
3054  Arg, DAG.getConstant(1, DL, MVT::i32));
3055  if (!Subtarget.isLittle())
3056  std::swap(Lo, Hi);
3057  unsigned LocRegLo = VA.getLocReg();
3058  unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3059  RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3060  RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3061  continue;
3062  }
3063  }
3064  break;
3065  case CCValAssign::BCvt:
3066  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3067  break;
3069  UseUpperBits = true;
3071  case CCValAssign::SExt:
3072  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3073  break;
3075  UseUpperBits = true;
3077  case CCValAssign::ZExt:
3078  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3079  break;
3081  UseUpperBits = true;
3083  case CCValAssign::AExt:
3084  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3085  break;
3086  }
3087 
3088  if (UseUpperBits) {
3089  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3090  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3091  Arg = DAG.getNode(
3092  ISD::SHL, DL, VA.getLocVT(), Arg,
3093  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3094  }
3095 
3096  // Arguments that can be passed on register must be kept at
3097  // RegsToPass vector
3098  if (VA.isRegLoc()) {
3099  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3100  continue;
3101  }
3102 
3103  // Register can't get to this point...
3104  assert(VA.isMemLoc());
3105 
3106  // emit ISD::STORE whichs stores the
3107  // parameter value to a stack Location
3108  MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3109  Chain, Arg, DL, IsTailCall, DAG));
3110  }
3111 
3112  // Transform all store nodes into one single node because all store
3113  // nodes are independent of each other.
3114  if (!MemOpChains.empty())
3115  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3116 
3117  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3118  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3119  // node so that legalize doesn't hack it.
3120 
3121  SDValue CalleeLo;
3122  EVT Ty = Callee.getValueType();
3123  bool GlobalOrExternal = false, IsCallReloc = false;
3124 
3125  // The long-calls feature is ignored in case of PIC.
3126  // While we do not support -mshared / -mno-shared properly,
3127  // ignore long-calls in case of -mabicalls too.
3128  if (!Subtarget.isABICalls() && !IsPIC) {
3129  // If the function should be called using "long call",
3130  // get its address into a register to prevent using
3131  // of the `jal` instruction for the direct call.
3132  if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3133  if (Subtarget.useLongCalls())
3134  Callee = Subtarget.hasSym32()
3135  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3136  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3137  } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3138  bool UseLongCalls = Subtarget.useLongCalls();
3139  // If the function has long-call/far/near attribute
3140  // it overrides command line switch pased to the backend.
3141  if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3142  if (F->hasFnAttribute("long-call"))
3143  UseLongCalls = true;
3144  else if (F->hasFnAttribute("short-call"))
3145  UseLongCalls = false;
3146  }
3147  if (UseLongCalls)
3148  Callee = Subtarget.hasSym32()
3149  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3150  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3151  }
3152  }
3153 
3154  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3155  if (IsPIC) {
3156  const GlobalValue *Val = G->getGlobal();
3157  InternalLinkage = Val->hasInternalLinkage();
3158 
3159  if (InternalLinkage)
3160  Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3161  else if (LargeGOT) {
3162  Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3163  MipsII::MO_CALL_LO16, Chain,
3164  FuncInfo->callPtrInfo(Val));
3165  IsCallReloc = true;
3166  } else {
3167  Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3168  FuncInfo->callPtrInfo(Val));
3169  IsCallReloc = true;
3170  }
3171  } else
3172  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3173  getPointerTy(DAG.getDataLayout()), 0,
3175  GlobalOrExternal = true;
3176  }
3177  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3178  const char *Sym = S->getSymbol();
3179 
3180  if (!IsPIC) // static
3181  Callee = DAG.getTargetExternalSymbol(
3183  else if (LargeGOT) {
3184  Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3185  MipsII::MO_CALL_LO16, Chain,
3186  FuncInfo->callPtrInfo(Sym));
3187  IsCallReloc = true;
3188  } else { // PIC
3189  Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3190  FuncInfo->callPtrInfo(Sym));
3191  IsCallReloc = true;
3192  }
3193 
3194  GlobalOrExternal = true;
3195  }
3196 
3197  SmallVector<SDValue, 8> Ops(1, Chain);
3198  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3199 
3200  getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3201  IsCallReloc, CLI, Callee, Chain);
3202 
3203  if (IsTailCall) {
3205  return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3206  }
3207 
3208  Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3209  SDValue InFlag = Chain.getValue(1);
3210 
3211  // Create the CALLSEQ_END node.
3212  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3213  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3214  InFlag = Chain.getValue(1);
3215 
3216  // Handle result values, copying them out of physregs into vregs that we
3217  // return.
3218  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3219  InVals, CLI);
3220 }
3221 
3222 /// LowerCallResult - Lower the result values of a call into the
3223 /// appropriate copies out of appropriate physical registers.
3224 SDValue MipsTargetLowering::LowerCallResult(
3225  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3226  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3227  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3228  TargetLowering::CallLoweringInfo &CLI) const {
3229  // Assign locations to each value returned by this call.
3231  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3232  *DAG.getContext());
3233 
3234  const ExternalSymbolSDNode *ES =
3235  dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3236  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3237  ES ? ES->getSymbol() : nullptr);
3238 
3239  // Copy all of the result registers out of their specified physreg.
3240  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3241  CCValAssign &VA = RVLocs[i];
3242  assert(VA.isRegLoc() && "Can only return in registers!");
3243 
3244  SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3245  RVLocs[i].getLocVT(), InFlag);
3246  Chain = Val.getValue(1);
3247  InFlag = Val.getValue(2);
3248 
3249  if (VA.isUpperBitsInLoc()) {
3250  unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3251  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3252  unsigned Shift =
3254  Val = DAG.getNode(
3255  Shift, DL, VA.getLocVT(), Val,
3256  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3257  }
3258 
3259  switch (VA.getLocInfo()) {
3260  default:
3261  llvm_unreachable("Unknown loc info!");
3262  case CCValAssign::Full:
3263  break;
3264  case CCValAssign::BCvt:
3265  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3266  break;
3267  case CCValAssign::AExt:
3269  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3270  break;
3271  case CCValAssign::ZExt:
3273  Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3274  DAG.getValueType(VA.getValVT()));
3275  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3276  break;
3277  case CCValAssign::SExt:
3279  Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3280  DAG.getValueType(VA.getValVT()));
3281  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3282  break;
3283  }
3284 
3285  InVals.push_back(Val);
3286  }
3287 
3288  return Chain;
3289 }
3290 
3292  EVT ArgVT, const SDLoc &DL,
3293  SelectionDAG &DAG) {
3294  MVT LocVT = VA.getLocVT();
3295  EVT ValVT = VA.getValVT();
3296 
3297  // Shift into the upper bits if necessary.
3298  switch (VA.getLocInfo()) {
3299  default:
3300  break;
3303  case CCValAssign::ZExtUpper: {
3304  unsigned ValSizeInBits = ArgVT.getSizeInBits();
3305  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3306  unsigned Opcode =
3308  Val = DAG.getNode(
3309  Opcode, DL, VA.getLocVT(), Val,
3310  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3311  break;
3312  }
3313  }
3314 
3315  // If this is an value smaller than the argument slot size (32-bit for O32,
3316  // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3317  // size. Extract the value and insert any appropriate assertions regarding
3318  // sign/zero extension.
3319  switch (VA.getLocInfo()) {
3320  default:
3321  llvm_unreachable("Unknown loc info!");
3322  case CCValAssign::Full:
3323  break;
3325  case CCValAssign::AExt:
3326  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3327  break;
3329  case CCValAssign::SExt:
3330  Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3331  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3332  break;
3334  case CCValAssign::ZExt:
3335  Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3336  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3337  break;
3338  case CCValAssign::BCvt:
3339  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3340  break;
3341  }
3342 
3343  return Val;
3344 }
3345 
3346 //===----------------------------------------------------------------------===//
3347 // Formal Arguments Calling Convention Implementation
3348 //===----------------------------------------------------------------------===//
3349 /// LowerFormalArguments - transform physical registers into virtual registers
3350 /// and generate load operations for arguments places on the stack.
3351 SDValue MipsTargetLowering::LowerFormalArguments(
3352  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3353  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3354  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3355  MachineFunction &MF = DAG.getMachineFunction();
3356  MachineFrameInfo &MFI = MF.getFrameInfo();
3357  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3358 
3359  MipsFI->setVarArgsFrameIndex(0);
3360 
3361  // Used with vargs to acumulate store chains.
3362  std::vector<SDValue> OutChains;
3363 
3364  // Assign locations to all of the incoming arguments.
3366  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3367  *DAG.getContext());
3368  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3369  const Function *Func = DAG.getMachineFunction().getFunction();
3370  Function::const_arg_iterator FuncArg = Func->arg_begin();
3371 
3372  if (Func->hasFnAttribute("interrupt") && !Func->arg_empty())
3374  "Functions with the interrupt attribute cannot have arguments!");
3375 
3376  CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3377  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3378  CCInfo.getInRegsParamsCount() > 0);
3379 
3380  unsigned CurArgIdx = 0;
3381  CCInfo.rewindByValRegsInfo();
3382 
3383  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3384  CCValAssign &VA = ArgLocs[i];
3385  if (Ins[i].isOrigArg()) {
3386  std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3387  CurArgIdx = Ins[i].getOrigArgIndex();
3388  }
3389  EVT ValVT = VA.getValVT();
3390  ISD::ArgFlagsTy Flags = Ins[i].Flags;
3391  bool IsRegLoc = VA.isRegLoc();
3392 
3393  if (Flags.isByVal()) {
3394  assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3395  unsigned FirstByValReg, LastByValReg;
3396  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3397  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3398 
3399  assert(Flags.getByValSize() &&
3400  "ByVal args of size 0 should have been ignored by front-end.");
3401  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3402  copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3403  FirstByValReg, LastByValReg, VA, CCInfo);
3404  CCInfo.nextInRegsParam();
3405  continue;
3406  }
3407 
3408  // Arguments stored on registers
3409  if (IsRegLoc) {
3410  MVT RegVT = VA.getLocVT();
3411  unsigned ArgReg = VA.getLocReg();
3412  const TargetRegisterClass *RC = getRegClassFor(RegVT);
3413 
3414  // Transform the arguments stored on
3415  // physical registers into virtual ones
3416  unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3417  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3418 
3419  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3420 
3421  // Handle floating point arguments passed in integer registers and
3422  // long double arguments passed in floating point registers.
3423  if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3424  (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3425  (RegVT == MVT::f64 && ValVT == MVT::i64))
3426  ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3427  else if (ABI.IsO32() && RegVT == MVT::i32 &&
3428  ValVT == MVT::f64) {
3429  unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3430  getNextIntArgReg(ArgReg), RC);
3431  SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3432  if (!Subtarget.isLittle())
3433  std::swap(ArgValue, ArgValue2);
3434  ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3435  ArgValue, ArgValue2);
3436  }
3437 
3438  InVals.push_back(ArgValue);
3439  } else { // VA.isRegLoc()
3440  MVT LocVT = VA.getLocVT();
3441 
3442  if (ABI.IsO32()) {
3443  // We ought to be able to use LocVT directly but O32 sets it to i32
3444  // when allocating floating point values to integer registers.
3445  // This shouldn't influence how we load the value into registers unless
3446  // we are targeting softfloat.
3448  LocVT = VA.getValVT();
3449  }
3450 
3451  // sanity check
3452  assert(VA.isMemLoc());
3453 
3454  // The stack pointer offset is relative to the caller stack frame.
3455  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3456  VA.getLocMemOffset(), true);
3457 
3458  // Create load nodes to retrieve arguments from the stack
3459  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3460  SDValue ArgValue = DAG.getLoad(
3461  LocVT, DL, Chain, FIN,
3463  OutChains.push_back(ArgValue.getValue(1));
3464 
3465  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3466 
3467  InVals.push_back(ArgValue);
3468  }
3469  }
3470 
3471  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3472  // The mips ABIs for returning structs by value requires that we copy
3473  // the sret argument into $v0 for the return. Save the argument into
3474  // a virtual register so that we can access it from the return points.
3475  if (Ins[i].Flags.isSRet()) {
3476  unsigned Reg = MipsFI->getSRetReturnReg();
3477  if (!Reg) {
3478  Reg = MF.getRegInfo().createVirtualRegister(
3480  MipsFI->setSRetReturnReg(Reg);
3481  }
3482  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3483  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3484  break;
3485  }
3486  }
3487 
3488  if (IsVarArg)
3489  writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3490 
3491  // All stores are grouped in one node to allow the matching between
3492  // the size of Ins and InVals. This only happens when on varg functions
3493  if (!OutChains.empty()) {
3494  OutChains.push_back(Chain);
3495  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3496  }
3497 
3498  return Chain;
3499 }
3500 
3501 //===----------------------------------------------------------------------===//
3502 // Return Value Calling Convention Implementation
3503 //===----------------------------------------------------------------------===//
3504 
3505 bool
3506 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3507  MachineFunction &MF, bool IsVarArg,
3508  const SmallVectorImpl<ISD::OutputArg> &Outs,
3509  LLVMContext &Context) const {
3511  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3512  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3513 }
3514 
3515 bool
3516 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3518  if (Type == MVT::i32)
3519  return true;
3520  }
3521  return IsSigned;
3522 }
3523 
3524 SDValue
3525 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3526  const SDLoc &DL,
3527  SelectionDAG &DAG) const {
3528 
3529  MachineFunction &MF = DAG.getMachineFunction();
3530  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3531 
3532  MipsFI->setISR();
3533 
3534  return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3535 }
3536 
3537 SDValue
3538 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3539  bool IsVarArg,
3540  const SmallVectorImpl<ISD::OutputArg> &Outs,
3541  const SmallVectorImpl<SDValue> &OutVals,
3542  const SDLoc &DL, SelectionDAG &DAG) const {
3543  // CCValAssign - represent the assignment of
3544  // the return value to a location
3546  MachineFunction &MF = DAG.getMachineFunction();
3547 
3548  // CCState - Info about the registers and stack slot.
3549  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3550 
3551  // Analyze return values.
3552  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3553 
3554  SDValue Flag;
3555  SmallVector<SDValue, 4> RetOps(1, Chain);
3556 
3557  // Copy the result values into the output registers.
3558  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3559  SDValue Val = OutVals[i];
3560  CCValAssign &VA = RVLocs[i];
3561  assert(VA.isRegLoc() && "Can only return in registers!");
3562  bool UseUpperBits = false;
3563 
3564  switch (VA.getLocInfo()) {
3565  default:
3566  llvm_unreachable("Unknown loc info!");
3567  case CCValAssign::Full:
3568  break;
3569  case CCValAssign::BCvt:
3570  Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3571  break;
3573  UseUpperBits = true;
3575  case CCValAssign::AExt:
3576  Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3577  break;
3579  UseUpperBits = true;
3581  case CCValAssign::ZExt:
3582  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3583  break;
3585  UseUpperBits = true;
3587  case CCValAssign::SExt:
3588  Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3589  break;
3590  }
3591 
3592  if (UseUpperBits) {
3593  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3594  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3595  Val = DAG.getNode(
3596  ISD::SHL, DL, VA.getLocVT(), Val,
3597  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3598  }
3599 
3600  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3601 
3602  // Guarantee that all emitted copies are stuck together with flags.
3603  Flag = Chain.getValue(1);
3604  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3605  }
3606 
3607  // The mips ABIs for returning structs by value requires that we copy
3608  // the sret argument into $v0 for the return. We saved the argument into
3609  // a virtual register in the entry block, so now we copy the value out
3610  // and into $v0.
3611  if (MF.getFunction()->hasStructRetAttr()) {
3612  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3613  unsigned Reg = MipsFI->getSRetReturnReg();
3614 
3615  if (!Reg)
3616  llvm_unreachable("sret virtual register not created in the entry block");
3617  SDValue Val =
3618  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3619  unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3620 
3621  Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3622  Flag = Chain.getValue(1);
3623  RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3624  }
3625 
3626  RetOps[0] = Chain; // Update chain.
3627 
3628  // Add the flag if we have it.
3629  if (Flag.getNode())
3630  RetOps.push_back(Flag);
3631 
3632  // ISRs must use "eret".
3633  if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
3634  return LowerInterruptReturn(RetOps, DL, DAG);
3635 
3636  // Standard return on Mips is a "jr $ra"
3637  return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3638 }
3639 
3640 //===----------------------------------------------------------------------===//
3641 // Mips Inline Assembly Support
3642 //===----------------------------------------------------------------------===//
3643 
3644 /// getConstraintType - Given a constraint letter, return the type of
3645 /// constraint it is for this target.
3647 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3648  // Mips specific constraints
3649  // GCC config/mips/constraints.md
3650  //
3651  // 'd' : An address register. Equivalent to r
3652  // unless generating MIPS16 code.
3653  // 'y' : Equivalent to r; retained for
3654  // backwards compatibility.
3655  // 'c' : A register suitable for use in an indirect
3656  // jump. This will always be $25 for -mabicalls.
3657  // 'l' : The lo register. 1 word storage.
3658  // 'x' : The hilo register pair. Double word storage.
3659  if (Constraint.size() == 1) {
3660  switch (Constraint[0]) {
3661  default : break;
3662  case 'd':
3663  case 'y':
3664  case 'f':
3665  case 'c':
3666  case 'l':
3667  case 'x':
3668  return C_RegisterClass;
3669  case 'R':
3670  return C_Memory;
3671  }
3672  }
3673 
3674  if (Constraint == "ZC")
3675  return C_Memory;
3676 
3677  return TargetLowering::getConstraintType(Constraint);
3678 }
3679 
3680 /// Examine constraint type and operand type and determine a weight value.
3681 /// This object must already have been set up with the operand type
3682 /// and the current alternative constraint selected.
3684 MipsTargetLowering::getSingleConstraintMatchWeight(
3685  AsmOperandInfo &info, const char *constraint) const {
3686  ConstraintWeight weight = CW_Invalid;
3687  Value *CallOperandVal = info.CallOperandVal;
3688  // If we don't have a value, we can't do a match,
3689  // but allow it at the lowest weight.
3690  if (!CallOperandVal)
3691  return CW_Default;
3692  Type *type = CallOperandVal->getType();
3693  // Look at the constraint type.
3694  switch (*constraint) {
3695  default:
3696  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3697  break;
3698  case 'd':
3699  case 'y':
3700  if (type->isIntegerTy())
3701  weight = CW_Register;
3702  break;
3703  case 'f': // FPU or MSA register
3704  if (Subtarget.hasMSA() && type->isVectorTy() &&
3705  cast<VectorType>(type)->getBitWidth() == 128)
3706  weight = CW_Register;
3707  else if (type->isFloatTy())
3708  weight = CW_Register;
3709  break;
3710  case 'c': // $25 for indirect jumps
3711  case 'l': // lo register
3712  case 'x': // hilo register pair
3713  if (type->isIntegerTy())
3714  weight = CW_SpecificReg;
3715  break;
3716  case 'I': // signed 16 bit immediate
3717  case 'J': // integer zero
3718  case 'K': // unsigned 16 bit immediate
3719  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3720  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3721  case 'O': // signed 15 bit immediate (+- 16383)
3722  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3723  if (isa<ConstantInt>(CallOperandVal))
3724  weight = CW_Constant;
3725  break;
3726  case 'R':
3727  weight = CW_Memory;
3728  break;
3729  }
3730  return weight;
3731 }
3732 
3733 /// This is a helper function to parse a physical register string and split it
3734 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3735 /// that is returned indicates whether parsing was successful. The second flag
3736 /// is true if the numeric part exists.
3737 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3738  unsigned long long &Reg) {
3739  if (C.front() != '{' || C.back() != '}')
3740  return std::make_pair(false, false);
3741 
3742  // Search for the first numeric character.
3743  StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3744  I = std::find_if(B, E, isdigit);
3745 
3746  Prefix = StringRef(B, I - B);
3747 
3748  // The second flag is set to false if no numeric characters were found.
3749  if (I == E)
3750  return std::make_pair(true, false);
3751 
3752  // Parse the numeric characters.
3753  return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3754  true);
3755 }
3756 
3757 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3758 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3759  const TargetRegisterInfo *TRI =
3761  const TargetRegisterClass *RC;
3762  StringRef Prefix;
3763  unsigned long long Reg;
3764 
3765  std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3766 
3767  if (!R.first)
3768  return std::make_pair(0U, nullptr);
3769 
3770  if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3771  // No numeric characters follow "hi" or "lo".
3772  if (R.second)
3773  return std::make_pair(0U, nullptr);
3774 
3775  RC = TRI->getRegClass(Prefix == "hi" ?
3776  Mips::HI32RegClassID : Mips::LO32RegClassID);
3777  return std::make_pair(*(RC->begin()), RC);
3778  } else if (Prefix.startswith("$msa")) {
3779  // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3780 
3781  // No numeric characters follow the name.
3782  if (R.second)
3783  return std::make_pair(0U, nullptr);
3784 
3786  .Case("$msair", Mips::MSAIR)
3787  .Case("$msacsr", Mips::MSACSR)
3788  .Case("$msaaccess", Mips::MSAAccess)
3789  .Case("$msasave", Mips::MSASave)
3790  .Case("$msamodify", Mips::MSAModify)
3791  .Case("$msarequest", Mips::MSARequest)
3792  .Case("$msamap", Mips::MSAMap)
3793  .Case("$msaunmap", Mips::MSAUnmap)
3794  .Default(0);
3795 
3796  if (!Reg)
3797  return std::make_pair(0U, nullptr);
3798 
3799  RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3800  return std::make_pair(Reg, RC);
3801  }
3802 
3803  if (!R.second)
3804  return std::make_pair(0U, nullptr);
3805 
3806  if (Prefix == "$f") { // Parse $f0-$f31.
3807  // If the size of FP registers is 64-bit or Reg is an even number, select
3808  // the 64-bit register class. Otherwise, select the 32-bit register class.
3809  if (VT == MVT::Other)
3810  VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3811 
3812  RC = getRegClassFor(VT);
3813 
3814  if (RC == &Mips::AFGR64RegClass) {
3815  assert(Reg % 2 == 0);
3816  Reg >>= 1;
3817  }
3818  } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3819  RC = TRI->getRegClass(Mips::FCCRegClassID);
3820  else if (Prefix == "$w") { // Parse $w0-$w31.
3821  RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3822  } else { // Parse $0-$31.
3823  assert(Prefix == "$");
3824  RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3825  }
3826 
3827  assert(Reg < RC->getNumRegs());
3828  return std::make_pair(*(RC->begin() + Reg), RC);
3829 }
3830 
3831 /// Given a register class constraint, like 'r', if this corresponds directly
3832 /// to an LLVM register class, return a register of 0 and the register class
3833 /// pointer.
3834 std::pair<unsigned, const TargetRegisterClass *>
3835 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3836  StringRef Constraint,
3837  MVT VT) const {
3838  if (Constraint.size() == 1) {
3839  switch (Constraint[0]) {
3840  case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3841  case 'y': // Same as 'r'. Exists for compatibility.
3842  case 'r':
3843  if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3844  if (Subtarget.inMips16Mode())
3845  return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3846  return std::make_pair(0U, &Mips::GPR32RegClass);
3847  }
3848  if (VT == MVT::i64 && !Subtarget.isGP64bit())
3849  return std::make_pair(0U, &Mips::GPR32RegClass);
3850  if (VT == MVT::i64 && Subtarget.isGP64bit())
3851  return std::make_pair(0U, &Mips::GPR64RegClass);
3852  // This will generate an error message
3853  return std::make_pair(0U, nullptr);
3854  case 'f': // FPU or MSA register
3855  if (VT == MVT::v16i8)
3856  return std::make_pair(0U, &Mips::MSA128BRegClass);
3857  else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3858  return std::make_pair(0U, &Mips::MSA128HRegClass);
3859  else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3860  return std::make_pair(0U, &Mips::MSA128WRegClass);
3861  else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3862  return std::make_pair(0U, &Mips::MSA128DRegClass);
3863  else if (VT == MVT::f32)
3864  return std::make_pair(0U, &Mips::FGR32RegClass);
3865  else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3866  if (Subtarget.isFP64bit())
3867  return std::make_pair(0U, &Mips::FGR64RegClass);
3868  return std::make_pair(0U, &Mips::AFGR64RegClass);
3869  }
3870  break;
3871  case 'c': // register suitable for indirect jump
3872  if (VT == MVT::i32)
3873  return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3874  assert(VT == MVT::i64 && "Unexpected type.");
3875  return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3876  case 'l': // register suitable for indirect jump
3877  if (VT == MVT::i32)
3878  return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3879  return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3880  case 'x': // register suitable for indirect jump
3881  // Fixme: Not triggering the use of both hi and low
3882  // This will generate an error message
3883  return std::make_pair(0U, nullptr);
3884  }
3885  }
3886 
3887  std::pair<unsigned, const TargetRegisterClass *> R;
3888  R = parseRegForInlineAsmConstraint(Constraint, VT);
3889 
3890  if (R.second)
3891  return R;
3892 
3893  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3894 }
3895 
3896 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3897 /// vector. If it is invalid, don't add anything to Ops.
3898 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3899  std::string &Constraint,
3900  std::vector<SDValue>&Ops,
3901  SelectionDAG &DAG) const {
3902  SDLoc DL(Op);
3903  SDValue Result;
3904 
3905  // Only support length 1 constraints for now.
3906  if (Constraint.length() > 1) return;
3907 
3908  char ConstraintLetter = Constraint[0];
3909  switch (ConstraintLetter) {
3910  default: break; // This will fall through to the generic implementation
3911  case 'I': // Signed 16 bit constant
3912  // If this fails, the parent routine will give an error
3913  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3914  EVT Type = Op.getValueType();
3915  int64_t Val = C->getSExtValue();
3916  if (isInt<16>(Val)) {
3917  Result = DAG.getTargetConstant(Val, DL, Type);
3918  break;
3919  }
3920  }
3921  return;
3922  case 'J': // integer zero
3923  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3924  EVT Type = Op.getValueType();
3925  int64_t Val = C->getZExtValue();
3926  if (Val == 0) {
3927  Result = DAG.getTargetConstant(0, DL, Type);
3928  break;
3929  }
3930  }
3931  return;
3932  case 'K': // unsigned 16 bit immediate
3933  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3934  EVT Type = Op.getValueType();
3935  uint64_t Val = (uint64_t)C->getZExtValue();
3936  if (isUInt<16>(Val)) {
3937  Result = DAG.getTargetConstant(Val, DL, Type);
3938  break;
3939  }
3940  }
3941  return;
3942  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3943  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3944  EVT Type = Op.getValueType();
3945  int64_t Val = C->getSExtValue();
3946  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3947  Result = DAG.getTargetConstant(Val, DL, Type);
3948  break;
3949  }
3950  }
3951  return;
3952  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3953  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3954  EVT Type = Op.getValueType();
3955  int64_t Val = C->getSExtValue();
3956  if ((Val >= -65535) && (Val <= -1)) {
3957  Result = DAG.getTargetConstant(Val, DL, Type);
3958  break;
3959  }
3960  }
3961  return;
3962  case 'O': // signed 15 bit immediate
3963  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3964  EVT Type = Op.getValueType();
3965  int64_t Val = C->getSExtValue();
3966  if ((isInt<15>(Val))) {
3967  Result = DAG.getTargetConstant(Val, DL, Type);
3968  break;
3969  }
3970  }
3971  return;
3972  case 'P': // immediate in the range of 1 to 65535 (inclusive)
3973  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3974  EVT Type = Op.getValueType();
3975  int64_t Val = C->getSExtValue();
3976  if ((Val <= 65535) && (Val >= 1)) {
3977  Result = DAG.getTargetConstant(Val, DL, Type);
3978  break;
3979  }
3980  }
3981  return;
3982  }
3983 
3984  if (Result.getNode()) {
3985  Ops.push_back(Result);
3986  return;
3987  }
3988 
3989  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3990 }
3991 
3992 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3993  const AddrMode &AM, Type *Ty,
3994  unsigned AS, Instruction *I) const {
3995  // No global is ever allowed as a base.
3996  if (AM.BaseGV)
3997  return false;
3998 
3999  switch (AM.Scale) {
4000  case 0: // "r+i" or just "i", depending on HasBaseReg.
4001  break;
4002  case 1:
4003  if (!AM.HasBaseReg) // allow "r+i".
4004  break;
4005  return false; // disallow "r+r" or "r+r+i".
4006  default:
4007  return false;
4008  }
4009 
4010  return true;
4011 }
4012 
4013 bool
4014 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4015  // The Mips target isn't yet aware of offsets.
4016  return false;
4017 }
4018 
4019 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4020  unsigned SrcAlign,
4021  bool IsMemset, bool ZeroMemset,
4022  bool MemcpyStrSrc,
4023  MachineFunction &MF) const {
4024  if (Subtarget.hasMips64())
4025  return MVT::i64;
4026 
4027  return MVT::i32;
4028 }
4029 
4030 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4031  if (VT != MVT::f32 && VT != MVT::f64)
4032  return false;
4033  if (Imm.isNegZero())
4034  return false;
4035  return Imm.isZero();
4036 }
4037 
4038 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4039 
4040  // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4041  if (ABI.IsN64() && isPositionIndependent())
4043 
4045 }
4046 
4047 bool MipsTargetLowering::useSoftFloat() const {
4048  return Subtarget.useSoftFloat();
4049 }
4050 
4051 void MipsTargetLowering::copyByValRegs(
4052  SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4053  SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4054  SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4055  unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4056  MipsCCState &State) const {
4057  MachineFunction &MF = DAG.getMachineFunction();
4058  MachineFrameInfo &MFI = MF.getFrameInfo();
4059  unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4060  unsigned NumRegs = LastReg - FirstReg;
4061  unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4062  unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4063  int FrameObjOffset;
4064  ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4065 
4066  if (RegAreaSize)
4067  FrameObjOffset =
4069  (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4070  else
4071  FrameObjOffset = VA.getLocMemOffset();
4072 
4073  // Create frame object.
4074  EVT PtrTy = getPointerTy(DAG.getDataLayout());
4075  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4076  SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4077  InVals.push_back(FIN);
4078 
4079  if (!NumRegs)
4080  return;
4081 
4082  // Copy arg registers.
4083  MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4084  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4085 
4086  for (unsigned I = 0; I < NumRegs; ++I) {
4087  unsigned ArgReg = ByValArgRegs[FirstReg + I];
4088  unsigned VReg = addLiveIn(MF, ArgReg, RC);
4089  unsigned Offset = I * GPRSizeInBytes;
4090  SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4091  DAG.getConstant(Offset, DL, PtrTy));
4092  SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4093  StorePtr, MachinePointerInfo(FuncArg, Offset));
4094  OutChains.push_back(Store);
4095  }
4096 }
4097 
4098 // Copy byVal arg to registers and stack.
4099 void MipsTargetLowering::passByValArg(
4100  SDValue Chain, const SDLoc &DL,
4101  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4102  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4103  MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4104  unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4105  const CCValAssign &VA) const {
4106  unsigned ByValSizeInBytes = Flags.getByValSize();
4107  unsigned OffsetInBytes = 0; // From beginning of struct
4108  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4109  unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4110  EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4111  RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4112  unsigned NumRegs = LastReg - FirstReg;
4113 
4114  if (NumRegs) {
4116  bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4117  unsigned I = 0;
4118 
4119  // Copy words to registers.
4120  for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4121  SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4122  DAG.getConstant(OffsetInBytes, DL, PtrTy));
4123  SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4124  MachinePointerInfo(), Alignment);
4125  MemOpChains.push_back(LoadVal.getValue(1));
4126  unsigned ArgReg = ArgRegs[FirstReg + I];
4127  RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4128  }
4129 
4130  // Return if the struct has been fully copied.
4131  if (ByValSizeInBytes == OffsetInBytes)
4132  return;
4133 
4134  // Copy the remainder of the byval argument with sub-word loads and shifts.
4135  if (LeftoverBytes) {
4136  SDValue Val;
4137 
4138  for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4139  OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4140  unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4141 
4142  if (RemainingSizeInBytes < LoadSizeInBytes)
4143  continue;
4144 
4145  // Load subword.
4146  SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4147  DAG.getConstant(OffsetInBytes, DL,
4148  PtrTy));
4149  SDValue LoadVal = DAG.getExtLoad(
4150  ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4151  MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4152  MemOpChains.push_back(LoadVal.getValue(1));
4153 
4154  // Shift the loaded value.
4155  unsigned Shamt;
4156 
4157  if (isLittle)
4158  Shamt = TotalBytesLoaded * 8;
4159  else
4160  Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4161 
4162  SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4163  DAG.getConstant(Shamt, DL, MVT::i32));
4164 
4165  if (Val.getNode())
4166  Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4167  else
4168  Val = Shift;
4169 
4170  OffsetInBytes += LoadSizeInBytes;
4171  TotalBytesLoaded += LoadSizeInBytes;
4172  Alignment = std::min(Alignment, LoadSizeInBytes);
4173  }
4174 
4175  unsigned ArgReg = ArgRegs[FirstReg + I];
4176  RegsToPass.push_back(std::make_pair(ArgReg, Val));
4177  return;
4178  }
4179  }
4180 
4181  // Copy remainder of byval arg to it with memcpy.
4182  unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4183  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4184  DAG.getConstant(OffsetInBytes, DL, PtrTy));
4185  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4186  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4187  Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4188  DAG.getConstant(MemCpySize, DL, PtrTy),
4189  Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4190  /*isTailCall=*/false,
4192  MemOpChains.push_back(Chain);
4193 }
4194 
4195 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4196  SDValue Chain, const SDLoc &DL,
4197  SelectionDAG &DAG,
4198  CCState &State) const {
4200  unsigned Idx = State.getFirstUnallocated(ArgRegs);
4201  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4202  MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4203  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4204  MachineFunction &MF = DAG.getMachineFunction();
4205  MachineFrameInfo &MFI = MF.getFrameInfo();
4206  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4207 
4208  // Offset of the first variable argument from stack pointer.
4209  int VaArgOffset;
4210 
4211  if (ArgRegs.size() == Idx)
4212  VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4213  else {
4214  VaArgOffset =
4216  (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4217  }
4218 
4219  // Record the frame index of the first variable argument
4220  // which is a value necessary to VASTART.
4221  int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4222  MipsFI->setVarArgsFrameIndex(FI);
4223 
4224  // Copy the integer registers that have not been used for argument passing
4225  // to the argument register save area. For O32, the save area is allocated
4226  // in the caller's stack frame, while for N32/64, it is allocated in the
4227  // callee's stack frame.
4228  for (unsigned I = Idx; I < ArgRegs.size();
4229  ++I, VaArgOffset += RegSizeInBytes) {
4230  unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4231  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4232  FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4233  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4234  SDValue Store =
4235  DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4236  cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4237  (Value *)nullptr);
4238  OutChains.push_back(Store);
4239  }
4240 }
4241 
4242 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4243  unsigned Align) const {
4245 
4246  assert(Size && "Byval argument's size shouldn't be 0.");
4247 
4248  Align = std::min(Align, TFL->getStackAlignment());
4249 
4250  unsigned FirstReg = 0;
4251  unsigned NumRegs = 0;
4252 
4253  if (State->getCallingConv() != CallingConv::Fast) {
4254  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4255  ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4256  // FIXME: The O32 case actually describes no shadow registers.
4257  const MCPhysReg *ShadowRegs =
4258  ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4259 
4260  // We used to check the size as well but we can't do that anymore since
4261  // CCState::HandleByVal() rounds up the size after calling this function.
4262  assert(!(Align % RegSizeInBytes) &&
4263  "Byval argument's alignment should be a multiple of"
4264  "RegSizeInBytes.");
4265 
4266  FirstReg = State->getFirstUnallocated(IntArgRegs);
4267 
4268  // If Align > RegSizeInBytes, the first arg register must be even.
4269  // FIXME: This condition happens to do the right thing but it's not the
4270  // right way to test it. We want to check that the stack frame offset
4271  // of the register is aligned.
4272  if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4273  State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4274  ++FirstReg;
4275  }
4276 
4277  // Mark the registers allocated.
4278  Size = alignTo(Size, RegSizeInBytes);
4279  for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4280  Size -= RegSizeInBytes, ++I, ++NumRegs)
4281  State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4282  }
4283 
4284  State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4285 }
4286 
4287 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4288  MachineBasicBlock *BB,
4289  bool isFPCmp,
4290  unsigned Opc) const {
4292  "Subtarget already supports SELECT nodes with the use of"
4293  "conditional-move instructions.");
4294 
4295  const TargetInstrInfo *TII =
4297  DebugLoc DL = MI.getDebugLoc();
4298 
4299  // To "insert" a SELECT instruction, we actually have to insert the
4300  // diamond control-flow pattern. The incoming instruction knows the
4301  // destination vreg to set, the condition code register to branch on, the
4302  // true/false values to select between, and a branch opcode to use.
4303  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4305 
4306  // thisMBB:
4307  // ...
4308  // TrueVal = ...
4309  // setcc r1, r2, r3
4310  // bNE r1, r0, copy1MBB
4311  // fallthrough --> copy0MBB
4312  MachineBasicBlock *thisMBB = BB;
4313  MachineFunction *F = BB->getParent();
4314  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4315  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4316  F->insert(It, copy0MBB);
4317  F->insert(It, sinkMBB);
4318 
4319  // Transfer the remainder of BB and its successor edges to sinkMBB.
4320  sinkMBB->splice(sinkMBB->begin(), BB,
4321  std::next(MachineBasicBlock::iterator(MI)), BB->end());
4322  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4323 
4324  // Next, add the true and fallthrough blocks as its successors.
4325  BB->addSuccessor(copy0MBB);
4326  BB->addSuccessor(sinkMBB);
4327 
4328  if (isFPCmp) {
4329  // bc1[tf] cc, sinkMBB
4330  BuildMI(BB, DL, TII->get(Opc))
4331  .addReg(MI.getOperand(1).getReg())
4332  .addMBB(sinkMBB);
4333  } else {
4334  // bne rs, $0, sinkMBB
4335  BuildMI(BB, DL, TII->get(Opc))
4336  .addReg(MI.getOperand(1).getReg())
4337  .addReg(Mips::ZERO)
4338  .addMBB(sinkMBB);
4339  }
4340 
4341  // copy0MBB:
4342  // %FalseValue = ...
4343  // # fallthrough to sinkMBB
4344  BB = copy0MBB;
4345 
4346  // Update machine-CFG edges
4347  BB->addSuccessor(sinkMBB);
4348 
4349  // sinkMBB:
4350  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4351  // ...
4352  BB = sinkMBB;
4353 
4354  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4355  .addReg(MI.getOperand(2).getReg())
4356  .addMBB(thisMBB)
4357  .addReg(MI.getOperand(3).getReg())
4358  .addMBB(copy0MBB);
4359 
4360  MI.eraseFromParent(); // The pseudo instruction is gone now.
4361 
4362  return BB;
4363 }
4364 
4365 // FIXME? Maybe this could be a TableGen attribute on some registers and
4366 // this table could be generated automatically from RegInfo.
4367 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4368  SelectionDAG &DAG) const {
4369  // Named registers is expected to be fairly rare. For now, just support $28
4370  // since the linux kernel uses it.
4371  if (Subtarget.isGP64bit()) {
4372  unsigned Reg = StringSwitch<unsigned>(RegName)
4373  .Case("$28", Mips::GP_64)
4374  .Default(0);
4375  if (Reg)
4376  return Reg;
4377  } else {
4378  unsigned Reg = StringSwitch<unsigned>(RegName)
4379  .Case("$28", Mips::GP)
4380  .Default(0);
4381  if (Reg)
4382  return Reg;
4383  }
4384  report_fatal_error("Invalid register name global variable");
4385 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type.
bool isABICalls() const
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:544
bool inMips16HardFloat() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
EVT getValueType() const
Return the ValueType of the referenced return value.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...