LLVM  6.0.0svn
MipsRegisterInfo.cpp
Go to the documentation of this file.
1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/Support/Debug.h"
34 #include <cstdint>
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mips-reg-info"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
44 
45 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
46 
47 const TargetRegisterClass *
49  unsigned Kind) const {
50  MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
51  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
52 
53  switch (PtrClassKind) {
55  return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
57  return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass
58  : &Mips::GPRMM16RegClass;
60  return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
62  return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
63  }
64 
65  llvm_unreachable("Unknown pointer kind");
66 }
67 
68 unsigned
70  MachineFunction &MF) const {
71  switch (RC->getID()) {
72  default:
73  return 0;
74  case Mips::GPR32RegClassID:
75  case Mips::GPR64RegClassID:
76  case Mips::DSPRRegClassID: {
78  return 28 - TFI->hasFP(MF);
79  }
80  case Mips::FGR32RegClassID:
81  return 32;
82  case Mips::AFGR64RegClassID:
83  return 16;
84  case Mips::FGR64RegClassID:
85  return 32;
86  }
87 }
88 
89 //===----------------------------------------------------------------------===//
90 // Callee Saved Registers methods
91 //===----------------------------------------------------------------------===//
92 
93 /// Mips Callee Saved Registers
94 const MCPhysReg *
96  const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
97  const Function *F = MF->getFunction();
98  if (F->hasFnAttribute("interrupt")) {
99  if (Subtarget.hasMips64())
100  return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
101  : CSR_Interrupt_64_SaveList;
102  else
103  return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
104  : CSR_Interrupt_32_SaveList;
105  }
106 
107  if (Subtarget.isSingleFloat())
108  return CSR_SingleFloatOnly_SaveList;
109 
110  if (Subtarget.isABI_N64())
111  return CSR_N64_SaveList;
112 
113  if (Subtarget.isABI_N32())
114  return CSR_N32_SaveList;
115 
116  if (Subtarget.isFP64bit())
117  return CSR_O32_FP64_SaveList;
118 
119  if (Subtarget.isFPXX())
120  return CSR_O32_FPXX_SaveList;
121 
122  return CSR_O32_SaveList;
123 }
124 
125 const uint32_t *
127  CallingConv::ID) const {
128  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
129  if (Subtarget.isSingleFloat())
130  return CSR_SingleFloatOnly_RegMask;
131 
132  if (Subtarget.isABI_N64())
133  return CSR_N64_RegMask;
134 
135  if (Subtarget.isABI_N32())
136  return CSR_N32_RegMask;
137 
138  if (Subtarget.isFP64bit())
139  return CSR_O32_FP64_RegMask;
140 
141  if (Subtarget.isFPXX())
142  return CSR_O32_FPXX_RegMask;
143 
144  return CSR_O32_RegMask;
145 }
146 
148  return CSR_Mips16RetHelper_RegMask;
149 }
150 
153  static const MCPhysReg ReservedGPR32[] = {
154  Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
155  };
156 
157  static const MCPhysReg ReservedGPR64[] = {
158  Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
159  };
160 
161  BitVector Reserved(getNumRegs());
162  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
163 
164  using RegIter = TargetRegisterClass::const_iterator;
165 
166  for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
167  Reserved.set(ReservedGPR32[I]);
168 
169  // Reserve registers for the NaCl sandbox.
170  if (Subtarget.isTargetNaCl()) {
171  Reserved.set(Mips::T6); // Reserved for control flow mask.
172  Reserved.set(Mips::T7); // Reserved for memory access mask.
173  Reserved.set(Mips::T8); // Reserved for thread pointer.
174  }
175 
176  for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
177  Reserved.set(ReservedGPR64[I]);
178 
179  // For mno-abicalls, GP is a program invariant!
180  if (!Subtarget.isABICalls()) {
181  Reserved.set(Mips::GP);
182  Reserved.set(Mips::GP_64);
183  }
184 
185  if (Subtarget.isFP64bit()) {
186  // Reserve all registers in AFGR64.
187  for (RegIter Reg = Mips::AFGR64RegClass.begin(),
188  EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
189  Reserved.set(*Reg);
190  } else {
191  // Reserve all registers in FGR64.
192  for (RegIter Reg = Mips::FGR64RegClass.begin(),
193  EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
194  Reserved.set(*Reg);
195  }
196  // Reserve FP if this function should have a dedicated frame pointer register.
197  if (Subtarget.getFrameLowering()->hasFP(MF)) {
198  if (Subtarget.inMips16Mode())
199  Reserved.set(Mips::S0);
200  else {
201  Reserved.set(Mips::FP);
202  Reserved.set(Mips::FP_64);
203 
204  // Reserve the base register if we need to both realign the stack and
205  // allocate variable-sized objects at runtime. This should test the
206  // same conditions as MipsFrameLowering::hasBP().
207  if (needsStackRealignment(MF) &&
209  Reserved.set(Mips::S7);
210  Reserved.set(Mips::S7_64);
211  }
212  }
213  }
214 
215  // Reserve hardware registers.
216  Reserved.set(Mips::HWR29);
217 
218  // Reserve DSP control register.
219  Reserved.set(Mips::DSPPos);
220  Reserved.set(Mips::DSPSCount);
221  Reserved.set(Mips::DSPCarry);
222  Reserved.set(Mips::DSPEFI);
223  Reserved.set(Mips::DSPOutFlag);
224 
225  // Reserve MSA control registers.
226  Reserved.set(Mips::MSAIR);
227  Reserved.set(Mips::MSACSR);
228  Reserved.set(Mips::MSAAccess);
229  Reserved.set(Mips::MSASave);
230  Reserved.set(Mips::MSAModify);
231  Reserved.set(Mips::MSARequest);
232  Reserved.set(Mips::MSAMap);
233  Reserved.set(Mips::MSAUnmap);
234 
235  // Reserve RA if in mips16 mode.
236  if (Subtarget.inMips16Mode()) {
237  const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
238  Reserved.set(Mips::RA);
239  Reserved.set(Mips::RA_64);
240  Reserved.set(Mips::T0);
241  Reserved.set(Mips::T1);
242  if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
243  Reserved.set(Mips::S2);
244  }
245 
246  // Reserve GP if small section is used.
247  if (Subtarget.useSmallSection()) {
248  Reserved.set(Mips::GP);
249  Reserved.set(Mips::GP_64);
250  }
251 
252  if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
253  for (const auto &Reg : Mips::OddSPRegClass)
254  Reserved.set(Reg);
255  }
256 
257  return Reserved;
258 }
259 
260 bool
262  return true;
263 }
264 
265 bool
267  return true;
268 }
269 
270 // FrameIndex represent objects inside a abstract stack.
271 // We must replace FrameIndex with an stack/frame pointer
272 // direct reference.
275  unsigned FIOperandNum, RegScavenger *RS) const {
276  MachineInstr &MI = *II;
277  MachineFunction &MF = *MI.getParent()->getParent();
278 
279  DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
280  errs() << "<--------->\n" << MI);
281 
282  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
283  uint64_t stackSize = MF.getFrameInfo().getStackSize();
284  int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
285 
286  DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
287  << "spOffset : " << spOffset << "\n"
288  << "stackSize : " << stackSize << "\n"
289  << "alignment : "
290  << MF.getFrameInfo().getObjectAlignment(FrameIndex) << "\n");
291 
292  eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
293 }
294 
295 unsigned MipsRegisterInfo::
297  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
298  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
299  bool IsN64 =
300  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
301 
302  if (Subtarget.inMips16Mode())
303  return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
304  else
305  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
306  (IsN64 ? Mips::SP_64 : Mips::SP);
307 }
308 
310  // Avoid realigning functions that explicitly do not want to be realigned.
311  // Normally, we should report an error when a function should be dynamically
312  // realigned but also has the attribute no-realign-stack. Unfortunately,
313  // with this attribute, MachineFrameInfo clamps each new object's alignment
314  // to that of the stack's alignment as specified by the ABI. As a result,
315  // the information of whether we have objects with larger alignment
316  // requirement than the stack's alignment is already lost at this point.
318  return false;
319 
320  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
321  unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
322  unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
323 
324  // Support dynamic stack realignment only for targets with standard encoding.
325  if (!Subtarget.hasStandardEncoding())
326  return false;
327 
328  // We can't perform dynamic stack realignment if we can't reserve the
329  // frame pointer register.
330  if (!MF.getRegInfo().canReserveReg(FP))
331  return false;
332 
333  // We can realign the stack if we know the maximum call frame size and we
334  // don't have variable sized objects.
335  if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
336  return true;
337 
338  // We have to reserve the base pointer register in the presence of variable
339  // sized objects.
340  return MF.getRegInfo().canReserveReg(BP);
341 }
bool isABICalls() const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:243
BitVector & set()
Definition: BitVector.h:398
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:234
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool inMips16Mode() const
The subset of registers permitted in certain microMIPS instructions such as lw16. ...
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:75
unsigned getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
bool isABI_O32() const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
F(f)
bool isFPXX() const
bool hasMips64() const
SI optimize exec mask operations pre RA
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool hasStandardEncoding() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Reg
All possible values of the reg field in the ModR/M byte.
bool hasMips32r6() const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
unsigned getID() const
Return the register class ID number.
BitVector getReservedRegs(const MachineFunction &MF) const override
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool useSmallSection() const
bool isTargetNaCl() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const TargetFrameLowering * getFrameLowering() const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
friend const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:243
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Code Generation virtual methods...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The default register class for integer values.
bool isSingleFloat() const
bool hasMips64r6() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool isABI_N32() const
static unsigned getPICCallReg()
Get PIC indirect call register.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:729
Information about stack frame layout on the target.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static const uint32_t * getMips16RetHelperMask()
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual const TargetFrameLowering * getFrameLowering() const
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool useOddSPReg() const
bool isABI_N64() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned Kind
bool isGP32bit() const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const MCPhysReg * const_iterator
#define DEBUG(X)
Definition: Debug.h:118
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
IRTranslator LLVM IR MI
bool canRealignStack(const MachineFunction &MF) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool isFP64bit() const
#define T1