LLVM  10.0.0svn
MipsRegisterInfo.cpp
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1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MIPS implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Debug.h"
33 #include <cstdint>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-reg-info"
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "MipsGenRegisterInfo.inc"
41 
43 
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
45 
46 const TargetRegisterClass *
48  unsigned Kind) const {
49  MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
50  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
51 
52  switch (PtrClassKind) {
54  return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56  return &Mips::GPRMM16RegClass;
58  return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
60  return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
61  }
62 
63  llvm_unreachable("Unknown pointer kind");
64 }
65 
66 unsigned
68  MachineFunction &MF) const {
69  switch (RC->getID()) {
70  default:
71  return 0;
72  case Mips::GPR32RegClassID:
73  case Mips::GPR64RegClassID:
74  case Mips::DSPRRegClassID: {
76  return 28 - TFI->hasFP(MF);
77  }
78  case Mips::FGR32RegClassID:
79  return 32;
80  case Mips::AFGR64RegClassID:
81  return 16;
82  case Mips::FGR64RegClassID:
83  return 32;
84  }
85 }
86 
87 //===----------------------------------------------------------------------===//
88 // Callee Saved Registers methods
89 //===----------------------------------------------------------------------===//
90 
91 /// Mips Callee Saved Registers
92 const MCPhysReg *
94  const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
95  const Function &F = MF->getFunction();
96  if (F.hasFnAttribute("interrupt")) {
97  if (Subtarget.hasMips64())
98  return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
99  : CSR_Interrupt_64_SaveList;
100  else
101  return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
102  : CSR_Interrupt_32_SaveList;
103  }
104 
105  if (Subtarget.isSingleFloat())
106  return CSR_SingleFloatOnly_SaveList;
107 
108  if (Subtarget.isABI_N64())
109  return CSR_N64_SaveList;
110 
111  if (Subtarget.isABI_N32())
112  return CSR_N32_SaveList;
113 
114  if (Subtarget.isFP64bit())
115  return CSR_O32_FP64_SaveList;
116 
117  if (Subtarget.isFPXX())
118  return CSR_O32_FPXX_SaveList;
119 
120  return CSR_O32_SaveList;
121 }
122 
123 const uint32_t *
125  CallingConv::ID) const {
126  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
127  if (Subtarget.isSingleFloat())
128  return CSR_SingleFloatOnly_RegMask;
129 
130  if (Subtarget.isABI_N64())
131  return CSR_N64_RegMask;
132 
133  if (Subtarget.isABI_N32())
134  return CSR_N32_RegMask;
135 
136  if (Subtarget.isFP64bit())
137  return CSR_O32_FP64_RegMask;
138 
139  if (Subtarget.isFPXX())
140  return CSR_O32_FPXX_RegMask;
141 
142  return CSR_O32_RegMask;
143 }
144 
146  return CSR_Mips16RetHelper_RegMask;
147 }
148 
151  static const MCPhysReg ReservedGPR32[] = {
152  Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
153  };
154 
155  static const MCPhysReg ReservedGPR64[] = {
156  Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
157  };
158 
159  BitVector Reserved(getNumRegs());
160  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
161 
162  for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
163  Reserved.set(ReservedGPR32[I]);
164 
165  // Reserve registers for the NaCl sandbox.
166  if (Subtarget.isTargetNaCl()) {
167  Reserved.set(Mips::T6); // Reserved for control flow mask.
168  Reserved.set(Mips::T7); // Reserved for memory access mask.
169  Reserved.set(Mips::T8); // Reserved for thread pointer.
170  }
171 
172  for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
173  Reserved.set(ReservedGPR64[I]);
174 
175  // For mno-abicalls, GP is a program invariant!
176  if (!Subtarget.isABICalls()) {
177  Reserved.set(Mips::GP);
178  Reserved.set(Mips::GP_64);
179  }
180 
181  if (Subtarget.isFP64bit()) {
182  // Reserve all registers in AFGR64.
183  for (MCPhysReg Reg : Mips::AFGR64RegClass)
184  Reserved.set(Reg);
185  } else {
186  // Reserve all registers in FGR64.
187  for (MCPhysReg Reg : Mips::FGR64RegClass)
188  Reserved.set(Reg);
189  }
190  // Reserve FP if this function should have a dedicated frame pointer register.
191  if (Subtarget.getFrameLowering()->hasFP(MF)) {
192  if (Subtarget.inMips16Mode())
193  Reserved.set(Mips::S0);
194  else {
195  Reserved.set(Mips::FP);
196  Reserved.set(Mips::FP_64);
197 
198  // Reserve the base register if we need to both realign the stack and
199  // allocate variable-sized objects at runtime. This should test the
200  // same conditions as MipsFrameLowering::hasBP().
201  if (needsStackRealignment(MF) &&
203  Reserved.set(Mips::S7);
204  Reserved.set(Mips::S7_64);
205  }
206  }
207  }
208 
209  // Reserve hardware registers.
210  Reserved.set(Mips::HWR29);
211 
212  // Reserve DSP control register.
213  Reserved.set(Mips::DSPPos);
214  Reserved.set(Mips::DSPSCount);
215  Reserved.set(Mips::DSPCarry);
216  Reserved.set(Mips::DSPEFI);
217  Reserved.set(Mips::DSPOutFlag);
218 
219  // Reserve MSA control registers.
220  for (MCPhysReg Reg : Mips::MSACtrlRegClass)
221  Reserved.set(Reg);
222 
223  // Reserve RA if in mips16 mode.
224  if (Subtarget.inMips16Mode()) {
225  const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
226  Reserved.set(Mips::RA);
227  Reserved.set(Mips::RA_64);
228  Reserved.set(Mips::T0);
229  Reserved.set(Mips::T1);
230  if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
231  Reserved.set(Mips::S2);
232  }
233 
234  // Reserve GP if small section is used.
235  if (Subtarget.useSmallSection()) {
236  Reserved.set(Mips::GP);
237  Reserved.set(Mips::GP_64);
238  }
239 
240  return Reserved;
241 }
242 
243 bool
245  return true;
246 }
247 
248 bool
250  return true;
251 }
252 
253 // FrameIndex represent objects inside a abstract stack.
254 // We must replace FrameIndex with an stack/frame pointer
255 // direct reference.
258  unsigned FIOperandNum, RegScavenger *RS) const {
259  MachineInstr &MI = *II;
260  MachineFunction &MF = *MI.getParent()->getParent();
261 
262  LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
263  errs() << "<--------->\n"
264  << MI);
265 
266  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
267  uint64_t stackSize = MF.getFrameInfo().getStackSize();
268  int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
269 
270  LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
271  << "spOffset : " << spOffset << "\n"
272  << "stackSize : " << stackSize << "\n"
273  << "alignment : "
274  << MF.getFrameInfo().getObjectAlignment(FrameIndex)
275  << "\n");
276 
277  eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
278 }
279 
282  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
283  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
284  bool IsN64 =
285  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
286 
287  if (Subtarget.inMips16Mode())
288  return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
289  else
290  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
291  (IsN64 ? Mips::SP_64 : Mips::SP);
292 }
293 
295  // Avoid realigning functions that explicitly do not want to be realigned.
296  // Normally, we should report an error when a function should be dynamically
297  // realigned but also has the attribute no-realign-stack. Unfortunately,
298  // with this attribute, MachineFrameInfo clamps each new object's alignment
299  // to that of the stack's alignment as specified by the ABI. As a result,
300  // the information of whether we have objects with larger alignment
301  // requirement than the stack's alignment is already lost at this point.
303  return false;
304 
305  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
306  unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
307  unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
308 
309  // Support dynamic stack realignment for all targets except Mips16.
310  if (Subtarget.inMips16Mode())
311  return false;
312 
313  // We can't perform dynamic stack realignment if we can't reserve the
314  // frame pointer register.
315  if (!MF.getRegInfo().canReserveReg(FP))
316  return false;
317 
318  // We can realign the stack if we know the maximum call frame size and we
319  // don't have variable sized objects.
320  if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
321  return true;
322 
323  // We have to reserve the base pointer register in the presence of variable
324  // sized objects.
325  return MF.getRegInfo().canReserveReg(BP);
326 }
bool isABICalls() const
BitVector & set()
Definition: BitVector.h:397
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool inMips16Mode() const
The subset of registers permitted in certain microMIPS instructions such as lw16. ...
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:74
unsigned Reg
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
F(f)
bool isFPXX() const
bool hasMips64() const
SI optimize exec mask operations pre RA
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool hasMips32r6() const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
unsigned getID() const
Return the register class ID number.
BitVector getReservedRegs(const MachineFunction &MF) const override
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool useSmallSection() const
bool isTargetNaCl() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const TargetFrameLowering * getFrameLowering() const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Code Generation virtual methods...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The default register class for integer values.
bool isSingleFloat() const
bool hasMips64r6() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool isABI_N32() const
static unsigned getPICCallReg()
Get PIC indirect call register.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1035
Information about stack frame layout on the target.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static const uint32_t * getMips16RetHelperMask()
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual const TargetFrameLowering * getFrameLowering() const
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isABI_N64() const
bool isGP32bit() const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
IRTranslator LLVM IR MI
bool canRealignStack(const MachineFunction &MF) const override
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool isFP64bit() const
#define T1
Wrapper class representing virtual and physical registers.
Definition: Register.h:19