LLVM  8.0.0svn
Public Types | Public Member Functions | Protected Member Functions | List of all members
llvm::TargetSubtargetInfo Class Reference

TargetSubtargetInfo - Generic base class for all target subtargets. More...

#include "llvm/CodeGen/TargetSubtargetInfo.h"

Inheritance diagram for llvm::TargetSubtargetInfo:
Inheritance graph
[legend]
Collaboration diagram for llvm::TargetSubtargetInfo:
Collaboration graph
[legend]

Public Types

using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }
 
using RegClassVector = SmallVectorImpl< const TargetRegisterClass * >
 

Public Member Functions

 TargetSubtargetInfo ()=delete
 
 TargetSubtargetInfo (const TargetSubtargetInfo &)=delete
 
TargetSubtargetInfooperator= (const TargetSubtargetInfo &)=delete
 
 ~TargetSubtargetInfo () override
 
virtual bool isXRaySupported () const
 
virtual const TargetInstrInfogetInstrInfo () const
 
virtual const TargetFrameLoweringgetFrameLowering () const
 
virtual const TargetLoweringgetTargetLowering () const
 
virtual const SelectionDAGTargetInfogetSelectionDAGInfo () const
 
virtual const CallLoweringgetCallLowering () const
 
virtual const InstructionSelectorgetInstructionSelector () const
 
virtual unsigned getHwMode () const
 
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler (CodeGenOpt::Level) const
 Target can subclass this hook to select a different DAG scheduler. More...
 
virtual const LegalizerInfogetLegalizerInfo () const
 
virtual const TargetRegisterInfogetRegisterInfo () const
 getRegisterInfo - If register information is available, return it. More...
 
virtual const RegisterBankInfogetRegBankInfo () const
 If the information for the register banks is available, return it. More...
 
virtual const InstrItineraryDatagetInstrItineraryData () const
 getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget. More...
 
virtual unsigned resolveSchedClass (unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
 Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. More...
 
virtual bool isZeroIdiom (const MachineInstr *MI, APInt &Mask) const
 Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget. More...
 
virtual bool isDependencyBreaking (const MachineInstr *MI, APInt &Mask) const
 Returns true if MI is a dependency breaking instruction for the subtarget. More...
 
virtual bool isOptimizableRegisterMove (const MachineInstr *MI) const
 Returns true if MI is a candidate for move elimination. More...
 
virtual bool enableMachineScheduler () const
 True if the subtarget should run MachineScheduler after aggressive coalescing. More...
 
virtual bool supportPrintSchedInfo () const
 Support printing of [latency:throughput] comment in output .S file. More...
 
virtual bool enableMachineSchedDefaultSched () const
 True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler. More...
 
virtual bool enableJoinGlobalCopies () const
 True if the subtarget should enable joining global copies. More...
 
virtual bool enablePostRAScheduler () const
 True if the subtarget should run a scheduler after register allocation. More...
 
virtual bool enableAtomicExpand () const
 True if the subtarget should run the atomic expansion pass. More...
 
virtual bool enableIndirectBrExpand () const
 True if the subtarget should run the indirectbr expansion pass. More...
 
virtual void overrideSchedPolicy (MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
 Override generic scheduling policy within a region. More...
 
virtual void adjustSchedDependency (SUnit *def, SUnit *use, SDep &dep) const
 
virtual AntiDepBreakMode getAntiDepBreakMode () const
 
virtual void getCriticalPathRCs (RegClassVector &CriticalPathRCs) const
 
virtual void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
 
virtual void getSMSMutations (std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
 
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler () const
 
virtual bool enableRALocalReassignment (CodeGenOpt::Level OptLevel) const
 True if the subtarget should run the local reassignment heuristic of the register allocator. More...
 
virtual bool enableAdvancedRASplitCost () const
 True if the subtarget should consider the cost of local intervals created by a split candidate when choosing the best split candidate. More...
 
virtual bool useAA () const
 Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.). More...
 
virtual bool enableEarlyIfConversion () const
 Enable the use of the early if conversion pass. More...
 
virtual std::unique_ptr< PBQPRAConstraintgetCustomPBQPConstraints () const
 Return PBQPConstraint(s) for the target. More...
 
virtual bool enableSubRegLiveness () const
 Enable tracking of subregister liveness in register allocator. More...
 
std::string getSchedInfoStr (const MachineInstr &MI) const
 Returns string representation of scheduler comment. More...
 
std::string getSchedInfoStr (MCInst const &MCI) const override
 Returns string representation of scheduler comment. More...
 
virtual void mirFileLoaded (MachineFunction &MF) const
 This is called after a .mir file was loaded. More...
 
- Public Member Functions inherited from llvm::MCSubtargetInfo
 MCSubtargetInfo (const MCSubtargetInfo &)=default
 
 MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
 
 MCSubtargetInfo ()=delete
 
MCSubtargetInfooperator= (const MCSubtargetInfo &)=delete
 
MCSubtargetInfooperator= (MCSubtargetInfo &&)=delete
 
virtual ~MCSubtargetInfo ()=default
 
const TriplegetTargetTriple () const
 
StringRef getCPU () const
 
const FeatureBitsetgetFeatureBits () const
 
void setFeatureBits (const FeatureBitset &FeatureBits_)
 
bool hasFeature (unsigned Feature) const
 
void setDefaultFeatures (StringRef CPU, StringRef FS)
 Set the features to the default for the given CPU with an appended feature string. More...
 
FeatureBitset ToggleFeature (uint64_t FB)
 Toggle a feature and return the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (const FeatureBitset &FB)
 Toggle a feature and return the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (StringRef FS)
 Toggle a set of features and return the re-computed feature bits. More...
 
FeatureBitset ApplyFeatureFlag (StringRef FS)
 Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. More...
 
bool checkFeatures (StringRef FS) const
 Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features. More...
 
const MCSchedModelgetSchedModelForCPU (StringRef CPU) const
 Get the machine model of a CPU. More...
 
const MCSchedModelgetSchedModel () const
 Get the machine model for this subtarget's CPU. More...
 
const MCWriteProcResEntrygetWriteProcResBegin (const MCSchedClassDesc *SC) const
 Return an iterator at the first process resource consumed by the given scheduling class. More...
 
const MCWriteProcResEntrygetWriteProcResEnd (const MCSchedClassDesc *SC) const
 
const MCWriteLatencyEntrygetWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
 
int getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
 
InstrItineraryData getInstrItineraryForCPU (StringRef CPU) const
 Get scheduling itinerary of a CPU. More...
 
void initInstrItins (InstrItineraryData &InstrItins) const
 Initialize an InstrItineraryData instance. More...
 
virtual unsigned resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, unsigned CPUID) const
 Resolve a variant scheduling class for the given MCInst and CPU. More...
 
bool isCPUStringValid (StringRef CPU) const
 Check whether the CPU string is valid. More...
 

Protected Member Functions

 TargetSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
 
- Protected Member Functions inherited from llvm::MCSubtargetInfo
void InitMCProcessorInfo (StringRef CPU, StringRef FS)
 Initialize the scheduling model and feature bits. More...
 

Detailed Description

TargetSubtargetInfo - Generic base class for all target subtargets.

All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.

Definition at line 62 of file TargetSubtargetInfo.h.

Member Typedef Documentation

◆ AntiDepBreakMode

using llvm::TargetSubtargetInfo::AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }

Definition at line 76 of file TargetSubtargetInfo.h.

◆ RegClassVector

Definition at line 77 of file TargetSubtargetInfo.h.

Constructor & Destructor Documentation

◆ TargetSubtargetInfo() [1/3]

TargetSubtargetInfo::TargetSubtargetInfo ( const Triple TT,
StringRef  CPU,
StringRef  FS,
ArrayRef< SubtargetFeatureKV PF,
ArrayRef< SubtargetFeatureKV PD,
const SubtargetInfoKV ProcSched,
const MCWriteProcResEntry WPR,
const MCWriteLatencyEntry WL,
const MCReadAdvanceEntry RA,
const InstrStage IS,
const unsigned OC,
const unsigned FP 
)
protected

Definition at line 26 of file TargetSubtargetInfo.cpp.

References ~TargetSubtargetInfo().

◆ TargetSubtargetInfo() [2/3]

llvm::TargetSubtargetInfo::TargetSubtargetInfo ( )
delete

◆ TargetSubtargetInfo() [3/3]

llvm::TargetSubtargetInfo::TargetSubtargetInfo ( const TargetSubtargetInfo )
delete

◆ ~TargetSubtargetInfo()

TargetSubtargetInfo::~TargetSubtargetInfo ( )
overridedefault

Referenced by TargetSubtargetInfo().

Member Function Documentation

◆ adjustSchedDependency()

virtual void llvm::TargetSubtargetInfo::adjustSchedDependency ( SUnit def,
SUnit use,
SDep dep 
) const
inlinevirtual

◆ enableAdvancedRASplitCost()

bool TargetSubtargetInfo::enableAdvancedRASplitCost ( ) const
virtual

True if the subtarget should consider the cost of local intervals created by a split candidate when choosing the best split candidate.

This heuristic may be compile time intensive.

Definition at line 58 of file TargetSubtargetInfo.cpp.

Referenced by getOptLevelToEnablePostRAScheduler().

◆ enableAtomicExpand()

bool TargetSubtargetInfo::enableAtomicExpand ( ) const
virtual

True if the subtarget should run the atomic expansion pass.

Definition at line 37 of file TargetSubtargetInfo.cpp.

Referenced by enableMachineSchedDefaultSched().

◆ enableEarlyIfConversion()

virtual bool llvm::TargetSubtargetInfo::enableEarlyIfConversion ( ) const
inlinevirtual

Enable the use of the early if conversion pass.

Definition at line 275 of file TargetSubtargetInfo.h.

Referenced by adjCycles().

◆ enableIndirectBrExpand()

bool TargetSubtargetInfo::enableIndirectBrExpand ( ) const
virtual

True if the subtarget should run the indirectbr expansion pass.

Definition at line 41 of file TargetSubtargetInfo.cpp.

Referenced by enableMachineSchedDefaultSched().

◆ enableJoinGlobalCopies()

bool TargetSubtargetInfo::enableJoinGlobalCopies ( ) const
virtual

True if the subtarget should enable joining global copies.

By default this is enabled if the machine scheduler is enabled, but can be overridden.

Definition at line 49 of file TargetSubtargetInfo.cpp.

References enableMachineScheduler().

Referenced by enableMachineSchedDefaultSched(), and isTerminalReg().

◆ enableMachineSchedDefaultSched()

virtual bool llvm::TargetSubtargetInfo::enableMachineSchedDefaultSched ( ) const
inlinevirtual

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.

Definition at line 198 of file TargetSubtargetInfo.h.

References enableAtomicExpand(), enableIndirectBrExpand(), enableJoinGlobalCopies(), and enablePostRAScheduler().

Referenced by llvm::createDefaultScheduler().

◆ enableMachineScheduler()

bool TargetSubtargetInfo::enableMachineScheduler ( ) const
virtual

True if the subtarget should run MachineScheduler after aggressive coalescing.

This currently replaces the SelectionDAG scheduler with the "source" order scheduler (though see below for an option to turn this off and use the TargetLowering preference). It does not yet disable the postRA scheduler.

Definition at line 45 of file TargetSubtargetInfo.cpp.

Referenced by llvm::createDefaultScheduler(), enableJoinGlobalCopies(), and isOptimizableRegisterMove().

◆ enablePostRAScheduler()

bool TargetSubtargetInfo::enablePostRAScheduler ( ) const
virtual

True if the subtarget should run a scheduler after register allocation.

By default this queries the PostRAScheduling bit in the scheduling model which is the preferred way to influence this.

Definition at line 62 of file TargetSubtargetInfo.cpp.

References llvm::MCSubtargetInfo::getSchedModel(), and llvm::MCSchedModel::PostRAScheduler.

Referenced by enableMachineSchedDefaultSched(), and INITIALIZE_PASS().

◆ enableRALocalReassignment()

bool TargetSubtargetInfo::enableRALocalReassignment ( CodeGenOpt::Level  OptLevel) const
virtual

True if the subtarget should run the local reassignment heuristic of the register allocator.

This heuristic may be compile time intensive, OptLevel provides a finer grain to tune the register allocator.

Definition at line 53 of file TargetSubtargetInfo.cpp.

Referenced by getOptLevelToEnablePostRAScheduler().

◆ enableSubRegLiveness()

virtual bool llvm::TargetSubtargetInfo::enableSubRegLiveness ( ) const
inlinevirtual

Enable tracking of subregister liveness in register allocator.

Please use MachineRegisterInfo::subRegLivenessEnabled() instead where possible.

Definition at line 287 of file TargetSubtargetInfo.h.

References getSchedInfoStr(), MI, and mirFileLoaded().

◆ getAntiDepBreakMode()

virtual AntiDepBreakMode llvm::TargetSubtargetInfo::getAntiDepBreakMode ( ) const
inlinevirtual

Definition at line 232 of file TargetSubtargetInfo.h.

Referenced by INITIALIZE_PASS().

◆ getCallLowering()

virtual const CallLowering* llvm::TargetSubtargetInfo::getCallLowering ( ) const
inlinevirtual

Definition at line 104 of file TargetSubtargetInfo.h.

Referenced by llvm::createLibcall().

◆ getCriticalPathRCs()

virtual void llvm::TargetSubtargetInfo::getCriticalPathRCs ( RegClassVector CriticalPathRCs) const
inlinevirtual

Definition at line 237 of file TargetSubtargetInfo.h.

References llvm::SmallVectorImpl< T >::clear().

Referenced by INITIALIZE_PASS().

◆ getCustomPBQPConstraints()

virtual std::unique_ptr<PBQPRAConstraint> llvm::TargetSubtargetInfo::getCustomPBQPConstraints ( ) const
inlinevirtual

Return PBQPConstraint(s) for the target.

Override to provide custom PBQP constraints.

Definition at line 280 of file TargetSubtargetInfo.h.

Referenced by normalizePBQPSpillWeight().

◆ getDAGScheduler()

virtual RegisterScheduler::FunctionPassCtor llvm::TargetSubtargetInfo::getDAGScheduler ( CodeGenOpt::Level  ) const
inlinevirtual

Target can subclass this hook to select a different DAG scheduler.

Definition at line 118 of file TargetSubtargetInfo.h.

Referenced by llvm::createDefaultScheduler().

◆ getFrameLowering()

virtual const TargetFrameLowering* llvm::TargetSubtargetInfo::getFrameLowering ( ) const
inlinevirtual

◆ getHwMode()

virtual unsigned llvm::TargetSubtargetInfo::getHwMode ( ) const
inlinevirtual

Definition at line 114 of file TargetSubtargetInfo.h.

◆ getInstrInfo()

virtual const TargetInstrInfo* llvm::TargetSubtargetInfo::getInstrInfo ( ) const
inlinevirtual

Definition at line 96 of file TargetSubtargetInfo.h.

Referenced by addExclusiveRegPair(), llvm::MachineBasicBlock::addLiveIn(), adjCycles(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), allPhiOperandsUndefined(), AssignProtectedObjSet(), llvm::MachineBasicBlock::canSplitCriticalEdge(), llvm::computeBlockSize(), llvm::MachineFrameInfo::computeMaxCallFrameSize(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), createPHIsForCMOVsInSinkBB(), createPHIsForSelects(), llvm::createSourceListDAGScheduler(), llvm::createSystemZLDCleanupPass(), llvm::createXCoreFrameToArgsOffsetEliminationPass(), llvm::ARMFrameLowering::determineCalleeSaves(), doesNotGeneratecode(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitComments(), llvm::SparcFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::SystemZFrameLowering::emitEpilogue(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), EmitNop(), llvm::NVPTXFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), llvm::SystemZFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitThumb2LoadConstPool(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::LegalizerHelper::fewerElementsVector(), llvm::finalizeBundle(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::getEHScopeMembership(), llvm::MachineBasicBlock::getFallThrough(), getFPReg(), llvm::ARMHazardRecognizer::getHazardType(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MSP430InstrInfo::getInstSizeInBytes(), getLayoutSuccessorProbThreshold(), getLoadStoreOffsetAlign(), getNewValueJumpOpcode(), llvm::SDNode::getOperationName(), getSchedInfoStr(), getSchedRegions(), getTargetIndexName(), llvm::BPFTargetLowering::getTargetNodeName(), getUnderlyingArgReg(), hasRegisterDependency(), llvm::TargetSchedModel::init(), llvm::ConvergingVLIWScheduler::initialize(), llvm::PostGenericScheduler::initialize(), INITIALIZE_PASS(), llvm::TailDuplicator::initMF(), initSlots2Values(), insertCopy(), insertCSRRestores(), insertCSRSaves(), llvm::Mips16RegisterInfo::intRegClass(), isCompareZero(), isFpMulInstruction(), isHardwareLoop(), isNopCopy(), isTerminalReg(), IsUnconditionalJump(), isVirtualRegisterOperand(), LoopIsOuterMostWithPredecessor(), llvm::X86CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), llvm::MachineInstr::mayAlias(), false::IntervalSorter::operator()(), parseCond(), llvm::MachineBasicBlock::print(), llvm::MachineInstr::print(), printMemOperand(), llvm::MachineOperand::printTargetFlags(), llvm::AArch64FrameLowering::processFunctionBeforeFrameFinalized(), propagateSwiftErrorVRegs(), llvm::TargetInstrInfo::reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), removePhis(), replaceFI(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::UnreachableBlockElimPass::run(), llvm::BreakFalseDeps::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::ExecutionDomainFix::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::MachineIRBuilderBase::setMF(), llvm::RegScavenger::setRegUsed(), llvm::DwarfDebug::shareAcrossDWOCUs(), llvm::MachineBasicBlock::SkipPHIsAndLabels(), llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug(), llvm::SparcFrameLowering::SparcFrameLowering(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), subRangeLiveAt(), trySequenceOfOnes(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), llvm::MachineFunction::verify(), llvm::VLIWResourceModel::VLIWResourceModel(), and llvm::LegalizerHelper::widenScalar().

◆ getInstrItineraryData()

virtual const InstrItineraryData* llvm::TargetSubtargetInfo::getInstrItineraryData ( ) const
inlinevirtual

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.

Definition at line 134 of file TargetSubtargetInfo.h.

Referenced by llvm::R600InstrInfo::CreateTargetScheduleState(), llvm::HexagonInstrInfo::CreateTargetScheduleState(), and getUnderlyingObjects().

◆ getInstructionSelector()

virtual const InstructionSelector* llvm::TargetSubtargetInfo::getInstructionSelector ( ) const
inlinevirtual

◆ getLegalizerInfo()

virtual const LegalizerInfo* llvm::TargetSubtargetInfo::getLegalizerInfo ( ) const
inlinevirtual

Definition at line 122 of file TargetSubtargetInfo.h.

Referenced by llvm::machineFunctionIsIllegal().

◆ getOptLevelToEnablePostRAScheduler()

virtual CodeGenOpt::Level llvm::TargetSubtargetInfo::getOptLevelToEnablePostRAScheduler ( ) const
inlinevirtual

◆ getPostRAMutations()

virtual void llvm::TargetSubtargetInfo::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation >> &  Mutations) const
inlinevirtual

Definition at line 243 of file TargetSubtargetInfo.h.

◆ getRegBankInfo()

virtual const RegisterBankInfo* llvm::TargetSubtargetInfo::getRegBankInfo ( ) const
inlinevirtual

If the information for the register banks is available, return it.

Otherwise return nullptr.

Definition at line 130 of file TargetSubtargetInfo.h.

Referenced by INITIALIZE_PASS_END(), llvm::MIRParserImpl::initializeJumpTableInfo(), llvm::X86CallLowering::lowerCall(), and llvm::AArch64CallLowering::lowerCall().

◆ getRegisterInfo()

virtual const TargetRegisterInfo* llvm::TargetSubtargetInfo::getRegisterInfo ( ) const
inlinevirtual

getRegisterInfo - If register information is available, return it.

If not, return null.

Definition at line 126 of file TargetSubtargetInfo.h.

Referenced by llvm::DwarfCompileUnit::addAddress(), llvm::DwarfCompileUnit::addComplexAddress(), addLiveInRegs(), addSavedGPR(), adjCycles(), AdjustStackOffset(), llvm::MachineFunction::allocateRegMask(), llvm::A57ChainingConstraint::apply(), llvm::HexagonSubtarget::CallMutation::apply(), assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), llvm::DebugHandlerBase::beginFunction(), llvm::CodeViewDebug::beginFunctionImpl(), llvm::AArch64InstrInfo::buildOutlinedFrame(), llvm::LiveRangeEdit::calculateRegClassAndHint(), llvm::HexagonPacketizerList::canPromoteToDotCur(), checkNumAlignedDPRCS2Regs(), computeLiveOuts(), llvm::TargetSchedModel::computeOutputLatency(), llvm::DwarfCompileUnit::constructLabelDIE(), llvm::MIRPrinter::convert(), llvm::MIRPrinter::convertStackObjects(), llvm::SystemZInstrInfo::copyPhysReg(), llvm::createBURRListDAGScheduler(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::createNVPTXPrologEpilogPass(), llvm::createRegUsageInfoCollector(), llvm::createSourceListDAGScheduler(), createVirtualRegs(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitDebugLocValue(), emitDebugValueComment(), llvm::ARMFrameLowering::emitEpilogue(), llvm::MipsAsmPrinter::emitFrameDirective(), EmitGCCInlineAsmStr(), llvm::AsmPrinter::emitImplicitDef(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitKill(), llvm::XCoreFrameLowering::emitPrologue(), llvm::MachineFrameInfo::estimateStackSize(), llvm::finalizeBundle(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getDwarfRegNum(), llvm::RISCVFrameLowering::getFrameIndexReference(), llvm::TargetFrameLowering::getFrameIndexReference(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), getLayoutSuccessorProbThreshold(), getLoadStoreOffsetAlign(), getMemcpyLoadsAndStores(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), getNewValueJumpOpcode(), getOpenCLAlignment(), llvm::MachineFrameInfo::getPristineRegs(), llvm::SystemZRegisterInfo::getRegAllocationHints(), GetRegistersForValue(), getRegTy(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), giveUpWithRemarks(), HandleVRSaveUpdate(), llvm::SparcFrameLowering::hasFP(), llvm::RISCVFrameLowering::hasFP(), llvm::ARMFrameLowering::hasFP(), llvm::ARCFrameLowering::hasFP(), llvm::AArch64FrameLowering::hasFP(), hasRegisterDependency(), hasUseAfterLoop(), INITIALIZE_PASS(), INITIALIZE_PASS_END(), llvm::MIRParserImpl::initializeJumpTableInfo(), llvm::TailDuplicator::initMF(), insertCSRRestores(), insertCSRSaves(), isACalleeSavedRegister(), isFpMulInstruction(), isImplicitOperandIn(), isNonFoldablePartialRegisterLoad(), isNopCopy(), llvm::TargetInstrInfo::isSchedulingBoundary(), isTerminalReg(), isVirtualRegisterOperand(), llvm::LiveRegMatrix::LiveRegMatrix(), llvm::X86InstrInfo::loadRegFromAddr(), lookupCandidateBaseReg(), LoopIsOuterMostWithPredecessor(), llvm::MipsCallLowering::lowerCall(), llvm::MachineFunction::MachineFunction(), MakeM0Inst(), needsReferenceType(), numVectorEltsOrZero(), patchMatchingInput(), llvm::PhysicalRegisterUsageInfo::print(), llvm::MIRPrinter::print(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::MachineFunction::print(), llvm::MachineBasicBlock::print(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::TargetInstrInfo::reassociateOps(), removePhis(), ReplaceFrameIndex(), llvm::AArch64FrameLowering::resolveFrameIndexReference(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::InstructionSelect::runOnMachineFunction(), llvm::BreakFalseDeps::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::ReachingDefAnalysis::runOnMachineFunction(), llvm::LiveStacks::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::ExecutionDomainFix::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::RegScavenger::setRegUsed(), llvm::X86MachineFunctionInfo::setRestoreBasePointer(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), srcMgrDiagHandler(), llvm::X86InstrInfo::storeRegToAddr(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateLiveIn(), UpdateOperandRegClass(), UpdatePredRedefs(), llvm::DwarfCompileUnit::updateSubprogramScopeDIE(), llvm::MachineFunction::verify(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ getSchedInfoStr() [1/2]

std::string TargetSubtargetInfo::getSchedInfoStr ( const MachineInstr MI) const

◆ getSchedInfoStr() [2/2]

std::string TargetSubtargetInfo::getSchedInfoStr ( MCInst const MCI) const
overridevirtual

◆ getSelectionDAGInfo()

virtual const SelectionDAGTargetInfo* llvm::TargetSubtargetInfo::getSelectionDAGInfo ( ) const
inlinevirtual

Definition at line 101 of file TargetSubtargetInfo.h.

Referenced by llvm::SelectionDAG::init(), and isContractable().

◆ getSMSMutations()

virtual void llvm::TargetSubtargetInfo::getSMSMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation >> &  Mutations) const
inlinevirtual

Definition at line 249 of file TargetSubtargetInfo.h.

◆ getTargetLowering()

virtual const TargetLowering* llvm::TargetSubtargetInfo::getTargetLowering ( ) const
inlinevirtual

◆ isDependencyBreaking()

virtual bool llvm::TargetSubtargetInfo::isDependencyBreaking ( const MachineInstr MI,
APInt Mask 
) const
inlinevirtual

Returns true if MI is a dependency breaking instruction for the subtarget.

Similar in behavior to isZeroIdiom. However, it knows how to identify all dependency breaking instructions (i.e. not just zero-idioms).

As for isZeroIdiom, this method returns a mask of "broken" dependencies. (See method isZeroIdiom for a detailed description of Mask).

Definition at line 168 of file TargetSubtargetInfo.h.

References isZeroIdiom().

◆ isOptimizableRegisterMove()

virtual bool llvm::TargetSubtargetInfo::isOptimizableRegisterMove ( const MachineInstr MI) const
inlinevirtual

Returns true if MI is a candidate for move elimination.

A candidate for move elimination may be optimized out at register renaming stage. Subtargets can specify the set of optimizable moves by instantiating tablegen class IsOptimizableRegisterMove (see llvm/Target/TargetInstrPredicate.td).

SubtargetEmitter is responsible for processing all the definitions of class IsOptimizableRegisterMove, and auto-generate an override for this method.

Definition at line 181 of file TargetSubtargetInfo.h.

References enableMachineScheduler().

◆ isXRaySupported()

virtual bool llvm::TargetSubtargetInfo::isXRaySupported ( ) const
inlinevirtual

Definition at line 84 of file TargetSubtargetInfo.h.

◆ isZeroIdiom()

virtual bool llvm::TargetSubtargetInfo::isZeroIdiom ( const MachineInstr MI,
APInt Mask 
) const
inlinevirtual

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.

This function also sets bits in Mask related to input operands that are not in a data dependency relationship. There is one bit for each machine operand; implicit operands follow explicit operands in the bit representation used for Mask. An empty (i.e. a mask with all bits cleared) means: data dependencies are "broken" for all the explicit input machine operands of MI.

Definition at line 157 of file TargetSubtargetInfo.h.

Referenced by isDependencyBreaking().

◆ mirFileLoaded()

void TargetSubtargetInfo::mirFileLoaded ( MachineFunction MF) const
virtual

This is called after a .mir file was loaded.

Definition at line 115 of file TargetSubtargetInfo.cpp.

Referenced by enableSubRegLiveness(), and llvm::MIRParserImpl::initializeMachineFunction().

◆ operator=()

TargetSubtargetInfo& llvm::TargetSubtargetInfo::operator= ( const TargetSubtargetInfo )
delete

◆ overrideSchedPolicy()

virtual void llvm::TargetSubtargetInfo::overrideSchedPolicy ( MachineSchedPolicy Policy,
unsigned  NumRegionInstrs 
) const
inlinevirtual

Override generic scheduling policy within a region.

This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic scheduling policy.

Definition at line 223 of file TargetSubtargetInfo.h.

◆ resolveSchedClass()

virtual unsigned llvm::TargetSubtargetInfo::resolveSchedClass ( unsigned  SchedClass,
const MachineInstr MI,
const TargetSchedModel SchedModel 
) const
inlinevirtual

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property.

This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.

Definition at line 142 of file TargetSubtargetInfo.h.

Referenced by llvm::TargetSchedModel::resolveSchedClass().

◆ supportPrintSchedInfo()

virtual bool llvm::TargetSubtargetInfo::supportPrintSchedInfo ( ) const
inlinevirtual

Support printing of [latency:throughput] comment in output .S file.

Definition at line 194 of file TargetSubtargetInfo.h.

Referenced by llvm::AsmPrinter::SetupMachineFunction().

◆ useAA()

bool TargetSubtargetInfo::useAA ( ) const
virtual

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 66 of file TargetSubtargetInfo.cpp.

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), getOptLevelToEnablePostRAScheduler(), replaceShuffleOfInsert(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::useAA().


The documentation for this class was generated from the following files: