LLVM  9.0.0svn
BPFRegisterInfo.cpp
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1 //===-- BPFRegisterInfo.cpp - BPF Register Information ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the BPF implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "BPFRegisterInfo.h"
14 #include "BPF.h"
15 #include "BPFSubtarget.h"
22 #include "llvm/IR/DiagnosticInfo.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "BPFGenRegisterInfo.inc"
27 using namespace llvm;
28 
30  : BPFGenRegisterInfo(BPF::R0) {}
31 
32 const MCPhysReg *
34  return CSR_SaveList;
35 }
36 
38  BitVector Reserved(getNumRegs());
39  markSuperRegs(Reserved, BPF::W10); // [W|R]10 is read only frame pointer
40  markSuperRegs(Reserved, BPF::W11); // [W|R]11 is pseudo stack pointer
41  return Reserved;
42 }
43 
44 static void WarnSize(int Offset, MachineFunction &MF, DebugLoc& DL)
45 {
46  if (Offset <= -512) {
47  const Function &F = MF.getFunction();
48  DiagnosticInfoUnsupported DiagStackSize(F,
49  "Looks like the BPF stack limit of 512 bytes is exceeded. "
50  "Please move large on stack variables into BPF per-cpu array map.\n",
51  DL);
52  F.getContext().diagnose(DiagStackSize);
53  }
54 }
55 
57  int SPAdj, unsigned FIOperandNum,
58  RegScavenger *RS) const {
59  assert(SPAdj == 0 && "Unexpected");
60 
61  unsigned i = 0;
62  MachineInstr &MI = *II;
63  MachineBasicBlock &MBB = *MI.getParent();
64  MachineFunction &MF = *MBB.getParent();
65  DebugLoc DL = MI.getDebugLoc();
66 
67  if (!DL)
68  /* try harder to get some debug loc */
69  for (auto &I : MBB)
70  if (I.getDebugLoc()) {
71  DL = I.getDebugLoc();
72  break;
73  }
74 
75  while (!MI.getOperand(i).isFI()) {
76  ++i;
77  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
78  }
79 
80  unsigned FrameReg = getFrameRegister(MF);
81  int FrameIndex = MI.getOperand(i).getIndex();
83 
84  if (MI.getOpcode() == BPF::MOV_rr) {
85  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
86 
87  WarnSize(Offset, MF, DL);
88  MI.getOperand(i).ChangeToRegister(FrameReg, false);
89  unsigned reg = MI.getOperand(i - 1).getReg();
90  BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
91  .addReg(reg)
92  .addImm(Offset);
93  return;
94  }
95 
96  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
97  MI.getOperand(i + 1).getImm();
98 
99  if (!isInt<32>(Offset))
100  llvm_unreachable("bug in frame offset");
101 
102  WarnSize(Offset, MF, DL);
103 
104  if (MI.getOpcode() == BPF::FI_ri) {
105  // architecture does not really support FI_ri, replace it with
106  // MOV_rr <target_reg>, frame_reg
107  // ADD_ri <target_reg>, imm
108  unsigned reg = MI.getOperand(i - 1).getReg();
109 
110  BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
111  .addReg(FrameReg);
112  BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
113  .addReg(reg)
114  .addImm(Offset);
115 
116  // Remove FI_ri instruction
117  MI.eraseFromParent();
118  } else {
119  MI.getOperand(i).ChangeToRegister(FrameReg, false);
120  MI.getOperand(i + 1).ChangeToImmediate(Offset);
121  }
122 }
123 
125  return BPF::R10;
126 }
unsigned getFrameRegister(const MachineFunction &MF) const override
Diagnostic information for unsupported feature in backend.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
A debug info location.
Definition: DebugLoc.h:33
F(f)
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
virtual const TargetInstrInfo * getInstrInfo() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
static void WarnSize(int Offset, MachineFunction &MF, DebugLoc &DL)
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
BitVector getReservedRegs(const MachineFunction &MF) const override