LLVM  6.0.0svn
BPFRegisterInfo.cpp
Go to the documentation of this file.
1 //===-- BPFRegisterInfo.cpp - BPF Register Information ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the BPF implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "BPFRegisterInfo.h"
15 #include "BPF.h"
16 #include "BPFSubtarget.h"
23 #include "llvm/IR/DiagnosticInfo.h"
25 
26 #define GET_REGINFO_TARGET_DESC
27 #include "BPFGenRegisterInfo.inc"
28 using namespace llvm;
29 
31  : BPFGenRegisterInfo(BPF::R0) {}
32 
33 const MCPhysReg *
35  return CSR_SaveList;
36 }
37 
39  BitVector Reserved(getNumRegs());
40  Reserved.set(BPF::R10); // R10 is read only frame pointer
41  Reserved.set(BPF::R11); // R11 is pseudo stack pointer
42  return Reserved;
43 }
44 
45 static void WarnSize(int Offset, MachineFunction &MF, DebugLoc& DL)
46 {
47  if (Offset <= -512) {
48  auto F = MF.getFunction();
49  DiagnosticInfoUnsupported DiagStackSize(*F,
50  "Looks like the BPF stack limit of 512 bytes is exceeded. "
51  "Please move large on stack variables into BPF per-cpu array map.\n",
52  DL);
53  F->getContext().diagnose(DiagStackSize);
54  }
55 }
56 
58  int SPAdj, unsigned FIOperandNum,
59  RegScavenger *RS) const {
60  assert(SPAdj == 0 && "Unexpected");
61 
62  unsigned i = 0;
63  MachineInstr &MI = *II;
64  MachineBasicBlock &MBB = *MI.getParent();
65  MachineFunction &MF = *MBB.getParent();
66  DebugLoc DL = MI.getDebugLoc();
67 
68  if (!DL)
69  /* try harder to get some debug loc */
70  for (auto &I : MBB)
71  if (I.getDebugLoc()) {
72  DL = I.getDebugLoc();
73  break;
74  }
75 
76  while (!MI.getOperand(i).isFI()) {
77  ++i;
78  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
79  }
80 
81  unsigned FrameReg = getFrameRegister(MF);
82  int FrameIndex = MI.getOperand(i).getIndex();
84 
85  if (MI.getOpcode() == BPF::MOV_rr) {
86  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
87 
88  WarnSize(Offset, MF, DL);
89  MI.getOperand(i).ChangeToRegister(FrameReg, false);
90  unsigned reg = MI.getOperand(i - 1).getReg();
91  BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
92  .addReg(reg)
93  .addImm(Offset);
94  return;
95  }
96 
97  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
98  MI.getOperand(i + 1).getImm();
99 
100  if (!isInt<32>(Offset))
101  llvm_unreachable("bug in frame offset");
102 
103  WarnSize(Offset, MF, DL);
104 
105  if (MI.getOpcode() == BPF::FI_ri) {
106  // architecture does not really support FI_ri, replace it with
107  // MOV_rr <target_reg>, frame_reg
108  // ADD_ri <target_reg>, imm
109  unsigned reg = MI.getOperand(i - 1).getReg();
110 
111  BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
112  .addReg(FrameReg);
113  BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
114  .addReg(reg)
115  .addImm(Offset);
116 
117  // Remove FI_ri instruction
118  MI.eraseFromParent();
119  } else {
120  MI.getOperand(i).ChangeToRegister(FrameReg, false);
121  MI.getOperand(i + 1).ChangeToImmediate(Offset);
122  }
123 }
124 
126  return BPF::R10;
127 }
BitVector & set()
Definition: BitVector.h:398
unsigned getFrameRegister(const MachineFunction &MF) const override
Diagnostic information for unsupported feature in backend.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
A debug info location.
Definition: DebugLoc.h:34
F(f)
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
virtual const TargetInstrInfo * getInstrInfo() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
static void WarnSize(int Offset, MachineFunction &MF, DebugLoc &DL)
int64_t getImm() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
BitVector getReservedRegs(const MachineFunction &MF) const override