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ARMBaseRegisterInfo.cpp
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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugLoc.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Type.h"
42 #include "llvm/MC/MCInstrDesc.h"
43 #include "llvm/Support/Debug.h"
48 #include <cassert>
49 #include <utility>
50 
51 #define DEBUG_TYPE "arm-register-info"
52 
53 #define GET_REGINFO_TARGET_DESC
54 #include "ARMGenRegisterInfo.inc"
55 
56 using namespace llvm;
57 
59  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
60 
61 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
62  return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
63 }
64 
65 const MCPhysReg*
67  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
68  bool UseSplitPush = STI.splitFramePushPop(*MF);
69  const MCPhysReg *RegList =
70  STI.isTargetDarwin()
71  ? CSR_iOS_SaveList
72  : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
73 
74  const Function &F = MF->getFunction();
75  if (F.getCallingConv() == CallingConv::GHC) {
76  // GHC set of callee saved regs is empty as all those regs are
77  // used for passing STG regs around
78  return CSR_NoRegs_SaveList;
79  } else if (F.hasFnAttribute("interrupt")) {
80  if (STI.isMClass()) {
81  // M-class CPUs have hardware which saves the registers needed to allow a
82  // function conforming to the AAPCS to function as a handler.
83  return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
84  } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
85  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
86  // need to be saved to restore user-mode state.
87  return CSR_FIQ_SaveList;
88  } else {
89  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
90  // exception handling.
91  return CSR_GenericInt_SaveList;
92  }
93  }
94 
95  if (STI.getTargetLowering()->supportSwiftError() &&
96  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
97  if (STI.isTargetDarwin())
98  return CSR_iOS_SwiftError_SaveList;
99 
100  return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
101  CSR_AAPCS_SwiftError_SaveList;
102  }
103 
105  return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
106  ? CSR_iOS_CXX_TLS_PE_SaveList
107  : CSR_iOS_CXX_TLS_SaveList;
108  return RegList;
109 }
110 
112  const MachineFunction *MF) const {
113  assert(MF && "Invalid MachineFunction pointer.");
115  MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
116  return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
117  return nullptr;
118 }
119 
120 const uint32_t *
122  CallingConv::ID CC) const {
123  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
124  if (CC == CallingConv::GHC)
125  // This is academic because all GHC calls are (supposed to be) tail calls
126  return CSR_NoRegs_RegMask;
127 
128  if (STI.getTargetLowering()->supportSwiftError() &&
129  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
130  return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
131  : CSR_AAPCS_SwiftError_RegMask;
132 
133  if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
134  return CSR_iOS_CXX_TLS_RegMask;
135  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
136 }
137 
138 const uint32_t*
140  return CSR_NoRegs_RegMask;
141 }
142 
143 const uint32_t *
146  "only know about special TLS call on Darwin");
147  return CSR_iOS_TLSCall_RegMask;
148 }
149 
150 const uint32_t *
152  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
153  if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
154  return CSR_NoRegs_RegMask;
155  else
156  return CSR_FPRegs_RegMask;
157 }
158 
159 const uint32_t *
161  CallingConv::ID CC) const {
162  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
163  // This should return a register mask that is the same as that returned by
164  // getCallPreservedMask but that additionally preserves the register used for
165  // the first i32 argument (which must also be the register used to return a
166  // single i32 return value)
167  //
168  // In case that the calling convention does not use the same register for
169  // both or otherwise does not want to enable this optimization, the function
170  // should return NULL
171  if (CC == CallingConv::GHC)
172  // This is academic because all GHC calls are (supposed to be) tail calls
173  return nullptr;
174  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
175  : CSR_AAPCS_ThisReturn_RegMask;
176 }
177 
180  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
181  const ARMFrameLowering *TFI = getFrameLowering(MF);
182 
183  // FIXME: avoid re-calculating this every time.
184  BitVector Reserved(getNumRegs());
185  markSuperRegs(Reserved, ARM::SP);
186  markSuperRegs(Reserved, ARM::PC);
187  markSuperRegs(Reserved, ARM::FPSCR);
188  markSuperRegs(Reserved, ARM::APSR_NZCV);
189  if (TFI->hasFP(MF))
190  markSuperRegs(Reserved, getFramePointerReg(STI));
191  if (hasBasePointer(MF))
192  markSuperRegs(Reserved, BasePtr);
193  // Some targets reserve R9.
194  if (STI.isR9Reserved())
195  markSuperRegs(Reserved, ARM::R9);
196  // Reserve D16-D31 if the subtarget doesn't support them.
197  if (!STI.hasVFP3() || STI.hasD16()) {
198  static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
199  for (unsigned R = 0; R < 16; ++R)
200  markSuperRegs(Reserved, ARM::D16 + R);
201  }
202  const TargetRegisterClass &RC = ARM::GPRPairRegClass;
203  for (unsigned Reg : RC)
204  for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
205  if (Reserved.test(*SI))
206  markSuperRegs(Reserved, Reg);
207 
208  assert(checkAllSuperRegsMarked(Reserved));
209  return Reserved;
210 }
211 
213 isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {
214  return !getReservedRegs(MF).test(PhysReg);
215 }
216 
217 const TargetRegisterClass *
219  const MachineFunction &) const {
220  const TargetRegisterClass *Super = RC;
222  do {
223  switch (Super->getID()) {
224  case ARM::GPRRegClassID:
225  case ARM::SPRRegClassID:
226  case ARM::DPRRegClassID:
227  case ARM::QPRRegClassID:
228  case ARM::QQPRRegClassID:
229  case ARM::QQQQPRRegClassID:
230  case ARM::GPRPairRegClassID:
231  return Super;
232  }
233  Super = *I++;
234  } while (Super);
235  return RC;
236 }
237 
238 const TargetRegisterClass *
240  const {
241  return &ARM::GPRRegClass;
242 }
243 
244 const TargetRegisterClass *
246  if (RC == &ARM::CCRRegClass)
247  return &ARM::rGPRRegClass; // Can't copy CCR registers.
248  return RC;
249 }
250 
251 unsigned
253  MachineFunction &MF) const {
254  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
255  const ARMFrameLowering *TFI = getFrameLowering(MF);
256 
257  switch (RC->getID()) {
258  default:
259  return 0;
260  case ARM::tGPRRegClassID: {
261  // hasFP ends up calling getMaxCallFrameComputed() which may not be
262  // available when getPressureLimit() is called as part of
263  // ScheduleDAGRRList.
264  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
265  ? TFI->hasFP(MF) : true;
266  return 5 - HasFP;
267  }
268  case ARM::GPRRegClassID: {
269  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
270  ? TFI->hasFP(MF) : true;
271  return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
272  }
273  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
274  case ARM::DPRRegClassID:
275  return 32 - 10;
276  }
277 }
278 
279 // Get the other register in a GPRPair.
280 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
281  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
282  if (ARM::GPRPairRegClass.contains(*Supers))
283  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
284  return 0;
285 }
286 
287 // Resolve the RegPairEven / RegPairOdd register allocator hints.
288 bool
290  ArrayRef<MCPhysReg> Order,
292  const MachineFunction &MF,
293  const VirtRegMap *VRM,
294  const LiveRegMatrix *Matrix) const {
295  const MachineRegisterInfo &MRI = MF.getRegInfo();
296  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
297 
298  unsigned Odd;
299  switch (Hint.first) {
300  case ARMRI::RegPairEven:
301  Odd = 0;
302  break;
303  case ARMRI::RegPairOdd:
304  Odd = 1;
305  break;
306  default:
307  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
308  return false;
309  }
310 
311  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
312  // Check if the other part of the pair has already been assigned, and provide
313  // the paired register as the first hint.
314  unsigned Paired = Hint.second;
315  if (Paired == 0)
316  return false;
317 
318  unsigned PairedPhys = 0;
320  PairedPhys = Paired;
321  } else if (VRM && VRM->hasPhys(Paired)) {
322  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
323  }
324 
325  // First prefer the paired physreg.
326  if (PairedPhys && is_contained(Order, PairedPhys))
327  Hints.push_back(PairedPhys);
328 
329  // Then prefer even or odd registers.
330  for (unsigned Reg : Order) {
331  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
332  continue;
333  // Don't provide hints that are paired to a reserved register.
334  unsigned Paired = getPairedGPR(Reg, !Odd, this);
335  if (!Paired || MRI.isReserved(Paired))
336  continue;
337  Hints.push_back(Reg);
338  }
339  return false;
340 }
341 
342 void
344  MachineFunction &MF) const {
346  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
347  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
348  Hint.first == (unsigned)ARMRI::RegPairEven) &&
350  // If 'Reg' is one of the even / odd register pair and it's now changed
351  // (e.g. coalesced) into a different register. The other register of the
352  // pair allocation hint must be updated to reflect the relationship
353  // change.
354  unsigned OtherReg = Hint.second;
355  Hint = MRI->getRegAllocationHint(OtherReg);
356  // Make sure the pair has not already divorced.
357  if (Hint.second == Reg) {
358  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
360  MRI->setRegAllocationHint(NewReg,
361  Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
362  : ARMRI::RegPairOdd, OtherReg);
363  }
364  }
365 }
366 
368  const MachineFrameInfo &MFI = MF.getFrameInfo();
369  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
370  const ARMFrameLowering *TFI = getFrameLowering(MF);
371 
372  // When outgoing call frames are so large that we adjust the stack pointer
373  // around the call, we can no longer use the stack pointer to reach the
374  // emergency spill slot.
375  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
376  return true;
377 
378  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
379  // negative range for ldr/str (255), and thumb1 is positive offsets only.
380  // It's going to be better to use the SP or Base Pointer instead. When there
381  // are variable sized objects, we can't reference off of the SP, so we
382  // reserve a Base Pointer.
383  if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
384  // Conservatively estimate whether the negative offset from the frame
385  // pointer will be sufficient to reach. If a function has a smallish
386  // frame, it's less likely to have lots of spills and callee saved
387  // space, so it's all more likely to be within range of the frame pointer.
388  // If it's wrong, the scavenger will still enable access to work, it just
389  // won't be optimal.
390  if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
391  return false;
392  return true;
393  }
394 
395  return false;
396 }
397 
399  const MachineRegisterInfo *MRI = &MF.getRegInfo();
400  const ARMFrameLowering *TFI = getFrameLowering(MF);
401  // We can't realign the stack if:
402  // 1. Dynamic stack realignment is explicitly disabled,
403  // 2. There are VLAs in the function and the base pointer is disabled.
405  return false;
406  // Stack realignment requires a frame pointer. If we already started
407  // register allocation with frame pointer elimination, it is too late now.
409  return false;
410  // We may also need a base pointer if there are dynamic allocas or stack
411  // pointer adjustments around calls.
412  if (TFI->hasReservedCallFrame(MF))
413  return true;
414  // A base pointer is required and allowed. Check that it isn't too late to
415  // reserve it.
416  return MRI->canReserveReg(BasePtr);
417 }
418 
421  const MachineFrameInfo &MFI = MF.getFrameInfo();
423  return true;
424  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
425  || needsStackRealignment(MF);
426 }
427 
428 unsigned
430  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
431  const ARMFrameLowering *TFI = getFrameLowering(MF);
432 
433  if (TFI->hasFP(MF))
434  return getFramePointerReg(STI);
435  return ARM::SP;
436 }
437 
438 /// emitLoadConstPool - Emits a load from constpool to materialize the
439 /// specified immediate.
442  const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
443  ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
444  MachineFunction &MF = *MBB.getParent();
445  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
447  const Constant *C =
449  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
450 
451  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
452  .addReg(DestReg, getDefRegState(true), SubIdx)
453  .addConstantPoolIndex(Idx)
454  .addImm(0)
455  .add(predOps(Pred, PredReg))
456  .setMIFlags(MIFlags);
457 }
458 
461  return true;
462 }
463 
466  return true;
467 }
468 
471  return true;
472 }
473 
476  return true;
477 }
478 
479 int64_t ARMBaseRegisterInfo::
480 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
481  const MCInstrDesc &Desc = MI->getDesc();
482  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
483  int64_t InstrOffs = 0;
484  int Scale = 1;
485  unsigned ImmIdx = 0;
486  switch (AddrMode) {
489  case ARMII::AddrMode_i12:
490  InstrOffs = MI->getOperand(Idx+1).getImm();
491  Scale = 1;
492  break;
493  case ARMII::AddrMode5: {
494  // VFP address mode.
495  const MachineOperand &OffOp = MI->getOperand(Idx+1);
496  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
497  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
498  InstrOffs = -InstrOffs;
499  Scale = 4;
500  break;
501  }
502  case ARMII::AddrMode2:
503  ImmIdx = Idx+2;
504  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
505  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
506  InstrOffs = -InstrOffs;
507  break;
508  case ARMII::AddrMode3:
509  ImmIdx = Idx+2;
510  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
511  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
512  InstrOffs = -InstrOffs;
513  break;
514  case ARMII::AddrModeT1_s:
515  ImmIdx = Idx+1;
516  InstrOffs = MI->getOperand(ImmIdx).getImm();
517  Scale = 4;
518  break;
519  default:
520  llvm_unreachable("Unsupported addressing mode!");
521  }
522 
523  return InstrOffs * Scale;
524 }
525 
526 /// needsFrameBaseReg - Returns true if the instruction's frame index
527 /// reference would be better served by a base register other than FP
528 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
529 /// references it should create new base registers for.
532  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
533  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
534  }
535 
536  // It's the load/store FI references that cause issues, as it can be difficult
537  // to materialize the offset if it won't fit in the literal field. Estimate
538  // based on the size of the local frame and some conservative assumptions
539  // about the rest of the stack frame (note, this is pre-regalloc, so
540  // we don't know everything for certain yet) whether this offset is likely
541  // to be out of range of the immediate. Return true if so.
542 
543  // We only generate virtual base registers for loads and stores, so
544  // return false for everything else.
545  unsigned Opc = MI->getOpcode();
546  switch (Opc) {
547  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
548  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
549  case ARM::t2LDRi12: case ARM::t2LDRi8:
550  case ARM::t2STRi12: case ARM::t2STRi8:
551  case ARM::VLDRS: case ARM::VLDRD:
552  case ARM::VSTRS: case ARM::VSTRD:
553  case ARM::tSTRspi: case ARM::tLDRspi:
554  break;
555  default:
556  return false;
557  }
558 
559  // Without a virtual base register, if the function has variable sized
560  // objects, all fixed-size local references will be via the frame pointer,
561  // Approximate the offset and see if it's legal for the instruction.
562  // Note that the incoming offset is based on the SP value at function entry,
563  // so it'll be negative.
564  MachineFunction &MF = *MI->getParent()->getParent();
565  const ARMFrameLowering *TFI = getFrameLowering(MF);
566  MachineFrameInfo &MFI = MF.getFrameInfo();
568 
569  // Estimate an offset from the frame pointer.
570  // Conservatively assume all callee-saved registers get pushed. R4-R6
571  // will be earlier than the FP, so we ignore those.
572  // R7, LR
573  int64_t FPOffset = Offset - 8;
574  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
575  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
576  FPOffset -= 80;
577  // Estimate an offset from the stack pointer.
578  // The incoming offset is relating to the SP at the start of the function,
579  // but when we access the local it'll be relative to the SP after local
580  // allocation, so adjust our SP-relative offset by that allocation size.
581  Offset += MFI.getLocalFrameSize();
582  // Assume that we'll have at least some spill slots allocated.
583  // FIXME: This is a total SWAG number. We should run some statistics
584  // and pick a real one.
585  Offset += 128; // 128 bytes of spill slots
586 
587  // If there's a frame pointer and the addressing mode allows it, try using it.
588  // The FP is only available if there is no dynamic realignment. We
589  // don't know for sure yet whether we'll need that, so we guess based
590  // on whether there are any local variables that would trigger it.
591  unsigned StackAlign = TFI->getStackAlignment();
592  if (TFI->hasFP(MF) &&
593  !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
594  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
595  return false;
596  }
597  // If we can reference via the stack pointer, try that.
598  // FIXME: This (and the code that resolves the references) can be improved
599  // to only disallow SP relative references in the live range of
600  // the VLA(s). In practice, it's unclear how much difference that
601  // would make, but it may be worth doing.
602  if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
603  return false;
604 
605  // The offset likely isn't legal, we want to allocate a virtual base register.
606  return true;
607 }
608 
609 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
610 /// be a pointer to FrameIdx at the beginning of the basic block.
613  unsigned BaseReg, int FrameIdx,
614  int64_t Offset) const {
616  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
617  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
618 
620  DebugLoc DL; // Defaults to "unknown"
621  if (Ins != MBB->end())
622  DL = Ins->getDebugLoc();
623 
624  const MachineFunction &MF = *MBB->getParent();
626  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
627  const MCInstrDesc &MCID = TII.get(ADDriOpc);
628  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
629 
630  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
631  .addFrameIndex(FrameIdx).addImm(Offset);
632 
633  if (!AFI->isThumb1OnlyFunction())
635 }
636 
638  int64_t Offset) const {
639  MachineBasicBlock &MBB = *MI.getParent();
640  MachineFunction &MF = *MBB.getParent();
641  const ARMBaseInstrInfo &TII =
642  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
644  int Off = Offset; // ARM doesn't need the general 64-bit offsets
645  unsigned i = 0;
646 
647  assert(!AFI->isThumb1OnlyFunction() &&
648  "This resolveFrameIndex does not support Thumb1!");
649 
650  while (!MI.getOperand(i).isFI()) {
651  ++i;
652  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
653  }
654  bool Done = false;
655  if (!AFI->isThumbFunction())
656  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
657  else {
658  assert(AFI->isThumb2Function());
659  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
660  }
661  assert(Done && "Unable to resolve frame index!");
662  (void)Done;
663 }
664 
666  int64_t Offset) const {
667  const MCInstrDesc &Desc = MI->getDesc();
668  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
669  unsigned i = 0;
670  for (; !MI->getOperand(i).isFI(); ++i)
671  assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
672 
673  // AddrMode4 and AddrMode6 cannot handle any offset.
674  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
675  return Offset == 0;
676 
677  unsigned NumBits = 0;
678  unsigned Scale = 1;
679  bool isSigned = true;
680  switch (AddrMode) {
683  // i8 supports only negative, and i12 supports only positive, so
684  // based on Offset sign, consider the appropriate instruction
685  Scale = 1;
686  if (Offset < 0) {
687  NumBits = 8;
688  Offset = -Offset;
689  } else {
690  NumBits = 12;
691  }
692  break;
693  case ARMII::AddrMode5:
694  // VFP address mode.
695  NumBits = 8;
696  Scale = 4;
697  break;
698  case ARMII::AddrMode_i12:
699  case ARMII::AddrMode2:
700  NumBits = 12;
701  break;
702  case ARMII::AddrMode3:
703  NumBits = 8;
704  break;
705  case ARMII::AddrModeT1_s:
706  NumBits = (BaseReg == ARM::SP ? 8 : 5);
707  Scale = 4;
708  isSigned = false;
709  break;
710  default:
711  llvm_unreachable("Unsupported addressing mode!");
712  }
713 
714  Offset += getFrameIndexInstrOffset(MI, i);
715  // Make sure the offset is encodable for instructions that scale the
716  // immediate.
717  if ((Offset & (Scale-1)) != 0)
718  return false;
719 
720  if (isSigned && Offset < 0)
721  Offset = -Offset;
722 
723  unsigned Mask = (1 << NumBits) - 1;
724  if ((unsigned)Offset <= Mask * Scale)
725  return true;
726 
727  return false;
728 }
729 
730 void
732  int SPAdj, unsigned FIOperandNum,
733  RegScavenger *RS) const {
734  MachineInstr &MI = *II;
735  MachineBasicBlock &MBB = *MI.getParent();
736  MachineFunction &MF = *MBB.getParent();
737  const ARMBaseInstrInfo &TII =
738  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
739  const ARMFrameLowering *TFI = getFrameLowering(MF);
741  assert(!AFI->isThumb1OnlyFunction() &&
742  "This eliminateFrameIndex does not support Thumb1!");
743  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
744  unsigned FrameReg;
745 
746  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
747 
748  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
749  // call frame setup/destroy instructions have already been eliminated. That
750  // means the stack pointer cannot be used to access the emergency spill slot
751  // when !hasReservedCallFrame().
752 #ifndef NDEBUG
753  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
754  assert(TFI->hasReservedCallFrame(MF) &&
755  "Cannot use SP to access the emergency spill slot in "
756  "functions without a reserved call frame");
758  "Cannot use SP to access the emergency spill slot in "
759  "functions with variable sized frame objects");
760  }
761 #endif // NDEBUG
762 
763  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
764 
765  // Modify MI as necessary to handle as much of 'Offset' as possible
766  bool Done = false;
767  if (!AFI->isThumbFunction())
768  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
769  else {
770  assert(AFI->isThumb2Function());
771  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
772  }
773  if (Done)
774  return;
775 
776  // If we get here, the immediate doesn't fit into the instruction. We folded
777  // as much as possible above, handle the rest, providing a register that is
778  // SP+LargeImm.
779  assert((Offset ||
782  "This code isn't needed if offset already handled!");
783 
784  unsigned ScratchReg = 0;
785  int PIdx = MI.findFirstPredOperandIdx();
786  ARMCC::CondCodes Pred = (PIdx == -1)
788  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
789  if (Offset == 0)
790  // Must be addrmode4/6.
791  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
792  else {
793  ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
794  if (!AFI->isThumbFunction())
795  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
796  Offset, Pred, PredReg, TII);
797  else {
798  assert(AFI->isThumb2Function());
799  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
800  Offset, Pred, PredReg, TII);
801  }
802  // Update the original instruction to use the scratch register.
803  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
804  }
805 }
806 
808  const TargetRegisterClass *SrcRC,
809  unsigned SubReg,
810  const TargetRegisterClass *DstRC,
811  unsigned DstSubReg,
812  const TargetRegisterClass *NewRC,
813  LiveIntervals &LIS) const {
814  auto MBB = MI->getParent();
815  auto MF = MBB->getParent();
816  const MachineRegisterInfo &MRI = MF->getRegInfo();
817  // If not copying into a sub-register this should be ok because we shouldn't
818  // need to split the reg.
819  if (!DstSubReg)
820  return true;
821  // Small registers don't frequently cause a problem, so we can coalesce them.
822  if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
823  getRegSizeInBits(*SrcRC) < 256)
824  return true;
825 
826  auto NewRCWeight =
828  auto SrcRCWeight =
830  auto DstRCWeight =
832  // If the source register class is more expensive than the destination, the
833  // coalescing is probably profitable.
834  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
835  return true;
836  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
837  return true;
838 
839  // If the register allocator isn't constrained, we can always allow coalescing
840  // unfortunately we don't know yet if we will be constrained.
841  // The goal of this heuristic is to restrict how many expensive registers
842  // we allow to coalesce in a given basic block.
843  auto AFI = MF->getInfo<ARMFunctionInfo>();
844  auto It = AFI->getCoalescedWeight(MBB);
845 
846  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
847  << It->second << "\n");
848  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
849  << NewRCWeight.RegWeight << "\n");
850 
851  // This number is the largest round number that which meets the criteria:
852  // (1) addresses PR18825
853  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
854  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
855  // In practice the SizeMultiplier will only factor in for straight line code
856  // that uses a lot of NEON vectors, which isn't terribly common.
857  unsigned SizeMultiplier = MBB->size()/100;
858  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
859  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
860  It->second += NewRCWeight.RegWeight;
861  return true;
862  }
863  return false;
864 }
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const MachineInstrBuilder & add(const MachineOperand &MO) const
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
This class represents lattice values for constants.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
void push_back(const T &Elt)
Definition: SmallVector.h:218
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:495
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
bool hasVFP3() const
Definition: ARMSubtarget.h:568
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
A debug info location.
Definition: DebugLoc.h:34
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isThumb1Only() const
Definition: ARMSubtarget.h:713
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
Live Register Matrix
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned SubReg
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP...
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const TargetRegisterClass *const * sc_iterator
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
unsigned getID() const
Return the register class ID number.
bool hasVFP2() const
Definition: ARMSubtarget.h:567
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
unsigned char getAM3Offset(unsigned AM3Opc)
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:733
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:647
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:224
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool hasD16() const
Definition: ARMSubtarget.h:636
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:725
bool isR9Reserved() const
Definition: ARMSubtarget.h:721
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
AddrOpc getAM2Op(unsigned AM2Opc)
unsigned getDefRegState(bool B)
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned char getAM5Offset(unsigned AM5Opc)
This file declares the machine register scavenger class.
const TargetRegisterInfo * getTargetRegisterInfo() const
AddrOpc getAM3Op(unsigned AM3Opc)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const MachineRegisterInfo * MRI
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isMClass() const
Definition: ARMSubtarget.h:716
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasBasePointer(const MachineFunction &MF) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static unsigned getFramePointerReg(const ARMSubtarget &STI)
MCSubRegIterator enumerates all sub-registers of Reg.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool useSoftFloat() const
Definition: ARMSubtarget.h:711
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
bool isDebugValue() const
Definition: MachineInstr.h:997
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
unsigned getAM2Offset(unsigned AM2Opc)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:622
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool canRealignStack(const MachineFunction &MF) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:97
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:95
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
bool isMaxCallFrameSizeComputed() const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
IRTranslator LLVM IR MI
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
AddrOpc getAM5Op(unsigned AM5Opc)
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1239