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ARMBaseRegisterInfo.cpp
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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugLoc.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Type.h"
42 #include "llvm/MC/MCInstrDesc.h"
43 #include "llvm/Support/Debug.h"
48 #include <cassert>
49 #include <utility>
50 
51 #define DEBUG_TYPE "arm-register-info"
52 
53 #define GET_REGINFO_TARGET_DESC
54 #include "ARMGenRegisterInfo.inc"
55 
56 using namespace llvm;
57 
59  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
60 
61 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
62  return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
63 }
64 
65 const MCPhysReg*
67  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
68  bool UseSplitPush = STI.splitFramePushPop(*MF);
69  const MCPhysReg *RegList =
70  STI.isTargetDarwin()
71  ? CSR_iOS_SaveList
72  : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
73 
74  const Function *F = MF->getFunction();
75  if (F->getCallingConv() == CallingConv::GHC) {
76  // GHC set of callee saved regs is empty as all those regs are
77  // used for passing STG regs around
78  return CSR_NoRegs_SaveList;
79  } else if (F->hasFnAttribute("interrupt")) {
80  if (STI.isMClass()) {
81  // M-class CPUs have hardware which saves the registers needed to allow a
82  // function conforming to the AAPCS to function as a handler.
83  return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
84  } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
85  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
86  // need to be saved to restore user-mode state.
87  return CSR_FIQ_SaveList;
88  } else {
89  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
90  // exception handling.
91  return CSR_GenericInt_SaveList;
92  }
93  }
94 
95  if (STI.getTargetLowering()->supportSwiftError() &&
96  F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
97  if (STI.isTargetDarwin())
98  return CSR_iOS_SwiftError_SaveList;
99 
100  return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
101  CSR_AAPCS_SwiftError_SaveList;
102  }
103 
105  return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
106  ? CSR_iOS_CXX_TLS_PE_SaveList
107  : CSR_iOS_CXX_TLS_SaveList;
108  return RegList;
109 }
110 
112  const MachineFunction *MF) const {
113  assert(MF && "Invalid MachineFunction pointer.");
115  MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
116  return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
117  return nullptr;
118 }
119 
120 const uint32_t *
122  CallingConv::ID CC) const {
123  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
124  if (CC == CallingConv::GHC)
125  // This is academic because all GHC calls are (supposed to be) tail calls
126  return CSR_NoRegs_RegMask;
127 
128  if (STI.getTargetLowering()->supportSwiftError() &&
129  MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
130  return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
131  : CSR_AAPCS_SwiftError_RegMask;
132 
133  if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
134  return CSR_iOS_CXX_TLS_RegMask;
135  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
136 }
137 
138 const uint32_t*
140  return CSR_NoRegs_RegMask;
141 }
142 
143 const uint32_t *
146  "only know about special TLS call on Darwin");
147  return CSR_iOS_TLSCall_RegMask;
148 }
149 
150 const uint32_t *
152  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
153  if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
154  return CSR_NoRegs_RegMask;
155  else
156  return CSR_FPRegs_RegMask;
157 }
158 
159 const uint32_t *
161  CallingConv::ID CC) const {
162  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
163  // This should return a register mask that is the same as that returned by
164  // getCallPreservedMask but that additionally preserves the register used for
165  // the first i32 argument (which must also be the register used to return a
166  // single i32 return value)
167  //
168  // In case that the calling convention does not use the same register for
169  // both or otherwise does not want to enable this optimization, the function
170  // should return NULL
171  if (CC == CallingConv::GHC)
172  // This is academic because all GHC calls are (supposed to be) tail calls
173  return nullptr;
174  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
175  : CSR_AAPCS_ThisReturn_RegMask;
176 }
177 
180  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
181  const ARMFrameLowering *TFI = getFrameLowering(MF);
182 
183  // FIXME: avoid re-calculating this every time.
184  BitVector Reserved(getNumRegs());
185  markSuperRegs(Reserved, ARM::SP);
186  markSuperRegs(Reserved, ARM::PC);
187  markSuperRegs(Reserved, ARM::FPSCR);
188  markSuperRegs(Reserved, ARM::APSR_NZCV);
189  if (TFI->hasFP(MF))
190  markSuperRegs(Reserved, getFramePointerReg(STI));
191  if (hasBasePointer(MF))
192  markSuperRegs(Reserved, BasePtr);
193  // Some targets reserve R9.
194  if (STI.isR9Reserved())
195  markSuperRegs(Reserved, ARM::R9);
196  // Reserve D16-D31 if the subtarget doesn't support them.
197  if (!STI.hasVFP3() || STI.hasD16()) {
198  static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
199  for (unsigned R = 0; R < 16; ++R)
200  markSuperRegs(Reserved, ARM::D16 + R);
201  }
202  const TargetRegisterClass &RC = ARM::GPRPairRegClass;
203  for (unsigned Reg : RC)
204  for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
205  if (Reserved.test(*SI))
206  markSuperRegs(Reserved, Reg);
207 
208  assert(checkAllSuperRegsMarked(Reserved));
209  return Reserved;
210 }
211 
212 const TargetRegisterClass *
214  const MachineFunction &) const {
215  const TargetRegisterClass *Super = RC;
217  do {
218  switch (Super->getID()) {
219  case ARM::GPRRegClassID:
220  case ARM::SPRRegClassID:
221  case ARM::DPRRegClassID:
222  case ARM::QPRRegClassID:
223  case ARM::QQPRRegClassID:
224  case ARM::QQQQPRRegClassID:
225  case ARM::GPRPairRegClassID:
226  return Super;
227  }
228  Super = *I++;
229  } while (Super);
230  return RC;
231 }
232 
233 const TargetRegisterClass *
235  const {
236  return &ARM::GPRRegClass;
237 }
238 
239 const TargetRegisterClass *
241  if (RC == &ARM::CCRRegClass)
242  return &ARM::rGPRRegClass; // Can't copy CCR registers.
243  return RC;
244 }
245 
246 unsigned
248  MachineFunction &MF) const {
249  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
250  const ARMFrameLowering *TFI = getFrameLowering(MF);
251 
252  switch (RC->getID()) {
253  default:
254  return 0;
255  case ARM::tGPRRegClassID: {
256  // hasFP ends up calling getMaxCallFrameComputed() which may not be
257  // available when getPressureLimit() is called as part of
258  // ScheduleDAGRRList.
259  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
260  ? TFI->hasFP(MF) : true;
261  return 5 - HasFP;
262  }
263  case ARM::GPRRegClassID: {
264  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
265  ? TFI->hasFP(MF) : true;
266  return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
267  }
268  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
269  case ARM::DPRRegClassID:
270  return 32 - 10;
271  }
272 }
273 
274 // Get the other register in a GPRPair.
275 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
276  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
277  if (ARM::GPRPairRegClass.contains(*Supers))
278  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
279  return 0;
280 }
281 
282 // Resolve the RegPairEven / RegPairOdd register allocator hints.
283 bool
285  ArrayRef<MCPhysReg> Order,
287  const MachineFunction &MF,
288  const VirtRegMap *VRM,
289  const LiveRegMatrix *Matrix) const {
290  const MachineRegisterInfo &MRI = MF.getRegInfo();
291  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
292 
293  unsigned Odd;
294  switch (Hint.first) {
295  case ARMRI::RegPairEven:
296  Odd = 0;
297  break;
298  case ARMRI::RegPairOdd:
299  Odd = 1;
300  break;
301  default:
302  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
303  return false;
304  }
305 
306  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
307  // Check if the other part of the pair has already been assigned, and provide
308  // the paired register as the first hint.
309  unsigned Paired = Hint.second;
310  if (Paired == 0)
311  return false;
312 
313  unsigned PairedPhys = 0;
315  PairedPhys = Paired;
316  } else if (VRM && VRM->hasPhys(Paired)) {
317  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
318  }
319 
320  // First prefer the paired physreg.
321  if (PairedPhys && is_contained(Order, PairedPhys))
322  Hints.push_back(PairedPhys);
323 
324  // Then prefer even or odd registers.
325  for (unsigned Reg : Order) {
326  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
327  continue;
328  // Don't provide hints that are paired to a reserved register.
329  unsigned Paired = getPairedGPR(Reg, !Odd, this);
330  if (!Paired || MRI.isReserved(Paired))
331  continue;
332  Hints.push_back(Reg);
333  }
334  return false;
335 }
336 
337 void
339  MachineFunction &MF) const {
341  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
342  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
343  Hint.first == (unsigned)ARMRI::RegPairEven) &&
345  // If 'Reg' is one of the even / odd register pair and it's now changed
346  // (e.g. coalesced) into a different register. The other register of the
347  // pair allocation hint must be updated to reflect the relationship
348  // change.
349  unsigned OtherReg = Hint.second;
350  Hint = MRI->getRegAllocationHint(OtherReg);
351  // Make sure the pair has not already divorced.
352  if (Hint.second == Reg) {
353  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
355  MRI->setRegAllocationHint(NewReg,
356  Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
357  : ARMRI::RegPairOdd, OtherReg);
358  }
359  }
360 }
361 
363  const MachineFrameInfo &MFI = MF.getFrameInfo();
364  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
365  const ARMFrameLowering *TFI = getFrameLowering(MF);
366 
367  // When outgoing call frames are so large that we adjust the stack pointer
368  // around the call, we can no longer use the stack pointer to reach the
369  // emergency spill slot.
370  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
371  return true;
372 
373  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
374  // negative range for ldr/str (255), and thumb1 is positive offsets only.
375  // It's going to be better to use the SP or Base Pointer instead. When there
376  // are variable sized objects, we can't reference off of the SP, so we
377  // reserve a Base Pointer.
378  if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
379  // Conservatively estimate whether the negative offset from the frame
380  // pointer will be sufficient to reach. If a function has a smallish
381  // frame, it's less likely to have lots of spills and callee saved
382  // space, so it's all more likely to be within range of the frame pointer.
383  // If it's wrong, the scavenger will still enable access to work, it just
384  // won't be optimal.
385  if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
386  return false;
387  return true;
388  }
389 
390  return false;
391 }
392 
394  const MachineRegisterInfo *MRI = &MF.getRegInfo();
395  const ARMFrameLowering *TFI = getFrameLowering(MF);
396  // We can't realign the stack if:
397  // 1. Dynamic stack realignment is explicitly disabled,
398  // 2. There are VLAs in the function and the base pointer is disabled.
400  return false;
401  // Stack realignment requires a frame pointer. If we already started
402  // register allocation with frame pointer elimination, it is too late now.
404  return false;
405  // We may also need a base pointer if there are dynamic allocas or stack
406  // pointer adjustments around calls.
407  if (TFI->hasReservedCallFrame(MF))
408  return true;
409  // A base pointer is required and allowed. Check that it isn't too late to
410  // reserve it.
411  return MRI->canReserveReg(BasePtr);
412 }
413 
416  const MachineFrameInfo &MFI = MF.getFrameInfo();
418  return true;
419  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
420  || needsStackRealignment(MF);
421 }
422 
423 unsigned
425  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
426  const ARMFrameLowering *TFI = getFrameLowering(MF);
427 
428  if (TFI->hasFP(MF))
429  return getFramePointerReg(STI);
430  return ARM::SP;
431 }
432 
433 /// emitLoadConstPool - Emits a load from constpool to materialize the
434 /// specified immediate.
437  const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
438  ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
439  MachineFunction &MF = *MBB.getParent();
440  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
442  const Constant *C =
444  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
445 
446  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
447  .addReg(DestReg, getDefRegState(true), SubIdx)
448  .addConstantPoolIndex(Idx)
449  .addImm(0)
450  .add(predOps(Pred, PredReg))
451  .setMIFlags(MIFlags);
452 }
453 
456  return true;
457 }
458 
461  return true;
462 }
463 
466  return true;
467 }
468 
471  return true;
472 }
473 
474 int64_t ARMBaseRegisterInfo::
475 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
476  const MCInstrDesc &Desc = MI->getDesc();
477  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
478  int64_t InstrOffs = 0;
479  int Scale = 1;
480  unsigned ImmIdx = 0;
481  switch (AddrMode) {
484  case ARMII::AddrMode_i12:
485  InstrOffs = MI->getOperand(Idx+1).getImm();
486  Scale = 1;
487  break;
488  case ARMII::AddrMode5: {
489  // VFP address mode.
490  const MachineOperand &OffOp = MI->getOperand(Idx+1);
491  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
492  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
493  InstrOffs = -InstrOffs;
494  Scale = 4;
495  break;
496  }
497  case ARMII::AddrMode2:
498  ImmIdx = Idx+2;
499  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
500  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
501  InstrOffs = -InstrOffs;
502  break;
503  case ARMII::AddrMode3:
504  ImmIdx = Idx+2;
505  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
506  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
507  InstrOffs = -InstrOffs;
508  break;
509  case ARMII::AddrModeT1_s:
510  ImmIdx = Idx+1;
511  InstrOffs = MI->getOperand(ImmIdx).getImm();
512  Scale = 4;
513  break;
514  default:
515  llvm_unreachable("Unsupported addressing mode!");
516  }
517 
518  return InstrOffs * Scale;
519 }
520 
521 /// needsFrameBaseReg - Returns true if the instruction's frame index
522 /// reference would be better served by a base register other than FP
523 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
524 /// references it should create new base registers for.
527  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
528  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
529  }
530 
531  // It's the load/store FI references that cause issues, as it can be difficult
532  // to materialize the offset if it won't fit in the literal field. Estimate
533  // based on the size of the local frame and some conservative assumptions
534  // about the rest of the stack frame (note, this is pre-regalloc, so
535  // we don't know everything for certain yet) whether this offset is likely
536  // to be out of range of the immediate. Return true if so.
537 
538  // We only generate virtual base registers for loads and stores, so
539  // return false for everything else.
540  unsigned Opc = MI->getOpcode();
541  switch (Opc) {
542  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
543  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
544  case ARM::t2LDRi12: case ARM::t2LDRi8:
545  case ARM::t2STRi12: case ARM::t2STRi8:
546  case ARM::VLDRS: case ARM::VLDRD:
547  case ARM::VSTRS: case ARM::VSTRD:
548  case ARM::tSTRspi: case ARM::tLDRspi:
549  break;
550  default:
551  return false;
552  }
553 
554  // Without a virtual base register, if the function has variable sized
555  // objects, all fixed-size local references will be via the frame pointer,
556  // Approximate the offset and see if it's legal for the instruction.
557  // Note that the incoming offset is based on the SP value at function entry,
558  // so it'll be negative.
559  MachineFunction &MF = *MI->getParent()->getParent();
560  const ARMFrameLowering *TFI = getFrameLowering(MF);
561  MachineFrameInfo &MFI = MF.getFrameInfo();
563 
564  // Estimate an offset from the frame pointer.
565  // Conservatively assume all callee-saved registers get pushed. R4-R6
566  // will be earlier than the FP, so we ignore those.
567  // R7, LR
568  int64_t FPOffset = Offset - 8;
569  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
570  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
571  FPOffset -= 80;
572  // Estimate an offset from the stack pointer.
573  // The incoming offset is relating to the SP at the start of the function,
574  // but when we access the local it'll be relative to the SP after local
575  // allocation, so adjust our SP-relative offset by that allocation size.
576  Offset += MFI.getLocalFrameSize();
577  // Assume that we'll have at least some spill slots allocated.
578  // FIXME: This is a total SWAG number. We should run some statistics
579  // and pick a real one.
580  Offset += 128; // 128 bytes of spill slots
581 
582  // If there's a frame pointer and the addressing mode allows it, try using it.
583  // The FP is only available if there is no dynamic realignment. We
584  // don't know for sure yet whether we'll need that, so we guess based
585  // on whether there are any local variables that would trigger it.
586  unsigned StackAlign = TFI->getStackAlignment();
587  if (TFI->hasFP(MF) &&
588  !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
589  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
590  return false;
591  }
592  // If we can reference via the stack pointer, try that.
593  // FIXME: This (and the code that resolves the references) can be improved
594  // to only disallow SP relative references in the live range of
595  // the VLA(s). In practice, it's unclear how much difference that
596  // would make, but it may be worth doing.
597  if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
598  return false;
599 
600  // The offset likely isn't legal, we want to allocate a virtual base register.
601  return true;
602 }
603 
604 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
605 /// be a pointer to FrameIdx at the beginning of the basic block.
608  unsigned BaseReg, int FrameIdx,
609  int64_t Offset) const {
611  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
612  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
613 
615  DebugLoc DL; // Defaults to "unknown"
616  if (Ins != MBB->end())
617  DL = Ins->getDebugLoc();
618 
619  const MachineFunction &MF = *MBB->getParent();
621  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
622  const MCInstrDesc &MCID = TII.get(ADDriOpc);
623  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
624 
625  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
626  .addFrameIndex(FrameIdx).addImm(Offset);
627 
628  if (!AFI->isThumb1OnlyFunction())
630 }
631 
633  int64_t Offset) const {
634  MachineBasicBlock &MBB = *MI.getParent();
635  MachineFunction &MF = *MBB.getParent();
636  const ARMBaseInstrInfo &TII =
637  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
639  int Off = Offset; // ARM doesn't need the general 64-bit offsets
640  unsigned i = 0;
641 
642  assert(!AFI->isThumb1OnlyFunction() &&
643  "This resolveFrameIndex does not support Thumb1!");
644 
645  while (!MI.getOperand(i).isFI()) {
646  ++i;
647  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
648  }
649  bool Done = false;
650  if (!AFI->isThumbFunction())
651  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
652  else {
653  assert(AFI->isThumb2Function());
654  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
655  }
656  assert(Done && "Unable to resolve frame index!");
657  (void)Done;
658 }
659 
661  int64_t Offset) const {
662  const MCInstrDesc &Desc = MI->getDesc();
663  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
664  unsigned i = 0;
665  for (; !MI->getOperand(i).isFI(); ++i)
666  assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
667 
668  // AddrMode4 and AddrMode6 cannot handle any offset.
669  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
670  return Offset == 0;
671 
672  unsigned NumBits = 0;
673  unsigned Scale = 1;
674  bool isSigned = true;
675  switch (AddrMode) {
678  // i8 supports only negative, and i12 supports only positive, so
679  // based on Offset sign, consider the appropriate instruction
680  Scale = 1;
681  if (Offset < 0) {
682  NumBits = 8;
683  Offset = -Offset;
684  } else {
685  NumBits = 12;
686  }
687  break;
688  case ARMII::AddrMode5:
689  // VFP address mode.
690  NumBits = 8;
691  Scale = 4;
692  break;
693  case ARMII::AddrMode_i12:
694  case ARMII::AddrMode2:
695  NumBits = 12;
696  break;
697  case ARMII::AddrMode3:
698  NumBits = 8;
699  break;
700  case ARMII::AddrModeT1_s:
701  NumBits = (BaseReg == ARM::SP ? 8 : 5);
702  Scale = 4;
703  isSigned = false;
704  break;
705  default:
706  llvm_unreachable("Unsupported addressing mode!");
707  }
708 
709  Offset += getFrameIndexInstrOffset(MI, i);
710  // Make sure the offset is encodable for instructions that scale the
711  // immediate.
712  if ((Offset & (Scale-1)) != 0)
713  return false;
714 
715  if (isSigned && Offset < 0)
716  Offset = -Offset;
717 
718  unsigned Mask = (1 << NumBits) - 1;
719  if ((unsigned)Offset <= Mask * Scale)
720  return true;
721 
722  return false;
723 }
724 
725 void
727  int SPAdj, unsigned FIOperandNum,
728  RegScavenger *RS) const {
729  MachineInstr &MI = *II;
730  MachineBasicBlock &MBB = *MI.getParent();
731  MachineFunction &MF = *MBB.getParent();
732  const ARMBaseInstrInfo &TII =
733  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
734  const ARMFrameLowering *TFI = getFrameLowering(MF);
736  assert(!AFI->isThumb1OnlyFunction() &&
737  "This eliminateFrameIndex does not support Thumb1!");
738  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
739  unsigned FrameReg;
740 
741  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
742 
743  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
744  // call frame setup/destroy instructions have already been eliminated. That
745  // means the stack pointer cannot be used to access the emergency spill slot
746  // when !hasReservedCallFrame().
747 #ifndef NDEBUG
748  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
749  assert(TFI->hasReservedCallFrame(MF) &&
750  "Cannot use SP to access the emergency spill slot in "
751  "functions without a reserved call frame");
753  "Cannot use SP to access the emergency spill slot in "
754  "functions with variable sized frame objects");
755  }
756 #endif // NDEBUG
757 
758  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
759 
760  // Modify MI as necessary to handle as much of 'Offset' as possible
761  bool Done = false;
762  if (!AFI->isThumbFunction())
763  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
764  else {
765  assert(AFI->isThumb2Function());
766  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
767  }
768  if (Done)
769  return;
770 
771  // If we get here, the immediate doesn't fit into the instruction. We folded
772  // as much as possible above, handle the rest, providing a register that is
773  // SP+LargeImm.
774  assert((Offset ||
777  "This code isn't needed if offset already handled!");
778 
779  unsigned ScratchReg = 0;
780  int PIdx = MI.findFirstPredOperandIdx();
781  ARMCC::CondCodes Pred = (PIdx == -1)
783  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
784  if (Offset == 0)
785  // Must be addrmode4/6.
786  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
787  else {
788  ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
789  if (!AFI->isThumbFunction())
790  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
791  Offset, Pred, PredReg, TII);
792  else {
793  assert(AFI->isThumb2Function());
794  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
795  Offset, Pred, PredReg, TII);
796  }
797  // Update the original instruction to use the scratch register.
798  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
799  }
800 }
801 
803  const TargetRegisterClass *SrcRC,
804  unsigned SubReg,
805  const TargetRegisterClass *DstRC,
806  unsigned DstSubReg,
807  const TargetRegisterClass *NewRC,
808  LiveIntervals &LIS) const {
809  auto MBB = MI->getParent();
810  auto MF = MBB->getParent();
811  const MachineRegisterInfo &MRI = MF->getRegInfo();
812  // If not copying into a sub-register this should be ok because we shouldn't
813  // need to split the reg.
814  if (!DstSubReg)
815  return true;
816  // Small registers don't frequently cause a problem, so we can coalesce them.
817  if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
818  getRegSizeInBits(*SrcRC) < 256)
819  return true;
820 
821  auto NewRCWeight =
823  auto SrcRCWeight =
825  auto DstRCWeight =
827  // If the source register class is more expensive than the destination, the
828  // coalescing is probably profitable.
829  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
830  return true;
831  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
832  return true;
833 
834  // If the register allocator isn't constrained, we can always allow coalescing
835  // unfortunately we don't know yet if we will be constrained.
836  // The goal of this heuristic is to restrict how many expensive registers
837  // we allow to coalesce in a given basic block.
838  auto AFI = MF->getInfo<ARMFunctionInfo>();
839  auto It = AFI->getCoalescedWeight(MBB);
840 
841  DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
842  << It->second << "\n");
843  DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
844  << NewRCWeight.RegWeight << "\n");
845 
846  // This number is the largest round number that which meets the criteria:
847  // (1) addresses PR18825
848  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
849  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
850  // In practice the SizeMultiplier will only factor in for straight line code
851  // that uses a lot of NEON vectors, which isn't terribly common.
852  unsigned SizeMultiplier = MBB->size()/100;
853  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
854  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
855  It->second += NewRCWeight.RegWeight;
856  return true;
857  }
858  return false;
859 }
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
void push_back(const T &Elt)
Definition: SmallVector.h:212
const MachineInstrBuilder & add(const MachineOperand &MO) const
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:459
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool test(unsigned Idx) const
Definition: BitVector.h:502
bool hasVFP3() const
Definition: ARMSubtarget.h:530
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
A debug info location.
Definition: DebugLoc.h:34
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isThumb1Only() const
Definition: ARMSubtarget.h:673
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
Live Register Matrix
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned SubReg
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP...
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const TargetRegisterClass *const * sc_iterator
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
unsigned getID() const
Return the register class ID number.
bool hasVFP2() const
Definition: ARMSubtarget.h:529
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
unsigned char getAM3Offset(unsigned AM3Opc)
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:693
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:601
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool hasD16() const
Definition: ARMSubtarget.h:592
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:685
bool isR9Reserved() const
Definition: ARMSubtarget.h:681
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
AddrOpc getAM2Op(unsigned AM2Opc)
unsigned getDefRegState(bool B)
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned char getAM5Offset(unsigned AM5Opc)
This file declares the machine register scavenger class.
const TargetRegisterInfo * getTargetRegisterInfo() const
AddrOpc getAM3Op(unsigned AM3Opc)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const MachineRegisterInfo * MRI
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isMClass() const
Definition: ARMSubtarget.h:676
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasBasePointer(const MachineFunction &MF) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static unsigned getFramePointerReg(const ARMSubtarget &STI)
MCSubRegIterator enumerates all sub-registers of Reg.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool useSoftFloat() const
Definition: ARMSubtarget.h:671
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
bool isDebugValue() const
Definition: MachineInstr.h:816
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
unsigned getAM2Offset(unsigned AM2Opc)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:560
int64_t getImm() const
bool canRealignStack(const MachineFunction &MF) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:172
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:96
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:95
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:270
#define DEBUG(X)
Definition: Debug.h:118
bool isMaxCallFrameSizeComputed() const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
IRTranslator LLVM IR MI
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
AddrOpc getAM5Op(unsigned AM5Opc)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:867