LLVM  6.0.0svn
Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::ARMBaseRegisterInfo Class Reference

#include "Target/ARM/ARMBaseRegisterInfo.h"

Inheritance diagram for llvm::ARMBaseRegisterInfo:
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Collaboration diagram for llvm::ARMBaseRegisterInfo:
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Public Member Functions

const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const override
 Code Generation virtual methods... More...
 
const MCPhysReggetCalleeSavedRegsViaCopy (const MachineFunction *MF) const
 
const uint32_tgetCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
 
const uint32_tgetNoPreservedMask () const override
 
const uint32_tgetTLSCallPreservedMask (const MachineFunction &MF) const
 
const uint32_tgetSjLjDispatchPreservedMask (const MachineFunction &MF) const
 
const uint32_tgetThisReturnPreservedMask (const MachineFunction &MF, CallingConv::ID) const
 getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e. More...
 
BitVector getReservedRegs (const MachineFunction &MF) const override
 
const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
 
const TargetRegisterClassgetCrossCopyRegClass (const TargetRegisterClass *RC) const override
 
const TargetRegisterClassgetLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override
 
unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
 
void getRegAllocationHints (unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
 
void updateRegAllocHint (unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
 
bool hasBasePointer (const MachineFunction &MF) const
 
bool canRealignStack (const MachineFunction &MF) const override
 
int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
 
bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
 needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. More...
 
void materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
 materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic block. More...
 
void resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
 
bool isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
 
bool cannotEliminateFrame (const MachineFunction &MF) const
 
unsigned getFrameRegister (const MachineFunction &MF) const override
 
unsigned getBaseRegister () const
 
bool isLowRegister (unsigned Reg) const
 
virtual void emitLoadConstPool (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
 emitLoadConstPool - Emits a load from constpool to materialize the specified immediate. More...
 
bool requiresRegisterScavenging (const MachineFunction &MF) const override
 Code Generation virtual methods... More...
 
bool trackLivenessAfterRegAlloc (const MachineFunction &MF) const override
 
bool requiresFrameIndexScavenging (const MachineFunction &MF) const override
 
bool requiresVirtualBaseRegisters (const MachineFunction &MF) const override
 
void eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
 
bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
 SrcRC and DstRC will be morphed into NewRC if this returns true. More...
 

Protected Member Functions

 ARMBaseRegisterInfo ()
 
unsigned getOpcode (int Op) const
 

Protected Attributes

unsigned BasePtr = ARM::R6
 BasePtr - ARM physical register used as a base ptr in complex stack frames. More...
 

Detailed Description

Definition at line 98 of file ARMBaseRegisterInfo.h.

Constructor & Destructor Documentation

◆ ARMBaseRegisterInfo()

ARMBaseRegisterInfo::ARMBaseRegisterInfo ( )
explicitprotected

Definition at line 58 of file ARMBaseRegisterInfo.cpp.

Member Function Documentation

◆ cannotEliminateFrame()

bool ARMBaseRegisterInfo::cannotEliminateFrame ( const MachineFunction MF) const

◆ canRealignStack()

bool ARMBaseRegisterInfo::canRealignStack ( const MachineFunction MF) const
override

◆ eliminateFrameIndex()

void ARMBaseRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  II,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS = nullptr 
) const
override

◆ emitLoadConstPool()

void ARMBaseRegisterInfo::emitLoadConstPool ( MachineBasicBlock MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc dl,
unsigned  DestReg,
unsigned  SubIdx,
int  Val,
ARMCC::CondCodes  Pred = ARMCC::AL,
unsigned  PredReg = 0,
unsigned  MIFlags = MachineInstr::NoFlags 
) const
virtual

◆ getBaseRegister()

unsigned llvm::ARMBaseRegisterInfo::getBaseRegister ( ) const
inline

◆ getCalleeSavedRegs()

const MCPhysReg * ARMBaseRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
override

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction MF) const

◆ getCallPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID  CC 
) const
override

◆ getCrossCopyRegClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass RC) const
override

Definition at line 240 of file ARMBaseRegisterInfo.cpp.

◆ getFrameIndexInstrOffset()

int64_t ARMBaseRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
override

◆ getFrameRegister()

unsigned ARMBaseRegisterInfo::getFrameRegister ( const MachineFunction MF) const
override

◆ getLargestLegalSuperClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass RC,
const MachineFunction MF 
) const
override

◆ getNoPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getNoPreservedMask ( ) const
override

Definition at line 139 of file ARMBaseRegisterInfo.cpp.

◆ getOpcode()

unsigned llvm::ARMBaseRegisterInfo::getOpcode ( int  Op) const
protected

◆ getPointerRegClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
override

◆ getRegAllocationHints()

void ARMBaseRegisterInfo::getRegAllocationHints ( unsigned  VirtReg,
ArrayRef< MCPhysReg Order,
SmallVectorImpl< MCPhysReg > &  Hints,
const MachineFunction MF,
const VirtRegMap VRM,
const LiveRegMatrix Matrix 
) const
override

◆ getRegPressureLimit()

unsigned ARMBaseRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
override

◆ getReservedRegs()

BitVector ARMBaseRegisterInfo::getReservedRegs ( const MachineFunction MF) const
override

◆ getSjLjDispatchPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getSjLjDispatchPreservedMask ( const MachineFunction MF) const

◆ getThisReturnPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getThisReturnPreservedMask ( const MachineFunction MF,
CallingConv::ID  CC 
) const

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e.

it is a calling convention that uses the same register for the first i32 argument and an i32 return value)

Should return NULL in the case that the calling convention does not have this property

Definition at line 160 of file ARMBaseRegisterInfo.cpp.

References getReservedRegs(), llvm::MachineFunction::getSubtarget(), llvm::CallingConv::GHC, and llvm::ARMSubtarget::isTargetDarwin().

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn().

◆ getTLSCallPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getTLSCallPreservedMask ( const MachineFunction MF) const

◆ hasBasePointer()

bool ARMBaseRegisterInfo::hasBasePointer ( const MachineFunction MF) const

◆ isFrameOffsetLegal()

bool ARMBaseRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
override

◆ isLowRegister()

bool llvm::ARMBaseRegisterInfo::isLowRegister ( unsigned  Reg) const

◆ materializeFrameBaseRegister()

void ARMBaseRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
unsigned  BaseReg,
int  FrameIdx,
int64_t  Offset 
) const
override

◆ needsFrameBaseReg()

bool ARMBaseRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
override

◆ requiresFrameIndexScavenging()

bool ARMBaseRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
override

Definition at line 468 of file ARMBaseRegisterInfo.cpp.

References requiresVirtualBaseRegisters().

Referenced by trackLivenessAfterRegAlloc().

◆ requiresRegisterScavenging()

bool ARMBaseRegisterInfo::requiresRegisterScavenging ( const MachineFunction MF) const
override

Code Generation virtual methods...

Definition at line 458 of file ARMBaseRegisterInfo.cpp.

References trackLivenessAfterRegAlloc().

Referenced by emitLoadConstPool().

◆ requiresVirtualBaseRegisters()

bool ARMBaseRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction MF) const
override

Definition at line 473 of file ARMBaseRegisterInfo.cpp.

References getFrameIndexInstrOffset().

Referenced by requiresFrameIndexScavenging().

◆ resolveFrameIndex()

void ARMBaseRegisterInfo::resolveFrameIndex ( MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
override

◆ shouldCoalesce()

bool ARMBaseRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC,
LiveIntervals LIS 
) const
override

◆ trackLivenessAfterRegAlloc()

bool ARMBaseRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction MF) const
override

Definition at line 463 of file ARMBaseRegisterInfo.cpp.

References requiresFrameIndexScavenging().

Referenced by requiresRegisterScavenging().

◆ updateRegAllocHint()

void ARMBaseRegisterInfo::updateRegAllocHint ( unsigned  Reg,
unsigned  NewReg,
MachineFunction MF 
) const
override

Member Data Documentation

◆ BasePtr

unsigned llvm::ARMBaseRegisterInfo::BasePtr = ARM::R6
protected

BasePtr - ARM physical register used as a base ptr in complex stack frames.

I.e., when we need a 3rd base, not just SP and FP, due to variable size stack objects.

Definition at line 103 of file ARMBaseRegisterInfo.h.

Referenced by canRealignStack(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), and getReservedRegs().


The documentation for this class was generated from the following files: