LLVM  6.0.0svn
Thumb1FrameLowering.cpp
Go to the documentation of this file.
1 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb1FrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "ThumbRegisterInfo.h"
21 #include "Utils/ARMBaseInfo.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCDwarf.h"
40 #include "llvm/MC/MCRegisterInfo.h"
41 #include "llvm/Support/Compiler.h"
44 #include <bitset>
45 #include <cassert>
46 #include <iterator>
47 #include <vector>
48 
49 using namespace llvm;
50 
52  : ARMFrameLowering(sti) {}
53 
55  const MachineFrameInfo &MFI = MF.getFrameInfo();
56  unsigned CFSize = MFI.getMaxCallFrameSize();
57  // It's not always a good idea to include the call frame as part of the
58  // stack frame. ARM (especially Thumb) has small immediate offset to
59  // address the stack frame. So a large call frame can cause poor codegen
60  // and may even makes it impossible to scavenge a register.
61  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
62  return false;
63 
64  return !MFI.hasVarSizedObjects();
65 }
66 
69  const TargetInstrInfo &TII, const DebugLoc &dl,
70  const ThumbRegisterInfo &MRI, int NumBytes,
71  unsigned MIFlags = MachineInstr::NoFlags) {
72  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
73  MRI, MIFlags);
74 }
75 
79  const Thumb1InstrInfo &TII =
80  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
81  const ThumbRegisterInfo *RegInfo =
82  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
83  if (!hasReservedCallFrame(MF)) {
84  // If we have alloca, convert as follows:
85  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
86  // ADJCALLSTACKUP -> add, sp, sp, amount
87  MachineInstr &Old = *I;
88  DebugLoc dl = Old.getDebugLoc();
89  unsigned Amount = TII.getFrameSize(Old);
90  if (Amount != 0) {
91  // We need to keep the stack aligned properly. To do this, we round the
92  // amount of space needed for the outgoing arguments up to the next
93  // alignment boundary.
94  Amount = alignTo(Amount, getStackAlignment());
95 
96  // Replace the pseudo instruction with a new instruction...
97  unsigned Opc = Old.getOpcode();
98  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
99  emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
100  } else {
101  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
102  emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
103  }
104  }
105  }
106  return MBB.erase(I);
107 }
108 
110  MachineBasicBlock &MBB) const {
111  MachineBasicBlock::iterator MBBI = MBB.begin();
112  MachineFrameInfo &MFI = MF.getFrameInfo();
114  MachineModuleInfo &MMI = MF.getMMI();
115  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
116  const ThumbRegisterInfo *RegInfo =
117  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
118  const Thumb1InstrInfo &TII =
119  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
120 
121  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
122  unsigned NumBytes = MFI.getStackSize();
123  assert(NumBytes >= ArgRegsSaveSize &&
124  "ArgRegsSaveSize is included in NumBytes");
125  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
126 
127  // Debug location must be unknown since the first debug location is used
128  // to determine the end of the prologue.
129  DebugLoc dl;
130 
131  unsigned FramePtr = RegInfo->getFrameRegister(MF);
132  unsigned BasePtr = RegInfo->getBaseRegister();
133  int CFAOffset = 0;
134 
135  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
136  NumBytes = (NumBytes + 3) & ~3;
137  MFI.setStackSize(NumBytes);
138 
139  // Determine the sizes of each callee-save spill areas and record which frame
140  // belongs to which callee-save spill areas.
141  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
142  int FramePtrSpillFI = 0;
143 
144  if (ArgRegsSaveSize) {
145  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
147  CFAOffset -= ArgRegsSaveSize;
148  unsigned CFIIndex = MF.addFrameInst(
149  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
150  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
151  .addCFIIndex(CFIIndex)
153  }
154 
155  if (!AFI->hasStackFrame()) {
156  if (NumBytes - ArgRegsSaveSize != 0) {
157  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
159  CFAOffset -= NumBytes - ArgRegsSaveSize;
160  unsigned CFIIndex = MF.addFrameInst(
161  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
162  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
163  .addCFIIndex(CFIIndex)
165  }
166  return;
167  }
168 
169  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
170  unsigned Reg = CSI[i].getReg();
171  int FI = CSI[i].getFrameIdx();
172  switch (Reg) {
173  case ARM::R8:
174  case ARM::R9:
175  case ARM::R10:
176  case ARM::R11:
177  if (STI.splitFramePushPop(MF)) {
178  GPRCS2Size += 4;
179  break;
180  }
182  case ARM::R4:
183  case ARM::R5:
184  case ARM::R6:
185  case ARM::R7:
186  case ARM::LR:
187  if (Reg == FramePtr)
188  FramePtrSpillFI = FI;
189  GPRCS1Size += 4;
190  break;
191  default:
192  DPRCSSize += 8;
193  }
194  }
195 
196  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
197  ++MBBI;
198  }
199 
200  // Determine starting offsets of spill areas.
201  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
202  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
203  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
204  bool HasFP = hasFP(MF);
205  if (HasFP)
206  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
207  NumBytes);
208  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
209  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
210  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
211  NumBytes = DPRCSOffset;
212 
213  int FramePtrOffsetInBlock = 0;
214  unsigned adjustedGPRCS1Size = GPRCS1Size;
215  if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
216  tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
217  FramePtrOffsetInBlock = NumBytes;
218  adjustedGPRCS1Size += NumBytes;
219  NumBytes = 0;
220  }
221 
222  if (adjustedGPRCS1Size) {
223  CFAOffset -= adjustedGPRCS1Size;
224  unsigned CFIIndex = MF.addFrameInst(
225  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
226  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
227  .addCFIIndex(CFIIndex)
229  }
230  for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
231  E = CSI.end(); I != E; ++I) {
232  unsigned Reg = I->getReg();
233  int FI = I->getFrameIdx();
234  switch (Reg) {
235  case ARM::R8:
236  case ARM::R9:
237  case ARM::R10:
238  case ARM::R11:
239  case ARM::R12:
240  if (STI.splitFramePushPop(MF))
241  break;
243  case ARM::R0:
244  case ARM::R1:
245  case ARM::R2:
246  case ARM::R3:
247  case ARM::R4:
248  case ARM::R5:
249  case ARM::R6:
250  case ARM::R7:
251  case ARM::LR:
252  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
253  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
254  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255  .addCFIIndex(CFIIndex)
257  break;
258  }
259  }
260 
261  // Adjust FP so it point to the stack slot that contains the previous FP.
262  if (HasFP) {
263  FramePtrOffsetInBlock +=
264  MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
265  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
266  .addReg(ARM::SP)
267  .addImm(FramePtrOffsetInBlock / 4)
269  .add(predOps(ARMCC::AL));
270  if(FramePtrOffsetInBlock) {
271  CFAOffset += FramePtrOffsetInBlock;
272  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
273  nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
274  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
275  .addCFIIndex(CFIIndex)
277  } else {
278  unsigned CFIIndex =
280  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
281  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
282  .addCFIIndex(CFIIndex)
284  }
285  if (NumBytes > 508)
286  // If offset is > 508 then sp cannot be adjusted in a single instruction,
287  // try restoring from fp instead.
288  AFI->setShouldRestoreSPFromFP(true);
289  }
290 
291  // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
292  // and tMOVr instructions. We don't need to add any call frame information
293  // in-between these instructions, because they do not modify the high
294  // registers.
295  while (true) {
296  MachineBasicBlock::iterator OldMBBI = MBBI;
297  // Skip a run of tMOVr instructions
298  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
299  MBBI++;
300  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
301  MBBI++;
302  } else {
303  // We have reached an instruction which is not a push, so the previous
304  // run of tMOVr instructions (which may have been empty) was not part of
305  // the prologue. Reset MBBI back to the last PUSH of the prologue.
306  MBBI = OldMBBI;
307  break;
308  }
309  }
310 
311  // Emit call frame information for the callee-saved high registers.
312  for (auto &I : CSI) {
313  unsigned Reg = I.getReg();
314  int FI = I.getFrameIdx();
315  switch (Reg) {
316  case ARM::R8:
317  case ARM::R9:
318  case ARM::R10:
319  case ARM::R11:
320  case ARM::R12: {
321  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
322  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
323  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
324  .addCFIIndex(CFIIndex)
326  break;
327  }
328  default:
329  break;
330  }
331  }
332 
333  if (NumBytes) {
334  // Insert it after all the callee-save spills.
335  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
337  if (!HasFP) {
338  CFAOffset -= NumBytes;
339  unsigned CFIIndex = MF.addFrameInst(
340  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
341  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
342  .addCFIIndex(CFIIndex)
344  }
345  }
346 
347  if (STI.isTargetELF() && HasFP)
349  AFI->getFramePtrSpillOffset());
350 
351  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
352  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
353  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
354 
355  if (RegInfo->needsStackRealignment(MF)) {
356  const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
357  // Emit the following sequence, using R4 as a temporary, since we cannot use
358  // SP as a source or destination register for the shifts:
359  // mov r4, sp
360  // lsrs r4, r4, #NrBitsToZero
361  // lsls r4, r4, #NrBitsToZero
362  // mov sp, r4
363  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
364  .addReg(ARM::SP, RegState::Kill)
365  .add(predOps(ARMCC::AL));
366 
367  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
368  .addDef(ARM::CPSR)
370  .addImm(NrBitsToZero)
371  .add(predOps(ARMCC::AL));
372 
373  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
374  .addDef(ARM::CPSR)
376  .addImm(NrBitsToZero)
377  .add(predOps(ARMCC::AL));
378 
379  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
380  .addReg(ARM::R4, RegState::Kill)
381  .add(predOps(ARMCC::AL));
382 
383  AFI->setShouldRestoreSPFromFP(true);
384  }
385 
386  // If we need a base pointer, set it up here. It's whatever the value
387  // of the stack pointer is at this point. Any variable size objects
388  // will be allocated after this, so we can still use the base pointer
389  // to reference locals.
390  if (RegInfo->hasBasePointer(MF))
391  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
392  .addReg(ARM::SP)
393  .add(predOps(ARMCC::AL));
394 
395  // If the frame has variable sized objects then the epilogue must restore
396  // the sp from fp. We can assume there's an FP here since hasFP already
397  // checks for hasVarSizedObjects.
398  if (MFI.hasVarSizedObjects())
399  AFI->setShouldRestoreSPFromFP(true);
400 
401  // In some cases, virtual registers have been introduced, e.g. by uses of
402  // emitThumbRegPlusImmInReg.
404 }
405 
406 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
407  if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
408  isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
409  return true;
410  else if (MI.getOpcode() == ARM::tPOP) {
411  return true;
412  } else if (MI.getOpcode() == ARM::tMOVr) {
413  unsigned Dst = MI.getOperand(0).getReg();
414  unsigned Src = MI.getOperand(1).getReg();
415  return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
416  ARM::hGPRRegClass.contains(Dst));
417  }
418  return false;
419 }
420 
422  MachineBasicBlock &MBB) const {
424  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
425  MachineFrameInfo &MFI = MF.getFrameInfo();
427  const ThumbRegisterInfo *RegInfo =
428  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
429  const Thumb1InstrInfo &TII =
430  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
431 
432  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
433  int NumBytes = (int)MFI.getStackSize();
434  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
435  "ArgRegsSaveSize is included in NumBytes");
436  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
437  unsigned FramePtr = RegInfo->getFrameRegister(MF);
438 
439  if (!AFI->hasStackFrame()) {
440  if (NumBytes - ArgRegsSaveSize != 0)
441  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
442  } else {
443  // Unwind MBBI to point to first LDR / VLDRD.
444  if (MBBI != MBB.begin()) {
445  do
446  --MBBI;
447  while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
448  if (!isCSRestore(*MBBI, CSRegs))
449  ++MBBI;
450  }
451 
452  // Move SP to start of FP callee save spill area.
453  NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
456  ArgRegsSaveSize);
457 
458  if (AFI->shouldRestoreSPFromFP()) {
459  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
460  // Reset SP based on frame pointer only if the stack frame extends beyond
461  // frame pointer stack slot, the target is ELF and the function has FP, or
462  // the target uses var sized objects.
463  if (NumBytes) {
464  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
465  "No scratch register to restore SP from FP!");
466  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
467  TII, *RegInfo);
468  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
469  .addReg(ARM::R4)
470  .add(predOps(ARMCC::AL));
471  } else
472  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
473  .addReg(FramePtr)
474  .add(predOps(ARMCC::AL));
475  } else {
476  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
477  &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
478  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
479  if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
480  emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
481  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
482  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
483  }
484  }
485 
486  if (needPopSpecialFixUp(MF)) {
487  bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
488  (void)Done;
489  assert(Done && "Emission of the special fixup failed!?");
490  }
491 }
492 
494  if (!needPopSpecialFixUp(*MBB.getParent()))
495  return true;
496 
497  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
498  return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
499 }
500 
501 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
502  ARMFunctionInfo *AFI =
503  const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
504  if (AFI->getArgRegsSaveSize())
505  return true;
506 
507  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
508  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
509  if (CSI.getReg() == ARM::LR)
510  return true;
511 
512  return false;
513 }
514 
515 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
516  const BitVector &PopFriendly,
517  const LivePhysRegs &UsedRegs, unsigned &PopReg,
518  unsigned &TmpReg) {
519  PopReg = TmpReg = 0;
520  for (auto Reg : GPRsNoLRSP.set_bits()) {
521  if (!UsedRegs.contains(Reg)) {
522  // Remember the first pop-friendly register and exit.
523  if (PopFriendly.test(Reg)) {
524  PopReg = Reg;
525  TmpReg = 0;
526  break;
527  }
528  // Otherwise, remember that the register will be available to
529  // save a pop-friendly register.
530  TmpReg = Reg;
531  }
532  }
533 }
534 
535 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
536  bool DoIt) const {
537  MachineFunction &MF = *MBB.getParent();
539  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
540  const TargetInstrInfo &TII = *STI.getInstrInfo();
541  const ThumbRegisterInfo *RegInfo =
542  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
543 
544  // If MBBI is a return instruction, or is a tPOP followed by a return
545  // instruction in the successor BB, we may be able to directly restore
546  // LR in the PC.
547  // This is only possible with v5T ops (v4T can't change the Thumb bit via
548  // a POP PC instruction), and only if we do not need to emit any SP update.
549  // Otherwise, we need a temporary register to pop the value
550  // and copy that value into LR.
551  auto MBBI = MBB.getFirstTerminator();
552  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
553  if (CanRestoreDirectly) {
554  if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
555  CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
556  MBBI->getOpcode() == ARM::tPOP_RET);
557  else {
558  auto MBBI_prev = MBBI;
559  MBBI_prev--;
560  assert(MBBI_prev->getOpcode() == ARM::tPOP);
561  assert(MBB.succ_size() == 1);
562  if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
563  MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
564  else
565  CanRestoreDirectly = false;
566  }
567  }
568 
569  if (CanRestoreDirectly) {
570  if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
571  return true;
572  MachineInstrBuilder MIB =
573  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
574  .add(predOps(ARMCC::AL));
575  // Copy implicit ops and popped registers, if any.
576  for (auto MO: MBBI->operands())
577  if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
578  MIB.add(MO);
579  MIB.addReg(ARM::PC, RegState::Define);
580  // Erase the old instruction (tBX_RET or tPOP).
581  MBB.erase(MBBI);
582  return true;
583  }
584 
585  // Look for a temporary register to use.
586  // First, compute the liveness information.
587  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
588  LivePhysRegs UsedRegs(TRI);
589  UsedRegs.addLiveOuts(MBB);
590  // The semantic of pristines changed recently and now,
591  // the callee-saved registers that are touched in the function
592  // are not part of the pristines set anymore.
593  // Add those callee-saved now.
594  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
595  for (unsigned i = 0; CSRegs[i]; ++i)
596  UsedRegs.addReg(CSRegs[i]);
597 
598  DebugLoc dl = DebugLoc();
599  if (MBBI != MBB.end()) {
600  dl = MBBI->getDebugLoc();
601  auto InstUpToMBBI = MBB.end();
602  while (InstUpToMBBI != MBBI)
603  // The pre-decrement is on purpose here.
604  // We want to have the liveness right before MBBI.
605  UsedRegs.stepBackward(*--InstUpToMBBI);
606  }
607 
608  // Look for a register that can be directly use in the POP.
609  unsigned PopReg = 0;
610  // And some temporary register, just in case.
611  unsigned TemporaryReg = 0;
612  BitVector PopFriendly =
613  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
614  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
615  // Rebuild the GPRs from the high registers because they are removed
616  // form the GPR reg class for thumb1.
617  BitVector GPRsNoLRSP =
618  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
619  GPRsNoLRSP |= PopFriendly;
620  GPRsNoLRSP.reset(ARM::LR);
621  GPRsNoLRSP.reset(ARM::SP);
622  GPRsNoLRSP.reset(ARM::PC);
623  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
624 
625  // If we couldn't find a pop-friendly register, restore LR before popping the
626  // other callee-saved registers, so we can use one of them as a temporary.
627  bool UseLDRSP = false;
628  if (!PopReg && MBBI != MBB.begin()) {
629  auto PrevMBBI = MBBI;
630  PrevMBBI--;
631  if (PrevMBBI->getOpcode() == ARM::tPOP) {
632  MBBI = PrevMBBI;
633  UsedRegs.stepBackward(*MBBI);
634  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
635  UseLDRSP = true;
636  }
637  }
638 
639  if (!DoIt && !PopReg && !TemporaryReg)
640  return false;
641 
642  assert((PopReg || TemporaryReg) && "Cannot get LR");
643 
644  if (UseLDRSP) {
645  assert(PopReg && "Do not know how to get LR");
646  // Load the LR via LDR tmp, [SP, #off]
647  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
648  .addReg(PopReg, RegState::Define)
649  .addReg(ARM::SP)
650  .addImm(MBBI->getNumOperands() - 3)
651  .add(predOps(ARMCC::AL));
652  // Move from the temporary register to the LR.
653  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
654  .addReg(ARM::LR, RegState::Define)
655  .addReg(PopReg, RegState::Kill)
656  .add(predOps(ARMCC::AL));
657  // Advance past the pop instruction.
658  MBBI++;
659  // Increment the SP.
660  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize + 4);
661  return true;
662  }
663 
664  if (TemporaryReg) {
665  assert(!PopReg && "Unnecessary MOV is about to be inserted");
666  PopReg = PopFriendly.find_first();
667  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
668  .addReg(TemporaryReg, RegState::Define)
669  .addReg(PopReg, RegState::Kill)
670  .add(predOps(ARMCC::AL));
671  }
672 
673  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
674  // We couldn't use the direct restoration above, so
675  // perform the opposite conversion: tPOP_RET to tPOP.
676  MachineInstrBuilder MIB =
677  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
678  .add(predOps(ARMCC::AL));
679  bool Popped = false;
680  for (auto MO: MBBI->operands())
681  if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
682  MO.getReg() != ARM::PC) {
683  MIB.add(MO);
684  if (!MO.isImplicit())
685  Popped = true;
686  }
687  // Is there anything left to pop?
688  if (!Popped)
689  MBB.erase(MIB.getInstr());
690  // Erase the old instruction.
691  MBB.erase(MBBI);
692  MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
693  .add(predOps(ARMCC::AL));
694  }
695 
696  assert(PopReg && "Do not know how to get LR");
697  BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
699  .addReg(PopReg, RegState::Define);
700 
701  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
702 
703  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
704  .addReg(ARM::LR, RegState::Define)
705  .addReg(PopReg, RegState::Kill)
706  .add(predOps(ARMCC::AL));
707 
708  if (TemporaryReg)
709  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
710  .addReg(PopReg, RegState::Define)
711  .addReg(TemporaryReg, RegState::Kill)
712  .add(predOps(ARMCC::AL));
713 
714  return true;
715 }
716 
717 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
718 
719 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
720 // or OrderEnd if no further registers are in that set. This does not advance
721 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
722 static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
723  const ARMRegSet &EnabledRegs,
724  const unsigned *OrderEnd) {
725  while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
726  ++CurrentReg;
727  return CurrentReg;
728 }
729 
733  const std::vector<CalleeSavedInfo> &CSI,
734  const TargetRegisterInfo *TRI) const {
735  if (CSI.empty())
736  return false;
737 
738  DebugLoc DL;
739  const TargetInstrInfo &TII = *STI.getInstrInfo();
740  MachineFunction &MF = *MBB.getParent();
741  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
743 
744  ARMRegSet LoRegsToSave; // r0-r7, lr
745  ARMRegSet HiRegsToSave; // r8-r11
746  ARMRegSet CopyRegs; // Registers which can be used after pushing
747  // LoRegs for saving HiRegs.
748 
749  for (unsigned i = CSI.size(); i != 0; --i) {
750  unsigned Reg = CSI[i-1].getReg();
751 
752  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
753  LoRegsToSave[Reg] = true;
754  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
755  HiRegsToSave[Reg] = true;
756  } else {
757  llvm_unreachable("callee-saved register of unexpected class");
758  }
759 
760  if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
761  !MF.getRegInfo().isLiveIn(Reg) &&
762  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
763  CopyRegs[Reg] = true;
764  }
765 
766  // Unused argument registers can be used for the high register saving.
767  for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
768  if (!MF.getRegInfo().isLiveIn(ArgReg))
769  CopyRegs[ArgReg] = true;
770 
771  // Push the low registers and lr
772  const MachineRegisterInfo &MRI = MF.getRegInfo();
773  if (!LoRegsToSave.none()) {
774  MachineInstrBuilder MIB =
775  BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
776  for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
777  if (LoRegsToSave[Reg]) {
778  bool isKill = !MRI.isLiveIn(Reg);
779  if (isKill && !MRI.isReserved(Reg))
780  MBB.addLiveIn(Reg);
781 
782  MIB.addReg(Reg, getKillRegState(isKill));
783  }
784  }
786  }
787 
788  // Push the high registers. There are no store instructions that can access
789  // these registers directly, so we have to move them to low registers, and
790  // push them. This might take multiple pushes, as it is possible for there to
791  // be fewer low registers available than high registers which need saving.
792 
793  // These are in reverse order so that in the case where we need to use
794  // multiple PUSH instructions, the order of the registers on the stack still
795  // matches the unwind info. They need to be swicthed back to ascending order
796  // before adding to the PUSH instruction.
797  static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
798  ARM::R5, ARM::R4, ARM::R3,
799  ARM::R2, ARM::R1, ARM::R0};
800  static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
801 
802  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
803  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
804 
805  // Find the first register to save.
806  const unsigned *HiRegToSave = findNextOrderedReg(
807  std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
808 
809  while (HiRegToSave != AllHighRegsEnd) {
810  // Find the first low register to use.
811  const unsigned *CopyReg =
812  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
813 
814  // Create the PUSH, but don't insert it yet (the MOVs need to come first).
815  MachineInstrBuilder PushMIB =
816  BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
817 
818  SmallVector<unsigned, 4> RegsToPush;
819  while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
820  if (HiRegsToSave[*HiRegToSave]) {
821  bool isKill = !MRI.isLiveIn(*HiRegToSave);
822  if (isKill && !MRI.isReserved(*HiRegToSave))
823  MBB.addLiveIn(*HiRegToSave);
824 
825  // Emit a MOV from the high reg to the low reg.
826  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
827  .addReg(*CopyReg, RegState::Define)
828  .addReg(*HiRegToSave, getKillRegState(isKill))
829  .add(predOps(ARMCC::AL));
830 
831  // Record the register that must be added to the PUSH.
832  RegsToPush.push_back(*CopyReg);
833 
834  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
835  HiRegToSave =
836  findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
837  }
838  }
839 
840  // Add the low registers to the PUSH, in ascending order.
841  for (unsigned Reg : llvm::reverse(RegsToPush))
842  PushMIB.addReg(Reg, RegState::Kill);
843 
844  // Insert the PUSH instruction after the MOVs.
845  MBB.insert(MI, PushMIB);
846  }
847 
848  return true;
849 }
850 
854  std::vector<CalleeSavedInfo> &CSI,
855  const TargetRegisterInfo *TRI) const {
856  if (CSI.empty())
857  return false;
858 
859  MachineFunction &MF = *MBB.getParent();
861  const TargetInstrInfo &TII = *STI.getInstrInfo();
862  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
864 
865  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
866  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
867 
868  ARMRegSet LoRegsToRestore;
869  ARMRegSet HiRegsToRestore;
870  // Low registers (r0-r7) which can be used to restore the high registers.
871  ARMRegSet CopyRegs;
872 
873  for (CalleeSavedInfo I : CSI) {
874  unsigned Reg = I.getReg();
875 
876  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
877  LoRegsToRestore[Reg] = true;
878  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
879  HiRegsToRestore[Reg] = true;
880  } else {
881  llvm_unreachable("callee-saved register of unexpected class");
882  }
883 
884  // If this is a low register not used as the frame pointer, we may want to
885  // use it for restoring the high registers.
886  if ((ARM::tGPRRegClass.contains(Reg)) &&
887  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
888  CopyRegs[Reg] = true;
889  }
890 
891  // If this is a return block, we may be able to use some unused return value
892  // registers for restoring the high regs.
893  auto Terminator = MBB.getFirstTerminator();
894  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
895  CopyRegs[ARM::R0] = true;
896  CopyRegs[ARM::R1] = true;
897  CopyRegs[ARM::R2] = true;
898  CopyRegs[ARM::R3] = true;
899  for (auto Op : Terminator->implicit_operands()) {
900  if (Op.isReg())
901  CopyRegs[Op.getReg()] = false;
902  }
903  }
904 
905  static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
906  ARM::R4, ARM::R5, ARM::R6, ARM::R7};
907  static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
908 
909  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
910  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
911 
912  // Find the first register to restore.
913  auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
914  HiRegsToRestore, AllHighRegsEnd);
915 
916  while (HiRegToRestore != AllHighRegsEnd) {
917  assert(!CopyRegs.none());
918  // Find the first low register to use.
919  auto CopyReg =
920  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
921 
922  // Create the POP instruction.
923  MachineInstrBuilder PopMIB =
924  BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
925 
926  while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
927  // Add the low register to the POP.
928  PopMIB.addReg(*CopyReg, RegState::Define);
929 
930  // Create the MOV from low to high register.
931  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
932  .addReg(*HiRegToRestore, RegState::Define)
933  .addReg(*CopyReg, RegState::Kill)
934  .add(predOps(ARMCC::AL));
935 
936  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
937  HiRegToRestore =
938  findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
939  }
940  }
941 
942  MachineInstrBuilder MIB =
943  BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
944 
945  bool NeedsPop = false;
946  for (unsigned i = CSI.size(); i != 0; --i) {
947  CalleeSavedInfo &Info = CSI[i-1];
948  unsigned Reg = Info.getReg();
949 
950  // High registers (excluding lr) have already been dealt with
951  if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
952  continue;
953 
954  if (Reg == ARM::LR) {
955  Info.setRestored(false);
956  if (!MBB.succ_empty() ||
957  MI->getOpcode() == ARM::TCRETURNdi ||
958  MI->getOpcode() == ARM::TCRETURNri)
959  // LR may only be popped into PC, as part of return sequence.
960  // If this isn't the return sequence, we'll need emitPopSpecialFixUp
961  // to restore LR the hard way.
962  // FIXME: if we don't pass any stack arguments it would be actually
963  // advantageous *and* correct to do the conversion to an ordinary call
964  // instruction here.
965  continue;
966  // Special epilogue for vararg functions. See emitEpilogue
967  if (isVarArg)
968  continue;
969  // ARMv4T requires BX, see emitEpilogue
970  if (!STI.hasV5TOps())
971  continue;
972 
973  // Pop LR into PC.
974  Reg = ARM::PC;
975  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
976  if (MI != MBB.end())
977  MIB.copyImplicitOps(*MI);
978  MI = MBB.erase(MI);
979  }
980  MIB.addReg(Reg, getDefRegState(true));
981  NeedsPop = true;
982  }
983 
984  // It's illegal to emit pop instruction without operands.
985  if (NeedsPop)
986  MBB.insert(MI, &*MIB);
987  else
988  MF.DeleteMachineInstr(MIB);
989 
990  return true;
991 }
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
const MachineInstrBuilder & add(const MachineOperand &MO) const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:244
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
#define R4(n)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:235
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineFunctionProperties & reset(Property P)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:404
bool test(unsigned Idx) const
Definition: BitVector.h:502
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
A debug info location.
Definition: DebugLoc.h:34
MachineModuleInfo & getMMI() const
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:677
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
#define R2(n)
void setGPRCalleeSavedArea2Offset(unsigned o)
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:391
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
return AArch64::GPR64RegClass contains(Reg)
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:455
bool isTargetELF() const
Definition: ARMSubtarget.h:611
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool contains(unsigned Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:106
static void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
const HexagonInstrInfo * TII
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
Thumb1FrameLowering(const ARMSubtarget &sti)
unsigned getFrameRegister(const MachineFunction &MF) const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
void setDPRCalleeSavedAreaOffset(unsigned o)
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
unsigned getArgRegsSaveSize() const
void setFramePtrSpillOffset(unsigned o)
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:232
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
unsigned getDPRCalleeSavedAreaSize() const
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:693
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:377
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:384
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:181
unsigned getGPRCalleeSavedArea1Size() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
BitVector & reset()
Definition: BitVector.h:439
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasBasePointer(const MachineFunction &MF) const
void setGPRCalleeSavedArea2Size(unsigned s)
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define R6(n)
void setGPRCalleeSavedArea1Size(unsigned s)
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs)
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
std::bitset< ARM::NUM_TARGET_REGS > ARMRegSet
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
unsigned succ_size() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getGPRCalleeSavedArea2Size() const
void setGPRCalleeSavedArea1Offset(unsigned o)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:49
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:467
static const unsigned * findNextOrderedReg(const unsigned *CurrentReg, const ARMRegSet &EnabledRegs, const unsigned *OrderEnd)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
void setDPRCalleeSavedAreaSize(unsigned s)
int getOffsetAdjustment() const
Return the correction for frame offsets.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasV5TOps() const
Definition: ARMSubtarget.h:498
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
unsigned getFramePtrSpillOffset() const
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
static const unsigned FramePtr
static void findTemporariesForLR(const BitVector &GPRsNoLRSP, const BitVector &PopFriendly, const LivePhysRegs &UsedRegs, unsigned &PopReg, unsigned &TmpReg)
IRTranslator LLVM IR MI
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
const ARMSubtarget & STI
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
unsigned getReg() const
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
This class contains meta information specific to a module.
void addReg(unsigned Reg)
Adds a physical register and all its sub-registers to the set.
Definition: LivePhysRegs.h:79