LLVM  9.0.0svn
Thumb1FrameLowering.cpp
Go to the documentation of this file.
1 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb1 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb1FrameLowering.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMSubtarget.h"
18 #include "Thumb1InstrInfo.h"
19 #include "ThumbRegisterInfo.h"
20 #include "Utils/ARMBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/DebugLoc.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCDwarf.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/Compiler.h"
43 #include <bitset>
44 #include <cassert>
45 #include <iterator>
46 #include <vector>
47 
48 using namespace llvm;
49 
51  : ARMFrameLowering(sti) {}
52 
54  const MachineFrameInfo &MFI = MF.getFrameInfo();
55  unsigned CFSize = MFI.getMaxCallFrameSize();
56  // It's not always a good idea to include the call frame as part of the
57  // stack frame. ARM (especially Thumb) has small immediate offset to
58  // address the stack frame. So a large call frame can cause poor codegen
59  // and may even makes it impossible to scavenge a register.
60  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
61  return false;
62 
63  return !MFI.hasVarSizedObjects();
64 }
65 
68  const TargetInstrInfo &TII, const DebugLoc &dl,
69  const ThumbRegisterInfo &MRI, int NumBytes,
70  unsigned MIFlags = MachineInstr::NoFlags) {
71  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
72  MRI, MIFlags);
73 }
74 
78  const Thumb1InstrInfo &TII =
79  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
80  const ThumbRegisterInfo *RegInfo =
81  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
82  if (!hasReservedCallFrame(MF)) {
83  // If we have alloca, convert as follows:
84  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
85  // ADJCALLSTACKUP -> add, sp, sp, amount
86  MachineInstr &Old = *I;
87  DebugLoc dl = Old.getDebugLoc();
88  unsigned Amount = TII.getFrameSize(Old);
89  if (Amount != 0) {
90  // We need to keep the stack aligned properly. To do this, we round the
91  // amount of space needed for the outgoing arguments up to the next
92  // alignment boundary.
93  Amount = alignTo(Amount, getStackAlignment());
94 
95  // Replace the pseudo instruction with a new instruction...
96  unsigned Opc = Old.getOpcode();
97  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
98  emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
99  } else {
100  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
101  emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
102  }
103  }
104  }
105  return MBB.erase(I);
106 }
107 
109  MachineBasicBlock &MBB) const {
110  MachineBasicBlock::iterator MBBI = MBB.begin();
111  MachineFrameInfo &MFI = MF.getFrameInfo();
113  MachineModuleInfo &MMI = MF.getMMI();
114  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
115  const ThumbRegisterInfo *RegInfo =
116  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
117  const Thumb1InstrInfo &TII =
118  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
119 
120  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
121  unsigned NumBytes = MFI.getStackSize();
122  assert(NumBytes >= ArgRegsSaveSize &&
123  "ArgRegsSaveSize is included in NumBytes");
124  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
125 
126  // Debug location must be unknown since the first debug location is used
127  // to determine the end of the prologue.
128  DebugLoc dl;
129 
130  unsigned FramePtr = RegInfo->getFrameRegister(MF);
131  unsigned BasePtr = RegInfo->getBaseRegister();
132  int CFAOffset = 0;
133 
134  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
135  NumBytes = (NumBytes + 3) & ~3;
136  MFI.setStackSize(NumBytes);
137 
138  // Determine the sizes of each callee-save spill areas and record which frame
139  // belongs to which callee-save spill areas.
140  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
141  int FramePtrSpillFI = 0;
142 
143  if (ArgRegsSaveSize) {
144  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
146  CFAOffset -= ArgRegsSaveSize;
147  unsigned CFIIndex = MF.addFrameInst(
148  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
149  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
150  .addCFIIndex(CFIIndex)
152  }
153 
154  if (!AFI->hasStackFrame()) {
155  if (NumBytes - ArgRegsSaveSize != 0) {
156  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
158  CFAOffset -= NumBytes - ArgRegsSaveSize;
159  unsigned CFIIndex = MF.addFrameInst(
160  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
161  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
162  .addCFIIndex(CFIIndex)
164  }
165  return;
166  }
167 
168  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
169  unsigned Reg = CSI[i].getReg();
170  int FI = CSI[i].getFrameIdx();
171  switch (Reg) {
172  case ARM::R8:
173  case ARM::R9:
174  case ARM::R10:
175  case ARM::R11:
176  if (STI.splitFramePushPop(MF)) {
177  GPRCS2Size += 4;
178  break;
179  }
181  case ARM::R4:
182  case ARM::R5:
183  case ARM::R6:
184  case ARM::R7:
185  case ARM::LR:
186  if (Reg == FramePtr)
187  FramePtrSpillFI = FI;
188  GPRCS1Size += 4;
189  break;
190  default:
191  DPRCSSize += 8;
192  }
193  }
194 
195  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
196  ++MBBI;
197  }
198 
199  // Determine starting offsets of spill areas.
200  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
201  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
202  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
203  bool HasFP = hasFP(MF);
204  if (HasFP)
205  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
206  NumBytes);
207  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
208  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
209  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
210  NumBytes = DPRCSOffset;
211 
212  int FramePtrOffsetInBlock = 0;
213  unsigned adjustedGPRCS1Size = GPRCS1Size;
214  if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
215  tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
216  FramePtrOffsetInBlock = NumBytes;
217  adjustedGPRCS1Size += NumBytes;
218  NumBytes = 0;
219  }
220 
221  if (adjustedGPRCS1Size) {
222  CFAOffset -= adjustedGPRCS1Size;
223  unsigned CFIIndex = MF.addFrameInst(
224  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
225  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
226  .addCFIIndex(CFIIndex)
228  }
229  for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
230  E = CSI.end(); I != E; ++I) {
231  unsigned Reg = I->getReg();
232  int FI = I->getFrameIdx();
233  switch (Reg) {
234  case ARM::R8:
235  case ARM::R9:
236  case ARM::R10:
237  case ARM::R11:
238  case ARM::R12:
239  if (STI.splitFramePushPop(MF))
240  break;
242  case ARM::R0:
243  case ARM::R1:
244  case ARM::R2:
245  case ARM::R3:
246  case ARM::R4:
247  case ARM::R5:
248  case ARM::R6:
249  case ARM::R7:
250  case ARM::LR:
251  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
252  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
253  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
254  .addCFIIndex(CFIIndex)
256  break;
257  }
258  }
259 
260  // Adjust FP so it point to the stack slot that contains the previous FP.
261  if (HasFP) {
262  FramePtrOffsetInBlock +=
263  MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
264  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
265  .addReg(ARM::SP)
266  .addImm(FramePtrOffsetInBlock / 4)
268  .add(predOps(ARMCC::AL));
269  if(FramePtrOffsetInBlock) {
270  CFAOffset += FramePtrOffsetInBlock;
271  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
272  nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
273  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
274  .addCFIIndex(CFIIndex)
276  } else {
277  unsigned CFIIndex =
279  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
280  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
281  .addCFIIndex(CFIIndex)
283  }
284  if (NumBytes > 508)
285  // If offset is > 508 then sp cannot be adjusted in a single instruction,
286  // try restoring from fp instead.
287  AFI->setShouldRestoreSPFromFP(true);
288  }
289 
290  // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
291  // and tMOVr instructions. We don't need to add any call frame information
292  // in-between these instructions, because they do not modify the high
293  // registers.
294  while (true) {
295  MachineBasicBlock::iterator OldMBBI = MBBI;
296  // Skip a run of tMOVr instructions
297  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
298  MBBI++;
299  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
300  MBBI++;
301  } else {
302  // We have reached an instruction which is not a push, so the previous
303  // run of tMOVr instructions (which may have been empty) was not part of
304  // the prologue. Reset MBBI back to the last PUSH of the prologue.
305  MBBI = OldMBBI;
306  break;
307  }
308  }
309 
310  // Emit call frame information for the callee-saved high registers.
311  for (auto &I : CSI) {
312  unsigned Reg = I.getReg();
313  int FI = I.getFrameIdx();
314  switch (Reg) {
315  case ARM::R8:
316  case ARM::R9:
317  case ARM::R10:
318  case ARM::R11:
319  case ARM::R12: {
320  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
321  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
322  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
323  .addCFIIndex(CFIIndex)
325  break;
326  }
327  default:
328  break;
329  }
330  }
331 
332  if (NumBytes) {
333  // Insert it after all the callee-save spills.
334  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
336  if (!HasFP) {
337  CFAOffset -= NumBytes;
338  unsigned CFIIndex = MF.addFrameInst(
339  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
340  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
341  .addCFIIndex(CFIIndex)
343  }
344  }
345 
346  if (STI.isTargetELF() && HasFP)
348  AFI->getFramePtrSpillOffset());
349 
350  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
351  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
352  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
353 
354  if (RegInfo->needsStackRealignment(MF)) {
355  const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
356  // Emit the following sequence, using R4 as a temporary, since we cannot use
357  // SP as a source or destination register for the shifts:
358  // mov r4, sp
359  // lsrs r4, r4, #NrBitsToZero
360  // lsls r4, r4, #NrBitsToZero
361  // mov sp, r4
362  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
363  .addReg(ARM::SP, RegState::Kill)
364  .add(predOps(ARMCC::AL));
365 
366  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
367  .addDef(ARM::CPSR)
369  .addImm(NrBitsToZero)
370  .add(predOps(ARMCC::AL));
371 
372  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
373  .addDef(ARM::CPSR)
375  .addImm(NrBitsToZero)
376  .add(predOps(ARMCC::AL));
377 
378  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
379  .addReg(ARM::R4, RegState::Kill)
380  .add(predOps(ARMCC::AL));
381 
382  AFI->setShouldRestoreSPFromFP(true);
383  }
384 
385  // If we need a base pointer, set it up here. It's whatever the value
386  // of the stack pointer is at this point. Any variable size objects
387  // will be allocated after this, so we can still use the base pointer
388  // to reference locals.
389  if (RegInfo->hasBasePointer(MF))
390  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
391  .addReg(ARM::SP)
392  .add(predOps(ARMCC::AL));
393 
394  // If the frame has variable sized objects then the epilogue must restore
395  // the sp from fp. We can assume there's an FP here since hasFP already
396  // checks for hasVarSizedObjects.
397  if (MFI.hasVarSizedObjects())
398  AFI->setShouldRestoreSPFromFP(true);
399 
400  // In some cases, virtual registers have been introduced, e.g. by uses of
401  // emitThumbRegPlusImmInReg.
403 }
404 
405 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
406  if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
407  isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
408  return true;
409  else if (MI.getOpcode() == ARM::tPOP) {
410  return true;
411  } else if (MI.getOpcode() == ARM::tMOVr) {
412  unsigned Dst = MI.getOperand(0).getReg();
413  unsigned Src = MI.getOperand(1).getReg();
414  return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
415  ARM::hGPRRegClass.contains(Dst));
416  }
417  return false;
418 }
419 
421  MachineBasicBlock &MBB) const {
423  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
424  MachineFrameInfo &MFI = MF.getFrameInfo();
426  const ThumbRegisterInfo *RegInfo =
427  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
428  const Thumb1InstrInfo &TII =
429  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
430 
431  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
432  int NumBytes = (int)MFI.getStackSize();
433  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
434  "ArgRegsSaveSize is included in NumBytes");
435  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
436  unsigned FramePtr = RegInfo->getFrameRegister(MF);
437 
438  if (!AFI->hasStackFrame()) {
439  if (NumBytes - ArgRegsSaveSize != 0)
440  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
441  } else {
442  // Unwind MBBI to point to first LDR / VLDRD.
443  if (MBBI != MBB.begin()) {
444  do
445  --MBBI;
446  while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
447  if (!isCSRestore(*MBBI, CSRegs))
448  ++MBBI;
449  }
450 
451  // Move SP to start of FP callee save spill area.
452  NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
455  ArgRegsSaveSize);
456 
457  if (AFI->shouldRestoreSPFromFP()) {
458  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
459  // Reset SP based on frame pointer only if the stack frame extends beyond
460  // frame pointer stack slot, the target is ELF and the function has FP, or
461  // the target uses var sized objects.
462  if (NumBytes) {
463  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
464  "No scratch register to restore SP from FP!");
465  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
466  TII, *RegInfo);
467  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
468  .addReg(ARM::R4)
469  .add(predOps(ARMCC::AL));
470  } else
471  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
472  .addReg(FramePtr)
473  .add(predOps(ARMCC::AL));
474  } else {
475  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
476  &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
477  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
478  if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
479  emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
480  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
481  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
482  }
483  }
484 
485  if (needPopSpecialFixUp(MF)) {
486  bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
487  (void)Done;
488  assert(Done && "Emission of the special fixup failed!?");
489  }
490 }
491 
493  if (!needPopSpecialFixUp(*MBB.getParent()))
494  return true;
495 
496  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
497  return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
498 }
499 
500 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
501  ARMFunctionInfo *AFI =
502  const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
503  if (AFI->getArgRegsSaveSize())
504  return true;
505 
506  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
507  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
508  if (CSI.getReg() == ARM::LR)
509  return true;
510 
511  return false;
512 }
513 
514 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
515  const BitVector &PopFriendly,
516  const LivePhysRegs &UsedRegs, unsigned &PopReg,
517  unsigned &TmpReg) {
518  PopReg = TmpReg = 0;
519  for (auto Reg : GPRsNoLRSP.set_bits()) {
520  if (!UsedRegs.contains(Reg)) {
521  // Remember the first pop-friendly register and exit.
522  if (PopFriendly.test(Reg)) {
523  PopReg = Reg;
524  TmpReg = 0;
525  break;
526  }
527  // Otherwise, remember that the register will be available to
528  // save a pop-friendly register.
529  TmpReg = Reg;
530  }
531  }
532 }
533 
534 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
535  bool DoIt) const {
536  MachineFunction &MF = *MBB.getParent();
538  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
539  const TargetInstrInfo &TII = *STI.getInstrInfo();
540  const ThumbRegisterInfo *RegInfo =
541  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
542 
543  // If MBBI is a return instruction, or is a tPOP followed by a return
544  // instruction in the successor BB, we may be able to directly restore
545  // LR in the PC.
546  // This is only possible with v5T ops (v4T can't change the Thumb bit via
547  // a POP PC instruction), and only if we do not need to emit any SP update.
548  // Otherwise, we need a temporary register to pop the value
549  // and copy that value into LR.
550  auto MBBI = MBB.getFirstTerminator();
551  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
552  if (CanRestoreDirectly) {
553  if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
554  CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
555  MBBI->getOpcode() == ARM::tPOP_RET);
556  else {
557  auto MBBI_prev = MBBI;
558  MBBI_prev--;
559  assert(MBBI_prev->getOpcode() == ARM::tPOP);
560  assert(MBB.succ_size() == 1);
561  if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
562  MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
563  else
564  CanRestoreDirectly = false;
565  }
566  }
567 
568  if (CanRestoreDirectly) {
569  if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
570  return true;
571  MachineInstrBuilder MIB =
572  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
573  .add(predOps(ARMCC::AL));
574  // Copy implicit ops and popped registers, if any.
575  for (auto MO: MBBI->operands())
576  if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
577  MIB.add(MO);
578  MIB.addReg(ARM::PC, RegState::Define);
579  // Erase the old instruction (tBX_RET or tPOP).
580  MBB.erase(MBBI);
581  return true;
582  }
583 
584  // Look for a temporary register to use.
585  // First, compute the liveness information.
587  LivePhysRegs UsedRegs(TRI);
588  UsedRegs.addLiveOuts(MBB);
589  // The semantic of pristines changed recently and now,
590  // the callee-saved registers that are touched in the function
591  // are not part of the pristines set anymore.
592  // Add those callee-saved now.
593  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
594  for (unsigned i = 0; CSRegs[i]; ++i)
595  UsedRegs.addReg(CSRegs[i]);
596 
597  DebugLoc dl = DebugLoc();
598  if (MBBI != MBB.end()) {
599  dl = MBBI->getDebugLoc();
600  auto InstUpToMBBI = MBB.end();
601  while (InstUpToMBBI != MBBI)
602  // The pre-decrement is on purpose here.
603  // We want to have the liveness right before MBBI.
604  UsedRegs.stepBackward(*--InstUpToMBBI);
605  }
606 
607  // Look for a register that can be directly use in the POP.
608  unsigned PopReg = 0;
609  // And some temporary register, just in case.
610  unsigned TemporaryReg = 0;
611  BitVector PopFriendly =
612  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
613  // R7 may be used as a frame pointer, hence marked as not generally
614  // allocatable, however there's no reason to not use it as a temporary for
615  // restoring LR.
616  if (STI.useR7AsFramePointer())
617  PopFriendly.set(ARM::R7);
618 
619  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
620  // Rebuild the GPRs from the high registers because they are removed
621  // form the GPR reg class for thumb1.
622  BitVector GPRsNoLRSP =
623  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
624  GPRsNoLRSP |= PopFriendly;
625  GPRsNoLRSP.reset(ARM::LR);
626  GPRsNoLRSP.reset(ARM::SP);
627  GPRsNoLRSP.reset(ARM::PC);
628  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
629 
630  // If we couldn't find a pop-friendly register, try restoring LR before
631  // popping the other callee-saved registers, so we could use one of them as a
632  // temporary.
633  bool UseLDRSP = false;
634  if (!PopReg && MBBI != MBB.begin()) {
635  auto PrevMBBI = MBBI;
636  PrevMBBI--;
637  if (PrevMBBI->getOpcode() == ARM::tPOP) {
638  UsedRegs.stepBackward(*PrevMBBI);
639  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
640  if (PopReg) {
641  MBBI = PrevMBBI;
642  UseLDRSP = true;
643  }
644  }
645  }
646 
647  if (!DoIt && !PopReg && !TemporaryReg)
648  return false;
649 
650  assert((PopReg || TemporaryReg) && "Cannot get LR");
651 
652  if (UseLDRSP) {
653  assert(PopReg && "Do not know how to get LR");
654  // Load the LR via LDR tmp, [SP, #off]
655  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
656  .addReg(PopReg, RegState::Define)
657  .addReg(ARM::SP)
658  .addImm(MBBI->getNumExplicitOperands() - 2)
659  .add(predOps(ARMCC::AL));
660  // Move from the temporary register to the LR.
661  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
662  .addReg(ARM::LR, RegState::Define)
663  .addReg(PopReg, RegState::Kill)
664  .add(predOps(ARMCC::AL));
665  // Advance past the pop instruction.
666  MBBI++;
667  // Increment the SP.
668  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize + 4);
669  return true;
670  }
671 
672  if (TemporaryReg) {
673  assert(!PopReg && "Unnecessary MOV is about to be inserted");
674  PopReg = PopFriendly.find_first();
675  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
676  .addReg(TemporaryReg, RegState::Define)
677  .addReg(PopReg, RegState::Kill)
678  .add(predOps(ARMCC::AL));
679  }
680 
681  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
682  // We couldn't use the direct restoration above, so
683  // perform the opposite conversion: tPOP_RET to tPOP.
684  MachineInstrBuilder MIB =
685  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
686  .add(predOps(ARMCC::AL));
687  bool Popped = false;
688  for (auto MO: MBBI->operands())
689  if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
690  MO.getReg() != ARM::PC) {
691  MIB.add(MO);
692  if (!MO.isImplicit())
693  Popped = true;
694  }
695  // Is there anything left to pop?
696  if (!Popped)
697  MBB.erase(MIB.getInstr());
698  // Erase the old instruction.
699  MBB.erase(MBBI);
700  MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
701  .add(predOps(ARMCC::AL));
702  }
703 
704  assert(PopReg && "Do not know how to get LR");
705  BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
707  .addReg(PopReg, RegState::Define);
708 
709  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
710 
711  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
712  .addReg(ARM::LR, RegState::Define)
713  .addReg(PopReg, RegState::Kill)
714  .add(predOps(ARMCC::AL));
715 
716  if (TemporaryReg)
717  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
718  .addReg(PopReg, RegState::Define)
719  .addReg(TemporaryReg, RegState::Kill)
720  .add(predOps(ARMCC::AL));
721 
722  return true;
723 }
724 
725 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
726 
727 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
728 // or OrderEnd if no further registers are in that set. This does not advance
729 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
730 static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
731  const ARMRegSet &EnabledRegs,
732  const unsigned *OrderEnd) {
733  while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
734  ++CurrentReg;
735  return CurrentReg;
736 }
737 
741  const std::vector<CalleeSavedInfo> &CSI,
742  const TargetRegisterInfo *TRI) const {
743  if (CSI.empty())
744  return false;
745 
746  DebugLoc DL;
747  const TargetInstrInfo &TII = *STI.getInstrInfo();
748  MachineFunction &MF = *MBB.getParent();
749  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
751 
752  ARMRegSet LoRegsToSave; // r0-r7, lr
753  ARMRegSet HiRegsToSave; // r8-r11
754  ARMRegSet CopyRegs; // Registers which can be used after pushing
755  // LoRegs for saving HiRegs.
756 
757  for (unsigned i = CSI.size(); i != 0; --i) {
758  unsigned Reg = CSI[i-1].getReg();
759 
760  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
761  LoRegsToSave[Reg] = true;
762  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
763  HiRegsToSave[Reg] = true;
764  } else {
765  llvm_unreachable("callee-saved register of unexpected class");
766  }
767 
768  if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
769  !MF.getRegInfo().isLiveIn(Reg) &&
770  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
771  CopyRegs[Reg] = true;
772  }
773 
774  // Unused argument registers can be used for the high register saving.
775  for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
776  if (!MF.getRegInfo().isLiveIn(ArgReg))
777  CopyRegs[ArgReg] = true;
778 
779  // Push the low registers and lr
780  const MachineRegisterInfo &MRI = MF.getRegInfo();
781  if (!LoRegsToSave.none()) {
782  MachineInstrBuilder MIB =
783  BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
784  for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
785  if (LoRegsToSave[Reg]) {
786  bool isKill = !MRI.isLiveIn(Reg);
787  if (isKill && !MRI.isReserved(Reg))
788  MBB.addLiveIn(Reg);
789 
790  MIB.addReg(Reg, getKillRegState(isKill));
791  }
792  }
794  }
795 
796  // Push the high registers. There are no store instructions that can access
797  // these registers directly, so we have to move them to low registers, and
798  // push them. This might take multiple pushes, as it is possible for there to
799  // be fewer low registers available than high registers which need saving.
800 
801  // These are in reverse order so that in the case where we need to use
802  // multiple PUSH instructions, the order of the registers on the stack still
803  // matches the unwind info. They need to be swicthed back to ascending order
804  // before adding to the PUSH instruction.
805  static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
806  ARM::R5, ARM::R4, ARM::R3,
807  ARM::R2, ARM::R1, ARM::R0};
808  static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
809 
810  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
811  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
812 
813  // Find the first register to save.
814  const unsigned *HiRegToSave = findNextOrderedReg(
815  std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
816 
817  while (HiRegToSave != AllHighRegsEnd) {
818  // Find the first low register to use.
819  const unsigned *CopyReg =
820  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
821 
822  // Create the PUSH, but don't insert it yet (the MOVs need to come first).
823  MachineInstrBuilder PushMIB =
824  BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
825 
826  SmallVector<unsigned, 4> RegsToPush;
827  while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
828  if (HiRegsToSave[*HiRegToSave]) {
829  bool isKill = !MRI.isLiveIn(*HiRegToSave);
830  if (isKill && !MRI.isReserved(*HiRegToSave))
831  MBB.addLiveIn(*HiRegToSave);
832 
833  // Emit a MOV from the high reg to the low reg.
834  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
835  .addReg(*CopyReg, RegState::Define)
836  .addReg(*HiRegToSave, getKillRegState(isKill))
837  .add(predOps(ARMCC::AL));
838 
839  // Record the register that must be added to the PUSH.
840  RegsToPush.push_back(*CopyReg);
841 
842  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
843  HiRegToSave =
844  findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
845  }
846  }
847 
848  // Add the low registers to the PUSH, in ascending order.
849  for (unsigned Reg : llvm::reverse(RegsToPush))
850  PushMIB.addReg(Reg, RegState::Kill);
851 
852  // Insert the PUSH instruction after the MOVs.
853  MBB.insert(MI, PushMIB);
854  }
855 
856  return true;
857 }
858 
862  std::vector<CalleeSavedInfo> &CSI,
863  const TargetRegisterInfo *TRI) const {
864  if (CSI.empty())
865  return false;
866 
867  MachineFunction &MF = *MBB.getParent();
869  const TargetInstrInfo &TII = *STI.getInstrInfo();
870  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
872 
873  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
874  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
875 
876  ARMRegSet LoRegsToRestore;
877  ARMRegSet HiRegsToRestore;
878  // Low registers (r0-r7) which can be used to restore the high registers.
879  ARMRegSet CopyRegs;
880 
881  for (CalleeSavedInfo I : CSI) {
882  unsigned Reg = I.getReg();
883 
884  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
885  LoRegsToRestore[Reg] = true;
886  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
887  HiRegsToRestore[Reg] = true;
888  } else {
889  llvm_unreachable("callee-saved register of unexpected class");
890  }
891 
892  // If this is a low register not used as the frame pointer, we may want to
893  // use it for restoring the high registers.
894  if ((ARM::tGPRRegClass.contains(Reg)) &&
895  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
896  CopyRegs[Reg] = true;
897  }
898 
899  // If this is a return block, we may be able to use some unused return value
900  // registers for restoring the high regs.
901  auto Terminator = MBB.getFirstTerminator();
902  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
903  CopyRegs[ARM::R0] = true;
904  CopyRegs[ARM::R1] = true;
905  CopyRegs[ARM::R2] = true;
906  CopyRegs[ARM::R3] = true;
907  for (auto Op : Terminator->implicit_operands()) {
908  if (Op.isReg())
909  CopyRegs[Op.getReg()] = false;
910  }
911  }
912 
913  static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
914  ARM::R4, ARM::R5, ARM::R6, ARM::R7};
915  static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
916 
917  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
918  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
919 
920  // Find the first register to restore.
921  auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
922  HiRegsToRestore, AllHighRegsEnd);
923 
924  while (HiRegToRestore != AllHighRegsEnd) {
925  assert(!CopyRegs.none());
926  // Find the first low register to use.
927  auto CopyReg =
928  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
929 
930  // Create the POP instruction.
931  MachineInstrBuilder PopMIB =
932  BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
933 
934  while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
935  // Add the low register to the POP.
936  PopMIB.addReg(*CopyReg, RegState::Define);
937 
938  // Create the MOV from low to high register.
939  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
940  .addReg(*HiRegToRestore, RegState::Define)
941  .addReg(*CopyReg, RegState::Kill)
942  .add(predOps(ARMCC::AL));
943 
944  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
945  HiRegToRestore =
946  findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
947  }
948  }
949 
950  MachineInstrBuilder MIB =
951  BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
952 
953  bool NeedsPop = false;
954  for (unsigned i = CSI.size(); i != 0; --i) {
955  CalleeSavedInfo &Info = CSI[i-1];
956  unsigned Reg = Info.getReg();
957 
958  // High registers (excluding lr) have already been dealt with
959  if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
960  continue;
961 
962  if (Reg == ARM::LR) {
963  Info.setRestored(false);
964  if (!MBB.succ_empty() ||
965  MI->getOpcode() == ARM::TCRETURNdi ||
966  MI->getOpcode() == ARM::TCRETURNri)
967  // LR may only be popped into PC, as part of return sequence.
968  // If this isn't the return sequence, we'll need emitPopSpecialFixUp
969  // to restore LR the hard way.
970  // FIXME: if we don't pass any stack arguments it would be actually
971  // advantageous *and* correct to do the conversion to an ordinary call
972  // instruction here.
973  continue;
974  // Special epilogue for vararg functions. See emitEpilogue
975  if (isVarArg)
976  continue;
977  // ARMv4T requires BX, see emitEpilogue
978  if (!STI.hasV5TOps())
979  continue;
980 
981  // Pop LR into PC.
982  Reg = ARM::PC;
983  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
984  if (MI != MBB.end())
985  MIB.copyImplicitOps(*MI);
986  MI = MBB.erase(MI);
987  }
988  MIB.addReg(Reg, getDefRegState(true));
989  NeedsPop = true;
990  }
991 
992  // It's illegal to emit pop instruction without operands.
993  if (NeedsPop)
994  MBB.insert(MI, &*MIB);
995  else
996  MF.DeleteMachineInstr(MIB);
997 
998  return true;
999 }
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
const MachineInstrBuilder & add(const MachineOperand &MO) const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
BitVector & set()
Definition: BitVector.h:397
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
#define R4(n)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineFunctionProperties & reset(Property P)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:504
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
MachineModuleInfo & getMMI() const
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:106
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
#define R2(n)
void setGPRCalleeSavedArea2Offset(unsigned o)
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:491
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
return AArch64::GPR64RegClass contains(Reg)
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:496
bool isTargetELF() const
Definition: ARMSubtarget.h:662
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
static void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
const HexagonInstrInfo * TII
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:331
Thumb1FrameLowering(const ARMSubtarget &sti)
unsigned getFrameRegister(const MachineFunction &MF) const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
void setDPRCalleeSavedAreaOffset(unsigned o)
unsigned getArgRegsSaveSize() const
void setFramePtrSpillOffset(unsigned o)
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
unsigned getDPRCalleeSavedAreaSize() const
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:739
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:731
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:477
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:484
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:180
unsigned getGPRCalleeSavedArea1Size() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
BitVector & reset()
Definition: BitVector.h:438
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasBasePointer(const MachineFunction &MF) const
void setGPRCalleeSavedArea2Size(unsigned s)
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define R6(n)
void setGPRCalleeSavedArea1Size(unsigned s)
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs)
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
std::bitset< ARM::NUM_TARGET_REGS > ARMRegSet
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
unsigned succ_size() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getGPRCalleeSavedArea2Size() const
void setGPRCalleeSavedArea1Offset(unsigned o)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:508
static const unsigned * findNextOrderedReg(const unsigned *CurrentReg, const ARMRegSet &EnabledRegs, const unsigned *OrderEnd)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
void setDPRCalleeSavedAreaSize(unsigned s)
int getOffsetAdjustment() const
Return the correction for frame offsets.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasV5TOps() const
Definition: ARMSubtarget.h:539
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:129
unsigned getFramePtrSpillOffset() const
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
void addReg(MCPhysReg Reg)
Adds a physical register and all its sub-registers to the set.
Definition: LivePhysRegs.h:79
static void findTemporariesForLR(const BitVector &GPRsNoLRSP, const BitVector &PopFriendly, const LivePhysRegs &UsedRegs, unsigned &PopReg, unsigned &TmpReg)
IRTranslator LLVM IR MI
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
const ARMSubtarget & STI
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
unsigned getReg() const
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
This class contains meta information specific to a module.