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LiveRegUnits.h
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1 //===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// A set of register units. It is intended for register liveness tracking.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_LIVEREGUNITS_H
16 #define LLVM_CODEGEN_LIVEREGUNITS_H
17 
18 #include "llvm/ADT/BitVector.h"
21 #include "llvm/MC/LaneBitmask.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include <cstdint>
24 
25 namespace llvm {
26 
27 class MachineInstr;
28 class MachineBasicBlock;
29 
30 /// A set of register units used to track register liveness.
31 class LiveRegUnits {
32  const TargetRegisterInfo *TRI = nullptr;
33  BitVector Units;
34 
35 public:
36  /// Constructs a new empty LiveRegUnits set.
37  LiveRegUnits() = default;
38 
39  /// Constructs and initialize an empty LiveRegUnits set.
41  init(TRI);
42  }
43 
44  /// For a machine instruction \p MI, adds all register units used in
45  /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is
46  /// useful when walking over a range of instructions to track registers
47  /// used or defined seperately.
48  static void accumulateUsedDefed(const MachineInstr &MI,
49  LiveRegUnits &ModifiedRegUnits,
50  LiveRegUnits &UsedRegUnits,
51  const TargetRegisterInfo *TRI) {
52  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
53  if (O->isRegMask())
54  ModifiedRegUnits.addRegsInMask(O->getRegMask());
55  if (!O->isReg())
56  continue;
57  unsigned Reg = O->getReg();
59  continue;
60  if (O->isDef()) {
61  // Some architectures (e.g. AArch64 XZR/WZR) have registers that are
62  // constant and may be used as destinations to indicate the generated
63  // value is discarded. No need to track such case as a def.
64  if (!TRI->isConstantPhysReg(Reg))
65  ModifiedRegUnits.addReg(Reg);
66  } else {
67  assert(O->isUse() && "Reg operand not a def and not a use");
68  UsedRegUnits.addReg(Reg);
69  }
70  }
71  return;
72  }
73 
74  /// Initialize and clear the set.
75  void init(const TargetRegisterInfo &TRI) {
76  this->TRI = &TRI;
77  Units.reset();
78  Units.resize(TRI.getNumRegUnits());
79  }
80 
81  /// Clears the set.
82  void clear() { Units.reset(); }
83 
84  /// Returns true if the set is empty.
85  bool empty() const { return Units.none(); }
86 
87  /// Adds register units covered by physical register \p Reg.
88  void addReg(unsigned Reg) {
89  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
90  Units.set(*Unit);
91  }
92 
93  /// Adds register units covered by physical register \p Reg that are
94  /// part of the lanemask \p Mask.
95  void addRegMasked(unsigned Reg, LaneBitmask Mask) {
96  for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
97  LaneBitmask UnitMask = (*Unit).second;
98  if (UnitMask.none() || (UnitMask & Mask).any())
99  Units.set((*Unit).first);
100  }
101  }
102 
103  /// Removes all register units covered by physical register \p Reg.
104  void removeReg(unsigned Reg) {
105  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
106  Units.reset(*Unit);
107  }
108 
109  /// Removes register units not preserved by the regmask \p RegMask.
110  /// The regmask has the same format as the one in the RegMask machine operand.
111  void removeRegsNotPreserved(const uint32_t *RegMask);
112 
113  /// Adds register units not preserved by the regmask \p RegMask.
114  /// The regmask has the same format as the one in the RegMask machine operand.
115  void addRegsInMask(const uint32_t *RegMask);
116 
117  /// Returns true if no part of physical register \p Reg is live.
118  bool available(unsigned Reg) const {
119  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
120  if (Units.test(*Unit))
121  return false;
122  }
123  return true;
124  }
125 
126  /// Updates liveness when stepping backwards over the instruction \p MI.
127  /// This removes all register units defined or clobbered in \p MI and then
128  /// adds the units used (as in use operands) in \p MI.
129  void stepBackward(const MachineInstr &MI);
130 
131  /// Adds all register units used, defined or clobbered in \p MI.
132  /// This is useful when walking over a range of instruction to find registers
133  /// unused over the whole range.
134  void accumulate(const MachineInstr &MI);
135 
136  /// Adds registers living out of block \p MBB.
137  /// Live out registers are the union of the live-in registers of the successor
138  /// blocks and pristine registers. Live out registers of the end block are the
139  /// callee saved registers.
140  void addLiveOuts(const MachineBasicBlock &MBB);
141 
142  /// Adds registers living into block \p MBB.
143  void addLiveIns(const MachineBasicBlock &MBB);
144 
145  /// Adds all register units marked in the bitvector \p RegUnits.
146  void addUnits(const BitVector &RegUnits) {
147  Units |= RegUnits;
148  }
149  /// Removes all register units marked in the bitvector \p RegUnits.
150  void removeUnits(const BitVector &RegUnits) {
151  Units.reset(RegUnits);
152  }
153  /// Return the internal bitvector representation of the set.
154  const BitVector &getBitVector() const {
155  return Units;
156  }
157 
158 private:
159  /// Adds pristine registers. Pristine registers are callee saved registers
160  /// that are unused in the function.
161  void addPristines(const MachineFunction &MF);
162 };
163 
164 } // end namespace llvm
165 
166 #endif // LLVM_CODEGEN_LIVEREGUNITS_H
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
BitVector & set()
Definition: BitVector.h:398
A common definition of LaneBitmask for use in TableGen and CodeGen.
bool empty() const
Returns true if the set is empty.
Definition: LiveRegUnits.h:85
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Definition: LiveRegUnits.h:48
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
void removeUnits(const BitVector &RegUnits)
Removes all register units marked in the bitvector RegUnits.
Definition: LiveRegUnits.h:150
const BitVector & getBitVector() const
Return the internal bitvector representation of the set.
Definition: LiveRegUnits.h:154
bool isValid() const
Returns true if this iterator is not yet at the end.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void removeReg(unsigned Reg)
Removes all register units covered by physical register Reg.
Definition: LiveRegUnits.h:104
void addRegsInMask(const uint32_t *RegMask)
Adds register units not preserved by the regmask RegMask.
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition: LiveRegUnits.h:75
BitVector & reset()
Definition: BitVector.h:439
constexpr bool none() const
Definition: LaneBitmask.h:52
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addUnits(const BitVector &RegUnits)
Adds all register units marked in the bitvector RegUnits.
Definition: LiveRegUnits.h:146
void addReg(unsigned Reg)
Adds register units covered by physical register Reg.
Definition: LiveRegUnits.h:88
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
void accumulate(const MachineInstr &MI)
Adds all register units used, defined or clobbered in MI.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void addRegMasked(unsigned Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask...
Definition: LiveRegUnits.h:95
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:202
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LiveRegUnits()=default
Constructs a new empty LiveRegUnits set.
bool available(unsigned Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:118
void clear()
Clears the set.
Definition: LiveRegUnits.h:82
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:31
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void removeRegsNotPreserved(const uint32_t *RegMask)
Removes register units not preserved by the regmask RegMask.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
LiveRegUnits(const TargetRegisterInfo &TRI)
Constructs and initialize an empty LiveRegUnits set.
Definition: LiveRegUnits.h:40