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LiveRegUnits.h
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1 //===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// A set of register units. It is intended for register liveness tracking.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_LIVEREGUNITS_H
16 #define LLVM_CODEGEN_LIVEREGUNITS_H
17 
18 #include "llvm/ADT/BitVector.h"
20 #include "llvm/MC/LaneBitmask.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include <cstdint>
23 
24 namespace llvm {
25 
26 class MachineInstr;
27 class MachineBasicBlock;
28 
29 /// A set of register units used to track register liveness.
30 class LiveRegUnits {
31  const TargetRegisterInfo *TRI = nullptr;
32  BitVector Units;
33 
34 public:
35  /// Constructs a new empty LiveRegUnits set.
36  LiveRegUnits() = default;
37 
38  /// Constructs and initialize an empty LiveRegUnits set.
40  init(TRI);
41  }
42 
43  /// Initialize and clear the set.
44  void init(const TargetRegisterInfo &TRI) {
45  this->TRI = &TRI;
46  Units.reset();
47  Units.resize(TRI.getNumRegUnits());
48  }
49 
50  /// Clears the set.
51  void clear() { Units.reset(); }
52 
53  /// Returns true if the set is empty.
54  bool empty() const { return Units.none(); }
55 
56  /// Adds register units covered by physical register \p Reg.
57  void addReg(unsigned Reg) {
58  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
59  Units.set(*Unit);
60  }
61 
62  /// \brief Adds register units covered by physical register \p Reg that are
63  /// part of the lanemask \p Mask.
64  void addRegMasked(unsigned Reg, LaneBitmask Mask) {
65  for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
66  LaneBitmask UnitMask = (*Unit).second;
67  if (UnitMask.none() || (UnitMask & Mask).any())
68  Units.set((*Unit).first);
69  }
70  }
71 
72  /// Removes all register units covered by physical register \p Reg.
73  void removeReg(unsigned Reg) {
74  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
75  Units.reset(*Unit);
76  }
77 
78  /// Removes register units not preserved by the regmask \p RegMask.
79  /// The regmask has the same format as the one in the RegMask machine operand.
80  void removeRegsNotPreserved(const uint32_t *RegMask);
81 
82  /// Adds register units not preserved by the regmask \p RegMask.
83  /// The regmask has the same format as the one in the RegMask machine operand.
84  void addRegsInMask(const uint32_t *RegMask);
85 
86  /// Returns true if no part of physical register \p Reg is live.
87  bool available(unsigned Reg) const {
88  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
89  if (Units.test(*Unit))
90  return false;
91  }
92  return true;
93  }
94 
95  /// Updates liveness when stepping backwards over the instruction \p MI.
96  /// This removes all register units defined or clobbered in \p MI and then
97  /// adds the units used (as in use operands) in \p MI.
98  void stepBackward(const MachineInstr &MI);
99 
100  /// Adds all register units used, defined or clobbered in \p MI.
101  /// This is useful when walking over a range of instruction to find registers
102  /// unused over the whole range.
103  void accumulate(const MachineInstr &MI);
104 
105  /// Adds registers living out of block \p MBB.
106  /// Live out registers are the union of the live-in registers of the successor
107  /// blocks and pristine registers. Live out registers of the end block are the
108  /// callee saved registers.
109  void addLiveOuts(const MachineBasicBlock &MBB);
110 
111  /// Adds registers living into block \p MBB.
112  void addLiveIns(const MachineBasicBlock &MBB);
113 
114  /// Adds all register units marked in the bitvector \p RegUnits.
115  void addUnits(const BitVector &RegUnits) {
116  Units |= RegUnits;
117  }
118  /// Removes all register units marked in the bitvector \p RegUnits.
119  void removeUnits(const BitVector &RegUnits) {
120  Units.reset(RegUnits);
121  }
122  /// Return the internal bitvector representation of the set.
123  const BitVector &getBitVector() const {
124  return Units;
125  }
126 
127 private:
128  /// Adds pristine registers. Pristine registers are callee saved registers
129  /// that are unused in the function.
130  void addPristines(const MachineFunction &MF);
131 };
132 
133 } // end namespace llvm
134 
135 #endif // LLVM_CODEGEN_LIVEREGUNITS_H
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
BitVector & set()
Definition: BitVector.h:398
A common definition of LaneBitmask for use in TableGen and CodeGen.
bool empty() const
Returns true if the set is empty.
Definition: LiveRegUnits.h:54
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool test(unsigned Idx) const
Definition: BitVector.h:502
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
void removeUnits(const BitVector &RegUnits)
Removes all register units marked in the bitvector RegUnits.
Definition: LiveRegUnits.h:119
const BitVector & getBitVector() const
Return the internal bitvector representation of the set.
Definition: LiveRegUnits.h:123
bool isValid() const
Returns true if this iterator is not yet at the end.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void removeReg(unsigned Reg)
Removes all register units covered by physical register Reg.
Definition: LiveRegUnits.h:73
Reg
All possible values of the reg field in the ModR/M byte.
void addRegsInMask(const uint32_t *RegMask)
Adds register units not preserved by the regmask RegMask.
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition: LiveRegUnits.h:44
BitVector & reset()
Definition: BitVector.h:439
constexpr bool none() const
Definition: LaneBitmask.h:52
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addUnits(const BitVector &RegUnits)
Adds all register units marked in the bitvector RegUnits.
Definition: LiveRegUnits.h:115
void addReg(unsigned Reg)
Adds register units covered by physical register Reg.
Definition: LiveRegUnits.h:57
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void accumulate(const MachineInstr &MI)
Adds all register units used, defined or clobbered in MI.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void addRegMasked(unsigned Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask...
Definition: LiveRegUnits.h:64
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:202
Representation of each machine instruction.
Definition: MachineInstr.h:59
LiveRegUnits()=default
Constructs a new empty LiveRegUnits set.
bool available(unsigned Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:87
void clear()
Clears the set.
Definition: LiveRegUnits.h:51
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
void removeRegsNotPreserved(const uint32_t *RegMask)
Removes register units not preserved by the regmask RegMask.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
LiveRegUnits(const TargetRegisterInfo &TRI)
Constructs and initialize an empty LiveRegUnits set.
Definition: LiveRegUnits.h:39