LLVM  6.0.0svn
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llvm::MachineOperand Class Reference

MachineOperand class - Representation of each machine instruction operand. More...

#include "llvm/CodeGen/MachineOperand.h"

Collaboration diagram for llvm::MachineOperand:
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Public Types

enum  MachineOperandType : unsigned char {
  MO_Register, MO_Immediate, MO_CImmediate, MO_FPImmediate,
  MO_MachineBasicBlock, MO_FrameIndex, MO_ConstantPoolIndex, MO_TargetIndex,
  MO_JumpTableIndex, MO_ExternalSymbol, MO_GlobalAddress, MO_BlockAddress,
  MO_RegisterMask, MO_RegisterLiveOut, MO_Metadata, MO_MCSymbol,
  MO_CFIIndex, MO_IntrinsicID, MO_Predicate, MO_Last = MO_Predicate
}
 

Public Member Functions

MachineOperandType getType () const
 getType - Returns the MachineOperandType for this operand. More...
 
unsigned getTargetFlags () const
 
void setTargetFlags (unsigned F)
 
void addTargetFlag (unsigned F)
 
MachineInstrgetParent ()
 getParent - Return the instruction that this operand belongs to. More...
 
const MachineInstrgetParent () const
 
void clearParent ()
 clearParent - Reset the parent pointer. More...
 
void print (raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
 
void print (raw_ostream &os, ModuleSlotTracker &MST, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
 
void dump () const
 
bool isReg () const
 isReg - Tests if this is a MO_Register operand. More...
 
bool isImm () const
 isImm - Tests if this is a MO_Immediate operand. More...
 
bool isCImm () const
 isCImm - Test if this is a MO_CImmediate operand. More...
 
bool isFPImm () const
 isFPImm - Tests if this is a MO_FPImmediate operand. More...
 
bool isMBB () const
 isMBB - Tests if this is a MO_MachineBasicBlock operand. More...
 
bool isFI () const
 isFI - Tests if this is a MO_FrameIndex operand. More...
 
bool isCPI () const
 isCPI - Tests if this is a MO_ConstantPoolIndex operand. More...
 
bool isTargetIndex () const
 isTargetIndex - Tests if this is a MO_TargetIndex operand. More...
 
bool isJTI () const
 isJTI - Tests if this is a MO_JumpTableIndex operand. More...
 
bool isGlobal () const
 isGlobal - Tests if this is a MO_GlobalAddress operand. More...
 
bool isSymbol () const
 isSymbol - Tests if this is a MO_ExternalSymbol operand. More...
 
bool isBlockAddress () const
 isBlockAddress - Tests if this is a MO_BlockAddress operand. More...
 
bool isRegMask () const
 isRegMask - Tests if this is a MO_RegisterMask operand. More...
 
bool isRegLiveOut () const
 isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand. More...
 
bool isMetadata () const
 isMetadata - Tests if this is a MO_Metadata operand. More...
 
bool isMCSymbol () const
 
bool isCFIIndex () const
 
bool isIntrinsicID () const
 
bool isPredicate () const
 
unsigned getReg () const
 getReg - Returns the register number. More...
 
unsigned getSubReg () const
 
bool isUse () const
 
bool isDef () const
 
bool isImplicit () const
 
bool isDead () const
 
bool isKill () const
 
bool isUndef () const
 
bool isInternalRead () const
 
bool isEarlyClobber () const
 
bool isTied () const
 
bool isDebug () const
 
bool readsReg () const
 readsReg - Returns true if this operand reads the previous value of its register. More...
 
void setReg (unsigned Reg)
 Change the register this operand corresponds to. More...
 
void setSubReg (unsigned subReg)
 
void substVirtReg (unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
 substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg. More...
 
void substPhysReg (unsigned Reg, const TargetRegisterInfo &)
 substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account. More...
 
void setIsUse (bool Val=true)
 
void setIsDef (bool Val=true)
 Change a def to a use, or a use to a def. More...
 
void setImplicit (bool Val=true)
 
void setIsKill (bool Val=true)
 
void setIsDead (bool Val=true)
 
void setIsUndef (bool Val=true)
 
void setIsInternalRead (bool Val=true)
 
void setIsEarlyClobber (bool Val=true)
 
void setIsDebug (bool Val=true)
 
int64_t getImm () const
 
const ConstantIntgetCImm () const
 
const ConstantFPgetFPImm () const
 
MachineBasicBlockgetMBB () const
 
int getIndex () const
 
const GlobalValuegetGlobal () const
 
const BlockAddressgetBlockAddress () const
 
MCSymbolgetMCSymbol () const
 
unsigned getCFIIndex () const
 
Intrinsic::ID getIntrinsicID () const
 
unsigned getPredicate () const
 
int64_t getOffset () const
 Return the offset from the symbol in this operand. More...
 
const chargetSymbolName () const
 
bool clobbersPhysReg (unsigned PhysReg) const
 clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. More...
 
const uint32_tgetRegMask () const
 getRegMask - Returns a bit mask of registers preserved by this RegMask operand. More...
 
const uint32_tgetRegLiveOut () const
 getRegLiveOut - Returns a bit mask of live-out registers. More...
 
const MDNodegetMetadata () const
 
void setImm (int64_t immVal)
 
void setFPImm (const ConstantFP *CFP)
 
void setOffset (int64_t Offset)
 
void setIndex (int Idx)
 
void setMetadata (const MDNode *MD)
 
void setMBB (MachineBasicBlock *MBB)
 
void setRegMask (const uint32_t *RegMaskPtr)
 Sets value of register mask operand referencing Mask. More...
 
bool isIdenticalTo (const MachineOperand &Other) const
 Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead). More...
 
void ChangeToImmediate (int64_t ImmVal)
 ChangeToImmediate - Replace this operand with a new immediate operand of the specified value. More...
 
void ChangeToFPImmediate (const ConstantFP *FPImm)
 ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value. More...
 
void ChangeToES (const char *SymName, unsigned char TargetFlags=0)
 ChangeToES - Replace this operand with a new external symbol operand. More...
 
void ChangeToMCSymbol (MCSymbol *Sym)
 ChangeToMCSymbol - Replace this operand with a new MC symbol operand. More...
 
void ChangeToFrameIndex (int Idx)
 Replace this operand with a frame index. More...
 
void ChangeToTargetIndex (unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
 Replace this operand with a target index. More...
 
void ChangeToRegister (unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
 ChangeToRegister - Replace this operand with a new register operand of the specified value. More...
 

Static Public Member Functions

static bool clobbersPhysReg (const uint32_t *RegMask, unsigned PhysReg)
 clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. More...
 
static MachineOperand CreateImm (int64_t Val)
 
static MachineOperand CreateCImm (const ConstantInt *CI)
 
static MachineOperand CreateFPImm (const ConstantFP *CFP)
 
static MachineOperand CreateReg (unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
 
static MachineOperand CreateMBB (MachineBasicBlock *MBB, unsigned char TargetFlags=0)
 
static MachineOperand CreateFI (int Idx)
 
static MachineOperand CreateCPI (unsigned Idx, int Offset, unsigned char TargetFlags=0)
 
static MachineOperand CreateTargetIndex (unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
 
static MachineOperand CreateJTI (unsigned Idx, unsigned char TargetFlags=0)
 
static MachineOperand CreateGA (const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
 
static MachineOperand CreateES (const char *SymName, unsigned char TargetFlags=0)
 
static MachineOperand CreateBA (const BlockAddress *BA, int64_t Offset, unsigned char TargetFlags=0)
 
static MachineOperand CreateRegMask (const uint32_t *Mask)
 CreateRegMask - Creates a register mask operand referencing Mask. More...
 
static MachineOperand CreateRegLiveOut (const uint32_t *Mask)
 
static MachineOperand CreateMetadata (const MDNode *Meta)
 
static MachineOperand CreateMCSymbol (MCSymbol *Sym, unsigned char TargetFlags=0)
 
static MachineOperand CreateCFIIndex (unsigned CFIIndex)
 
static MachineOperand CreateIntrinsicID (Intrinsic::ID ID)
 
static MachineOperand CreatePredicate (unsigned Pred)
 

Friends

class MachineInstr
 
class MachineRegisterInfo
 
struct DenseMapInfo< MachineOperand >
 
hash_code hash_value (const MachineOperand &MO)
 MachineOperand hash_value overload. More...
 

Detailed Description

MachineOperand class - Representation of each machine instruction operand.

This class isn't a POD type because it has a private constructor, but its destructor must be trivial. Functions like MachineInstr::addOperand(), MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on not having to call the MachineOperand destructor.

Definition at line 47 of file MachineOperand.h.

Member Enumeration Documentation

◆ MachineOperandType

Enumerator
MO_Register 

Register operand.

MO_Immediate 

Immediate operand.

MO_CImmediate 

Immediate >64bit operand.

MO_FPImmediate 

Floating-point immediate operand.

MO_MachineBasicBlock 

MachineBasicBlock reference.

MO_FrameIndex 

Abstract Stack Frame Index.

MO_ConstantPoolIndex 

Address of indexed Constant in Constant Pool.

MO_TargetIndex 

Target-dependent index+offset operand.

MO_JumpTableIndex 

Address of indexed Jump Table for switch.

MO_ExternalSymbol 

Name of external global symbol.

MO_GlobalAddress 

Address of a global value.

MO_BlockAddress 

Address of a basic block.

MO_RegisterMask 

Mask of preserved registers.

MO_RegisterLiveOut 

Mask of live-out registers.

MO_Metadata 

Metadata reference (for debug info)

MO_MCSymbol 

MCSymbol reference (for debug/eh info)

MO_CFIIndex 

MCCFIInstruction index.

MO_IntrinsicID 

Intrinsic ID for ISel.

MO_Predicate 

Generic predicate for ISel.

MO_Last 

Definition at line 49 of file MachineOperand.h.

Member Function Documentation

◆ addTargetFlag()

void llvm::MachineOperand::addTargetFlag ( unsigned  F)
inline

Definition at line 207 of file MachineOperand.h.

References assert(), F(), and isReg().

Referenced by llvm::HexagonInstrInfo::immediateExtend(), and INITIALIZE_PASS().

◆ ChangeToES()

void MachineOperand::ChangeToES ( const char SymName,
unsigned char  TargetFlags = 0 
)

ChangeToES - Replace this operand with a new external symbol operand.

Definition at line 184 of file MachineInstr.cpp.

References assert(), isReg(), isTied(), MO_ExternalSymbol, setOffset(), and setTargetFlags().

Referenced by setRegMask().

◆ ChangeToFPImmediate()

void MachineOperand::ChangeToFPImmediate ( const ConstantFP FPImm)

ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.

If an operand is known to be an FP immediate already, the setFPImm method should be used.

Definition at line 175 of file MachineInstr.cpp.

References assert(), isReg(), isTied(), and MO_FPImmediate.

Referenced by setRegMask().

◆ ChangeToFrameIndex()

void MachineOperand::ChangeToFrameIndex ( int  Idx)

Replace this operand with a frame index.

Definition at line 206 of file MachineInstr.cpp.

References assert(), isReg(), isTied(), MO_FrameIndex, and setIndex().

Referenced by changeFCMPPredToAArch64CC(), setRegMask(), swapRegAndNonRegOperand(), llvm::updateDbgValueForSpill(), and updateOperand().

◆ ChangeToImmediate()

void MachineOperand::ChangeToImmediate ( int64_t  ImmVal)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

If an operand is known to be an immediate already, the setImm method should be used.

Definition at line 166 of file MachineInstr.cpp.

References assert(), ImmVal, isReg(), isTied(), and MO_Immediate.

Referenced by changeFCMPPredToAArch64CC(), llvm::createX86OptimizeLEAs(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getLeaOP(), getLoadStoreOffsetAlign(), hoistAndMergeSGPRInits(), llvm::Mips16RegisterInfo::intRegClass(), llvm::SIInstrInfo::legalizeOperandsVOP2(), replaceFI(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), setRegMask(), swapRegAndNonRegOperand(), tryConstantFoldOp(), llvm::updateDbgValueForSpill(), and updateOperand().

◆ ChangeToMCSymbol()

void MachineOperand::ChangeToMCSymbol ( MCSymbol Sym)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

Definition at line 196 of file MachineInstr.cpp.

References assert(), isReg(), isTied(), MO_MCSymbol, and Sym.

Referenced by setRegMask().

◆ ChangeToRegister()

void MachineOperand::ChangeToRegister ( unsigned  Reg,
bool  isDef,
bool  isImp = false,
bool  isKill = false,
bool  isDead = false,
bool  isUndef = false,
bool  isDebug = false 
)

ChangeToRegister - Replace this operand with a new register operand of the specified value.

If an operand is known to be an register already, the setReg method should be used.

Definition at line 232 of file MachineInstr.cpp.

References llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::MachineBasicBlock::getParent(), getParent(), isDead(), isDebug(), isDef(), isKill(), isReg(), isUndef(), MBB, MI, MO_Register, Reg, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced by AssignProtectedObjSet(), llvm::createX86OptimizeLEAs(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), getLoadStoreOffsetAlign(), llvm::Mips16RegisterInfo::intRegClass(), isSubregOf(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOpWithMove(), replaceFI(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), setRegMask(), swapRegAndNonRegOperand(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ ChangeToTargetIndex()

void MachineOperand::ChangeToTargetIndex ( unsigned  Idx,
int64_t  Offset,
unsigned char  TargetFlags = 0 
)

Replace this operand with a target index.

Definition at line 216 of file MachineInstr.cpp.

References assert(), isReg(), isTied(), MO_TargetIndex, setIndex(), setOffset(), and setTargetFlags().

Referenced by setRegMask().

◆ clearParent()

void llvm::MachineOperand::clearParent ( )
inline

clearParent - Reset the parent pointer.

The MachineOperand copy constructor also copies ParentMI, expecting the original to be deleted. If a MachineOperand is ever stored outside a MachineInstr, the parent pointer must be cleared.

Never call clearParent() on an operand in a MachineInstr.

Definition at line 227 of file MachineOperand.h.

References dump(), and print().

◆ clobbersPhysReg() [1/2]

static bool llvm::MachineOperand::clobbersPhysReg ( const uint32_t RegMask,
unsigned  PhysReg 
)
inlinestatic

◆ clobbersPhysReg() [2/2]

bool llvm::MachineOperand::clobbersPhysReg ( unsigned  PhysReg) const
inline

clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.

Definition at line 504 of file MachineOperand.h.

References clobbersPhysReg(), and getRegMask().

◆ CreateBA()

static MachineOperand llvm::MachineOperand::CreateBA ( const BlockAddress BA,
int64_t  Offset,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ CreateCFIIndex()

static MachineOperand llvm::MachineOperand::CreateCFIIndex ( unsigned  CFIIndex)
inlinestatic

Definition at line 763 of file MachineOperand.h.

References CFIIndex, and MO_CFIIndex.

Referenced by llvm::MachineInstrBuilder::addCFIIndex(), and isImplicitOperandIn().

◆ CreateCImm()

static MachineOperand llvm::MachineOperand::CreateCImm ( const ConstantInt CI)
inlinestatic

Definition at line 628 of file MachineOperand.h.

References CI, and MO_CImmediate.

Referenced by llvm::MachineInstrBuilder::addCImm(), and isImplicitOperandIn().

◆ CreateCPI()

static MachineOperand llvm::MachineOperand::CreateCPI ( unsigned  Idx,
int  Offset,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ CreateES()

static MachineOperand llvm::MachineOperand::CreateES ( const char SymName,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ CreateFI()

static MachineOperand llvm::MachineOperand::CreateFI ( int  Idx)
inlinestatic

◆ CreateFPImm()

static MachineOperand llvm::MachineOperand::CreateFPImm ( const ConstantFP CFP)
inlinestatic

◆ CreateGA()

static MachineOperand llvm::MachineOperand::CreateGA ( const GlobalValue GV,
int64_t  Offset,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ CreateImm()

static MachineOperand llvm::MachineOperand::CreateImm ( int64_t  Val)
inlinestatic

◆ CreateIntrinsicID()

static MachineOperand llvm::MachineOperand::CreateIntrinsicID ( Intrinsic::ID  ID)
inlinestatic

Definition at line 769 of file MachineOperand.h.

References IntrinsicID, and MO_IntrinsicID.

Referenced by llvm::MachineInstrBuilder::addIntrinsicID(), and isImplicitOperandIn().

◆ CreateJTI()

static MachineOperand llvm::MachineOperand::CreateJTI ( unsigned  Idx,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ CreateMBB()

static MachineOperand llvm::MachineOperand::CreateMBB ( MachineBasicBlock MBB,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ CreateMCSymbol()

static MachineOperand llvm::MachineOperand::CreateMCSymbol ( MCSymbol Sym,
unsigned char  TargetFlags = 0 
)
inlinestatic

Definition at line 754 of file MachineOperand.h.

References MO_MCSymbol, setOffset(), setTargetFlags(), and Sym.

Referenced by llvm::MachineInstrBuilder::addSym(), and EmitNops().

◆ CreateMetadata()

static MachineOperand llvm::MachineOperand::CreateMetadata ( const MDNode Meta)
inlinestatic

Definition at line 748 of file MachineOperand.h.

References MD, and MO_Metadata.

Referenced by llvm::MachineInstrBuilder::addMetadata(), and isImplicitOperandIn().

◆ CreatePredicate()

static MachineOperand llvm::MachineOperand::CreatePredicate ( unsigned  Pred)
inlinestatic

Definition at line 775 of file MachineOperand.h.

References MO_Predicate, and Pred.

Referenced by llvm::MachineInstrBuilder::addPredicate(), and isImplicitOperandIn().

◆ CreateReg()

static MachineOperand llvm::MachineOperand::CreateReg ( unsigned  Reg,
bool  isDef,
bool  isImp = false,
bool  isKill = false,
bool  isDead = false,
bool  isUndef = false,
bool  isEarlyClobber = false,
unsigned  SubReg = 0,
bool  isDebug = false,
bool  isInternalRead = false 
)
inlinestatic

Definition at line 640 of file MachineOperand.h.

References assert(), isDead(), isDebug(), isDef(), isEarlyClobber(), isInternalRead(), isKill(), isUndef(), MO_Register, Reg, RegNo, setSubReg(), and SubReg.

Referenced by llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::R600InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::condCodeOp(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::createSIFixWWMLivenessPass(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonFrameLowering::emitPrologue(), llvm::X86InstrInfo::foldMemoryOperandImpl(), forceReg(), llvm::HexagonFrameLowering::getAlignaInstr(), llvm::X86AddressMode::getFullAddress(), getUnderlyingArgReg(), llvm::LiveVariables::HandleVirtRegDef(), ImposeStackOrdering(), INITIALIZE_PASS(), isCopy(), isFunctionEntryBlock(), isImmValidForOpcode(), isImplicitOperandIn(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::CallLowering::lowerCall(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::predOps(), profitImm(), removeExternalCFGEdges(), llvm::rewriteT2FrameIndex(), llvm::FastISel::selectGetElementPtr(), llvm::FastISel::selectIntrinsicCall(), llvm::FastISel::selectPatchpoint(), llvm::FastISel::selectStackmap(), llvm::FastISel::selectXRayCustomEvent(), llvm::t1CondCodeOp(), llvm::tryFoldSPUpdateIntoPushPop(), and llvm::LiveDebugVariables::~LiveDebugVariables().

◆ CreateRegLiveOut()

static MachineOperand llvm::MachineOperand::CreateRegLiveOut ( const uint32_t Mask)
inlinestatic

◆ CreateRegMask()

static MachineOperand llvm::MachineOperand::CreateRegMask ( const uint32_t Mask)
inlinestatic

CreateRegMask - Creates a register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand.

A RegMask operand represents a set of non-clobbered physical registers on an instruction that clobbers many registers, typically a call. The bit mask has a bit set for each physreg that is preserved by this instruction, as described in the documentation for TargetRegisterInfo::getCallPreservedMask().

Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line 736 of file MachineOperand.h.

References assert(), llvm::BitmaskEnumDetail::Mask(), MO_RegisterMask, and RegMask.

Referenced by llvm::MachineInstrBuilder::addRegMask(), isImplicitOperandIn(), and llvm::FastISel::selectPatchpoint().

◆ CreateTargetIndex()

static MachineOperand llvm::MachineOperand::CreateTargetIndex ( unsigned  Idx,
int64_t  Offset,
unsigned char  TargetFlags = 0 
)
inlinestatic

◆ dump()

LLVM_DUMP_METHOD void MachineOperand::dump ( ) const

Definition at line 570 of file MachineInstr.cpp.

Referenced by clearParent().

◆ getBlockAddress()

const BlockAddress* llvm::MachineOperand::getBlockAddress ( ) const
inline

◆ getCFIIndex()

unsigned llvm::MachineOperand::getCFIIndex ( ) const
inline

◆ getCImm()

const ConstantInt* llvm::MachineOperand::getCImm ( ) const
inline

◆ getFPImm()

const ConstantFP* llvm::MachineOperand::getFPImm ( ) const
inline

◆ getGlobal()

const GlobalValue* llvm::MachineOperand::getGlobal ( ) const
inline

Definition at line 448 of file MachineOperand.h.

References assert(), and isGlobal().

Referenced by llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::ARCMCInstLower::ARCMCInstLower(), llvm::EHStreamer::callToNoUnwindFunction(), changeFCMPPredToAArch64CC(), createPHIsForCMOVsInSinkBB(), llvm::PPCFrameLowering::emitEpilogue(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), llvm::getAddressFromInstr(), llvm::SystemZMCInstLower::getExpr(), llvm::MSP430MCInstLower::GetGlobalAddressSymbol(), llvm::BPFMCInstLower::GetGlobalAddressSymbol(), llvm::LanaiMCInstLower::GetGlobalAddressSymbol(), llvm::AArch64MCInstLower::GetGlobalAddressSymbol(), getLeaOP(), getNumExtraSGPRs(), GetSymbolFromOperand(), llvm::hash_value(), llvm::HexagonLowerToMC(), llvm::NVPTXAsmPrinter::ignoreLoc(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), isIdenticalTo(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimilarDispOp(), llvm::WebAssemblyMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), LowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), makeImplicit(), llvm::rdf::operator<<(), llvm::MIPrinter::print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printSymbolOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), QueryCallee(), llvm::DetectRoundChange::runOnMachineFunction(), stripRegisterPrefix(), trySequenceOfOnes(), and UseReg().

◆ getImm()

int64_t llvm::MachineOperand::getImm ( ) const
inline

Definition at line 422 of file MachineOperand.h.

References assert(), and isImm().

Referenced by llvm::DwarfUnit::addConstantValue(), llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), llvm::R600InstrInfo::addFlag(), adjustDefLatency(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), areCandidatesToMergeOrPair(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), AssignProtectedObjSet(), attachMEMCPYScratchRegs(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canBeExpandedToORR(), canCompareBeNewValueJump(), canFoldIntoCSel(), llvm::X86InstrInfo::canMakeTailCallConditional(), changeFCMPPredToAArch64CC(), llvm::X86InstrInfo::classifyLEAReg(), llvm::R600InstrInfo::clearFlag(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), compareMachineOp(), CompareMBBNumbers(), computeExprForSpill(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSILowerI1CopiesPass(), llvm::createSparcDelaySlotFillerPass(), llvm::createX86OptimizeLEAs(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitClzero(), emitDebugValueComment(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::AsmPrinter::emitFrameAlloc(), EmitGCCInlineAsmStr(), EmitHiLo(), emitIndirectDst(), emitIndirectSrc(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), EmitMSInlineAsmStr(), EmitNops(), emitPostSt(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), ExpandMOVImmSExti8(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::X86InstrInfo::findCommutedOpIndices(), findCondCodeUsedByInstr(), llvm::MachineInstr::findInlineAsmFlagIdx(), FindStartOfTree(), llvm::MachineInstr::findTiedOperandIdx(), llvm::foldFrameOffset(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), forceReg(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), llvm::getAddressFromInstr(), getADDriFromLEA(), getAdjustedCmp(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::SystemZInstrInfo::getBranchInfo(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::getConstantVRegVal(), getDebugLocValue(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getDwarfRegNum(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::X86InstrInfo::getFrameAdjustment(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::MSP430InstrInfo::getFramePoppedByCallee(), llvm::TargetInstrInfo::getFrameSize(), llvm::TargetInstrInfo::getFrameTotalSize(), llvm::SystemZInstrInfo::getFusedCompare(), getHWReg(), llvm::StackMapOpers::getID(), GetImm(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::getInstrPredicate(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::NVPTXInstrInfo::getLdStCodeAddrSpace(), getLeaOP(), getLoadStoreOffsetAlign(), getLoadStoreOffsetSizeInBits(), getLSMultipleTransferSize(), getMappedOp(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMemoryOpOffset(), getMFHiLoOpc(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNumCallArgs(), getNumMicroOpsSwiftLdSt(), llvm::StackMapOpers::getNumPatchBytes(), llvm::SIInstrInfo::getNumWaitStates(), getOModValue(), getPostIndexedLoadStoreOpcode(), llvm::ARMBaseInstrInfo::getPredicate(), getReassignedChan(), llvm::TargetInstrInfo::getRegSequenceInputs(), getRetOpcode(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStoreOffset(), getStoreTarget(), getTruncatedShiftCount(), getUnconditionalBrDisp(), llvm::NVPTXAsmPrinter::getVirtualRegisterName(), getWinAllocaAmount(), llvm::AArch64InstrInfo::hasExtendedReg(), llvm::hash_value(), HashMachineInstr(), hasLEAOffset(), llvm::SIInstrInfo::hasModifiersSet(), llvm::AArch64InstrInfo::hasShiftedReg(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), llvm::NVPTXAsmPrinter::ignoreLoc(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::intRegClass(), llvm::isAArch64FrameOffsetLegal(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::ARMBaseInstrInfo::isAm2ScaledReg(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), isCompareZero(), llvm::HexagonInstrInfo::isConstExtended(), llvm::MachineInstr::isConvergent(), isCrossCopy(), llvm::AArch64InstrInfo::isExynosShiftLeftFast(), llvm::AArch64InstrInfo::isFalkorShiftExtFast(), isFpMulInstruction(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isIdenticalTo(), isImmValidForOpcode(), isImplicitlyDef(), isIncrementOrDecrement(), llvm::SIInstrInfo::isInlineConstant(), isKImmOperand(), isKImmOrKUImmOperand(), isKUImmOperand(), isLdOffsetInRangeOfSt(), llvm::ARMBaseInstrInfo::isLdstScaledReg(), llvm::ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(), llvm::ARMBaseInstrInfo::isLdstSoMinusReg(), isLEASimpleIncOrDec(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::R600InstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), isPromotableZeroStoreInst(), isRedundantFlagInstr(), isReverseInlineImm(), isSafeToFoldImmIntoCopy(), llvm::isScale(), llvm::AArch64InstrInfo::isScaledAddr(), isShift(), isSignExtendingOp(), isSimpleBD12Move(), isSimpleIf(), isSimpleMove(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), isSubregOf(), isSuitableForMask(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), isUseSafeToFold(), isVirtualRegisterOperand(), isZeroExtendingOp(), isZeroImm(), llvm::MipsInstrInfo::isZeroImm(), llvm::AArch64LegalizerInfo::legalizeCustom(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRIEfLow(), lowerRIHigh(), lowerRILow(), lowerSubvectorLoad(), lowerSubvectorStore(), lowerVECTOR_SHUFFLE_VSHF(), makeImplicit(), matchPair(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), Mips16WhichOp8uOr16simm(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::LegalizerHelper::narrowScalar(), llvm::PPCRegisterInfo::needsFrameBaseReg(), opcodeEmitsNoInsts(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCond(), parseCondBranch(), llvm::MIPrinter::print(), llvm::MachineInstr::print(), llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::SystemZAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), printConstant(), printExtendedName(), llvm::MipsAsmPrinter::printFCCOperand(), printIntelMemReference(), printLeaMemReference(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printOperand(), printPCRelImm(), profitImm(), readsVCCZ(), llvm::StackMaps::recordStackMap(), llvm::HexagonInstrInfo::reduceLoopCount(), registerDefinedBetween(), regOverlapsSet(), removePhis(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::WebAssemblyInstrInfo::reverseBranchCondition(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::AArch64InstrInfo::shouldClusterMemOps(), shrinkScalarCompare(), stripRegisterPrefix(), swapRegAndNonRegOperand(), llvm::SIInstrInfo::swapSourceModifiers(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), tryConstantFoldOp(), tryOptimizeLEAtoMOV(), trySequenceOfOnes(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::HexagonPacketizerList::useCalleesSP(), llvm::HexagonPacketizerList::useCallersSP(), UseReg(), verifyInsExtInstruction(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and llvm::LegalizerHelper::widenScalar().

◆ getIndex()

int llvm::MachineOperand::getIndex ( ) const
inline

Definition at line 442 of file MachineOperand.h.

References assert(), isCPI(), isFI(), isJTI(), and isTargetIndex().

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::ARCMCInstLower::ARCMCInstLower(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), BBHasFallthrough(), BBIsJumpedOver(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::MipsRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitJumpTableAddrs(), llvm::ARMAsmPrinter::EmitJumpTableInsts(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::TargetLoweringBase::emitPatchPoint(), foldImmediates(), llvm::getAddressFromInstr(), getConstantFromPool(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::LanaiMCInstLower::GetConstantPoolIndexSymbol(), llvm::SystemZMCInstLower::getExpr(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), llvm::LanaiMCInstLower::GetJumpTableSymbol(), getRetOpcode(), llvm::X86InstrInfo::getSPAdjust(), getStartOrEndSlot(), getUnconditionalBrDisp(), llvm::hash_value(), HashMachineInstr(), llvm::HexagonLowerToMC(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), isIdenticalTo(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::SIInstrInfo::isSGPRStackAccess(), isSimilarDispOp(), isSimpleMove(), llvm::SIInstrInfo::isStackAccess(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), lookupCandidateBaseReg(), llvm::AArch64MCInstLower::lowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), LowerSymbolOperand(), MatchingStackOffset(), matchPair(), false::IntervalSorter::operator()(), llvm::MIPrinter::print(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printSymbolOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::ARMBaseInstrInfo::reMaterialize(), stripRegisterPrefix(), swapRegAndNonRegOperand(), trySequenceOfOnes(), UseReg(), and X86SelectAddress().

◆ getIntrinsicID()

Intrinsic::ID llvm::MachineOperand::getIntrinsicID ( ) const
inline

◆ getMBB()

MachineBasicBlock* llvm::MachineOperand::getMBB ( ) const
inline

Definition at line 437 of file MachineOperand.h.

References assert(), and isMBB().

Referenced by llvm::XCoreInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::R600InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::SystemZInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::ARCMCInstLower::ARCMCInstLower(), BBIsJumpedOver(), changeFCMPPredToAArch64CC(), llvm::LiveRangeCalc::createDeadDefs(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), EmitGCCInlineAsmStr(), EmitHiLo(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), EmitNops(), llvm::SystemZPostRASchedStrategy::enterMBB(), llvm::HexagonEvaluator::evaluate(), findCorrespondingPred(), llvm::AVRInstrInfo::getBranchDestBlock(), llvm::SIInstrInfo::getBranchDestBlock(), llvm::AArch64InstrInfo::getBranchDestBlock(), getCmpForPseudo(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), llvm::SystemZMCInstLower::getExpr(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingBlock(), getInitPhiReg(), getLeaOP(), getLoopPhiReg(), llvm::MipsInstrInfo::GetMemOperand(), getNewValueJumpOpcode(), getPHIDeps(), getPHIPred(), getPhiRegs(), getPHISrcRegOpIdx(), getRegsUsedByPHIs(), getTargetMBB(), getUnconditionalBrDisp(), getVariantKind(), hasDataDependence(), llvm::hash_value(), HashMachineInstr(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), llvm::NVPTXAsmPrinter::ignoreLoc(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), INITIALIZE_PASS(), insertPHI(), isIdenticalTo(), isImmValidForOpcode(), isSimilarDispOp(), isSimpleIf(), isSourceDefinedByImplicitDef(), IsUnconditionalJump(), llvm::SIInstrInfo::legalizeOperands(), llvm::MSP430MCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), LowerSymbolOperand(), matchPair(), opcodeEmitsNoInsts(), llvm::rdf::operator<<(), llvm::AArch64InstrInfo::optimizeCondBranch(), parseCondBranch(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::HexagonInstrInfo::reduceLoopCount(), removePhis(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), stripRegisterPrefix(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::LegalizerHelper::widenScalar().

◆ getMCSymbol()

MCSymbol* llvm::MachineOperand::getMCSymbol ( ) const
inline

◆ getMetadata()

const MDNode* llvm::MachineOperand::getMetadata ( ) const
inline

◆ getOffset()

int64_t llvm::MachineOperand::getOffset ( ) const
inline

Return the offset from the symbol in this operand.

This always returns 0 for ExternalSymbol operands.

Definition at line 480 of file MachineOperand.h.

References assert(), isBlockAddress(), isCPI(), isGlobal(), isMCSymbol(), isSymbol(), and isTargetIndex().

Referenced by llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), llvm::ARCMCInstLower::ARCMCInstLower(), changeFCMPPredToAArch64CC(), llvm::createX86OptimizeLEAs(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::PPCFrameLowering::emitEpilogue(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), llvm::SystemZMCInstLower::getExpr(), GetSymbolRef(), llvm::hash_value(), HashMachineInstr(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), isIdenticalTo(), llvm::WebAssemblyMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::MSP430MCInstLower::LowerSymbolOperand(), llvm::BPFMCInstLower::LowerSymbolOperand(), llvm::LanaiMCInstLower::LowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(), llvm::AArch64MCInstLower::lowerSymbolOperandDarwin(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), makeImplicit(), llvm::MIPrinter::print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printSymbolOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), stripRegisterPrefix(), trySequenceOfOnes(), and UseReg().

◆ getParent() [1/2]

MachineInstr* llvm::MachineOperand::getParent ( )
inline

getParent - Return the instruction that this operand belongs to.

Definition at line 216 of file MachineOperand.h.

Referenced by addSegmentsWithValNo(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), changeFCMPPredToAArch64CC(), ChangeToRegister(), createBBSelectReg(), createDeadDef(), llvm::createHexagonHardwareLoops(), llvm::createWebAssemblyReplacePhysRegs(), llvm::createX86OptimizeLEAs(), CriticalPathStep(), llvm::MachineInstr::emitError(), llvm::MachineInstr::eraseFromBundle(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::RegBankSelect::getAnalysisUsage(), getFoldableImm(), getLoadStoreOffsetSizeInBits(), llvm::MachineInstr::getMF(), llvm::MachineRegisterInfo::defusechain_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::getOperandNo(), llvm::MachineInstr::getRegClassConstraint(), GetSymbolRef(), getUsedRegMask(), INITIALIZE_PASS(), isCrossCopy(), llvm::MachineInstr::isDereferenceableInvariantLoad(), isIdenticalTo(), llvm::SIInstrInfo::isInlineConstant(), isKilled(), isKImmOperand(), isKUImmOperand(), isNoReturnDef(), isSubregOf(), isUseSafeToFold(), llvm::AMDGPUMCInstLower::lowerOperand(), matchPair(), MoveForSingleUse(), multipleIterations(), OneUseDominatesOtherUses(), llvm::MachineRegisterInfo::defusechain_instr_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::operator*(), llvm::MachineRegisterInfo::defusechain_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::operator++(), llvm::MachineRegisterInfo::defusechain_instr_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::operator++(), llvm::MIPrinter::print(), llvm::MachineInstr::print(), llvm::MIPrinter::printTargetFlags(), readsVCCZ(), RematerializeCheapDef(), removeDeadSegment(), removeExternalCFGEdges(), llvm::MachineInstr::removeFromBundle(), llvm::MachineInstr::removeFromParent(), removePhis(), ReplaceDominatedUses(), replaceRegUsesAfterLoop(), llvm::MachineSSAUpdater::RewriteUse(), llvm::Localizer::runOnMachineFunction(), scavengeVReg(), setIsDef(), setReg(), false::Chain::str(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tryFoldInst(), llvm::FastISel::tryToFoldLoad(), UpdatePredRedefs(), llvm::MachineTraceMetrics::Ensemble::verify(), llvm::MachineFunction::verify(), and llvm::MachineRegisterInfo::verifyUseList().

◆ getParent() [2/2]

const MachineInstr* llvm::MachineOperand::getParent ( ) const
inline

Definition at line 217 of file MachineOperand.h.

◆ getPredicate()

unsigned llvm::MachineOperand::getPredicate ( ) const
inline

◆ getReg()

unsigned llvm::MachineOperand::getReg ( ) const
inline

getReg - Returns the register number.

Definition at line 279 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addExclusiveRegPair(), addLiveInRegs(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterKilled(), llvm::MachineRegisterInfo::addRegOperandToUseList(), addRegsToSet(), addSegmentsWithValNo(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ScheduleDAGInstrs::addVRegUseDeps(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::analyzeArguments(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::LiveRangeEdit::anyRematerializable(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::RegisterBankInfo::applyDefaultMapping(), areCandidatesToMergeOrPair(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), biasPhysRegCopy(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), BuildInstOrderMap(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canCombine(), canCompareBeNewValueJump(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), canFoldIntoSelect(), canMoveInstsAcrossMemOp(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), changeFCMPPredToAArch64CC(), llvm::X86InstrInfo::classifyLEAReg(), llvm::HexagonPacketizerList::cleanUpDotCur(), clobbersCTR(), collectDebugValues(), CombineCVTAToLocal(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), compareMachineOp(), computeBytesPoppedByCalleeForSRet(), llvm::TargetSchedModel::computeOutputLatency(), llvm::InstructionSelector::constrainOperandRegToRegClass(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), ContainsReg(), ConvertImplicitDefToConstZero(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), copyHint(), copyRegOperand(), countersNonZero(), llvm::createCopyConstrainDAGMutation(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::CreateEmptyPHI(), llvm::createHexagonHardwareLoops(), llvm::createLanaiDelaySlotFillerPass(), createPHIsForCMOVsInSinkBB(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createSparcDelaySlotFillerPass(), llvm::createWebAssemblyLowerBrUnless(), llvm::createWebAssemblyOptimizeLiveIntervals(), llvm::createX86FixupLEAs(), llvm::createX86FixupSetCC(), llvm::createX86OptimizeLEAs(), llvm::createXCoreFrameToArgsOffsetEliminationPass(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::HexagonFrameLowering::determineCalleeSaves(), dumpMachineInstrRangeWithSlotIndex(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), emitClzero(), emitDebugValueComment(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), EmitHiLo(), llvm::AsmPrinter::emitImplicitDef(), emitIndirectDst(), emitIndirectSrc(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::WebAssemblyAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitKill(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), emitLoadM0FromVGPRLoop(), emitMonitor(), EmitNops(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), emitPCMPSTRI(), emitPCMPSTRM(), emitPostSt(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitWRPKRU(), emitXBegin(), eraseGPOpnd(), eraseIfDead(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::InstructionSelector::executeMatchTable(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::CallLowering::ValueHandler::extendRegister(), llvm::DbgVariableLocation::extractFromMachineInstruction(), llvm::LegalizerHelper::fewerElementsVector(), llvm::finalizeBundle(), findDeadCallerSavedReg(), llvm::X86InstrInfo::findFMA3CommutedOpIndices(), findIncDecAfter(), findNextInsertLocation(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), FindStartOfTree(), finishConvertToThreeAddress(), llvm::fixStackStores(), fixupCalleeSaveRestoreStackOffset(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::foldFrameOffset(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), for(), forceReg(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::LegalizerInfo::getAction(), llvm::getAddressFromInstr(), llvm::RegBankSelect::getAnalysisUsage(), getBaseAddressRegister(), llvm::HexagonInstrInfo::getBaseAndOffset(), getCallTargetRegOpnd(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), getCopyRegClasses(), getCopyRewriter(), getDataDeps(), getDefRegMask(), GetDSubRegs(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getDwarfRegNum(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), getFoldableImm(), getFPReg(), llvm::ARMBaseInstrInfo::getFramePred(), llvm::SystemZInstrInfo::getFusedCompare(), llvm::HexagonHazardRecognizer::getHazardType(), getImmOrMaterializedImm(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingValue(), getInitPhiReg(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::getInstrPredicate(), getInstrVecReg(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getLeaOP(), getLiveLanesAt(), getLoadInfo(), getLoopPhiReg(), getLSMultipleTransferSize(), getMappedOp(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMFHiLoOpc(), getNewValueJumpOpcode(), llvm::rdf::DataFlowGraph::getNextShadow(), getNonDebugInstr(), getNumMicroOpsSwiftLdSt(), getOModValue(), llvm::PPCInstrInfo::getOperandLatency(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), getPHIDeps(), getPHIDestReg(), getPhiRegs(), getPHISourceReg(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPHIValue(), getPostIndexedLoadStoreOpcode(), getReassignedChan(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), getRegClassFromGRPhysReg(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), getRegsUsedByPHIs(), getRetOpcode(), getShuffleComment(), getSingleDef(), getSmrdOpcode(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStoreTarget(), getSubOpcode(), getTypeToPrint(), getUnconditionalBrDisp(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetUndefVal(), getUnderlyingArgReg(), getUnderlyingObjects(), getUsedRegMask(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), getWinAllocaAmount(), llvm::MipsTargetLowering::HandleByVal(), llvm::LiveIntervals::handleMoveIntoBundle(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), llvm::hash_value(), HashMachineInstr(), hasInefficientLEABaseReg(), llvm::X86InstrInfo::hasLiveCondCodeDef(), hasOneNonDBGUseInst(), hasRAWHazard(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasUseAfterLoop(), hasVGPROperands(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), llvm::NVPTXAsmPrinter::ignoreLoc(), ImmInRange(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::insertBranch(), insertCopy(), insertDivByZeroTrap(), InsertLDR_STR(), insertPHI(), InstructionStoresToFI(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::Mips16RegisterInfo::intRegClass(), llvm::ARMBaseInstrInfo::isAddrMode3OpImm(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::InstructionSelector::isBaseWithConstantOffset(), isCandidateStore(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::WebAssembly::isChild(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), llvm::PPCInstrInfo::isCoalescableExtInstr(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCompareZero(), isConstant(), llvm::MachineInstr::isConstantValuePHI(), isCopy(), isCopyFromExec(), isCopyToExec(), isCopyToReg(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isCSRestore(), isDbgValueDescribedByReg(), isDebug(), isDefInSubRange(), isDescribedByReg(), llvm::rdf::TargetOperandInfo::isFixedReg(), isFpMulInstruction(), llvm::AArch64InstrInfo::isFPRCopy(), isFullCopyOf(), isFullExecCopy(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isIdenticalOp(), isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineInstr::isIdentityCopy(), isImmValidForOpcode(), isImplicitlyDef(), isIncrementOrDecrement(), isInstrUniform(), llvm::ARMBaseInstrInfo::isLDMBaseRegInList(), isLEASimpleIncOrDec(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLive(), isLiveOut(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), isLocalCopy(), isLogicalOpOnExec(), isMMSourceRegister(), isMMThreeBitGPRegister(), llvm::NVPTXInstrInfo::isMoveInstr(), isNonFoldablePartialRegisterLoad(), llvm::InstructionSelector::isOperandImmEqual(), isOperandKill(), llvm::SIInstrInfo::isOperandLegal(), isPhysicalRegCopy(), llvm::R600InstrInfo::isPredicated(), isPreISelGenericFloatingPointOpcode(), isPromotableZeroStoreInst(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), isRegOperand(), isRematerializable(), IsSafeAndProfitableToMove(), llvm::X86InstrInfo::isSafeToClobberEFLAGS(), isSameReg(), isSecondInstructionInSequence(), isSExtLoad(), llvm::SIInstrInfo::isSGPRStackAccess(), isShift(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleBD12Move(), isSimpleIf(), isSimpleIndexCalc(), isSimpleMove(), isSourceDefinedByImplicitDef(), IsSP(), llvm::SIInstrInfo::isStackAccess(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), isSubregOf(), isSubRegOf(), isSuitableForMask(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTransformable(), isTwoAddrUse(), isUseSafeToFold(), isVGPR(), llvm::SIInstrInfo::isVGPRCopy(), isVirtualRegisterOperand(), llvm::AArch64LegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::LegalizerHelper::libcall(), llvm::MipsSEInstrInfo::loadImmediate(), llvm::Mips16InstrInfo::loadImmediate(), loadM0FromVGPR(), llvm::MSP430MCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LegalizerHelper::lower(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRIEfLow(), lowerRIHigh(), lowerRILow(), lowerSubvectorLoad(), lowerSubvectorStore(), lowerVECTOR_SHUFFLE_VSHF(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), makeImplicit(), llvm::rdf::DataFlowGraph::makeRegRef(), matchPair(), mayAlias(), MaybeRewriteToFallthrough(), mayCombineMisaligned(), mayLoadFromGOTOrConstantPool(), llvm::DebugLocEntry::MergeValues(), MIIsInTerminatorSequence(), Mips16WhichOp8uOr16simm(), MoveAndTeeForMultiUse(), llvm::MachineRegisterInfo::moveOperands(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::LegalizerHelper::narrowScalar(), llvm::AggressiveAntiDepBreaker::Observe(), OneUseDominatesOtherUses(), optimizeCall(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCond(), parseOperands(), phiHasBreakDef(), phiHasVGPROperands(), preservesValueOf(), llvm::MIPrinter::print(), print(), llvm::MachineInstr::print(), llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), printAsmMRegister(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), printExtendedName(), printIntelMemReference(), printLeaMemReference(), printMemReference(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), profitImm(), pushDepHeight(), readsVCCZ(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::TargetInstrInfo::reassociateOps(), llvm::HexagonInstrInfo::reduceLoopCount(), registerDefinedBetween(), regOverlapsSet(), llvm::WebAssemblyAsmPrinter::regToString(), llvm::R600SchedStrategy::releaseBottomNode(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::TargetInstrInfo::reMaterialize(), removeCopies(), RemoveDeadAddBetweenLEAAndJT(), removeIPMBasedCompare(), removeKillInfo(), removePhis(), llvm::MachineRegisterInfo::removeRegOperandFromUseList(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::PPCFrameLowering::replaceFPWithRealFP(), resultTests(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::rewriteAArch64FrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::UnreachableBlockElimPass::run(), llvm::Localizer::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::AMDGPUAsmPrinter::runOnMachineFunction(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::R600SchedStrategy::schedNode(), selectCopy(), llvm::FastISel::selectIntrinsicCall(), selectMergeValues(), selectUnmergeValues(), llvm::ARMBaseInstrInfo::setExecutionDomain(), setM0ToIndexFromSGPR(), setReg(), llvm::X86InstrInfo::setSpecialOperandAttr(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::SystemZRegisterInfo::shouldCoalesce(), shrinkScalarCompare(), simpleLibcall(), SinkingPreventsImplicitNullCheck(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::LiveDebugVariables::splitRegister(), false::Chain::str(), stripRegisterPrefix(), swapRegAndNonRegOperand(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tieOpsIfNeeded(), TrackDefUses(), tryChangeVGPRtoSGPRinCopy(), llvm::LegalizerCombiner::tryCombineAnyExt(), llvm::LegalizerCombiner::tryCombineInstruction(), llvm::LegalizerCombiner::tryCombineMerges(), llvm::LegalizerCombiner::tryCombineSExt(), llvm::LegalizerCombiner::tryCombineZExt(), tryConstantFoldOp(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), llvm::X86InstrInfo::unfoldMemoryOperand(), unsupportedBinOp(), llvm::AntiDepBreaker::UpdateDbgValue(), llvm::HexagonPacketizerList::updateOffset(), updateOperand(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::HexagonSubtarget::usePredicatedCalls(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), llvm::LegalizerHelper::widenScalar(), X86SelectAddress(), and llvm::LiveDebugVariables::~LiveDebugVariables().

◆ getRegLiveOut()

const uint32_t* llvm::MachineOperand::getRegLiveOut ( ) const
inline

getRegLiveOut - Returns a bit mask of live-out registers.

Definition at line 516 of file MachineOperand.h.

References assert(), and isRegLiveOut().

Referenced by getDwarfRegNum(), and llvm::MIPrinter::print().

◆ getRegMask()

const uint32_t* llvm::MachineOperand::getRegMask ( ) const
inline

◆ getSubReg()

unsigned llvm::MachineOperand::getSubReg ( ) const
inline

Definition at line 284 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addSegmentsWithValNo(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), canFoldCopy(), canMoveInstsAcrossMemOp(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::convertToThreeAddress(), copyHint(), copyRegOperand(), llvm::createHexagonHardwareLoops(), definesFullReg(), llvm::HexagonFrameLowering::determineCalleeSaves(), dumpMachineInstrRangeWithSlotIndex(), emitLoadM0FromVGPRLoop(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::HexagonInstrInfo::getBaseAndOffset(), getCopyRewriter(), getDefRegMask(), getDwarfRegNum(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), getImmOrMaterializedImm(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getLiveLanesAt(), getOModValue(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), getRegsUsedByPHIs(), getSrcFromCopy(), getUsedRegMask(), llvm::LiveIntervals::handleMoveIntoBundle(), llvm::hash_value(), INITIALIZE_PASS(), insertPHI(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCopy(), isCrossCopy(), isDebug(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::MachineInstr::isFullCopy(), isFullUndefDef(), isIdenticalTo(), llvm::MachineInstr::isIdentityCopy(), isImmValidForOpcode(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::SIInstrInfo::isOperandLegal(), isSafeToFoldImmIntoCopy(), isSameReg(), isSExtLoad(), isSimpleIf(), isSourceDefinedByImplicitDef(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), isSubregOf(), isSubRegOf(), isUseSafeToFold(), isVirtualRegisterOperand(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::rdf::DataFlowGraph::makeRegRef(), matchPair(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::MIPrinter::print(), print(), llvm::ARMAsmPrinter::printOperand(), profitImm(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), regOverlapsSet(), llvm::R600SchedStrategy::releaseBottomNode(), removeDeadSegment(), llvm::UnreachableBlockElimPass::run(), llvm::TailDuplicator::shouldTailDuplicate(), substPhysReg(), substVirtReg(), swapRegAndNonRegOperand(), tryFoldInst(), and updateOperand().

◆ getSymbolName()

const char* llvm::MachineOperand::getSymbolName ( ) const
inline

◆ getTargetFlags()

unsigned llvm::MachineOperand::getTargetFlags ( ) const
inline

Definition at line 199 of file MachineOperand.h.

References isReg().

Referenced by llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), canDefBePartOfLOH(), createPHIsForCMOVsInSinkBB(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), eraseGPOpnd(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::MSP430MCInstLower::GetBlockAddressSymbol(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::MSP430MCInstLower::GetExternalSymbolSymbol(), llvm::MSP430MCInstLower::GetGlobalAddressSymbol(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), GetSymbolFromOperand(), GetSymbolRef(), getVariantKind(), handleMiddleInst(), handleUse(), llvm::hash_value(), llvm::HexagonLowerToMC(), llvm::MipsMCInstLower::Initialize(), isCandidateLoad(), llvm::HexagonInstrInfo::isConstExtended(), isIdenticalTo(), llvm::WebAssemblyMCInstLower::Lower(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), LowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::MSP430MCInstLower::LowerSymbolOperand(), llvm::LanaiMCInstLower::LowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandDarwin(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), makeImplicit(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printSymbolOperand(), llvm::MIPrinter::printTargetFlags(), trySequenceOfOnes(), and UseReg().

◆ getType()

MachineOperandType llvm::MachineOperand::getType ( ) const
inline

getType - Returns the MachineOperandType for this operand.

Definition at line 197 of file MachineOperand.h.

Referenced by llvm::MachineInstrBuilder::addDisp(), canDefBePartOfLOH(), compareMachineOp(), EmitHiLo(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), EmitNops(), llvm::SystemZMCInstLower::getExpr(), getRetOpcode(), llvm::hash_value(), HashMachineInstr(), llvm::HexagonLowerToMC(), llvm::NVPTXAsmPrinter::ignoreLoc(), INITIALIZE_PASS(), IsAnAddressOperand(), llvm::DenseMapInfo< MachineOperand >::isEqual(), isIdenticalTo(), llvm::SIInstrInfo::isLiteralConstantLike(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), LowerSymbolOperand(), makeImplicit(), matchPair(), llvm::MIPrinter::print(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), printLeaMemReference(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printOperand(), printPCRelImm(), printSymbolOperand(), and stripRegisterPrefix().

◆ isBlockAddress()

bool llvm::MachineOperand::isBlockAddress ( ) const
inline

isBlockAddress - Tests if this is a MO_BlockAddress operand.

Definition at line 263 of file MachineOperand.h.

References MO_BlockAddress.

Referenced by getBlockAddress(), getOffset(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), setOffset(), stripRegisterPrefix(), and UseReg().

◆ isCFIIndex()

bool llvm::MachineOperand::isCFIIndex ( ) const
inline

Definition at line 271 of file MachineOperand.h.

References MO_CFIIndex.

Referenced by getCFIIndex().

◆ isCImm()

bool llvm::MachineOperand::isCImm ( ) const
inline

◆ isCPI()

bool llvm::MachineOperand::isCPI ( ) const
inline

◆ isDead()

bool llvm::MachineOperand::isDead ( ) const
inline

Definition at line 304 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addExclusiveRegPair(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::MachineOperandIteratorBase::analyzePhysReg(), canFoldIntoMOVCC(), canFoldIntoSelect(), ChangeToRegister(), llvm::X86InstrInfo::classifyLEAReg(), collectDebugValues(), llvm::PPCInstrInfo::commuteInstructionImpl(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyRegOperand(), llvm::createCopyConstrainDAGMutation(), CreateReg(), llvm::createWebAssemblyOptimizeLiveIntervals(), definesFullReg(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::ARMBaseInstrInfo::FoldImmediate(), getCopyRewriter(), GetDSubRegs(), getFPReg(), getLiveLanesAt(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::getRegState(), llvm::LiveVariables::HandleVirtRegDef(), llvm::X86InstrInfo::hasLiveCondCodeDef(), llvm::X86InstrInfo::hasReassociableOperands(), INITIALIZE_PASS(), InsertLDR_STR(), llvm::rdf::TargetOperandInfo::isClobbering(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isFpMulInstruction(), isFullUndefDef(), llvm::MachineInstr::isIdenticalTo(), isLoadAndTestAsCmp(), llvm::X86InstrInfo::isSafeToClobberEFLAGS(), isSimpleIf(), isSourceDefinedByImplicitDef(), isVirtualRegisterOperand(), makeImplicit(), matchPair(), MoveAndTeeForMultiUse(), llvm::MIPrinter::print(), print(), setRegMask(), llvm::X86InstrInfo::setSpecialOperandAttr(), swapRegAndNonRegOperand(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), UpdateCPSRUse(), updatePhysDepsDownwards(), and VerifyLowRegs().

◆ isDebug()

bool llvm::MachineOperand::isDebug ( ) const
inline

◆ isDef()

bool llvm::MachineOperand::isDef ( ) const
inline

Definition at line 294 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addLiveInRegs(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldIntoMOVCC(), canFoldIntoSelect(), ChangeToRegister(), clobbersCTR(), computeBytesPoppedByCalleeForSRet(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), countersNonZero(), createBBSelectReg(), llvm::createHexagonHardwareLoops(), llvm::createLanaiDelaySlotFillerPass(), CreateReg(), llvm::createSparcDelaySlotFillerPass(), llvm::createX86FixupLEAs(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), dumpMachineInstrRangeWithSlotIndex(), EmitGCCInlineAsmStr(), emitKill(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::finalizeBundle(), findDeadCallerSavedReg(), findDefIdx(), llvm::MachineInstr::findRegisterDefOperandIdx(), findUseIdx(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::RegBankSelect::getAnalysisUsage(), getCopyRewriter(), getDefRegMask(), llvm::PPCInstrInfo::getInstrLatency(), getInstrVecReg(), getLiveLanesAt(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::getRegState(), getRegsUsedByPHIs(), llvm::HexagonInstrInfo::getSize(), llvm::LiveIntervals::handleMoveIntoBundle(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), llvm::hash_value(), llvm::X86InstrInfo::hasLiveCondCodeDef(), hasUseAfterLoop(), INITIALIZE_PASS(), InstructionStoresToFI(), llvm::WebAssembly::isChild(), llvm::rdf::TargetOperandInfo::isClobbering(), isCrossCopy(), isDebug(), llvm::rdf::TargetOperandInfo::isFixedReg(), isFullUndefDef(), isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), isOperandKill(), llvm::MachineInstr::isRegTiedToUseOperand(), IsSafeAndProfitableToMove(), llvm::X86InstrInfo::isSafeToClobberEFLAGS(), isSimpleIf(), isSimpleIndexCalc(), isVirtualRegisterOperand(), llvm::Mips16InstrInfo::loadImmediate(), matchPair(), mayLoadFromGOTOrConstantPool(), MIIsInTerminatorSequence(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::AggressiveAntiDepBreaker::Observe(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), parseOperands(), llvm::PatchPointOpers::PatchPointOpers(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), print(), printImplicitRegisterFlag(), readsVCCZ(), llvm::R600SchedStrategy::releaseBottomNode(), RemoveDeadAddBetweenLEAAndJT(), removeDeadSegment(), removePhis(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), resultTests(), setRegMask(), substPhysReg(), llvm::MachineInstr::tieOperands(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), and llvm::HexagonSubtarget::usePredicatedCalls().

◆ isEarlyClobber()

bool llvm::MachineOperand::isEarlyClobber ( ) const
inline

◆ isFI()

bool llvm::MachineOperand::isFI ( ) const
inline

isFI - Tests if this is a MO_FrameIndex operand.

Definition at line 251 of file MachineOperand.h.

References MO_FrameIndex.

Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::BPFRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::TargetLoweringBase::emitPatchPoint(), findNextInsertLocation(), foldImmediates(), llvm::HexagonFrameLowering::getAlignaInstr(), getFrameIndexOperandNum(), getIndex(), getOModValue(), llvm::X86InstrInfo::getSPAdjust(), isCSRestore(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::isLeaMem(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::isMem(), llvm::SIInstrInfo::isOperandLegal(), llvm::SIInstrInfo::isSGPRStackAccess(), isSimpleMove(), llvm::SIInstrInfo::isStackAccess(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), lookupCandidateBaseReg(), MatchingStackOffset(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), false::IntervalSorter::operator()(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), setIndex(), swapRegAndNonRegOperand(), tryFoldInst(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ isFPImm()

bool llvm::MachineOperand::isFPImm ( ) const
inline

◆ isGlobal()

bool llvm::MachineOperand::isGlobal ( ) const
inline

◆ isIdenticalTo()

bool MachineOperand::isIdenticalTo ( const MachineOperand Other) const

◆ isImm()

bool llvm::MachineOperand::isImm ( ) const
inline

isImm - Tests if this is a MO_Immediate operand.

Definition at line 243 of file MachineOperand.h.

References MO_Immediate.

Referenced by llvm::DwarfUnit::addConstantValue(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), areCandidatesToMergeOrPair(), areCombinableOperations(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canFoldIntoCSel(), canShrink(), changeFCMPPredToAArch64CC(), llvm::createHexagonHardwareLoops(), llvm::createSILowerI1CopiesPass(), llvm::createSparcDelaySlotFillerPass(), llvm::createX86OptimizeLEAs(), llvm::X86RegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::PPCFrameLowering::emitEpilogue(), EmitHiLo(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), EmitNops(), llvm::HexagonEvaluator::evaluate(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::MachineInstr::findInlineAsmFlagIdx(), llvm::MachineInstr::findTiedOperandIdx(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), getADDriFromLEA(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::getConstantVRegVal(), getDebugLocValue(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getDwarfRegNum(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::R600InstrInfo::getFlagOp(), GetImm(), getImm(), getImmOrMaterializedImm(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::TargetInstrInfo::getInsertSubregInputs(), getLeaOP(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getOModValue(), llvm::AArch64InstrInfo::getOutliningType(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::X86InstrInfo::getSPAdjust(), llvm::R600InstrInfo::getSrcs(), getStoreOffset(), getStoreTarget(), getUnconditionalBrDisp(), getWinAllocaAmount(), llvm::AArch64InstrInfo::hasExtendedReg(), hasLEAOffset(), llvm::AArch64InstrInfo::hasShiftedReg(), llvm::NVPTXAsmPrinter::ignoreLoc(), llvm::HexagonInstrInfo::immediateExtend(), INITIALIZE_PASS(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isCompareZero(), llvm::HexagonInstrInfo::isConstExtended(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), llvm::SIInstrInfo::isImmOperandLegal(), isImmValidForOpcode(), llvm::MachineInstr::isIndirectDebugValue(), llvm::SIInstrInfo::isInlineConstant(), llvm::isLeaMem(), isLEASimpleIncOrDec(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isLiteralConstant(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::SIInstrInfo::isOperandLegal(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isSafeToFoldImmIntoCopy(), llvm::isScale(), isSimilarDispOp(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), isSubregOf(), isUseSafeToFold(), isValidDispOp(), isZeroImm(), llvm::MipsInstrInfo::isZeroImm(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOpWithMove(), makeImplicit(), matchPair(), llvm::SIInstrInfo::moveToVALU(), opcodeEmitsNoInsts(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MachineInstr::print(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::SystemZAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), printExtendedName(), printIntelMemReference(), profitImm(), setImm(), llvm::R600InstrInfo::setImmOperand(), shrinkScalarCompare(), stripRegisterPrefix(), swapRegAndNonRegOperand(), tryAddToFoldList(), tryConstantFoldOp(), tryFoldInst(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), validThroughout(), verifyInsExtInstruction(), llvm::SIInstrInfo::verifyInstruction(), and VerifyLowRegs().

◆ isImplicit()

bool llvm::MachineOperand::isImplicit ( ) const
inline

Definition at line 299 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addOperand(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterKilled(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::TargetSchedModel::computeOperandLatency(), ContainsReg(), copyExtraImplicitOps(), llvm::MachineInstr::copyImplicitOps(), countOperands(), llvm::createSparcDelaySlotFillerPass(), llvm::createWebAssemblyReplacePhysRegs(), definesFullReg(), dumpMachineInstrRangeWithSlotIndex(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitPCMPSTRI(), emitPCMPSTRM(), getCopyRewriter(), getDwarfRegNum(), llvm::PPCInstrInfo::getInstrLatency(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::MachineInstr::getNumExplicitOperands(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::getRegState(), getRetOpcode(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), llvm::WebAssembly::isChild(), isFullUndefDef(), isImmValidForOpcode(), isOperandKill(), isUseSafeToFold(), isVirtualRegisterOperand(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), matchPair(), mayLoadFromGOTOrConstantPool(), MoveAndTeeForMultiUse(), llvm::AggressiveAntiDepBreaker::Observe(), llvm::PatchPointOpers::PatchPointOpers(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), print(), printImplicitRegisterFlag(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::SIInstrInfo::usesConstantBus(), and VerifyLowRegs().

◆ isInternalRead()

bool llvm::MachineOperand::isInternalRead ( ) const
inline

◆ isIntrinsicID()

bool llvm::MachineOperand::isIntrinsicID ( ) const
inline

Definition at line 272 of file MachineOperand.h.

References MO_IntrinsicID.

Referenced by llvm::InstructionSelector::executeMatchTable(), and getIntrinsicID().

◆ isJTI()

bool llvm::MachineOperand::isJTI ( ) const
inline

◆ isKill()

bool llvm::MachineOperand::isKill ( ) const
inline

Definition at line 309 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addExclusiveRegPair(), llvm::MachineInstr::addRegisterKilled(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), ChangeToRegister(), llvm::X86InstrInfo::classifyLEAReg(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyFlagsToImplicitVCC(), copyRegOperand(), createBBSelectReg(), CreateReg(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), findIncDecAfter(), llvm::MachineInstr::findRegisterUseOperandIdx(), finishConvertToThreeAddress(), llvm::fixStackStores(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), genFusedMultiply(), genMaddR(), GetDSubRegs(), getMFHiLoOpc(), getNewValueJumpOpcode(), getPostIndexedLoadStoreOpcode(), llvm::getRegState(), getStoreTarget(), INITIALIZE_PASS(), insertDivByZeroTrap(), InsertFPConstInst(), InsertFPImmInst(), InsertLDR_STR(), InsertSPConstInst(), InsertSPImmInst(), isFpMulInstruction(), llvm::MachineInstr::isIdenticalTo(), isLEASimpleIncOrDec(), isOperandKill(), llvm::X86InstrInfo::isSafeToClobberEFLAGS(), isSimpleIndexCalc(), isSubregOf(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::MipsSEInstrInfo::loadImmediate(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), matchPair(), preserveCondRegFlags(), llvm::MIPrinter::print(), print(), llvm::TargetInstrInfo::reassociateOps(), registerDefinedBetween(), regOverlapsSet(), removeKillInfo(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), ReplaceFrameIndex(), setRegMask(), false::Chain::str(), swapRegAndNonRegOperand(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tryOptimizeLEAtoMOV(), UpdateCPSRUse(), updatePhysDepsDownwards(), UseReg(), and VerifyLowRegs().

◆ isMBB()

bool llvm::MachineOperand::isMBB ( ) const
inline

◆ isMCSymbol()

bool llvm::MachineOperand::isMCSymbol ( ) const
inline

Definition at line 270 of file MachineOperand.h.

References MO_MCSymbol.

Referenced by getMCSymbol(), getOffset(), isSimilarDispOp(), isValidDispOp(), and setOffset().

◆ isMetadata()

bool llvm::MachineOperand::isMetadata ( ) const
inline

isMetadata - Tests if this is a MO_Metadata operand.

Definition at line 269 of file MachineOperand.h.

References MO_Metadata.

Referenced by llvm::MachineInstr::emitError(), EmitGCCInlineAsmStr(), EmitMSInlineAsmStr(), getMetadata(), matchPair(), llvm::MachineInstr::print(), printExtendedName(), and setMetadata().

◆ isPredicate()

bool llvm::MachineOperand::isPredicate ( ) const
inline

Definition at line 273 of file MachineOperand.h.

References MO_Predicate.

Referenced by getPredicate().

◆ isReg()

bool llvm::MachineOperand::isReg ( ) const
inline

isReg - Tests if this is a MO_Register operand.

Definition at line 241 of file MachineOperand.h.

References MO_Register.

Referenced by addLiveInRegs(), llvm::MachineInstr::addOperand(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterKilled(), addRegsToSet(), addTargetFlag(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::LiveRangeEdit::anyRematerializable(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), BuildInstOrderMap(), llvm::ScheduleDAGInstrs::buildSchedGraph(), canCombine(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), changeFCMPPredToAArch64CC(), ChangeToES(), ChangeToFPImmediate(), ChangeToFrameIndex(), ChangeToImmediate(), ChangeToMCSymbol(), ChangeToRegister(), ChangeToTargetIndex(), checkRegOnlyPHIInputs(), clobbersCTR(), collectDebugValues(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::HexagonEvaluator::composeWithSubRegIndex(), computeBytesPoppedByCalleeForSRet(), computeExprForSpill(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), llvm::MachineInstr::copyImplicitOps(), copyRegOperand(), countersNonZero(), countOperands(), llvm::createHexagonHardwareLoops(), llvm::createLanaiDelaySlotFillerPass(), createPHIsForCMOVsInSinkBB(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createSparcDelaySlotFillerPass(), llvm::createX86FixupLEAs(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), dumpMachineInstrRangeWithSlotIndex(), earlyUseOperand(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), EmitGCCInlineAsmStr(), EmitHiLo(), emitIndirectDst(), emitKill(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::SystemZPostRASchedStrategy::enterMBB(), eraseGPOpnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::InstructionSelector::executeMatchTable(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::DbgVariableLocation::extractFromMachineInstruction(), llvm::finalizeBundle(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), findDeadCallerSavedReg(), findDefIdx(), findNextInsertLocation(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::findTiedOperandIdx(), findUseIdx(), finishConvertToThreeAddress(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), for(), forceReg(), FuseInst(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::getAddressFromInstr(), llvm::RegBankSelect::getAnalysisUsage(), getBaseAddressRegister(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getCallTargetRegOpnd(), getCopyRewriter(), getDataDeps(), getDebugLocValue(), getDefRegMask(), getDwarfRegNum(), getFMAPatterns(), getFoldableImm(), getFPReg(), llvm::HexagonHazardRecognizer::getHazardType(), getImmOrMaterializedImm(), llvm::PPCInstrInfo::getInstrLatency(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), getInstrVecReg(), getLiveLanesAt(), getMaddPatterns(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMFHiLoOpc(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), getNonDebugInstr(), llvm::MachineInstr::getNumExplicitOperands(), getOModValue(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), getPostIncrementOperand(), getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), llvm::getRegState(), getRegsUsedByPHIs(), getShuffleComment(), llvm::HexagonInstrInfo::getSize(), llvm::X86InstrInfo::getSPAdjust(), getStoreTarget(), getSubOpcode(), getSubReg(), getTargetFlags(), getTypeToPrint(), getUnderlyingArgReg(), getUsedRegMask(), llvm::SIInstrInfo::getVALUOp(), llvm::PerFunctionMIParsingState::getVRegInfo(), getWinAllocaAmount(), llvm::LiveIntervals::handleMoveIntoBundle(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), hasInefficientLEABaseReg(), llvm::X86InstrInfo::hasLiveCondCodeDef(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasUseAfterLoop(), hasVGPROperands(), INITIALIZE_PASS(), InstructionStoresToFI(), llvm::Mips16RegisterInfo::intRegClass(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::InstructionSelector::isBaseWithConstantOffset(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::WebAssembly::isChild(), llvm::rdf::TargetOperandInfo::isClobbering(), isCompareZero(), isCopyFromExec(), isCopyToExec(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isDbgValueDescribedByReg(), isDead(), isDebug(), isDebug(), isDef(), isDescribedByReg(), isEarlyClobber(), llvm::AArch64InstrInfo::isFPRCopy(), isFullCopyOf(), isFullUndefDef(), isIdenticalOp(), llvm::MachineInstr::isIdenticalTo(), isImmValidForOpcode(), isImplicit(), isImplicitOperandIn(), llvm::MachineInstr::isIndirectDebugValue(), isInternalRead(), isKill(), llvm::isLeaMem(), isLEASimpleIncOrDec(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLegalVSrcOperand(), isLiveOut(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), isLogicalOpOnExec(), llvm::isMem(), isMemoryOp(), isMMSourceRegister(), isMMThreeBitGPRegister(), llvm::NVPTXInstrInfo::isMoveInstr(), llvm::InstructionSelector::isOperandImmEqual(), isOperandKill(), llvm::SIInstrInfo::isOperandLegal(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRegOperand(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::MachineInstr::isRegTiedToUseOperand(), IsSafeAndProfitableToMove(), llvm::X86InstrInfo::isSafeToClobberEFLAGS(), isSameReg(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleIf(), isSimpleIndexCalc(), IsSP(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), isSubregOf(), isTied(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTwoAddrUse(), isUndef(), isUse(), isUseSafeToFold(), isVGPR(), isVirtualRegisterOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::Mips16InstrInfo::loadImmediate(), llvm::SystemZMCInstLower::lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), lowerVECTOR_SHUFFLE_VSHF(), llvm::rdf::DataFlowGraph::makeRegRef(), matchPair(), mayLoadFromGOTOrConstantPool(), mergeOperations(), llvm::DebugLocEntry::MergeValues(), MIIsInTerminatorSequence(), MoveAndTeeForMultiUse(), llvm::MachineRegisterInfo::moveOperands(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::AggressiveAntiDepBreaker::Observe(), OneUseDominatesOtherUses(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), parseCond(), parseOperands(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::MachineInstr::print(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), printExtendedName(), profitImm(), readsReg(), readsVCCZ(), llvm::MachineInstr::readsWritesVirtualRegister(), regOverlapsSet(), llvm::R600SchedStrategy::releaseBottomNode(), RemoveDeadAddBetweenLEAAndJT(), removeKillInfo(), llvm::MachineInstr::RemoveOperand(), removePhis(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::PPCFrameLowering::replaceFPWithRealFP(), resultTests(), llvm::AMDGPUAsmPrinter::runOnMachineFunction(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::R600SchedStrategy::schedNode(), llvm::FastISel::selectIntrinsicCall(), setImplicit(), setIsDead(), setIsDebug(), setIsDef(), setIsEarlyClobber(), setIsInternalRead(), setIsKill(), setIsUndef(), llvm::X86InstrInfo::setSpecialOperandAttr(), setSubReg(), setTargetFlags(), shrinkScalarCompare(), SinkingPreventsImplicitNullCheck(), llvm::LiveDebugVariables::splitRegister(), false::Chain::str(), stripRegisterPrefix(), llvm::SystemZInstrInfo::SystemZInstrInfo(), TrackDefUses(), tryAddToFoldList(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::MachineInstr::untieRegOperand(), llvm::AntiDepBreaker::UpdateDbgValue(), updateOperand(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::HexagonSubtarget::usePredicatedCalls(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), X86SelectAddress(), and llvm::LiveDebugVariables::~LiveDebugVariables().

◆ isRegLiveOut()

bool llvm::MachineOperand::isRegLiveOut ( ) const
inline

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

Definition at line 267 of file MachineOperand.h.

References MO_RegisterLiveOut.

Referenced by getDwarfRegNum(), and getRegLiveOut().

◆ isRegMask()

bool llvm::MachineOperand::isRegMask ( ) const
inline

◆ isSymbol()

bool llvm::MachineOperand::isSymbol ( ) const
inline

◆ isTargetIndex()

bool llvm::MachineOperand::isTargetIndex ( ) const
inline

isTargetIndex - Tests if this is a MO_TargetIndex operand.

Definition at line 255 of file MachineOperand.h.

References MO_TargetIndex.

Referenced by getIndex(), getOffset(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isOperandLegal(), setIndex(), and setOffset().

◆ isTied()

bool llvm::MachineOperand::isTied ( ) const
inline

◆ isUndef()

bool llvm::MachineOperand::isUndef ( ) const
inline

Definition at line 314 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addExclusiveRegPair(), llvm::MachineInstr::addRegisterKilled(), addSegmentsWithValNo(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), ChangeToRegister(), llvm::X86InstrInfo::classifyLEAReg(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::convertToThreeAddress(), copyFlagsToImplicitVCC(), copyRegOperand(), CreateReg(), llvm::createSIWholeQuadModePass(), definesFullReg(), emitLoadM0FromVGPRLoop(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), GetDSubRegs(), getLiveLanesAt(), getMFHiLoOpc(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::getRegState(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::LiveIntervals::handleMoveIntoBundle(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::insertBranch(), InsertLDR_STR(), llvm::IsCPSRDead< MachineInstr >(), isLocalCopy(), isMemoryOp(), isSourceDefinedByImplicitDef(), isUseSafeToFold(), makeImplicit(), mayCombineMisaligned(), mergeOperations(), preserveCondRegFlags(), llvm::MIPrinter::print(), print(), readsReg(), readsVCCZ(), llvm::MachineInstr::readsWritesVirtualRegister(), regOverlapsSet(), llvm::R600SchedStrategy::releaseBottomNode(), removeDeadSegment(), ReplaceDominatedUses(), llvm::UnreachableBlockElimPass::run(), llvm::ThumbRegisterInfo::saveScavengerRegister(), setRegMask(), llvm::MachineBasicBlock::SplitCriticalEdge(), swapRegAndNonRegOperand(), llvm::SystemZInstrInfo::SystemZInstrInfo(), trySequenceOfOnes(), and updateOperand().

◆ isUse()

bool llvm::MachineOperand::isUse ( ) const
inline

Definition at line 289 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addOperand(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterKilled(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::canExecuteInBundle(), collectDebugValues(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyRegOperand(), countersNonZero(), llvm::createHexagonHardwareLoops(), llvm::createLanaiDelaySlotFillerPass(), llvm::createSparcDelaySlotFillerPass(), CriticalPathStep(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::findTiedOperandIdx(), llvm::TargetInstrInfo::foldMemoryOperand(), for(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), getCallTargetRegOpnd(), getLiveLanesAt(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::MachineInstr::getRegClassConstraint(), getUsedRegMask(), llvm::PerFunctionMIParsingState::getVRegInfo(), llvm::LiveIntervals::handleMoveIntoBundle(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), INITIALIZE_PASS(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isDebug(), isFullCopyOf(), isFullUndefDef(), isImmValidForOpcode(), isPromotableZeroStoreInst(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::X86InstrInfo::isSafeToClobberEFLAGS(), isSimpleIndexCalc(), isTwoAddrUse(), matchPair(), mayLoadFromGOTOrConstantPool(), MoveAndTeeForMultiUse(), multipleIterations(), parseOperands(), print(), readsReg(), readsVCCZ(), llvm::MachineInstr::readsWritesVirtualRegister(), regOverlapsSet(), RemoveDeadAddBetweenLEAAndJT(), removeDeadSegment(), removePhis(), resultTests(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::MachineInstr::tieOperands(), TrackDefUses(), llvm::HexagonSubtarget::usePredicatedCalls(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), and llvm::SIInstrInfo::verifyInstruction().

◆ print() [1/2]

void MachineOperand::print ( raw_ostream os,
const TargetRegisterInfo TRI = nullptr,
const TargetIntrinsicInfo IntrinsicInfo = nullptr 
) const

◆ print() [2/2]

void MachineOperand::print ( raw_ostream os,
ModuleSlotTracker MST,
const TargetRegisterInfo TRI = nullptr,
const TargetIntrinsicInfo IntrinsicInfo = nullptr 
) const

◆ readsReg()

bool llvm::MachineOperand::readsReg ( ) const
inline

readsReg - Returns true if this operand reads the previous value of its register.

A use operand with the <undef> flag set doesn't read its register. A sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set.

This refers to reading the register value from before the current instruction or bundle. Internal bundle reads are not included.

Definition at line 346 of file MachineOperand.h.

References assert(), getSubReg(), isInternalRead(), isReg(), isUndef(), isUse(), Reg, and setReg().

Referenced by llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::LiveRangeEdit::anyRematerializable(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::createCopyConstrainDAGMutation(), llvm::ConnectedVNInfoEqClasses::Distribute(), findUseIdx(), getDataDeps(), getLiveLanesAt(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::LiveVariables::HandleVirtRegDef(), isCrossCopy(), matchPair(), updatePhysDepsDownwards(), and updatePhysDepsUpwards().

◆ setFPImm()

void llvm::MachineOperand::setFPImm ( const ConstantFP CFP)
inline

Definition at line 535 of file MachineOperand.h.

References assert(), CFP, and isFPImm().

◆ setImm()

void llvm::MachineOperand::setImm ( int64_t  immVal)
inline

Definition at line 530 of file MachineOperand.h.

References assert(), and isImm().

Referenced by llvm::R600InstrInfo::addFlag(), AssignProtectedObjSet(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), changeFCMPPredToAArch64CC(), llvm::R600InstrInfo::clearFlag(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::createHexagonHardwareLoops(), CreateImm(), llvm::createSIWholeQuadModePass(), llvm::createX86OptimizeLEAs(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::SystemZInstrInfo::expandPostRAPseudo(), forceReg(), getLeaOP(), getLSMultipleTransferSize(), getOModValue(), llvm::AArch64InstrInfo::getOutliningType(), getReassignedChan(), getUnconditionalBrDisp(), hasOneNonDBGUseInst(), INITIALIZE_PASS(), llvm::R600InstrInfo::insertBranch(), isSubregOf(), multipleIterations(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::reduceLoopCount(), removePhis(), llvm::R600InstrInfo::reverseBranchCondition(), RewriteP2Align(), llvm::setDirectAddressInInstr(), llvm::X86InstrInfo::setFrameAdjustment(), llvm::R600InstrInfo::setImmOperand(), shrinkScalarCompare(), llvm::SIInstrInfo::swapSourceModifiers(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), llvm::HexagonPacketizerList::undoChangedOffset(), llvm::HexagonPacketizerList::useCalleesSP(), and llvm::HexagonPacketizerList::useCallersSP().

◆ setImplicit()

void llvm::MachineOperand::setImplicit ( bool  Val = true)
inline

◆ setIndex()

void llvm::MachineOperand::setIndex ( int  Idx)
inline

◆ setIsDead()

void llvm::MachineOperand::setIsDead ( bool  Val = true)
inline

◆ setIsDebug()

void llvm::MachineOperand::setIsDebug ( bool  Val = true)
inline

◆ setIsDef()

void MachineOperand::setIsDef ( bool  Val = true)

◆ setIsEarlyClobber()

void llvm::MachineOperand::setIsEarlyClobber ( bool  Val = true)
inline

◆ setIsInternalRead()

void llvm::MachineOperand::setIsInternalRead ( bool  Val = true)
inline

◆ setIsKill()

void llvm::MachineOperand::setIsKill ( bool  Val = true)
inline

◆ setIsUndef()

void llvm::MachineOperand::setIsUndef ( bool  Val = true)
inline

◆ setIsUse()

void llvm::MachineOperand::setIsUse ( bool  Val = true)
inline

Definition at line 378 of file MachineOperand.h.

References setIsDef(), and Val.

◆ setMBB()

void llvm::MachineOperand::setMBB ( MachineBasicBlock MBB)
inline

◆ setMetadata()

void llvm::MachineOperand::setMetadata ( const MDNode MD)
inline

Definition at line 554 of file MachineOperand.h.

References assert(), isMetadata(), and MD.

Referenced by AssignProtectedObjSet(), and llvm::updateDbgValueForSpill().

◆ setOffset()

void llvm::MachineOperand::setOffset ( int64_t  Offset)
inline

◆ setReg()

void MachineOperand::setReg ( unsigned  Reg)

Change the register this operand corresponds to.

Definition at line 87 of file MachineInstr.cpp.

References llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::MachineBasicBlock::getParent(), getParent(), getReg(), MBB, MI, MRI, Reg, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced by addSegmentsWithValNo(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), changeFCMPPredToAArch64CC(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), computeBytesPoppedByCalleeForSRet(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), copyRegOperand(), createBBSelectReg(), llvm::createHexagonHardwareLoops(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createWebAssemblyReplacePhysRegs(), llvm::createX86OptimizeLEAs(), llvm::ConnectedVNInfoEqClasses::Distribute(), llvm::SparcRegisterInfo::eliminateFrameIndex(), emitPostSt(), eraseGPOpnd(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), FindStartOfTree(), llvm::fixStackStores(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), getRegClassFromGRPhysReg(), getRegsUsedByPHIs(), getTag(), INITIALIZE_PASS(), InsertLDR_STR(), insertPHI(), isFullCopyOf(), isFullUndefDef(), isImmValidForOpcode(), isPromotableZeroStoreInst(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::X86CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), MaybeRewriteToDrop(), MaybeRewriteToFallthrough(), MoveAndTeeForMultiUse(), MoveForSingleUse(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), readsReg(), registerDefinedBetween(), regOverlapsSet(), RematerializeCheapDef(), removeDeadSegment(), removeExternalCFGEdges(), removePhis(), ReplaceDominatedUses(), llvm::PPCFrameLowering::replaceFPWithRealFP(), replaceRegUsesAfterLoop(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::MachineSSAUpdater::RewriteUse(), llvm::rdf::CopyPropagation::run(), llvm::Localizer::runOnMachineFunction(), llvm::setDirectAddressInInstr(), llvm::LiveDebugVariables::splitRegister(), false::Chain::str(), substPhysReg(), substVirtReg(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), llvm::AntiDepBreaker::UpdateDbgValue(), and llvm::LegalizerHelper::widenScalar().

◆ setRegMask()

void llvm::MachineOperand::setRegMask ( const uint32_t RegMaskPtr)
inline

Sets value of register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand. See CreateRegMask(). Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line 568 of file MachineOperand.h.

References assert(), ChangeToES(), ChangeToFPImmediate(), ChangeToFrameIndex(), ChangeToImmediate(), ChangeToMCSymbol(), ChangeToRegister(), ChangeToTargetIndex(), hash_value, ImmVal, isDead(), isDebug(), isDef(), isIdenticalTo(), isKill(), isRegMask(), isUndef(), Other, and Sym.

◆ setSubReg()

void llvm::MachineOperand::setSubReg ( unsigned  subReg)
inline

◆ setTargetFlags()

void llvm::MachineOperand::setTargetFlags ( unsigned  F)
inline

◆ substPhysReg()

void MachineOperand::substPhysReg ( unsigned  Reg,
const TargetRegisterInfo TRI 
)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account.

For instance, substPhysReg(EAX) will change reg1024:sub_8bit to AL.

Definition at line 117 of file MachineInstr.cpp.

References assert(), getSubReg(), llvm::MCRegisterInfo::getSubReg(), isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), setIsUndef(), setReg(), and setSubReg().

Referenced by addSegmentsWithValNo(), getRegClassFromGRPhysReg(), llvm::MachineRegisterInfo::replaceRegWith(), setSubReg(), and llvm::LiveDebugVariables::splitRegister().

◆ substVirtReg()

void MachineOperand::substVirtReg ( unsigned  Reg,
unsigned  SubIdx,
const TargetRegisterInfo TRI 
)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

Take any existing SubReg index into account, using TargetRegisterInfo to compose the subreg indices if necessary. Reg must be a virtual register, SubIdx can be 0.

Definition at line 107 of file MachineInstr.cpp.

References assert(), llvm::TargetRegisterInfo::composeSubRegIndices(), getSubReg(), llvm::TargetRegisterInfo::isVirtualRegister(), setReg(), and setSubReg().

Referenced by setSubReg(), and updateOperand().

Friends And Related Function Documentation

◆ DenseMapInfo< MachineOperand >

friend struct DenseMapInfo< MachineOperand >
friend

Definition at line 792 of file MachineOperand.h.

◆ hash_value

hash_code hash_value ( const MachineOperand MO)
friend

MachineOperand hash_value overload.

Note that this includes the same information in the hash that isIdenticalTo uses for comparison. It is thus suited for use in hash tables which use that function for equality comparisons only.

Referenced by llvm::DenseMapInfo< MachineOperand >::getHashValue(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::operator<<(), and setRegMask().

◆ MachineInstr

friend class MachineInstr
friend

Definition at line 781 of file MachineOperand.h.

◆ MachineRegisterInfo

friend class MachineRegisterInfo
friend

Definition at line 782 of file MachineOperand.h.

Member Data Documentation

◆ BA

const BlockAddress* llvm::MachineOperand::BA

Definition at line 185 of file MachineOperand.h.

Referenced by CreateBA().

◆ CFIIndex

unsigned llvm::MachineOperand::CFIIndex

Definition at line 168 of file MachineOperand.h.

Referenced by CreateCFIIndex().

◆ CFP

const ConstantFP* llvm::MachineOperand::CFP

Definition at line 162 of file MachineOperand.h.

Referenced by CreateFPImm(), and setFPImm().

◆ CI

const ConstantInt* llvm::MachineOperand::CI

Definition at line 163 of file MachineOperand.h.

Referenced by CreateCImm(), and llvm::MachineInstr::emitError().

◆ GV

const GlobalValue* llvm::MachineOperand::GV

Definition at line 184 of file MachineOperand.h.

Referenced by CreateGA().

◆ ImmVal

int64_t llvm::MachineOperand::ImmVal

Definition at line 164 of file MachineOperand.h.

Referenced by ChangeToImmediate(), and setRegMask().

◆ Index

int llvm::MachineOperand::Index

Definition at line 182 of file MachineOperand.h.

◆ IntrinsicID

Intrinsic::ID llvm::MachineOperand::IntrinsicID

Definition at line 169 of file MachineOperand.h.

Referenced by CreateIntrinsicID().

◆ MBB

MachineBasicBlock* llvm::MachineOperand::MBB

◆ MD

const MDNode* llvm::MachineOperand::MD

Definition at line 166 of file MachineOperand.h.

Referenced by CreateMetadata(), and setMetadata().

◆ Next

MachineOperand* llvm::MachineOperand::Next

Definition at line 175 of file MachineOperand.h.

◆ OffsetedInfo

struct { ... } llvm::MachineOperand::OffsetedInfo

OffsetedInfo - This struct contains the offset and an object identifier.

this represent the object as with an optional offset from it.

Referenced by CreateBA(), CreateES(), and CreateGA().

◆ OffsetHi

int llvm::MachineOperand::OffsetHi

Definition at line 188 of file MachineOperand.h.

◆ OffsetLo

unsigned llvm::MachineOperand::OffsetLo

Definition at line 152 of file MachineOperand.h.

◆ Pred

unsigned llvm::MachineOperand::Pred

◆ Prev

MachineOperand* llvm::MachineOperand::Prev

Definition at line 174 of file MachineOperand.h.

◆ Reg

struct { ... } llvm::MachineOperand::Reg

◆ RegMask

const uint32_t* llvm::MachineOperand::RegMask

Definition at line 165 of file MachineOperand.h.

Referenced by CreateRegLiveOut(), CreateRegMask(), and isIdenticalTo().

◆ RegNo

unsigned llvm::MachineOperand::RegNo

Definition at line 151 of file MachineOperand.h.

Referenced by CreateReg().

◆ Sym

MCSymbol* llvm::MachineOperand::Sym

Definition at line 167 of file MachineOperand.h.

Referenced by ChangeToMCSymbol(), CreateMCSymbol(), and setRegMask().

◆ SymbolName

const char* llvm::MachineOperand::SymbolName

Definition at line 183 of file MachineOperand.h.

◆ Val

union { ... } llvm::MachineOperand::Val

The documentation for this class was generated from the following files: