LLVM  8.0.0svn
AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
19 #include "AArch64Subtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/DiagnosticInfo.h"
32 
33 using namespace llvm;
34 
35 #define GET_REGINFO_TARGET_DESC
36 #include "AArch64GenRegisterInfo.inc"
37 
39  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
41 }
42 
43 const MCPhysReg *
45  assert(MF && "Invalid MachineFunction pointer.");
47  // GHC set of callee saved regs is empty as all those regs are
48  // used for passing STG regs around
49  return CSR_AArch64_NoRegs_SaveList;
51  return CSR_AArch64_AllRegs_SaveList;
53  return CSR_AArch64_AAVPCS_SaveList;
55  return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
56  CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
57  CSR_AArch64_CXX_TLS_Darwin_SaveList;
59  ->supportSwiftError() &&
61  Attribute::SwiftError))
62  return CSR_AArch64_AAPCS_SwiftError_SaveList;
64  return CSR_AArch64_RT_MostRegs_SaveList;
65  else
66  return CSR_AArch64_AAPCS_SaveList;
67 }
68 
70  const MachineFunction *MF) const {
71  assert(MF && "Invalid MachineFunction pointer.");
73  MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
74  return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
75  return nullptr;
76 }
77 
79  MachineFunction &MF) const {
80  const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
81  SmallVector<MCPhysReg, 32> UpdatedCSRs;
82  for (const MCPhysReg *I = CSRs; *I; ++I)
83  UpdatedCSRs.push_back(*I);
84 
85  for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
87  UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
88  }
89  }
90  // Register lists are zero-terminated.
91  UpdatedCSRs.push_back(0);
92  MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
93 }
94 
95 const TargetRegisterClass *
97  unsigned Idx) const {
98  // edge case for GPR/FPR register classes
99  if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
100  return &AArch64::FPR32RegClass;
101  else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
102  return &AArch64::FPR64RegClass;
103 
104  // Forward to TableGen's default version.
105  return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
106 }
107 
108 const uint32_t *
110  CallingConv::ID CC) const {
111  bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
112  if (CC == CallingConv::GHC)
113  // This is academic because all GHC calls are (supposed to be) tail calls
114  return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
115  if (CC == CallingConv::AnyReg)
116  return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
117  if (CC == CallingConv::CXX_FAST_TLS)
118  return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
119  : CSR_AArch64_CXX_TLS_Darwin_RegMask;
121  return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
123  ->supportSwiftError() &&
124  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
125  return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
126  : CSR_AArch64_AAPCS_SwiftError_RegMask;
127  if (CC == CallingConv::PreserveMost)
128  return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
129  : CSR_AArch64_RT_MostRegs_RegMask;
130  else
131  return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
132 }
133 
135  if (TT.isOSDarwin())
136  return CSR_AArch64_TLS_Darwin_RegMask;
137 
138  assert(TT.isOSBinFormatELF() && "Invalid target");
139  return CSR_AArch64_TLS_ELF_RegMask;
140 }
141 
143  const uint32_t **Mask) const {
144  uint32_t *UpdatedMask = MF.allocateRegMask();
145  unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
146  memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
147 
148  for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
150  for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),
151  this, true);
152  SubReg.isValid(); ++SubReg) {
153  // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
154  // register mask.
155  UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
156  }
157  }
158  }
159  *Mask = UpdatedMask;
160 }
161 
162 const uint32_t *
164  CallingConv::ID CC) const {
165  // This should return a register mask that is the same as that returned by
166  // getCallPreservedMask but that additionally preserves the register used for
167  // the first i64 argument (which must also be the register used to return a
168  // single i64 return value)
169  //
170  // In case that the calling convention does not use the same register for
171  // both, the function should return NULL (does not currently apply)
172  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
173  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
174 }
175 
177  return CSR_AArch64_StackProbe_Windows_RegMask;
178 }
179 
180 BitVector
182  const AArch64FrameLowering *TFI = getFrameLowering(MF);
183 
184  // FIXME: avoid re-calculating this every time.
185  BitVector Reserved(getNumRegs());
186  markSuperRegs(Reserved, AArch64::WSP);
187  markSuperRegs(Reserved, AArch64::WZR);
188 
189  if (TFI->hasFP(MF) || TT.isOSDarwin())
190  markSuperRegs(Reserved, AArch64::W29);
191 
192  for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
194  markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
195  }
196 
197  if (hasBasePointer(MF))
198  markSuperRegs(Reserved, AArch64::W19);
199 
200  assert(checkAllSuperRegsMarked(Reserved));
201  return Reserved;
202 }
203 
205  unsigned Reg) const {
206  return getReservedRegs(MF)[Reg];
207 }
208 
210  // FIXME: Get the list of argument registers from TableGen.
211  static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
212  AArch64::X3, AArch64::X4, AArch64::X5,
213  AArch64::X6, AArch64::X7 };
214  return std::any_of(std::begin(GPRArgRegs), std::end(GPRArgRegs),
215  [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});
216 }
217 
219  const MachineFunction &MF) const {
220  const Function &F = MF.getFunction();
221  F.getContext().diagnose(DiagnosticInfoUnsupported{F, "AArch64 doesn't support"
222  " function calls if any of the argument registers is reserved."});
223 }
224 
226  unsigned PhysReg) const {
227  return !isReservedReg(MF, PhysReg);
228 }
229 
230 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
231  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
232 }
233 
234 const TargetRegisterClass *
236  unsigned Kind) const {
237  return &AArch64::GPR64spRegClass;
238 }
239 
240 const TargetRegisterClass *
242  if (RC == &AArch64::CCRRegClass)
243  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
244  return RC;
245 }
246 
247 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
248 
250  const MachineFrameInfo &MFI = MF.getFrameInfo();
251 
252  // In the presence of variable sized objects, if the fixed stack size is
253  // large enough that referencing from the FP won't result in things being
254  // in range relatively often, we can use a base pointer to allow access
255  // from the other direction like the SP normally works.
256  // Furthermore, if both variable sized objects are present, and the
257  // stack needs to be dynamically re-aligned, the base pointer is the only
258  // reliable way to reference the locals.
259  if (MFI.hasVarSizedObjects()) {
260  if (needsStackRealignment(MF))
261  return true;
262  // Conservatively estimate whether the negative offset from the frame
263  // pointer will be sufficient to reach. If a function has a smallish
264  // frame, it's less likely to have lots of spills and callee saved
265  // space, so it's all more likely to be within range of the frame pointer.
266  // If it's wrong, we'll materialize the constant and still get to the
267  // object; it's just suboptimal. Negative offsets use the unscaled
268  // load/store instructions, which have a 9-bit signed immediate.
269  return MFI.getLocalFrameSize() >= 256;
270  }
271 
272  return false;
273 }
274 
275 unsigned
277  const AArch64FrameLowering *TFI = getFrameLowering(MF);
278  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
279 }
280 
282  const MachineFunction &MF) const {
283  return true;
284 }
285 
287  const MachineFunction &MF) const {
288  return true;
289 }
290 
291 bool
293  // This function indicates whether the emergency spillslot should be placed
294  // close to the beginning of the stackframe (closer to FP) or the end
295  // (closer to SP).
296  //
297  // The beginning works most reliably if we have a frame pointer.
298  const AArch64FrameLowering &TFI = *getFrameLowering(MF);
299  return TFI.hasFP(MF);
300 }
301 
303  const MachineFunction &MF) const {
304  return true;
305 }
306 
307 bool
309  const MachineFrameInfo &MFI = MF.getFrameInfo();
311  return true;
312  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
313 }
314 
315 /// needsFrameBaseReg - Returns true if the instruction's frame index
316 /// reference would be better served by a base register other than FP
317 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
318 /// references it should create new base registers for.
320  int64_t Offset) const {
321  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
322  assert(i < MI->getNumOperands() &&
323  "Instr doesn't have FrameIndex operand!");
324 
325  // It's the load/store FI references that cause issues, as it can be difficult
326  // to materialize the offset if it won't fit in the literal field. Estimate
327  // based on the size of the local frame and some conservative assumptions
328  // about the rest of the stack frame (note, this is pre-regalloc, so
329  // we don't know everything for certain yet) whether this offset is likely
330  // to be out of range of the immediate. Return true if so.
331 
332  // We only generate virtual base registers for loads and stores, so
333  // return false for everything else.
334  if (!MI->mayLoad() && !MI->mayStore())
335  return false;
336 
337  // Without a virtual base register, if the function has variable sized
338  // objects, all fixed-size local references will be via the frame pointer,
339  // Approximate the offset and see if it's legal for the instruction.
340  // Note that the incoming offset is based on the SP value at function entry,
341  // so it'll be negative.
342  MachineFunction &MF = *MI->getParent()->getParent();
343  const AArch64FrameLowering *TFI = getFrameLowering(MF);
344  MachineFrameInfo &MFI = MF.getFrameInfo();
345 
346  // Estimate an offset from the frame pointer.
347  // Conservatively assume all GPR callee-saved registers get pushed.
348  // FP, LR, X19-X28, D8-D15. 64-bits each.
349  int64_t FPOffset = Offset - 16 * 20;
350  // Estimate an offset from the stack pointer.
351  // The incoming offset is relating to the SP at the start of the function,
352  // but when we access the local it'll be relative to the SP after local
353  // allocation, so adjust our SP-relative offset by that allocation size.
354  Offset += MFI.getLocalFrameSize();
355  // Assume that we'll have at least some spill slots allocated.
356  // FIXME: This is a total SWAG number. We should run some statistics
357  // and pick a real one.
358  Offset += 128; // 128 bytes of spill slots
359 
360  // If there is a frame pointer, try using it.
361  // The FP is only available if there is no dynamic realignment. We
362  // don't know for sure yet whether we'll need that, so we guess based
363  // on whether there are any local variables that would trigger it.
364  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
365  return false;
366 
367  // If we can reference via the stack pointer or base pointer, try that.
368  // FIXME: This (and the code that resolves the references) can be improved
369  // to only disallow SP relative references in the live range of
370  // the VLA(s). In practice, it's unclear how much difference that
371  // would make, but it may be worth doing.
372  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
373  return false;
374 
375  // The offset likely isn't legal; we want to allocate a virtual base register.
376  return true;
377 }
378 
380  unsigned BaseReg,
381  int64_t Offset) const {
382  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
383  assert(MI && "Unable to get the legal offset for nil instruction.");
384  int SaveOffset = Offset;
385  return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
386 }
387 
388 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
389 /// at the beginning of the basic block.
391  unsigned BaseReg,
392  int FrameIdx,
393  int64_t Offset) const {
395  DebugLoc DL; // Defaults to "unknown"
396  if (Ins != MBB->end())
397  DL = Ins->getDebugLoc();
398  const MachineFunction &MF = *MBB->getParent();
399  const AArch64InstrInfo *TII =
400  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
401  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
403  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
404  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
405 
406  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
407  .addFrameIndex(FrameIdx)
408  .addImm(Offset)
409  .addImm(Shifter);
410 }
411 
413  int64_t Offset) const {
414  int Off = Offset; // ARM doesn't need the general 64-bit offsets
415  unsigned i = 0;
416 
417  while (!MI.getOperand(i).isFI()) {
418  ++i;
419  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
420  }
421  const MachineFunction *MF = MI.getParent()->getParent();
422  const AArch64InstrInfo *TII =
423  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
424  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
425  assert(Done && "Unable to resolve frame index!");
426  (void)Done;
427 }
428 
430  int SPAdj, unsigned FIOperandNum,
431  RegScavenger *RS) const {
432  assert(SPAdj == 0 && "Unexpected");
433 
434  MachineInstr &MI = *II;
435  MachineBasicBlock &MBB = *MI.getParent();
436  MachineFunction &MF = *MBB.getParent();
437  const AArch64InstrInfo *TII =
438  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
439  const AArch64FrameLowering *TFI = getFrameLowering(MF);
440 
441  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
442  unsigned FrameReg;
443  int Offset;
444 
445  // Special handling of dbg_value, stackmap and patchpoint instructions.
446  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
447  MI.getOpcode() == TargetOpcode::PATCHPOINT) {
448  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
449  /*PreferFP=*/true);
450  Offset += MI.getOperand(FIOperandNum + 1).getImm();
451  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
452  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
453  return;
454  }
455 
456  // Modify MI as necessary to handle as much of 'Offset' as possible
457  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
458  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
459  return;
460 
461  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
462  "Emergency spill slot is out of reach");
463 
464  // If we get here, the immediate doesn't fit into the instruction. We folded
465  // as much as possible above. Handle the rest, providing a register that is
466  // SP+LargeImm.
467  unsigned ScratchReg =
468  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
469  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
470  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
471 }
472 
474  MachineFunction &MF) const {
475  const AArch64FrameLowering *TFI = getFrameLowering(MF);
476 
477  switch (RC->getID()) {
478  default:
479  return 0;
480  case AArch64::GPR32RegClassID:
481  case AArch64::GPR32spRegClassID:
482  case AArch64::GPR32allRegClassID:
483  case AArch64::GPR64spRegClassID:
484  case AArch64::GPR64allRegClassID:
485  case AArch64::GPR64RegClassID:
486  case AArch64::GPR32commonRegClassID:
487  case AArch64::GPR64commonRegClassID:
488  return 32 - 1 // XZR/SP
489  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
491  - hasBasePointer(MF); // X19
492  case AArch64::FPR8RegClassID:
493  case AArch64::FPR16RegClassID:
494  case AArch64::FPR32RegClassID:
495  case AArch64::FPR64RegClassID:
496  case AArch64::FPR128RegClassID:
497  return 32;
498 
499  case AArch64::DDRegClassID:
500  case AArch64::DDDRegClassID:
501  case AArch64::DDDDRegClassID:
502  case AArch64::QQRegClassID:
503  case AArch64::QQQRegClassID:
504  case AArch64::QQQQRegClassID:
505  return 32;
506 
507  case AArch64::FPR128_loRegClassID:
508  return 16;
509  }
510 }
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Diagnostic information for unsupported feature in backend.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:592
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
bool cannotEliminateFrame(const MachineFunction &MF) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned Reg
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
A debug info location.
Definition: DebugLoc.h:34
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isAnyArgRegReserved(const MachineFunction &MF) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned SubReg
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
unsigned getID() const
Return the register class ID number.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
AArch64RegisterInfo(const Triple &TT)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:224
static const MCPhysReg GPRArgRegs[]
bool isXRegisterReserved(size_t i) const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1049
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
MCSubRegIterator enumerates all sub-registers of Reg.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
bool isDebugValue() const
Definition: MachineInstr.h:997
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getNumXRegisterReserved() const
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
BitVector getReservedRegs(const MachineFunction &MF) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
void emitReservedArgRegCallError(const MachineFunction &MF) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetOptions Options
Definition: TargetMachine.h:97
#define I(x, y, z)
Definition: MD5.cpp:58
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const uint32_t * getTLSCallPreservedMask() const
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const unsigned Kind
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isConstantPhysReg(unsigned PhysReg) const override
bool hasBasePointer(const MachineFunction &MF) const
bool isXRegCustomCalleeSaved(size_t i) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
bool isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...