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AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
19 #include "AArch64Subtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Function.h"
31 
32 using namespace llvm;
33 
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
36 
38  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
40 }
41 
42 const MCPhysReg *
44  assert(MF && "Invalid MachineFunction pointer.");
46  // GHC set of callee saved regs is empty as all those regs are
47  // used for passing STG regs around
48  return CSR_AArch64_NoRegs_SaveList;
50  return CSR_AArch64_AllRegs_SaveList;
52  return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
53  CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
54  CSR_AArch64_CXX_TLS_Darwin_SaveList;
56  ->supportSwiftError() &&
58  Attribute::SwiftError))
59  return CSR_AArch64_AAPCS_SwiftError_SaveList;
61  return CSR_AArch64_RT_MostRegs_SaveList;
62  else
63  return CSR_AArch64_AAPCS_SaveList;
64 }
65 
67  const MachineFunction *MF) const {
68  assert(MF && "Invalid MachineFunction pointer.");
70  MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
71  return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
72  return nullptr;
73 }
74 
75 const uint32_t *
77  CallingConv::ID CC) const {
78  if (CC == CallingConv::GHC)
79  // This is academic because all GHC calls are (supposed to be) tail calls
80  return CSR_AArch64_NoRegs_RegMask;
81  if (CC == CallingConv::AnyReg)
82  return CSR_AArch64_AllRegs_RegMask;
83  if (CC == CallingConv::CXX_FAST_TLS)
84  return CSR_AArch64_CXX_TLS_Darwin_RegMask;
86  ->supportSwiftError() &&
87  MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
88  return CSR_AArch64_AAPCS_SwiftError_RegMask;
89  if (CC == CallingConv::PreserveMost)
90  return CSR_AArch64_RT_MostRegs_RegMask;
91  else
92  return CSR_AArch64_AAPCS_RegMask;
93 }
94 
96  if (TT.isOSDarwin())
97  return CSR_AArch64_TLS_Darwin_RegMask;
98 
99  assert(TT.isOSBinFormatELF() && "Invalid target");
100  return CSR_AArch64_TLS_ELF_RegMask;
101 }
102 
103 const uint32_t *
105  CallingConv::ID CC) const {
106  // This should return a register mask that is the same as that returned by
107  // getCallPreservedMask but that additionally preserves the register used for
108  // the first i64 argument (which must also be the register used to return a
109  // single i64 return value)
110  //
111  // In case that the calling convention does not use the same register for
112  // both, the function should return NULL (does not currently apply)
113  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
114  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
115 }
116 
117 BitVector
119  const AArch64FrameLowering *TFI = getFrameLowering(MF);
120 
121  // FIXME: avoid re-calculating this every time.
122  BitVector Reserved(getNumRegs());
123  markSuperRegs(Reserved, AArch64::WSP);
124  markSuperRegs(Reserved, AArch64::WZR);
125 
126  if (TFI->hasFP(MF) || TT.isOSDarwin())
127  markSuperRegs(Reserved, AArch64::W29);
128 
130  markSuperRegs(Reserved, AArch64::W18); // Platform register
131 
132  if (hasBasePointer(MF))
133  markSuperRegs(Reserved, AArch64::W19);
134 
135  assert(checkAllSuperRegsMarked(Reserved));
136  return Reserved;
137 }
138 
140  unsigned Reg) const {
141  const AArch64FrameLowering *TFI = getFrameLowering(MF);
142 
143  switch (Reg) {
144  default:
145  break;
146  case AArch64::SP:
147  case AArch64::XZR:
148  case AArch64::WSP:
149  case AArch64::WZR:
150  return true;
151  case AArch64::X18:
152  case AArch64::W18:
153  return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
154  case AArch64::FP:
155  case AArch64::W29:
156  return TFI->hasFP(MF) || TT.isOSDarwin();
157  case AArch64::W19:
158  case AArch64::X19:
159  return hasBasePointer(MF);
160  }
161 
162  return false;
163 }
164 
165 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
166  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
167 }
168 
169 const TargetRegisterClass *
171  unsigned Kind) const {
172  return &AArch64::GPR64spRegClass;
173 }
174 
175 const TargetRegisterClass *
177  if (RC == &AArch64::CCRRegClass)
178  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
179  return RC;
180 }
181 
182 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
183 
185  const MachineFrameInfo &MFI = MF.getFrameInfo();
186 
187  // In the presence of variable sized objects, if the fixed stack size is
188  // large enough that referencing from the FP won't result in things being
189  // in range relatively often, we can use a base pointer to allow access
190  // from the other direction like the SP normally works.
191  // Furthermore, if both variable sized objects are present, and the
192  // stack needs to be dynamically re-aligned, the base pointer is the only
193  // reliable way to reference the locals.
194  if (MFI.hasVarSizedObjects()) {
195  if (needsStackRealignment(MF))
196  return true;
197  // Conservatively estimate whether the negative offset from the frame
198  // pointer will be sufficient to reach. If a function has a smallish
199  // frame, it's less likely to have lots of spills and callee saved
200  // space, so it's all more likely to be within range of the frame pointer.
201  // If it's wrong, we'll materialize the constant and still get to the
202  // object; it's just suboptimal. Negative offsets use the unscaled
203  // load/store instructions, which have a 9-bit signed immediate.
204  return MFI.getLocalFrameSize() >= 256;
205  }
206 
207  return false;
208 }
209 
210 unsigned
212  const AArch64FrameLowering *TFI = getFrameLowering(MF);
213  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
214 }
215 
217  const MachineFunction &MF) const {
218  return true;
219 }
220 
222  const MachineFunction &MF) const {
223  return true;
224 }
225 
226 bool
228  const MachineFrameInfo &MFI = MF.getFrameInfo();
229  // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
230  // to the stack pointer, so only put the emergency spill slot next to the
231  // FP when there's no better way to access it (SP or base pointer).
232  return MFI.hasVarSizedObjects() && !hasBasePointer(MF);
233 }
234 
236  const MachineFunction &MF) const {
237  return true;
238 }
239 
240 bool
242  const MachineFrameInfo &MFI = MF.getFrameInfo();
244  return true;
245  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
246 }
247 
248 /// needsFrameBaseReg - Returns true if the instruction's frame index
249 /// reference would be better served by a base register other than FP
250 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
251 /// references it should create new base registers for.
253  int64_t Offset) const {
254  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
255  assert(i < MI->getNumOperands() &&
256  "Instr doesn't have FrameIndex operand!");
257 
258  // It's the load/store FI references that cause issues, as it can be difficult
259  // to materialize the offset if it won't fit in the literal field. Estimate
260  // based on the size of the local frame and some conservative assumptions
261  // about the rest of the stack frame (note, this is pre-regalloc, so
262  // we don't know everything for certain yet) whether this offset is likely
263  // to be out of range of the immediate. Return true if so.
264 
265  // We only generate virtual base registers for loads and stores, so
266  // return false for everything else.
267  if (!MI->mayLoad() && !MI->mayStore())
268  return false;
269 
270  // Without a virtual base register, if the function has variable sized
271  // objects, all fixed-size local references will be via the frame pointer,
272  // Approximate the offset and see if it's legal for the instruction.
273  // Note that the incoming offset is based on the SP value at function entry,
274  // so it'll be negative.
275  MachineFunction &MF = *MI->getParent()->getParent();
276  const AArch64FrameLowering *TFI = getFrameLowering(MF);
277  MachineFrameInfo &MFI = MF.getFrameInfo();
278 
279  // Estimate an offset from the frame pointer.
280  // Conservatively assume all GPR callee-saved registers get pushed.
281  // FP, LR, X19-X28, D8-D15. 64-bits each.
282  int64_t FPOffset = Offset - 16 * 20;
283  // Estimate an offset from the stack pointer.
284  // The incoming offset is relating to the SP at the start of the function,
285  // but when we access the local it'll be relative to the SP after local
286  // allocation, so adjust our SP-relative offset by that allocation size.
287  Offset += MFI.getLocalFrameSize();
288  // Assume that we'll have at least some spill slots allocated.
289  // FIXME: This is a total SWAG number. We should run some statistics
290  // and pick a real one.
291  Offset += 128; // 128 bytes of spill slots
292 
293  // If there is a frame pointer, try using it.
294  // The FP is only available if there is no dynamic realignment. We
295  // don't know for sure yet whether we'll need that, so we guess based
296  // on whether there are any local variables that would trigger it.
297  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
298  return false;
299 
300  // If we can reference via the stack pointer or base pointer, try that.
301  // FIXME: This (and the code that resolves the references) can be improved
302  // to only disallow SP relative references in the live range of
303  // the VLA(s). In practice, it's unclear how much difference that
304  // would make, but it may be worth doing.
305  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
306  return false;
307 
308  // The offset likely isn't legal; we want to allocate a virtual base register.
309  return true;
310 }
311 
313  unsigned BaseReg,
314  int64_t Offset) const {
315  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
316  assert(MI && "Unable to get the legal offset for nil instruction.");
317  int SaveOffset = Offset;
318  return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
319 }
320 
321 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
322 /// at the beginning of the basic block.
324  unsigned BaseReg,
325  int FrameIdx,
326  int64_t Offset) const {
328  DebugLoc DL; // Defaults to "unknown"
329  if (Ins != MBB->end())
330  DL = Ins->getDebugLoc();
331  const MachineFunction &MF = *MBB->getParent();
332  const AArch64InstrInfo *TII =
333  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
334  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
336  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
337  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
338 
339  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
340  .addFrameIndex(FrameIdx)
341  .addImm(Offset)
342  .addImm(Shifter);
343 }
344 
346  int64_t Offset) const {
347  int Off = Offset; // ARM doesn't need the general 64-bit offsets
348  unsigned i = 0;
349 
350  while (!MI.getOperand(i).isFI()) {
351  ++i;
352  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
353  }
354  const MachineFunction *MF = MI.getParent()->getParent();
355  const AArch64InstrInfo *TII =
356  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
357  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
358  assert(Done && "Unable to resolve frame index!");
359  (void)Done;
360 }
361 
363  int SPAdj, unsigned FIOperandNum,
364  RegScavenger *RS) const {
365  assert(SPAdj == 0 && "Unexpected");
366 
367  MachineInstr &MI = *II;
368  MachineBasicBlock &MBB = *MI.getParent();
369  MachineFunction &MF = *MBB.getParent();
370  const AArch64InstrInfo *TII =
371  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
372  const AArch64FrameLowering *TFI = getFrameLowering(MF);
373 
374  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
375  unsigned FrameReg;
376  int Offset;
377 
378  // Special handling of dbg_value, stackmap and patchpoint instructions.
379  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
380  MI.getOpcode() == TargetOpcode::PATCHPOINT) {
381  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
382  /*PreferFP=*/true);
383  Offset += MI.getOperand(FIOperandNum + 1).getImm();
384  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
385  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
386  return;
387  }
388 
389  // Modify MI as necessary to handle as much of 'Offset' as possible
390  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
391  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
392  return;
393 
394  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
395  "Emergency spill slot is out of reach");
396 
397  // If we get here, the immediate doesn't fit into the instruction. We folded
398  // as much as possible above. Handle the rest, providing a register that is
399  // SP+LargeImm.
400  unsigned ScratchReg =
401  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
402  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
403  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
404 }
405 
407  MachineFunction &MF) const {
408  const AArch64FrameLowering *TFI = getFrameLowering(MF);
409 
410  switch (RC->getID()) {
411  default:
412  return 0;
413  case AArch64::GPR32RegClassID:
414  case AArch64::GPR32spRegClassID:
415  case AArch64::GPR32allRegClassID:
416  case AArch64::GPR64spRegClassID:
417  case AArch64::GPR64allRegClassID:
418  case AArch64::GPR64RegClassID:
419  case AArch64::GPR32commonRegClassID:
420  case AArch64::GPR64commonRegClassID:
421  return 32 - 1 // XZR/SP
422  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
424  .isX18Reserved() // X18 reserved as platform register
425  - hasBasePointer(MF); // X19
426  case AArch64::FPR8RegClassID:
427  case AArch64::FPR16RegClassID:
428  case AArch64::FPR32RegClassID:
429  case AArch64::FPR64RegClassID:
430  case AArch64::FPR128RegClassID:
431  return 32;
432 
433  case AArch64::DDRegClassID:
434  case AArch64::DDDRegClassID:
435  case AArch64::DDDDRegClassID:
436  case AArch64::QQRegClassID:
437  case AArch64::QQQRegClassID:
438  case AArch64::QQQQRegClassID:
439  return 32;
440 
441  case AArch64::FPR128_loRegClassID:
442  return 16;
443  }
444 }
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
bool cannotEliminateFrame(const MachineFunction &MF) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
int64_t getLocalFrameSize() const
Get the size of the local object blob.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
A debug info location.
Definition: DebugLoc.h:34
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
unsigned getID() const
Return the register class ID number.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
AArch64RegisterInfo(const Triple &TT)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:639
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const MachineInstrBuilder & addFrameIndex(int Idx) const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
bool isDebugValue() const
Definition: MachineInstr.h:816
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
int64_t getImm() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
BitVector getReservedRegs(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetOptions Options
Definition: TargetMachine.h:96
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const uint32_t * getTLSCallPreservedMask() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const unsigned Kind
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:626
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isConstantPhysReg(unsigned PhysReg) const override
bool hasBasePointer(const MachineFunction &MF) const
IRTranslator LLVM IR MI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295