LLVM  7.0.0svn
AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
19 #include "AArch64Subtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Function.h"
31 
32 using namespace llvm;
33 
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
36 
38  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
40 }
41 
42 const MCPhysReg *
44  assert(MF && "Invalid MachineFunction pointer.");
46  // GHC set of callee saved regs is empty as all those regs are
47  // used for passing STG regs around
48  return CSR_AArch64_NoRegs_SaveList;
50  return CSR_AArch64_AllRegs_SaveList;
52  return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
53  CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
54  CSR_AArch64_CXX_TLS_Darwin_SaveList;
56  ->supportSwiftError() &&
58  Attribute::SwiftError))
59  return CSR_AArch64_AAPCS_SwiftError_SaveList;
61  return CSR_AArch64_RT_MostRegs_SaveList;
62  else
63  return CSR_AArch64_AAPCS_SaveList;
64 }
65 
67  const MachineFunction *MF) const {
68  assert(MF && "Invalid MachineFunction pointer.");
70  MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
71  return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
72  return nullptr;
73 }
74 
75 const TargetRegisterClass *
77  unsigned Idx) const {
78  // edge case for GPR/FPR register classes
79  if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
80  return &AArch64::FPR32RegClass;
81  else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
82  return &AArch64::FPR64RegClass;
83 
84  // Forward to TableGen's default version.
85  return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
86 }
87 
88 const uint32_t *
90  CallingConv::ID CC) const {
91  bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
92  if (CC == CallingConv::GHC)
93  // This is academic because all GHC calls are (supposed to be) tail calls
94  return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
95  if (CC == CallingConv::AnyReg)
96  return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
97  if (CC == CallingConv::CXX_FAST_TLS)
98  return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
99  : CSR_AArch64_CXX_TLS_Darwin_RegMask;
101  ->supportSwiftError() &&
102  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
103  return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
104  : CSR_AArch64_AAPCS_SwiftError_RegMask;
105  if (CC == CallingConv::PreserveMost)
106  return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
107  : CSR_AArch64_RT_MostRegs_RegMask;
108  else
109  return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
110 }
111 
113  if (TT.isOSDarwin())
114  return CSR_AArch64_TLS_Darwin_RegMask;
115 
116  assert(TT.isOSBinFormatELF() && "Invalid target");
117  return CSR_AArch64_TLS_ELF_RegMask;
118 }
119 
120 const uint32_t *
122  CallingConv::ID CC) const {
123  // This should return a register mask that is the same as that returned by
124  // getCallPreservedMask but that additionally preserves the register used for
125  // the first i64 argument (which must also be the register used to return a
126  // single i64 return value)
127  //
128  // In case that the calling convention does not use the same register for
129  // both, the function should return NULL (does not currently apply)
130  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
131  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
132 }
133 
135  return CSR_AArch64_StackProbe_Windows_RegMask;
136 }
137 
138 BitVector
140  const AArch64FrameLowering *TFI = getFrameLowering(MF);
141 
142  // FIXME: avoid re-calculating this every time.
143  BitVector Reserved(getNumRegs());
144  markSuperRegs(Reserved, AArch64::WSP);
145  markSuperRegs(Reserved, AArch64::WZR);
146 
147  if (TFI->hasFP(MF) || TT.isOSDarwin())
148  markSuperRegs(Reserved, AArch64::W29);
149 
151  markSuperRegs(Reserved, AArch64::W18); // Platform register
152 
154  markSuperRegs(Reserved, AArch64::W20); // Platform register
155 
156  if (hasBasePointer(MF))
157  markSuperRegs(Reserved, AArch64::W19);
158 
159  assert(checkAllSuperRegsMarked(Reserved));
160  return Reserved;
161 }
162 
164  unsigned Reg) const {
165  const AArch64FrameLowering *TFI = getFrameLowering(MF);
166 
167  switch (Reg) {
168  default:
169  break;
170  case AArch64::SP:
171  case AArch64::XZR:
172  case AArch64::WSP:
173  case AArch64::WZR:
174  return true;
175  case AArch64::X18:
176  case AArch64::W18:
177  return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
178  case AArch64::X19:
179  case AArch64::W19:
180  return hasBasePointer(MF);
181  case AArch64::X20:
182  case AArch64::W20:
183  return MF.getSubtarget<AArch64Subtarget>().isX20Reserved();
184  case AArch64::FP:
185  case AArch64::W29:
186  return TFI->hasFP(MF) || TT.isOSDarwin();
187  }
188 
189  return false;
190 }
191 
192 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
193  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
194 }
195 
196 const TargetRegisterClass *
198  unsigned Kind) const {
199  return &AArch64::GPR64spRegClass;
200 }
201 
202 const TargetRegisterClass *
204  if (RC == &AArch64::CCRRegClass)
205  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
206  return RC;
207 }
208 
209 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
210 
212  const MachineFrameInfo &MFI = MF.getFrameInfo();
213 
214  // In the presence of variable sized objects, if the fixed stack size is
215  // large enough that referencing from the FP won't result in things being
216  // in range relatively often, we can use a base pointer to allow access
217  // from the other direction like the SP normally works.
218  // Furthermore, if both variable sized objects are present, and the
219  // stack needs to be dynamically re-aligned, the base pointer is the only
220  // reliable way to reference the locals.
221  if (MFI.hasVarSizedObjects()) {
222  if (needsStackRealignment(MF))
223  return true;
224  // Conservatively estimate whether the negative offset from the frame
225  // pointer will be sufficient to reach. If a function has a smallish
226  // frame, it's less likely to have lots of spills and callee saved
227  // space, so it's all more likely to be within range of the frame pointer.
228  // If it's wrong, we'll materialize the constant and still get to the
229  // object; it's just suboptimal. Negative offsets use the unscaled
230  // load/store instructions, which have a 9-bit signed immediate.
231  return MFI.getLocalFrameSize() >= 256;
232  }
233 
234  return false;
235 }
236 
237 unsigned
239  const AArch64FrameLowering *TFI = getFrameLowering(MF);
240  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
241 }
242 
244  const MachineFunction &MF) const {
245  return true;
246 }
247 
249  const MachineFunction &MF) const {
250  return true;
251 }
252 
253 bool
255  // This function indicates whether the emergency spillslot should be placed
256  // close to the beginning of the stackframe (closer to FP) or the end
257  // (closer to SP).
258  //
259  // The beginning works most reliably if we have a frame pointer.
260  const AArch64FrameLowering &TFI = *getFrameLowering(MF);
261  return TFI.hasFP(MF);
262 }
263 
265  const MachineFunction &MF) const {
266  return true;
267 }
268 
269 bool
271  const MachineFrameInfo &MFI = MF.getFrameInfo();
273  return true;
274  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
275 }
276 
277 /// needsFrameBaseReg - Returns true if the instruction's frame index
278 /// reference would be better served by a base register other than FP
279 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
280 /// references it should create new base registers for.
282  int64_t Offset) const {
283  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
284  assert(i < MI->getNumOperands() &&
285  "Instr doesn't have FrameIndex operand!");
286 
287  // It's the load/store FI references that cause issues, as it can be difficult
288  // to materialize the offset if it won't fit in the literal field. Estimate
289  // based on the size of the local frame and some conservative assumptions
290  // about the rest of the stack frame (note, this is pre-regalloc, so
291  // we don't know everything for certain yet) whether this offset is likely
292  // to be out of range of the immediate. Return true if so.
293 
294  // We only generate virtual base registers for loads and stores, so
295  // return false for everything else.
296  if (!MI->mayLoad() && !MI->mayStore())
297  return false;
298 
299  // Without a virtual base register, if the function has variable sized
300  // objects, all fixed-size local references will be via the frame pointer,
301  // Approximate the offset and see if it's legal for the instruction.
302  // Note that the incoming offset is based on the SP value at function entry,
303  // so it'll be negative.
304  MachineFunction &MF = *MI->getParent()->getParent();
305  const AArch64FrameLowering *TFI = getFrameLowering(MF);
306  MachineFrameInfo &MFI = MF.getFrameInfo();
307 
308  // Estimate an offset from the frame pointer.
309  // Conservatively assume all GPR callee-saved registers get pushed.
310  // FP, LR, X19-X28, D8-D15. 64-bits each.
311  int64_t FPOffset = Offset - 16 * 20;
312  // Estimate an offset from the stack pointer.
313  // The incoming offset is relating to the SP at the start of the function,
314  // but when we access the local it'll be relative to the SP after local
315  // allocation, so adjust our SP-relative offset by that allocation size.
316  Offset += MFI.getLocalFrameSize();
317  // Assume that we'll have at least some spill slots allocated.
318  // FIXME: This is a total SWAG number. We should run some statistics
319  // and pick a real one.
320  Offset += 128; // 128 bytes of spill slots
321 
322  // If there is a frame pointer, try using it.
323  // The FP is only available if there is no dynamic realignment. We
324  // don't know for sure yet whether we'll need that, so we guess based
325  // on whether there are any local variables that would trigger it.
326  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
327  return false;
328 
329  // If we can reference via the stack pointer or base pointer, try that.
330  // FIXME: This (and the code that resolves the references) can be improved
331  // to only disallow SP relative references in the live range of
332  // the VLA(s). In practice, it's unclear how much difference that
333  // would make, but it may be worth doing.
334  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
335  return false;
336 
337  // The offset likely isn't legal; we want to allocate a virtual base register.
338  return true;
339 }
340 
342  unsigned BaseReg,
343  int64_t Offset) const {
344  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
345  assert(MI && "Unable to get the legal offset for nil instruction.");
346  int SaveOffset = Offset;
347  return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
348 }
349 
350 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
351 /// at the beginning of the basic block.
353  unsigned BaseReg,
354  int FrameIdx,
355  int64_t Offset) const {
357  DebugLoc DL; // Defaults to "unknown"
358  if (Ins != MBB->end())
359  DL = Ins->getDebugLoc();
360  const MachineFunction &MF = *MBB->getParent();
361  const AArch64InstrInfo *TII =
362  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
363  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
365  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
366  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
367 
368  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
369  .addFrameIndex(FrameIdx)
370  .addImm(Offset)
371  .addImm(Shifter);
372 }
373 
375  int64_t Offset) const {
376  int Off = Offset; // ARM doesn't need the general 64-bit offsets
377  unsigned i = 0;
378 
379  while (!MI.getOperand(i).isFI()) {
380  ++i;
381  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
382  }
383  const MachineFunction *MF = MI.getParent()->getParent();
384  const AArch64InstrInfo *TII =
385  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
386  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
387  assert(Done && "Unable to resolve frame index!");
388  (void)Done;
389 }
390 
392  int SPAdj, unsigned FIOperandNum,
393  RegScavenger *RS) const {
394  assert(SPAdj == 0 && "Unexpected");
395 
396  MachineInstr &MI = *II;
397  MachineBasicBlock &MBB = *MI.getParent();
398  MachineFunction &MF = *MBB.getParent();
399  const AArch64InstrInfo *TII =
400  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
401  const AArch64FrameLowering *TFI = getFrameLowering(MF);
402 
403  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
404  unsigned FrameReg;
405  int Offset;
406 
407  // Special handling of dbg_value, stackmap and patchpoint instructions.
408  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
409  MI.getOpcode() == TargetOpcode::PATCHPOINT) {
410  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
411  /*PreferFP=*/true);
412  Offset += MI.getOperand(FIOperandNum + 1).getImm();
413  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
414  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
415  return;
416  }
417 
418  // Modify MI as necessary to handle as much of 'Offset' as possible
419  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
420  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
421  return;
422 
423  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
424  "Emergency spill slot is out of reach");
425 
426  // If we get here, the immediate doesn't fit into the instruction. We folded
427  // as much as possible above. Handle the rest, providing a register that is
428  // SP+LargeImm.
429  unsigned ScratchReg =
430  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
431  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
432  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
433 }
434 
436  MachineFunction &MF) const {
437  const AArch64FrameLowering *TFI = getFrameLowering(MF);
438 
439  switch (RC->getID()) {
440  default:
441  return 0;
442  case AArch64::GPR32RegClassID:
443  case AArch64::GPR32spRegClassID:
444  case AArch64::GPR32allRegClassID:
445  case AArch64::GPR64spRegClassID:
446  case AArch64::GPR64allRegClassID:
447  case AArch64::GPR64RegClassID:
448  case AArch64::GPR32commonRegClassID:
449  case AArch64::GPR64commonRegClassID:
450  return 32 - 1 // XZR/SP
451  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
453  .isX18Reserved() // X18 reserved as platform register
455  .isX20Reserved() // X20 reserved as platform register
456  - hasBasePointer(MF); // X19
457  case AArch64::FPR8RegClassID:
458  case AArch64::FPR16RegClassID:
459  case AArch64::FPR32RegClassID:
460  case AArch64::FPR64RegClassID:
461  case AArch64::FPR128RegClassID:
462  return 32;
463 
464  case AArch64::DDRegClassID:
465  case AArch64::DDDRegClassID:
466  case AArch64::DDDDRegClassID:
467  case AArch64::QQRegClassID:
468  case AArch64::QQQRegClassID:
469  case AArch64::QQQQRegClassID:
470  return 32;
471 
472  case AArch64::FPR128_loRegClassID:
473  return 16;
474  }
475 }
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
bool cannotEliminateFrame(const MachineFunction &MF) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned Reg
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:307
A debug info location.
Definition: DebugLoc.h:34
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
unsigned getID() const
Return the register class ID number.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
AArch64RegisterInfo(const Triple &TT)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:672
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const MachineInstrBuilder & addFrameIndex(int Idx) const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
bool isDebugValue() const
Definition: MachineInstr.h:849
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
BitVector getReservedRegs(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetOptions Options
Definition: TargetMachine.h:98
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const uint32_t * getTLSCallPreservedMask() const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const unsigned Kind
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:659
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isConstantPhysReg(unsigned PhysReg) const override
bool hasBasePointer(const MachineFunction &MF) const
IRTranslator LLVM IR MI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...