LLVM  9.0.0svn
AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16 
17 #include "AArch64.h"
18 #include "AArch64RegisterInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
34 
35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
36 
37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
38  const AArch64RegisterInfo RI;
39  const AArch64Subtarget &Subtarget;
40 
41 public:
42  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 
44  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
45  /// such, whenever a client has an instance of instruction info, it should
46  /// always be able to get register info as well (through this method).
47  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
52 
53  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54  unsigned &DstReg, unsigned &SubIdx) const override;
55 
56  bool
58  AliasAnalysis *AA = nullptr) const override;
59 
60  unsigned isLoadFromStackSlot(const MachineInstr &MI,
61  int &FrameIndex) const override;
62  unsigned isStoreToStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64 
65  /// Does this instruction set its full destination register to zero?
66  static bool isGPRZero(const MachineInstr &MI);
67 
68  /// Does this instruction rename a GPR without modifying bits?
69  static bool isGPRCopy(const MachineInstr &MI);
70 
71  /// Does this instruction rename an FPR without modifying bits?
72  static bool isFPRCopy(const MachineInstr &MI);
73 
74  /// Return true if pairing the given load or store is hinted to be
75  /// unprofitable.
76  static bool isLdStPairSuppressed(const MachineInstr &MI);
77 
78  /// Return true if the given load or store is a strided memory access.
79  static bool isStridedAccess(const MachineInstr &MI);
80 
81  /// Return true if this is an unscaled load/store.
82  static bool isUnscaledLdSt(unsigned Opc);
83  static bool isUnscaledLdSt(MachineInstr &MI) {
84  return isUnscaledLdSt(MI.getOpcode());
85  }
86 
87  /// Return true if pairing the given load or store may be paired with another.
88  static bool isPairableLdStInst(const MachineInstr &MI);
89 
90  /// Return the opcode that set flags when possible. The caller is
91  /// responsible for ensuring the opc has a flag setting equivalent.
92  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
93 
94  /// Return true if this is a load/store that can be potentially paired/merged.
95  bool isCandidateToMergeOrPair(MachineInstr &MI) const;
96 
97  /// Hint that pairing the given load or store is unprofitable.
98  static void suppressLdStPair(MachineInstr &MI);
99 
101  int64_t &Offset,
102  const TargetRegisterInfo *TRI) const override;
103 
105  int64_t &Offset, unsigned &Width,
106  const TargetRegisterInfo *TRI) const;
107 
108  /// Return the immediate offset of the base register in a load/store \p LdSt.
110 
111  /// Returns true if opcode \p Opc is a memory operation. If it is, set
112  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
113  ///
114  /// For unscaled instructions, \p Scale is set to 1.
115  bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
116  int64_t &MinOffset, int64_t &MaxOffset) const;
117 
118  bool shouldClusterMemOps(MachineOperand &BaseOp1, MachineOperand &BaseOp2,
119  unsigned NumLoads) const override;
120 
122  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
123  bool KillSrc, unsigned Opcode,
124  llvm::ArrayRef<unsigned> Indices) const;
126  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
127  bool KillSrc) const override;
128 
130  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
131  bool isKill, int FrameIndex,
132  const TargetRegisterClass *RC,
133  const TargetRegisterInfo *TRI) const override;
134 
136  MachineBasicBlock::iterator MBBI, unsigned DestReg,
137  int FrameIndex, const TargetRegisterClass *RC,
138  const TargetRegisterInfo *TRI) const override;
139 
140  // This tells target independent code that it is okay to pass instructions
141  // with subreg operands to foldMemoryOperandImpl.
142  bool isSubregFoldable() const override { return true; }
143 
145  MachineInstr *
147  ArrayRef<unsigned> Ops,
148  MachineBasicBlock::iterator InsertPt, int FrameIndex,
149  LiveIntervals *LIS = nullptr) const override;
150 
151  /// \returns true if a branch from an instruction with opcode \p BranchOpc
152  /// bytes is capable of jumping to a position \p BrOffset bytes away.
153  bool isBranchOffsetInRange(unsigned BranchOpc,
154  int64_t BrOffset) const override;
155 
156  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
157 
159  MachineBasicBlock *&FBB,
161  bool AllowModify = false) const override;
162  unsigned removeBranch(MachineBasicBlock &MBB,
163  int *BytesRemoved = nullptr) const override;
166  const DebugLoc &DL,
167  int *BytesAdded = nullptr) const override;
168  bool
171  unsigned, unsigned, int &, int &, int &) const override;
173  const DebugLoc &DL, unsigned DstReg,
174  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
175  unsigned FalseReg) const override;
176  void getNoop(MCInst &NopInst) const override;
177 
178  bool isSchedulingBoundary(const MachineInstr &MI,
179  const MachineBasicBlock *MBB,
180  const MachineFunction &MF) const override;
181 
182  /// analyzeCompare - For a comparison instruction, return the source registers
183  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
184  /// Return true if the comparison instruction can be analyzed.
185  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
186  unsigned &SrcReg2, int &CmpMask,
187  int &CmpValue) const override;
188  /// optimizeCompareInstr - Convert the instruction supplying the argument to
189  /// the comparison into one that sets the zero bit in the flags register.
190  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
191  unsigned SrcReg2, int CmpMask, int CmpValue,
192  const MachineRegisterInfo *MRI) const override;
193  bool optimizeCondBranch(MachineInstr &MI) const override;
194 
195  /// Return true when a code sequence can improve throughput. It
196  /// should be called only for instructions in loops.
197  /// \param Pattern - combiner pattern
198  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
199  /// Return true when there is potentially a faster code sequence
200  /// for an instruction chain ending in ``Root``. All potential patterns are
201  /// listed in the ``Patterns`` array.
203  MachineInstr &Root,
204  SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
205  /// Return true when Inst is associative and commutative so that it can be
206  /// reassociated.
207  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
208  /// When getMachineCombinerPatterns() finds patterns, this function generates
209  /// the instructions that could replace the original code sequence
211  MachineInstr &Root, MachineCombinerPattern Pattern,
214  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
215  /// AArch64 supports MachineCombiner.
216  bool useMachineCombiner() const override;
217 
218  bool expandPostRAPseudo(MachineInstr &MI) const override;
219 
220  std::pair<unsigned, unsigned>
221  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
228 
230  bool OutlineFromLinkOnceODRs) const override;
232  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
234  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
236  unsigned &Flags) const override;
238  const outliner::OutlinedFunction &OF) const override;
242  const outliner::Candidate &C) const override;
243  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
244  /// Returns true if the instruction has a shift by immediate that can be
245  /// executed in one cycle less.
246  static bool isFalkorShiftExtFast(const MachineInstr &MI);
247  /// Return true if the instructions is a SEH instruciton used for unwinding
248  /// on Windows.
249  static bool isSEHInstruction(const MachineInstr &MI);
250 
251 #define GET_INSTRINFO_HELPER_DECLS
252 #include "AArch64GenInstrInfo.inc"
253 
254 private:
255  /// Sets the offsets on outlined instructions in \p MBB which use SP
256  /// so that they will be valid post-outlining.
257  ///
258  /// \param MBB A \p MachineBasicBlock in an outlined function.
259  void fixupPostOutline(MachineBasicBlock &MBB) const;
260 
261  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
262  MachineBasicBlock *TBB,
263  ArrayRef<MachineOperand> Cond) const;
264  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
265  const MachineRegisterInfo *MRI) const;
266 
267  /// Returns an unused general-purpose register which can be used for
268  /// constructing an outlined call if one exists. Returns 0 otherwise.
269  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
270 };
271 
272 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
273 /// plus Offset. This is intended to be used from within the prolog/epilog
274 /// insertion (PEI) pass, where a virtual scratch register may be allocated
275 /// if necessary, to be replaced by the scavenger at the end of PEI.
276 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
277  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
278  int Offset, const TargetInstrInfo *TII,
280  bool SetNZCV = false, bool NeedsWinCFI = false);
281 
282 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
283 /// FP. Return false if the offset could not be handled directly in MI, and
284 /// return the left-over portion by reference.
285 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
286  unsigned FrameReg, int &Offset,
287  const AArch64InstrInfo *TII);
288 
289 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
291  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
292  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
293  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
294 };
295 
296 /// Check if the @p Offset is a valid frame offset for @p MI.
297 /// The returned value reports the validity of the frame offset for @p MI.
298 /// It uses the values defined by AArch64FrameOffsetStatus for that.
299 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
300 /// use an offset.eq
301 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
302 /// rewritten in @p MI.
303 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
304 /// amount that is off the limit of the legal offset.
305 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
306 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
307 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
308 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
309 /// is a legal offset.
311  bool *OutUseUnscaledOp = nullptr,
312  unsigned *OutUnscaledOp = nullptr,
313  int *EmittableOffset = nullptr);
314 
315 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
316 
317 static inline bool isCondBranchOpcode(int Opc) {
318  switch (Opc) {
319  case AArch64::Bcc:
320  case AArch64::CBZW:
321  case AArch64::CBZX:
322  case AArch64::CBNZW:
323  case AArch64::CBNZX:
324  case AArch64::TBZW:
325  case AArch64::TBZX:
326  case AArch64::TBNZW:
327  case AArch64::TBNZX:
328  return true;
329  default:
330  return false;
331  }
332 }
333 
334 static inline bool isIndirectBranchOpcode(int Opc) {
335  return Opc == AArch64::BR;
336 }
337 
338 // struct TSFlags {
339 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
340 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
341 // }
342 
343 namespace AArch64 {
344 
352 };
353 
358 };
359 
360 #undef TSFLAG_ELEMENT_SIZE_TYPE
361 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
362 }
363 
364 } // end namespace llvm
365 
366 #endif
bool getMemOperandWithOffsetWidth(MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
uint64_t CallInst * C
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
This class represents lattice values for constants.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
Offset can apply, at least partly.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
An individual sequence of instructions to be replaced with a call to an outlined function.
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool isUnscaledLdSt(unsigned Opc)
Return true if this is an unscaled load/store.
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
const HexagonInstrInfo * TII
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) const
Returns true if opcode Opc is a memory operation.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
static const MachineMemOperand::Flags MOSuppressPair
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static bool isUnscaledLdSt(MachineInstr &MI)
static bool isCondBranchOpcode(int Opc)
bool getMemOperandWithOffset(MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
MachineInstrBundleIterator< MachineInstr > iterator
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:629
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool shouldClusterMemOps(MachineOperand &BaseOp1, MachineOperand &BaseOp2, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
InstrType
Represents how an instruction should be mapped by the outliner.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
The information necessary to create an outlined function for some class of candidate.
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void getNoop(MCInst &NopInst) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isCandidateToMergeOrPair(MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
bool isSubregFoldable() const override
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
IRTranslator LLVM IR MI
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
static const MachineMemOperand::Flags MOStridedAccess
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override