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AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16 
17 #include "AArch64.h"
18 #include "AArch64RegisterInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
34 
35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
36 
37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
38  const AArch64RegisterInfo RI;
39  const AArch64Subtarget &Subtarget;
40 
41 public:
42  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 
44  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
45  /// such, whenever a client has an instance of instruction info, it should
46  /// always be able to get register info as well (through this method).
47  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
52 
53  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54  unsigned &DstReg, unsigned &SubIdx) const override;
55 
56  bool
58  AliasAnalysis *AA = nullptr) const override;
59 
60  unsigned isLoadFromStackSlot(const MachineInstr &MI,
61  int &FrameIndex) const override;
62  unsigned isStoreToStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64 
65  /// Returns true if there is a shiftable register and that the shift value
66  /// is non-zero.
67  bool hasShiftedReg(const MachineInstr &MI) const;
68 
69  /// Returns true if there is an extendable register and that the extending
70  /// value is non-zero.
71  bool hasExtendedReg(const MachineInstr &MI) const;
72 
73  /// \brief Does this instruction set its full destination register to zero?
74  bool isGPRZero(const MachineInstr &MI) const;
75 
76  /// \brief Does this instruction rename a GPR without modifying bits?
77  bool isGPRCopy(const MachineInstr &MI) const;
78 
79  /// \brief Does this instruction rename an FPR without modifying bits?
80  bool isFPRCopy(const MachineInstr &MI) const;
81 
82  /// Return true if this is load/store scales or extends its register offset.
83  /// This refers to scaling a dynamic index as opposed to scaled immediates.
84  /// MI should be a memory op that allows scaled addressing.
85  bool isScaledAddr(const MachineInstr &MI) const;
86 
87  /// Return true if pairing the given load or store is hinted to be
88  /// unprofitable.
89  bool isLdStPairSuppressed(const MachineInstr &MI) const;
90 
91  /// Return true if the given load or store is a strided memory access.
92  bool isStridedAccess(const MachineInstr &MI) const;
93 
94  /// Return true if this is an unscaled load/store.
95  bool isUnscaledLdSt(unsigned Opc) const;
96 
97  /// Return true if this is an unscaled load/store.
98  bool isUnscaledLdSt(MachineInstr &MI) const;
99 
100  static bool isPairableLdStInst(const MachineInstr &MI) {
101  switch (MI.getOpcode()) {
102  default:
103  return false;
104  // Scaled instructions.
105  case AArch64::STRSui:
106  case AArch64::STRDui:
107  case AArch64::STRQui:
108  case AArch64::STRXui:
109  case AArch64::STRWui:
110  case AArch64::LDRSui:
111  case AArch64::LDRDui:
112  case AArch64::LDRQui:
113  case AArch64::LDRXui:
114  case AArch64::LDRWui:
115  case AArch64::LDRSWui:
116  // Unscaled instructions.
117  case AArch64::STURSi:
118  case AArch64::STURDi:
119  case AArch64::STURQi:
120  case AArch64::STURWi:
121  case AArch64::STURXi:
122  case AArch64::LDURSi:
123  case AArch64::LDURDi:
124  case AArch64::LDURQi:
125  case AArch64::LDURWi:
126  case AArch64::LDURXi:
127  case AArch64::LDURSWi:
128  return true;
129  }
130  }
131 
132  /// \brief Return the opcode that set flags when possible. The caller is
133  /// responsible for ensuring the opc has a flag setting equivalent.
134  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit) {
135  switch (Opc) {
136  default:
137  llvm_unreachable("Opcode has no flag setting equivalent!");
138  // 32-bit cases:
139  case AArch64::ADDWri:
140  Is64Bit = false;
141  return AArch64::ADDSWri;
142  case AArch64::ADDWrr:
143  Is64Bit = false;
144  return AArch64::ADDSWrr;
145  case AArch64::ADDWrs:
146  Is64Bit = false;
147  return AArch64::ADDSWrs;
148  case AArch64::ADDWrx:
149  Is64Bit = false;
150  return AArch64::ADDSWrx;
151  case AArch64::ANDWri:
152  Is64Bit = false;
153  return AArch64::ANDSWri;
154  case AArch64::ANDWrr:
155  Is64Bit = false;
156  return AArch64::ANDSWrr;
157  case AArch64::ANDWrs:
158  Is64Bit = false;
159  return AArch64::ANDSWrs;
160  case AArch64::BICWrr:
161  Is64Bit = false;
162  return AArch64::BICSWrr;
163  case AArch64::BICWrs:
164  Is64Bit = false;
165  return AArch64::BICSWrs;
166  case AArch64::SUBWri:
167  Is64Bit = false;
168  return AArch64::SUBSWri;
169  case AArch64::SUBWrr:
170  Is64Bit = false;
171  return AArch64::SUBSWrr;
172  case AArch64::SUBWrs:
173  Is64Bit = false;
174  return AArch64::SUBSWrs;
175  case AArch64::SUBWrx:
176  Is64Bit = false;
177  return AArch64::SUBSWrx;
178  // 64-bit cases:
179  case AArch64::ADDXri:
180  Is64Bit = true;
181  return AArch64::ADDSXri;
182  case AArch64::ADDXrr:
183  Is64Bit = true;
184  return AArch64::ADDSXrr;
185  case AArch64::ADDXrs:
186  Is64Bit = true;
187  return AArch64::ADDSXrs;
188  case AArch64::ADDXrx:
189  Is64Bit = true;
190  return AArch64::ADDSXrx;
191  case AArch64::ANDXri:
192  Is64Bit = true;
193  return AArch64::ANDSXri;
194  case AArch64::ANDXrr:
195  Is64Bit = true;
196  return AArch64::ANDSXrr;
197  case AArch64::ANDXrs:
198  Is64Bit = true;
199  return AArch64::ANDSXrs;
200  case AArch64::BICXrr:
201  Is64Bit = true;
202  return AArch64::BICSXrr;
203  case AArch64::BICXrs:
204  Is64Bit = true;
205  return AArch64::BICSXrs;
206  case AArch64::SUBXri:
207  Is64Bit = true;
208  return AArch64::SUBSXri;
209  case AArch64::SUBXrr:
210  Is64Bit = true;
211  return AArch64::SUBSXrr;
212  case AArch64::SUBXrs:
213  Is64Bit = true;
214  return AArch64::SUBSXrs;
215  case AArch64::SUBXrx:
216  Is64Bit = true;
217  return AArch64::SUBSXrx;
218  }
219  }
220 
221  /// Return true if this is a load/store that can be potentially paired/merged.
222  bool isCandidateToMergeOrPair(MachineInstr &MI) const;
223 
224  /// Hint that pairing the given load or store is unprofitable.
225  void suppressLdStPair(MachineInstr &MI) const;
226 
227  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
228  int64_t &Offset,
229  const TargetRegisterInfo *TRI) const override;
230 
231  bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
232  int64_t &Offset, unsigned &Width,
233  const TargetRegisterInfo *TRI) const;
234 
235  /// Return the immediate offset of the base register in a load/store \p LdSt.
237 
238  /// \brief Returns true if opcode \p Opc is a memory operation. If it is, set
239  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
240  ///
241  /// For unscaled instructions, \p Scale is set to 1.
242  bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
243  int64_t &MinOffset, int64_t &MaxOffset) const;
244 
245  bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
246  MachineInstr &SecondLdSt, unsigned BaseReg2,
247  unsigned NumLoads) const override;
248 
250  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
251  bool KillSrc, unsigned Opcode,
252  llvm::ArrayRef<unsigned> Indices) const;
254  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
255  bool KillSrc) const override;
256 
258  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
259  bool isKill, int FrameIndex,
260  const TargetRegisterClass *RC,
261  const TargetRegisterInfo *TRI) const override;
262 
264  MachineBasicBlock::iterator MBBI, unsigned DestReg,
265  int FrameIndex, const TargetRegisterClass *RC,
266  const TargetRegisterInfo *TRI) const override;
267 
268  // This tells target independent code that it is okay to pass instructions
269  // with subreg operands to foldMemoryOperandImpl.
270  bool isSubregFoldable() const override { return true; }
271 
273  MachineInstr *
275  ArrayRef<unsigned> Ops,
276  MachineBasicBlock::iterator InsertPt, int FrameIndex,
277  LiveIntervals *LIS = nullptr) const override;
278 
279  /// \returns true if a branch from an instruction with opcode \p BranchOpc
280  /// bytes is capable of jumping to a position \p BrOffset bytes away.
281  bool isBranchOffsetInRange(unsigned BranchOpc,
282  int64_t BrOffset) const override;
283 
284  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
285 
287  MachineBasicBlock *&FBB,
289  bool AllowModify = false) const override;
290  unsigned removeBranch(MachineBasicBlock &MBB,
291  int *BytesRemoved = nullptr) const override;
294  const DebugLoc &DL,
295  int *BytesAdded = nullptr) const override;
296  bool
299  unsigned, unsigned, int &, int &, int &) const override;
301  const DebugLoc &DL, unsigned DstReg,
302  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
303  unsigned FalseReg) const override;
304  void getNoop(MCInst &NopInst) const override;
305 
306  /// analyzeCompare - For a comparison instruction, return the source registers
307  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
308  /// Return true if the comparison instruction can be analyzed.
309  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
310  unsigned &SrcReg2, int &CmpMask,
311  int &CmpValue) const override;
312  /// optimizeCompareInstr - Convert the instruction supplying the argument to
313  /// the comparison into one that sets the zero bit in the flags register.
314  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
315  unsigned SrcReg2, int CmpMask, int CmpValue,
316  const MachineRegisterInfo *MRI) const override;
317  bool optimizeCondBranch(MachineInstr &MI) const override;
318 
319  /// Return true when a code sequence can improve throughput. It
320  /// should be called only for instructions in loops.
321  /// \param Pattern - combiner pattern
322  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
323  /// Return true when there is potentially a faster code sequence
324  /// for an instruction chain ending in ``Root``. All potential patterns are
325  /// listed in the ``Patterns`` array.
327  MachineInstr &Root,
328  SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
329  /// Return true when Inst is associative and commutative so that it can be
330  /// reassociated.
331  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
332  /// When getMachineCombinerPatterns() finds patterns, this function generates
333  /// the instructions that could replace the original code sequence
335  MachineInstr &Root, MachineCombinerPattern Pattern,
338  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
339  /// AArch64 supports MachineCombiner.
340  bool useMachineCombiner() const override;
341 
342  bool expandPostRAPseudo(MachineInstr &MI) const override;
343 
344  std::pair<unsigned, unsigned>
345  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
352 
353  bool
356  bool OutlineFromLinkOnceODRs) const override;
357  MachineOutlinerInfo getOutlininingCandidateInfo(
358  std::vector<
359  std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
360  &RepeatedSequenceLocs) const override;
361  AArch64GenInstrInfo::MachineOutlinerInstrType
362  getOutliningType(MachineInstr &MI) const override;
364  const MachineOutlinerInfo &MInfo) const override;
366  const MachineOutlinerInfo &MInfo) const override;
370  const MachineOutlinerInfo &MInfo) const override;
371  /// Returns true if the instruction has a shift left that can be executed
372  /// more efficiently.
373  bool isExynosShiftLeftFast(const MachineInstr &MI) const;
374  /// Returns true if the instruction has a shift by immediate that can be
375  /// executed in one cycle less.
376  bool isFalkorShiftExtFast(const MachineInstr &MI) const;
377 
378 private:
379  /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
380  /// so that they will be valid post-outlining.
381  ///
382  /// \param MBB A \p MachineBasicBlock in an outlined function.
383  void fixupPostOutline(MachineBasicBlock &MBB) const;
384 
385  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
386  MachineBasicBlock *TBB,
387  ArrayRef<MachineOperand> Cond) const;
388  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
389  const MachineRegisterInfo *MRI) const;
390 };
391 
392 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
393 /// plus Offset. This is intended to be used from within the prolog/epilog
394 /// insertion (PEI) pass, where a virtual scratch register may be allocated
395 /// if necessary, to be replaced by the scavenger at the end of PEI.
397  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
398  int Offset, const TargetInstrInfo *TII,
400  bool SetNZCV = false);
401 
402 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
403 /// FP. Return false if the offset could not be handled directly in MI, and
404 /// return the left-over portion by reference.
405 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
406  unsigned FrameReg, int &Offset,
407  const AArch64InstrInfo *TII);
408 
409 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
411  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
412  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
413  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
414 };
415 
416 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
417 /// The returned value reports the validity of the frame offset for @p MI.
418 /// It uses the values defined by AArch64FrameOffsetStatus for that.
419 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
420 /// use an offset.eq
421 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
422 /// rewritten in @p MI.
423 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
424 /// amount that is off the limit of the legal offset.
425 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
426 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
427 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
428 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
429 /// is a legal offset.
430 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
431  bool *OutUseUnscaledOp = nullptr,
432  unsigned *OutUnscaledOp = nullptr,
433  int *EmittableOffset = nullptr);
434 
435 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
436 
437 static inline bool isCondBranchOpcode(int Opc) {
438  switch (Opc) {
439  case AArch64::Bcc:
440  case AArch64::CBZW:
441  case AArch64::CBZX:
442  case AArch64::CBNZW:
443  case AArch64::CBNZX:
444  case AArch64::TBZW:
445  case AArch64::TBZX:
446  case AArch64::TBNZW:
447  case AArch64::TBNZX:
448  return true;
449  default:
450  return false;
451  }
452 }
453 
454 static inline bool isIndirectBranchOpcode(int Opc) {
455  return Opc == AArch64::BR;
456 }
457 
458 } // end namespace llvm
459 
460 #endif
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
AArch64GenInstrInfo::MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const override
bool isScaledAddr(const MachineInstr &MI) const
Return true if this is load/store scales or extends its register offset.
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool hasExtendedReg(const MachineInstr &MI) const
Returns true if there is an extendable register and that the extending value is non-zero.
bool isGPRCopy(const MachineInstr &MI) const
Does this instruction rename a GPR without modifying bits?
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
Offset can apply, at least partly.
A debug info location.
Definition: DebugLoc.h:34
bool isFPRCopy(const MachineInstr &MI) const
Does this instruction rename an FPR without modifying bits?
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
const HexagonInstrInfo * TII
bool isStridedAccess(const MachineInstr &MI) const
Return true if the given load or store is a strided memory access.
bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) const
Returns true if opcode Opc is a memory operation.
bool hasShiftedReg(const MachineInstr &MI) const
Returns true if there is a shiftable register and that the shift value is non-zero.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool isUnscaledLdSt(unsigned Opc) const
Return true if this is an unscaled load/store.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
static const MachineMemOperand::Flags MOSuppressPair
bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
bool isLdStPairSuppressed(const MachineInstr &MI) const
Return true if pairing the given load or store is hinted to be unprofitable.
bool isExynosShiftLeftFast(const MachineInstr &MI) const
Returns true if the instruction has a shift left that can be executed more efficiently.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
TargetInstrInfo - Interface to description of machine instruction set.
static bool isCondBranchOpcode(int Opc)
bool isGPRZero(const MachineInstr &MI) const
Does this instruction set its full destination register to zero?
void insertOutlinerEpilogue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:596
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
MachineOutlinerInfo getOutlininingCandidateInfo(std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &RepeatedSequenceLocs) const override
static bool isPairableLdStInst(const MachineInstr &MI)
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void getNoop(MCInst &NopInst) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
void insertOutlinerPrologue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isCandidateToMergeOrPair(MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
bool isSubregFoldable() const override
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
#define I(x, y, z)
Definition: MD5.cpp:58
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
void suppressLdStPair(MachineInstr &MI) const
Hint that pairing the given load or store is unprofitable.
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool canOutlineWithoutLRSave(MachineBasicBlock::iterator &CallInsertionPt) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
IRTranslator LLVM IR MI
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool isFalkorShiftExtFast(const MachineInstr &MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
static const MachineMemOperand::Flags MOStridedAccess