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AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "llvm/ADT/Optional.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
34 
35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
36 
37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
38  const AArch64RegisterInfo RI;
39  const AArch64Subtarget &Subtarget;
40 
41 public:
42  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 
44  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
45  /// such, whenever a client has an instance of instruction info, it should
46  /// always be able to get register info as well (through this method).
47  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
52 
53  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54  unsigned &DstReg, unsigned &SubIdx) const override;
55 
56  bool
58  const MachineInstr &MIb,
59  AliasAnalysis *AA = nullptr) const override;
60 
61  unsigned isLoadFromStackSlot(const MachineInstr &MI,
62  int &FrameIndex) const override;
63  unsigned isStoreToStackSlot(const MachineInstr &MI,
64  int &FrameIndex) const override;
65 
66  /// Does this instruction set its full destination register to zero?
67  static bool isGPRZero(const MachineInstr &MI);
68 
69  /// Does this instruction rename a GPR without modifying bits?
70  static bool isGPRCopy(const MachineInstr &MI);
71 
72  /// Does this instruction rename an FPR without modifying bits?
73  static bool isFPRCopy(const MachineInstr &MI);
74 
75  /// Return true if pairing the given load or store is hinted to be
76  /// unprofitable.
77  static bool isLdStPairSuppressed(const MachineInstr &MI);
78 
79  /// Return true if the given load or store is a strided memory access.
80  static bool isStridedAccess(const MachineInstr &MI);
81 
82  /// Return true if this is an unscaled load/store.
83  static bool isUnscaledLdSt(unsigned Opc);
84  static bool isUnscaledLdSt(MachineInstr &MI) {
85  return isUnscaledLdSt(MI.getOpcode());
86  }
87 
88  /// Returns the unscaled load/store for the scaled load/store opcode,
89  /// if there is a corresponding unscaled variant available.
90  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
91 
92 
93  /// Returns the index for the immediate for a given instruction.
94  static unsigned getLoadStoreImmIdx(unsigned Opc);
95 
96  /// Return true if pairing the given load or store may be paired with another.
97  static bool isPairableLdStInst(const MachineInstr &MI);
98 
99  /// Return the opcode that set flags when possible. The caller is
100  /// responsible for ensuring the opc has a flag setting equivalent.
101  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
102 
103  /// Return true if this is a load/store that can be potentially paired/merged.
104  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
105 
106  /// Hint that pairing the given load or store is unprofitable.
107  static void suppressLdStPair(MachineInstr &MI);
108 
109  bool getMemOperandWithOffset(const MachineInstr &MI,
110  const MachineOperand *&BaseOp,
111  int64_t &Offset,
112  const TargetRegisterInfo *TRI) const override;
113 
115  const MachineOperand *&BaseOp,
116  int64_t &Offset, unsigned &Width,
117  const TargetRegisterInfo *TRI) const;
118 
119  /// Return the immediate offset of the base register in a load/store \p LdSt.
121 
122  /// Returns true if opcode \p Opc is a memory operation. If it is, set
123  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
124  ///
125  /// For unscaled instructions, \p Scale is set to 1.
126  static bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
127  int64_t &MinOffset, int64_t &MaxOffset);
128 
129  bool shouldClusterMemOps(const MachineOperand &BaseOp1,
130  const MachineOperand &BaseOp2,
131  unsigned NumLoads) const override;
132 
134  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
135  bool KillSrc, unsigned Opcode,
136  llvm::ArrayRef<unsigned> Indices) const;
138  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
139  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
140  llvm::ArrayRef<unsigned> Indices) const;
142  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
143  bool KillSrc) const override;
144 
146  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
147  bool isKill, int FrameIndex,
148  const TargetRegisterClass *RC,
149  const TargetRegisterInfo *TRI) const override;
150 
152  MachineBasicBlock::iterator MBBI, unsigned DestReg,
153  int FrameIndex, const TargetRegisterClass *RC,
154  const TargetRegisterInfo *TRI) const override;
155 
156  // This tells target independent code that it is okay to pass instructions
157  // with subreg operands to foldMemoryOperandImpl.
158  bool isSubregFoldable() const override { return true; }
159 
161  MachineInstr *
163  ArrayRef<unsigned> Ops,
164  MachineBasicBlock::iterator InsertPt, int FrameIndex,
165  LiveIntervals *LIS = nullptr) const override;
166 
167  /// \returns true if a branch from an instruction with opcode \p BranchOpc
168  /// bytes is capable of jumping to a position \p BrOffset bytes away.
169  bool isBranchOffsetInRange(unsigned BranchOpc,
170  int64_t BrOffset) const override;
171 
172  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
173 
175  MachineBasicBlock *&FBB,
177  bool AllowModify = false) const override;
178  unsigned removeBranch(MachineBasicBlock &MBB,
179  int *BytesRemoved = nullptr) const override;
182  const DebugLoc &DL,
183  int *BytesAdded = nullptr) const override;
184  bool
187  unsigned, unsigned, int &, int &, int &) const override;
189  const DebugLoc &DL, unsigned DstReg,
190  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
191  unsigned FalseReg) const override;
192  void getNoop(MCInst &NopInst) const override;
193 
194  bool isSchedulingBoundary(const MachineInstr &MI,
195  const MachineBasicBlock *MBB,
196  const MachineFunction &MF) const override;
197 
198  /// analyzeCompare - For a comparison instruction, return the source registers
199  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
200  /// Return true if the comparison instruction can be analyzed.
201  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
202  unsigned &SrcReg2, int &CmpMask,
203  int &CmpValue) const override;
204  /// optimizeCompareInstr - Convert the instruction supplying the argument to
205  /// the comparison into one that sets the zero bit in the flags register.
206  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
207  unsigned SrcReg2, int CmpMask, int CmpValue,
208  const MachineRegisterInfo *MRI) const override;
209  bool optimizeCondBranch(MachineInstr &MI) const override;
210 
211  /// Return true when a code sequence can improve throughput. It
212  /// should be called only for instructions in loops.
213  /// \param Pattern - combiner pattern
214  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
215  /// Return true when there is potentially a faster code sequence
216  /// for an instruction chain ending in ``Root``. All potential patterns are
217  /// listed in the ``Patterns`` array.
219  MachineInstr &Root,
220  SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
221  /// Return true when Inst is associative and commutative so that it can be
222  /// reassociated.
223  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
224  /// When getMachineCombinerPatterns() finds patterns, this function generates
225  /// the instructions that could replace the original code sequence
227  MachineInstr &Root, MachineCombinerPattern Pattern,
230  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
231  /// AArch64 supports MachineCombiner.
232  bool useMachineCombiner() const override;
233 
234  bool expandPostRAPseudo(MachineInstr &MI) const override;
235 
236  std::pair<unsigned, unsigned>
237  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
244 
246  bool OutlineFromLinkOnceODRs) const override;
248  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
250  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
252  unsigned &Flags) const override;
254  const outliner::OutlinedFunction &OF) const override;
258  const outliner::Candidate &C) const override;
259  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
260  /// Returns true if the instruction has a shift by immediate that can be
261  /// executed in one cycle less.
262  static bool isFalkorShiftExtFast(const MachineInstr &MI);
263  /// Return true if the instructions is a SEH instruciton used for unwinding
264  /// on Windows.
265  static bool isSEHInstruction(const MachineInstr &MI);
266 
267 #define GET_INSTRINFO_HELPER_DECLS
268 #include "AArch64GenInstrInfo.inc"
269 
270 protected:
271  /// If the specific machine instruction is a instruction that moves/copies
272  /// value from one register to another register return true along with
273  /// @Source machine operand and @Destination machine operand.
274  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
275  const MachineOperand *&Destination) const override;
276 
277 private:
278  /// Sets the offsets on outlined instructions in \p MBB which use SP
279  /// so that they will be valid post-outlining.
280  ///
281  /// \param MBB A \p MachineBasicBlock in an outlined function.
282  void fixupPostOutline(MachineBasicBlock &MBB) const;
283 
284  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
285  MachineBasicBlock *TBB,
286  ArrayRef<MachineOperand> Cond) const;
287  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
288  const MachineRegisterInfo *MRI) const;
289 
290  /// Returns an unused general-purpose register which can be used for
291  /// constructing an outlined call if one exists. Returns 0 otherwise.
292  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
293 };
294 
295 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
296 /// plus Offset. This is intended to be used from within the prolog/epilog
297 /// insertion (PEI) pass, where a virtual scratch register may be allocated
298 /// if necessary, to be replaced by the scavenger at the end of PEI.
299 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
300  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
301  int Offset, const TargetInstrInfo *TII,
303  bool SetNZCV = false, bool NeedsWinCFI = false,
304  bool *HasWinCFI = nullptr);
305 
306 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
307 /// FP. Return false if the offset could not be handled directly in MI, and
308 /// return the left-over portion by reference.
309 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
310  unsigned FrameReg, int &Offset,
311  const AArch64InstrInfo *TII);
312 
313 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
315  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
316  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
317  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
318 };
319 
320 /// Check if the @p Offset is a valid frame offset for @p MI.
321 /// The returned value reports the validity of the frame offset for @p MI.
322 /// It uses the values defined by AArch64FrameOffsetStatus for that.
323 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
324 /// use an offset.eq
325 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
326 /// rewritten in @p MI.
327 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
328 /// amount that is off the limit of the legal offset.
329 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
330 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
331 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
332 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
333 /// is a legal offset.
335  bool *OutUseUnscaledOp = nullptr,
336  unsigned *OutUnscaledOp = nullptr,
337  int *EmittableOffset = nullptr);
338 
339 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
340 
341 static inline bool isCondBranchOpcode(int Opc) {
342  switch (Opc) {
343  case AArch64::Bcc:
344  case AArch64::CBZW:
345  case AArch64::CBZX:
346  case AArch64::CBNZW:
347  case AArch64::CBNZX:
348  case AArch64::TBZW:
349  case AArch64::TBZX:
350  case AArch64::TBNZW:
351  case AArch64::TBNZX:
352  return true;
353  default:
354  return false;
355  }
356 }
357 
358 static inline bool isIndirectBranchOpcode(int Opc) {
359  return Opc == AArch64::BR;
360 }
361 
362 // struct TSFlags {
363 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
364 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
365 // }
366 
367 namespace AArch64 {
368 
376 };
377 
382 };
383 
384 #undef TSFLAG_ELEMENT_SIZE_TYPE
385 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
386 }
387 
388 } // end namespace llvm
389 
390 #endif
uint64_t CallInst * C
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
Offset can apply, at least partly.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
An individual sequence of instructions to be replaced with a call to an outlined function.
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool isUnscaledLdSt(unsigned Opc)
Return true if this is an unscaled load/store.
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
const HexagonInstrInfo * TII
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
static const MachineMemOperand::Flags MOSuppressPair
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static bool isUnscaledLdSt(MachineInstr &MI)
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
static bool isCondBranchOpcode(int Opc)
MachineInstrBundleIterator< MachineInstr > iterator
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:657
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
InstrType
Represents how an instruction should be mapped by the outliner.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
The information necessary to create an outlined function for some class of candidate.
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void getNoop(MCInst &NopInst) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
static bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MachineOperand class - Representation of each machine instruction operand.
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSubregFoldable() const override
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static Optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
IRTranslator LLVM IR MI
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
static const MachineMemOperand::Flags MOStridedAccess
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override