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AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "AArch64GenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 class AArch64Subtarget;
27 class AArch64TargetMachine;
28 
33 
34 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
35 
36 class AArch64InstrInfo final : public AArch64GenInstrInfo {
37  const AArch64RegisterInfo RI;
38  const AArch64Subtarget &Subtarget;
39 
40 public:
41  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
42 
43  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44  /// such, whenever a client has an instance of instruction info, it should
45  /// always be able to get register info as well (through this method).
46  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
47 
48  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
49 
50  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
51 
52  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
53  unsigned &DstReg, unsigned &SubIdx) const override;
54 
55  bool
57  AliasAnalysis *AA = nullptr) const override;
58 
59  unsigned isLoadFromStackSlot(const MachineInstr &MI,
60  int &FrameIndex) const override;
61  unsigned isStoreToStackSlot(const MachineInstr &MI,
62  int &FrameIndex) const override;
63 
64  /// Does this instruction set its full destination register to zero?
65  static bool isGPRZero(const MachineInstr &MI);
66 
67  /// Does this instruction rename a GPR without modifying bits?
68  static bool isGPRCopy(const MachineInstr &MI);
69 
70  /// Does this instruction rename an FPR without modifying bits?
71  static bool isFPRCopy(const MachineInstr &MI);
72 
73  /// Return true if pairing the given load or store is hinted to be
74  /// unprofitable.
75  static bool isLdStPairSuppressed(const MachineInstr &MI);
76 
77  /// Return true if the given load or store is a strided memory access.
78  static bool isStridedAccess(const MachineInstr &MI);
79 
80  /// Return true if this is an unscaled load/store.
81  static bool isUnscaledLdSt(unsigned Opc);
82  static bool isUnscaledLdSt(MachineInstr &MI) {
83  return isUnscaledLdSt(MI.getOpcode());
84  }
85 
86  /// Return true if pairing the given load or store may be paired with another.
87  static bool isPairableLdStInst(const MachineInstr &MI);
88 
89  /// Return the opcode that set flags when possible. The caller is
90  /// responsible for ensuring the opc has a flag setting equivalent.
91  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
92 
93  /// Return true if this is a load/store that can be potentially paired/merged.
94  bool isCandidateToMergeOrPair(MachineInstr &MI) const;
95 
96  /// Hint that pairing the given load or store is unprofitable.
97  static void suppressLdStPair(MachineInstr &MI);
98 
100  int64_t &Offset,
101  const TargetRegisterInfo *TRI) const override;
102 
104  int64_t &Offset, unsigned &Width,
105  const TargetRegisterInfo *TRI) const;
106 
107  /// Return the immediate offset of the base register in a load/store \p LdSt.
109 
110  /// Returns true if opcode \p Opc is a memory operation. If it is, set
111  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
112  ///
113  /// For unscaled instructions, \p Scale is set to 1.
114  bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
115  int64_t &MinOffset, int64_t &MaxOffset) const;
116 
117  bool shouldClusterMemOps(MachineOperand &BaseOp1, MachineOperand &BaseOp2,
118  unsigned NumLoads) const override;
119 
121  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
122  bool KillSrc, unsigned Opcode,
123  llvm::ArrayRef<unsigned> Indices) const;
125  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
126  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
127  llvm::ArrayRef<unsigned> Indices) const;
129  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
130  bool KillSrc) const override;
131 
133  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
134  bool isKill, int FrameIndex,
135  const TargetRegisterClass *RC,
136  const TargetRegisterInfo *TRI) const override;
137 
139  MachineBasicBlock::iterator MBBI, unsigned DestReg,
140  int FrameIndex, const TargetRegisterClass *RC,
141  const TargetRegisterInfo *TRI) const override;
142 
143  // This tells target independent code that it is okay to pass instructions
144  // with subreg operands to foldMemoryOperandImpl.
145  bool isSubregFoldable() const override { return true; }
146 
148  MachineInstr *
150  ArrayRef<unsigned> Ops,
151  MachineBasicBlock::iterator InsertPt, int FrameIndex,
152  LiveIntervals *LIS = nullptr) const override;
153 
154  /// \returns true if a branch from an instruction with opcode \p BranchOpc
155  /// bytes is capable of jumping to a position \p BrOffset bytes away.
156  bool isBranchOffsetInRange(unsigned BranchOpc,
157  int64_t BrOffset) const override;
158 
159  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
160 
162  MachineBasicBlock *&FBB,
164  bool AllowModify = false) const override;
165  unsigned removeBranch(MachineBasicBlock &MBB,
166  int *BytesRemoved = nullptr) const override;
169  const DebugLoc &DL,
170  int *BytesAdded = nullptr) const override;
171  bool
174  unsigned, unsigned, int &, int &, int &) const override;
176  const DebugLoc &DL, unsigned DstReg,
177  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
178  unsigned FalseReg) const override;
179  void getNoop(MCInst &NopInst) const override;
180 
181  bool isSchedulingBoundary(const MachineInstr &MI,
182  const MachineBasicBlock *MBB,
183  const MachineFunction &MF) const override;
184 
185  /// analyzeCompare - For a comparison instruction, return the source registers
186  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
187  /// Return true if the comparison instruction can be analyzed.
188  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
189  unsigned &SrcReg2, int &CmpMask,
190  int &CmpValue) const override;
191  /// optimizeCompareInstr - Convert the instruction supplying the argument to
192  /// the comparison into one that sets the zero bit in the flags register.
193  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
194  unsigned SrcReg2, int CmpMask, int CmpValue,
195  const MachineRegisterInfo *MRI) const override;
196  bool optimizeCondBranch(MachineInstr &MI) const override;
197 
198  /// Return true when a code sequence can improve throughput. It
199  /// should be called only for instructions in loops.
200  /// \param Pattern - combiner pattern
201  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
202  /// Return true when there is potentially a faster code sequence
203  /// for an instruction chain ending in ``Root``. All potential patterns are
204  /// listed in the ``Patterns`` array.
206  MachineInstr &Root,
207  SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
208  /// Return true when Inst is associative and commutative so that it can be
209  /// reassociated.
210  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
211  /// When getMachineCombinerPatterns() finds patterns, this function generates
212  /// the instructions that could replace the original code sequence
214  MachineInstr &Root, MachineCombinerPattern Pattern,
217  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
218  /// AArch64 supports MachineCombiner.
219  bool useMachineCombiner() const override;
220 
221  bool expandPostRAPseudo(MachineInstr &MI) const override;
222 
223  std::pair<unsigned, unsigned>
224  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
231 
233  bool OutlineFromLinkOnceODRs) const override;
235  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
237  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
239  unsigned &Flags) const override;
241  const outliner::OutlinedFunction &OF) const override;
245  const outliner::Candidate &C) const override;
246  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
247  /// Returns true if the instruction has a shift by immediate that can be
248  /// executed in one cycle less.
249  static bool isFalkorShiftExtFast(const MachineInstr &MI);
250  /// Return true if the instructions is a SEH instruciton used for unwinding
251  /// on Windows.
252  static bool isSEHInstruction(const MachineInstr &MI);
253 
254 #define GET_INSTRINFO_HELPER_DECLS
255 #include "AArch64GenInstrInfo.inc"
256 
257 private:
258  /// Sets the offsets on outlined instructions in \p MBB which use SP
259  /// so that they will be valid post-outlining.
260  ///
261  /// \param MBB A \p MachineBasicBlock in an outlined function.
262  void fixupPostOutline(MachineBasicBlock &MBB) const;
263 
264  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
265  MachineBasicBlock *TBB,
266  ArrayRef<MachineOperand> Cond) const;
267  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
268  const MachineRegisterInfo *MRI) const;
269 
270  /// Returns an unused general-purpose register which can be used for
271  /// constructing an outlined call if one exists. Returns 0 otherwise.
272  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
273 };
274 
275 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
276 /// plus Offset. This is intended to be used from within the prolog/epilog
277 /// insertion (PEI) pass, where a virtual scratch register may be allocated
278 /// if necessary, to be replaced by the scavenger at the end of PEI.
279 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
280  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
281  int Offset, const TargetInstrInfo *TII,
283  bool SetNZCV = false, bool NeedsWinCFI = false);
284 
285 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
286 /// FP. Return false if the offset could not be handled directly in MI, and
287 /// return the left-over portion by reference.
288 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
289  unsigned FrameReg, int &Offset,
290  const AArch64InstrInfo *TII);
291 
292 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
294  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
295  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
296  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
297 };
298 
299 /// Check if the @p Offset is a valid frame offset for @p MI.
300 /// The returned value reports the validity of the frame offset for @p MI.
301 /// It uses the values defined by AArch64FrameOffsetStatus for that.
302 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
303 /// use an offset.eq
304 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
305 /// rewritten in @p MI.
306 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
307 /// amount that is off the limit of the legal offset.
308 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
309 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
310 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
311 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
312 /// is a legal offset.
314  bool *OutUseUnscaledOp = nullptr,
315  unsigned *OutUnscaledOp = nullptr,
316  int *EmittableOffset = nullptr);
317 
318 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
319 
320 static inline bool isCondBranchOpcode(int Opc) {
321  switch (Opc) {
322  case AArch64::Bcc:
323  case AArch64::CBZW:
324  case AArch64::CBZX:
325  case AArch64::CBNZW:
326  case AArch64::CBNZX:
327  case AArch64::TBZW:
328  case AArch64::TBZX:
329  case AArch64::TBNZW:
330  case AArch64::TBNZX:
331  return true;
332  default:
333  return false;
334  }
335 }
336 
337 static inline bool isIndirectBranchOpcode(int Opc) {
338  return Opc == AArch64::BR;
339 }
340 
341 // struct TSFlags {
342 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
343 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
344 // }
345 
346 namespace AArch64 {
347 
355 };
356 
361 };
362 
363 #undef TSFLAG_ELEMENT_SIZE_TYPE
364 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
365 }
366 
367 } // end namespace llvm
368 
369 #endif
bool getMemOperandWithOffsetWidth(MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
uint64_t CallInst * C
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
Offset can apply, at least partly.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
An individual sequence of instructions to be replaced with a call to an outlined function.
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool isUnscaledLdSt(unsigned Opc)
Return true if this is an unscaled load/store.
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
const HexagonInstrInfo * TII
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) const
Returns true if opcode Opc is a memory operation.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
static const MachineMemOperand::Flags MOSuppressPair
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static bool isUnscaledLdSt(MachineInstr &MI)
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
static bool isCondBranchOpcode(int Opc)
bool getMemOperandWithOffset(MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
MachineInstrBundleIterator< MachineInstr > iterator
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:630
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool shouldClusterMemOps(MachineOperand &BaseOp1, MachineOperand &BaseOp2, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
InstrType
Represents how an instruction should be mapped by the outliner.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
The information necessary to create an outlined function for some class of candidate.
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void getNoop(MCInst &NopInst) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isCandidateToMergeOrPair(MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
bool isSubregFoldable() const override
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
IRTranslator LLVM IR MI
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
static const MachineMemOperand::Flags MOStridedAccess
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override