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AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "AArch64StackOffset.h"
19 #include "llvm/ADT/Optional.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "AArch64GenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AArch64Subtarget;
29 class AArch64TargetMachine;
30 
35 
36 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
37 
38 class AArch64InstrInfo final : public AArch64GenInstrInfo {
39  const AArch64RegisterInfo RI;
40  const AArch64Subtarget &Subtarget;
41 
42 public:
43  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
44 
45  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46  /// such, whenever a client has an instance of instruction info, it should
47  /// always be able to get register info as well (through this method).
48  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
49 
50  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
51 
52  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
53 
54  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
55  unsigned &DstReg, unsigned &SubIdx) const override;
56 
57  bool
59  const MachineInstr &MIb,
60  AliasAnalysis *AA = nullptr) const override;
61 
62  unsigned isLoadFromStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64  unsigned isStoreToStackSlot(const MachineInstr &MI,
65  int &FrameIndex) const override;
66 
67  /// Does this instruction set its full destination register to zero?
68  static bool isGPRZero(const MachineInstr &MI);
69 
70  /// Does this instruction rename a GPR without modifying bits?
71  static bool isGPRCopy(const MachineInstr &MI);
72 
73  /// Does this instruction rename an FPR without modifying bits?
74  static bool isFPRCopy(const MachineInstr &MI);
75 
76  /// Return true if pairing the given load or store is hinted to be
77  /// unprofitable.
78  static bool isLdStPairSuppressed(const MachineInstr &MI);
79 
80  /// Return true if the given load or store is a strided memory access.
81  static bool isStridedAccess(const MachineInstr &MI);
82 
83  /// Return true if this is an unscaled load/store.
84  static bool isUnscaledLdSt(unsigned Opc);
85  static bool isUnscaledLdSt(MachineInstr &MI) {
86  return isUnscaledLdSt(MI.getOpcode());
87  }
88 
89  /// Returns the unscaled load/store for the scaled load/store opcode,
90  /// if there is a corresponding unscaled variant available.
91  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
92 
93 
94  /// Returns the index for the immediate for a given instruction.
95  static unsigned getLoadStoreImmIdx(unsigned Opc);
96 
97  /// Return true if pairing the given load or store may be paired with another.
98  static bool isPairableLdStInst(const MachineInstr &MI);
99 
100  /// Return the opcode that set flags when possible. The caller is
101  /// responsible for ensuring the opc has a flag setting equivalent.
102  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
103 
104  /// Return true if this is a load/store that can be potentially paired/merged.
105  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
106 
107  /// Hint that pairing the given load or store is unprofitable.
108  static void suppressLdStPair(MachineInstr &MI);
109 
110  bool getMemOperandWithOffset(const MachineInstr &MI,
111  const MachineOperand *&BaseOp,
112  int64_t &Offset,
113  const TargetRegisterInfo *TRI) const override;
114 
116  const MachineOperand *&BaseOp,
117  int64_t &Offset, unsigned &Width,
118  const TargetRegisterInfo *TRI) const;
119 
120  /// Return the immediate offset of the base register in a load/store \p LdSt.
122 
123  /// Returns true if opcode \p Opc is a memory operation. If it is, set
124  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
125  ///
126  /// For unscaled instructions, \p Scale is set to 1.
127  static bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
128  int64_t &MinOffset, int64_t &MaxOffset);
129 
130  bool shouldClusterMemOps(const MachineOperand &BaseOp1,
131  const MachineOperand &BaseOp2,
132  unsigned NumLoads) const override;
133 
135  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
136  bool KillSrc, unsigned Opcode,
137  llvm::ArrayRef<unsigned> Indices) const;
139  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
140  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
141  llvm::ArrayRef<unsigned> Indices) const;
143  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
144  bool KillSrc) const override;
145 
147  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
148  bool isKill, int FrameIndex,
149  const TargetRegisterClass *RC,
150  const TargetRegisterInfo *TRI) const override;
151 
153  MachineBasicBlock::iterator MBBI, unsigned DestReg,
154  int FrameIndex, const TargetRegisterClass *RC,
155  const TargetRegisterInfo *TRI) const override;
156 
157  // This tells target independent code that it is okay to pass instructions
158  // with subreg operands to foldMemoryOperandImpl.
159  bool isSubregFoldable() const override { return true; }
160 
162  MachineInstr *
164  ArrayRef<unsigned> Ops,
165  MachineBasicBlock::iterator InsertPt, int FrameIndex,
166  LiveIntervals *LIS = nullptr,
167  VirtRegMap *VRM = nullptr) const override;
168 
169  /// \returns true if a branch from an instruction with opcode \p BranchOpc
170  /// bytes is capable of jumping to a position \p BrOffset bytes away.
171  bool isBranchOffsetInRange(unsigned BranchOpc,
172  int64_t BrOffset) const override;
173 
174  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
175 
177  MachineBasicBlock *&FBB,
179  bool AllowModify = false) const override;
180  unsigned removeBranch(MachineBasicBlock &MBB,
181  int *BytesRemoved = nullptr) const override;
184  const DebugLoc &DL,
185  int *BytesAdded = nullptr) const override;
186  bool
189  unsigned, unsigned, int &, int &, int &) const override;
191  const DebugLoc &DL, unsigned DstReg,
192  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
193  unsigned FalseReg) const override;
194  void getNoop(MCInst &NopInst) const override;
195 
196  bool isSchedulingBoundary(const MachineInstr &MI,
197  const MachineBasicBlock *MBB,
198  const MachineFunction &MF) const override;
199 
200  /// analyzeCompare - For a comparison instruction, return the source registers
201  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
202  /// Return true if the comparison instruction can be analyzed.
203  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
204  unsigned &SrcReg2, int &CmpMask,
205  int &CmpValue) const override;
206  /// optimizeCompareInstr - Convert the instruction supplying the argument to
207  /// the comparison into one that sets the zero bit in the flags register.
208  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
209  unsigned SrcReg2, int CmpMask, int CmpValue,
210  const MachineRegisterInfo *MRI) const override;
211  bool optimizeCondBranch(MachineInstr &MI) const override;
212 
213  /// Return true when a code sequence can improve throughput. It
214  /// should be called only for instructions in loops.
215  /// \param Pattern - combiner pattern
216  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
217  /// Return true when there is potentially a faster code sequence
218  /// for an instruction chain ending in ``Root``. All potential patterns are
219  /// listed in the ``Patterns`` array.
221  MachineInstr &Root,
222  SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
223  /// Return true when Inst is associative and commutative so that it can be
224  /// reassociated.
225  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
226  /// When getMachineCombinerPatterns() finds patterns, this function generates
227  /// the instructions that could replace the original code sequence
229  MachineInstr &Root, MachineCombinerPattern Pattern,
232  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
233  /// AArch64 supports MachineCombiner.
234  bool useMachineCombiner() const override;
235 
236  bool expandPostRAPseudo(MachineInstr &MI) const override;
237 
238  std::pair<unsigned, unsigned>
239  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
246 
248  bool OutlineFromLinkOnceODRs) const override;
250  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
252  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
254  unsigned &Flags) const override;
256  const outliner::OutlinedFunction &OF) const override;
260  const outliner::Candidate &C) const override;
261  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
262  /// Returns true if the instruction has a shift by immediate that can be
263  /// executed in one cycle less.
264  static bool isFalkorShiftExtFast(const MachineInstr &MI);
265  /// Return true if the instructions is a SEH instruciton used for unwinding
266  /// on Windows.
267  static bool isSEHInstruction(const MachineInstr &MI);
268 
269 #define GET_INSTRINFO_HELPER_DECLS
270 #include "AArch64GenInstrInfo.inc"
271 
272 protected:
273  /// If the specific machine instruction is a instruction that moves/copies
274  /// value from one register to another register return true along with
275  /// @Source machine operand and @Destination machine operand.
276  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
277  const MachineOperand *&Destination) const override;
278 
279 private:
280  /// Sets the offsets on outlined instructions in \p MBB which use SP
281  /// so that they will be valid post-outlining.
282  ///
283  /// \param MBB A \p MachineBasicBlock in an outlined function.
284  void fixupPostOutline(MachineBasicBlock &MBB) const;
285 
286  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
287  MachineBasicBlock *TBB,
288  ArrayRef<MachineOperand> Cond) const;
289  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
290  const MachineRegisterInfo *MRI) const;
291 
292  /// Returns an unused general-purpose register which can be used for
293  /// constructing an outlined call if one exists. Returns 0 otherwise.
294  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
295 };
296 
297 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
298 /// plus Offset. This is intended to be used from within the prolog/epilog
299 /// insertion (PEI) pass, where a virtual scratch register may be allocated
300 /// if necessary, to be replaced by the scavenger at the end of PEI.
301 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
302  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
303  StackOffset Offset, const TargetInstrInfo *TII,
305  bool SetNZCV = false, bool NeedsWinCFI = false,
306  bool *HasWinCFI = nullptr);
307 
308 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
309 /// FP. Return false if the offset could not be handled directly in MI, and
310 /// return the left-over portion by reference.
311 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
312  unsigned FrameReg, StackOffset &Offset,
313  const AArch64InstrInfo *TII);
314 
315 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
317  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
318  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
319  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
320 };
321 
322 /// Check if the @p Offset is a valid frame offset for @p MI.
323 /// The returned value reports the validity of the frame offset for @p MI.
324 /// It uses the values defined by AArch64FrameOffsetStatus for that.
325 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
326 /// use an offset.eq
327 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
328 /// rewritten in @p MI.
329 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
330 /// amount that is off the limit of the legal offset.
331 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
332 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
333 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
334 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
335 /// is a legal offset.
337  bool *OutUseUnscaledOp = nullptr,
338  unsigned *OutUnscaledOp = nullptr,
339  int *EmittableOffset = nullptr);
340 
341 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
342 
343 static inline bool isCondBranchOpcode(int Opc) {
344  switch (Opc) {
345  case AArch64::Bcc:
346  case AArch64::CBZW:
347  case AArch64::CBZX:
348  case AArch64::CBNZW:
349  case AArch64::CBNZX:
350  case AArch64::TBZW:
351  case AArch64::TBZX:
352  case AArch64::TBNZW:
353  case AArch64::TBNZX:
354  return true;
355  default:
356  return false;
357  }
358 }
359 
360 static inline bool isIndirectBranchOpcode(int Opc) {
361  return Opc == AArch64::BR;
362 }
363 
364 // struct TSFlags {
365 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
366 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
367 // }
368 
369 namespace AArch64 {
370 
378 };
379 
384 };
385 
386 #undef TSFLAG_ELEMENT_SIZE_TYPE
387 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
388 }
389 
390 } // end namespace llvm
391 
392 #endif
uint64_t CallInst * C
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
Offset can apply, at least partly.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
An individual sequence of instructions to be replaced with a call to an outlined function.
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool isUnscaledLdSt(unsigned Opc)
Return true if this is an unscaled load/store.
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
const HexagonInstrInfo * TII
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
AArch64InstrInfo(const AArch64Subtarget &STI)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
static const MachineMemOperand::Flags MOSuppressPair
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static bool isUnscaledLdSt(MachineInstr &MI)
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
static bool isCondBranchOpcode(int Opc)
MachineInstrBundleIterator< MachineInstr > iterator
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:657
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
InstrType
Represents how an instruction should be mapped by the outliner.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
The information necessary to create an outlined function for some class of candidate.
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void getNoop(MCInst &NopInst) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
static bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MachineOperand class - Representation of each machine instruction operand.
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSubregFoldable() const override
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static Optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
IRTranslator LLVM IR MI
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
static const MachineMemOperand::Flags MOStridedAccess
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override