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AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16 
17 #include "AArch64.h"
18 #include "AArch64RegisterInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
34 
35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
36 
37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
38  const AArch64RegisterInfo RI;
39  const AArch64Subtarget &Subtarget;
40 
41 public:
42  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 
44  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
45  /// such, whenever a client has an instance of instruction info, it should
46  /// always be able to get register info as well (through this method).
47  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
52 
53  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54  unsigned &DstReg, unsigned &SubIdx) const override;
55 
56  bool
58  AliasAnalysis *AA = nullptr) const override;
59 
60  unsigned isLoadFromStackSlot(const MachineInstr &MI,
61  int &FrameIndex) const override;
62  unsigned isStoreToStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64 
65  /// Returns true if there is a shiftable register and that the shift value
66  /// is non-zero.
67  static bool hasShiftedReg(const MachineInstr &MI);
68 
69  /// Returns true if there is an extendable register and that the extending
70  /// value is non-zero.
71  static bool hasExtendedReg(const MachineInstr &MI);
72 
73  /// Does this instruction set its full destination register to zero?
74  static bool isGPRZero(const MachineInstr &MI);
75 
76  /// Does this instruction rename a GPR without modifying bits?
77  static bool isGPRCopy(const MachineInstr &MI);
78 
79  /// Does this instruction rename an FPR without modifying bits?
80  static bool isFPRCopy(const MachineInstr &MI);
81 
82  /// Return true if this is load/store scales or extends its register offset.
83  /// This refers to scaling a dynamic index as opposed to scaled immediates.
84  /// MI should be a memory op that allows scaled addressing.
85  static bool isScaledAddr(const MachineInstr &MI);
86 
87  /// Return true if pairing the given load or store is hinted to be
88  /// unprofitable.
89  static bool isLdStPairSuppressed(const MachineInstr &MI);
90 
91  /// Return true if the given load or store is a strided memory access.
92  static bool isStridedAccess(const MachineInstr &MI);
93 
94  /// Return true if this is an unscaled load/store.
95  static bool isUnscaledLdSt(unsigned Opc);
96  static bool isUnscaledLdSt(MachineInstr &MI) {
97  return isUnscaledLdSt(MI.getOpcode());
98  }
99 
100  /// Return true if pairing the given load or store may be paired with another.
101  static bool isPairableLdStInst(const MachineInstr &MI);
102 
103  /// Return the opcode that set flags when possible. The caller is
104  /// responsible for ensuring the opc has a flag setting equivalent.
105  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
106 
107  /// Return true if this is a load/store that can be potentially paired/merged.
108  bool isCandidateToMergeOrPair(MachineInstr &MI) const;
109 
110  /// Hint that pairing the given load or store is unprofitable.
111  static void suppressLdStPair(MachineInstr &MI);
112 
113  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
114  int64_t &Offset,
115  const TargetRegisterInfo *TRI) const override;
116 
117  bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
118  int64_t &Offset, unsigned &Width,
119  const TargetRegisterInfo *TRI) const;
120 
121  /// Return the immediate offset of the base register in a load/store \p LdSt.
123 
124  /// Returns true if opcode \p Opc is a memory operation. If it is, set
125  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
126  ///
127  /// For unscaled instructions, \p Scale is set to 1.
128  bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
129  int64_t &MinOffset, int64_t &MaxOffset) const;
130 
131  bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
132  MachineInstr &SecondLdSt, unsigned BaseReg2,
133  unsigned NumLoads) const override;
134 
136  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
137  bool KillSrc, unsigned Opcode,
138  llvm::ArrayRef<unsigned> Indices) const;
140  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
141  bool KillSrc) const override;
142 
144  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
145  bool isKill, int FrameIndex,
146  const TargetRegisterClass *RC,
147  const TargetRegisterInfo *TRI) const override;
148 
150  MachineBasicBlock::iterator MBBI, unsigned DestReg,
151  int FrameIndex, const TargetRegisterClass *RC,
152  const TargetRegisterInfo *TRI) const override;
153 
154  // This tells target independent code that it is okay to pass instructions
155  // with subreg operands to foldMemoryOperandImpl.
156  bool isSubregFoldable() const override { return true; }
157 
159  MachineInstr *
161  ArrayRef<unsigned> Ops,
162  MachineBasicBlock::iterator InsertPt, int FrameIndex,
163  LiveIntervals *LIS = nullptr) const override;
164 
165  /// \returns true if a branch from an instruction with opcode \p BranchOpc
166  /// bytes is capable of jumping to a position \p BrOffset bytes away.
167  bool isBranchOffsetInRange(unsigned BranchOpc,
168  int64_t BrOffset) const override;
169 
170  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
171 
173  MachineBasicBlock *&FBB,
175  bool AllowModify = false) const override;
176  unsigned removeBranch(MachineBasicBlock &MBB,
177  int *BytesRemoved = nullptr) const override;
180  const DebugLoc &DL,
181  int *BytesAdded = nullptr) const override;
182  bool
185  unsigned, unsigned, int &, int &, int &) const override;
187  const DebugLoc &DL, unsigned DstReg,
188  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
189  unsigned FalseReg) const override;
190  void getNoop(MCInst &NopInst) const override;
191 
192  /// analyzeCompare - For a comparison instruction, return the source registers
193  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
194  /// Return true if the comparison instruction can be analyzed.
195  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
196  unsigned &SrcReg2, int &CmpMask,
197  int &CmpValue) const override;
198  /// optimizeCompareInstr - Convert the instruction supplying the argument to
199  /// the comparison into one that sets the zero bit in the flags register.
200  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
201  unsigned SrcReg2, int CmpMask, int CmpValue,
202  const MachineRegisterInfo *MRI) const override;
203  bool optimizeCondBranch(MachineInstr &MI) const override;
204 
205  /// Return true when a code sequence can improve throughput. It
206  /// should be called only for instructions in loops.
207  /// \param Pattern - combiner pattern
208  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
209  /// Return true when there is potentially a faster code sequence
210  /// for an instruction chain ending in ``Root``. All potential patterns are
211  /// listed in the ``Patterns`` array.
213  MachineInstr &Root,
214  SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
215  /// Return true when Inst is associative and commutative so that it can be
216  /// reassociated.
217  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
218  /// When getMachineCombinerPatterns() finds patterns, this function generates
219  /// the instructions that could replace the original code sequence
221  MachineInstr &Root, MachineCombinerPattern Pattern,
224  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
225  /// AArch64 supports MachineCombiner.
226  bool useMachineCombiner() const override;
227 
228  bool expandPostRAPseudo(MachineInstr &MI) const override;
229 
230  std::pair<unsigned, unsigned>
231  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
238 
239  /// AArch64 supports the MachineOutliner.
240  bool useMachineOutliner() const override { return true; }
241 
242  bool
245  bool OutlineFromLinkOnceODRs) const override;
246  MachineOutlinerInfo getOutlininingCandidateInfo(
247  std::vector<
248  std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
249  &RepeatedSequenceLocs) const override;
250  AArch64GenInstrInfo::MachineOutlinerInstrType
251  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
252  unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const override;
254  const MachineOutlinerInfo &MInfo) const override;
256  const MachineOutlinerInfo &MInfo) const override;
260  const MachineOutlinerInfo &MInfo) const override;
261  /// Returns true if the instruction sets to an immediate value that can be
262  /// executed more efficiently.
263  bool isExynosResetFast(const MachineInstr &MI) const;
264  /// Returns true if the instruction has a shift left that can be executed
265  /// more efficiently.
266  bool isExynosShiftLeftFast(const MachineInstr &MI) const;
267  /// Returns true if the instruction has a shift by immediate that can be
268  /// executed in one cycle less.
269  bool isFalkorShiftExtFast(const MachineInstr &MI) const;
270 
271 private:
272  /// Sets the offsets on outlined instructions in \p MBB which use SP
273  /// so that they will be valid post-outlining.
274  ///
275  /// \param MBB A \p MachineBasicBlock in an outlined function.
276  void fixupPostOutline(MachineBasicBlock &MBB) const;
277 
278  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
279  MachineBasicBlock *TBB,
280  ArrayRef<MachineOperand> Cond) const;
281  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
282  const MachineRegisterInfo *MRI) const;
283 };
284 
285 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
286 /// plus Offset. This is intended to be used from within the prolog/epilog
287 /// insertion (PEI) pass, where a virtual scratch register may be allocated
288 /// if necessary, to be replaced by the scavenger at the end of PEI.
290  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
291  int Offset, const TargetInstrInfo *TII,
293  bool SetNZCV = false);
294 
295 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
296 /// FP. Return false if the offset could not be handled directly in MI, and
297 /// return the left-over portion by reference.
298 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
299  unsigned FrameReg, int &Offset,
300  const AArch64InstrInfo *TII);
301 
302 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
304  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
305  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
306  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
307 };
308 
309 /// Check if the @p Offset is a valid frame offset for @p MI.
310 /// The returned value reports the validity of the frame offset for @p MI.
311 /// It uses the values defined by AArch64FrameOffsetStatus for that.
312 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
313 /// use an offset.eq
314 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
315 /// rewritten in @p MI.
316 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
317 /// amount that is off the limit of the legal offset.
318 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
319 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
320 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
321 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
322 /// is a legal offset.
323 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
324  bool *OutUseUnscaledOp = nullptr,
325  unsigned *OutUnscaledOp = nullptr,
326  int *EmittableOffset = nullptr);
327 
328 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
329 
330 static inline bool isCondBranchOpcode(int Opc) {
331  switch (Opc) {
332  case AArch64::Bcc:
333  case AArch64::CBZW:
334  case AArch64::CBZX:
335  case AArch64::CBNZW:
336  case AArch64::CBNZX:
337  case AArch64::TBZW:
338  case AArch64::TBZX:
339  case AArch64::TBNZW:
340  case AArch64::TBNZX:
341  return true;
342  default:
343  return false;
344  }
345 }
346 
347 static inline bool isIndirectBranchOpcode(int Opc) {
348  return Opc == AArch64::BR;
349 }
350 
351 } // end namespace llvm
352 
353 #endif
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
static bool hasShiftedReg(const MachineInstr &MI)
Returns true if there is a shiftable register and that the shift value is non-zero.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
Offset can apply, at least partly.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool isUnscaledLdSt(unsigned Opc)
Return true if this is an unscaled load/store.
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const override
const HexagonInstrInfo * TII
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) const
Returns true if opcode Opc is a memory operation.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
bool isExynosResetFast(const MachineInstr &MI) const
Returns true if the instruction sets to an immediate value that can be executed more efficiently...
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
static const MachineMemOperand::Flags MOSuppressPair
bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
bool isExynosShiftLeftFast(const MachineInstr &MI) const
Returns true if the instruction has a shift left that can be executed more efficiently.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static bool isUnscaledLdSt(MachineInstr &MI)
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
TargetInstrInfo - Interface to description of machine instruction set.
static bool isCondBranchOpcode(int Opc)
AArch64GenInstrInfo::MachineOutlinerInstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool useMachineOutliner() const override
AArch64 supports the MachineOutliner.
void insertOutlinerEpilogue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:598
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
MachineOutlinerInfo getOutlininingCandidateInfo(std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &RepeatedSequenceLocs) const override
static bool isScaledAddr(const MachineInstr &MI)
Return true if this is load/store scales or extends its register offset.
static bool hasExtendedReg(const MachineInstr &MI)
Returns true if there is an extendable register and that the extending value is non-zero.
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void getNoop(MCInst &NopInst) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
void insertOutlinerPrologue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isCandidateToMergeOrPair(MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
bool isSubregFoldable() const override
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
#define I(x, y, z)
Definition: MD5.cpp:58
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool canOutlineWithoutLRSave(MachineBasicBlock::iterator &CallInsertionPt) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
IRTranslator LLVM IR MI
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool isFalkorShiftExtFast(const MachineInstr &MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
static const MachineMemOperand::Flags MOStridedAccess