LLVM  6.0.0svn
AArch64RegisterInfo.h
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1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "AArch64GenRegisterInfo.inc"
19 
20 namespace llvm {
21 
22 class MachineFunction;
23 class RegScavenger;
24 class TargetRegisterClass;
25 class Triple;
26 
28  const Triple &TT;
29 
30 public:
31  AArch64RegisterInfo(const Triple &TT);
32 
33  bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
34 
35  /// Code Generation virtual methods...
36  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
37  const MCPhysReg *
40  CallingConv::ID) const override;
41 
42  unsigned getCSRFirstUseCost() const override {
43  // The cost will be compared against BlockFrequency where entry has the
44  // value of 1 << 14. A value of 5 will choose to spill or split really
45  // cold path instead of using a callee-saved register.
46  return 5;
47  }
48 
49  // Calls involved in thread-local variable lookup save more registers than
50  // normal calls, so they need a different mask to represent this.
51  const uint32_t *getTLSCallPreservedMask() const;
52 
53  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
54  /// case that 'returned' is on an i64 first argument if the calling convention
55  /// is one that can (partially) model this attribute with a preserved mask
56  /// (i.e. it is a calling convention that uses the same register for the first
57  /// i64 argument and an i64 return value)
58  ///
59  /// Should return NULL in the case that the calling convention does not have
60  /// this property
62  CallingConv::ID) const;
63 
64  BitVector getReservedRegs(const MachineFunction &MF) const override;
65  bool isConstantPhysReg(unsigned PhysReg) const override;
66  const TargetRegisterClass *
68  unsigned Kind = 0) const override;
69  const TargetRegisterClass *
70  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
71 
72  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
73  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
74  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
75 
76  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
77  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
78  int64_t Offset) const override;
79  void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
80  int FrameIdx,
81  int64_t Offset) const override;
82  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
83  int64_t Offset) const override;
85  unsigned FIOperandNum,
86  RegScavenger *RS = nullptr) const override;
87  bool cannotEliminateFrame(const MachineFunction &MF) const;
88 
89  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
90  bool hasBasePointer(const MachineFunction &MF) const;
91  unsigned getBaseRegister() const;
92 
93  // Debug information queries.
94  unsigned getFrameRegister(const MachineFunction &MF) const override;
95 
96  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
97  MachineFunction &MF) const override;
98 
99  bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {
100  return true;
101  }
102 };
103 
104 } // end namespace llvm
105 
106 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
unsigned getCSRFirstUseCost() const override
unsigned getFrameRegister(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Reg
All possible values of the reg field in the ModR/M byte.
AArch64RegisterInfo(const Triple &TT)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
BitVector getReservedRegs(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool trackLivenessAfterRegAlloc(const MachineFunction &) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const uint32_t * getTLSCallPreservedMask() const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const unsigned Kind
bool isConstantPhysReg(unsigned PhysReg) const override
bool hasBasePointer(const MachineFunction &MF) const
IRTranslator LLVM IR MI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...