LLVM  9.0.0svn
AArch64ExpandPseudoInsts.cpp
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1 //===- AArch64ExpandPseudoInsts.cpp - Expand pseudo instructions ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling and other late optimizations. This
11 // pass should be run after register allocation but before the post-regalloc
12 // scheduling pass.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AArch64InstrInfo.h"
17 #include "AArch64Subtarget.h"
19 #include "Utils/AArch64BaseInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/Triple.h"
30 #include "llvm/IR/DebugLoc.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
36 #include <cassert>
37 #include <cstdint>
38 #include <iterator>
39 #include <limits>
40 #include <utility>
41 
42 using namespace llvm;
43 
44 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
45 
46 namespace {
47 
48 class AArch64ExpandPseudo : public MachineFunctionPass {
49 public:
50  const AArch64InstrInfo *TII;
51 
52  static char ID;
53 
54  AArch64ExpandPseudo() : MachineFunctionPass(ID) {
56  }
57 
58  bool runOnMachineFunction(MachineFunction &Fn) override;
59 
60  StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME; }
61 
62 private:
63  bool expandMBB(MachineBasicBlock &MBB);
64  bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
65  MachineBasicBlock::iterator &NextMBBI);
66  bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
67  unsigned BitSize);
68  bool expandMOVImmSimple(MachineBasicBlock &MBB,
70  unsigned BitSize,
71  unsigned OneChunks,
72  unsigned ZeroChunks);
73 
74  bool expandCMP_SWAP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
75  unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
76  unsigned ExtendImm, unsigned ZeroReg,
77  MachineBasicBlock::iterator &NextMBBI);
78  bool expandCMP_SWAP_128(MachineBasicBlock &MBB,
80  MachineBasicBlock::iterator &NextMBBI);
81 };
82 
83 } // end anonymous namespace
84 
86 
87 INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
88  AARCH64_EXPAND_PSEUDO_NAME, false, false)
89 
90 /// Transfer implicit operands on the pseudo instruction to the
91 /// instructions created from the expansion.
92 static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
94  const MCInstrDesc &Desc = OldMI.getDesc();
95  for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); i != e;
96  ++i) {
97  const MachineOperand &MO = OldMI.getOperand(i);
98  assert(MO.isReg() && MO.getReg());
99  if (MO.isUse())
100  UseMI.add(MO);
101  else
102  DefMI.add(MO);
103  }
104 }
105 
106 /// Helper function which extracts the specified 16-bit chunk from a
107 /// 64-bit value.
108 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
109  assert(ChunkIdx < 4 && "Out of range chunk index specified!");
110 
111  return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
112 }
113 
114 /// Check whether the given 16-bit chunk replicated to full 64-bit width
115 /// can be materialized with an ORR instruction.
116 static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
117  Chunk = (Chunk << 48) | (Chunk << 32) | (Chunk << 16) | Chunk;
118 
119  return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
120 }
121 
122 /// Check for identical 16-bit chunks within the constant and if so
123 /// materialize them with a single ORR instruction. The remaining one or two
124 /// 16-bit chunks will be materialized with MOVK instructions.
125 ///
126 /// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
127 /// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
128 /// an ORR instruction.
129 static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
130  MachineBasicBlock &MBB,
132  const AArch64InstrInfo *TII) {
133  using CountMap = DenseMap<uint64_t, unsigned>;
134 
135  CountMap Counts;
136 
137  // Scan the constant and count how often every chunk occurs.
138  for (unsigned Idx = 0; Idx < 4; ++Idx)
139  ++Counts[getChunk(UImm, Idx)];
140 
141  // Traverse the chunks to find one which occurs more than once.
142  for (CountMap::const_iterator Chunk = Counts.begin(), End = Counts.end();
143  Chunk != End; ++Chunk) {
144  const uint64_t ChunkVal = Chunk->first;
145  const unsigned Count = Chunk->second;
146 
147  uint64_t Encoding = 0;
148 
149  // We are looking for chunks which have two or three instances and can be
150  // materialized with an ORR instruction.
151  if ((Count != 2 && Count != 3) || !canUseOrr(ChunkVal, Encoding))
152  continue;
153 
154  const bool CountThree = Count == 3;
155  // Create the ORR-immediate instruction.
156  MachineInstrBuilder MIB =
157  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
158  .add(MI.getOperand(0))
159  .addReg(AArch64::XZR)
160  .addImm(Encoding);
161 
162  const unsigned DstReg = MI.getOperand(0).getReg();
163  const bool DstIsDead = MI.getOperand(0).isDead();
164 
165  unsigned ShiftAmt = 0;
166  uint64_t Imm16 = 0;
167  // Find the first chunk not materialized with the ORR instruction.
168  for (; ShiftAmt < 64; ShiftAmt += 16) {
169  Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
170 
171  if (Imm16 != ChunkVal)
172  break;
173  }
174 
175  // Create the first MOVK instruction.
176  MachineInstrBuilder MIB1 =
177  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
178  .addReg(DstReg,
179  RegState::Define | getDeadRegState(DstIsDead && CountThree))
180  .addReg(DstReg)
181  .addImm(Imm16)
183 
184  // In case we have three instances the whole constant is now materialized
185  // and we can exit.
186  if (CountThree) {
187  transferImpOps(MI, MIB, MIB1);
188  MI.eraseFromParent();
189  return true;
190  }
191 
192  // Find the remaining chunk which needs to be materialized.
193  for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) {
194  Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
195 
196  if (Imm16 != ChunkVal)
197  break;
198  }
199 
200  // Create the second MOVK instruction.
201  MachineInstrBuilder MIB2 =
202  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
203  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
204  .addReg(DstReg)
205  .addImm(Imm16)
207 
208  transferImpOps(MI, MIB, MIB2);
209  MI.eraseFromParent();
210  return true;
211  }
212 
213  return false;
214 }
215 
216 /// Check whether this chunk matches the pattern '1...0...'. This pattern
217 /// starts a contiguous sequence of ones if we look at the bits from the LSB
218 /// towards the MSB.
219 static bool isStartChunk(uint64_t Chunk) {
220  if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
221  return false;
222 
223  return isMask_64(~Chunk);
224 }
225 
226 /// Check whether this chunk matches the pattern '0...1...' This pattern
227 /// ends a contiguous sequence of ones if we look at the bits from the LSB
228 /// towards the MSB.
229 static bool isEndChunk(uint64_t Chunk) {
230  if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
231  return false;
232 
233  return isMask_64(Chunk);
234 }
235 
236 /// Clear or set all bits in the chunk at the given index.
237 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
238  const uint64_t Mask = 0xFFFF;
239 
240  if (Clear)
241  // Clear chunk in the immediate.
242  Imm &= ~(Mask << (Idx * 16));
243  else
244  // Set all bits in the immediate for the particular chunk.
245  Imm |= Mask << (Idx * 16);
246 
247  return Imm;
248 }
249 
250 /// Check whether the constant contains a sequence of contiguous ones,
251 /// which might be interrupted by one or two chunks. If so, materialize the
252 /// sequence of contiguous ones with an ORR instruction.
253 /// Materialize the chunks which are either interrupting the sequence or outside
254 /// of the sequence with a MOVK instruction.
255 ///
256 /// Assuming S is a chunk which starts the sequence (1...0...), E is a chunk
257 /// which ends the sequence (0...1...). Then we are looking for constants which
258 /// contain at least one S and E chunk.
259 /// E.g. |E|A|B|S|, |A|E|B|S| or |A|B|E|S|.
260 ///
261 /// We are also looking for constants like |S|A|B|E| where the contiguous
262 /// sequence of ones wraps around the MSB into the LSB.
263 static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
264  MachineBasicBlock &MBB,
266  const AArch64InstrInfo *TII) {
267  const int NotSet = -1;
268  const uint64_t Mask = 0xFFFF;
269 
270  int StartIdx = NotSet;
271  int EndIdx = NotSet;
272  // Try to find the chunks which start/end a contiguous sequence of ones.
273  for (int Idx = 0; Idx < 4; ++Idx) {
274  int64_t Chunk = getChunk(UImm, Idx);
275  // Sign extend the 16-bit chunk to 64-bit.
276  Chunk = (Chunk << 48) >> 48;
277 
278  if (isStartChunk(Chunk))
279  StartIdx = Idx;
280  else if (isEndChunk(Chunk))
281  EndIdx = Idx;
282  }
283 
284  // Early exit in case we can't find a start/end chunk.
285  if (StartIdx == NotSet || EndIdx == NotSet)
286  return false;
287 
288  // Outside of the contiguous sequence of ones everything needs to be zero.
289  uint64_t Outside = 0;
290  // Chunks between the start and end chunk need to have all their bits set.
291  uint64_t Inside = Mask;
292 
293  // If our contiguous sequence of ones wraps around from the MSB into the LSB,
294  // just swap indices and pretend we are materializing a contiguous sequence
295  // of zeros surrounded by a contiguous sequence of ones.
296  if (StartIdx > EndIdx) {
297  std::swap(StartIdx, EndIdx);
298  std::swap(Outside, Inside);
299  }
300 
301  uint64_t OrrImm = UImm;
302  int FirstMovkIdx = NotSet;
303  int SecondMovkIdx = NotSet;
304 
305  // Find out which chunks we need to patch up to obtain a contiguous sequence
306  // of ones.
307  for (int Idx = 0; Idx < 4; ++Idx) {
308  const uint64_t Chunk = getChunk(UImm, Idx);
309 
310  // Check whether we are looking at a chunk which is not part of the
311  // contiguous sequence of ones.
312  if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) {
313  OrrImm = updateImm(OrrImm, Idx, Outside == 0);
314 
315  // Remember the index we need to patch.
316  if (FirstMovkIdx == NotSet)
317  FirstMovkIdx = Idx;
318  else
319  SecondMovkIdx = Idx;
320 
321  // Check whether we are looking a chunk which is part of the contiguous
322  // sequence of ones.
323  } else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) {
324  OrrImm = updateImm(OrrImm, Idx, Inside != Mask);
325 
326  // Remember the index we need to patch.
327  if (FirstMovkIdx == NotSet)
328  FirstMovkIdx = Idx;
329  else
330  SecondMovkIdx = Idx;
331  }
332  }
333  assert(FirstMovkIdx != NotSet && "Constant materializable with single ORR!");
334 
335  // Create the ORR-immediate instruction.
336  uint64_t Encoding = 0;
337  AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
338  MachineInstrBuilder MIB =
339  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
340  .add(MI.getOperand(0))
341  .addReg(AArch64::XZR)
342  .addImm(Encoding);
343 
344  const unsigned DstReg = MI.getOperand(0).getReg();
345  const bool DstIsDead = MI.getOperand(0).isDead();
346 
347  const bool SingleMovk = SecondMovkIdx == NotSet;
348  // Create the first MOVK instruction.
349  MachineInstrBuilder MIB1 =
350  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
351  .addReg(DstReg,
352  RegState::Define | getDeadRegState(DstIsDead && SingleMovk))
353  .addReg(DstReg)
354  .addImm(getChunk(UImm, FirstMovkIdx))
355  .addImm(
356  AArch64_AM::getShifterImm(AArch64_AM::LSL, FirstMovkIdx * 16));
357 
358  // Early exit in case we only need to emit a single MOVK instruction.
359  if (SingleMovk) {
360  transferImpOps(MI, MIB, MIB1);
361  MI.eraseFromParent();
362  return true;
363  }
364 
365  // Create the second MOVK instruction.
366  MachineInstrBuilder MIB2 =
367  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
368  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
369  .addReg(DstReg)
370  .addImm(getChunk(UImm, SecondMovkIdx))
371  .addImm(
372  AArch64_AM::getShifterImm(AArch64_AM::LSL, SecondMovkIdx * 16));
373 
374  transferImpOps(MI, MIB, MIB2);
375  MI.eraseFromParent();
376  return true;
377 }
378 
379 /// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
380 /// real move-immediate instructions to synthesize the immediate.
381 bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
383  unsigned BitSize) {
384  MachineInstr &MI = *MBBI;
385  unsigned DstReg = MI.getOperand(0).getReg();
386  uint64_t Imm = MI.getOperand(1).getImm();
387  const unsigned Mask = 0xFFFF;
388 
389  if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
390  // Useless def, and we don't want to risk creating an invalid ORR (which
391  // would really write to sp).
392  MI.eraseFromParent();
393  return true;
394  }
395 
396  // Scan the immediate and count the number of 16-bit chunks which are either
397  // all ones or all zeros.
398  unsigned OneChunks = 0;
399  unsigned ZeroChunks = 0;
400  for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
401  const unsigned Chunk = (Imm >> Shift) & Mask;
402  if (Chunk == Mask)
403  OneChunks++;
404  else if (Chunk == 0)
405  ZeroChunks++;
406  }
407 
408  // FIXME: Prefer MOVZ/MOVN over ORR because of the rules for the "mov"
409  // alias.
410 
411  // Try a single ORR.
412  uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
413  uint64_t Encoding;
414  if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
415  unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
416  MachineInstrBuilder MIB =
417  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
418  .add(MI.getOperand(0))
419  .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
420  .addImm(Encoding);
421  transferImpOps(MI, MIB, MIB);
422  MI.eraseFromParent();
423  return true;
424  }
425 
426  // Two instruction sequences.
427  //
428  // Prefer MOVZ/MOVN followed by MOVK; it's more readable, and possibly the
429  // fastest sequence with fast literal generation.
430  if (OneChunks >= (BitSize / 16) - 2 || ZeroChunks >= (BitSize / 16) - 2)
431  return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
432 
433  assert(BitSize == 64 && "All 32-bit immediates can be expanded with a"
434  "MOVZ/MOVK pair");
435 
436  // Try other two-instruction sequences.
437 
438  // 64-bit ORR followed by MOVK.
439  // We try to construct the ORR immediate in three different ways: either we
440  // zero out the chunk which will be replaced, we fill the chunk which will
441  // be replaced with ones, or we take the bit pattern from the other half of
442  // the 64-bit immediate. This is comprehensive because of the way ORR
443  // immediates are constructed.
444  for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
445  uint64_t ShiftedMask = (0xFFFFULL << Shift);
446  uint64_t ZeroChunk = UImm & ~ShiftedMask;
447  uint64_t OneChunk = UImm | ShiftedMask;
448  uint64_t RotatedImm = (UImm << 32) | (UImm >> 32);
449  uint64_t ReplicateChunk = ZeroChunk | (RotatedImm & ShiftedMask);
450  if (AArch64_AM::processLogicalImmediate(ZeroChunk, BitSize, Encoding) ||
451  AArch64_AM::processLogicalImmediate(OneChunk, BitSize, Encoding) ||
453  BitSize, Encoding)) {
454  // Create the ORR-immediate instruction.
455  MachineInstrBuilder MIB =
456  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
457  .add(MI.getOperand(0))
458  .addReg(AArch64::XZR)
459  .addImm(Encoding);
460 
461  // Create the MOVK instruction.
462  const unsigned Imm16 = getChunk(UImm, Shift / 16);
463  const unsigned DstReg = MI.getOperand(0).getReg();
464  const bool DstIsDead = MI.getOperand(0).isDead();
465  MachineInstrBuilder MIB1 =
466  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
467  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
468  .addReg(DstReg)
469  .addImm(Imm16)
471 
472  transferImpOps(MI, MIB, MIB1);
473  MI.eraseFromParent();
474  return true;
475  }
476  }
477 
478  // FIXME: Add more two-instruction sequences.
479 
480  // Three instruction sequences.
481  //
482  // Prefer MOVZ/MOVN followed by two MOVK; it's more readable, and possibly
483  // the fastest sequence with fast literal generation. (If neither MOVK is
484  // part of a fast literal generation pair, it could be slower than the
485  // four-instruction sequence, but we won't worry about that for now.)
486  if (OneChunks || ZeroChunks)
487  return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
488 
489  // Check for identical 16-bit chunks within the constant and if so materialize
490  // them with a single ORR instruction. The remaining one or two 16-bit chunks
491  // will be materialized with MOVK instructions.
492  if (BitSize == 64 && tryToreplicateChunks(UImm, MI, MBB, MBBI, TII))
493  return true;
494 
495  // Check whether the constant contains a sequence of contiguous ones, which
496  // might be interrupted by one or two chunks. If so, materialize the sequence
497  // of contiguous ones with an ORR instruction. Materialize the chunks which
498  // are either interrupting the sequence or outside of the sequence with a
499  // MOVK instruction.
500  if (BitSize == 64 && trySequenceOfOnes(UImm, MI, MBB, MBBI, TII))
501  return true;
502 
503  // We found no possible two or three instruction sequence; use the general
504  // four-instruction sequence.
505  return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
506 }
507 
508 /// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to a
509 /// MOVZ or MOVN of width BitSize followed by up to 3 MOVK instructions.
510 bool AArch64ExpandPseudo::expandMOVImmSimple(MachineBasicBlock &MBB,
512  unsigned BitSize,
513  unsigned OneChunks,
514  unsigned ZeroChunks) {
515  MachineInstr &MI = *MBBI;
516  unsigned DstReg = MI.getOperand(0).getReg();
517  uint64_t Imm = MI.getOperand(1).getImm();
518  const unsigned Mask = 0xFFFF;
519 
520  // Use a MOVZ or MOVN instruction to set the high bits, followed by one or
521  // more MOVK instructions to insert additional 16-bit portions into the
522  // lower bits.
523  bool isNeg = false;
524 
525  // Use MOVN to materialize the high bits if we have more all one chunks
526  // than all zero chunks.
527  if (OneChunks > ZeroChunks) {
528  isNeg = true;
529  Imm = ~Imm;
530  }
531 
532  unsigned FirstOpc;
533  if (BitSize == 32) {
534  Imm &= (1LL << 32) - 1;
535  FirstOpc = (isNeg ? AArch64::MOVNWi : AArch64::MOVZWi);
536  } else {
537  FirstOpc = (isNeg ? AArch64::MOVNXi : AArch64::MOVZXi);
538  }
539  unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
540  unsigned LastShift = 0; // LSL amount for last MOVK
541  if (Imm != 0) {
542  unsigned LZ = countLeadingZeros(Imm);
543  unsigned TZ = countTrailingZeros(Imm);
544  Shift = (TZ / 16) * 16;
545  LastShift = ((63 - LZ) / 16) * 16;
546  }
547  unsigned Imm16 = (Imm >> Shift) & Mask;
548  bool DstIsDead = MI.getOperand(0).isDead();
549  MachineInstrBuilder MIB1 =
550  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
551  .addReg(DstReg, RegState::Define |
552  getDeadRegState(DstIsDead && Shift == LastShift))
553  .addImm(Imm16)
555 
556  // If a MOVN was used for the high bits of a negative value, flip the rest
557  // of the bits back for use with MOVK.
558  if (isNeg)
559  Imm = ~Imm;
560 
561  if (Shift == LastShift) {
562  transferImpOps(MI, MIB1, MIB1);
563  MI.eraseFromParent();
564  return true;
565  }
566 
567  MachineInstrBuilder MIB2;
568  unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
569  while (Shift < LastShift) {
570  Shift += 16;
571  Imm16 = (Imm >> Shift) & Mask;
572  if (Imm16 == (isNeg ? Mask : 0))
573  continue; // This 16-bit portion is already set correctly.
574  MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
575  .addReg(DstReg,
577  getDeadRegState(DstIsDead && Shift == LastShift))
578  .addReg(DstReg)
579  .addImm(Imm16)
581  }
582 
583  transferImpOps(MI, MIB1, MIB2);
584  MI.eraseFromParent();
585  return true;
586 }
587 
588 bool AArch64ExpandPseudo::expandCMP_SWAP(
589  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp,
590  unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
591  MachineBasicBlock::iterator &NextMBBI) {
592  MachineInstr &MI = *MBBI;
593  DebugLoc DL = MI.getDebugLoc();
594  const MachineOperand &Dest = MI.getOperand(0);
595  unsigned StatusReg = MI.getOperand(1).getReg();
596  bool StatusDead = MI.getOperand(1).isDead();
597  // Duplicating undef operands into 2 instructions does not guarantee the same
598  // value on both; However undef should be replaced by xzr anyway.
599  assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
600  unsigned AddrReg = MI.getOperand(2).getReg();
601  unsigned DesiredReg = MI.getOperand(3).getReg();
602  unsigned NewReg = MI.getOperand(4).getReg();
603 
604  MachineFunction *MF = MBB.getParent();
605  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
606  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
607  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
608 
609  MF->insert(++MBB.getIterator(), LoadCmpBB);
610  MF->insert(++LoadCmpBB->getIterator(), StoreBB);
611  MF->insert(++StoreBB->getIterator(), DoneBB);
612 
613  // .Lloadcmp:
614  // mov wStatus, 0
615  // ldaxr xDest, [xAddr]
616  // cmp xDest, xDesired
617  // b.ne .Ldone
618  if (!StatusDead)
619  BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
620  .addImm(0).addImm(0);
621  BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
622  .addReg(AddrReg);
623  BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
624  .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
625  .addReg(DesiredReg)
626  .addImm(ExtendImm);
627  BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
628  .addImm(AArch64CC::NE)
629  .addMBB(DoneBB)
630  .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
631  LoadCmpBB->addSuccessor(DoneBB);
632  LoadCmpBB->addSuccessor(StoreBB);
633 
634  // .Lstore:
635  // stlxr wStatus, xNew, [xAddr]
636  // cbnz wStatus, .Lloadcmp
637  BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
638  .addReg(NewReg)
639  .addReg(AddrReg);
640  BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
641  .addReg(StatusReg, getKillRegState(StatusDead))
642  .addMBB(LoadCmpBB);
643  StoreBB->addSuccessor(LoadCmpBB);
644  StoreBB->addSuccessor(DoneBB);
645 
646  DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
647  DoneBB->transferSuccessors(&MBB);
648 
649  MBB.addSuccessor(LoadCmpBB);
650 
651  NextMBBI = MBB.end();
652  MI.eraseFromParent();
653 
654  // Recompute livein lists.
655  LivePhysRegs LiveRegs;
656  computeAndAddLiveIns(LiveRegs, *DoneBB);
657  computeAndAddLiveIns(LiveRegs, *StoreBB);
658  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
659  // Do an extra pass around the loop to get loop carried registers right.
660  StoreBB->clearLiveIns();
661  computeAndAddLiveIns(LiveRegs, *StoreBB);
662  LoadCmpBB->clearLiveIns();
663  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
664 
665  return true;
666 }
667 
668 bool AArch64ExpandPseudo::expandCMP_SWAP_128(
670  MachineBasicBlock::iterator &NextMBBI) {
671  MachineInstr &MI = *MBBI;
672  DebugLoc DL = MI.getDebugLoc();
673  MachineOperand &DestLo = MI.getOperand(0);
674  MachineOperand &DestHi = MI.getOperand(1);
675  unsigned StatusReg = MI.getOperand(2).getReg();
676  bool StatusDead = MI.getOperand(2).isDead();
677  // Duplicating undef operands into 2 instructions does not guarantee the same
678  // value on both; However undef should be replaced by xzr anyway.
679  assert(!MI.getOperand(3).isUndef() && "cannot handle undef");
680  unsigned AddrReg = MI.getOperand(3).getReg();
681  unsigned DesiredLoReg = MI.getOperand(4).getReg();
682  unsigned DesiredHiReg = MI.getOperand(5).getReg();
683  unsigned NewLoReg = MI.getOperand(6).getReg();
684  unsigned NewHiReg = MI.getOperand(7).getReg();
685 
686  MachineFunction *MF = MBB.getParent();
687  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
688  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
689  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
690 
691  MF->insert(++MBB.getIterator(), LoadCmpBB);
692  MF->insert(++LoadCmpBB->getIterator(), StoreBB);
693  MF->insert(++StoreBB->getIterator(), DoneBB);
694 
695  // .Lloadcmp:
696  // ldaxp xDestLo, xDestHi, [xAddr]
697  // cmp xDestLo, xDesiredLo
698  // sbcs xDestHi, xDesiredHi
699  // b.ne .Ldone
700  BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX))
701  .addReg(DestLo.getReg(), RegState::Define)
702  .addReg(DestHi.getReg(), RegState::Define)
703  .addReg(AddrReg);
704  BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
705  .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
706  .addReg(DesiredLoReg)
707  .addImm(0);
708  BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
709  .addUse(AArch64::WZR)
710  .addUse(AArch64::WZR)
712  BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
713  .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
714  .addReg(DesiredHiReg)
715  .addImm(0);
716  BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
717  .addUse(StatusReg, RegState::Kill)
718  .addUse(StatusReg, RegState::Kill)
720  BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
721  .addUse(StatusReg, getKillRegState(StatusDead))
722  .addMBB(DoneBB);
723  LoadCmpBB->addSuccessor(DoneBB);
724  LoadCmpBB->addSuccessor(StoreBB);
725 
726  // .Lstore:
727  // stlxp wStatus, xNewLo, xNewHi, [xAddr]
728  // cbnz wStatus, .Lloadcmp
729  BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg)
730  .addReg(NewLoReg)
731  .addReg(NewHiReg)
732  .addReg(AddrReg);
733  BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
734  .addReg(StatusReg, getKillRegState(StatusDead))
735  .addMBB(LoadCmpBB);
736  StoreBB->addSuccessor(LoadCmpBB);
737  StoreBB->addSuccessor(DoneBB);
738 
739  DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
740  DoneBB->transferSuccessors(&MBB);
741 
742  MBB.addSuccessor(LoadCmpBB);
743 
744  NextMBBI = MBB.end();
745  MI.eraseFromParent();
746 
747  // Recompute liveness bottom up.
748  LivePhysRegs LiveRegs;
749  computeAndAddLiveIns(LiveRegs, *DoneBB);
750  computeAndAddLiveIns(LiveRegs, *StoreBB);
751  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
752  // Do an extra pass in the loop to get the loop carried dependencies right.
753  StoreBB->clearLiveIns();
754  computeAndAddLiveIns(LiveRegs, *StoreBB);
755  LoadCmpBB->clearLiveIns();
756  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
757 
758  return true;
759 }
760 
761 /// If MBBI references a pseudo instruction that should be expanded here,
762 /// do the expansion and return true. Otherwise return false.
763 bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
765  MachineBasicBlock::iterator &NextMBBI) {
766  MachineInstr &MI = *MBBI;
767  unsigned Opcode = MI.getOpcode();
768  switch (Opcode) {
769  default:
770  break;
771 
772  case AArch64::ADDWrr:
773  case AArch64::SUBWrr:
774  case AArch64::ADDXrr:
775  case AArch64::SUBXrr:
776  case AArch64::ADDSWrr:
777  case AArch64::SUBSWrr:
778  case AArch64::ADDSXrr:
779  case AArch64::SUBSXrr:
780  case AArch64::ANDWrr:
781  case AArch64::ANDXrr:
782  case AArch64::BICWrr:
783  case AArch64::BICXrr:
784  case AArch64::ANDSWrr:
785  case AArch64::ANDSXrr:
786  case AArch64::BICSWrr:
787  case AArch64::BICSXrr:
788  case AArch64::EONWrr:
789  case AArch64::EONXrr:
790  case AArch64::EORWrr:
791  case AArch64::EORXrr:
792  case AArch64::ORNWrr:
793  case AArch64::ORNXrr:
794  case AArch64::ORRWrr:
795  case AArch64::ORRXrr: {
796  unsigned Opcode;
797  switch (MI.getOpcode()) {
798  default:
799  return false;
800  case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break;
801  case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break;
802  case AArch64::ADDXrr: Opcode = AArch64::ADDXrs; break;
803  case AArch64::SUBXrr: Opcode = AArch64::SUBXrs; break;
804  case AArch64::ADDSWrr: Opcode = AArch64::ADDSWrs; break;
805  case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break;
806  case AArch64::ADDSXrr: Opcode = AArch64::ADDSXrs; break;
807  case AArch64::SUBSXrr: Opcode = AArch64::SUBSXrs; break;
808  case AArch64::ANDWrr: Opcode = AArch64::ANDWrs; break;
809  case AArch64::ANDXrr: Opcode = AArch64::ANDXrs; break;
810  case AArch64::BICWrr: Opcode = AArch64::BICWrs; break;
811  case AArch64::BICXrr: Opcode = AArch64::BICXrs; break;
812  case AArch64::ANDSWrr: Opcode = AArch64::ANDSWrs; break;
813  case AArch64::ANDSXrr: Opcode = AArch64::ANDSXrs; break;
814  case AArch64::BICSWrr: Opcode = AArch64::BICSWrs; break;
815  case AArch64::BICSXrr: Opcode = AArch64::BICSXrs; break;
816  case AArch64::EONWrr: Opcode = AArch64::EONWrs; break;
817  case AArch64::EONXrr: Opcode = AArch64::EONXrs; break;
818  case AArch64::EORWrr: Opcode = AArch64::EORWrs; break;
819  case AArch64::EORXrr: Opcode = AArch64::EORXrs; break;
820  case AArch64::ORNWrr: Opcode = AArch64::ORNWrs; break;
821  case AArch64::ORNXrr: Opcode = AArch64::ORNXrs; break;
822  case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break;
823  case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break;
824  }
825  MachineInstrBuilder MIB1 =
826  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
827  MI.getOperand(0).getReg())
828  .add(MI.getOperand(1))
829  .add(MI.getOperand(2))
831  transferImpOps(MI, MIB1, MIB1);
832  MI.eraseFromParent();
833  return true;
834  }
835 
836  case AArch64::LOADgot: {
837  MachineFunction *MF = MBB.getParent();
838  unsigned DstReg = MI.getOperand(0).getReg();
839  const MachineOperand &MO1 = MI.getOperand(1);
840  unsigned Flags = MO1.getTargetFlags();
841 
842  if (MF->getTarget().getCodeModel() == CodeModel::Tiny) {
843  // Tiny codemodel expand to LDR
844  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
845  TII->get(AArch64::LDRXl), DstReg);
846 
847  if (MO1.isGlobal()) {
848  MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags);
849  } else if (MO1.isSymbol()) {
850  MIB.addExternalSymbol(MO1.getSymbolName(), Flags);
851  } else {
852  assert(MO1.isCPI() &&
853  "Only expect globals, externalsymbols, or constant pools");
854  MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags);
855  }
856  } else {
857  // Small codemodel expand into ADRP + LDR.
858  MachineInstrBuilder MIB1 =
859  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
860  MachineInstrBuilder MIB2 =
861  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRXui))
862  .add(MI.getOperand(0))
863  .addReg(DstReg);
864 
865  if (MO1.isGlobal()) {
866  MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE);
867  MIB2.addGlobalAddress(MO1.getGlobal(), 0,
869  } else if (MO1.isSymbol()) {
871  MIB2.addExternalSymbol(MO1.getSymbolName(), Flags |
874  } else {
875  assert(MO1.isCPI() &&
876  "Only expect globals, externalsymbols, or constant pools");
877  MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
878  Flags | AArch64II::MO_PAGE);
879  MIB2.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
880  Flags | AArch64II::MO_PAGEOFF |
882  }
883 
884  transferImpOps(MI, MIB1, MIB2);
885  }
886  MI.eraseFromParent();
887  return true;
888  }
889 
890  case AArch64::MOVaddr:
891  case AArch64::MOVaddrJT:
892  case AArch64::MOVaddrCP:
893  case AArch64::MOVaddrBA:
894  case AArch64::MOVaddrTLS:
895  case AArch64::MOVaddrEXT: {
896  // Expand into ADRP + ADD.
897  unsigned DstReg = MI.getOperand(0).getReg();
898  MachineInstrBuilder MIB1 =
899  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
900  .add(MI.getOperand(1));
901 
902  MachineInstrBuilder MIB2 =
903  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
904  .add(MI.getOperand(0))
905  .addReg(DstReg)
906  .add(MI.getOperand(2))
907  .addImm(0);
908 
909  transferImpOps(MI, MIB1, MIB2);
910  MI.eraseFromParent();
911  return true;
912  }
913  case AArch64::ADDlowTLS:
914  // Produce a plain ADD
915  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
916  .add(MI.getOperand(0))
917  .add(MI.getOperand(1))
918  .add(MI.getOperand(2))
919  .addImm(0);
920  MI.eraseFromParent();
921  return true;
922 
923  case AArch64::MOVbaseTLS: {
924  unsigned DstReg = MI.getOperand(0).getReg();
925  auto SysReg = AArch64SysReg::TPIDR_EL0;
926  MachineFunction *MF = MBB.getParent();
927  if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
929  SysReg = AArch64SysReg::TPIDR_EL1;
930  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
931  .addImm(SysReg);
932  MI.eraseFromParent();
933  return true;
934  }
935 
936  case AArch64::MOVi32imm:
937  return expandMOVImm(MBB, MBBI, 32);
938  case AArch64::MOVi64imm:
939  return expandMOVImm(MBB, MBBI, 64);
940  case AArch64::RET_ReallyLR: {
941  // Hiding the LR use with RET_ReallyLR may lead to extra kills in the
942  // function and missing live-ins. We are fine in practice because callee
943  // saved register handling ensures the register value is restored before
944  // RET, but we need the undef flag here to appease the MachineVerifier
945  // liveness checks.
946  MachineInstrBuilder MIB =
947  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
948  .addReg(AArch64::LR, RegState::Undef);
949  transferImpOps(MI, MIB, MIB);
950  MI.eraseFromParent();
951  return true;
952  }
953  case AArch64::CMP_SWAP_8:
954  return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRB, AArch64::STLXRB,
955  AArch64::SUBSWrx,
957  AArch64::WZR, NextMBBI);
958  case AArch64::CMP_SWAP_16:
959  return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRH, AArch64::STLXRH,
960  AArch64::SUBSWrx,
962  AArch64::WZR, NextMBBI);
963  case AArch64::CMP_SWAP_32:
964  return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRW, AArch64::STLXRW,
965  AArch64::SUBSWrs,
967  AArch64::WZR, NextMBBI);
968  case AArch64::CMP_SWAP_64:
969  return expandCMP_SWAP(MBB, MBBI,
970  AArch64::LDAXRX, AArch64::STLXRX, AArch64::SUBSXrs,
972  AArch64::XZR, NextMBBI);
973  case AArch64::CMP_SWAP_128:
974  return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);
975 
976  case AArch64::AESMCrrTied:
977  case AArch64::AESIMCrrTied: {
978  MachineInstrBuilder MIB =
979  BuildMI(MBB, MBBI, MI.getDebugLoc(),
980  TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
981  AArch64::AESIMCrr))
982  .add(MI.getOperand(0))
983  .add(MI.getOperand(1));
984  transferImpOps(MI, MIB, MIB);
985  MI.eraseFromParent();
986  return true;
987  }
988  }
989  return false;
990 }
991 
992 /// Iterate over the instructions in basic block MBB and expand any
993 /// pseudo instructions. Return true if anything was modified.
994 bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
995  bool Modified = false;
996 
997  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
998  while (MBBI != E) {
999  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1000  Modified |= expandMI(MBB, MBBI, NMBBI);
1001  MBBI = NMBBI;
1002  }
1003 
1004  return Modified;
1005 }
1006 
1007 bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1008  TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
1009 
1010  bool Modified = false;
1011  for (auto &MBB : MF)
1012  Modified |= expandMBB(MBB);
1013  return Modified;
1014 }
1015 
1016 /// Returns an instance of the pseudo instruction expansion pass.
1018  return new AArch64ExpandPseudo();
1019 }
unsigned getTargetFlags() const
const MachineInstrBuilder & add(const MachineOperand &MO) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of ...
A debug info location.
Definition: DebugLoc.h:33
static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const AArch64InstrInfo *TII)
Check for identical 16-bit chunks within the constant and if so materialize them with a single ORR in...
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isOSFuchsia() const
Definition: Triple.h:494
static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding)
Check whether the given 16-bit chunk replicated to full 64-bit width can be materialized with an ORR ...
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo", AARCH64_EXPAND_PSEUDO_NAME, false, false) static void transferImpOps(MachineInstr &OldMI
Transfer implicit operands on the pseudo instruction to the instructions created from the expansion...
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
const char * getSymbolName() const
constexpr bool isMask_64(uint64_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
Definition: MathExtras.h:410
virtual const TargetInstrInfo * getInstrInfo() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
unsigned getKillRegState(bool B)
static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear)
Clear or set all bits in the chunk at the given index.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
unsigned getDeadRegState(bool B)
static bool isStartChunk(uint64_t Chunk)
Check whether this chunk matches the pattern &#39;1...0...&#39;.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
void initializeAArch64ExpandPseudoPass(PassRegistry &)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const GlobalValue * getGlobal() const
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
const Triple & getTargetTriple() const
self_iterator getIterator()
Definition: ilist_node.h:81
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx)
Helper function which extracts the specified 16-bit chunk from a 64-bit value.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
static bool isEndChunk(uint64_t Chunk)
Check whether this chunk matches the pattern &#39;0...1...&#39; This pattern ends a contiguous sequence of on...
static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const AArch64InstrInfo *TII)
Check whether the constant contains a sequence of contiguous ones, which might be interrupted by one ...
int64_t getImm() const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
CodeModel::Model getCodeModel() const
Returns the code model.
static unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm)
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit...
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
int64_t getOffset() const
Return the offset from the symbol in this operand.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
#define AARCH64_EXPAND_PSEUDO_NAME
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413