LLVM  6.0.0svn
AArch64BaseInfo.h
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1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
19 
20 // FIXME: Is it easiest to fix this layering violation by moving the .inc
21 // #includes from AArch64MCTargetDesc.h to here?
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
27 
28 namespace llvm {
29 
30 inline static unsigned getWRegFromXReg(unsigned Reg) {
31  switch (Reg) {
32  case AArch64::X0: return AArch64::W0;
33  case AArch64::X1: return AArch64::W1;
34  case AArch64::X2: return AArch64::W2;
35  case AArch64::X3: return AArch64::W3;
36  case AArch64::X4: return AArch64::W4;
37  case AArch64::X5: return AArch64::W5;
38  case AArch64::X6: return AArch64::W6;
39  case AArch64::X7: return AArch64::W7;
40  case AArch64::X8: return AArch64::W8;
41  case AArch64::X9: return AArch64::W9;
42  case AArch64::X10: return AArch64::W10;
43  case AArch64::X11: return AArch64::W11;
44  case AArch64::X12: return AArch64::W12;
45  case AArch64::X13: return AArch64::W13;
46  case AArch64::X14: return AArch64::W14;
47  case AArch64::X15: return AArch64::W15;
48  case AArch64::X16: return AArch64::W16;
49  case AArch64::X17: return AArch64::W17;
50  case AArch64::X18: return AArch64::W18;
51  case AArch64::X19: return AArch64::W19;
52  case AArch64::X20: return AArch64::W20;
53  case AArch64::X21: return AArch64::W21;
54  case AArch64::X22: return AArch64::W22;
55  case AArch64::X23: return AArch64::W23;
56  case AArch64::X24: return AArch64::W24;
57  case AArch64::X25: return AArch64::W25;
58  case AArch64::X26: return AArch64::W26;
59  case AArch64::X27: return AArch64::W27;
60  case AArch64::X28: return AArch64::W28;
61  case AArch64::FP: return AArch64::W29;
62  case AArch64::LR: return AArch64::W30;
63  case AArch64::SP: return AArch64::WSP;
64  case AArch64::XZR: return AArch64::WZR;
65  }
66  // For anything else, return it unchanged.
67  return Reg;
68 }
69 
70 inline static unsigned getXRegFromWReg(unsigned Reg) {
71  switch (Reg) {
72  case AArch64::W0: return AArch64::X0;
73  case AArch64::W1: return AArch64::X1;
74  case AArch64::W2: return AArch64::X2;
75  case AArch64::W3: return AArch64::X3;
76  case AArch64::W4: return AArch64::X4;
77  case AArch64::W5: return AArch64::X5;
78  case AArch64::W6: return AArch64::X6;
79  case AArch64::W7: return AArch64::X7;
80  case AArch64::W8: return AArch64::X8;
81  case AArch64::W9: return AArch64::X9;
82  case AArch64::W10: return AArch64::X10;
83  case AArch64::W11: return AArch64::X11;
84  case AArch64::W12: return AArch64::X12;
85  case AArch64::W13: return AArch64::X13;
86  case AArch64::W14: return AArch64::X14;
87  case AArch64::W15: return AArch64::X15;
88  case AArch64::W16: return AArch64::X16;
89  case AArch64::W17: return AArch64::X17;
90  case AArch64::W18: return AArch64::X18;
91  case AArch64::W19: return AArch64::X19;
92  case AArch64::W20: return AArch64::X20;
93  case AArch64::W21: return AArch64::X21;
94  case AArch64::W22: return AArch64::X22;
95  case AArch64::W23: return AArch64::X23;
96  case AArch64::W24: return AArch64::X24;
97  case AArch64::W25: return AArch64::X25;
98  case AArch64::W26: return AArch64::X26;
99  case AArch64::W27: return AArch64::X27;
100  case AArch64::W28: return AArch64::X28;
101  case AArch64::W29: return AArch64::FP;
102  case AArch64::W30: return AArch64::LR;
103  case AArch64::WSP: return AArch64::SP;
104  case AArch64::WZR: return AArch64::XZR;
105  }
106  // For anything else, return it unchanged.
107  return Reg;
108 }
109 
110 static inline unsigned getBRegFromDReg(unsigned Reg) {
111  switch (Reg) {
112  case AArch64::D0: return AArch64::B0;
113  case AArch64::D1: return AArch64::B1;
114  case AArch64::D2: return AArch64::B2;
115  case AArch64::D3: return AArch64::B3;
116  case AArch64::D4: return AArch64::B4;
117  case AArch64::D5: return AArch64::B5;
118  case AArch64::D6: return AArch64::B6;
119  case AArch64::D7: return AArch64::B7;
120  case AArch64::D8: return AArch64::B8;
121  case AArch64::D9: return AArch64::B9;
122  case AArch64::D10: return AArch64::B10;
123  case AArch64::D11: return AArch64::B11;
124  case AArch64::D12: return AArch64::B12;
125  case AArch64::D13: return AArch64::B13;
126  case AArch64::D14: return AArch64::B14;
127  case AArch64::D15: return AArch64::B15;
128  case AArch64::D16: return AArch64::B16;
129  case AArch64::D17: return AArch64::B17;
130  case AArch64::D18: return AArch64::B18;
131  case AArch64::D19: return AArch64::B19;
132  case AArch64::D20: return AArch64::B20;
133  case AArch64::D21: return AArch64::B21;
134  case AArch64::D22: return AArch64::B22;
135  case AArch64::D23: return AArch64::B23;
136  case AArch64::D24: return AArch64::B24;
137  case AArch64::D25: return AArch64::B25;
138  case AArch64::D26: return AArch64::B26;
139  case AArch64::D27: return AArch64::B27;
140  case AArch64::D28: return AArch64::B28;
141  case AArch64::D29: return AArch64::B29;
142  case AArch64::D30: return AArch64::B30;
143  case AArch64::D31: return AArch64::B31;
144  }
145  // For anything else, return it unchanged.
146  return Reg;
147 }
148 
149 
150 static inline unsigned getDRegFromBReg(unsigned Reg) {
151  switch (Reg) {
152  case AArch64::B0: return AArch64::D0;
153  case AArch64::B1: return AArch64::D1;
154  case AArch64::B2: return AArch64::D2;
155  case AArch64::B3: return AArch64::D3;
156  case AArch64::B4: return AArch64::D4;
157  case AArch64::B5: return AArch64::D5;
158  case AArch64::B6: return AArch64::D6;
159  case AArch64::B7: return AArch64::D7;
160  case AArch64::B8: return AArch64::D8;
161  case AArch64::B9: return AArch64::D9;
162  case AArch64::B10: return AArch64::D10;
163  case AArch64::B11: return AArch64::D11;
164  case AArch64::B12: return AArch64::D12;
165  case AArch64::B13: return AArch64::D13;
166  case AArch64::B14: return AArch64::D14;
167  case AArch64::B15: return AArch64::D15;
168  case AArch64::B16: return AArch64::D16;
169  case AArch64::B17: return AArch64::D17;
170  case AArch64::B18: return AArch64::D18;
171  case AArch64::B19: return AArch64::D19;
172  case AArch64::B20: return AArch64::D20;
173  case AArch64::B21: return AArch64::D21;
174  case AArch64::B22: return AArch64::D22;
175  case AArch64::B23: return AArch64::D23;
176  case AArch64::B24: return AArch64::D24;
177  case AArch64::B25: return AArch64::D25;
178  case AArch64::B26: return AArch64::D26;
179  case AArch64::B27: return AArch64::D27;
180  case AArch64::B28: return AArch64::D28;
181  case AArch64::B29: return AArch64::D29;
182  case AArch64::B30: return AArch64::D30;
183  case AArch64::B31: return AArch64::D31;
184  }
185  // For anything else, return it unchanged.
186  return Reg;
187 }
188 
189 namespace AArch64CC {
190 
191 // The CondCodes constants map directly to the 4-bit encoding of the condition
192 // field for predicated instructions.
193 enum CondCode { // Meaning (integer) Meaning (floating-point)
194  EQ = 0x0, // Equal Equal
195  NE = 0x1, // Not equal Not equal, or unordered
196  HS = 0x2, // Unsigned higher or same >, ==, or unordered
197  LO = 0x3, // Unsigned lower Less than
198  MI = 0x4, // Minus, negative Less than
199  PL = 0x5, // Plus, positive or zero >, ==, or unordered
200  VS = 0x6, // Overflow Unordered
201  VC = 0x7, // No overflow Not unordered
202  HI = 0x8, // Unsigned higher Greater than, or unordered
203  LS = 0x9, // Unsigned lower or same Less than or equal
204  GE = 0xa, // Greater than or equal Greater than or equal
205  LT = 0xb, // Less than Less than, or unordered
206  GT = 0xc, // Greater than Greater than
207  LE = 0xd, // Less than or equal <, ==, or unordered
208  AL = 0xe, // Always (unconditional) Always (unconditional)
209  NV = 0xf, // Always (unconditional) Always (unconditional)
210  // Note the NV exists purely to disassemble 0b1111. Execution is "always".
212 };
213 
214 inline static const char *getCondCodeName(CondCode Code) {
215  switch (Code) {
216  default: llvm_unreachable("Unknown condition code");
217  case EQ: return "eq";
218  case NE: return "ne";
219  case HS: return "hs";
220  case LO: return "lo";
221  case MI: return "mi";
222  case PL: return "pl";
223  case VS: return "vs";
224  case VC: return "vc";
225  case HI: return "hi";
226  case LS: return "ls";
227  case GE: return "ge";
228  case LT: return "lt";
229  case GT: return "gt";
230  case LE: return "le";
231  case AL: return "al";
232  case NV: return "nv";
233  }
234 }
235 
236 inline static CondCode getInvertedCondCode(CondCode Code) {
237  // To reverse a condition it's necessary to only invert the low bit:
238 
239  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
240 }
241 
242 /// Given a condition code, return NZCV flags that would satisfy that condition.
243 /// The flag bits are in the format expected by the ccmp instructions.
244 /// Note that many different flag settings can satisfy a given condition code,
245 /// this function just returns one of them.
246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
247  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
248  enum { N = 8, Z = 4, C = 2, V = 1 };
249  switch (Code) {
250  default: llvm_unreachable("Unknown condition code");
251  case EQ: return Z; // Z == 1
252  case NE: return 0; // Z == 0
253  case HS: return C; // C == 1
254  case LO: return 0; // C == 0
255  case MI: return N; // N == 1
256  case PL: return 0; // N == 0
257  case VS: return V; // V == 1
258  case VC: return 0; // V == 0
259  case HI: return C; // C == 1 && Z == 0
260  case LS: return 0; // C == 0 || Z == 1
261  case GE: return 0; // N == V
262  case LT: return N; // N != V
263  case GT: return 0; // Z == 0 && N == V
264  case LE: return Z; // Z == 1 || N != V
265  }
266 }
267 } // end namespace AArch64CC
268 
269 struct SysAlias {
270  const char *Name;
271  uint16_t Encoding;
273 
274  SysAlias (const char *N, uint16_t E) : Name(N), Encoding(E) {};
275  SysAlias (const char *N, uint16_t E, FeatureBitset F) :
276  Name(N), Encoding(E), FeaturesRequired(F) {};
277 
278  bool haveFeatures(FeatureBitset ActiveFeatures) const {
279  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
280  }
281 
282  FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
283 };
284 
286  bool NeedsReg;
287  SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
288 };
289 
290 namespace AArch64AT{
291  struct AT : SysAlias {
292  using SysAlias::SysAlias;
293  };
294  #define GET_AT_DECL
295  #include "AArch64GenSystemOperands.inc"
296 }
297 
298 namespace AArch64DB {
299  struct DB : SysAlias {
300  using SysAlias::SysAlias;
301  };
302  #define GET_DB_DECL
303  #include "AArch64GenSystemOperands.inc"
304 }
305 
306 namespace AArch64DC {
307  struct DC : SysAlias {
308  using SysAlias::SysAlias;
309  };
310  #define GET_DC_DECL
311  #include "AArch64GenSystemOperands.inc"
312 }
313 
314 namespace AArch64IC {
315  struct IC : SysAliasReg {
317  };
318  #define GET_IC_DECL
319  #include "AArch64GenSystemOperands.inc"
320 }
321 
322 namespace AArch64ISB {
323  struct ISB : SysAlias {
324  using SysAlias::SysAlias;
325  };
326  #define GET_ISB_DECL
327  #include "AArch64GenSystemOperands.inc"
328 }
329 
330 namespace AArch64PRFM {
331  struct PRFM : SysAlias {
332  using SysAlias::SysAlias;
333  };
334  #define GET_PRFM_DECL
335  #include "AArch64GenSystemOperands.inc"
336 }
337 
338 namespace AArch64PState {
339  struct PState : SysAlias{
340  using SysAlias::SysAlias;
341  };
342  #define GET_PSTATE_DECL
343  #include "AArch64GenSystemOperands.inc"
344 }
345 
346 namespace AArch64PSBHint {
347  struct PSB : SysAlias {
348  using SysAlias::SysAlias;
349  };
350  #define GET_PSB_DECL
351  #include "AArch64GenSystemOperands.inc"
352 }
353 
354 namespace AArch64SE {
356  Invalid = -1,
362 
367 
372  };
373 }
374 
375 namespace AArch64Layout {
377  Invalid = -1,
382 
387 
388  // Bare layout for the 128-bit vector
389  // (only show ".b", ".h", ".s", ".d" without vector number)
394  };
395 }
396 
397 inline static const char *
399  switch (Layout) {
400  case AArch64Layout::VL_8B: return ".8b";
401  case AArch64Layout::VL_4H: return ".4h";
402  case AArch64Layout::VL_2S: return ".2s";
403  case AArch64Layout::VL_1D: return ".1d";
404  case AArch64Layout::VL_16B: return ".16b";
405  case AArch64Layout::VL_8H: return ".8h";
406  case AArch64Layout::VL_4S: return ".4s";
407  case AArch64Layout::VL_2D: return ".2d";
408  case AArch64Layout::VL_B: return ".b";
409  case AArch64Layout::VL_H: return ".h";
410  case AArch64Layout::VL_S: return ".s";
411  case AArch64Layout::VL_D: return ".d";
412  default: llvm_unreachable("Unknown Vector Layout");
413  }
414 }
415 
416 inline static AArch64Layout::VectorLayout
419  .Case(".8b", AArch64Layout::VL_8B)
420  .Case(".4h", AArch64Layout::VL_4H)
421  .Case(".2s", AArch64Layout::VL_2S)
422  .Case(".1d", AArch64Layout::VL_1D)
423  .Case(".16b", AArch64Layout::VL_16B)
424  .Case(".8h", AArch64Layout::VL_8H)
425  .Case(".4s", AArch64Layout::VL_4S)
426  .Case(".2d", AArch64Layout::VL_2D)
427  .Case(".b", AArch64Layout::VL_B)
428  .Case(".h", AArch64Layout::VL_H)
429  .Case(".s", AArch64Layout::VL_S)
430  .Case(".d", AArch64Layout::VL_D)
432 }
433 
434 namespace AArch64SysReg {
435  struct SysReg {
436  const char *Name;
437  unsigned Encoding;
438  bool Readable;
439  bool Writeable;
441 
442  bool haveFeatures(FeatureBitset ActiveFeatures) const {
443  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
444  }
445  };
446 
447  #define GET_SYSREG_DECL
448  #include "AArch64GenSystemOperands.inc"
449 
450  const SysReg *lookupSysRegByName(StringRef);
451  const SysReg *lookupSysRegByEncoding(uint16_t);
452 
454  std::string genericRegisterString(uint32_t Bits);
455 }
456 
457 namespace AArch64TLBI {
458  struct TLBI : SysAliasReg {
460  };
461  #define GET_TLBI_DECL
462  #include "AArch64GenSystemOperands.inc"
463 }
464 
465 namespace AArch64II {
466  /// Target Operand Flag enum.
467  enum TOF {
468  //===------------------------------------------------------------------===//
469  // AArch64 Specific MachineOperand flags.
470 
472 
473  MO_FRAGMENT = 0xf,
474 
475  /// MO_PAGE - A symbol operand with this flag represents the pc-relative
476  /// offset of the 4K page containing the symbol. This is used with the
477  /// ADRP instruction.
478  MO_PAGE = 1,
479 
480  /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
481  /// that symbol within a 4K page. This offset is added to the page address
482  /// to produce the complete address.
484 
485  /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
486  /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
487  MO_G3 = 3,
488 
489  /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
490  /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
491  MO_G2 = 4,
492 
493  /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
494  /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
495  MO_G1 = 5,
496 
497  /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
498  /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
499  MO_G0 = 6,
500 
501  /// MO_HI12 - This flag indicates that a symbol operand represents the bits
502  /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
503  /// by-12-bits instruction.
504  MO_HI12 = 7,
505 
506  /// MO_GOT - This flag indicates that a symbol operand represents the
507  /// address of the GOT entry for the symbol, rather than the address of
508  /// the symbol itself.
509  MO_GOT = 0x10,
510 
511  /// MO_NC - Indicates whether the linker is expected to check the symbol
512  /// reference for overflow. For example in an ADRP/ADD pair of relocations
513  /// the ADRP usually does check, but not the ADD.
514  MO_NC = 0x20,
515 
516  /// MO_TLS - Indicates that the operand being accessed is some kind of
517  /// thread-local symbol. On Darwin, only one type of thread-local access
518  /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
519  /// referee will affect interpretation.
520  MO_TLS = 0x40
521  };
522 } // end namespace AArch64II
523 
524 } // end namespace llvm
525 
526 #endif
uint64_t CallInst * C
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address...
static unsigned getBRegFromDReg(unsigned Reg)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
SysAlias(const char *N, uint16_t E)
static CondCode getInvertedCondCode(CondCode Code)
TOF
Target Operand Flag enum.
static unsigned getXRegFromWReg(unsigned Reg)
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address...
bool haveFeatures(FeatureBitset ActiveFeatures) const
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address...
Reg
All possible values of the reg field in the ModR/M byte.
static const char * getCondCodeName(CondCode Code)
zlib-gnu style compression
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
#define F(x, y, z)
Definition: MD5.cpp:55
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
FeatureBitset getRequiredFeatures() const
const char * Name
static unsigned getWRegFromXReg(unsigned Reg)
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address...
Container class for subtarget features.
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address...
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
const char * Name
#define E
Definition: LargeTest.cpp:27
const size_t N
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
std::string genericRegisterString(uint32_t Bits)
const SysReg * lookupSysRegByName(StringRef)
uint32_t parseGenericRegister(StringRef Name)
bool haveFeatures(FeatureBitset ActiveFeatures) const
static unsigned getDRegFromBReg(unsigned Reg)
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page...
SysAlias(const char *N, uint16_t E, FeatureBitset F)
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
FeatureBitset FeaturesRequired
const SysReg * lookupSysRegByEncoding(uint16_t)
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow...
SysAliasReg(const char *N, uint16_t E, bool R)