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StackMaps.cpp
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1 //===- StackMaps.cpp ------------------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/CodeGen/StackMaps.h"
11 #include "llvm/ADT/DenseMapInfo.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/Twine.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/Support/Debug.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <cstdint>
36 #include <iterator>
37 #include <utility>
38 
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "stackmaps"
42 
44  "stackmap-version", cl::init(3), cl::Hidden,
45  cl::desc("Specify the stackmap encoding version (default = 3)"));
46 
47 const char *StackMaps::WSMP = "Stack Maps: ";
48 
50  : MI(MI) {
51  assert(getVarIdx() <= MI->getNumOperands() &&
52  "invalid stackmap definition");
53 }
54 
56  : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
57  !MI->getOperand(0).isImplicit()) {
58 #ifndef NDEBUG
59  unsigned CheckStartIdx = 0, e = MI->getNumOperands();
60  while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
61  MI->getOperand(CheckStartIdx).isDef() &&
62  !MI->getOperand(CheckStartIdx).isImplicit())
63  ++CheckStartIdx;
64 
65  assert(getMetaIdx() == CheckStartIdx &&
66  "Unexpected additional definition in Patchpoint intrinsic.");
67 #endif
68 }
69 
70 unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
71  if (!StartIdx)
72  StartIdx = getVarIdx();
73 
74  // Find the next scratch register (implicit def and early clobber)
75  unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
76  while (ScratchIdx < e &&
77  !(MI->getOperand(ScratchIdx).isReg() &&
78  MI->getOperand(ScratchIdx).isDef() &&
79  MI->getOperand(ScratchIdx).isImplicit() &&
80  MI->getOperand(ScratchIdx).isEarlyClobber()))
81  ++ScratchIdx;
82 
83  assert(ScratchIdx != e && "No scratch register available");
84  return ScratchIdx;
85 }
86 
88  if (StackMapVersion != 3)
89  llvm_unreachable("Unsupported stackmap version!");
90 }
91 
92 /// Go up the super-register chain until we hit a valid dwarf register number.
93 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
94  int RegNum = TRI->getDwarfRegNum(Reg, false);
95  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
96  RegNum = TRI->getDwarfRegNum(*SR, false);
97 
98  assert(RegNum >= 0 && "Invalid Dwarf register number.");
99  return (unsigned)RegNum;
100 }
101 
103 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
104  MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
105  LiveOutVec &LiveOuts) const {
107  if (MOI->isImm()) {
108  switch (MOI->getImm()) {
109  default:
110  llvm_unreachable("Unrecognized operand type.");
111  case StackMaps::DirectMemRefOp: {
112  auto &DL = AP.MF->getDataLayout();
113 
114  unsigned Size = DL.getPointerSizeInBits();
115  assert((Size % 8) == 0 && "Need pointer size in bytes.");
116  Size /= 8;
117  unsigned Reg = (++MOI)->getReg();
118  int64_t Imm = (++MOI)->getImm();
119  Locs.emplace_back(StackMaps::Location::Direct, Size,
120  getDwarfRegNum(Reg, TRI), Imm);
121  break;
122  }
123  case StackMaps::IndirectMemRefOp: {
124  int64_t Size = (++MOI)->getImm();
125  assert(Size > 0 && "Need a valid size for indirect memory locations.");
126  unsigned Reg = (++MOI)->getReg();
127  int64_t Imm = (++MOI)->getImm();
128  Locs.emplace_back(StackMaps::Location::Indirect, Size,
129  getDwarfRegNum(Reg, TRI), Imm);
130  break;
131  }
132  case StackMaps::ConstantOp: {
133  ++MOI;
134  assert(MOI->isImm() && "Expected constant operand.");
135  int64_t Imm = MOI->getImm();
136  Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm);
137  break;
138  }
139  }
140  return ++MOI;
141  }
142 
143  // The physical register number will ultimately be encoded as a DWARF regno.
144  // The stack map also records the size of a spill slot that can hold the
145  // register content. (The runtime can track the actual size of the data type
146  // if it needs to.)
147  if (MOI->isReg()) {
148  // Skip implicit registers (this includes our scratch registers)
149  if (MOI->isImplicit())
150  return ++MOI;
151 
153  "Virtreg operands should have been rewritten before now.");
154  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
155  assert(!MOI->getSubReg() && "Physical subreg still around.");
156 
157  unsigned Offset = 0;
158  unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI);
159  unsigned LLVMRegNum = TRI->getLLVMRegNum(DwarfRegNum, false);
160  unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());
161  if (SubRegIdx)
162  Offset = TRI->getSubRegIdxOffset(SubRegIdx);
163 
164  Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC),
165  DwarfRegNum, Offset);
166  return ++MOI;
167  }
168 
169  if (MOI->isRegLiveOut())
170  LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
171 
172  return ++MOI;
173 }
174 
175 void StackMaps::print(raw_ostream &OS) {
176  const TargetRegisterInfo *TRI =
177  AP.MF ? AP.MF->getSubtarget().getRegisterInfo() : nullptr;
178  OS << WSMP << "callsites:\n";
179  for (const auto &CSI : CSInfos) {
180  const LocationVec &CSLocs = CSI.Locations;
181  const LiveOutVec &LiveOuts = CSI.LiveOuts;
182 
183  OS << WSMP << "callsite " << CSI.ID << "\n";
184  OS << WSMP << " has " << CSLocs.size() << " locations\n";
185 
186  unsigned Idx = 0;
187  for (const auto &Loc : CSLocs) {
188  OS << WSMP << "\t\tLoc " << Idx << ": ";
189  switch (Loc.Type) {
191  OS << "<Unprocessed operand>";
192  break;
193  case Location::Register:
194  OS << "Register ";
195  if (TRI)
196  OS << printReg(Loc.Reg, TRI);
197  else
198  OS << Loc.Reg;
199  break;
200  case Location::Direct:
201  OS << "Direct ";
202  if (TRI)
203  OS << printReg(Loc.Reg, TRI);
204  else
205  OS << Loc.Reg;
206  if (Loc.Offset)
207  OS << " + " << Loc.Offset;
208  break;
209  case Location::Indirect:
210  OS << "Indirect ";
211  if (TRI)
212  OS << printReg(Loc.Reg, TRI);
213  else
214  OS << Loc.Reg;
215  OS << "+" << Loc.Offset;
216  break;
217  case Location::Constant:
218  OS << "Constant " << Loc.Offset;
219  break;
221  OS << "Constant Index " << Loc.Offset;
222  break;
223  }
224  OS << "\t[encoding: .byte " << Loc.Type << ", .byte 0"
225  << ", .short " << Loc.Size << ", .short " << Loc.Reg << ", .short 0"
226  << ", .int " << Loc.Offset << "]\n";
227  Idx++;
228  }
229 
230  OS << WSMP << "\thas " << LiveOuts.size() << " live-out registers\n";
231 
232  Idx = 0;
233  for (const auto &LO : LiveOuts) {
234  OS << WSMP << "\t\tLO " << Idx << ": ";
235  if (TRI)
236  OS << printReg(LO.Reg, TRI);
237  else
238  OS << LO.Reg;
239  OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "
240  << LO.Size << "]\n";
241  Idx++;
242  }
243  }
244 }
245 
246 /// Create a live-out register record for the given register Reg.
248 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
249  unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI);
250  unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg));
251  return LiveOutReg(Reg, DwarfRegNum, Size);
252 }
253 
254 /// Parse the register live-out mask and return a vector of live-out registers
255 /// that need to be recorded in the stackmap.
257 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
258  assert(Mask && "No register mask specified");
259  const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
260  LiveOutVec LiveOuts;
261 
262  // Create a LiveOutReg for each bit that is set in the register mask.
263  for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
264  if ((Mask[Reg / 32] >> Reg % 32) & 1)
265  LiveOuts.push_back(createLiveOutReg(Reg, TRI));
266 
267  // We don't need to keep track of a register if its super-register is already
268  // in the list. Merge entries that refer to the same dwarf register and use
269  // the maximum size that needs to be spilled.
270 
271  llvm::sort(LiveOuts, [](const LiveOutReg &LHS, const LiveOutReg &RHS) {
272  // Only sort by the dwarf register number.
273  return LHS.DwarfRegNum < RHS.DwarfRegNum;
274  });
275 
276  for (auto I = LiveOuts.begin(), E = LiveOuts.end(); I != E; ++I) {
277  for (auto II = std::next(I); II != E; ++II) {
278  if (I->DwarfRegNum != II->DwarfRegNum) {
279  // Skip all the now invalid entries.
280  I = --II;
281  break;
282  }
283  I->Size = std::max(I->Size, II->Size);
284  if (TRI->isSuperRegister(I->Reg, II->Reg))
285  I->Reg = II->Reg;
286  II->Reg = 0; // mark for deletion.
287  }
288  }
289 
290  LiveOuts.erase(
291  llvm::remove_if(LiveOuts,
292  [](const LiveOutReg &LO) { return LO.Reg == 0; }),
293  LiveOuts.end());
294 
295  return LiveOuts;
296 }
297 
298 void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
301  bool recordResult) {
302  MCContext &OutContext = AP.OutStreamer->getContext();
303  MCSymbol *MILabel = OutContext.createTempSymbol();
304  AP.OutStreamer->EmitLabel(MILabel);
305 
306  LocationVec Locations;
307  LiveOutVec LiveOuts;
308 
309  if (recordResult) {
310  assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
311  parseOperand(MI.operands_begin(), std::next(MI.operands_begin()), Locations,
312  LiveOuts);
313  }
314 
315  // Parse operands.
316  while (MOI != MOE) {
317  MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
318  }
319 
320  // Move large constants into the constant pool.
321  for (auto &Loc : Locations) {
322  // Constants are encoded as sign-extended integers.
323  // -1 is directly encoded as .long 0xFFFFFFFF with no constant pool.
324  if (Loc.Type == Location::Constant && !isInt<32>(Loc.Offset)) {
325  Loc.Type = Location::ConstantIndex;
326  // ConstPool is intentionally a MapVector of 'uint64_t's (as
327  // opposed to 'int64_t's). We should never be in a situation
328  // where we have to insert either the tombstone or the empty
329  // keys into a map, and for a DenseMap<uint64_t, T> these are
330  // (uint64_t)0 and (uint64_t)-1. They can be and are
331  // represented using 32 bit integers.
332  assert((uint64_t)Loc.Offset != DenseMapInfo<uint64_t>::getEmptyKey() &&
333  (uint64_t)Loc.Offset !=
335  "empty and tombstone keys should fit in 32 bits!");
336  auto Result = ConstPool.insert(std::make_pair(Loc.Offset, Loc.Offset));
337  Loc.Offset = Result.first - ConstPool.begin();
338  }
339  }
340 
341  // Create an expression to calculate the offset of the callsite from function
342  // entry.
343  const MCExpr *CSOffsetExpr = MCBinaryExpr::createSub(
344  MCSymbolRefExpr::create(MILabel, OutContext),
345  MCSymbolRefExpr::create(AP.CurrentFnSymForSize, OutContext), OutContext);
346 
347  CSInfos.emplace_back(CSOffsetExpr, ID, std::move(Locations),
348  std::move(LiveOuts));
349 
350  // Record the stack size of the current function and update callsite count.
351  const MachineFrameInfo &MFI = AP.MF->getFrameInfo();
352  const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
353  bool HasDynamicFrameSize =
354  MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(*(AP.MF));
355  uint64_t FrameSize = HasDynamicFrameSize ? UINT64_MAX : MFI.getStackSize();
356 
357  auto CurrentIt = FnInfos.find(AP.CurrentFnSym);
358  if (CurrentIt != FnInfos.end())
359  CurrentIt->second.RecordCount++;
360  else
361  FnInfos.insert(std::make_pair(AP.CurrentFnSym, FunctionInfo(FrameSize)));
362 }
363 
365  assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
366 
367  StackMapOpers opers(&MI);
368  const int64_t ID = MI.getOperand(PatchPointOpers::IDPos).getImm();
369  recordStackMapOpers(MI, ID, std::next(MI.operands_begin(), opers.getVarIdx()),
370  MI.operands_end());
371 }
372 
374  assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
375 
376  PatchPointOpers opers(&MI);
377  const int64_t ID = opers.getID();
378  auto MOI = std::next(MI.operands_begin(), opers.getStackMapStartIdx());
379  recordStackMapOpers(MI, ID, MOI, MI.operands_end(),
380  opers.isAnyReg() && opers.hasDef());
381 
382 #ifndef NDEBUG
383  // verify anyregcc
384  auto &Locations = CSInfos.back().Locations;
385  if (opers.isAnyReg()) {
386  unsigned NArgs = opers.getNumCallArgs();
387  for (unsigned i = 0, e = (opers.hasDef() ? NArgs + 1 : NArgs); i != e; ++i)
388  assert(Locations[i].Type == Location::Register &&
389  "anyreg arg must be in reg.");
390  }
391 #endif
392 }
393 
395  assert(MI.getOpcode() == TargetOpcode::STATEPOINT && "expected statepoint");
396 
397  StatepointOpers opers(&MI);
398  // Record all the deopt and gc operands (they're contiguous and run from the
399  // initial index to the end of the operand list)
400  const unsigned StartIdx = opers.getVarIdx();
401  recordStackMapOpers(MI, opers.getID(), MI.operands_begin() + StartIdx,
402  MI.operands_end(), false);
403 }
404 
405 /// Emit the stackmap header.
406 ///
407 /// Header {
408 /// uint8 : Stack Map Version (currently 2)
409 /// uint8 : Reserved (expected to be 0)
410 /// uint16 : Reserved (expected to be 0)
411 /// }
412 /// uint32 : NumFunctions
413 /// uint32 : NumConstants
414 /// uint32 : NumRecords
415 void StackMaps::emitStackmapHeader(MCStreamer &OS) {
416  // Header.
417  OS.EmitIntValue(StackMapVersion, 1); // Version.
418  OS.EmitIntValue(0, 1); // Reserved.
419  OS.EmitIntValue(0, 2); // Reserved.
420 
421  // Num functions.
422  LLVM_DEBUG(dbgs() << WSMP << "#functions = " << FnInfos.size() << '\n');
423  OS.EmitIntValue(FnInfos.size(), 4);
424  // Num constants.
425  LLVM_DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.size() << '\n');
426  OS.EmitIntValue(ConstPool.size(), 4);
427  // Num callsites.
428  LLVM_DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n');
429  OS.EmitIntValue(CSInfos.size(), 4);
430 }
431 
432 /// Emit the function frame record for each function.
433 ///
434 /// StkSizeRecord[NumFunctions] {
435 /// uint64 : Function Address
436 /// uint64 : Stack Size
437 /// uint64 : Record Count
438 /// }
439 void StackMaps::emitFunctionFrameRecords(MCStreamer &OS) {
440  // Function Frame records.
441  LLVM_DEBUG(dbgs() << WSMP << "functions:\n");
442  for (auto const &FR : FnInfos) {
443  LLVM_DEBUG(dbgs() << WSMP << "function addr: " << FR.first
444  << " frame size: " << FR.second.StackSize
445  << " callsite count: " << FR.second.RecordCount << '\n');
446  OS.EmitSymbolValue(FR.first, 8);
447  OS.EmitIntValue(FR.second.StackSize, 8);
448  OS.EmitIntValue(FR.second.RecordCount, 8);
449  }
450 }
451 
452 /// Emit the constant pool.
453 ///
454 /// int64 : Constants[NumConstants]
455 void StackMaps::emitConstantPoolEntries(MCStreamer &OS) {
456  // Constant pool entries.
457  LLVM_DEBUG(dbgs() << WSMP << "constants:\n");
458  for (const auto &ConstEntry : ConstPool) {
459  LLVM_DEBUG(dbgs() << WSMP << ConstEntry.second << '\n');
460  OS.EmitIntValue(ConstEntry.second, 8);
461  }
462 }
463 
464 /// Emit the callsite info for each callsite.
465 ///
466 /// StkMapRecord[NumRecords] {
467 /// uint64 : PatchPoint ID
468 /// uint32 : Instruction Offset
469 /// uint16 : Reserved (record flags)
470 /// uint16 : NumLocations
471 /// Location[NumLocations] {
472 /// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
473 /// uint8 : Size in Bytes
474 /// uint16 : Dwarf RegNum
475 /// int32 : Offset
476 /// }
477 /// uint16 : Padding
478 /// uint16 : NumLiveOuts
479 /// LiveOuts[NumLiveOuts] {
480 /// uint16 : Dwarf RegNum
481 /// uint8 : Reserved
482 /// uint8 : Size in Bytes
483 /// }
484 /// uint32 : Padding (only if required to align to 8 byte)
485 /// }
486 ///
487 /// Location Encoding, Type, Value:
488 /// 0x1, Register, Reg (value in register)
489 /// 0x2, Direct, Reg + Offset (frame index)
490 /// 0x3, Indirect, [Reg + Offset] (spilled value)
491 /// 0x4, Constant, Offset (small constant)
492 /// 0x5, ConstIndex, Constants[Offset] (large constant)
493 void StackMaps::emitCallsiteEntries(MCStreamer &OS) {
494  LLVM_DEBUG(print(dbgs()));
495  // Callsite entries.
496  for (const auto &CSI : CSInfos) {
497  const LocationVec &CSLocs = CSI.Locations;
498  const LiveOutVec &LiveOuts = CSI.LiveOuts;
499 
500  // Verify stack map entry. It's better to communicate a problem to the
501  // runtime than crash in case of in-process compilation. Currently, we do
502  // simple overflow checks, but we may eventually communicate other
503  // compilation errors this way.
504  if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
505  OS.EmitIntValue(UINT64_MAX, 8); // Invalid ID.
506  OS.EmitValue(CSI.CSOffsetExpr, 4);
507  OS.EmitIntValue(0, 2); // Reserved.
508  OS.EmitIntValue(0, 2); // 0 locations.
509  OS.EmitIntValue(0, 2); // padding.
510  OS.EmitIntValue(0, 2); // 0 live-out registers.
511  OS.EmitIntValue(0, 4); // padding.
512  continue;
513  }
514 
515  OS.EmitIntValue(CSI.ID, 8);
516  OS.EmitValue(CSI.CSOffsetExpr, 4);
517 
518  // Reserved for flags.
519  OS.EmitIntValue(0, 2);
520  OS.EmitIntValue(CSLocs.size(), 2);
521 
522  for (const auto &Loc : CSLocs) {
523  OS.EmitIntValue(Loc.Type, 1);
524  OS.EmitIntValue(0, 1); // Reserved
525  OS.EmitIntValue(Loc.Size, 2);
526  OS.EmitIntValue(Loc.Reg, 2);
527  OS.EmitIntValue(0, 2); // Reserved
528  OS.EmitIntValue(Loc.Offset, 4);
529  }
530 
531  // Emit alignment to 8 byte.
532  OS.EmitValueToAlignment(8);
533 
534  // Num live-out registers and padding to align to 4 byte.
535  OS.EmitIntValue(0, 2);
536  OS.EmitIntValue(LiveOuts.size(), 2);
537 
538  for (const auto &LO : LiveOuts) {
539  OS.EmitIntValue(LO.DwarfRegNum, 2);
540  OS.EmitIntValue(0, 1);
541  OS.EmitIntValue(LO.Size, 1);
542  }
543  // Emit alignment to 8 byte.
544  OS.EmitValueToAlignment(8);
545  }
546 }
547 
548 /// Serialize the stackmap data.
550  (void)WSMP;
551  // Bail out if there's no stack map data.
552  assert((!CSInfos.empty() || ConstPool.empty()) &&
553  "Expected empty constant pool too!");
554  assert((!CSInfos.empty() || FnInfos.empty()) &&
555  "Expected empty function record too!");
556  if (CSInfos.empty())
557  return;
558 
559  MCContext &OutContext = AP.OutStreamer->getContext();
560  MCStreamer &OS = *AP.OutStreamer;
561 
562  // Create the section.
563  MCSection *StackMapSection =
564  OutContext.getObjectFileInfo()->getStackMapSection();
565  OS.SwitchSection(StackMapSection);
566 
567  // Emit a dummy symbol to force section inclusion.
568  OS.EmitLabel(OutContext.getOrCreateSymbol(Twine("__LLVM_StackMaps")));
569 
570  // Serialize data.
571  LLVM_DEBUG(dbgs() << "********** Stack Map Output **********\n");
572  emitStackmapHeader(OS);
573  emitFunctionFrameRecords(OS);
574  emitConstantPoolEntries(OS);
575  emitCallsiteEntries(OS);
576  OS.AddBlankLine();
577 
578  // Clean up.
579  CSInfos.clear();
580  ConstPool.clear();
581 }
static bool isReg(const MCInst &MI, unsigned OpNo)
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:39
void push_back(const T &Elt)
Definition: SmallVector.h:218
mop_iterator operands_end()
Definition: MachineInstr.h:454
void clear()
Definition: MapVector.h:89
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:70
size_type size() const
Definition: MapVector.h:61
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void EmitSymbolValue(const MCSymbol *Sym, unsigned Size, bool IsSectionRelative=false)
Special case of EmitValue that avoids the client having to pass in a MCExpr for MCSymbols.
Definition: MCStreamer.cpp:147
MCSection * getStackMapSection() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
virtual void AddBlankLine()
AddBlankLine - Emit a blank line to a .s file to pretty it up.
Definition: MCStreamer.h:327
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getSubReg() const
unsigned const TargetRegisterInfo * TRI
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
bool isEarlyClobber() const
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool empty() const
Definition: MapVector.h:80
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Context object for machine code objects.
Definition: MCContext.h:63
#define UINT64_MAX
Definition: DataTypes.h:83
PatchPointOpers(const MachineInstr *MI)
Definition: StackMaps.cpp:55
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
iterator find(const KeyT &Key)
Definition: MapVector.h:148
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:112
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:143
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:394
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
Streaming machine code generation interface.
Definition: MCStreamer.h:183
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:112
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:999
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:987
static cl::opt< int > StackMapVersion("stackmap-version", cl::init(3), cl::Hidden, cl::desc("Specify the stackmap encoding version (default = 3)"))
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:297
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
Definition: StackMaps.h:128
MI-level patchpoint operands.
Definition: StackMaps.h:77
auto remove_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::remove_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1082
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:373
void serializeToStackMapSection()
If there is any stack map data, create a stack map section and serialize the map info into it...
Definition: StackMaps.cpp:549
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:972
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: MapVector.h:118
StackMapOpers(const MachineInstr *MI)
Definition: StackMaps.cpp:49
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:309
MachineOperand class - Representation of each machine instruction operand.
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
Definition: StackMaps.h:57
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:364
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
MI-level stackmap operands.
Definition: StackMaps.h:36
StackMaps(AsmPrinter &AP)
Definition: StackMaps.cpp:87
#define I(x, y, z)
Definition: MD5.cpp:58
MI-level Statepoint operands.
Definition: StackMaps.h:155
uint32_t Size
Definition: Profile.cpp:47
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator begin()
Definition: MapVector.h:70
iterator end()
Definition: MapVector.h:72
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
mop_iterator operands_begin()
Definition: MachineInstr.h:453
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:328
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
MCSymbol * CurrentFnSymForSize
The symbol used to represent the start of the current function for the purpose of calculating its siz...
Definition: AsmPrinter.h:117
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:93
IRTranslator LLVM IR MI
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
bool isImplicit() const