LLVM  6.0.0svn
MIRPrinter.cpp
Go to the documentation of this file.
1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Twine.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalValue.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Value.h"
53 #include "llvm/MC/LaneBitmask.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
58 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/Format.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR("simplify-mir",
79  cl::desc("Leave out unnecessary information when printing MIR"));
80 
81 namespace {
82 
83 /// This structure describes how to print out stack object references.
84 struct FrameIndexOperand {
85  std::string Name;
86  unsigned ID;
87  bool IsFixed;
88 
89  FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
90  : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
91 
92  /// Return an ordinary stack object reference.
93  static FrameIndexOperand create(StringRef Name, unsigned ID) {
94  return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
95  }
96 
97  /// Return a fixed stack object reference.
98  static FrameIndexOperand createFixed(unsigned ID) {
99  return FrameIndexOperand("", ID, /*IsFixed=*/true);
100  }
101 };
102 
103 } // end anonymous namespace
104 
105 namespace llvm {
106 
107 /// This class prints out the machine functions using the MIR serialization
108 /// format.
109 class MIRPrinter {
110  raw_ostream &OS;
111  DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
112  /// Maps from stack object indices to operand indices which will be used when
113  /// printing frame index machine operands.
114  DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
115 
116 public:
117  MIRPrinter(raw_ostream &OS) : OS(OS) {}
118 
119  void print(const MachineFunction &MF);
120 
121  void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
122  const TargetRegisterInfo *TRI);
123  void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
124  const MachineFrameInfo &MFI);
125  void convert(yaml::MachineFunction &MF,
127  void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
128  const MachineJumpTableInfo &JTI);
129  void convertStackObjects(yaml::MachineFunction &YMF,
130  const MachineFunction &MF, ModuleSlotTracker &MST);
131 
132 private:
133  void initRegisterMaskIds(const MachineFunction &MF);
134 };
135 
136 /// This class prints out the machine instructions using the MIR serialization
137 /// format.
138 class MIPrinter {
139  raw_ostream &OS;
140  ModuleSlotTracker &MST;
141  const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
142  const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143  /// Synchronization scope names registered with LLVMContext.
145 
146  bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
147  bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
148 
149 public:
151  const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
152  const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
153  : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
154  StackObjectOperandMapping(StackObjectOperandMapping) {}
155 
156  void print(const MachineBasicBlock &MBB);
157 
158  void print(const MachineInstr &MI);
159  void printMBBReference(const MachineBasicBlock &MBB);
160  void printIRBlockReference(const BasicBlock &BB);
161  void printIRValueReference(const Value &V);
162  void printStackObjectReference(int FrameIndex);
163  void printOffset(int64_t Offset);
164  void printTargetFlags(const MachineOperand &Op);
165  void print(const MachineInstr &MI, unsigned OpIdx,
166  const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
167  LLT TypeToPrint, bool IsDef = false);
168  void print(const LLVMContext &Context, const TargetInstrInfo &TII,
169  const MachineMemOperand &Op);
170  void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID);
171 
172  void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
173 };
174 
175 } // end namespace llvm
176 
177 namespace llvm {
178 namespace yaml {
179 
180 /// This struct serializes the LLVM IR module.
181 template <> struct BlockScalarTraits<Module> {
182  static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
183  Mod.print(OS, nullptr);
184  }
185 
186  static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
187  llvm_unreachable("LLVM Module is supposed to be parsed separately");
188  return "";
189  }
190 };
191 
192 } // end namespace yaml
193 } // end namespace llvm
194 
195 static void printReg(unsigned Reg, raw_ostream &OS,
196  const TargetRegisterInfo *TRI) {
197  // TODO: Print Stack Slots.
198  if (!Reg)
199  OS << '_';
201  OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
202  else if (Reg < TRI->getNumRegs())
203  OS << '%' << StringRef(TRI->getName(Reg)).lower();
204  else
205  llvm_unreachable("Can't print this kind of register yet");
206 }
207 
208 static void printReg(unsigned Reg, yaml::StringValue &Dest,
209  const TargetRegisterInfo *TRI) {
210  raw_string_ostream OS(Dest.Value);
211  printReg(Reg, OS, TRI);
212 }
213 
215  initRegisterMaskIds(MF);
216 
217  yaml::MachineFunction YamlMF;
218  YamlMF.Name = MF.getName();
219  YamlMF.Alignment = MF.getAlignment();
221 
222  YamlMF.Legalized = MF.getProperties().hasProperty(
226  YamlMF.Selected = MF.getProperties().hasProperty(
228 
229  convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
231  MST.incorporateFunction(*MF.getFunction());
232  convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
233  convertStackObjects(YamlMF, MF, MST);
234  if (const auto *ConstantPool = MF.getConstantPool())
235  convert(YamlMF, *ConstantPool);
236  if (const auto *JumpTableInfo = MF.getJumpTableInfo())
237  convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
238  raw_string_ostream StrOS(YamlMF.Body.Value.Value);
239  bool IsNewlineNeeded = false;
240  for (const auto &MBB : MF) {
241  if (IsNewlineNeeded)
242  StrOS << "\n";
243  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
244  .print(MBB);
245  IsNewlineNeeded = true;
246  }
247  StrOS.flush();
248  yaml::Output Out(OS);
249  if (!SimplifyMIR)
250  Out.setWriteDefaultValues(true);
251  Out << YamlMF;
252 }
253 
254 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
255  const TargetRegisterInfo *TRI) {
256  assert(RegMask && "Can't print an empty register mask");
257  OS << StringRef("CustomRegMask(");
258 
259  bool IsRegInRegMaskFound = false;
260  for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
261  // Check whether the register is asserted in regmask.
262  if (RegMask[I / 32] & (1u << (I % 32))) {
263  if (IsRegInRegMaskFound)
264  OS << ',';
265  printReg(I, OS, TRI);
266  IsRegInRegMaskFound = true;
267  }
268  }
269 
270  OS << ')';
271 }
272 
273 static void printRegClassOrBank(unsigned Reg, raw_ostream &OS,
274  const MachineRegisterInfo &RegInfo,
275  const TargetRegisterInfo *TRI) {
276  if (RegInfo.getRegClassOrNull(Reg))
277  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
278  else if (RegInfo.getRegBankOrNull(Reg))
279  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
280  else {
281  OS << "_";
282  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
283  "Generic registers must have a valid type");
284  }
285 }
286 
287 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
288  const MachineRegisterInfo &RegInfo,
289  const TargetRegisterInfo *TRI) {
290  raw_string_ostream OS(Dest.Value);
291  printRegClassOrBank(Reg, OS, RegInfo, TRI);
292 }
293 
294 
296  const MachineRegisterInfo &RegInfo,
297  const TargetRegisterInfo *TRI) {
298  MF.TracksRegLiveness = RegInfo.tracksLiveness();
299 
300  // Print the virtual register definitions.
301  for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
304  VReg.ID = I;
305  printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
306  unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
307  if (PreferredReg)
308  printReg(PreferredReg, VReg.PreferredRegister, TRI);
309  MF.VirtualRegisters.push_back(VReg);
310  }
311 
312  // Print the live ins.
313  for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
315  printReg(LI.first, LiveIn.Register, TRI);
316  if (LI.second)
317  printReg(LI.second, LiveIn.VirtualRegister, TRI);
318  MF.LiveIns.push_back(LiveIn);
319  }
320 
321  // Prints the callee saved registers.
322  if (RegInfo.isUpdatedCSRsInitialized()) {
323  const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
324  std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
325  for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
327  printReg(*I, Reg, TRI);
328  CalleeSavedRegisters.push_back(Reg);
329  }
330  MF.CalleeSavedRegisters = CalleeSavedRegisters;
331  }
332 }
333 
335  yaml::MachineFrameInfo &YamlMFI,
336  const MachineFrameInfo &MFI) {
339  YamlMFI.HasStackMap = MFI.hasStackMap();
340  YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
341  YamlMFI.StackSize = MFI.getStackSize();
342  YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
343  YamlMFI.MaxAlignment = MFI.getMaxAlignment();
344  YamlMFI.AdjustsStack = MFI.adjustsStack();
345  YamlMFI.HasCalls = MFI.hasCalls();
347  ? MFI.getMaxCallFrameSize() : ~0u;
349  YamlMFI.HasVAStart = MFI.hasVAStart();
351  if (MFI.getSavePoint()) {
352  raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
353  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
355  }
356  if (MFI.getRestorePoint()) {
357  raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
358  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
360  }
361 }
362 
364  const MachineFunction &MF,
365  ModuleSlotTracker &MST) {
366  const MachineFrameInfo &MFI = MF.getFrameInfo();
367  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
368  // Process fixed stack objects.
369  unsigned ID = 0;
370  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
371  if (MFI.isDeadObjectIndex(I))
372  continue;
373 
375  YamlObject.ID = ID;
376  YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
379  YamlObject.Offset = MFI.getObjectOffset(I);
380  YamlObject.Size = MFI.getObjectSize(I);
381  YamlObject.Alignment = MFI.getObjectAlignment(I);
382  YamlObject.StackID = MFI.getStackID(I);
383  YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
384  YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
385  YMF.FixedStackObjects.push_back(YamlObject);
386  StackObjectOperandMapping.insert(
387  std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
388  }
389 
390  // Process ordinary stack objects.
391  ID = 0;
392  for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
393  if (MFI.isDeadObjectIndex(I))
394  continue;
395 
396  yaml::MachineStackObject YamlObject;
397  YamlObject.ID = ID;
398  if (const auto *Alloca = MFI.getObjectAllocation(I))
399  YamlObject.Name.Value =
400  Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
401  YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
406  YamlObject.Offset = MFI.getObjectOffset(I);
407  YamlObject.Size = MFI.getObjectSize(I);
408  YamlObject.Alignment = MFI.getObjectAlignment(I);
409  YamlObject.StackID = MFI.getStackID(I);
410 
411  YMF.StackObjects.push_back(YamlObject);
412  StackObjectOperandMapping.insert(std::make_pair(
413  I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
414  }
415 
416  for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
418  printReg(CSInfo.getReg(), Reg, TRI);
419  auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
420  assert(StackObjectInfo != StackObjectOperandMapping.end() &&
421  "Invalid stack object index");
422  const FrameIndexOperand &StackObject = StackObjectInfo->second;
423  if (StackObject.IsFixed) {
424  YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
425  YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
426  CSInfo.isRestored();
427  } else {
428  YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
429  YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
430  CSInfo.isRestored();
431  }
432  }
433  for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
434  auto LocalObject = MFI.getLocalFrameObjectMap(I);
435  auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
436  assert(StackObjectInfo != StackObjectOperandMapping.end() &&
437  "Invalid stack object index");
438  const FrameIndexOperand &StackObject = StackObjectInfo->second;
439  assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
440  YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
441  }
442 
443  // Print the stack object references in the frame information class after
444  // converting the stack objects.
445  if (MFI.hasStackProtectorIndex()) {
447  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
449  }
450 
451  // Print the debug variable information.
452  for (const MachineFunction::VariableDbgInfo &DebugVar :
453  MF.getVariableDbgInfo()) {
454  auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
455  assert(StackObjectInfo != StackObjectOperandMapping.end() &&
456  "Invalid stack object index");
457  const FrameIndexOperand &StackObject = StackObjectInfo->second;
458  assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
459  auto &Object = YMF.StackObjects[StackObject.ID];
460  {
461  raw_string_ostream StrOS(Object.DebugVar.Value);
462  DebugVar.Var->printAsOperand(StrOS, MST);
463  }
464  {
465  raw_string_ostream StrOS(Object.DebugExpr.Value);
466  DebugVar.Expr->printAsOperand(StrOS, MST);
467  }
468  {
469  raw_string_ostream StrOS(Object.DebugLoc.Value);
470  DebugVar.Loc->printAsOperand(StrOS, MST);
471  }
472  }
473 }
474 
477  unsigned ID = 0;
478  for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
479  std::string Str;
480  raw_string_ostream StrOS(Str);
481  if (Constant.isMachineConstantPoolEntry()) {
482  Constant.Val.MachineCPVal->print(StrOS);
483  } else {
484  Constant.Val.ConstVal->printAsOperand(StrOS);
485  }
486 
487  yaml::MachineConstantPoolValue YamlConstant;
488  YamlConstant.ID = ID++;
489  YamlConstant.Value = StrOS.str();
490  YamlConstant.Alignment = Constant.getAlignment();
491  YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
492 
493  MF.Constants.push_back(YamlConstant);
494  }
495 }
496 
498  yaml::MachineJumpTable &YamlJTI,
499  const MachineJumpTableInfo &JTI) {
500  YamlJTI.Kind = JTI.getEntryKind();
501  unsigned ID = 0;
502  for (const auto &Table : JTI.getJumpTables()) {
503  std::string Str;
505  Entry.ID = ID++;
506  for (const auto *MBB : Table.MBBs) {
507  raw_string_ostream StrOS(Str);
508  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
509  .printMBBReference(*MBB);
510  Entry.Blocks.push_back(StrOS.str());
511  Str.clear();
512  }
513  YamlJTI.Entries.push_back(Entry);
514  }
515 }
516 
517 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
518  const auto *TRI = MF.getSubtarget().getRegisterInfo();
519  unsigned I = 0;
520  for (const uint32_t *Mask : TRI->getRegMasks())
521  RegisterMaskIds.insert(std::make_pair(Mask, I++));
522 }
523 
526  bool &IsFallthrough) {
528 
529  for (const MachineInstr &MI : MBB) {
530  if (MI.isPHI())
531  continue;
532  for (const MachineOperand &MO : MI.operands()) {
533  if (!MO.isMBB())
534  continue;
535  MachineBasicBlock *Succ = MO.getMBB();
536  auto RP = Seen.insert(Succ);
537  if (RP.second)
538  Result.push_back(Succ);
539  }
540  }
541  MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
542  IsFallthrough = I == MBB.end() || !I->isBarrier();
543 }
544 
545 bool
546 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
547  if (MBB.succ_size() <= 1)
548  return true;
549  if (!MBB.hasSuccessorProbabilities())
550  return true;
551 
552  SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
553  MBB.Probs.end());
555  Normalized.end());
556  SmallVector<BranchProbability,8> Equal(Normalized.size());
558 
559  return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
560 }
561 
562 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
564  bool GuessedFallthrough;
565  guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
566  if (GuessedFallthrough) {
567  const MachineFunction &MF = *MBB.getParent();
568  MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
569  if (NextI != MF.end()) {
570  MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
571  if (!is_contained(GuessedSuccs, Next))
572  GuessedSuccs.push_back(Next);
573  }
574  }
575  if (GuessedSuccs.size() != MBB.succ_size())
576  return false;
577  return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
578 }
579 
581  assert(MBB.getNumber() >= 0 && "Invalid MBB number");
582  OS << "bb." << MBB.getNumber();
583  bool HasAttributes = false;
584  if (const auto *BB = MBB.getBasicBlock()) {
585  if (BB->hasName()) {
586  OS << "." << BB->getName();
587  } else {
588  HasAttributes = true;
589  OS << " (";
590  int Slot = MST.getLocalSlot(BB);
591  if (Slot == -1)
592  OS << "<ir-block badref>";
593  else
594  OS << (Twine("%ir-block.") + Twine(Slot)).str();
595  }
596  }
597  if (MBB.hasAddressTaken()) {
598  OS << (HasAttributes ? ", " : " (");
599  OS << "address-taken";
600  HasAttributes = true;
601  }
602  if (MBB.isEHPad()) {
603  OS << (HasAttributes ? ", " : " (");
604  OS << "landing-pad";
605  HasAttributes = true;
606  }
607  if (MBB.getAlignment()) {
608  OS << (HasAttributes ? ", " : " (");
609  OS << "align " << MBB.getAlignment();
610  HasAttributes = true;
611  }
612  if (HasAttributes)
613  OS << ")";
614  OS << ":\n";
615 
616  bool HasLineAttributes = false;
617  // Print the successors
618  bool canPredictProbs = canPredictBranchProbabilities(MBB);
619  // Even if the list of successors is empty, if we cannot guess it,
620  // we need to print it to tell the parser that the list is empty.
621  // This is needed, because MI model unreachable as empty blocks
622  // with an empty successor list. If the parser would see that
623  // without the successor list, it would guess the code would
624  // fallthrough.
625  if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
626  !canPredictSuccessors(MBB)) {
627  OS.indent(2) << "successors: ";
628  for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
629  if (I != MBB.succ_begin())
630  OS << ", ";
631  printMBBReference(**I);
632  if (!SimplifyMIR || !canPredictProbs)
633  OS << '('
634  << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
635  << ')';
636  }
637  OS << "\n";
638  HasLineAttributes = true;
639  }
640 
641  // Print the live in registers.
642  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
643  if (MRI.tracksLiveness() && !MBB.livein_empty()) {
644  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
645  OS.indent(2) << "liveins: ";
646  bool First = true;
647  for (const auto &LI : MBB.liveins()) {
648  if (!First)
649  OS << ", ";
650  First = false;
651  printReg(LI.PhysReg, OS, &TRI);
652  if (!LI.LaneMask.all())
653  OS << ":0x" << PrintLaneMask(LI.LaneMask);
654  }
655  OS << "\n";
656  HasLineAttributes = true;
657  }
658 
659  if (HasLineAttributes)
660  OS << "\n";
661  bool IsInBundle = false;
662  for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
663  const MachineInstr &MI = *I;
664  if (IsInBundle && !MI.isInsideBundle()) {
665  OS.indent(2) << "}\n";
666  IsInBundle = false;
667  }
668  OS.indent(IsInBundle ? 4 : 2);
669  print(MI);
670  if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
671  OS << " {";
672  IsInBundle = true;
673  }
674  OS << "\n";
675  }
676  if (IsInBundle)
677  OS.indent(2) << "}\n";
678 }
679 
680 /// Return true when an instruction has tied register that can't be determined
681 /// by the instruction's descriptor.
683  const MCInstrDesc &MCID = MI.getDesc();
684  for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
685  const auto &Operand = MI.getOperand(I);
686  if (!Operand.isReg() || Operand.isDef())
687  // Ignore the defined registers as MCID marks only the uses as tied.
688  continue;
689  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
690  int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
691  if (ExpectedTiedIdx != TiedIdx)
692  return true;
693  }
694  return false;
695 }
696 
697 static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
698  SmallBitVector &PrintedTypes,
699  const MachineRegisterInfo &MRI) {
700  const MachineOperand &Op = MI.getOperand(OpIdx);
701  if (!Op.isReg())
702  return LLT{};
703 
704  if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
705  return MRI.getType(Op.getReg());
706 
707  auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
708  if (!OpInfo.isGenericType())
709  return MRI.getType(Op.getReg());
710 
711  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
712  return LLT{};
713 
714  PrintedTypes.set(OpInfo.getGenericTypeIndex());
715  return MRI.getType(Op.getReg());
716 }
717 
719  const auto *MF = MI.getMF();
720  const auto &MRI = MF->getRegInfo();
721  const auto &SubTarget = MF->getSubtarget();
722  const auto *TRI = SubTarget.getRegisterInfo();
723  assert(TRI && "Expected target register info");
724  const auto *TII = SubTarget.getInstrInfo();
725  assert(TII && "Expected target instruction info");
726  if (MI.isCFIInstruction())
727  assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
728 
729  SmallBitVector PrintedTypes(8);
730  bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
731  unsigned I = 0, E = MI.getNumOperands();
732  for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
733  !MI.getOperand(I).isImplicit();
734  ++I) {
735  if (I)
736  OS << ", ";
737  print(MI, I, TRI, ShouldPrintRegisterTies,
738  getTypeToPrint(MI, I, PrintedTypes, MRI),
739  /*IsDef=*/true);
740  }
741 
742  if (I)
743  OS << " = ";
745  OS << "frame-setup ";
746  OS << TII->getName(MI.getOpcode());
747  if (I < E)
748  OS << ' ';
749 
750  bool NeedComma = false;
751  for (; I < E; ++I) {
752  if (NeedComma)
753  OS << ", ";
754  print(MI, I, TRI, ShouldPrintRegisterTies,
755  getTypeToPrint(MI, I, PrintedTypes, MRI));
756  NeedComma = true;
757  }
758 
759  if (MI.getDebugLoc()) {
760  if (NeedComma)
761  OS << ',';
762  OS << " debug-location ";
763  MI.getDebugLoc()->printAsOperand(OS, MST);
764  }
765 
766  if (!MI.memoperands_empty()) {
767  OS << " :: ";
768  const LLVMContext &Context = MF->getFunction()->getContext();
769  bool NeedComma = false;
770  for (const auto *Op : MI.memoperands()) {
771  if (NeedComma)
772  OS << ", ";
773  print(Context, *TII, *Op);
774  NeedComma = true;
775  }
776  }
777 }
778 
780  OS << "%bb." << MBB.getNumber();
781  if (const auto *BB = MBB.getBasicBlock()) {
782  if (BB->hasName())
783  OS << '.' << BB->getName();
784  }
785 }
786 
787 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
788  if (Slot == -1)
789  OS << "<badref>";
790  else
791  OS << Slot;
792 }
793 
795  OS << "%ir-block.";
796  if (BB.hasName()) {
798  return;
799  }
800  const Function *F = BB.getParent();
801  int Slot;
802  if (F == MST.getCurrentFunction()) {
803  Slot = MST.getLocalSlot(&BB);
804  } else {
805  ModuleSlotTracker CustomMST(F->getParent(),
806  /*ShouldInitializeAllMetadata=*/false);
807  CustomMST.incorporateFunction(*F);
808  Slot = CustomMST.getLocalSlot(&BB);
809  }
810  printIRSlotNumber(OS, Slot);
811 }
812 
814  if (isa<GlobalValue>(V)) {
815  V.printAsOperand(OS, /*PrintType=*/false, MST);
816  return;
817  }
818  if (isa<Constant>(V)) {
819  // Machine memory operands can load/store to/from constant value pointers.
820  OS << '`';
821  V.printAsOperand(OS, /*PrintType=*/true, MST);
822  OS << '`';
823  return;
824  }
825  OS << "%ir.";
826  if (V.hasName()) {
828  return;
829  }
830  printIRSlotNumber(OS, MST.getLocalSlot(&V));
831 }
832 
834  auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
835  assert(ObjectInfo != StackObjectOperandMapping.end() &&
836  "Invalid frame index");
837  const FrameIndexOperand &Operand = ObjectInfo->second;
838  if (Operand.IsFixed) {
839  OS << "%fixed-stack." << Operand.ID;
840  return;
841  }
842  OS << "%stack." << Operand.ID;
843  if (!Operand.Name.empty())
844  OS << '.' << Operand.Name;
845 }
846 
848  if (Offset == 0)
849  return;
850  if (Offset < 0) {
851  OS << " - " << -Offset;
852  return;
853  }
854  OS << " + " << Offset;
855 }
856 
857 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
859  for (const auto &I : Flags) {
860  if (I.first == TF) {
861  return I.second;
862  }
863  }
864  return nullptr;
865 }
866 
868  if (!Op.getTargetFlags())
869  return;
870  const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
871  assert(TII && "expected instruction info");
873  OS << "target-flags(";
874  const bool HasDirectFlags = Flags.first;
875  const bool HasBitmaskFlags = Flags.second;
876  if (!HasDirectFlags && !HasBitmaskFlags) {
877  OS << "<unknown>) ";
878  return;
879  }
880  if (HasDirectFlags) {
881  if (const auto *Name = getTargetFlagName(TII, Flags.first))
882  OS << Name;
883  else
884  OS << "<unknown target flag>";
885  }
886  if (!HasBitmaskFlags) {
887  OS << ") ";
888  return;
889  }
890  bool IsCommaNeeded = HasDirectFlags;
891  unsigned BitMask = Flags.second;
893  for (const auto &Mask : BitMasks) {
894  // Check if the flag's bitmask has the bits of the current mask set.
895  if ((BitMask & Mask.first) == Mask.first) {
896  if (IsCommaNeeded)
897  OS << ", ";
898  IsCommaNeeded = true;
899  OS << Mask.second;
900  // Clear the bits which were serialized from the flag's bitmask.
901  BitMask &= ~(Mask.first);
902  }
903  }
904  if (BitMask) {
905  // When the resulting flag's bitmask isn't zero, we know that we didn't
906  // serialize all of the bit flags.
907  if (IsCommaNeeded)
908  OS << ", ";
909  OS << "<unknown bitmask target flag>";
910  }
911  OS << ") ";
912 }
913 
914 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
915  const auto *TII = MF.getSubtarget().getInstrInfo();
916  assert(TII && "expected instruction info");
917  auto Indices = TII->getSerializableTargetIndices();
918  for (const auto &I : Indices) {
919  if (I.first == Index) {
920  return I.second;
921  }
922  }
923  return nullptr;
924 }
925 
926 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
927  const TargetRegisterInfo *TRI,
928  bool ShouldPrintRegisterTies, LLT TypeToPrint,
929  bool IsDef) {
930  const MachineOperand &Op = MI.getOperand(OpIdx);
931  printTargetFlags(Op);
932  switch (Op.getType()) {
934  unsigned Reg = Op.getReg();
935  if (Op.isImplicit())
936  OS << (Op.isDef() ? "implicit-def " : "implicit ");
937  else if (!IsDef && Op.isDef())
938  // Print the 'def' flag only when the operand is defined after '='.
939  OS << "def ";
940  if (Op.isInternalRead())
941  OS << "internal ";
942  if (Op.isDead())
943  OS << "dead ";
944  if (Op.isKill())
945  OS << "killed ";
946  if (Op.isUndef())
947  OS << "undef ";
948  if (Op.isEarlyClobber())
949  OS << "early-clobber ";
950  if (Op.isDebug())
951  OS << "debug-use ";
952  printReg(Reg, OS, TRI);
953  // Print the sub register.
954  if (Op.getSubReg() != 0)
955  OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
957  const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo();
958  if (IsDef || MRI.def_empty(Reg)) {
959  OS << ':';
960  printRegClassOrBank(Reg, OS, MRI, TRI);
961  }
962  }
963  if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
964  OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(OpIdx) << ")";
965  if (TypeToPrint.isValid())
966  OS << '(' << TypeToPrint << ')';
967  break;
968  }
970  if (MI.isOperandSubregIdx(OpIdx))
971  OS << "%subreg." << TRI->getSubRegIndexName(Op.getImm());
972  else
973  OS << Op.getImm();
974  break;
976  Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
977  break;
979  Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
980  break;
982  printMBBReference(*Op.getMBB());
983  break;
985  printStackObjectReference(Op.getIndex());
986  break;
988  OS << "%const." << Op.getIndex();
989  printOffset(Op.getOffset());
990  break;
992  OS << "target-index(";
993  if (const auto *Name =
994  getTargetIndexName(*Op.getParent()->getMF(), Op.getIndex()))
995  OS << Name;
996  else
997  OS << "<unknown>";
998  OS << ')';
999  printOffset(Op.getOffset());
1000  break;
1002  OS << "%jump-table." << Op.getIndex();
1003  break;
1005  StringRef Name = Op.getSymbolName();
1006  OS << '$';
1007  if (Name.empty()) {
1008  OS << "\"\"";
1009  } else {
1010  printLLVMNameWithoutPrefix(OS, Name);
1011  }
1012  printOffset(Op.getOffset());
1013  break;
1014  }
1016  Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
1017  printOffset(Op.getOffset());
1018  break;
1020  OS << "blockaddress(";
1021  Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
1022  MST);
1023  OS << ", ";
1024  printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
1025  OS << ')';
1026  printOffset(Op.getOffset());
1027  break;
1029  auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
1030  if (RegMaskInfo != RegisterMaskIds.end())
1031  OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
1032  else
1033  printCustomRegMask(Op.getRegMask(), OS, TRI);
1034  break;
1035  }
1037  const uint32_t *RegMask = Op.getRegLiveOut();
1038  OS << "liveout(";
1039  bool IsCommaNeeded = false;
1040  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
1041  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
1042  if (IsCommaNeeded)
1043  OS << ", ";
1044  printReg(Reg, OS, TRI);
1045  IsCommaNeeded = true;
1046  }
1047  }
1048  OS << ")";
1049  break;
1050  }
1052  Op.getMetadata()->printAsOperand(OS, MST);
1053  break;
1055  OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
1056  break;
1058  const MachineFunction &MF = *Op.getParent()->getMF();
1059  print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
1060  break;
1061  }
1064  if (ID < Intrinsic::num_intrinsics)
1065  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
1066  else {
1067  const MachineFunction &MF = *Op.getParent()->getMF();
1069  OS << "intrinsic(@" << TII->getName(ID) << ')';
1070  }
1071  break;
1072  }
1074  auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
1075  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
1076  << CmpInst::getPredicateName(Pred) << ')';
1077  break;
1078  }
1079  }
1080 }
1081 
1082 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
1083  unsigned TMMOFlag) {
1085  for (const auto &I : Flags) {
1086  if (I.first == TMMOFlag) {
1087  return I.second;
1088  }
1089  }
1090  return nullptr;
1091 }
1092 
1094  const MachineMemOperand &Op) {
1095  OS << '(';
1096  if (Op.isVolatile())
1097  OS << "volatile ";
1098  if (Op.isNonTemporal())
1099  OS << "non-temporal ";
1100  if (Op.isDereferenceable())
1101  OS << "dereferenceable ";
1102  if (Op.isInvariant())
1103  OS << "invariant ";
1106  << "\" ";
1109  << "\" ";
1112  << "\" ";
1113  if (Op.isLoad())
1114  OS << "load ";
1115  else {
1116  assert(Op.isStore() && "Non load machine operand must be a store");
1117  OS << "store ";
1118  }
1119 
1120  printSyncScope(Context, Op.getSyncScopeID());
1121 
1123  OS << toIRString(Op.getOrdering()) << ' ';
1125  OS << toIRString(Op.getFailureOrdering()) << ' ';
1126 
1127  OS << Op.getSize();
1128  if (const Value *Val = Op.getValue()) {
1129  OS << (Op.isLoad() ? " from " : " into ");
1130  printIRValueReference(*Val);
1131  } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
1132  OS << (Op.isLoad() ? " from " : " into ");
1133  assert(PVal && "Expected a pseudo source value");
1134  switch (PVal->kind()) {
1136  OS << "stack";
1137  break;
1139  OS << "got";
1140  break;
1142  OS << "jump-table";
1143  break;
1145  OS << "constant-pool";
1146  break;
1148  printStackObjectReference(
1149  cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
1150  break;
1152  OS << "call-entry ";
1153  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1154  OS, /*PrintType=*/false, MST);
1155  break;
1157  OS << "call-entry $";
1159  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1160  break;
1162  llvm_unreachable("TargetCustom pseudo source values are not supported");
1163  break;
1164  }
1165  }
1166  printOffset(Op.getOffset());
1167  if (Op.getBaseAlignment() != Op.getSize())
1168  OS << ", align " << Op.getBaseAlignment();
1169  auto AAInfo = Op.getAAInfo();
1170  if (AAInfo.TBAA) {
1171  OS << ", !tbaa ";
1172  AAInfo.TBAA->printAsOperand(OS, MST);
1173  }
1174  if (AAInfo.Scope) {
1175  OS << ", !alias.scope ";
1176  AAInfo.Scope->printAsOperand(OS, MST);
1177  }
1178  if (AAInfo.NoAlias) {
1179  OS << ", !noalias ";
1180  AAInfo.NoAlias->printAsOperand(OS, MST);
1181  }
1182  if (Op.getRanges()) {
1183  OS << ", !range ";
1184  Op.getRanges()->printAsOperand(OS, MST);
1185  }
1186  OS << ')';
1187 }
1188 
1190  switch (SSID) {
1191  case SyncScope::System: {
1192  break;
1193  }
1194  default: {
1195  if (SSNs.empty())
1196  Context.getSyncScopeNames(SSNs);
1197 
1198  OS << "syncscope(\"";
1199  PrintEscapedString(SSNs[SSID], OS);
1200  OS << "\") ";
1201  break;
1202  }
1203  }
1204 }
1205 
1206 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
1207  const TargetRegisterInfo *TRI) {
1208  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
1209  if (Reg == -1) {
1210  OS << "<badreg>";
1211  return;
1212  }
1213  printReg(Reg, OS, TRI);
1214 }
1215 
1217  const TargetRegisterInfo *TRI) {
1218  switch (CFI.getOperation()) {
1220  OS << "same_value ";
1221  if (CFI.getLabel())
1222  OS << "<mcsymbol> ";
1223  printCFIRegister(CFI.getRegister(), OS, TRI);
1224  break;
1226  OS << "offset ";
1227  if (CFI.getLabel())
1228  OS << "<mcsymbol> ";
1229  printCFIRegister(CFI.getRegister(), OS, TRI);
1230  OS << ", " << CFI.getOffset();
1231  break;
1233  OS << "def_cfa_register ";
1234  if (CFI.getLabel())
1235  OS << "<mcsymbol> ";
1236  printCFIRegister(CFI.getRegister(), OS, TRI);
1237  break;
1239  OS << "def_cfa_offset ";
1240  if (CFI.getLabel())
1241  OS << "<mcsymbol> ";
1242  OS << CFI.getOffset();
1243  break;
1245  OS << "def_cfa ";
1246  if (CFI.getLabel())
1247  OS << "<mcsymbol> ";
1248  printCFIRegister(CFI.getRegister(), OS, TRI);
1249  OS << ", " << CFI.getOffset();
1250  break;
1252  OS << "restore ";
1253  if (CFI.getLabel())
1254  OS << "<mcsymbol> ";
1255  printCFIRegister(CFI.getRegister(), OS, TRI);
1256  break;
1257  default:
1258  // TODO: Print the other CFI Operations.
1259  OS << "<unserializable cfi operation>";
1260  break;
1261  }
1262 }
1263 
1264 void llvm::printMIR(raw_ostream &OS, const Module &M) {
1265  yaml::Output Out(OS);
1266  Out << const_cast<Module &>(M);
1267 }
1268 
1270  MIRPrinter Printer(OS);
1271  Printer.print(MF);
1272 }
unsigned getTargetFlags() const
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool hasSuccessorProbabilities() const
Return true if any of the successors have probabilities attached to them.
A common definition of LaneBitmask for use in TableGen and CodeGen.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
instr_iterator instr_begin()
LLVMContext & Context
static StringRef input(StringRef Str, void *Ctxt, Module &Mod)
Definition: MIRPrinter.cpp:186
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Atomic ordering constants.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the function&#39;s prologue.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:656
bool hasVAStart() const
Returns true if the function calls the llvm.va_start intrinsic.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool hasStackProtectorIndex() const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
void PrintEscapedString(StringRef Name, raw_ostream &Out)
PrintEscapedString - Print each character of the specified string, escaping it if it is not printable...
Definition: AsmWriter.cpp:386
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Definition: MIRPrinter.cpp:787
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MIRPrinter.cpp:857
This class prints out the machine functions using the MIR serialization format.
Definition: MIRPrinter.cpp:109
bool isCFIInstruction() const
Definition: MachineInstr.h:809
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
Optional< std::vector< FlowStringValue > > CalleeSavedRegisters
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
uint64_t getSize() const
Return the size in bytes of the memory reference.
static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI)
Definition: MIRPrinter.cpp:697
MachineBasicBlock reference.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:396
Mask of live-out registers.
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
print alias Alias Set Printer
bool isInternalRead() const
VariableDbgInfoMapTy & getVariableDbgInfo()
void printTargetFlags(const MachineOperand &Op)
Definition: MIRPrinter.cpp:867
bool isVariableSizedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a variable sized object.
Mask of preserved registers.
Function * getFunction() const
Definition: Constants.h:839
bool isEarlyClobber() const
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A description of a memory reference used in the backend.
std::pair< int, int64_t > getLocalFrameObjectMap(int i) const
Get the local offset mapping for a for an object.
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:591
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Serializable representation of the fixed stack object from the MachineFrameInfo class.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const MDNode * getRanges() const
Return the range tag for the memory reference.
MachineBasicBlock * getRestorePoint() const
void print(const MachineBasicBlock &MBB)
Definition: MIRPrinter.cpp:580
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MIRPrinter.cpp:914
Target-dependent index+offset operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Name of external global symbol.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getAlignment() const
getAlignment - Return the alignment (log2, not bytes) of the function.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
const char * getSymbolName() const
unsigned getCFIIndex() const
bool isImmutableObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to an immutable object.
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
std::vector< VirtualRegisterDefinition > VirtualRegisters
Immediate >64bit operand.
static void normalizeProbabilities(ProbabilityIter Begin, ProbabilityIter End)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
int getObjectIndexBegin() const
Return the minimum frame object index.
BasicBlock * getBasicBlock() const
Definition: Constants.h:840
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
This class is a data container for one entry in a MachineConstantPool.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual const TargetInstrInfo * getInstrInfo() const
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:235
MCSymbol * getLabel() const
Definition: MCDwarf.h:470
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:249
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
MIRPrinter(raw_ostream &OS)
Definition: MIRPrinter.cpp:117
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
const TargetRegisterInfo * getTargetRegisterInfo() const
std::vector< FlowStringValue > Blocks
unsigned const MachineRegisterInfo * MRI
Serializable representation of stack object from the MachineFrameInfo class.
bool hasName() const
Definition: Value.h:251
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
static cl::opt< bool > SimplifyMIR("simplify-mir", cl::desc("Leave out unnecessary information when printing MIR"))
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
MachineJumpTable JumpTableInfo
Constant pool.
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:305
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:371
unsigned getAlignment() const
Return alignment of the basic block.
int getStackProtectorIndex() const
Return the index for the stack protector object.
int getOffset() const
Definition: MCDwarf.h:485
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:469
virtual ArrayRef< const char * > getRegMaskNames() const =0
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:853
void print(raw_ostream &O, bool IsForDebug=false) const
Implement operator<< on Value.
Definition: AsmWriter.cpp:3494
void convertStackObjects(yaml::MachineFunction &YMF, const MachineFunction &MF, ModuleSlotTracker &MST)
Definition: MIRPrinter.cpp:363
unsigned MaxCallFrameSize
~0u means: not computed yet.
This class prints out the machine instructions using the MIR serialization format.
Definition: MIRPrinter.cpp:138
std::vector< MachineStackObject > StackObjects
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
self_iterator getIterator()
Definition: ilist_node.h:82
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:254
Serializable representation of MachineFrameInfo.
static void printReg(unsigned Reg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:195
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
void printMIR(raw_ostream &OS, const Module &M)
Print LLVM IR using the MIR serialization format to the given output stream.
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:771
The Output class is used to generate a yaml document from in-memory structs and vectors.
Definition: YAMLTraits.h:1260
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:3573
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:478
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:59
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
unsigned getRegister() const
Definition: MCDwarf.h:472
const std::vector< MachineConstantPoolEntry > & getConstants() const
void print(raw_ostream &OS, AssemblyAnnotationWriter *AAW, bool ShouldPreserveUseListOrder=false, bool IsForDebug=false) const
Print the module to an output stream with an optional AssemblyAnnotationWriter.
Definition: AsmWriter.cpp:3411
void setWriteDefaultValues(bool Write)
Set whether or not to output optional values which are equal to the default value.
Definition: YAMLTraits.h:1270
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:418
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
Module.h This file contains the declarations for the Module class.
static void printRegClassOrBank(unsigned Reg, raw_ostream &OS, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:273
void printIRBlockReference(const BasicBlock &BB)
Definition: MIRPrinter.cpp:794
Intrinsic::ID getIntrinsicID() const
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:404
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:438
void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID)
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
MCSymbol reference (for debug/eh info)
bool isIntPredicate() const
Definition: InstrTypes.h:945
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Special value supplied for machine level alias analysis.
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
A wrapper around std::string which contains a source range that&#39;s being set during parsing...
unsigned succ_size() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
std::vector< MachineFunctionLiveIn > LiveIns
static void output(const Module &Mod, void *Ctxt, raw_ostream &OS)
Definition: MIRPrinter.cpp:182
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This class should be specialized by type that requires custom conversion to/from a YAML literal block...
Definition: YAMLTraits.h:168
bool isEHPad() const
Returns true if the block is a landing pad.
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isAliasedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to an object that might be pointed to by an LLVM IR v...
static bool hasComplexRegisterTies(const MachineInstr &MI)
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
Definition: MIRPrinter.cpp:682
std::vector< Entry > Entries
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:220
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
const BlockAddress * getBlockAddress() const
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
std::vector< MachineConstantPoolValue > Constants
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
int getOffsetAdjustment() const
Return the correction for frame offsets.
Abstract Stack Frame Index.
void printMBBReference(const MachineBasicBlock &MBB)
Definition: MIRPrinter.cpp:779
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:295
This file defines passes to print out IR in various granularities.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
uint8_t getStackID(int ObjectIdx) const
void printOffset(int64_t Offset)
Definition: MIRPrinter.cpp:847
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:123
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:3617
MachineBasicBlock * getSavePoint() const
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the the memory access done by this i...
Definition: MachineInstr.h:394
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
std::vector< FixedMachineStackObject > FixedStackObjects
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:462
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:556
LLVM Value Representation.
Definition: Value.h:73
JTEntryKind getEntryKind() const
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
void printIRValueReference(const Value &V)
Definition: MIRPrinter.cpp:813
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
void printStackObjectReference(int FrameIndex)
Definition: MIRPrinter.cpp:833
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
bool isMaxCallFrameSizeComputed() const
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Address of indexed Constant in Constant Pool.
MachineJumpTableInfo::JTEntryKind Kind
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST, const DenseMap< const uint32_t *, unsigned > &RegisterMaskIds, const DenseMap< int, FrameIndexOperand > &StackObjectOperandMapping)
Definition: MIRPrinter.cpp:150
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
int64_t getLocalFrameObjectCount() const
Return the number of objects allocated into the local object block.
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void print(const MachineFunction &MF)
Definition: MIRPrinter.cpp:214
uint32_t getNumerator() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:180
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock *> &Successors, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
Definition: MIRPrinter.cpp:524
const MDNode * getMetadata() const
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
bool isImplicit() const
bool hasCalls() const
Return true if the current function has any function calls.
Metadata reference (for debug info)
unsigned getPredicate() const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:867