LLVM  10.0.0svn
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "asm-printer"
54 
56  std::unique_ptr<MCStreamer> Streamer)
57  : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
58  InConstantPool(false), OptimizationGoals(-1) {}
59 
61  // Make sure to terminate any constant pools that were at the end
62  // of the function.
63  if (!InConstantPool)
64  return;
65  InConstantPool = false;
66  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
67 }
68 
70  if (AFI->isThumbFunction()) {
71  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
72  OutStreamer->EmitThumbFunc(CurrentFnSym);
73  } else {
74  OutStreamer->EmitAssemblerFlag(MCAF_Code32);
75  }
76  OutStreamer->EmitLabel(CurrentFnSym);
77 }
78 
80  uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
81  assert(Size && "C++ constructor pointer had zero size!");
82 
84  assert(GV && "C++ constructor pointer was not a GlobalValue!");
85 
86  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
88  (Subtarget->isTargetELF()
91  OutContext);
92 
93  OutStreamer->EmitValue(E, Size);
94 }
95 
97  if (PromotedGlobals.count(GV))
98  // The global was promoted into a constant pool. It should not be emitted.
99  return;
101 }
102 
103 /// runOnMachineFunction - This uses the EmitInstruction()
104 /// method to print assembly for each instruction.
105 ///
107  AFI = MF.getInfo<ARMFunctionInfo>();
108  MCP = MF.getConstantPool();
109  Subtarget = &MF.getSubtarget<ARMSubtarget>();
110 
112  const Function &F = MF.getFunction();
113  const TargetMachine& TM = MF.getTarget();
114 
115  // Collect all globals that had their storage promoted to a constant pool.
116  // Functions are emitted before variables, so this accumulates promoted
117  // globals from all functions in PromotedGlobals.
118  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
119  PromotedGlobals.insert(GV);
120 
121  // Calculate this function's optimization goal.
122  unsigned OptimizationGoal;
123  if (F.hasOptNone())
124  // For best debugging illusion, speed and small size sacrificed
125  OptimizationGoal = 6;
126  else if (F.hasMinSize())
127  // Aggressively for small size, speed and debug illusion sacrificed
128  OptimizationGoal = 4;
129  else if (F.hasOptSize())
130  // For small size, but speed and debugging illusion preserved
131  OptimizationGoal = 3;
132  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
133  // Aggressively for speed, small size and debug illusion sacrificed
134  OptimizationGoal = 2;
135  else if (TM.getOptLevel() > CodeGenOpt::None)
136  // For speed, but small size and good debug illusion preserved
137  OptimizationGoal = 1;
138  else // TM.getOptLevel() == CodeGenOpt::None
139  // For good debugging, but speed and small size preserved
140  OptimizationGoal = 5;
141 
142  // Combine a new optimization goal with existing ones.
143  if (OptimizationGoals == -1) // uninitialized goals
144  OptimizationGoals = OptimizationGoal;
145  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
146  OptimizationGoals = 0;
147 
148  if (Subtarget->isTargetCOFF()) {
149  bool Internal = F.hasInternalLinkage();
153 
154  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
155  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
156  OutStreamer->EmitCOFFSymbolType(Type);
157  OutStreamer->EndCOFFSymbolDef();
158  }
159 
160  // Emit the rest of the function body.
162 
163  // Emit the XRay table for this function.
164  emitXRayTable();
165 
166  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
167  // These are created per function, rather than per TU, since it's
168  // relatively easy to exceed the thumb branch range within a TU.
169  if (! ThumbIndirectPads.empty()) {
170  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
171  EmitAlignment(Align(2));
172  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
173  OutStreamer->EmitLabel(TIP.second);
175  .addReg(TIP.first)
176  // Add predicate operands.
177  .addImm(ARMCC::AL)
178  .addReg(0));
179  }
180  ThumbIndirectPads.clear();
181  }
182 
183  // We didn't modify anything.
184  return false;
185 }
186 
188  raw_ostream &O) {
189  assert(MO.isGlobal() && "caller should check MO.isGlobal");
190  unsigned TF = MO.getTargetFlags();
191  if (TF & ARMII::MO_LO16)
192  O << ":lower16:";
193  else if (TF & ARMII::MO_HI16)
194  O << ":upper16:";
195  GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
196  printOffset(MO.getOffset(), O);
197 }
198 
200  raw_ostream &O) {
201  const MachineOperand &MO = MI->getOperand(OpNum);
202 
203  switch (MO.getType()) {
204  default: llvm_unreachable("<unknown operand type>");
206  Register Reg = MO.getReg();
208  assert(!MO.getSubReg() && "Subregs should be eliminated!");
209  if(ARM::GPRPairRegClass.contains(Reg)) {
210  const MachineFunction &MF = *MI->getParent()->getParent();
212  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
213  }
215  break;
216  }
218  O << '#';
219  unsigned TF = MO.getTargetFlags();
220  if (TF == ARMII::MO_LO16)
221  O << ":lower16:";
222  else if (TF == ARMII::MO_HI16)
223  O << ":upper16:";
224  O << MO.getImm();
225  break;
226  }
228  MO.getMBB()->getSymbol()->print(O, MAI);
229  return;
231  PrintSymbolOperand(MO, O);
232  break;
233  }
235  if (Subtarget->genExecuteOnly())
236  llvm_unreachable("execute-only should not generate constant pools");
237  GetCPISymbol(MO.getIndex())->print(O, MAI);
238  break;
239  }
240 }
241 
242 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
243  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
244  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
245  const DataLayout &DL = getDataLayout();
247  "CPI" + Twine(getFunctionNumber()) + "_" +
248  Twine(CPID));
249 }
250 
251 //===--------------------------------------------------------------------===//
252 
253 MCSymbol *ARMAsmPrinter::
254 GetARMJTIPICJumpTableLabel(unsigned uid) const {
255  const DataLayout &DL = getDataLayout();
257  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
258  << getFunctionNumber() << '_' << uid;
259  return OutContext.getOrCreateSymbol(Name);
260 }
261 
262 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
263  const char *ExtraCode, raw_ostream &O) {
264  // Does this asm operand have a single letter operand modifier?
265  if (ExtraCode && ExtraCode[0]) {
266  if (ExtraCode[1] != 0) return true; // Unknown modifier.
267 
268  switch (ExtraCode[0]) {
269  default:
270  // See if this is a generic print operand
271  return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
272  case 'P': // Print a VFP double precision register.
273  case 'q': // Print a NEON quad precision register.
274  printOperand(MI, OpNum, O);
275  return false;
276  case 'y': // Print a VFP single precision register as indexed double.
277  if (MI->getOperand(OpNum).isReg()) {
278  Register Reg = MI->getOperand(OpNum).getReg();
280  // Find the 'd' register that has this 's' register as a sub-register,
281  // and determine the lane number.
282  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
283  if (!ARM::DPRRegClass.contains(*SR))
284  continue;
285  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
286  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
287  return false;
288  }
289  }
290  return true;
291  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
292  if (!MI->getOperand(OpNum).isImm())
293  return true;
294  O << ~(MI->getOperand(OpNum).getImm());
295  return false;
296  case 'L': // The low 16 bits of an immediate constant.
297  if (!MI->getOperand(OpNum).isImm())
298  return true;
299  O << (MI->getOperand(OpNum).getImm() & 0xffff);
300  return false;
301  case 'M': { // A register range suitable for LDM/STM.
302  if (!MI->getOperand(OpNum).isReg())
303  return true;
304  const MachineOperand &MO = MI->getOperand(OpNum);
305  Register RegBegin = MO.getReg();
306  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
307  // already got the operands in registers that are operands to the
308  // inline asm statement.
309  O << "{";
310  if (ARM::GPRPairRegClass.contains(RegBegin)) {
312  Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
313  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
314  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
315  }
316  O << ARMInstPrinter::getRegisterName(RegBegin);
317 
318  // FIXME: The register allocator not only may not have given us the
319  // registers in sequence, but may not be in ascending registers. This
320  // will require changes in the register allocator that'll need to be
321  // propagated down here if the operands change.
322  unsigned RegOps = OpNum + 1;
323  while (MI->getOperand(RegOps).isReg()) {
324  O << ", "
326  RegOps++;
327  }
328 
329  O << "}";
330 
331  return false;
332  }
333  case 'R': // The most significant register of a pair.
334  case 'Q': { // The least significant register of a pair.
335  if (OpNum == 0)
336  return true;
337  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
338  if (!FlagsOP.isImm())
339  return true;
340  unsigned Flags = FlagsOP.getImm();
341 
342  // This operand may not be the one that actually provides the register. If
343  // it's tied to a previous one then we should refer instead to that one
344  // for registers and their classes.
345  unsigned TiedIdx;
346  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
347  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
348  unsigned OpFlags = MI->getOperand(OpNum).getImm();
349  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
350  }
351  Flags = MI->getOperand(OpNum).getImm();
352 
353  // Later code expects OpNum to be pointing at the register rather than
354  // the flags.
355  OpNum += 1;
356  }
357 
358  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
359  unsigned RC;
360  bool FirstHalf;
361  const ARMBaseTargetMachine &ATM =
362  static_cast<const ARMBaseTargetMachine &>(TM);
363 
364  // 'Q' should correspond to the low order register and 'R' to the high
365  // order register. Whether this corresponds to the upper or lower half
366  // depends on the endianess mode.
367  if (ExtraCode[0] == 'Q')
368  FirstHalf = ATM.isLittleEndian();
369  else
370  // ExtraCode[0] == 'R'.
371  FirstHalf = !ATM.isLittleEndian();
373  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
374  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
375  if (NumVals != 1)
376  return true;
377  const MachineOperand &MO = MI->getOperand(OpNum);
378  if (!MO.isReg())
379  return true;
381  Register Reg =
382  TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
384  return false;
385  }
386  if (NumVals != 2)
387  return true;
388  unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
389  if (RegOp >= MI->getNumOperands())
390  return true;
391  const MachineOperand &MO = MI->getOperand(RegOp);
392  if (!MO.isReg())
393  return true;
394  Register Reg = MO.getReg();
396  return false;
397  }
398 
399  case 'e': // The low doubleword register of a NEON quad register.
400  case 'f': { // The high doubleword register of a NEON quad register.
401  if (!MI->getOperand(OpNum).isReg())
402  return true;
403  Register Reg = MI->getOperand(OpNum).getReg();
404  if (!ARM::QPRRegClass.contains(Reg))
405  return true;
407  Register SubReg =
408  TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
409  O << ARMInstPrinter::getRegisterName(SubReg);
410  return false;
411  }
412 
413  // This modifier is not yet supported.
414  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
415  return true;
416  case 'H': { // The highest-numbered register of a pair.
417  const MachineOperand &MO = MI->getOperand(OpNum);
418  if (!MO.isReg())
419  return true;
420  const MachineFunction &MF = *MI->getParent()->getParent();
422  Register Reg = MO.getReg();
423  if(!ARM::GPRPairRegClass.contains(Reg))
424  return false;
425  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
427  return false;
428  }
429  }
430  }
431 
432  printOperand(MI, OpNum, O);
433  return false;
434 }
435 
437  unsigned OpNum, const char *ExtraCode,
438  raw_ostream &O) {
439  // Does this asm operand have a single letter operand modifier?
440  if (ExtraCode && ExtraCode[0]) {
441  if (ExtraCode[1] != 0) return true; // Unknown modifier.
442 
443  switch (ExtraCode[0]) {
444  case 'A': // A memory operand for a VLD1/VST1 instruction.
445  default: return true; // Unknown modifier.
446  case 'm': // The base register of a memory operand.
447  if (!MI->getOperand(OpNum).isReg())
448  return true;
450  return false;
451  }
452  }
453 
454  const MachineOperand &MO = MI->getOperand(OpNum);
455  assert(MO.isReg() && "unexpected inline asm memory operand");
456  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
457  return false;
458 }
459 
460 static bool isThumb(const MCSubtargetInfo& STI) {
461  return STI.getFeatureBits()[ARM::ModeThumb];
462 }
463 
465  const MCSubtargetInfo *EndInfo) const {
466  // If either end mode is unknown (EndInfo == NULL) or different than
467  // the start mode, then restore the start mode.
468  const bool WasThumb = isThumb(StartInfo);
469  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
470  OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
471  }
472 }
473 
475  const Triple &TT = TM.getTargetTriple();
476  // Use unified assembler syntax.
477  OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
478 
479  // Emit ARM Build Attributes
480  if (TT.isOSBinFormatELF())
481  emitAttributes();
482 
483  // Use the triple's architecture and subarchitecture to determine
484  // if we're thumb for the purposes of the top level code16 assembler
485  // flag.
486  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
487  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
488 }
489 
490 static void
493  // L_foo$stub:
494  OutStreamer.EmitLabel(StubLabel);
495  // .indirect_symbol _foo
496  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
497 
498  if (MCSym.getInt())
499  // External to current translation unit.
500  OutStreamer.EmitIntValue(0, 4/*size*/);
501  else
502  // Internal to current translation unit.
503  //
504  // When we place the LSDA into the TEXT section, the type info
505  // pointers need to be indirect and pc-rel. We accomplish this by
506  // using NLPs; however, sometimes the types are local to the file.
507  // We need to fill in the value for the NLP in those cases.
508  OutStreamer.EmitValue(
509  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
510  4 /*size*/);
511 }
512 
513 
515  const Triple &TT = TM.getTargetTriple();
516  if (TT.isOSBinFormatMachO()) {
517  // All darwin targets use mach-o.
518  const TargetLoweringObjectFileMachO &TLOFMacho =
519  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
520  MachineModuleInfoMachO &MMIMacho =
522 
523  // Output non-lazy-pointers for external and common global variables.
525 
526  if (!Stubs.empty()) {
527  // Switch with ".non_lazy_symbol_pointer" directive.
528  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
529  EmitAlignment(Align(4));
530 
531  for (auto &Stub : Stubs)
532  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
533 
534  Stubs.clear();
535  OutStreamer->AddBlankLine();
536  }
537 
538  Stubs = MMIMacho.GetThreadLocalGVStubList();
539  if (!Stubs.empty()) {
540  // Switch with ".non_lazy_symbol_pointer" directive.
541  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
542  EmitAlignment(Align(4));
543 
544  for (auto &Stub : Stubs)
545  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
546 
547  Stubs.clear();
548  OutStreamer->AddBlankLine();
549  }
550 
551  // Funny Darwin hack: This flag tells the linker that no global symbols
552  // contain code that falls through to other global symbols (e.g. the obvious
553  // implementation of multiple entry points). If this doesn't occur, the
554  // linker can safely perform dead code stripping. Since LLVM never
555  // generates code that does this, it is always safe to set.
556  OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
557  }
558 
559  // The last attribute to be emitted is ABI_optimization_goals
560  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
561  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
562 
563  if (OptimizationGoals > 0 &&
564  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
565  Subtarget->isTargetMuslAEABI()))
567  OptimizationGoals = -1;
568 
570 }
571 
572 //===----------------------------------------------------------------------===//
573 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
574 // FIXME:
575 // The following seem like one-off assembler flags, but they actually need
576 // to appear in the .ARM.attributes section in ELF.
577 // Instead of subclassing the MCELFStreamer, we do the work here.
578 
579 // Returns true if all functions have the same function attribute value.
580 // It also returns true when the module has no functions.
582  StringRef Value) {
583  return !any_of(M, [&](const Function &F) {
584  return F.getFnAttribute(Attr).getValueAsString() != Value;
585  });
586 }
587 
588 void ARMAsmPrinter::emitAttributes() {
589  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
590  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
591 
593 
594  ATS.switchVendor("aeabi");
595 
596  // Compute ARM ELF Attributes based on the default subtarget that
597  // we'd have constructed. The existing ARM behavior isn't LTO clean
598  // anyhow.
599  // FIXME: For ifunc related functions we could iterate over and look
600  // for a feature string that doesn't match the default one.
601  const Triple &TT = TM.getTargetTriple();
602  StringRef CPU = TM.getTargetCPU();
604  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
605  if (!FS.empty()) {
606  if (!ArchFS.empty())
607  ArchFS = (Twine(ArchFS) + "," + FS).str();
608  else
609  ArchFS = FS;
610  }
611  const ARMBaseTargetMachine &ATM =
612  static_cast<const ARMBaseTargetMachine &>(TM);
613  const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
614 
615  // Emit build attributes for the available hardware.
616  ATS.emitTargetAttributes(STI);
617 
618  // RW data addressing.
619  if (isPositionIndependent()) {
622  } else if (STI.isRWPI()) {
623  // RWPI specific attributes.
626  }
627 
628  // RO data addressing.
629  if (isPositionIndependent() || STI.isROPI()) {
632  }
633 
634  // GOT use.
635  if (isPositionIndependent()) {
638  } else {
641  }
642 
643  // Set FP Denormals.
645  "denormal-fp-math",
646  "preserve-sign") ||
651  "denormal-fp-math",
652  "positive-zero") ||
656  else if (!TM.Options.UnsafeFPMath)
659  else {
660  if (!STI.hasVFP2Base()) {
661  // When the target doesn't have an FPU (by design or
662  // intention), the assumptions made on the software support
663  // mirror that of the equivalent hardware support *if it
664  // existed*. For v7 and better we indicate that denormals are
665  // flushed preserving sign, and for V6 we indicate that
666  // denormals are flushed to positive zero.
667  if (STI.hasV7Ops())
670  } else if (STI.hasVFP3Base()) {
671  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
672  // the sign bit of the zero matches the sign bit of the input or
673  // result that is being flushed to zero.
676  }
677  // For VFPv2 implementations it is implementation defined as
678  // to whether denormals are flushed to positive zero or to
679  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
680  // LLVM has chosen to flush this to positive zero (most likely for
681  // GCC compatibility), so that's the chosen value here (the
682  // absence of its emission implies zero).
683  }
684 
685  // Set FP exceptions and rounding
687  "no-trapping-math", "true") ||
691  else if (!TM.Options.UnsafeFPMath) {
693 
694  // If the user has permitted this code to choose the IEEE 754
695  // rounding at run-time, emit the rounding attribute.
698  }
699 
700  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
701  // equivalent of GCC's -ffinite-math-only flag.
705  else
708 
709  // FIXME: add more flags to ARMBuildAttributes.h
710  // 8-bytes alignment stuff.
713 
714  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
715  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
717 
718  // FIXME: To support emitting this build attribute as GCC does, the
719  // -mfp16-format option and associated plumbing must be
720  // supported. For now the __fp16 type is exposed by default, so this
721  // attribute should be emitted with value 1.
724 
725  if (MMI) {
726  if (const Module *SourceModule = MMI->getModule()) {
727  // ABI_PCS_wchar_t to indicate wchar_t width
728  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
729  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
730  SourceModule->getModuleFlag("wchar_size"))) {
731  int WCharWidth = WCharWidthValue->getZExtValue();
732  assert((WCharWidth == 2 || WCharWidth == 4) &&
733  "wchar_t width must be 2 or 4 bytes");
735  }
736 
737  // ABI_enum_size to indicate enum width
738  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
739  // (all enums contain a value needing 32 bits to encode).
740  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
741  SourceModule->getModuleFlag("min_enum_size"))) {
742  int EnumWidth = EnumWidthValue->getZExtValue();
743  assert((EnumWidth == 1 || EnumWidth == 4) &&
744  "Minimum enum width must be 1 or 4 bytes");
745  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
746  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
747  }
748  }
749  }
750 
751  // We currently do not support using R9 as the TLS pointer.
752  if (STI.isRWPI())
755  else if (STI.isR9Reserved())
758  else
761 }
762 
763 //===----------------------------------------------------------------------===//
764 
766  unsigned LabelId, MCContext &Ctx) {
767 
768  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
769  + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
770  return Label;
771 }
772 
774  unsigned LabelId, MCContext &Ctx) {
775 
776  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
777  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
778  return Label;
779 }
780 
783  switch (Modifier) {
784  case ARMCP::no_modifier:
786  case ARMCP::TLSGD:
788  case ARMCP::TPOFF:
790  case ARMCP::GOTTPOFF:
792  case ARMCP::SBREL:
794  case ARMCP::GOT_PREL:
796  case ARMCP::SECREL:
798  }
799  llvm_unreachable("Invalid ARMCPModifier!");
800 }
801 
802 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
803  unsigned char TargetFlags) {
804  if (Subtarget->isTargetMachO()) {
805  bool IsIndirect =
806  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
807 
808  if (!IsIndirect)
809  return getSymbol(GV);
810 
811  // FIXME: Remove this when Darwin transition to @GOT like syntax.
812  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
813  MachineModuleInfoMachO &MMIMachO =
816  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
817  : MMIMachO.getGVStubEntry(MCSym);
818 
819  if (!StubSym.getPointer())
821  !GV->hasInternalLinkage());
822  return MCSym;
823  } else if (Subtarget->isTargetCOFF()) {
824  assert(Subtarget->isTargetWindows() &&
825  "Windows is the only supported COFF target");
826 
827  bool IsIndirect =
828  (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
829  if (!IsIndirect)
830  return getSymbol(GV);
831 
833  if (TargetFlags & ARMII::MO_DLLIMPORT)
834  Name = "__imp_";
835  else if (TargetFlags & ARMII::MO_COFFSTUB)
836  Name = ".refptr.";
837  getNameWithPrefix(Name, GV);
838 
839  MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
840 
841  if (TargetFlags & ARMII::MO_COFFSTUB) {
842  MachineModuleInfoCOFF &MMICOFF =
845  MMICOFF.getGVStubEntry(MCSym);
846 
847  if (!StubSym.getPointer())
848  StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
849  }
850 
851  return MCSym;
852  } else if (Subtarget->isTargetELF()) {
853  return getSymbol(GV);
854  }
855  llvm_unreachable("unexpected target");
856 }
857 
858 void ARMAsmPrinter::
860  const DataLayout &DL = getDataLayout();
861  int Size = DL.getTypeAllocSize(MCPV->getType());
862 
863  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
864 
865  if (ACPV->isPromotedGlobal()) {
866  // This constant pool entry is actually a global whose storage has been
867  // promoted into the constant pool. This global may be referenced still
868  // by debug information, and due to the way AsmPrinter is set up, the debug
869  // info is immutable by the time we decide to promote globals to constant
870  // pools. Because of this, we need to ensure we emit a symbol for the global
871  // with private linkage (the default) so debug info can refer to it.
872  //
873  // However, if this global is promoted into several functions we must ensure
874  // we don't try and emit duplicate symbols!
875  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
876  for (const auto *GV : ACPC->promotedGlobals()) {
877  if (!EmittedPromotedGlobalLabels.count(GV)) {
878  MCSymbol *GVSym = getSymbol(GV);
879  OutStreamer->EmitLabel(GVSym);
880  EmittedPromotedGlobalLabels.insert(GV);
881  }
882  }
883  return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
884  }
885 
886  MCSymbol *MCSym;
887  if (ACPV->isLSDA()) {
888  MCSym = getCurExceptionSym();
889  } else if (ACPV->isBlockAddress()) {
890  const BlockAddress *BA =
891  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
892  MCSym = GetBlockAddressSymbol(BA);
893  } else if (ACPV->isGlobalValue()) {
894  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
895 
896  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
897  // flag the global as MO_NONLAZY.
898  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
899  MCSym = GetARMGVSymbol(GV, TF);
900  } else if (ACPV->isMachineBasicBlock()) {
901  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
902  MCSym = MBB->getSymbol();
903  } else {
904  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
905  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
906  MCSym = GetExternalSymbolSymbol(Sym);
907  }
908 
909  // Create an MCSymbol for the reference.
910  const MCExpr *Expr =
912  OutContext);
913 
914  if (ACPV->getPCAdjustment()) {
915  MCSymbol *PCLabel =
917  ACPV->getLabelId(), OutContext);
918  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
919  PCRelExpr =
920  MCBinaryExpr::createAdd(PCRelExpr,
922  OutContext),
923  OutContext);
924  if (ACPV->mustAddCurrentAddress()) {
925  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
926  // label, so just emit a local label end reference that instead.
928  OutStreamer->EmitLabel(DotSym);
929  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
930  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
931  }
932  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
933  }
934  OutStreamer->EmitValue(Expr, Size);
935 }
936 
938  const MachineOperand &MO1 = MI->getOperand(1);
939  unsigned JTI = MO1.getIndex();
940 
941  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
942  // ARM mode tables.
943  EmitAlignment(Align(4));
944 
945  // Emit a label for the jump table.
946  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
947  OutStreamer->EmitLabel(JTISymbol);
948 
949  // Mark the jump table as data-in-code.
950  OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
951 
952  // Emit each entry of the table.
953  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
954  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
955  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
956 
957  for (MachineBasicBlock *MBB : JTBBs) {
958  // Construct an MCExpr for the entry. We want a value of the form:
959  // (BasicBlockAddr - TableBeginAddr)
960  //
961  // For example, a table with entries jumping to basic blocks BB0 and BB1
962  // would look like:
963  // LJTI_0_0:
964  // .word (LBB0 - LJTI_0_0)
965  // .word (LBB1 - LJTI_0_0)
966  const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
967 
968  if (isPositionIndependent() || Subtarget->isROPI())
969  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
970  OutContext),
971  OutContext);
972  // If we're generating a table of Thumb addresses in static relocation
973  // model, we need to add one to keep interworking correctly.
974  else if (AFI->isThumbFunction())
976  OutContext);
977  OutStreamer->EmitValue(Expr, 4);
978  }
979  // Mark the end of jump table data-in-code region.
980  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
981 }
982 
984  const MachineOperand &MO1 = MI->getOperand(1);
985  unsigned JTI = MO1.getIndex();
986 
987  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
988  // ARM mode tables.
989  EmitAlignment(Align(4));
990 
991  // Emit a label for the jump table.
992  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
993  OutStreamer->EmitLabel(JTISymbol);
994 
995  // Emit each entry of the table.
996  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
997  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
998  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
999 
1000  for (MachineBasicBlock *MBB : JTBBs) {
1001  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1002  OutContext);
1003  // If this isn't a TBB or TBH, the entries are direct branch instructions.
1005  .addExpr(MBBSymbolExpr)
1006  .addImm(ARMCC::AL)
1007  .addReg(0));
1008  }
1009 }
1010 
1012  unsigned OffsetWidth) {
1013  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1014  const MachineOperand &MO1 = MI->getOperand(1);
1015  unsigned JTI = MO1.getIndex();
1016 
1017  if (Subtarget->isThumb1Only())
1018  EmitAlignment(Align(4));
1019 
1020  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1021  OutStreamer->EmitLabel(JTISymbol);
1022 
1023  // Emit each entry of the table.
1024  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1025  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1026  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1027 
1028  // Mark the jump table as data-in-code.
1029  OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1031 
1032  for (auto MBB : JTBBs) {
1033  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1034  OutContext);
1035  // Otherwise it's an offset from the dispatch instruction. Construct an
1036  // MCExpr for the entry. We want a value of the form:
1037  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1038  //
1039  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1040  // would look like:
1041  // LJTI_0_0:
1042  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1043  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1044  // where LCPI0_0 is a label defined just before the TBB instruction using
1045  // this table.
1046  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1047  const MCExpr *Expr = MCBinaryExpr::createAdd(
1050  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1052  OutContext);
1053  OutStreamer->EmitValue(Expr, OffsetWidth);
1054  }
1055  // Mark the end of jump table data-in-code region. 32-bit offsets use
1056  // actual branch instructions here, so we don't mark those as a data-region
1057  // at all.
1058  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1059 
1060  // Make sure the next instruction is 2-byte aligned.
1061  EmitAlignment(Align(2));
1062 }
1063 
1064 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1066  "Only instruction which are involved into frame setup code are allowed");
1067 
1068  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1069  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1070  const MachineFunction &MF = *MI->getParent()->getParent();
1071  const TargetRegisterInfo *TargetRegInfo =
1073  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1074 
1075  Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1076  unsigned Opc = MI->getOpcode();
1077  unsigned SrcReg, DstReg;
1078 
1079  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1080  // Two special cases:
1081  // 1) tPUSH does not have src/dst regs.
1082  // 2) for Thumb1 code we sometimes materialize the constant via constpool
1083  // load. Yes, this is pretty fragile, but for now I don't see better
1084  // way... :(
1085  SrcReg = DstReg = ARM::SP;
1086  } else {
1087  SrcReg = MI->getOperand(1).getReg();
1088  DstReg = MI->getOperand(0).getReg();
1089  }
1090 
1091  // Try to figure out the unwinding opcode out of src / dst regs.
1092  if (MI->mayStore()) {
1093  // Register saves.
1094  assert(DstReg == ARM::SP &&
1095  "Only stack pointer as a destination reg is supported");
1096 
1097  SmallVector<unsigned, 4> RegList;
1098  // Skip src & dst reg, and pred ops.
1099  unsigned StartOp = 2 + 2;
1100  // Use all the operands.
1101  unsigned NumOffset = 0;
1102  // Amount of SP adjustment folded into a push.
1103  unsigned Pad = 0;
1104 
1105  switch (Opc) {
1106  default:
1107  MI->print(errs());
1108  llvm_unreachable("Unsupported opcode for unwinding information");
1109  case ARM::tPUSH:
1110  // Special case here: no src & dst reg, but two extra imp ops.
1111  StartOp = 2; NumOffset = 2;
1113  case ARM::STMDB_UPD:
1114  case ARM::t2STMDB_UPD:
1115  case ARM::VSTMDDB_UPD:
1116  assert(SrcReg == ARM::SP &&
1117  "Only stack pointer as a source reg is supported");
1118  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1119  i != NumOps; ++i) {
1120  const MachineOperand &MO = MI->getOperand(i);
1121  // Actually, there should never be any impdef stuff here. Skip it
1122  // temporary to workaround PR11902.
1123  if (MO.isImplicit())
1124  continue;
1125  // Registers, pushed as a part of folding an SP update into the
1126  // push instruction are marked as undef and should not be
1127  // restored when unwinding, because the function can modify the
1128  // corresponding stack slots.
1129  if (MO.isUndef()) {
1130  assert(RegList.empty() &&
1131  "Pad registers must come before restored ones");
1132  unsigned Width =
1133  TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1134  Pad += Width;
1135  continue;
1136  }
1137  // Check for registers that are remapped (for a Thumb1 prologue that
1138  // saves high registers).
1139  Register Reg = MO.getReg();
1140  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1141  Reg = RemappedReg;
1142  RegList.push_back(Reg);
1143  }
1144  break;
1145  case ARM::STR_PRE_IMM:
1146  case ARM::STR_PRE_REG:
1147  case ARM::t2STR_PRE:
1148  assert(MI->getOperand(2).getReg() == ARM::SP &&
1149  "Only stack pointer as a source reg is supported");
1150  RegList.push_back(SrcReg);
1151  break;
1152  }
1154  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1155  // Account for the SP adjustment, folded into the push.
1156  if (Pad)
1157  ATS.emitPad(Pad);
1158  }
1159  } else {
1160  // Changes of stack / frame pointer.
1161  if (SrcReg == ARM::SP) {
1162  int64_t Offset = 0;
1163  switch (Opc) {
1164  default:
1165  MI->print(errs());
1166  llvm_unreachable("Unsupported opcode for unwinding information");
1167  case ARM::MOVr:
1168  case ARM::tMOVr:
1169  Offset = 0;
1170  break;
1171  case ARM::ADDri:
1172  case ARM::t2ADDri:
1173  Offset = -MI->getOperand(2).getImm();
1174  break;
1175  case ARM::SUBri:
1176  case ARM::t2SUBri:
1177  Offset = MI->getOperand(2).getImm();
1178  break;
1179  case ARM::tSUBspi:
1180  Offset = MI->getOperand(2).getImm()*4;
1181  break;
1182  case ARM::tADDspi:
1183  case ARM::tADDrSPi:
1184  Offset = -MI->getOperand(2).getImm()*4;
1185  break;
1186  case ARM::tLDRpci: {
1187  // Grab the constpool index and check, whether it corresponds to
1188  // original or cloned constpool entry.
1189  unsigned CPI = MI->getOperand(1).getIndex();
1190  const MachineConstantPool *MCP = MF.getConstantPool();
1191  if (CPI >= MCP->getConstants().size())
1192  CPI = AFI->getOriginalCPIdx(CPI);
1193  assert(CPI != -1U && "Invalid constpool index");
1194 
1195  // Derive the actual offset.
1196  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1197  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1198  // FIXME: Check for user, it should be "add" instruction!
1199  Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1200  break;
1201  }
1202  }
1203 
1205  if (DstReg == FramePtr && FramePtr != ARM::SP)
1206  // Set-up of the frame pointer. Positive values correspond to "add"
1207  // instruction.
1208  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1209  else if (DstReg == ARM::SP) {
1210  // Change of SP by an offset. Positive values correspond to "sub"
1211  // instruction.
1212  ATS.emitPad(Offset);
1213  } else {
1214  // Move of SP to a register. Positive values correspond to an "add"
1215  // instruction.
1216  ATS.emitMovSP(DstReg, -Offset);
1217  }
1218  }
1219  } else if (DstReg == ARM::SP) {
1220  MI->print(errs());
1221  llvm_unreachable("Unsupported opcode for unwinding information");
1222  } else if (Opc == ARM::tMOVr) {
1223  // If a Thumb1 function spills r8-r11, we copy the values to low
1224  // registers before pushing them. Record the copy so we can emit the
1225  // correct ".save" later.
1226  AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1227  } else {
1228  MI->print(errs());
1229  llvm_unreachable("Unsupported opcode for unwinding information");
1230  }
1231  }
1232 }
1233 
1234 // Simple pseudo-instructions have their lowering (with expansion to real
1235 // instructions) auto-generated.
1236 #include "ARMGenMCPseudoLowering.inc"
1237 
1239  const DataLayout &DL = getDataLayout();
1240  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1241  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1242 
1243  const MachineFunction &MF = *MI->getParent()->getParent();
1244  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1245  unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1246 
1247  // If we just ended a constant pool, mark it as such.
1248  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1249  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1250  InConstantPool = false;
1251  }
1252 
1253  // Emit unwinding stuff for frame-related instructions
1254  if (Subtarget->isTargetEHABICompatible() &&
1256  EmitUnwindingInstruction(MI);
1257 
1258  // Do any auto-generated pseudo lowerings.
1259  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1260  return;
1261 
1263  "Pseudo flag setting opcode should be expanded early");
1264 
1265  // Check for manual lowerings.
1266  unsigned Opc = MI->getOpcode();
1267  switch (Opc) {
1268  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1269  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1270  case ARM::LEApcrel:
1271  case ARM::tLEApcrel:
1272  case ARM::t2LEApcrel: {
1273  // FIXME: Need to also handle globals and externals
1274  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1276  ARM::t2LEApcrel ? ARM::t2ADR
1277  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1278  : ARM::ADR))
1279  .addReg(MI->getOperand(0).getReg())
1280  .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1281  // Add predicate operands.
1282  .addImm(MI->getOperand(2).getImm())
1283  .addReg(MI->getOperand(3).getReg()));
1284  return;
1285  }
1286  case ARM::LEApcrelJT:
1287  case ARM::tLEApcrelJT:
1288  case ARM::t2LEApcrelJT: {
1289  MCSymbol *JTIPICSymbol =
1290  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1292  ARM::t2LEApcrelJT ? ARM::t2ADR
1293  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1294  : ARM::ADR))
1295  .addReg(MI->getOperand(0).getReg())
1296  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1297  // Add predicate operands.
1298  .addImm(MI->getOperand(2).getImm())
1299  .addReg(MI->getOperand(3).getReg()));
1300  return;
1301  }
1302  // Darwin call instructions are just normal call instructions with different
1303  // clobber semantics (they clobber R9).
1304  case ARM::BX_CALL: {
1306  .addReg(ARM::LR)
1307  .addReg(ARM::PC)
1308  // Add predicate operands.
1309  .addImm(ARMCC::AL)
1310  .addReg(0)
1311  // Add 's' bit operand (always reg0 for this)
1312  .addReg(0));
1313 
1314  assert(Subtarget->hasV4TOps());
1316  .addReg(MI->getOperand(0).getReg()));
1317  return;
1318  }
1319  case ARM::tBX_CALL: {
1320  if (Subtarget->hasV5TOps())
1321  llvm_unreachable("Expected BLX to be selected for v5t+");
1322 
1323  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1324  // that the saved lr has its LSB set correctly (the arch doesn't
1325  // have blx).
1326  // So here we generate a bl to a small jump pad that does bx rN.
1327  // The jump pads are emitted after the function body.
1328 
1329  Register TReg = MI->getOperand(0).getReg();
1330  MCSymbol *TRegSym = nullptr;
1331  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1332  if (TIP.first == TReg) {
1333  TRegSym = TIP.second;
1334  break;
1335  }
1336  }
1337 
1338  if (!TRegSym) {
1339  TRegSym = OutContext.createTempSymbol();
1340  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1341  }
1342 
1343  // Create a link-saving branch to the Reg Indirect Jump Pad.
1345  // Predicate comes first here.
1346  .addImm(ARMCC::AL).addReg(0)
1347  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1348  return;
1349  }
1350  case ARM::BMOVPCRX_CALL: {
1352  .addReg(ARM::LR)
1353  .addReg(ARM::PC)
1354  // Add predicate operands.
1355  .addImm(ARMCC::AL)
1356  .addReg(0)
1357  // Add 's' bit operand (always reg0 for this)
1358  .addReg(0));
1359 
1361  .addReg(ARM::PC)
1362  .addReg(MI->getOperand(0).getReg())
1363  // Add predicate operands.
1364  .addImm(ARMCC::AL)
1365  .addReg(0)
1366  // Add 's' bit operand (always reg0 for this)
1367  .addReg(0));
1368  return;
1369  }
1370  case ARM::BMOVPCB_CALL: {
1372  .addReg(ARM::LR)
1373  .addReg(ARM::PC)
1374  // Add predicate operands.
1375  .addImm(ARMCC::AL)
1376  .addReg(0)
1377  // Add 's' bit operand (always reg0 for this)
1378  .addReg(0));
1379 
1380  const MachineOperand &Op = MI->getOperand(0);
1381  const GlobalValue *GV = Op.getGlobal();
1382  const unsigned TF = Op.getTargetFlags();
1383  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1384  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1386  .addExpr(GVSymExpr)
1387  // Add predicate operands.
1388  .addImm(ARMCC::AL)
1389  .addReg(0));
1390  return;
1391  }
1392  case ARM::MOVi16_ga_pcrel:
1393  case ARM::t2MOVi16_ga_pcrel: {
1394  MCInst TmpInst;
1395  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1396  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1397 
1398  unsigned TF = MI->getOperand(1).getTargetFlags();
1399  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1400  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1401  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1402 
1403  MCSymbol *LabelSym =
1405  MI->getOperand(2).getImm(), OutContext);
1406  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1407  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1408  const MCExpr *PCRelExpr =
1410  MCBinaryExpr::createAdd(LabelSymExpr,
1413  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1414 
1415  // Add predicate operands.
1417  TmpInst.addOperand(MCOperand::createReg(0));
1418  // Add 's' bit operand (always reg0 for this)
1419  TmpInst.addOperand(MCOperand::createReg(0));
1420  EmitToStreamer(*OutStreamer, TmpInst);
1421  return;
1422  }
1423  case ARM::MOVTi16_ga_pcrel:
1424  case ARM::t2MOVTi16_ga_pcrel: {
1425  MCInst TmpInst;
1426  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1427  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1428  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1429  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1430 
1431  unsigned TF = MI->getOperand(2).getTargetFlags();
1432  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1433  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1434  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1435 
1436  MCSymbol *LabelSym =
1438  MI->getOperand(3).getImm(), OutContext);
1439  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1440  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1441  const MCExpr *PCRelExpr =
1443  MCBinaryExpr::createAdd(LabelSymExpr,
1446  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1447  // Add predicate operands.
1449  TmpInst.addOperand(MCOperand::createReg(0));
1450  // Add 's' bit operand (always reg0 for this)
1451  TmpInst.addOperand(MCOperand::createReg(0));
1452  EmitToStreamer(*OutStreamer, TmpInst);
1453  return;
1454  }
1455  case ARM::t2BFi:
1456  case ARM::t2BFic:
1457  case ARM::t2BFLi:
1458  case ARM::t2BFr:
1459  case ARM::t2BFLr: {
1460  // This is a Branch Future instruction.
1461 
1462  const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1464  MI->getOperand(0).getIndex(), OutContext),
1465  OutContext);
1466 
1467  auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1468  if (MI->getOperand(1).isReg()) {
1469  // For BFr/BFLr
1470  MCInst.addReg(MI->getOperand(1).getReg());
1471  } else {
1472  // For BFi/BFLi/BFic
1473  const MCExpr *BranchTarget;
1474  if (MI->getOperand(1).isMBB())
1475  BranchTarget = MCSymbolRefExpr::create(
1476  MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1477  else if (MI->getOperand(1).isGlobal()) {
1478  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1479  BranchTarget = MCSymbolRefExpr::create(
1480  GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1481  } else if (MI->getOperand(1).isSymbol()) {
1482  BranchTarget = MCSymbolRefExpr::create(
1484  OutContext);
1485  } else
1486  llvm_unreachable("Unhandled operand kind in Branch Future instruction");
1487 
1488  MCInst.addExpr(BranchTarget);
1489  }
1490 
1491  if (Opc == ARM::t2BFic) {
1492  const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1494  MI->getOperand(2).getIndex(), OutContext),
1495  OutContext);
1496  MCInst.addExpr(ElseLabel);
1497  MCInst.addImm(MI->getOperand(3).getImm());
1498  } else {
1499  MCInst.addImm(MI->getOperand(2).getImm())
1500  .addReg(MI->getOperand(3).getReg());
1501  }
1502 
1504  return;
1505  }
1506  case ARM::t2BF_LabelPseudo: {
1507  // This is a pseudo op for a label used by a branch future instruction
1508 
1509  // Emit the label.
1512  MI->getOperand(0).getIndex(), OutContext));
1513  return;
1514  }
1515  case ARM::tPICADD: {
1516  // This is a pseudo op for a label + instruction sequence, which looks like:
1517  // LPC0:
1518  // add r0, pc
1519  // This adds the address of LPC0 to r0.
1520 
1521  // Emit the label.
1524  MI->getOperand(2).getImm(), OutContext));
1525 
1526  // Form and emit the add.
1527  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1528  .addReg(MI->getOperand(0).getReg())
1529  .addReg(MI->getOperand(0).getReg())
1530  .addReg(ARM::PC)
1531  // Add predicate operands.
1532  .addImm(ARMCC::AL)
1533  .addReg(0));
1534  return;
1535  }
1536  case ARM::PICADD: {
1537  // This is a pseudo op for a label + instruction sequence, which looks like:
1538  // LPC0:
1539  // add r0, pc, r0
1540  // This adds the address of LPC0 to r0.
1541 
1542  // Emit the label.
1545  MI->getOperand(2).getImm(), OutContext));
1546 
1547  // Form and emit the add.
1549  .addReg(MI->getOperand(0).getReg())
1550  .addReg(ARM::PC)
1551  .addReg(MI->getOperand(1).getReg())
1552  // Add predicate operands.
1553  .addImm(MI->getOperand(3).getImm())
1554  .addReg(MI->getOperand(4).getReg())
1555  // Add 's' bit operand (always reg0 for this)
1556  .addReg(0));
1557  return;
1558  }
1559  case ARM::PICSTR:
1560  case ARM::PICSTRB:
1561  case ARM::PICSTRH:
1562  case ARM::PICLDR:
1563  case ARM::PICLDRB:
1564  case ARM::PICLDRH:
1565  case ARM::PICLDRSB:
1566  case ARM::PICLDRSH: {
1567  // This is a pseudo op for a label + instruction sequence, which looks like:
1568  // LPC0:
1569  // OP r0, [pc, r0]
1570  // The LCP0 label is referenced by a constant pool entry in order to get
1571  // a PC-relative address at the ldr instruction.
1572 
1573  // Emit the label.
1576  MI->getOperand(2).getImm(), OutContext));
1577 
1578  // Form and emit the load
1579  unsigned Opcode;
1580  switch (MI->getOpcode()) {
1581  default:
1582  llvm_unreachable("Unexpected opcode!");
1583  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1584  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1585  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1586  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1587  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1588  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1589  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1590  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1591  }
1593  .addReg(MI->getOperand(0).getReg())
1594  .addReg(ARM::PC)
1595  .addReg(MI->getOperand(1).getReg())
1596  .addImm(0)
1597  // Add predicate operands.
1598  .addImm(MI->getOperand(3).getImm())
1599  .addReg(MI->getOperand(4).getReg()));
1600 
1601  return;
1602  }
1603  case ARM::CONSTPOOL_ENTRY: {
1604  if (Subtarget->genExecuteOnly())
1605  llvm_unreachable("execute-only should not generate constant pools");
1606 
1607  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1608  /// in the function. The first operand is the ID# for this instruction, the
1609  /// second is the index into the MachineConstantPool that this is, the third
1610  /// is the size in bytes of this constant pool entry.
1611  /// The required alignment is specified on the basic block holding this MI.
1612  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1613  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1614 
1615  // If this is the first entry of the pool, mark it.
1616  if (!InConstantPool) {
1617  OutStreamer->EmitDataRegion(MCDR_DataRegion);
1618  InConstantPool = true;
1619  }
1620 
1621  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1622 
1623  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1624  if (MCPE.isMachineConstantPoolEntry())
1626  else
1627  EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1628  return;
1629  }
1630  case ARM::JUMPTABLE_ADDRS:
1631  EmitJumpTableAddrs(MI);
1632  return;
1633  case ARM::JUMPTABLE_INSTS:
1634  EmitJumpTableInsts(MI);
1635  return;
1636  case ARM::JUMPTABLE_TBB:
1637  case ARM::JUMPTABLE_TBH:
1638  EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1639  return;
1640  case ARM::t2BR_JT: {
1642  .addReg(ARM::PC)
1643  .addReg(MI->getOperand(0).getReg())
1644  // Add predicate operands.
1645  .addImm(ARMCC::AL)
1646  .addReg(0));
1647  return;
1648  }
1649  case ARM::t2TBB_JT:
1650  case ARM::t2TBH_JT: {
1651  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1652  // Lower and emit the PC label, then the instruction itself.
1653  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1655  .addReg(MI->getOperand(0).getReg())
1656  .addReg(MI->getOperand(1).getReg())
1657  // Add predicate operands.
1658  .addImm(ARMCC::AL)
1659  .addReg(0));
1660  return;
1661  }
1662  case ARM::tTBB_JT:
1663  case ARM::tTBH_JT: {
1664 
1665  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1666  Register Base = MI->getOperand(0).getReg();
1667  Register Idx = MI->getOperand(1).getReg();
1668  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1669 
1670  // Multiply up idx if necessary.
1671  if (!Is8Bit)
1673  .addReg(Idx)
1674  .addReg(ARM::CPSR)
1675  .addReg(Idx)
1676  .addImm(1)
1677  // Add predicate operands.
1678  .addImm(ARMCC::AL)
1679  .addReg(0));
1680 
1681  if (Base == ARM::PC) {
1682  // TBB [base, idx] =
1683  // ADDS idx, idx, base
1684  // LDRB idx, [idx, #4] ; or LDRH if TBH
1685  // LSLS idx, #1
1686  // ADDS pc, pc, idx
1687 
1688  // When using PC as the base, it's important that there is no padding
1689  // between the last ADDS and the start of the jump table. The jump table
1690  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1691  //
1692  // FIXME: Ideally we could vary the LDRB index based on the padding
1693  // between the sequence and jump table, however that relies on MCExprs
1694  // for load indexes which are currently not supported.
1695  OutStreamer->EmitCodeAlignment(4);
1696  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1697  .addReg(Idx)
1698  .addReg(Idx)
1699  .addReg(Base)
1700  // Add predicate operands.
1701  .addImm(ARMCC::AL)
1702  .addReg(0));
1703 
1704  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1706  .addReg(Idx)
1707  .addReg(Idx)
1708  .addImm(Is8Bit ? 4 : 2)
1709  // Add predicate operands.
1710  .addImm(ARMCC::AL)
1711  .addReg(0));
1712  } else {
1713  // TBB [base, idx] =
1714  // LDRB idx, [base, idx] ; or LDRH if TBH
1715  // LSLS idx, #1
1716  // ADDS pc, pc, idx
1717 
1718  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1720  .addReg(Idx)
1721  .addReg(Base)
1722  .addReg(Idx)
1723  // Add predicate operands.
1724  .addImm(ARMCC::AL)
1725  .addReg(0));
1726  }
1727 
1729  .addReg(Idx)
1730  .addReg(ARM::CPSR)
1731  .addReg(Idx)
1732  .addImm(1)
1733  // Add predicate operands.
1734  .addImm(ARMCC::AL)
1735  .addReg(0));
1736 
1737  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1738  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1739  .addReg(ARM::PC)
1740  .addReg(ARM::PC)
1741  .addReg(Idx)
1742  // Add predicate operands.
1743  .addImm(ARMCC::AL)
1744  .addReg(0));
1745  return;
1746  }
1747  case ARM::tBR_JTr:
1748  case ARM::BR_JTr: {
1749  // mov pc, target
1750  MCInst TmpInst;
1751  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1752  ARM::MOVr : ARM::tMOVr;
1753  TmpInst.setOpcode(Opc);
1754  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1755  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1756  // Add predicate operands.
1758  TmpInst.addOperand(MCOperand::createReg(0));
1759  // Add 's' bit operand (always reg0 for this)
1760  if (Opc == ARM::MOVr)
1761  TmpInst.addOperand(MCOperand::createReg(0));
1762  EmitToStreamer(*OutStreamer, TmpInst);
1763  return;
1764  }
1765  case ARM::BR_JTm_i12: {
1766  // ldr pc, target
1767  MCInst TmpInst;
1768  TmpInst.setOpcode(ARM::LDRi12);
1769  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1770  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1771  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1772  // Add predicate operands.
1774  TmpInst.addOperand(MCOperand::createReg(0));
1775  EmitToStreamer(*OutStreamer, TmpInst);
1776  return;
1777  }
1778  case ARM::BR_JTm_rs: {
1779  // ldr pc, target
1780  MCInst TmpInst;
1781  TmpInst.setOpcode(ARM::LDRrs);
1782  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1783  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1784  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1785  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1786  // Add predicate operands.
1788  TmpInst.addOperand(MCOperand::createReg(0));
1789  EmitToStreamer(*OutStreamer, TmpInst);
1790  return;
1791  }
1792  case ARM::BR_JTadd: {
1793  // add pc, target, idx
1795  .addReg(ARM::PC)
1796  .addReg(MI->getOperand(0).getReg())
1797  .addReg(MI->getOperand(1).getReg())
1798  // Add predicate operands.
1799  .addImm(ARMCC::AL)
1800  .addReg(0)
1801  // Add 's' bit operand (always reg0 for this)
1802  .addReg(0));
1803  return;
1804  }
1805  case ARM::SPACE:
1806  OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1807  return;
1808  case ARM::TRAP: {
1809  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1810  // FIXME: Remove this special case when they do.
1811  if (!Subtarget->isTargetMachO()) {
1812  uint32_t Val = 0xe7ffdefeUL;
1813  OutStreamer->AddComment("trap");
1814  ATS.emitInst(Val);
1815  return;
1816  }
1817  break;
1818  }
1819  case ARM::TRAPNaCl: {
1820  uint32_t Val = 0xe7fedef0UL;
1821  OutStreamer->AddComment("trap");
1822  ATS.emitInst(Val);
1823  return;
1824  }
1825  case ARM::tTRAP: {
1826  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1827  // FIXME: Remove this special case when they do.
1828  if (!Subtarget->isTargetMachO()) {
1829  uint16_t Val = 0xdefe;
1830  OutStreamer->AddComment("trap");
1831  ATS.emitInst(Val, 'n');
1832  return;
1833  }
1834  break;
1835  }
1836  case ARM::t2Int_eh_sjlj_setjmp:
1837  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1838  case ARM::tInt_eh_sjlj_setjmp: {
1839  // Two incoming args: GPR:$src, GPR:$val
1840  // mov $val, pc
1841  // adds $val, #7
1842  // str $val, [$src, #4]
1843  // movs r0, #0
1844  // b LSJLJEH
1845  // movs r0, #1
1846  // LSJLJEH:
1847  Register SrcReg = MI->getOperand(0).getReg();
1848  Register ValReg = MI->getOperand(1).getReg();
1849  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1850  OutStreamer->AddComment("eh_setjmp begin");
1852  .addReg(ValReg)
1853  .addReg(ARM::PC)
1854  // Predicate.
1855  .addImm(ARMCC::AL)
1856  .addReg(0));
1857 
1859  .addReg(ValReg)
1860  // 's' bit operand
1861  .addReg(ARM::CPSR)
1862  .addReg(ValReg)
1863  .addImm(7)
1864  // Predicate.
1865  .addImm(ARMCC::AL)
1866  .addReg(0));
1867 
1869  .addReg(ValReg)
1870  .addReg(SrcReg)
1871  // The offset immediate is #4. The operand value is scaled by 4 for the
1872  // tSTR instruction.
1873  .addImm(1)
1874  // Predicate.
1875  .addImm(ARMCC::AL)
1876  .addReg(0));
1877 
1879  .addReg(ARM::R0)
1880  .addReg(ARM::CPSR)
1881  .addImm(0)
1882  // Predicate.
1883  .addImm(ARMCC::AL)
1884  .addReg(0));
1885 
1886  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1888  .addExpr(SymbolExpr)
1889  .addImm(ARMCC::AL)
1890  .addReg(0));
1891 
1892  OutStreamer->AddComment("eh_setjmp end");
1894  .addReg(ARM::R0)
1895  .addReg(ARM::CPSR)
1896  .addImm(1)
1897  // Predicate.
1898  .addImm(ARMCC::AL)
1899  .addReg(0));
1900 
1901  OutStreamer->EmitLabel(Label);
1902  return;
1903  }
1904 
1905  case ARM::Int_eh_sjlj_setjmp_nofp:
1906  case ARM::Int_eh_sjlj_setjmp: {
1907  // Two incoming args: GPR:$src, GPR:$val
1908  // add $val, pc, #8
1909  // str $val, [$src, #+4]
1910  // mov r0, #0
1911  // add pc, pc, #0
1912  // mov r0, #1
1913  Register SrcReg = MI->getOperand(0).getReg();
1914  Register ValReg = MI->getOperand(1).getReg();
1915 
1916  OutStreamer->AddComment("eh_setjmp begin");
1918  .addReg(ValReg)
1919  .addReg(ARM::PC)
1920  .addImm(8)
1921  // Predicate.
1922  .addImm(ARMCC::AL)
1923  .addReg(0)
1924  // 's' bit operand (always reg0 for this).
1925  .addReg(0));
1926 
1928  .addReg(ValReg)
1929  .addReg(SrcReg)
1930  .addImm(4)
1931  // Predicate.
1932  .addImm(ARMCC::AL)
1933  .addReg(0));
1934 
1936  .addReg(ARM::R0)
1937  .addImm(0)
1938  // Predicate.
1939  .addImm(ARMCC::AL)
1940  .addReg(0)
1941  // 's' bit operand (always reg0 for this).
1942  .addReg(0));
1943 
1945  .addReg(ARM::PC)
1946  .addReg(ARM::PC)
1947  .addImm(0)
1948  // Predicate.
1949  .addImm(ARMCC::AL)
1950  .addReg(0)
1951  // 's' bit operand (always reg0 for this).
1952  .addReg(0));
1953 
1954  OutStreamer->AddComment("eh_setjmp end");
1956  .addReg(ARM::R0)
1957  .addImm(1)
1958  // Predicate.
1959  .addImm(ARMCC::AL)
1960  .addReg(0)
1961  // 's' bit operand (always reg0 for this).
1962  .addReg(0));
1963  return;
1964  }
1965  case ARM::Int_eh_sjlj_longjmp: {
1966  // ldr sp, [$src, #8]
1967  // ldr $scratch, [$src, #4]
1968  // ldr r7, [$src]
1969  // bx $scratch
1970  Register SrcReg = MI->getOperand(0).getReg();
1971  Register ScratchReg = MI->getOperand(1).getReg();
1973  .addReg(ARM::SP)
1974  .addReg(SrcReg)
1975  .addImm(8)
1976  // Predicate.
1977  .addImm(ARMCC::AL)
1978  .addReg(0));
1979 
1981  .addReg(ScratchReg)
1982  .addReg(SrcReg)
1983  .addImm(4)
1984  // Predicate.
1985  .addImm(ARMCC::AL)
1986  .addReg(0));
1987 
1988  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1989  // These platforms always use the same frame register
1991  .addReg(FramePtr)
1992  .addReg(SrcReg)
1993  .addImm(0)
1994  // Predicate.
1995  .addImm(ARMCC::AL)
1996  .addReg(0));
1997  } else {
1998  // If the calling code might use either R7 or R11 as
1999  // frame pointer register, restore it into both.
2001  .addReg(ARM::R7)
2002  .addReg(SrcReg)
2003  .addImm(0)
2004  // Predicate.
2005  .addImm(ARMCC::AL)
2006  .addReg(0));
2008  .addReg(ARM::R11)
2009  .addReg(SrcReg)
2010  .addImm(0)
2011  // Predicate.
2012  .addImm(ARMCC::AL)
2013  .addReg(0));
2014  }
2015 
2016  assert(Subtarget->hasV4TOps());
2018  .addReg(ScratchReg)
2019  // Predicate.
2020  .addImm(ARMCC::AL)
2021  .addReg(0));
2022  return;
2023  }
2024  case ARM::tInt_eh_sjlj_longjmp: {
2025  // ldr $scratch, [$src, #8]
2026  // mov sp, $scratch
2027  // ldr $scratch, [$src, #4]
2028  // ldr r7, [$src]
2029  // bx $scratch
2030  Register SrcReg = MI->getOperand(0).getReg();
2031  Register ScratchReg = MI->getOperand(1).getReg();
2032 
2034  .addReg(ScratchReg)
2035  .addReg(SrcReg)
2036  // The offset immediate is #8. The operand value is scaled by 4 for the
2037  // tLDR instruction.
2038  .addImm(2)
2039  // Predicate.
2040  .addImm(ARMCC::AL)
2041  .addReg(0));
2042 
2044  .addReg(ARM::SP)
2045  .addReg(ScratchReg)
2046  // Predicate.
2047  .addImm(ARMCC::AL)
2048  .addReg(0));
2049 
2051  .addReg(ScratchReg)
2052  .addReg(SrcReg)
2053  .addImm(1)
2054  // Predicate.
2055  .addImm(ARMCC::AL)
2056  .addReg(0));
2057 
2058  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2059  // These platforms always use the same frame register
2061  .addReg(FramePtr)
2062  .addReg(SrcReg)
2063  .addImm(0)
2064  // Predicate.
2065  .addImm(ARMCC::AL)
2066  .addReg(0));
2067  } else {
2068  // If the calling code might use either R7 or R11 as
2069  // frame pointer register, restore it into both.
2071  .addReg(ARM::R7)
2072  .addReg(SrcReg)
2073  .addImm(0)
2074  // Predicate.
2075  .addImm(ARMCC::AL)
2076  .addReg(0));
2078  .addReg(ARM::R11)
2079  .addReg(SrcReg)
2080  .addImm(0)
2081  // Predicate.
2082  .addImm(ARMCC::AL)
2083  .addReg(0));
2084  }
2085 
2087  .addReg(ScratchReg)
2088  // Predicate.
2089  .addImm(ARMCC::AL)
2090  .addReg(0));
2091  return;
2092  }
2093  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2094  // ldr.w r11, [$src, #0]
2095  // ldr.w sp, [$src, #8]
2096  // ldr.w pc, [$src, #4]
2097 
2098  Register SrcReg = MI->getOperand(0).getReg();
2099 
2100  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2101  .addReg(ARM::R11)
2102  .addReg(SrcReg)
2103  .addImm(0)
2104  // Predicate
2105  .addImm(ARMCC::AL)
2106  .addReg(0));
2107  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2108  .addReg(ARM::SP)
2109  .addReg(SrcReg)
2110  .addImm(8)
2111  // Predicate
2112  .addImm(ARMCC::AL)
2113  .addReg(0));
2114  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2115  .addReg(ARM::PC)
2116  .addReg(SrcReg)
2117  .addImm(4)
2118  // Predicate
2119  .addImm(ARMCC::AL)
2120  .addReg(0));
2121  return;
2122  }
2123  case ARM::PATCHABLE_FUNCTION_ENTER:
2125  return;
2126  case ARM::PATCHABLE_FUNCTION_EXIT:
2128  return;
2129  case ARM::PATCHABLE_TAIL_CALL:
2131  return;
2132  }
2133 
2134  MCInst TmpInst;
2135  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2136 
2137  EmitToStreamer(*OutStreamer, TmpInst);
2138 }
2139 
2140 //===----------------------------------------------------------------------===//
2141 // Target Registry Stuff
2142 //===----------------------------------------------------------------------===//
2143 
2144 // Force static initialization.
2145 extern "C" void LLVMInitializeARMAsmPrinter() {
2150 }
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
unsigned getTargetFlags() const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:454
MachineConstantPoolValue * MachineCPVal
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:271
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:216
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
StringRef getTargetFeatureString() const
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:713
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
union llvm::MachineConstantPoolEntry::@168 Val
The constant itself.
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:327
This class represents lattice values for constants.
Definition: AllocatorList.h:23
PointerTy getPointer() const
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:616
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:321
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:622
void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool hasV4TOps() const
Definition: ARMSubtarget.h:567
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void push_back(const T &Elt)
Definition: SmallVector.h:211
ARMConstantPoolValue - ARM specific constantpool value.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
Target specific streamer interface.
Definition: MCStreamer.h:85
unsigned Reg
virtual void emitPad(int64_t Offset)
unsigned getSubReg() const
Global Offset Table, Thread Pointer Offset.
unsigned char getPCAdjustment() const
void EmitAlignment(Align Alignment, const GlobalObject *GV=nullptr) const
Emit an alignment directive to the specified power of two boundary.
bool isTargetCOFF() const
Definition: ARMSubtarget.h:697
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:530
MachineBasicBlock reference.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the EmitInstruction() method to print assembly for each instruction...
virtual void finishAttributeSection()
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isThumb1Only() const
Definition: ARMSubtarget.h:755
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:718
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Global Offset Table, PC Relative.
Thread Pointer Offset.
Target & getTheThumbLETarget()
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
static bool isThumb(const MCSubtargetInfo &STI)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
void LLVMInitializeARMAsmPrinter()
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
return AArch64::GPR64RegClass contains(Reg)
bool genExecuteOnly() const
Definition: ARMSubtarget.h:674
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool isTargetELF() const
Definition: ARMSubtarget.h:698
ARMCP::ARMCPModifier getModifier() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
The address of a basic block.
Definition: Constants.h:839
MCContext & getContext() const
Definition: MCStreamer.h:252
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: ARMBaseInfo.h:259
Definition: BitVector.h:937
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
virtual void emitInst(uint32_t Inst, char Suffix='\0')
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const FeatureBitset & getFeatureBits() const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:475
unsigned SubReg
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
.data_region jt16
Definition: MCDirectives.h:60
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const char * getSymbolName() const
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
Target & getTheARMBETarget()
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Context object for machine code objects.
Definition: MCContext.h:65
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:42
void EmitFunctionBody()
This method emits the body and trailer for a function.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file. ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:550
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:52
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:207
Target & getTheThumbBETarget()
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
IntType getInt() const
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:726
Register getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
bool isTargetDarwin() const
Definition: ARMSubtarget.h:688
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
This class is a data container for one entry in a MachineConstantPool.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
StringRef getTargetCPU() const
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:265
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:465
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:130
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:161
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:99
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:49
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:767
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false)
Definition: MCExpr.cpp:169
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:844
.data_region jt32
Definition: MCDirectives.h:61
Address of a global value.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Streaming machine code generation interface.
Definition: MCStreamer.h:190
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:225
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:112
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
PointerIntPair - This class implements a pair of a pointer and small integer.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:487
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
MCSection * getNonLazySymbolPointerSection() const
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:444
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1172
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
bool hasInternalLinkage() const
Definition: GlobalValue.h:443
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:51
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:799
Thread Local Storage (General Dynamic Mode)
const Triple & getTargetTriple() const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an &#39;S&#39; bit onto real opcodes.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Ty & getObjFileInfo()
Keep track of various per-function pieces of information for backends that would like to do so...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
FPDenormal::DenormalMode FPDenormalMode
FPDenormalMode - This flags specificies which denormal numbers the code is permitted to require...
DenseMap< unsigned, unsigned > EHPrologueRemappedRegs
const Constant * stripPointerCasts() const
Definition: Constant.h:183
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Abstract base class for all machine specific constantpool value subclasses.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:246
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
MCSection * getThreadLocalPointerSection() const
void EmitJumpTableInsts(const MachineInstr *MI)
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:212
void setOpcode(unsigned Op)
Definition: MCInst.h:170
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
bool isTargetAEABI() const
Definition: ARMSubtarget.h:708
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:449
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
.indirect_symbol (MachO)
Definition: MCDirectives.h:33
unsigned getOriginalCPIdx(unsigned CloneIdx) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:235
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:203
StubValueTy & getGVStubEntry(MCSymbol *Sym)
.syntax (ARM/ELF)
Definition: MCDirectives.h:50
MCSymbol * getCurExceptionSym()
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
bool isROPI() const
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:53
FunctionNumber(functionNumber)
Definition: LLParser.cpp:2825
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Section Relative (Windows TLS)
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:694
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:129
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:220
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
TargetOptions Options
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
void EmitJumpTableAddrs(const MachineInstr *MI)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:38
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:619
Generic base class for all target subtargets.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:128
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool hasV5TOps() const
Definition: ARMSubtarget.h:568
Type * getType() const
getType - get type of this MachineConstantPoolValue.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
const Module * getModule() const
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:185
bool isReg() const
isReg - Tests if this is a MO_Register operand.
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
const std::string & getModuleInlineAsm() const
Get any module-scope inline assembly blocks.
Definition: Module.h:248
bool isTargetMachO() const
Definition: ARMSubtarget.h:699
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
.data_region jt8
Definition: MCDirectives.h:59
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:74
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:399
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:284
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:593
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
static const unsigned FramePtr
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool isTargetWindows() const
Definition: ARMSubtarget.h:695
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:220
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:250
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Register getReg() const
getReg - Returns the register number.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
Target & getTheARMLETarget()
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void EmitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:297
.end_data_region
Definition: MCDirectives.h:62
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:250
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isImplicit() const
virtual void switchVendor(StringRef Vendor)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
A function that returns a base type.
Definition: COFF.h:261