LLVM  9.0.0svn
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/BinaryFormat/COFF.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Mangler.h"
32 #include "llvm/IR/Module.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCELFStreamer.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Support/Debug.h"
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "asm-printer"
53 
55  std::unique_ptr<MCStreamer> Streamer)
56  : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
57  InConstantPool(false), OptimizationGoals(-1) {}
58 
60  // Make sure to terminate any constant pools that were at the end
61  // of the function.
62  if (!InConstantPool)
63  return;
64  InConstantPool = false;
65  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
66 }
67 
69  if (AFI->isThumbFunction()) {
70  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
71  OutStreamer->EmitThumbFunc(CurrentFnSym);
72  } else {
73  OutStreamer->EmitAssemblerFlag(MCAF_Code32);
74  }
75  OutStreamer->EmitLabel(CurrentFnSym);
76 }
77 
79  uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
80  assert(Size && "C++ constructor pointer had zero size!");
81 
83  assert(GV && "C++ constructor pointer was not a GlobalValue!");
84 
85  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
87  (Subtarget->isTargetELF()
90  OutContext);
91 
92  OutStreamer->EmitValue(E, Size);
93 }
94 
96  if (PromotedGlobals.count(GV))
97  // The global was promoted into a constant pool. It should not be emitted.
98  return;
100 }
101 
102 /// runOnMachineFunction - This uses the EmitInstruction()
103 /// method to print assembly for each instruction.
104 ///
106  AFI = MF.getInfo<ARMFunctionInfo>();
107  MCP = MF.getConstantPool();
108  Subtarget = &MF.getSubtarget<ARMSubtarget>();
109 
111  const Function &F = MF.getFunction();
112  const TargetMachine& TM = MF.getTarget();
113 
114  // Collect all globals that had their storage promoted to a constant pool.
115  // Functions are emitted before variables, so this accumulates promoted
116  // globals from all functions in PromotedGlobals.
117  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
118  PromotedGlobals.insert(GV);
119 
120  // Calculate this function's optimization goal.
121  unsigned OptimizationGoal;
122  if (F.hasOptNone())
123  // For best debugging illusion, speed and small size sacrificed
124  OptimizationGoal = 6;
125  else if (F.hasMinSize())
126  // Aggressively for small size, speed and debug illusion sacrificed
127  OptimizationGoal = 4;
128  else if (F.hasOptSize())
129  // For small size, but speed and debugging illusion preserved
130  OptimizationGoal = 3;
131  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
132  // Aggressively for speed, small size and debug illusion sacrificed
133  OptimizationGoal = 2;
134  else if (TM.getOptLevel() > CodeGenOpt::None)
135  // For speed, but small size and good debug illusion preserved
136  OptimizationGoal = 1;
137  else // TM.getOptLevel() == CodeGenOpt::None
138  // For good debugging, but speed and small size preserved
139  OptimizationGoal = 5;
140 
141  // Combine a new optimization goal with existing ones.
142  if (OptimizationGoals == -1) // uninitialized goals
143  OptimizationGoals = OptimizationGoal;
144  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
145  OptimizationGoals = 0;
146 
147  if (Subtarget->isTargetCOFF()) {
148  bool Internal = F.hasInternalLinkage();
152 
153  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
154  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
155  OutStreamer->EmitCOFFSymbolType(Type);
156  OutStreamer->EndCOFFSymbolDef();
157  }
158 
159  // Emit the rest of the function body.
161 
162  // Emit the XRay table for this function.
163  emitXRayTable();
164 
165  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
166  // These are created per function, rather than per TU, since it's
167  // relatively easy to exceed the thumb branch range within a TU.
168  if (! ThumbIndirectPads.empty()) {
169  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
170  EmitAlignment(1);
171  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
172  OutStreamer->EmitLabel(TIP.second);
174  .addReg(TIP.first)
175  // Add predicate operands.
176  .addImm(ARMCC::AL)
177  .addReg(0));
178  }
179  ThumbIndirectPads.clear();
180  }
181 
182  // We didn't modify anything.
183  return false;
184 }
185 
187  raw_ostream &O) {
188  const MachineOperand &MO = MI->getOperand(OpNum);
189  unsigned TF = MO.getTargetFlags();
190 
191  switch (MO.getType()) {
192  default: llvm_unreachable("<unknown operand type>");
194  unsigned Reg = MO.getReg();
196  assert(!MO.getSubReg() && "Subregs should be eliminated!");
197  if(ARM::GPRPairRegClass.contains(Reg)) {
198  const MachineFunction &MF = *MI->getParent()->getParent();
200  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
201  }
203  break;
204  }
206  int64_t Imm = MO.getImm();
207  O << '#';
208  if (TF == ARMII::MO_LO16)
209  O << ":lower16:";
210  else if (TF == ARMII::MO_HI16)
211  O << ":upper16:";
212  O << Imm;
213  break;
214  }
216  MO.getMBB()->getSymbol()->print(O, MAI);
217  return;
219  const GlobalValue *GV = MO.getGlobal();
220  if (TF & ARMII::MO_LO16)
221  O << ":lower16:";
222  else if (TF & ARMII::MO_HI16)
223  O << ":upper16:";
224  GetARMGVSymbol(GV, TF)->print(O, MAI);
225 
226  printOffset(MO.getOffset(), O);
227  break;
228  }
230  if (Subtarget->genExecuteOnly())
231  llvm_unreachable("execute-only should not generate constant pools");
232  GetCPISymbol(MO.getIndex())->print(O, MAI);
233  break;
234  }
235 }
236 
237 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
238  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
239  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
240  const DataLayout &DL = getDataLayout();
242  "CPI" + Twine(getFunctionNumber()) + "_" +
243  Twine(CPID));
244 }
245 
246 //===--------------------------------------------------------------------===//
247 
248 MCSymbol *ARMAsmPrinter::
249 GetARMJTIPICJumpTableLabel(unsigned uid) const {
250  const DataLayout &DL = getDataLayout();
252  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
253  << getFunctionNumber() << '_' << uid;
254  return OutContext.getOrCreateSymbol(Name);
255 }
256 
257 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
258  const char *ExtraCode, raw_ostream &O) {
259  // Does this asm operand have a single letter operand modifier?
260  if (ExtraCode && ExtraCode[0]) {
261  if (ExtraCode[1] != 0) return true; // Unknown modifier.
262 
263  switch (ExtraCode[0]) {
264  default:
265  // See if this is a generic print operand
266  return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
267  case 'P': // Print a VFP double precision register.
268  case 'q': // Print a NEON quad precision register.
269  printOperand(MI, OpNum, O);
270  return false;
271  case 'y': // Print a VFP single precision register as indexed double.
272  if (MI->getOperand(OpNum).isReg()) {
273  unsigned Reg = MI->getOperand(OpNum).getReg();
275  // Find the 'd' register that has this 's' register as a sub-register,
276  // and determine the lane number.
277  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
278  if (!ARM::DPRRegClass.contains(*SR))
279  continue;
280  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
281  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
282  return false;
283  }
284  }
285  return true;
286  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
287  if (!MI->getOperand(OpNum).isImm())
288  return true;
289  O << ~(MI->getOperand(OpNum).getImm());
290  return false;
291  case 'L': // The low 16 bits of an immediate constant.
292  if (!MI->getOperand(OpNum).isImm())
293  return true;
294  O << (MI->getOperand(OpNum).getImm() & 0xffff);
295  return false;
296  case 'M': { // A register range suitable for LDM/STM.
297  if (!MI->getOperand(OpNum).isReg())
298  return true;
299  const MachineOperand &MO = MI->getOperand(OpNum);
300  unsigned RegBegin = MO.getReg();
301  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
302  // already got the operands in registers that are operands to the
303  // inline asm statement.
304  O << "{";
305  if (ARM::GPRPairRegClass.contains(RegBegin)) {
307  unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
308  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
309  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
310  }
311  O << ARMInstPrinter::getRegisterName(RegBegin);
312 
313  // FIXME: The register allocator not only may not have given us the
314  // registers in sequence, but may not be in ascending registers. This
315  // will require changes in the register allocator that'll need to be
316  // propagated down here if the operands change.
317  unsigned RegOps = OpNum + 1;
318  while (MI->getOperand(RegOps).isReg()) {
319  O << ", "
321  RegOps++;
322  }
323 
324  O << "}";
325 
326  return false;
327  }
328  case 'R': // The most significant register of a pair.
329  case 'Q': { // The least significant register of a pair.
330  if (OpNum == 0)
331  return true;
332  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
333  if (!FlagsOP.isImm())
334  return true;
335  unsigned Flags = FlagsOP.getImm();
336 
337  // This operand may not be the one that actually provides the register. If
338  // it's tied to a previous one then we should refer instead to that one
339  // for registers and their classes.
340  unsigned TiedIdx;
341  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
342  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
343  unsigned OpFlags = MI->getOperand(OpNum).getImm();
344  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
345  }
346  Flags = MI->getOperand(OpNum).getImm();
347 
348  // Later code expects OpNum to be pointing at the register rather than
349  // the flags.
350  OpNum += 1;
351  }
352 
353  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
354  unsigned RC;
355  bool FirstHalf;
356  const ARMBaseTargetMachine &ATM =
357  static_cast<const ARMBaseTargetMachine &>(TM);
358 
359  // 'Q' should correspond to the low order register and 'R' to the high
360  // order register. Whether this corresponds to the upper or lower half
361  // depends on the endianess mode.
362  if (ExtraCode[0] == 'Q')
363  FirstHalf = ATM.isLittleEndian();
364  else
365  // ExtraCode[0] == 'R'.
366  FirstHalf = !ATM.isLittleEndian();
368  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
369  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
370  if (NumVals != 1)
371  return true;
372  const MachineOperand &MO = MI->getOperand(OpNum);
373  if (!MO.isReg())
374  return true;
376  unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ?
377  ARM::gsub_0 : ARM::gsub_1);
379  return false;
380  }
381  if (NumVals != 2)
382  return true;
383  unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
384  if (RegOp >= MI->getNumOperands())
385  return true;
386  const MachineOperand &MO = MI->getOperand(RegOp);
387  if (!MO.isReg())
388  return true;
389  unsigned Reg = MO.getReg();
391  return false;
392  }
393 
394  case 'e': // The low doubleword register of a NEON quad register.
395  case 'f': { // The high doubleword register of a NEON quad register.
396  if (!MI->getOperand(OpNum).isReg())
397  return true;
398  unsigned Reg = MI->getOperand(OpNum).getReg();
399  if (!ARM::QPRRegClass.contains(Reg))
400  return true;
402  unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
403  ARM::dsub_0 : ARM::dsub_1);
404  O << ARMInstPrinter::getRegisterName(SubReg);
405  return false;
406  }
407 
408  // This modifier is not yet supported.
409  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
410  return true;
411  case 'H': { // The highest-numbered register of a pair.
412  const MachineOperand &MO = MI->getOperand(OpNum);
413  if (!MO.isReg())
414  return true;
415  const MachineFunction &MF = *MI->getParent()->getParent();
417  unsigned Reg = MO.getReg();
418  if(!ARM::GPRPairRegClass.contains(Reg))
419  return false;
420  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
422  return false;
423  }
424  }
425  }
426 
427  printOperand(MI, OpNum, O);
428  return false;
429 }
430 
432  unsigned OpNum, const char *ExtraCode,
433  raw_ostream &O) {
434  // Does this asm operand have a single letter operand modifier?
435  if (ExtraCode && ExtraCode[0]) {
436  if (ExtraCode[1] != 0) return true; // Unknown modifier.
437 
438  switch (ExtraCode[0]) {
439  case 'A': // A memory operand for a VLD1/VST1 instruction.
440  default: return true; // Unknown modifier.
441  case 'm': // The base register of a memory operand.
442  if (!MI->getOperand(OpNum).isReg())
443  return true;
445  return false;
446  }
447  }
448 
449  const MachineOperand &MO = MI->getOperand(OpNum);
450  assert(MO.isReg() && "unexpected inline asm memory operand");
451  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
452  return false;
453 }
454 
455 static bool isThumb(const MCSubtargetInfo& STI) {
456  return STI.getFeatureBits()[ARM::ModeThumb];
457 }
458 
460  const MCSubtargetInfo *EndInfo) const {
461  // If either end mode is unknown (EndInfo == NULL) or different than
462  // the start mode, then restore the start mode.
463  const bool WasThumb = isThumb(StartInfo);
464  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
465  OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
466  }
467 }
468 
470  const Triple &TT = TM.getTargetTriple();
471  // Use unified assembler syntax.
472  OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
473 
474  // Emit ARM Build Attributes
475  if (TT.isOSBinFormatELF())
476  emitAttributes();
477 
478  // Use the triple's architecture and subarchitecture to determine
479  // if we're thumb for the purposes of the top level code16 assembler
480  // flag.
481  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
482  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
483 }
484 
485 static void
488  // L_foo$stub:
489  OutStreamer.EmitLabel(StubLabel);
490  // .indirect_symbol _foo
491  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
492 
493  if (MCSym.getInt())
494  // External to current translation unit.
495  OutStreamer.EmitIntValue(0, 4/*size*/);
496  else
497  // Internal to current translation unit.
498  //
499  // When we place the LSDA into the TEXT section, the type info
500  // pointers need to be indirect and pc-rel. We accomplish this by
501  // using NLPs; however, sometimes the types are local to the file.
502  // We need to fill in the value for the NLP in those cases.
503  OutStreamer.EmitValue(
504  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
505  4 /*size*/);
506 }
507 
508 
510  const Triple &TT = TM.getTargetTriple();
511  if (TT.isOSBinFormatMachO()) {
512  // All darwin targets use mach-o.
513  const TargetLoweringObjectFileMachO &TLOFMacho =
514  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
515  MachineModuleInfoMachO &MMIMacho =
517 
518  // Output non-lazy-pointers for external and common global variables.
520 
521  if (!Stubs.empty()) {
522  // Switch with ".non_lazy_symbol_pointer" directive.
523  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
524  EmitAlignment(2);
525 
526  for (auto &Stub : Stubs)
527  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
528 
529  Stubs.clear();
530  OutStreamer->AddBlankLine();
531  }
532 
533  Stubs = MMIMacho.GetThreadLocalGVStubList();
534  if (!Stubs.empty()) {
535  // Switch with ".non_lazy_symbol_pointer" directive.
536  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
537  EmitAlignment(2);
538 
539  for (auto &Stub : Stubs)
540  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
541 
542  Stubs.clear();
543  OutStreamer->AddBlankLine();
544  }
545 
546  // Funny Darwin hack: This flag tells the linker that no global symbols
547  // contain code that falls through to other global symbols (e.g. the obvious
548  // implementation of multiple entry points). If this doesn't occur, the
549  // linker can safely perform dead code stripping. Since LLVM never
550  // generates code that does this, it is always safe to set.
551  OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
552  }
553 
554  // The last attribute to be emitted is ABI_optimization_goals
555  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
556  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
557 
558  if (OptimizationGoals > 0 &&
559  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
560  Subtarget->isTargetMuslAEABI()))
562  OptimizationGoals = -1;
563 
565 }
566 
567 //===----------------------------------------------------------------------===//
568 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
569 // FIXME:
570 // The following seem like one-off assembler flags, but they actually need
571 // to appear in the .ARM.attributes section in ELF.
572 // Instead of subclassing the MCELFStreamer, we do the work here.
573 
574 // Returns true if all functions have the same function attribute value.
575 // It also returns true when the module has no functions.
577  StringRef Value) {
578  return !any_of(M, [&](const Function &F) {
579  return F.getFnAttribute(Attr).getValueAsString() != Value;
580  });
581 }
582 
583 void ARMAsmPrinter::emitAttributes() {
584  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
585  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
586 
588 
589  ATS.switchVendor("aeabi");
590 
591  // Compute ARM ELF Attributes based on the default subtarget that
592  // we'd have constructed. The existing ARM behavior isn't LTO clean
593  // anyhow.
594  // FIXME: For ifunc related functions we could iterate over and look
595  // for a feature string that doesn't match the default one.
596  const Triple &TT = TM.getTargetTriple();
597  StringRef CPU = TM.getTargetCPU();
599  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
600  if (!FS.empty()) {
601  if (!ArchFS.empty())
602  ArchFS = (Twine(ArchFS) + "," + FS).str();
603  else
604  ArchFS = FS;
605  }
606  const ARMBaseTargetMachine &ATM =
607  static_cast<const ARMBaseTargetMachine &>(TM);
608  const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
609 
610  // Emit build attributes for the available hardware.
611  ATS.emitTargetAttributes(STI);
612 
613  // RW data addressing.
614  if (isPositionIndependent()) {
617  } else if (STI.isRWPI()) {
618  // RWPI specific attributes.
621  }
622 
623  // RO data addressing.
624  if (isPositionIndependent() || STI.isROPI()) {
627  }
628 
629  // GOT use.
630  if (isPositionIndependent()) {
633  } else {
636  }
637 
638  // Set FP Denormals.
640  "denormal-fp-math",
641  "preserve-sign") ||
646  "denormal-fp-math",
647  "positive-zero") ||
651  else if (!TM.Options.UnsafeFPMath)
654  else {
655  if (!STI.hasVFP2()) {
656  // When the target doesn't have an FPU (by design or
657  // intention), the assumptions made on the software support
658  // mirror that of the equivalent hardware support *if it
659  // existed*. For v7 and better we indicate that denormals are
660  // flushed preserving sign, and for V6 we indicate that
661  // denormals are flushed to positive zero.
662  if (STI.hasV7Ops())
665  } else if (STI.hasVFP3()) {
666  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
667  // the sign bit of the zero matches the sign bit of the input or
668  // result that is being flushed to zero.
671  }
672  // For VFPv2 implementations it is implementation defined as
673  // to whether denormals are flushed to positive zero or to
674  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
675  // LLVM has chosen to flush this to positive zero (most likely for
676  // GCC compatibility), so that's the chosen value here (the
677  // absence of its emission implies zero).
678  }
679 
680  // Set FP exceptions and rounding
682  "no-trapping-math", "true") ||
686  else if (!TM.Options.UnsafeFPMath) {
688 
689  // If the user has permitted this code to choose the IEEE 754
690  // rounding at run-time, emit the rounding attribute.
693  }
694 
695  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
696  // equivalent of GCC's -ffinite-math-only flag.
700  else
703 
704  // FIXME: add more flags to ARMBuildAttributes.h
705  // 8-bytes alignment stuff.
708 
709  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
710  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
712 
713  // FIXME: To support emitting this build attribute as GCC does, the
714  // -mfp16-format option and associated plumbing must be
715  // supported. For now the __fp16 type is exposed by default, so this
716  // attribute should be emitted with value 1.
719 
720  if (MMI) {
721  if (const Module *SourceModule = MMI->getModule()) {
722  // ABI_PCS_wchar_t to indicate wchar_t width
723  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
724  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
725  SourceModule->getModuleFlag("wchar_size"))) {
726  int WCharWidth = WCharWidthValue->getZExtValue();
727  assert((WCharWidth == 2 || WCharWidth == 4) &&
728  "wchar_t width must be 2 or 4 bytes");
730  }
731 
732  // ABI_enum_size to indicate enum width
733  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
734  // (all enums contain a value needing 32 bits to encode).
735  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
736  SourceModule->getModuleFlag("min_enum_size"))) {
737  int EnumWidth = EnumWidthValue->getZExtValue();
738  assert((EnumWidth == 1 || EnumWidth == 4) &&
739  "Minimum enum width must be 1 or 4 bytes");
740  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
741  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
742  }
743  }
744  }
745 
746  // We currently do not support using R9 as the TLS pointer.
747  if (STI.isRWPI())
750  else if (STI.isR9Reserved())
753  else
756 }
757 
758 //===----------------------------------------------------------------------===//
759 
761  unsigned LabelId, MCContext &Ctx) {
762 
763  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
764  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
765  return Label;
766 }
767 
770  switch (Modifier) {
771  case ARMCP::no_modifier:
773  case ARMCP::TLSGD:
775  case ARMCP::TPOFF:
777  case ARMCP::GOTTPOFF:
779  case ARMCP::SBREL:
781  case ARMCP::GOT_PREL:
783  case ARMCP::SECREL:
785  }
786  llvm_unreachable("Invalid ARMCPModifier!");
787 }
788 
789 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
790  unsigned char TargetFlags) {
791  if (Subtarget->isTargetMachO()) {
792  bool IsIndirect =
793  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
794 
795  if (!IsIndirect)
796  return getSymbol(GV);
797 
798  // FIXME: Remove this when Darwin transition to @GOT like syntax.
799  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
800  MachineModuleInfoMachO &MMIMachO =
803  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
804  : MMIMachO.getGVStubEntry(MCSym);
805 
806  if (!StubSym.getPointer())
808  !GV->hasInternalLinkage());
809  return MCSym;
810  } else if (Subtarget->isTargetCOFF()) {
811  assert(Subtarget->isTargetWindows() &&
812  "Windows is the only supported COFF target");
813 
814  bool IsIndirect =
815  (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
816  if (!IsIndirect)
817  return getSymbol(GV);
818 
820  if (TargetFlags & ARMII::MO_DLLIMPORT)
821  Name = "__imp_";
822  else if (TargetFlags & ARMII::MO_COFFSTUB)
823  Name = ".refptr.";
824  getNameWithPrefix(Name, GV);
825 
826  MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
827 
828  if (TargetFlags & ARMII::MO_COFFSTUB) {
829  MachineModuleInfoCOFF &MMICOFF =
832  MMICOFF.getGVStubEntry(MCSym);
833 
834  if (!StubSym.getPointer())
835  StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
836  }
837 
838  return MCSym;
839  } else if (Subtarget->isTargetELF()) {
840  return getSymbol(GV);
841  }
842  llvm_unreachable("unexpected target");
843 }
844 
845 void ARMAsmPrinter::
847  const DataLayout &DL = getDataLayout();
848  int Size = DL.getTypeAllocSize(MCPV->getType());
849 
850  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
851 
852  if (ACPV->isPromotedGlobal()) {
853  // This constant pool entry is actually a global whose storage has been
854  // promoted into the constant pool. This global may be referenced still
855  // by debug information, and due to the way AsmPrinter is set up, the debug
856  // info is immutable by the time we decide to promote globals to constant
857  // pools. Because of this, we need to ensure we emit a symbol for the global
858  // with private linkage (the default) so debug info can refer to it.
859  //
860  // However, if this global is promoted into several functions we must ensure
861  // we don't try and emit duplicate symbols!
862  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
863  for (const auto *GV : ACPC->promotedGlobals()) {
864  if (!EmittedPromotedGlobalLabels.count(GV)) {
865  MCSymbol *GVSym = getSymbol(GV);
866  OutStreamer->EmitLabel(GVSym);
867  EmittedPromotedGlobalLabels.insert(GV);
868  }
869  }
870  return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
871  }
872 
873  MCSymbol *MCSym;
874  if (ACPV->isLSDA()) {
875  MCSym = getCurExceptionSym();
876  } else if (ACPV->isBlockAddress()) {
877  const BlockAddress *BA =
878  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
879  MCSym = GetBlockAddressSymbol(BA);
880  } else if (ACPV->isGlobalValue()) {
881  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
882 
883  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
884  // flag the global as MO_NONLAZY.
885  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
886  MCSym = GetARMGVSymbol(GV, TF);
887  } else if (ACPV->isMachineBasicBlock()) {
888  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
889  MCSym = MBB->getSymbol();
890  } else {
891  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
892  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
893  MCSym = GetExternalSymbolSymbol(Sym);
894  }
895 
896  // Create an MCSymbol for the reference.
897  const MCExpr *Expr =
899  OutContext);
900 
901  if (ACPV->getPCAdjustment()) {
902  MCSymbol *PCLabel =
904  ACPV->getLabelId(), OutContext);
905  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
906  PCRelExpr =
907  MCBinaryExpr::createAdd(PCRelExpr,
909  OutContext),
910  OutContext);
911  if (ACPV->mustAddCurrentAddress()) {
912  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
913  // label, so just emit a local label end reference that instead.
915  OutStreamer->EmitLabel(DotSym);
916  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
917  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
918  }
919  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
920  }
921  OutStreamer->EmitValue(Expr, Size);
922 }
923 
925  const MachineOperand &MO1 = MI->getOperand(1);
926  unsigned JTI = MO1.getIndex();
927 
928  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
929  // ARM mode tables.
930  EmitAlignment(2);
931 
932  // Emit a label for the jump table.
933  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
934  OutStreamer->EmitLabel(JTISymbol);
935 
936  // Mark the jump table as data-in-code.
937  OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
938 
939  // Emit each entry of the table.
940  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
941  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
942  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
943 
944  for (MachineBasicBlock *MBB : JTBBs) {
945  // Construct an MCExpr for the entry. We want a value of the form:
946  // (BasicBlockAddr - TableBeginAddr)
947  //
948  // For example, a table with entries jumping to basic blocks BB0 and BB1
949  // would look like:
950  // LJTI_0_0:
951  // .word (LBB0 - LJTI_0_0)
952  // .word (LBB1 - LJTI_0_0)
953  const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
954 
955  if (isPositionIndependent() || Subtarget->isROPI())
956  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
957  OutContext),
958  OutContext);
959  // If we're generating a table of Thumb addresses in static relocation
960  // model, we need to add one to keep interworking correctly.
961  else if (AFI->isThumbFunction())
963  OutContext);
964  OutStreamer->EmitValue(Expr, 4);
965  }
966  // Mark the end of jump table data-in-code region.
967  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
968 }
969 
971  const MachineOperand &MO1 = MI->getOperand(1);
972  unsigned JTI = MO1.getIndex();
973 
974  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
975  // ARM mode tables.
976  EmitAlignment(2);
977 
978  // Emit a label for the jump table.
979  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
980  OutStreamer->EmitLabel(JTISymbol);
981 
982  // Emit each entry of the table.
983  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
984  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
985  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
986 
987  for (MachineBasicBlock *MBB : JTBBs) {
988  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
989  OutContext);
990  // If this isn't a TBB or TBH, the entries are direct branch instructions.
992  .addExpr(MBBSymbolExpr)
993  .addImm(ARMCC::AL)
994  .addReg(0));
995  }
996 }
997 
999  unsigned OffsetWidth) {
1000  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1001  const MachineOperand &MO1 = MI->getOperand(1);
1002  unsigned JTI = MO1.getIndex();
1003 
1004  if (Subtarget->isThumb1Only())
1005  EmitAlignment(2);
1006 
1007  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1008  OutStreamer->EmitLabel(JTISymbol);
1009 
1010  // Emit each entry of the table.
1011  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1012  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1013  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1014 
1015  // Mark the jump table as data-in-code.
1016  OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1018 
1019  for (auto MBB : JTBBs) {
1020  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1021  OutContext);
1022  // Otherwise it's an offset from the dispatch instruction. Construct an
1023  // MCExpr for the entry. We want a value of the form:
1024  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1025  //
1026  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1027  // would look like:
1028  // LJTI_0_0:
1029  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1030  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1031  // where LCPI0_0 is a label defined just before the TBB instruction using
1032  // this table.
1033  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1034  const MCExpr *Expr = MCBinaryExpr::createAdd(
1037  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1039  OutContext);
1040  OutStreamer->EmitValue(Expr, OffsetWidth);
1041  }
1042  // Mark the end of jump table data-in-code region. 32-bit offsets use
1043  // actual branch instructions here, so we don't mark those as a data-region
1044  // at all.
1045  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1046 
1047  // Make sure the next instruction is 2-byte aligned.
1048  EmitAlignment(1);
1049 }
1050 
1051 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1053  "Only instruction which are involved into frame setup code are allowed");
1054 
1055  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1056  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1057  const MachineFunction &MF = *MI->getParent()->getParent();
1058  const TargetRegisterInfo *TargetRegInfo =
1060  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1061  const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1062 
1063  unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
1064  unsigned Opc = MI->getOpcode();
1065  unsigned SrcReg, DstReg;
1066 
1067  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1068  // Two special cases:
1069  // 1) tPUSH does not have src/dst regs.
1070  // 2) for Thumb1 code we sometimes materialize the constant via constpool
1071  // load. Yes, this is pretty fragile, but for now I don't see better
1072  // way... :(
1073  SrcReg = DstReg = ARM::SP;
1074  } else {
1075  SrcReg = MI->getOperand(1).getReg();
1076  DstReg = MI->getOperand(0).getReg();
1077  }
1078 
1079  // Try to figure out the unwinding opcode out of src / dst regs.
1080  if (MI->mayStore()) {
1081  // Register saves.
1082  assert(DstReg == ARM::SP &&
1083  "Only stack pointer as a destination reg is supported");
1084 
1085  SmallVector<unsigned, 4> RegList;
1086  // Skip src & dst reg, and pred ops.
1087  unsigned StartOp = 2 + 2;
1088  // Use all the operands.
1089  unsigned NumOffset = 0;
1090  // Amount of SP adjustment folded into a push.
1091  unsigned Pad = 0;
1092 
1093  switch (Opc) {
1094  default:
1095  MI->print(errs());
1096  llvm_unreachable("Unsupported opcode for unwinding information");
1097  case ARM::tPUSH:
1098  // Special case here: no src & dst reg, but two extra imp ops.
1099  StartOp = 2; NumOffset = 2;
1101  case ARM::STMDB_UPD:
1102  case ARM::t2STMDB_UPD:
1103  case ARM::VSTMDDB_UPD:
1104  assert(SrcReg == ARM::SP &&
1105  "Only stack pointer as a source reg is supported");
1106  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1107  i != NumOps; ++i) {
1108  const MachineOperand &MO = MI->getOperand(i);
1109  // Actually, there should never be any impdef stuff here. Skip it
1110  // temporary to workaround PR11902.
1111  if (MO.isImplicit())
1112  continue;
1113  // Registers, pushed as a part of folding an SP update into the
1114  // push instruction are marked as undef and should not be
1115  // restored when unwinding, because the function can modify the
1116  // corresponding stack slots.
1117  if (MO.isUndef()) {
1118  assert(RegList.empty() &&
1119  "Pad registers must come before restored ones");
1120  unsigned Width =
1121  TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1122  Pad += Width;
1123  continue;
1124  }
1125  RegList.push_back(MO.getReg());
1126  }
1127  break;
1128  case ARM::STR_PRE_IMM:
1129  case ARM::STR_PRE_REG:
1130  case ARM::t2STR_PRE:
1131  assert(MI->getOperand(2).getReg() == ARM::SP &&
1132  "Only stack pointer as a source reg is supported");
1133  RegList.push_back(SrcReg);
1134  break;
1135  }
1137  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1138  // Account for the SP adjustment, folded into the push.
1139  if (Pad)
1140  ATS.emitPad(Pad);
1141  }
1142  } else {
1143  // Changes of stack / frame pointer.
1144  if (SrcReg == ARM::SP) {
1145  int64_t Offset = 0;
1146  switch (Opc) {
1147  default:
1148  MI->print(errs());
1149  llvm_unreachable("Unsupported opcode for unwinding information");
1150  case ARM::MOVr:
1151  case ARM::tMOVr:
1152  Offset = 0;
1153  break;
1154  case ARM::ADDri:
1155  case ARM::t2ADDri:
1156  Offset = -MI->getOperand(2).getImm();
1157  break;
1158  case ARM::SUBri:
1159  case ARM::t2SUBri:
1160  Offset = MI->getOperand(2).getImm();
1161  break;
1162  case ARM::tSUBspi:
1163  Offset = MI->getOperand(2).getImm()*4;
1164  break;
1165  case ARM::tADDspi:
1166  case ARM::tADDrSPi:
1167  Offset = -MI->getOperand(2).getImm()*4;
1168  break;
1169  case ARM::tLDRpci: {
1170  // Grab the constpool index and check, whether it corresponds to
1171  // original or cloned constpool entry.
1172  unsigned CPI = MI->getOperand(1).getIndex();
1173  const MachineConstantPool *MCP = MF.getConstantPool();
1174  if (CPI >= MCP->getConstants().size())
1175  CPI = AFI.getOriginalCPIdx(CPI);
1176  assert(CPI != -1U && "Invalid constpool index");
1177 
1178  // Derive the actual offset.
1179  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1180  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1181  // FIXME: Check for user, it should be "add" instruction!
1182  Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1183  break;
1184  }
1185  }
1186 
1188  if (DstReg == FramePtr && FramePtr != ARM::SP)
1189  // Set-up of the frame pointer. Positive values correspond to "add"
1190  // instruction.
1191  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1192  else if (DstReg == ARM::SP) {
1193  // Change of SP by an offset. Positive values correspond to "sub"
1194  // instruction.
1195  ATS.emitPad(Offset);
1196  } else {
1197  // Move of SP to a register. Positive values correspond to an "add"
1198  // instruction.
1199  ATS.emitMovSP(DstReg, -Offset);
1200  }
1201  }
1202  } else if (DstReg == ARM::SP) {
1203  MI->print(errs());
1204  llvm_unreachable("Unsupported opcode for unwinding information");
1205  }
1206  else {
1207  MI->print(errs());
1208  llvm_unreachable("Unsupported opcode for unwinding information");
1209  }
1210  }
1211 }
1212 
1213 // Simple pseudo-instructions have their lowering (with expansion to real
1214 // instructions) auto-generated.
1215 #include "ARMGenMCPseudoLowering.inc"
1216 
1218  const DataLayout &DL = getDataLayout();
1219  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1220  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1221 
1222  const MachineFunction &MF = *MI->getParent()->getParent();
1223  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1224  unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1225 
1226  // If we just ended a constant pool, mark it as such.
1227  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1228  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1229  InConstantPool = false;
1230  }
1231 
1232  // Emit unwinding stuff for frame-related instructions
1233  if (Subtarget->isTargetEHABICompatible() &&
1235  EmitUnwindingInstruction(MI);
1236 
1237  // Do any auto-generated pseudo lowerings.
1238  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1239  return;
1240 
1242  "Pseudo flag setting opcode should be expanded early");
1243 
1244  // Check for manual lowerings.
1245  unsigned Opc = MI->getOpcode();
1246  switch (Opc) {
1247  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1248  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1249  case ARM::LEApcrel:
1250  case ARM::tLEApcrel:
1251  case ARM::t2LEApcrel: {
1252  // FIXME: Need to also handle globals and externals
1253  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1255  ARM::t2LEApcrel ? ARM::t2ADR
1256  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1257  : ARM::ADR))
1258  .addReg(MI->getOperand(0).getReg())
1259  .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1260  // Add predicate operands.
1261  .addImm(MI->getOperand(2).getImm())
1262  .addReg(MI->getOperand(3).getReg()));
1263  return;
1264  }
1265  case ARM::LEApcrelJT:
1266  case ARM::tLEApcrelJT:
1267  case ARM::t2LEApcrelJT: {
1268  MCSymbol *JTIPICSymbol =
1269  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1271  ARM::t2LEApcrelJT ? ARM::t2ADR
1272  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1273  : ARM::ADR))
1274  .addReg(MI->getOperand(0).getReg())
1275  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1276  // Add predicate operands.
1277  .addImm(MI->getOperand(2).getImm())
1278  .addReg(MI->getOperand(3).getReg()));
1279  return;
1280  }
1281  // Darwin call instructions are just normal call instructions with different
1282  // clobber semantics (they clobber R9).
1283  case ARM::BX_CALL: {
1285  .addReg(ARM::LR)
1286  .addReg(ARM::PC)
1287  // Add predicate operands.
1288  .addImm(ARMCC::AL)
1289  .addReg(0)
1290  // Add 's' bit operand (always reg0 for this)
1291  .addReg(0));
1292 
1293  assert(Subtarget->hasV4TOps());
1295  .addReg(MI->getOperand(0).getReg()));
1296  return;
1297  }
1298  case ARM::tBX_CALL: {
1299  if (Subtarget->hasV5TOps())
1300  llvm_unreachable("Expected BLX to be selected for v5t+");
1301 
1302  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1303  // that the saved lr has its LSB set correctly (the arch doesn't
1304  // have blx).
1305  // So here we generate a bl to a small jump pad that does bx rN.
1306  // The jump pads are emitted after the function body.
1307 
1308  unsigned TReg = MI->getOperand(0).getReg();
1309  MCSymbol *TRegSym = nullptr;
1310  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1311  if (TIP.first == TReg) {
1312  TRegSym = TIP.second;
1313  break;
1314  }
1315  }
1316 
1317  if (!TRegSym) {
1318  TRegSym = OutContext.createTempSymbol();
1319  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1320  }
1321 
1322  // Create a link-saving branch to the Reg Indirect Jump Pad.
1324  // Predicate comes first here.
1325  .addImm(ARMCC::AL).addReg(0)
1326  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1327  return;
1328  }
1329  case ARM::BMOVPCRX_CALL: {
1331  .addReg(ARM::LR)
1332  .addReg(ARM::PC)
1333  // Add predicate operands.
1334  .addImm(ARMCC::AL)
1335  .addReg(0)
1336  // Add 's' bit operand (always reg0 for this)
1337  .addReg(0));
1338 
1340  .addReg(ARM::PC)
1341  .addReg(MI->getOperand(0).getReg())
1342  // Add predicate operands.
1343  .addImm(ARMCC::AL)
1344  .addReg(0)
1345  // Add 's' bit operand (always reg0 for this)
1346  .addReg(0));
1347  return;
1348  }
1349  case ARM::BMOVPCB_CALL: {
1351  .addReg(ARM::LR)
1352  .addReg(ARM::PC)
1353  // Add predicate operands.
1354  .addImm(ARMCC::AL)
1355  .addReg(0)
1356  // Add 's' bit operand (always reg0 for this)
1357  .addReg(0));
1358 
1359  const MachineOperand &Op = MI->getOperand(0);
1360  const GlobalValue *GV = Op.getGlobal();
1361  const unsigned TF = Op.getTargetFlags();
1362  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1363  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1365  .addExpr(GVSymExpr)
1366  // Add predicate operands.
1367  .addImm(ARMCC::AL)
1368  .addReg(0));
1369  return;
1370  }
1371  case ARM::MOVi16_ga_pcrel:
1372  case ARM::t2MOVi16_ga_pcrel: {
1373  MCInst TmpInst;
1374  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1375  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1376 
1377  unsigned TF = MI->getOperand(1).getTargetFlags();
1378  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1379  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1380  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1381 
1382  MCSymbol *LabelSym =
1384  MI->getOperand(2).getImm(), OutContext);
1385  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1386  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1387  const MCExpr *PCRelExpr =
1389  MCBinaryExpr::createAdd(LabelSymExpr,
1392  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1393 
1394  // Add predicate operands.
1396  TmpInst.addOperand(MCOperand::createReg(0));
1397  // Add 's' bit operand (always reg0 for this)
1398  TmpInst.addOperand(MCOperand::createReg(0));
1399  EmitToStreamer(*OutStreamer, TmpInst);
1400  return;
1401  }
1402  case ARM::MOVTi16_ga_pcrel:
1403  case ARM::t2MOVTi16_ga_pcrel: {
1404  MCInst TmpInst;
1405  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1406  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1407  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1408  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1409 
1410  unsigned TF = MI->getOperand(2).getTargetFlags();
1411  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1412  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1413  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1414 
1415  MCSymbol *LabelSym =
1417  MI->getOperand(3).getImm(), OutContext);
1418  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1419  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1420  const MCExpr *PCRelExpr =
1422  MCBinaryExpr::createAdd(LabelSymExpr,
1425  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1426  // Add predicate operands.
1428  TmpInst.addOperand(MCOperand::createReg(0));
1429  // Add 's' bit operand (always reg0 for this)
1430  TmpInst.addOperand(MCOperand::createReg(0));
1431  EmitToStreamer(*OutStreamer, TmpInst);
1432  return;
1433  }
1434  case ARM::tPICADD: {
1435  // This is a pseudo op for a label + instruction sequence, which looks like:
1436  // LPC0:
1437  // add r0, pc
1438  // This adds the address of LPC0 to r0.
1439 
1440  // Emit the label.
1443  MI->getOperand(2).getImm(), OutContext));
1444 
1445  // Form and emit the add.
1446  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1447  .addReg(MI->getOperand(0).getReg())
1448  .addReg(MI->getOperand(0).getReg())
1449  .addReg(ARM::PC)
1450  // Add predicate operands.
1451  .addImm(ARMCC::AL)
1452  .addReg(0));
1453  return;
1454  }
1455  case ARM::PICADD: {
1456  // This is a pseudo op for a label + instruction sequence, which looks like:
1457  // LPC0:
1458  // add r0, pc, r0
1459  // This adds the address of LPC0 to r0.
1460 
1461  // Emit the label.
1464  MI->getOperand(2).getImm(), OutContext));
1465 
1466  // Form and emit the add.
1468  .addReg(MI->getOperand(0).getReg())
1469  .addReg(ARM::PC)
1470  .addReg(MI->getOperand(1).getReg())
1471  // Add predicate operands.
1472  .addImm(MI->getOperand(3).getImm())
1473  .addReg(MI->getOperand(4).getReg())
1474  // Add 's' bit operand (always reg0 for this)
1475  .addReg(0));
1476  return;
1477  }
1478  case ARM::PICSTR:
1479  case ARM::PICSTRB:
1480  case ARM::PICSTRH:
1481  case ARM::PICLDR:
1482  case ARM::PICLDRB:
1483  case ARM::PICLDRH:
1484  case ARM::PICLDRSB:
1485  case ARM::PICLDRSH: {
1486  // This is a pseudo op for a label + instruction sequence, which looks like:
1487  // LPC0:
1488  // OP r0, [pc, r0]
1489  // The LCP0 label is referenced by a constant pool entry in order to get
1490  // a PC-relative address at the ldr instruction.
1491 
1492  // Emit the label.
1495  MI->getOperand(2).getImm(), OutContext));
1496 
1497  // Form and emit the load
1498  unsigned Opcode;
1499  switch (MI->getOpcode()) {
1500  default:
1501  llvm_unreachable("Unexpected opcode!");
1502  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1503  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1504  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1505  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1506  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1507  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1508  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1509  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1510  }
1512  .addReg(MI->getOperand(0).getReg())
1513  .addReg(ARM::PC)
1514  .addReg(MI->getOperand(1).getReg())
1515  .addImm(0)
1516  // Add predicate operands.
1517  .addImm(MI->getOperand(3).getImm())
1518  .addReg(MI->getOperand(4).getReg()));
1519 
1520  return;
1521  }
1522  case ARM::CONSTPOOL_ENTRY: {
1523  if (Subtarget->genExecuteOnly())
1524  llvm_unreachable("execute-only should not generate constant pools");
1525 
1526  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1527  /// in the function. The first operand is the ID# for this instruction, the
1528  /// second is the index into the MachineConstantPool that this is, the third
1529  /// is the size in bytes of this constant pool entry.
1530  /// The required alignment is specified on the basic block holding this MI.
1531  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1532  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1533 
1534  // If this is the first entry of the pool, mark it.
1535  if (!InConstantPool) {
1536  OutStreamer->EmitDataRegion(MCDR_DataRegion);
1537  InConstantPool = true;
1538  }
1539 
1540  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1541 
1542  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1543  if (MCPE.isMachineConstantPoolEntry())
1545  else
1546  EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1547  return;
1548  }
1549  case ARM::JUMPTABLE_ADDRS:
1550  EmitJumpTableAddrs(MI);
1551  return;
1552  case ARM::JUMPTABLE_INSTS:
1553  EmitJumpTableInsts(MI);
1554  return;
1555  case ARM::JUMPTABLE_TBB:
1556  case ARM::JUMPTABLE_TBH:
1557  EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1558  return;
1559  case ARM::t2BR_JT: {
1561  .addReg(ARM::PC)
1562  .addReg(MI->getOperand(0).getReg())
1563  // Add predicate operands.
1564  .addImm(ARMCC::AL)
1565  .addReg(0));
1566  return;
1567  }
1568  case ARM::t2TBB_JT:
1569  case ARM::t2TBH_JT: {
1570  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1571  // Lower and emit the PC label, then the instruction itself.
1572  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1574  .addReg(MI->getOperand(0).getReg())
1575  .addReg(MI->getOperand(1).getReg())
1576  // Add predicate operands.
1577  .addImm(ARMCC::AL)
1578  .addReg(0));
1579  return;
1580  }
1581  case ARM::tTBB_JT:
1582  case ARM::tTBH_JT: {
1583 
1584  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1585  unsigned Base = MI->getOperand(0).getReg();
1586  unsigned Idx = MI->getOperand(1).getReg();
1587  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1588 
1589  // Multiply up idx if necessary.
1590  if (!Is8Bit)
1592  .addReg(Idx)
1593  .addReg(ARM::CPSR)
1594  .addReg(Idx)
1595  .addImm(1)
1596  // Add predicate operands.
1597  .addImm(ARMCC::AL)
1598  .addReg(0));
1599 
1600  if (Base == ARM::PC) {
1601  // TBB [base, idx] =
1602  // ADDS idx, idx, base
1603  // LDRB idx, [idx, #4] ; or LDRH if TBH
1604  // LSLS idx, #1
1605  // ADDS pc, pc, idx
1606 
1607  // When using PC as the base, it's important that there is no padding
1608  // between the last ADDS and the start of the jump table. The jump table
1609  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1610  //
1611  // FIXME: Ideally we could vary the LDRB index based on the padding
1612  // between the sequence and jump table, however that relies on MCExprs
1613  // for load indexes which are currently not supported.
1614  OutStreamer->EmitCodeAlignment(4);
1615  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1616  .addReg(Idx)
1617  .addReg(Idx)
1618  .addReg(Base)
1619  // Add predicate operands.
1620  .addImm(ARMCC::AL)
1621  .addReg(0));
1622 
1623  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1625  .addReg(Idx)
1626  .addReg(Idx)
1627  .addImm(Is8Bit ? 4 : 2)
1628  // Add predicate operands.
1629  .addImm(ARMCC::AL)
1630  .addReg(0));
1631  } else {
1632  // TBB [base, idx] =
1633  // LDRB idx, [base, idx] ; or LDRH if TBH
1634  // LSLS idx, #1
1635  // ADDS pc, pc, idx
1636 
1637  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1639  .addReg(Idx)
1640  .addReg(Base)
1641  .addReg(Idx)
1642  // Add predicate operands.
1643  .addImm(ARMCC::AL)
1644  .addReg(0));
1645  }
1646 
1648  .addReg(Idx)
1649  .addReg(ARM::CPSR)
1650  .addReg(Idx)
1651  .addImm(1)
1652  // Add predicate operands.
1653  .addImm(ARMCC::AL)
1654  .addReg(0));
1655 
1656  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1657  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1658  .addReg(ARM::PC)
1659  .addReg(ARM::PC)
1660  .addReg(Idx)
1661  // Add predicate operands.
1662  .addImm(ARMCC::AL)
1663  .addReg(0));
1664  return;
1665  }
1666  case ARM::tBR_JTr:
1667  case ARM::BR_JTr: {
1668  // mov pc, target
1669  MCInst TmpInst;
1670  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1671  ARM::MOVr : ARM::tMOVr;
1672  TmpInst.setOpcode(Opc);
1673  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1674  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1675  // Add predicate operands.
1677  TmpInst.addOperand(MCOperand::createReg(0));
1678  // Add 's' bit operand (always reg0 for this)
1679  if (Opc == ARM::MOVr)
1680  TmpInst.addOperand(MCOperand::createReg(0));
1681  EmitToStreamer(*OutStreamer, TmpInst);
1682  return;
1683  }
1684  case ARM::BR_JTm_i12: {
1685  // ldr pc, target
1686  MCInst TmpInst;
1687  TmpInst.setOpcode(ARM::LDRi12);
1688  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1689  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1690  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1691  // Add predicate operands.
1693  TmpInst.addOperand(MCOperand::createReg(0));
1694  EmitToStreamer(*OutStreamer, TmpInst);
1695  return;
1696  }
1697  case ARM::BR_JTm_rs: {
1698  // ldr pc, target
1699  MCInst TmpInst;
1700  TmpInst.setOpcode(ARM::LDRrs);
1701  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1702  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1703  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1704  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1705  // Add predicate operands.
1707  TmpInst.addOperand(MCOperand::createReg(0));
1708  EmitToStreamer(*OutStreamer, TmpInst);
1709  return;
1710  }
1711  case ARM::BR_JTadd: {
1712  // add pc, target, idx
1714  .addReg(ARM::PC)
1715  .addReg(MI->getOperand(0).getReg())
1716  .addReg(MI->getOperand(1).getReg())
1717  // Add predicate operands.
1718  .addImm(ARMCC::AL)
1719  .addReg(0)
1720  // Add 's' bit operand (always reg0 for this)
1721  .addReg(0));
1722  return;
1723  }
1724  case ARM::SPACE:
1725  OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1726  return;
1727  case ARM::TRAP: {
1728  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1729  // FIXME: Remove this special case when they do.
1730  if (!Subtarget->isTargetMachO()) {
1731  uint32_t Val = 0xe7ffdefeUL;
1732  OutStreamer->AddComment("trap");
1733  ATS.emitInst(Val);
1734  return;
1735  }
1736  break;
1737  }
1738  case ARM::TRAPNaCl: {
1739  uint32_t Val = 0xe7fedef0UL;
1740  OutStreamer->AddComment("trap");
1741  ATS.emitInst(Val);
1742  return;
1743  }
1744  case ARM::tTRAP: {
1745  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1746  // FIXME: Remove this special case when they do.
1747  if (!Subtarget->isTargetMachO()) {
1748  uint16_t Val = 0xdefe;
1749  OutStreamer->AddComment("trap");
1750  ATS.emitInst(Val, 'n');
1751  return;
1752  }
1753  break;
1754  }
1755  case ARM::t2Int_eh_sjlj_setjmp:
1756  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1757  case ARM::tInt_eh_sjlj_setjmp: {
1758  // Two incoming args: GPR:$src, GPR:$val
1759  // mov $val, pc
1760  // adds $val, #7
1761  // str $val, [$src, #4]
1762  // movs r0, #0
1763  // b LSJLJEH
1764  // movs r0, #1
1765  // LSJLJEH:
1766  unsigned SrcReg = MI->getOperand(0).getReg();
1767  unsigned ValReg = MI->getOperand(1).getReg();
1768  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1769  OutStreamer->AddComment("eh_setjmp begin");
1771  .addReg(ValReg)
1772  .addReg(ARM::PC)
1773  // Predicate.
1774  .addImm(ARMCC::AL)
1775  .addReg(0));
1776 
1778  .addReg(ValReg)
1779  // 's' bit operand
1780  .addReg(ARM::CPSR)
1781  .addReg(ValReg)
1782  .addImm(7)
1783  // Predicate.
1784  .addImm(ARMCC::AL)
1785  .addReg(0));
1786 
1788  .addReg(ValReg)
1789  .addReg(SrcReg)
1790  // The offset immediate is #4. The operand value is scaled by 4 for the
1791  // tSTR instruction.
1792  .addImm(1)
1793  // Predicate.
1794  .addImm(ARMCC::AL)
1795  .addReg(0));
1796 
1798  .addReg(ARM::R0)
1799  .addReg(ARM::CPSR)
1800  .addImm(0)
1801  // Predicate.
1802  .addImm(ARMCC::AL)
1803  .addReg(0));
1804 
1805  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1807  .addExpr(SymbolExpr)
1808  .addImm(ARMCC::AL)
1809  .addReg(0));
1810 
1811  OutStreamer->AddComment("eh_setjmp end");
1813  .addReg(ARM::R0)
1814  .addReg(ARM::CPSR)
1815  .addImm(1)
1816  // Predicate.
1817  .addImm(ARMCC::AL)
1818  .addReg(0));
1819 
1820  OutStreamer->EmitLabel(Label);
1821  return;
1822  }
1823 
1824  case ARM::Int_eh_sjlj_setjmp_nofp:
1825  case ARM::Int_eh_sjlj_setjmp: {
1826  // Two incoming args: GPR:$src, GPR:$val
1827  // add $val, pc, #8
1828  // str $val, [$src, #+4]
1829  // mov r0, #0
1830  // add pc, pc, #0
1831  // mov r0, #1
1832  unsigned SrcReg = MI->getOperand(0).getReg();
1833  unsigned ValReg = MI->getOperand(1).getReg();
1834 
1835  OutStreamer->AddComment("eh_setjmp begin");
1837  .addReg(ValReg)
1838  .addReg(ARM::PC)
1839  .addImm(8)
1840  // Predicate.
1841  .addImm(ARMCC::AL)
1842  .addReg(0)
1843  // 's' bit operand (always reg0 for this).
1844  .addReg(0));
1845 
1847  .addReg(ValReg)
1848  .addReg(SrcReg)
1849  .addImm(4)
1850  // Predicate.
1851  .addImm(ARMCC::AL)
1852  .addReg(0));
1853 
1855  .addReg(ARM::R0)
1856  .addImm(0)
1857  // Predicate.
1858  .addImm(ARMCC::AL)
1859  .addReg(0)
1860  // 's' bit operand (always reg0 for this).
1861  .addReg(0));
1862 
1864  .addReg(ARM::PC)
1865  .addReg(ARM::PC)
1866  .addImm(0)
1867  // Predicate.
1868  .addImm(ARMCC::AL)
1869  .addReg(0)
1870  // 's' bit operand (always reg0 for this).
1871  .addReg(0));
1872 
1873  OutStreamer->AddComment("eh_setjmp end");
1875  .addReg(ARM::R0)
1876  .addImm(1)
1877  // Predicate.
1878  .addImm(ARMCC::AL)
1879  .addReg(0)
1880  // 's' bit operand (always reg0 for this).
1881  .addReg(0));
1882  return;
1883  }
1884  case ARM::Int_eh_sjlj_longjmp: {
1885  // ldr sp, [$src, #8]
1886  // ldr $scratch, [$src, #4]
1887  // ldr r7, [$src]
1888  // bx $scratch
1889  unsigned SrcReg = MI->getOperand(0).getReg();
1890  unsigned ScratchReg = MI->getOperand(1).getReg();
1892  .addReg(ARM::SP)
1893  .addReg(SrcReg)
1894  .addImm(8)
1895  // Predicate.
1896  .addImm(ARMCC::AL)
1897  .addReg(0));
1898 
1900  .addReg(ScratchReg)
1901  .addReg(SrcReg)
1902  .addImm(4)
1903  // Predicate.
1904  .addImm(ARMCC::AL)
1905  .addReg(0));
1906 
1907  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1908  // These platforms always use the same frame register
1910  .addReg(FramePtr)
1911  .addReg(SrcReg)
1912  .addImm(0)
1913  // Predicate.
1914  .addImm(ARMCC::AL)
1915  .addReg(0));
1916  } else {
1917  // If the calling code might use either R7 or R11 as
1918  // frame pointer register, restore it into both.
1920  .addReg(ARM::R7)
1921  .addReg(SrcReg)
1922  .addImm(0)
1923  // Predicate.
1924  .addImm(ARMCC::AL)
1925  .addReg(0));
1927  .addReg(ARM::R11)
1928  .addReg(SrcReg)
1929  .addImm(0)
1930  // Predicate.
1931  .addImm(ARMCC::AL)
1932  .addReg(0));
1933  }
1934 
1935  assert(Subtarget->hasV4TOps());
1937  .addReg(ScratchReg)
1938  // Predicate.
1939  .addImm(ARMCC::AL)
1940  .addReg(0));
1941  return;
1942  }
1943  case ARM::tInt_eh_sjlj_longjmp: {
1944  // ldr $scratch, [$src, #8]
1945  // mov sp, $scratch
1946  // ldr $scratch, [$src, #4]
1947  // ldr r7, [$src]
1948  // bx $scratch
1949  unsigned SrcReg = MI->getOperand(0).getReg();
1950  unsigned ScratchReg = MI->getOperand(1).getReg();
1951 
1953  .addReg(ScratchReg)
1954  .addReg(SrcReg)
1955  // The offset immediate is #8. The operand value is scaled by 4 for the
1956  // tLDR instruction.
1957  .addImm(2)
1958  // Predicate.
1959  .addImm(ARMCC::AL)
1960  .addReg(0));
1961 
1963  .addReg(ARM::SP)
1964  .addReg(ScratchReg)
1965  // Predicate.
1966  .addImm(ARMCC::AL)
1967  .addReg(0));
1968 
1970  .addReg(ScratchReg)
1971  .addReg(SrcReg)
1972  .addImm(1)
1973  // Predicate.
1974  .addImm(ARMCC::AL)
1975  .addReg(0));
1976 
1977  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1978  // These platforms always use the same frame register
1980  .addReg(FramePtr)
1981  .addReg(SrcReg)
1982  .addImm(0)
1983  // Predicate.
1984  .addImm(ARMCC::AL)
1985  .addReg(0));
1986  } else {
1987  // If the calling code might use either R7 or R11 as
1988  // frame pointer register, restore it into both.
1990  .addReg(ARM::R7)
1991  .addReg(SrcReg)
1992  .addImm(0)
1993  // Predicate.
1994  .addImm(ARMCC::AL)
1995  .addReg(0));
1997  .addReg(ARM::R11)
1998  .addReg(SrcReg)
1999  .addImm(0)
2000  // Predicate.
2001  .addImm(ARMCC::AL)
2002  .addReg(0));
2003  }
2004 
2006  .addReg(ScratchReg)
2007  // Predicate.
2008  .addImm(ARMCC::AL)
2009  .addReg(0));
2010  return;
2011  }
2012  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2013  // ldr.w r11, [$src, #0]
2014  // ldr.w sp, [$src, #8]
2015  // ldr.w pc, [$src, #4]
2016 
2017  unsigned SrcReg = MI->getOperand(0).getReg();
2018 
2019  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2020  .addReg(ARM::R11)
2021  .addReg(SrcReg)
2022  .addImm(0)
2023  // Predicate
2024  .addImm(ARMCC::AL)
2025  .addReg(0));
2026  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2027  .addReg(ARM::SP)
2028  .addReg(SrcReg)
2029  .addImm(8)
2030  // Predicate
2031  .addImm(ARMCC::AL)
2032  .addReg(0));
2033  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2034  .addReg(ARM::PC)
2035  .addReg(SrcReg)
2036  .addImm(4)
2037  // Predicate
2038  .addImm(ARMCC::AL)
2039  .addReg(0));
2040  return;
2041  }
2042  case ARM::PATCHABLE_FUNCTION_ENTER:
2044  return;
2045  case ARM::PATCHABLE_FUNCTION_EXIT:
2047  return;
2048  case ARM::PATCHABLE_TAIL_CALL:
2050  return;
2051  }
2052 
2053  MCInst TmpInst;
2054  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2055 
2056  EmitToStreamer(*OutStreamer, TmpInst);
2057 }
2058 
2059 //===----------------------------------------------------------------------===//
2060 // Target Registry Stuff
2061 //===----------------------------------------------------------------------===//
2062 
2063 // Force static initialization.
2064 extern "C" void LLVMInitializeARMAsmPrinter() {
2069 }
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
unsigned getTargetFlags() const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:445
MachineConstantPoolValue * MachineCPVal
union llvm::MachineConstantPoolEntry::@166 Val
The constant itself.
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:265
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:213
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
StringRef getTargetFeatureString() const
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:677
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
This class represents lattice values for constants.
Definition: AllocatorList.h:23
PointerTy getPointer() const
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:594
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:316
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:600
void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:614
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool hasV4TOps() const
Definition: ARMSubtarget.h:538
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void push_back(const T &Elt)
Definition: SmallVector.h:211
ARMConstantPoolValue - ARM specific constantpool value.
unsigned getReg() const
getReg - Returns the register number.
Target specific streamer interface.
Definition: MCStreamer.h:83
unsigned Reg
virtual void emitPad(int64_t Offset)
unsigned getSubReg() const
Global Offset Table, Thread Pointer Offset.
unsigned char getPCAdjustment() const
bool isTargetCOFF() const
Definition: ARMSubtarget.h:661
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
MachineBasicBlock reference.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the EmitInstruction() method to print assembly for each instruction...
virtual void finishAttributeSection()
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isThumb1Only() const
Definition: ARMSubtarget.h:719
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:682
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Global Offset Table, PC Relative.
Thread Pointer Offset.
Target & getTheThumbLETarget()
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
static bool isThumb(const MCSubtargetInfo &STI)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
void LLVMInitializeARMAsmPrinter()
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
return AArch64::GPR64RegClass contains(Reg)
bool genExecuteOnly() const
Definition: ARMSubtarget.h:638
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool isTargetELF() const
Definition: ARMSubtarget.h:662
ARMCP::ARMCPModifier getModifier() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
The address of a basic block.
Definition: Constants.h:839
MCContext & getContext() const
Definition: MCStreamer.h:250
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: ARMBaseInfo.h:253
Definition: BitVector.h:937
virtual void emitInst(uint32_t Inst, char Suffix='\0')
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const FeatureBitset & getFeatureBits() const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:469
unsigned SubReg
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
.data_region jt16
Definition: MCDirectives.h:59
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target & getTheARMBETarget()
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Context object for machine code objects.
Definition: MCContext.h:62
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:42
void EmitFunctionBody()
This method emits the body and trailer for a function.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file. ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:544
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:204
Target & getTheThumbBETarget()
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
IntType getInt() const
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:690
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
bool isTargetDarwin() const
Definition: ARMSubtarget.h:652
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
This class is a data container for one entry in a MachineConstantPool.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
StringRef getTargetCPU() const
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:265
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:128
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:159
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:99
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:731
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
.data_region jt32
Definition: MCDirectives.h:60
Address of a global value.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Streaming machine code generation interface.
Definition: MCStreamer.h:188
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:220
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:112
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
PointerIntPair - This class implements a pair of a pointer and small integer.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
MCSection * getNonLazySymbolPointerSection() const
void EmitAlignment(unsigned NumBits, const GlobalObject *GV=nullptr) const
Emit an alignment directive to the specified power of two boundary.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:435
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:50
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:771
Thread Local Storage (General Dynamic Mode)
const Triple & getTargetTriple() const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an &#39;S&#39; bit onto real opcodes.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Ty & getObjFileInfo()
Keep track of various per-function pieces of information for backends that would like to do so...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:624
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
FPDenormal::DenormalMode FPDenormalMode
FPDenormalMode - This flags specificies which denormal numbers the code is permitted to require...
const Constant * stripPointerCasts() const
Definition: Constant.h:177
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Abstract base class for all machine specific constantpool value subclasses.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:240
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
MCSection * getThreadLocalPointerSection() const
void EmitJumpTableInsts(const MachineInstr *MI)
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:209
void setOpcode(unsigned Op)
Definition: MCInst.h:170
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
bool isTargetAEABI() const
Definition: ARMSubtarget.h:672
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:440
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
.indirect_symbol (MachO)
Definition: MCDirectives.h:32
unsigned getOriginalCPIdx(unsigned CloneIdx) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:232
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:203
StubValueTy & getGVStubEntry(MCSymbol *Sym)
.syntax (ARM/ELF)
Definition: MCDirectives.h:49
MCSymbol * getCurExceptionSym()
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
bool isROPI() const
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
FunctionNumber(functionNumber)
Definition: LLParser.cpp:2739
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:350
Section Relative (Windows TLS)
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:461
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:680
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
TargetOptions Options
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
void EmitJumpTableAddrs(const MachineInstr *MI)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:38
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:597
Generic base class for all target subtargets.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:128
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool hasV5TOps() const
Definition: ARMSubtarget.h:539
Type * getType() const
getType - get type of this MachineConstantPoolValue.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const Module * getModule() const
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
const std::string & getModuleInlineAsm() const
Get any module-scope inline assembly blocks.
Definition: Module.h:248
bool isTargetMachO() const
Definition: ARMSubtarget.h:663
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
.data_region jt8
Definition: MCDirectives.h:58
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:72
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:351
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:278
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:569
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
static const unsigned FramePtr
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool isTargetWindows() const
Definition: ARMSubtarget.h:659
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:217
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Address of indexed Constant in Constant Pool.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
Target & getTheARMLETarget()
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
void EmitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:294
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
.end_data_region
Definition: MCDirectives.h:61
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:244
bool isImplicit() const
virtual void switchVendor(StringRef Vendor)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
A function that returns a base type.
Definition: COFF.h:261