LLVM  8.0.0svn
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMAsmPrinter.h"
16 #include "ARM.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "asm-printer"
54 
56  std::unique_ptr<MCStreamer> Streamer)
57  : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
58  InConstantPool(false), OptimizationGoals(-1) {}
59 
61  // Make sure to terminate any constant pools that were at the end
62  // of the function.
63  if (!InConstantPool)
64  return;
65  InConstantPool = false;
66  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
67 }
68 
70  if (AFI->isThumbFunction()) {
71  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
72  OutStreamer->EmitThumbFunc(CurrentFnSym);
73  } else {
74  OutStreamer->EmitAssemblerFlag(MCAF_Code32);
75  }
76  OutStreamer->EmitLabel(CurrentFnSym);
77 }
78 
80  uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
81  assert(Size && "C++ constructor pointer had zero size!");
82 
84  assert(GV && "C++ constructor pointer was not a GlobalValue!");
85 
86  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
88  (Subtarget->isTargetELF()
91  OutContext);
92 
93  OutStreamer->EmitValue(E, Size);
94 }
95 
97  if (PromotedGlobals.count(GV))
98  // The global was promoted into a constant pool. It should not be emitted.
99  return;
101 }
102 
103 /// runOnMachineFunction - This uses the EmitInstruction()
104 /// method to print assembly for each instruction.
105 ///
107  AFI = MF.getInfo<ARMFunctionInfo>();
108  MCP = MF.getConstantPool();
109  Subtarget = &MF.getSubtarget<ARMSubtarget>();
110 
112  const Function &F = MF.getFunction();
113  const TargetMachine& TM = MF.getTarget();
114 
115  // Collect all globals that had their storage promoted to a constant pool.
116  // Functions are emitted before variables, so this accumulates promoted
117  // globals from all functions in PromotedGlobals.
118  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
119  PromotedGlobals.insert(GV);
120 
121  // Calculate this function's optimization goal.
122  unsigned OptimizationGoal;
123  if (F.hasFnAttribute(Attribute::OptimizeNone))
124  // For best debugging illusion, speed and small size sacrificed
125  OptimizationGoal = 6;
126  else if (F.optForMinSize())
127  // Aggressively for small size, speed and debug illusion sacrificed
128  OptimizationGoal = 4;
129  else if (F.optForSize())
130  // For small size, but speed and debugging illusion preserved
131  OptimizationGoal = 3;
132  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
133  // Aggressively for speed, small size and debug illusion sacrificed
134  OptimizationGoal = 2;
135  else if (TM.getOptLevel() > CodeGenOpt::None)
136  // For speed, but small size and good debug illusion preserved
137  OptimizationGoal = 1;
138  else // TM.getOptLevel() == CodeGenOpt::None
139  // For good debugging, but speed and small size preserved
140  OptimizationGoal = 5;
141 
142  // Combine a new optimization goal with existing ones.
143  if (OptimizationGoals == -1) // uninitialized goals
144  OptimizationGoals = OptimizationGoal;
145  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
146  OptimizationGoals = 0;
147 
148  if (Subtarget->isTargetCOFF()) {
149  bool Internal = F.hasInternalLinkage();
153 
154  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
155  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
156  OutStreamer->EmitCOFFSymbolType(Type);
157  OutStreamer->EndCOFFSymbolDef();
158  }
159 
160  // Emit the rest of the function body.
162 
163  // Emit the XRay table for this function.
164  emitXRayTable();
165 
166  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
167  // These are created per function, rather than per TU, since it's
168  // relatively easy to exceed the thumb branch range within a TU.
169  if (! ThumbIndirectPads.empty()) {
170  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
171  EmitAlignment(1);
172  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
173  OutStreamer->EmitLabel(TIP.second);
175  .addReg(TIP.first)
176  // Add predicate operands.
177  .addImm(ARMCC::AL)
178  .addReg(0));
179  }
180  ThumbIndirectPads.clear();
181  }
182 
183  // We didn't modify anything.
184  return false;
185 }
186 
188  raw_ostream &O) {
189  const MachineOperand &MO = MI->getOperand(OpNum);
190  unsigned TF = MO.getTargetFlags();
191 
192  switch (MO.getType()) {
193  default: llvm_unreachable("<unknown operand type>");
195  unsigned Reg = MO.getReg();
197  assert(!MO.getSubReg() && "Subregs should be eliminated!");
198  if(ARM::GPRPairRegClass.contains(Reg)) {
199  const MachineFunction &MF = *MI->getParent()->getParent();
201  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
202  }
204  break;
205  }
207  int64_t Imm = MO.getImm();
208  O << '#';
209  if (TF == ARMII::MO_LO16)
210  O << ":lower16:";
211  else if (TF == ARMII::MO_HI16)
212  O << ":upper16:";
213  O << Imm;
214  break;
215  }
217  MO.getMBB()->getSymbol()->print(O, MAI);
218  return;
220  const GlobalValue *GV = MO.getGlobal();
221  if (TF & ARMII::MO_LO16)
222  O << ":lower16:";
223  else if (TF & ARMII::MO_HI16)
224  O << ":upper16:";
225  GetARMGVSymbol(GV, TF)->print(O, MAI);
226 
227  printOffset(MO.getOffset(), O);
228  break;
229  }
231  if (Subtarget->genExecuteOnly())
232  llvm_unreachable("execute-only should not generate constant pools");
233  GetCPISymbol(MO.getIndex())->print(O, MAI);
234  break;
235  }
236 }
237 
238 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
239  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
240  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
241  const DataLayout &DL = getDataLayout();
243  "CPI" + Twine(getFunctionNumber()) + "_" +
244  Twine(CPID));
245 }
246 
247 //===--------------------------------------------------------------------===//
248 
249 MCSymbol *ARMAsmPrinter::
250 GetARMJTIPICJumpTableLabel(unsigned uid) const {
251  const DataLayout &DL = getDataLayout();
253  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
254  << getFunctionNumber() << '_' << uid;
255  return OutContext.getOrCreateSymbol(Name);
256 }
257 
258 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
259  unsigned AsmVariant, const char *ExtraCode,
260  raw_ostream &O) {
261  // Does this asm operand have a single letter operand modifier?
262  if (ExtraCode && ExtraCode[0]) {
263  if (ExtraCode[1] != 0) return true; // Unknown modifier.
264 
265  switch (ExtraCode[0]) {
266  default:
267  // See if this is a generic print operand
268  return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
269  case 'a': // Print as a memory address.
270  if (MI->getOperand(OpNum).isReg()) {
271  O << "["
273  << "]";
274  return false;
275  }
277  case 'c': // Don't print "#" before an immediate operand.
278  if (!MI->getOperand(OpNum).isImm())
279  return true;
280  O << MI->getOperand(OpNum).getImm();
281  return false;
282  case 'P': // Print a VFP double precision register.
283  case 'q': // Print a NEON quad precision register.
284  printOperand(MI, OpNum, O);
285  return false;
286  case 'y': // Print a VFP single precision register as indexed double.
287  if (MI->getOperand(OpNum).isReg()) {
288  unsigned Reg = MI->getOperand(OpNum).getReg();
290  // Find the 'd' register that has this 's' register as a sub-register,
291  // and determine the lane number.
292  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
293  if (!ARM::DPRRegClass.contains(*SR))
294  continue;
295  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
296  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
297  return false;
298  }
299  }
300  return true;
301  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
302  if (!MI->getOperand(OpNum).isImm())
303  return true;
304  O << ~(MI->getOperand(OpNum).getImm());
305  return false;
306  case 'L': // The low 16 bits of an immediate constant.
307  if (!MI->getOperand(OpNum).isImm())
308  return true;
309  O << (MI->getOperand(OpNum).getImm() & 0xffff);
310  return false;
311  case 'M': { // A register range suitable for LDM/STM.
312  if (!MI->getOperand(OpNum).isReg())
313  return true;
314  const MachineOperand &MO = MI->getOperand(OpNum);
315  unsigned RegBegin = MO.getReg();
316  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
317  // already got the operands in registers that are operands to the
318  // inline asm statement.
319  O << "{";
320  if (ARM::GPRPairRegClass.contains(RegBegin)) {
322  unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
323  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
324  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
325  }
326  O << ARMInstPrinter::getRegisterName(RegBegin);
327 
328  // FIXME: The register allocator not only may not have given us the
329  // registers in sequence, but may not be in ascending registers. This
330  // will require changes in the register allocator that'll need to be
331  // propagated down here if the operands change.
332  unsigned RegOps = OpNum + 1;
333  while (MI->getOperand(RegOps).isReg()) {
334  O << ", "
336  RegOps++;
337  }
338 
339  O << "}";
340 
341  return false;
342  }
343  case 'R': // The most significant register of a pair.
344  case 'Q': { // The least significant register of a pair.
345  if (OpNum == 0)
346  return true;
347  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
348  if (!FlagsOP.isImm())
349  return true;
350  unsigned Flags = FlagsOP.getImm();
351 
352  // This operand may not be the one that actually provides the register. If
353  // it's tied to a previous one then we should refer instead to that one
354  // for registers and their classes.
355  unsigned TiedIdx;
356  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
357  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
358  unsigned OpFlags = MI->getOperand(OpNum).getImm();
359  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
360  }
361  Flags = MI->getOperand(OpNum).getImm();
362 
363  // Later code expects OpNum to be pointing at the register rather than
364  // the flags.
365  OpNum += 1;
366  }
367 
368  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
369  unsigned RC;
371  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
372  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
373  if (NumVals != 1)
374  return true;
375  const MachineOperand &MO = MI->getOperand(OpNum);
376  if (!MO.isReg())
377  return true;
379  unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
380  ARM::gsub_0 : ARM::gsub_1);
382  return false;
383  }
384  if (NumVals != 2)
385  return true;
386  unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
387  if (RegOp >= MI->getNumOperands())
388  return true;
389  const MachineOperand &MO = MI->getOperand(RegOp);
390  if (!MO.isReg())
391  return true;
392  unsigned Reg = MO.getReg();
394  return false;
395  }
396 
397  case 'e': // The low doubleword register of a NEON quad register.
398  case 'f': { // The high doubleword register of a NEON quad register.
399  if (!MI->getOperand(OpNum).isReg())
400  return true;
401  unsigned Reg = MI->getOperand(OpNum).getReg();
402  if (!ARM::QPRRegClass.contains(Reg))
403  return true;
405  unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
406  ARM::dsub_0 : ARM::dsub_1);
407  O << ARMInstPrinter::getRegisterName(SubReg);
408  return false;
409  }
410 
411  // This modifier is not yet supported.
412  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
413  return true;
414  case 'H': { // The highest-numbered register of a pair.
415  const MachineOperand &MO = MI->getOperand(OpNum);
416  if (!MO.isReg())
417  return true;
418  const MachineFunction &MF = *MI->getParent()->getParent();
420  unsigned Reg = MO.getReg();
421  if(!ARM::GPRPairRegClass.contains(Reg))
422  return false;
423  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
425  return false;
426  }
427  }
428  }
429 
430  printOperand(MI, OpNum, O);
431  return false;
432 }
433 
435  unsigned OpNum, unsigned AsmVariant,
436  const char *ExtraCode,
437  raw_ostream &O) {
438  // Does this asm operand have a single letter operand modifier?
439  if (ExtraCode && ExtraCode[0]) {
440  if (ExtraCode[1] != 0) return true; // Unknown modifier.
441 
442  switch (ExtraCode[0]) {
443  case 'A': // A memory operand for a VLD1/VST1 instruction.
444  default: return true; // Unknown modifier.
445  case 'm': // The base register of a memory operand.
446  if (!MI->getOperand(OpNum).isReg())
447  return true;
449  return false;
450  }
451  }
452 
453  const MachineOperand &MO = MI->getOperand(OpNum);
454  assert(MO.isReg() && "unexpected inline asm memory operand");
455  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
456  return false;
457 }
458 
459 static bool isThumb(const MCSubtargetInfo& STI) {
460  return STI.getFeatureBits()[ARM::ModeThumb];
461 }
462 
464  const MCSubtargetInfo *EndInfo) const {
465  // If either end mode is unknown (EndInfo == NULL) or different than
466  // the start mode, then restore the start mode.
467  const bool WasThumb = isThumb(StartInfo);
468  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
469  OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
470  }
471 }
472 
474  const Triple &TT = TM.getTargetTriple();
475  // Use unified assembler syntax.
476  OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
477 
478  // Emit ARM Build Attributes
479  if (TT.isOSBinFormatELF())
480  emitAttributes();
481 
482  // Use the triple's architecture and subarchitecture to determine
483  // if we're thumb for the purposes of the top level code16 assembler
484  // flag.
485  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
486  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
487 }
488 
489 static void
492  // L_foo$stub:
493  OutStreamer.EmitLabel(StubLabel);
494  // .indirect_symbol _foo
495  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
496 
497  if (MCSym.getInt())
498  // External to current translation unit.
499  OutStreamer.EmitIntValue(0, 4/*size*/);
500  else
501  // Internal to current translation unit.
502  //
503  // When we place the LSDA into the TEXT section, the type info
504  // pointers need to be indirect and pc-rel. We accomplish this by
505  // using NLPs; however, sometimes the types are local to the file.
506  // We need to fill in the value for the NLP in those cases.
507  OutStreamer.EmitValue(
508  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
509  4 /*size*/);
510 }
511 
512 
514  const Triple &TT = TM.getTargetTriple();
515  if (TT.isOSBinFormatMachO()) {
516  // All darwin targets use mach-o.
517  const TargetLoweringObjectFileMachO &TLOFMacho =
518  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
519  MachineModuleInfoMachO &MMIMacho =
521 
522  // Output non-lazy-pointers for external and common global variables.
524 
525  if (!Stubs.empty()) {
526  // Switch with ".non_lazy_symbol_pointer" directive.
527  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
528  EmitAlignment(2);
529 
530  for (auto &Stub : Stubs)
531  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
532 
533  Stubs.clear();
534  OutStreamer->AddBlankLine();
535  }
536 
537  Stubs = MMIMacho.GetThreadLocalGVStubList();
538  if (!Stubs.empty()) {
539  // Switch with ".non_lazy_symbol_pointer" directive.
540  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
541  EmitAlignment(2);
542 
543  for (auto &Stub : Stubs)
544  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
545 
546  Stubs.clear();
547  OutStreamer->AddBlankLine();
548  }
549 
550  // Funny Darwin hack: This flag tells the linker that no global symbols
551  // contain code that falls through to other global symbols (e.g. the obvious
552  // implementation of multiple entry points). If this doesn't occur, the
553  // linker can safely perform dead code stripping. Since LLVM never
554  // generates code that does this, it is always safe to set.
555  OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
556  }
557 
558  // The last attribute to be emitted is ABI_optimization_goals
559  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
560  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
561 
562  if (OptimizationGoals > 0 &&
563  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
564  Subtarget->isTargetMuslAEABI()))
566  OptimizationGoals = -1;
567 
569 }
570 
571 //===----------------------------------------------------------------------===//
572 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
573 // FIXME:
574 // The following seem like one-off assembler flags, but they actually need
575 // to appear in the .ARM.attributes section in ELF.
576 // Instead of subclassing the MCELFStreamer, we do the work here.
577 
578 // Returns true if all functions have the same function attribute value.
579 // It also returns true when the module has no functions.
581  StringRef Value) {
582  return !any_of(M, [&](const Function &F) {
583  return F.getFnAttribute(Attr).getValueAsString() != Value;
584  });
585 }
586 
587 void ARMAsmPrinter::emitAttributes() {
588  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
589  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
590 
592 
593  ATS.switchVendor("aeabi");
594 
595  // Compute ARM ELF Attributes based on the default subtarget that
596  // we'd have constructed. The existing ARM behavior isn't LTO clean
597  // anyhow.
598  // FIXME: For ifunc related functions we could iterate over and look
599  // for a feature string that doesn't match the default one.
600  const Triple &TT = TM.getTargetTriple();
601  StringRef CPU = TM.getTargetCPU();
603  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
604  if (!FS.empty()) {
605  if (!ArchFS.empty())
606  ArchFS = (Twine(ArchFS) + "," + FS).str();
607  else
608  ArchFS = FS;
609  }
610  const ARMBaseTargetMachine &ATM =
611  static_cast<const ARMBaseTargetMachine &>(TM);
612  const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
613 
614  // Emit build attributes for the available hardware.
615  ATS.emitTargetAttributes(STI);
616 
617  // RW data addressing.
618  if (isPositionIndependent()) {
621  } else if (STI.isRWPI()) {
622  // RWPI specific attributes.
625  }
626 
627  // RO data addressing.
628  if (isPositionIndependent() || STI.isROPI()) {
631  }
632 
633  // GOT use.
634  if (isPositionIndependent()) {
637  } else {
640  }
641 
642  // Set FP Denormals.
644  "denormal-fp-math",
645  "preserve-sign") ||
650  "denormal-fp-math",
651  "positive-zero") ||
655  else if (!TM.Options.UnsafeFPMath)
658  else {
659  if (!STI.hasVFP2()) {
660  // When the target doesn't have an FPU (by design or
661  // intention), the assumptions made on the software support
662  // mirror that of the equivalent hardware support *if it
663  // existed*. For v7 and better we indicate that denormals are
664  // flushed preserving sign, and for V6 we indicate that
665  // denormals are flushed to positive zero.
666  if (STI.hasV7Ops())
669  } else if (STI.hasVFP3()) {
670  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
671  // the sign bit of the zero matches the sign bit of the input or
672  // result that is being flushed to zero.
675  }
676  // For VFPv2 implementations it is implementation defined as
677  // to whether denormals are flushed to positive zero or to
678  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
679  // LLVM has chosen to flush this to positive zero (most likely for
680  // GCC compatibility), so that's the chosen value here (the
681  // absence of its emission implies zero).
682  }
683 
684  // Set FP exceptions and rounding
686  "no-trapping-math", "true") ||
690  else if (!TM.Options.UnsafeFPMath) {
692 
693  // If the user has permitted this code to choose the IEEE 754
694  // rounding at run-time, emit the rounding attribute.
697  }
698 
699  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
700  // equivalent of GCC's -ffinite-math-only flag.
704  else
707 
708  // FIXME: add more flags to ARMBuildAttributes.h
709  // 8-bytes alignment stuff.
712 
713  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
714  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
716 
717  // FIXME: To support emitting this build attribute as GCC does, the
718  // -mfp16-format option and associated plumbing must be
719  // supported. For now the __fp16 type is exposed by default, so this
720  // attribute should be emitted with value 1.
723 
724  if (MMI) {
725  if (const Module *SourceModule = MMI->getModule()) {
726  // ABI_PCS_wchar_t to indicate wchar_t width
727  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
728  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
729  SourceModule->getModuleFlag("wchar_size"))) {
730  int WCharWidth = WCharWidthValue->getZExtValue();
731  assert((WCharWidth == 2 || WCharWidth == 4) &&
732  "wchar_t width must be 2 or 4 bytes");
734  }
735 
736  // ABI_enum_size to indicate enum width
737  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
738  // (all enums contain a value needing 32 bits to encode).
739  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
740  SourceModule->getModuleFlag("min_enum_size"))) {
741  int EnumWidth = EnumWidthValue->getZExtValue();
742  assert((EnumWidth == 1 || EnumWidth == 4) &&
743  "Minimum enum width must be 1 or 4 bytes");
744  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
745  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
746  }
747  }
748  }
749 
750  // We currently do not support using R9 as the TLS pointer.
751  if (STI.isRWPI())
754  else if (STI.isR9Reserved())
757  else
760 }
761 
762 //===----------------------------------------------------------------------===//
763 
765  unsigned LabelId, MCContext &Ctx) {
766 
767  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
768  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
769  return Label;
770 }
771 
774  switch (Modifier) {
775  case ARMCP::no_modifier:
777  case ARMCP::TLSGD:
779  case ARMCP::TPOFF:
781  case ARMCP::GOTTPOFF:
783  case ARMCP::SBREL:
785  case ARMCP::GOT_PREL:
787  case ARMCP::SECREL:
789  }
790  llvm_unreachable("Invalid ARMCPModifier!");
791 }
792 
793 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
794  unsigned char TargetFlags) {
795  if (Subtarget->isTargetMachO()) {
796  bool IsIndirect =
797  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
798 
799  if (!IsIndirect)
800  return getSymbol(GV);
801 
802  // FIXME: Remove this when Darwin transition to @GOT like syntax.
803  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
804  MachineModuleInfoMachO &MMIMachO =
807  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
808  : MMIMachO.getGVStubEntry(MCSym);
809 
810  if (!StubSym.getPointer())
812  !GV->hasInternalLinkage());
813  return MCSym;
814  } else if (Subtarget->isTargetCOFF()) {
815  assert(Subtarget->isTargetWindows() &&
816  "Windows is the only supported COFF target");
817 
818  bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
819  if (!IsIndirect)
820  return getSymbol(GV);
821 
823  Name = "__imp_";
824  getNameWithPrefix(Name, GV);
825 
826  return OutContext.getOrCreateSymbol(Name);
827  } else if (Subtarget->isTargetELF()) {
828  return getSymbol(GV);
829  }
830  llvm_unreachable("unexpected target");
831 }
832 
833 void ARMAsmPrinter::
835  const DataLayout &DL = getDataLayout();
836  int Size = DL.getTypeAllocSize(MCPV->getType());
837 
838  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
839 
840  if (ACPV->isPromotedGlobal()) {
841  // This constant pool entry is actually a global whose storage has been
842  // promoted into the constant pool. This global may be referenced still
843  // by debug information, and due to the way AsmPrinter is set up, the debug
844  // info is immutable by the time we decide to promote globals to constant
845  // pools. Because of this, we need to ensure we emit a symbol for the global
846  // with private linkage (the default) so debug info can refer to it.
847  //
848  // However, if this global is promoted into several functions we must ensure
849  // we don't try and emit duplicate symbols!
850  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
851  for (const auto *GV : ACPC->promotedGlobals()) {
852  if (!EmittedPromotedGlobalLabels.count(GV)) {
853  MCSymbol *GVSym = getSymbol(GV);
854  OutStreamer->EmitLabel(GVSym);
855  EmittedPromotedGlobalLabels.insert(GV);
856  }
857  }
858  return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
859  }
860 
861  MCSymbol *MCSym;
862  if (ACPV->isLSDA()) {
863  MCSym = getCurExceptionSym();
864  } else if (ACPV->isBlockAddress()) {
865  const BlockAddress *BA =
866  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
867  MCSym = GetBlockAddressSymbol(BA);
868  } else if (ACPV->isGlobalValue()) {
869  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
870 
871  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
872  // flag the global as MO_NONLAZY.
873  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
874  MCSym = GetARMGVSymbol(GV, TF);
875  } else if (ACPV->isMachineBasicBlock()) {
876  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
877  MCSym = MBB->getSymbol();
878  } else {
879  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
880  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
881  MCSym = GetExternalSymbolSymbol(Sym);
882  }
883 
884  // Create an MCSymbol for the reference.
885  const MCExpr *Expr =
887  OutContext);
888 
889  if (ACPV->getPCAdjustment()) {
890  MCSymbol *PCLabel =
892  ACPV->getLabelId(), OutContext);
893  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
894  PCRelExpr =
895  MCBinaryExpr::createAdd(PCRelExpr,
897  OutContext),
898  OutContext);
899  if (ACPV->mustAddCurrentAddress()) {
900  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
901  // label, so just emit a local label end reference that instead.
903  OutStreamer->EmitLabel(DotSym);
904  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
905  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
906  }
907  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
908  }
909  OutStreamer->EmitValue(Expr, Size);
910 }
911 
913  const MachineOperand &MO1 = MI->getOperand(1);
914  unsigned JTI = MO1.getIndex();
915 
916  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
917  // ARM mode tables.
918  EmitAlignment(2);
919 
920  // Emit a label for the jump table.
921  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
922  OutStreamer->EmitLabel(JTISymbol);
923 
924  // Mark the jump table as data-in-code.
925  OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
926 
927  // Emit each entry of the table.
928  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
929  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
930  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
931 
932  for (MachineBasicBlock *MBB : JTBBs) {
933  // Construct an MCExpr for the entry. We want a value of the form:
934  // (BasicBlockAddr - TableBeginAddr)
935  //
936  // For example, a table with entries jumping to basic blocks BB0 and BB1
937  // would look like:
938  // LJTI_0_0:
939  // .word (LBB0 - LJTI_0_0)
940  // .word (LBB1 - LJTI_0_0)
941  const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
942 
943  if (isPositionIndependent() || Subtarget->isROPI())
944  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
945  OutContext),
946  OutContext);
947  // If we're generating a table of Thumb addresses in static relocation
948  // model, we need to add one to keep interworking correctly.
949  else if (AFI->isThumbFunction())
951  OutContext);
952  OutStreamer->EmitValue(Expr, 4);
953  }
954  // Mark the end of jump table data-in-code region.
955  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
956 }
957 
959  const MachineOperand &MO1 = MI->getOperand(1);
960  unsigned JTI = MO1.getIndex();
961 
962  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
963  // ARM mode tables.
964  EmitAlignment(2);
965 
966  // Emit a label for the jump table.
967  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
968  OutStreamer->EmitLabel(JTISymbol);
969 
970  // Emit each entry of the table.
971  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
972  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
973  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
974 
975  for (MachineBasicBlock *MBB : JTBBs) {
976  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
977  OutContext);
978  // If this isn't a TBB or TBH, the entries are direct branch instructions.
980  .addExpr(MBBSymbolExpr)
981  .addImm(ARMCC::AL)
982  .addReg(0));
983  }
984 }
985 
987  unsigned OffsetWidth) {
988  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
989  const MachineOperand &MO1 = MI->getOperand(1);
990  unsigned JTI = MO1.getIndex();
991 
992  if (Subtarget->isThumb1Only())
993  EmitAlignment(2);
994 
995  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
996  OutStreamer->EmitLabel(JTISymbol);
997 
998  // Emit each entry of the table.
999  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1000  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1001  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1002 
1003  // Mark the jump table as data-in-code.
1004  OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1006 
1007  for (auto MBB : JTBBs) {
1008  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1009  OutContext);
1010  // Otherwise it's an offset from the dispatch instruction. Construct an
1011  // MCExpr for the entry. We want a value of the form:
1012  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1013  //
1014  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1015  // would look like:
1016  // LJTI_0_0:
1017  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1018  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1019  // where LCPI0_0 is a label defined just before the TBB instruction using
1020  // this table.
1021  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1022  const MCExpr *Expr = MCBinaryExpr::createAdd(
1025  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1027  OutContext);
1028  OutStreamer->EmitValue(Expr, OffsetWidth);
1029  }
1030  // Mark the end of jump table data-in-code region. 32-bit offsets use
1031  // actual branch instructions here, so we don't mark those as a data-region
1032  // at all.
1033  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1034 
1035  // Make sure the next instruction is 2-byte aligned.
1036  EmitAlignment(1);
1037 }
1038 
1039 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1041  "Only instruction which are involved into frame setup code are allowed");
1042 
1043  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1044  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1045  const MachineFunction &MF = *MI->getParent()->getParent();
1046  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1047  const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1048 
1049  unsigned FramePtr = RegInfo->getFrameRegister(MF);
1050  unsigned Opc = MI->getOpcode();
1051  unsigned SrcReg, DstReg;
1052 
1053  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1054  // Two special cases:
1055  // 1) tPUSH does not have src/dst regs.
1056  // 2) for Thumb1 code we sometimes materialize the constant via constpool
1057  // load. Yes, this is pretty fragile, but for now I don't see better
1058  // way... :(
1059  SrcReg = DstReg = ARM::SP;
1060  } else {
1061  SrcReg = MI->getOperand(1).getReg();
1062  DstReg = MI->getOperand(0).getReg();
1063  }
1064 
1065  // Try to figure out the unwinding opcode out of src / dst regs.
1066  if (MI->mayStore()) {
1067  // Register saves.
1068  assert(DstReg == ARM::SP &&
1069  "Only stack pointer as a destination reg is supported");
1070 
1071  SmallVector<unsigned, 4> RegList;
1072  // Skip src & dst reg, and pred ops.
1073  unsigned StartOp = 2 + 2;
1074  // Use all the operands.
1075  unsigned NumOffset = 0;
1076  // Amount of SP adjustment folded into a push.
1077  unsigned Pad = 0;
1078 
1079  switch (Opc) {
1080  default:
1081  MI->print(errs());
1082  llvm_unreachable("Unsupported opcode for unwinding information");
1083  case ARM::tPUSH:
1084  // Special case here: no src & dst reg, but two extra imp ops.
1085  StartOp = 2; NumOffset = 2;
1087  case ARM::STMDB_UPD:
1088  case ARM::t2STMDB_UPD:
1089  case ARM::VSTMDDB_UPD:
1090  assert(SrcReg == ARM::SP &&
1091  "Only stack pointer as a source reg is supported");
1092  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1093  i != NumOps; ++i) {
1094  const MachineOperand &MO = MI->getOperand(i);
1095  // Actually, there should never be any impdef stuff here. Skip it
1096  // temporary to workaround PR11902.
1097  if (MO.isImplicit())
1098  continue;
1099  // Registers, pushed as a part of folding an SP update into the
1100  // push instruction are marked as undef and should not be
1101  // restored when unwinding, because the function can modify the
1102  // corresponding stack slots.
1103  if (MO.isUndef()) {
1104  assert(RegList.empty() &&
1105  "Pad registers must come before restored ones");
1106  Pad += 4;
1107  continue;
1108  }
1109  RegList.push_back(MO.getReg());
1110  }
1111  break;
1112  case ARM::STR_PRE_IMM:
1113  case ARM::STR_PRE_REG:
1114  case ARM::t2STR_PRE:
1115  assert(MI->getOperand(2).getReg() == ARM::SP &&
1116  "Only stack pointer as a source reg is supported");
1117  RegList.push_back(SrcReg);
1118  break;
1119  }
1121  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1122  // Account for the SP adjustment, folded into the push.
1123  if (Pad)
1124  ATS.emitPad(Pad);
1125  }
1126  } else {
1127  // Changes of stack / frame pointer.
1128  if (SrcReg == ARM::SP) {
1129  int64_t Offset = 0;
1130  switch (Opc) {
1131  default:
1132  MI->print(errs());
1133  llvm_unreachable("Unsupported opcode for unwinding information");
1134  case ARM::MOVr:
1135  case ARM::tMOVr:
1136  Offset = 0;
1137  break;
1138  case ARM::ADDri:
1139  case ARM::t2ADDri:
1140  Offset = -MI->getOperand(2).getImm();
1141  break;
1142  case ARM::SUBri:
1143  case ARM::t2SUBri:
1144  Offset = MI->getOperand(2).getImm();
1145  break;
1146  case ARM::tSUBspi:
1147  Offset = MI->getOperand(2).getImm()*4;
1148  break;
1149  case ARM::tADDspi:
1150  case ARM::tADDrSPi:
1151  Offset = -MI->getOperand(2).getImm()*4;
1152  break;
1153  case ARM::tLDRpci: {
1154  // Grab the constpool index and check, whether it corresponds to
1155  // original or cloned constpool entry.
1156  unsigned CPI = MI->getOperand(1).getIndex();
1157  const MachineConstantPool *MCP = MF.getConstantPool();
1158  if (CPI >= MCP->getConstants().size())
1159  CPI = AFI.getOriginalCPIdx(CPI);
1160  assert(CPI != -1U && "Invalid constpool index");
1161 
1162  // Derive the actual offset.
1163  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1164  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1165  // FIXME: Check for user, it should be "add" instruction!
1166  Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1167  break;
1168  }
1169  }
1170 
1172  if (DstReg == FramePtr && FramePtr != ARM::SP)
1173  // Set-up of the frame pointer. Positive values correspond to "add"
1174  // instruction.
1175  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1176  else if (DstReg == ARM::SP) {
1177  // Change of SP by an offset. Positive values correspond to "sub"
1178  // instruction.
1179  ATS.emitPad(Offset);
1180  } else {
1181  // Move of SP to a register. Positive values correspond to an "add"
1182  // instruction.
1183  ATS.emitMovSP(DstReg, -Offset);
1184  }
1185  }
1186  } else if (DstReg == ARM::SP) {
1187  MI->print(errs());
1188  llvm_unreachable("Unsupported opcode for unwinding information");
1189  }
1190  else {
1191  MI->print(errs());
1192  llvm_unreachable("Unsupported opcode for unwinding information");
1193  }
1194  }
1195 }
1196 
1197 // Simple pseudo-instructions have their lowering (with expansion to real
1198 // instructions) auto-generated.
1199 #include "ARMGenMCPseudoLowering.inc"
1200 
1202  const DataLayout &DL = getDataLayout();
1203  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1204  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1205 
1206  const MachineFunction &MF = *MI->getParent()->getParent();
1207  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1208  unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1209 
1210  // If we just ended a constant pool, mark it as such.
1211  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1212  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1213  InConstantPool = false;
1214  }
1215 
1216  // Emit unwinding stuff for frame-related instructions
1217  if (Subtarget->isTargetEHABICompatible() &&
1219  EmitUnwindingInstruction(MI);
1220 
1221  // Do any auto-generated pseudo lowerings.
1222  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1223  return;
1224 
1226  "Pseudo flag setting opcode should be expanded early");
1227 
1228  // Check for manual lowerings.
1229  unsigned Opc = MI->getOpcode();
1230  switch (Opc) {
1231  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1232  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1233  case ARM::LEApcrel:
1234  case ARM::tLEApcrel:
1235  case ARM::t2LEApcrel: {
1236  // FIXME: Need to also handle globals and externals
1237  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1239  ARM::t2LEApcrel ? ARM::t2ADR
1240  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1241  : ARM::ADR))
1242  .addReg(MI->getOperand(0).getReg())
1243  .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1244  // Add predicate operands.
1245  .addImm(MI->getOperand(2).getImm())
1246  .addReg(MI->getOperand(3).getReg()));
1247  return;
1248  }
1249  case ARM::LEApcrelJT:
1250  case ARM::tLEApcrelJT:
1251  case ARM::t2LEApcrelJT: {
1252  MCSymbol *JTIPICSymbol =
1253  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1255  ARM::t2LEApcrelJT ? ARM::t2ADR
1256  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1257  : ARM::ADR))
1258  .addReg(MI->getOperand(0).getReg())
1259  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1260  // Add predicate operands.
1261  .addImm(MI->getOperand(2).getImm())
1262  .addReg(MI->getOperand(3).getReg()));
1263  return;
1264  }
1265  // Darwin call instructions are just normal call instructions with different
1266  // clobber semantics (they clobber R9).
1267  case ARM::BX_CALL: {
1269  .addReg(ARM::LR)
1270  .addReg(ARM::PC)
1271  // Add predicate operands.
1272  .addImm(ARMCC::AL)
1273  .addReg(0)
1274  // Add 's' bit operand (always reg0 for this)
1275  .addReg(0));
1276 
1277  assert(Subtarget->hasV4TOps());
1279  .addReg(MI->getOperand(0).getReg()));
1280  return;
1281  }
1282  case ARM::tBX_CALL: {
1283  if (Subtarget->hasV5TOps())
1284  llvm_unreachable("Expected BLX to be selected for v5t+");
1285 
1286  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1287  // that the saved lr has its LSB set correctly (the arch doesn't
1288  // have blx).
1289  // So here we generate a bl to a small jump pad that does bx rN.
1290  // The jump pads are emitted after the function body.
1291 
1292  unsigned TReg = MI->getOperand(0).getReg();
1293  MCSymbol *TRegSym = nullptr;
1294  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1295  if (TIP.first == TReg) {
1296  TRegSym = TIP.second;
1297  break;
1298  }
1299  }
1300 
1301  if (!TRegSym) {
1302  TRegSym = OutContext.createTempSymbol();
1303  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1304  }
1305 
1306  // Create a link-saving branch to the Reg Indirect Jump Pad.
1308  // Predicate comes first here.
1309  .addImm(ARMCC::AL).addReg(0)
1310  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1311  return;
1312  }
1313  case ARM::BMOVPCRX_CALL: {
1315  .addReg(ARM::LR)
1316  .addReg(ARM::PC)
1317  // Add predicate operands.
1318  .addImm(ARMCC::AL)
1319  .addReg(0)
1320  // Add 's' bit operand (always reg0 for this)
1321  .addReg(0));
1322 
1324  .addReg(ARM::PC)
1325  .addReg(MI->getOperand(0).getReg())
1326  // Add predicate operands.
1327  .addImm(ARMCC::AL)
1328  .addReg(0)
1329  // Add 's' bit operand (always reg0 for this)
1330  .addReg(0));
1331  return;
1332  }
1333  case ARM::BMOVPCB_CALL: {
1335  .addReg(ARM::LR)
1336  .addReg(ARM::PC)
1337  // Add predicate operands.
1338  .addImm(ARMCC::AL)
1339  .addReg(0)
1340  // Add 's' bit operand (always reg0 for this)
1341  .addReg(0));
1342 
1343  const MachineOperand &Op = MI->getOperand(0);
1344  const GlobalValue *GV = Op.getGlobal();
1345  const unsigned TF = Op.getTargetFlags();
1346  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1347  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1349  .addExpr(GVSymExpr)
1350  // Add predicate operands.
1351  .addImm(ARMCC::AL)
1352  .addReg(0));
1353  return;
1354  }
1355  case ARM::MOVi16_ga_pcrel:
1356  case ARM::t2MOVi16_ga_pcrel: {
1357  MCInst TmpInst;
1358  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1359  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1360 
1361  unsigned TF = MI->getOperand(1).getTargetFlags();
1362  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1363  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1364  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1365 
1366  MCSymbol *LabelSym =
1368  MI->getOperand(2).getImm(), OutContext);
1369  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1370  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1371  const MCExpr *PCRelExpr =
1373  MCBinaryExpr::createAdd(LabelSymExpr,
1376  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1377 
1378  // Add predicate operands.
1380  TmpInst.addOperand(MCOperand::createReg(0));
1381  // Add 's' bit operand (always reg0 for this)
1382  TmpInst.addOperand(MCOperand::createReg(0));
1383  EmitToStreamer(*OutStreamer, TmpInst);
1384  return;
1385  }
1386  case ARM::MOVTi16_ga_pcrel:
1387  case ARM::t2MOVTi16_ga_pcrel: {
1388  MCInst TmpInst;
1389  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1390  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1391  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1392  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1393 
1394  unsigned TF = MI->getOperand(2).getTargetFlags();
1395  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1396  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1397  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1398 
1399  MCSymbol *LabelSym =
1401  MI->getOperand(3).getImm(), OutContext);
1402  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1403  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1404  const MCExpr *PCRelExpr =
1406  MCBinaryExpr::createAdd(LabelSymExpr,
1409  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1410  // Add predicate operands.
1412  TmpInst.addOperand(MCOperand::createReg(0));
1413  // Add 's' bit operand (always reg0 for this)
1414  TmpInst.addOperand(MCOperand::createReg(0));
1415  EmitToStreamer(*OutStreamer, TmpInst);
1416  return;
1417  }
1418  case ARM::tPICADD: {
1419  // This is a pseudo op for a label + instruction sequence, which looks like:
1420  // LPC0:
1421  // add r0, pc
1422  // This adds the address of LPC0 to r0.
1423 
1424  // Emit the label.
1427  MI->getOperand(2).getImm(), OutContext));
1428 
1429  // Form and emit the add.
1430  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1431  .addReg(MI->getOperand(0).getReg())
1432  .addReg(MI->getOperand(0).getReg())
1433  .addReg(ARM::PC)
1434  // Add predicate operands.
1435  .addImm(ARMCC::AL)
1436  .addReg(0));
1437  return;
1438  }
1439  case ARM::PICADD: {
1440  // This is a pseudo op for a label + instruction sequence, which looks like:
1441  // LPC0:
1442  // add r0, pc, r0
1443  // This adds the address of LPC0 to r0.
1444 
1445  // Emit the label.
1448  MI->getOperand(2).getImm(), OutContext));
1449 
1450  // Form and emit the add.
1452  .addReg(MI->getOperand(0).getReg())
1453  .addReg(ARM::PC)
1454  .addReg(MI->getOperand(1).getReg())
1455  // Add predicate operands.
1456  .addImm(MI->getOperand(3).getImm())
1457  .addReg(MI->getOperand(4).getReg())
1458  // Add 's' bit operand (always reg0 for this)
1459  .addReg(0));
1460  return;
1461  }
1462  case ARM::PICSTR:
1463  case ARM::PICSTRB:
1464  case ARM::PICSTRH:
1465  case ARM::PICLDR:
1466  case ARM::PICLDRB:
1467  case ARM::PICLDRH:
1468  case ARM::PICLDRSB:
1469  case ARM::PICLDRSH: {
1470  // This is a pseudo op for a label + instruction sequence, which looks like:
1471  // LPC0:
1472  // OP r0, [pc, r0]
1473  // The LCP0 label is referenced by a constant pool entry in order to get
1474  // a PC-relative address at the ldr instruction.
1475 
1476  // Emit the label.
1479  MI->getOperand(2).getImm(), OutContext));
1480 
1481  // Form and emit the load
1482  unsigned Opcode;
1483  switch (MI->getOpcode()) {
1484  default:
1485  llvm_unreachable("Unexpected opcode!");
1486  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1487  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1488  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1489  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1490  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1491  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1492  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1493  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1494  }
1496  .addReg(MI->getOperand(0).getReg())
1497  .addReg(ARM::PC)
1498  .addReg(MI->getOperand(1).getReg())
1499  .addImm(0)
1500  // Add predicate operands.
1501  .addImm(MI->getOperand(3).getImm())
1502  .addReg(MI->getOperand(4).getReg()));
1503 
1504  return;
1505  }
1506  case ARM::CONSTPOOL_ENTRY: {
1507  if (Subtarget->genExecuteOnly())
1508  llvm_unreachable("execute-only should not generate constant pools");
1509 
1510  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1511  /// in the function. The first operand is the ID# for this instruction, the
1512  /// second is the index into the MachineConstantPool that this is, the third
1513  /// is the size in bytes of this constant pool entry.
1514  /// The required alignment is specified on the basic block holding this MI.
1515  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1516  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1517 
1518  // If this is the first entry of the pool, mark it.
1519  if (!InConstantPool) {
1520  OutStreamer->EmitDataRegion(MCDR_DataRegion);
1521  InConstantPool = true;
1522  }
1523 
1524  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1525 
1526  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1527  if (MCPE.isMachineConstantPoolEntry())
1529  else
1530  EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1531  return;
1532  }
1533  case ARM::JUMPTABLE_ADDRS:
1534  EmitJumpTableAddrs(MI);
1535  return;
1536  case ARM::JUMPTABLE_INSTS:
1537  EmitJumpTableInsts(MI);
1538  return;
1539  case ARM::JUMPTABLE_TBB:
1540  case ARM::JUMPTABLE_TBH:
1541  EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1542  return;
1543  case ARM::t2BR_JT: {
1545  .addReg(ARM::PC)
1546  .addReg(MI->getOperand(0).getReg())
1547  // Add predicate operands.
1548  .addImm(ARMCC::AL)
1549  .addReg(0));
1550  return;
1551  }
1552  case ARM::t2TBB_JT:
1553  case ARM::t2TBH_JT: {
1554  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1555  // Lower and emit the PC label, then the instruction itself.
1556  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1558  .addReg(MI->getOperand(0).getReg())
1559  .addReg(MI->getOperand(1).getReg())
1560  // Add predicate operands.
1561  .addImm(ARMCC::AL)
1562  .addReg(0));
1563  return;
1564  }
1565  case ARM::tTBB_JT:
1566  case ARM::tTBH_JT: {
1567 
1568  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1569  unsigned Base = MI->getOperand(0).getReg();
1570  unsigned Idx = MI->getOperand(1).getReg();
1571  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1572 
1573  // Multiply up idx if necessary.
1574  if (!Is8Bit)
1576  .addReg(Idx)
1577  .addReg(ARM::CPSR)
1578  .addReg(Idx)
1579  .addImm(1)
1580  // Add predicate operands.
1581  .addImm(ARMCC::AL)
1582  .addReg(0));
1583 
1584  if (Base == ARM::PC) {
1585  // TBB [base, idx] =
1586  // ADDS idx, idx, base
1587  // LDRB idx, [idx, #4] ; or LDRH if TBH
1588  // LSLS idx, #1
1589  // ADDS pc, pc, idx
1590 
1591  // When using PC as the base, it's important that there is no padding
1592  // between the last ADDS and the start of the jump table. The jump table
1593  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1594  //
1595  // FIXME: Ideally we could vary the LDRB index based on the padding
1596  // between the sequence and jump table, however that relies on MCExprs
1597  // for load indexes which are currently not supported.
1598  OutStreamer->EmitCodeAlignment(4);
1599  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1600  .addReg(Idx)
1601  .addReg(Idx)
1602  .addReg(Base)
1603  // Add predicate operands.
1604  .addImm(ARMCC::AL)
1605  .addReg(0));
1606 
1607  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1609  .addReg(Idx)
1610  .addReg(Idx)
1611  .addImm(Is8Bit ? 4 : 2)
1612  // Add predicate operands.
1613  .addImm(ARMCC::AL)
1614  .addReg(0));
1615  } else {
1616  // TBB [base, idx] =
1617  // LDRB idx, [base, idx] ; or LDRH if TBH
1618  // LSLS idx, #1
1619  // ADDS pc, pc, idx
1620 
1621  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1623  .addReg(Idx)
1624  .addReg(Base)
1625  .addReg(Idx)
1626  // Add predicate operands.
1627  .addImm(ARMCC::AL)
1628  .addReg(0));
1629  }
1630 
1632  .addReg(Idx)
1633  .addReg(ARM::CPSR)
1634  .addReg(Idx)
1635  .addImm(1)
1636  // Add predicate operands.
1637  .addImm(ARMCC::AL)
1638  .addReg(0));
1639 
1640  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1641  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1642  .addReg(ARM::PC)
1643  .addReg(ARM::PC)
1644  .addReg(Idx)
1645  // Add predicate operands.
1646  .addImm(ARMCC::AL)
1647  .addReg(0));
1648  return;
1649  }
1650  case ARM::tBR_JTr:
1651  case ARM::BR_JTr: {
1652  // mov pc, target
1653  MCInst TmpInst;
1654  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1655  ARM::MOVr : ARM::tMOVr;
1656  TmpInst.setOpcode(Opc);
1657  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1658  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1659  // Add predicate operands.
1661  TmpInst.addOperand(MCOperand::createReg(0));
1662  // Add 's' bit operand (always reg0 for this)
1663  if (Opc == ARM::MOVr)
1664  TmpInst.addOperand(MCOperand::createReg(0));
1665  EmitToStreamer(*OutStreamer, TmpInst);
1666  return;
1667  }
1668  case ARM::BR_JTm_i12: {
1669  // ldr pc, target
1670  MCInst TmpInst;
1671  TmpInst.setOpcode(ARM::LDRi12);
1672  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1673  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1674  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1675  // Add predicate operands.
1677  TmpInst.addOperand(MCOperand::createReg(0));
1678  EmitToStreamer(*OutStreamer, TmpInst);
1679  return;
1680  }
1681  case ARM::BR_JTm_rs: {
1682  // ldr pc, target
1683  MCInst TmpInst;
1684  TmpInst.setOpcode(ARM::LDRrs);
1685  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1686  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1687  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1688  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1689  // Add predicate operands.
1691  TmpInst.addOperand(MCOperand::createReg(0));
1692  EmitToStreamer(*OutStreamer, TmpInst);
1693  return;
1694  }
1695  case ARM::BR_JTadd: {
1696  // add pc, target, idx
1698  .addReg(ARM::PC)
1699  .addReg(MI->getOperand(0).getReg())
1700  .addReg(MI->getOperand(1).getReg())
1701  // Add predicate operands.
1702  .addImm(ARMCC::AL)
1703  .addReg(0)
1704  // Add 's' bit operand (always reg0 for this)
1705  .addReg(0));
1706  return;
1707  }
1708  case ARM::SPACE:
1709  OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1710  return;
1711  case ARM::TRAP: {
1712  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1713  // FIXME: Remove this special case when they do.
1714  if (!Subtarget->isTargetMachO()) {
1715  uint32_t Val = 0xe7ffdefeUL;
1716  OutStreamer->AddComment("trap");
1717  ATS.emitInst(Val);
1718  return;
1719  }
1720  break;
1721  }
1722  case ARM::TRAPNaCl: {
1723  uint32_t Val = 0xe7fedef0UL;
1724  OutStreamer->AddComment("trap");
1725  ATS.emitInst(Val);
1726  return;
1727  }
1728  case ARM::tTRAP: {
1729  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1730  // FIXME: Remove this special case when they do.
1731  if (!Subtarget->isTargetMachO()) {
1732  uint16_t Val = 0xdefe;
1733  OutStreamer->AddComment("trap");
1734  ATS.emitInst(Val, 'n');
1735  return;
1736  }
1737  break;
1738  }
1739  case ARM::t2Int_eh_sjlj_setjmp:
1740  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1741  case ARM::tInt_eh_sjlj_setjmp: {
1742  // Two incoming args: GPR:$src, GPR:$val
1743  // mov $val, pc
1744  // adds $val, #7
1745  // str $val, [$src, #4]
1746  // movs r0, #0
1747  // b LSJLJEH
1748  // movs r0, #1
1749  // LSJLJEH:
1750  unsigned SrcReg = MI->getOperand(0).getReg();
1751  unsigned ValReg = MI->getOperand(1).getReg();
1752  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1753  OutStreamer->AddComment("eh_setjmp begin");
1755  .addReg(ValReg)
1756  .addReg(ARM::PC)
1757  // Predicate.
1758  .addImm(ARMCC::AL)
1759  .addReg(0));
1760 
1762  .addReg(ValReg)
1763  // 's' bit operand
1764  .addReg(ARM::CPSR)
1765  .addReg(ValReg)
1766  .addImm(7)
1767  // Predicate.
1768  .addImm(ARMCC::AL)
1769  .addReg(0));
1770 
1772  .addReg(ValReg)
1773  .addReg(SrcReg)
1774  // The offset immediate is #4. The operand value is scaled by 4 for the
1775  // tSTR instruction.
1776  .addImm(1)
1777  // Predicate.
1778  .addImm(ARMCC::AL)
1779  .addReg(0));
1780 
1782  .addReg(ARM::R0)
1783  .addReg(ARM::CPSR)
1784  .addImm(0)
1785  // Predicate.
1786  .addImm(ARMCC::AL)
1787  .addReg(0));
1788 
1789  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1791  .addExpr(SymbolExpr)
1792  .addImm(ARMCC::AL)
1793  .addReg(0));
1794 
1795  OutStreamer->AddComment("eh_setjmp end");
1797  .addReg(ARM::R0)
1798  .addReg(ARM::CPSR)
1799  .addImm(1)
1800  // Predicate.
1801  .addImm(ARMCC::AL)
1802  .addReg(0));
1803 
1804  OutStreamer->EmitLabel(Label);
1805  return;
1806  }
1807 
1808  case ARM::Int_eh_sjlj_setjmp_nofp:
1809  case ARM::Int_eh_sjlj_setjmp: {
1810  // Two incoming args: GPR:$src, GPR:$val
1811  // add $val, pc, #8
1812  // str $val, [$src, #+4]
1813  // mov r0, #0
1814  // add pc, pc, #0
1815  // mov r0, #1
1816  unsigned SrcReg = MI->getOperand(0).getReg();
1817  unsigned ValReg = MI->getOperand(1).getReg();
1818 
1819  OutStreamer->AddComment("eh_setjmp begin");
1821  .addReg(ValReg)
1822  .addReg(ARM::PC)
1823  .addImm(8)
1824  // Predicate.
1825  .addImm(ARMCC::AL)
1826  .addReg(0)
1827  // 's' bit operand (always reg0 for this).
1828  .addReg(0));
1829 
1831  .addReg(ValReg)
1832  .addReg(SrcReg)
1833  .addImm(4)
1834  // Predicate.
1835  .addImm(ARMCC::AL)
1836  .addReg(0));
1837 
1839  .addReg(ARM::R0)
1840  .addImm(0)
1841  // Predicate.
1842  .addImm(ARMCC::AL)
1843  .addReg(0)
1844  // 's' bit operand (always reg0 for this).
1845  .addReg(0));
1846 
1848  .addReg(ARM::PC)
1849  .addReg(ARM::PC)
1850  .addImm(0)
1851  // Predicate.
1852  .addImm(ARMCC::AL)
1853  .addReg(0)
1854  // 's' bit operand (always reg0 for this).
1855  .addReg(0));
1856 
1857  OutStreamer->AddComment("eh_setjmp end");
1859  .addReg(ARM::R0)
1860  .addImm(1)
1861  // Predicate.
1862  .addImm(ARMCC::AL)
1863  .addReg(0)
1864  // 's' bit operand (always reg0 for this).
1865  .addReg(0));
1866  return;
1867  }
1868  case ARM::Int_eh_sjlj_longjmp: {
1869  // ldr sp, [$src, #8]
1870  // ldr $scratch, [$src, #4]
1871  // ldr r7, [$src]
1872  // bx $scratch
1873  unsigned SrcReg = MI->getOperand(0).getReg();
1874  unsigned ScratchReg = MI->getOperand(1).getReg();
1876  .addReg(ARM::SP)
1877  .addReg(SrcReg)
1878  .addImm(8)
1879  // Predicate.
1880  .addImm(ARMCC::AL)
1881  .addReg(0));
1882 
1884  .addReg(ScratchReg)
1885  .addReg(SrcReg)
1886  .addImm(4)
1887  // Predicate.
1888  .addImm(ARMCC::AL)
1889  .addReg(0));
1890 
1891  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1892  // These platforms always use the same frame register
1894  .addReg(FramePtr)
1895  .addReg(SrcReg)
1896  .addImm(0)
1897  // Predicate.
1898  .addImm(ARMCC::AL)
1899  .addReg(0));
1900  } else {
1901  // If the calling code might use either R7 or R11 as
1902  // frame pointer register, restore it into both.
1904  .addReg(ARM::R7)
1905  .addReg(SrcReg)
1906  .addImm(0)
1907  // Predicate.
1908  .addImm(ARMCC::AL)
1909  .addReg(0));
1911  .addReg(ARM::R11)
1912  .addReg(SrcReg)
1913  .addImm(0)
1914  // Predicate.
1915  .addImm(ARMCC::AL)
1916  .addReg(0));
1917  }
1918 
1919  assert(Subtarget->hasV4TOps());
1921  .addReg(ScratchReg)
1922  // Predicate.
1923  .addImm(ARMCC::AL)
1924  .addReg(0));
1925  return;
1926  }
1927  case ARM::tInt_eh_sjlj_longjmp: {
1928  // ldr $scratch, [$src, #8]
1929  // mov sp, $scratch
1930  // ldr $scratch, [$src, #4]
1931  // ldr r7, [$src]
1932  // bx $scratch
1933  unsigned SrcReg = MI->getOperand(0).getReg();
1934  unsigned ScratchReg = MI->getOperand(1).getReg();
1935 
1937  .addReg(ScratchReg)
1938  .addReg(SrcReg)
1939  // The offset immediate is #8. The operand value is scaled by 4 for the
1940  // tLDR instruction.
1941  .addImm(2)
1942  // Predicate.
1943  .addImm(ARMCC::AL)
1944  .addReg(0));
1945 
1947  .addReg(ARM::SP)
1948  .addReg(ScratchReg)
1949  // Predicate.
1950  .addImm(ARMCC::AL)
1951  .addReg(0));
1952 
1954  .addReg(ScratchReg)
1955  .addReg(SrcReg)
1956  .addImm(1)
1957  // Predicate.
1958  .addImm(ARMCC::AL)
1959  .addReg(0));
1960 
1961  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1962  // These platforms always use the same frame register
1964  .addReg(FramePtr)
1965  .addReg(SrcReg)
1966  .addImm(0)
1967  // Predicate.
1968  .addImm(ARMCC::AL)
1969  .addReg(0));
1970  } else {
1971  // If the calling code might use either R7 or R11 as
1972  // frame pointer register, restore it into both.
1974  .addReg(ARM::R7)
1975  .addReg(SrcReg)
1976  .addImm(0)
1977  // Predicate.
1978  .addImm(ARMCC::AL)
1979  .addReg(0));
1981  .addReg(ARM::R11)
1982  .addReg(SrcReg)
1983  .addImm(0)
1984  // Predicate.
1985  .addImm(ARMCC::AL)
1986  .addReg(0));
1987  }
1988 
1990  .addReg(ScratchReg)
1991  // Predicate.
1992  .addImm(ARMCC::AL)
1993  .addReg(0));
1994  return;
1995  }
1996  case ARM::tInt_WIN_eh_sjlj_longjmp: {
1997  // ldr.w r11, [$src, #0]
1998  // ldr.w sp, [$src, #8]
1999  // ldr.w pc, [$src, #4]
2000 
2001  unsigned SrcReg = MI->getOperand(0).getReg();
2002 
2003  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2004  .addReg(ARM::R11)
2005  .addReg(SrcReg)
2006  .addImm(0)
2007  // Predicate
2008  .addImm(ARMCC::AL)
2009  .addReg(0));
2010  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2011  .addReg(ARM::SP)
2012  .addReg(SrcReg)
2013  .addImm(8)
2014  // Predicate
2015  .addImm(ARMCC::AL)
2016  .addReg(0));
2017  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2018  .addReg(ARM::PC)
2019  .addReg(SrcReg)
2020  .addImm(4)
2021  // Predicate
2022  .addImm(ARMCC::AL)
2023  .addReg(0));
2024  return;
2025  }
2026  case ARM::PATCHABLE_FUNCTION_ENTER:
2028  return;
2029  case ARM::PATCHABLE_FUNCTION_EXIT:
2031  return;
2032  case ARM::PATCHABLE_TAIL_CALL:
2034  return;
2035  }
2036 
2037  MCInst TmpInst;
2038  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2039 
2040  EmitToStreamer(*OutStreamer, TmpInst);
2041 }
2042 
2043 //===----------------------------------------------------------------------===//
2044 // Target Registry Stuff
2045 //===----------------------------------------------------------------------===//
2046 
2047 // Force static initialization.
2048 extern "C" void LLVMInitializeARMAsmPrinter() {
2053 }
unsigned getTargetFlags() const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:432
MachineConstantPoolValue * MachineCPVal
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:259
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:209
void push_back(const T &Elt)
Definition: SmallVector.h:218
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
StringRef getTargetFeatureString() const
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:658
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
PointerTy getPointer() const
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:294
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool hasV4TOps() const
Definition: ARMSubtarget.h:522
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
ARMConstantPoolValue - ARM specific constantpool value.
unsigned getReg() const
getReg - Returns the register number.
Target specific streamer interface.
Definition: MCStreamer.h:83
unsigned Reg
virtual void emitPad(int64_t Offset)
unsigned getSubReg() const
Global Offset Table, Thread Pointer Offset.
unsigned char getPCAdjustment() const
bool isTargetCOFF() const
Definition: ARMSubtarget.h:642
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:307
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:504
MachineBasicBlock reference.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the EmitInstruction() method to print assembly for each instruction...
virtual void finishAttributeSection()
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
setjmp/longjmp based exceptions
bool isThumb1Only() const
Definition: ARMSubtarget.h:699
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:663
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Global Offset Table, PC Relative.
Thread Pointer Offset.
Target & getTheThumbLETarget()
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
static bool isThumb(const MCSubtargetInfo &STI)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
void LLVMInitializeARMAsmPrinter()
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
return AArch64::GPR64RegClass contains(Reg)
bool genExecuteOnly() const
Definition: ARMSubtarget.h:620
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool isTargetELF() const
Definition: ARMSubtarget.h:643
ARMCP::ARMCPModifier getModifier() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
The address of a basic block.
Definition: Constants.h:836
MCContext & getContext() const
Definition: MCStreamer.h:250
Definition: BitVector.h:921
virtual void emitInst(uint32_t Inst, char Suffix='\0')
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const FeatureBitset & getFeatureBits() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:470
unsigned SubReg
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
.data_region jt16
Definition: MCDirectives.h:59
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
Target & getTheARMBETarget()
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Context object for machine code objects.
Definition: MCContext.h:63
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:43
void EmitFunctionBody()
This method emits the body and trailer for a function.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file. ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:200
Target & getTheThumbBETarget()
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
IntType getInt() const
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:671
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
bool isTargetDarwin() const
Definition: ARMSubtarget.h:633
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
This class is a data container for one entry in a MachineConstantPool.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
StringRef getTargetCPU() const
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:266
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
static const char * getRegisterName(unsigned RegNo)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:460
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:112
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:143
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:99
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:711
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:672
.data_region jt32
Definition: MCDirectives.h:60
Address of a global value.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Streaming machine code generation interface.
Definition: MCStreamer.h:183
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:32
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:112
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
PointerIntPair - This class implements a pair of a pointer and small integer.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
MCSection * getNonLazySymbolPointerSection() const
void EmitAlignment(unsigned NumBits, const GlobalObject *GV=nullptr) const
Emit an alignment directive to the specified power of two boundary.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:422
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1025
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:584
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:50
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:730
Thread Local Storage (General Dynamic Mode)
const Triple & getTargetTriple() const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an &#39;S&#39; bit onto real opcodes.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:38
Ty & getObjFileInfo()
Keep track of various per-function pieces of information for backends that would like to do so...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
FPDenormal::DenormalMode FPDenormalMode
FPDenormalMode - This flags specificies which denormal numbers the code is permitted to require...
const Constant * stripPointerCasts() const
Definition: Constant.h:173
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Abstract base class for all machine specific constantpool value subclasses.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:239
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCSection * getThreadLocalPointerSection() const
void EmitJumpTableInsts(const MachineInstr *MI)
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:205
void setOpcode(unsigned Op)
Definition: MCInst.h:173
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
bool isTargetAEABI() const
Definition: ARMSubtarget.h:653
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:427
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
.indirect_symbol (MachO)
Definition: MCDirectives.h:32
unsigned getOriginalCPIdx(unsigned CloneIdx) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:228
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:204
.syntax (ARM/ELF)
Definition: MCDirectives.h:49
MCSymbol * getCurExceptionSym()
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
bool isROPI() const
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
FunctionNumber(functionNumber)
Definition: LLParser.cpp:2704
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Section Relative (Windows TLS)
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
union llvm::MachineConstantPoolEntry::@146 Val
The constant itself.
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:649
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
TargetOptions Options
Definition: TargetMachine.h:98
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:581
void EmitJumpTableAddrs(const MachineInstr *MI)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:39
Generic base class for all target subtargets.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:124
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
bool hasV5TOps() const
Definition: ARMSubtarget.h:523
Type * getType() const
getType - get type of this MachineConstantPoolValue.
const Module * getModule() const
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
const std::string & getModuleInlineAsm() const
Get any module-scope inline assembly blocks.
Definition: Module.h:246
bool isTargetMachO() const
Definition: ARMSubtarget.h:644
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
.data_region jt8
Definition: MCDirectives.h:58
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:73
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:322
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:272
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:570
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:317
static const unsigned FramePtr
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
bool isTargetWindows() const
Definition: ARMSubtarget.h:640
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:213
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
IRTranslator LLVM IR MI
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:238
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Address of indexed Constant in Constant Pool.
Target & getTheARMLETarget()
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
void EmitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:197
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
.end_data_region
Definition: MCDirectives.h:61
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:243
bool isImplicit() const
virtual void switchVendor(StringRef Vendor)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:60
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
A function that returns a base type.
Definition: COFF.h:262