LLVM  8.0.0svn
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/Support/CodeGen.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "arm-subtarget"
45 
46 #define GET_SUBTARGETINFO_TARGET_DESC
47 #define GET_SUBTARGETINFO_CTOR
48 #include "ARMGenSubtargetInfo.inc"
49 
50 static cl::opt<bool>
51 UseFusedMulOps("arm-use-mulops",
52  cl::init(true), cl::Hidden);
53 
54 enum ITMode {
58 };
59 
60 static cl::opt<ITMode>
61 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
63  cl::values(clEnumValN(DefaultIT, "arm-default-it",
64  "Generate IT block based on arch"),
65  clEnumValN(RestrictedIT, "arm-restrict-it",
66  "Disallow deprecated IT based on ARMv8"),
67  clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
68  "Allow IT blocks based on ARMv7")));
69 
70 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
71 /// currently supported (for testing only).
72 static cl::opt<bool>
73 ForceFastISel("arm-force-fast-isel",
74  cl::init(false), cl::Hidden);
75 
76 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
77 /// so that we can use initializer lists for subtarget initialization.
79  StringRef FS) {
80  initializeEnvironment();
81  initSubtargetFeatures(CPU, FS);
82  return *this;
83 }
84 
85 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
86  StringRef FS) {
88  if (STI.isThumb1Only())
89  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
90 
91  return new ARMFrameLowering(STI);
92 }
93 
94 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
95  const std::string &FS,
96  const ARMBaseTargetMachine &TM, bool IsLittle)
98  CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
99  TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
100  // At this point initializeSubtargetDependencies has been called so
101  // we can query directly.
102  InstrInfo(isThumb1Only()
103  ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
104  : !isThumb()
105  ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106  : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
107  TLInfo(TM, *this) {
108 
109  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
110  Legalizer.reset(new ARMLegalizerInfo(*this));
111 
112  auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
113 
114  // FIXME: At this point, we can't rely on Subtarget having RBI.
115  // It's awkward to mix passing RBI and the Subtarget; should we pass
116  // TII/TRI as well?
117  InstSelector.reset(createARMInstructionSelector(
118  *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
119 
120  RegBankInfo.reset(RBI);
121 }
122 
124  return CallLoweringInfo.get();
125 }
126 
128  return InstSelector.get();
129 }
130 
132  return Legalizer.get();
133 }
134 
136  return RegBankInfo.get();
137 }
138 
140  // We don't currently suppport Thumb, but Windows requires Thumb.
141  return hasV6Ops() && hasARMOps() && !isTargetWindows();
142 }
143 
144 void ARMSubtarget::initializeEnvironment() {
145  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
146  // directly from it, but we can try to make sure they're consistent when both
147  // available.
151  assert((!TM.getMCAsmInfo() ||
154  "inconsistent sjlj choice between CodeGen and MC");
155 }
156 
157 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
158  if (CPUString.empty()) {
159  CPUString = "generic";
160 
161  if (isTargetDarwin()) {
162  StringRef ArchName = TargetTriple.getArchName();
163  ARM::ArchKind AK = ARM::parseArch(ArchName);
164  if (AK == ARM::ArchKind::ARMV7S)
165  // Default to the Swift CPU when targeting armv7s/thumbv7s.
166  CPUString = "swift";
167  else if (AK == ARM::ArchKind::ARMV7K)
168  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
169  // ARMv7k does not use SjLj exception handling.
170  CPUString = "cortex-a7";
171  }
172  }
173 
174  // Insert the architecture feature derived from the target triple into the
175  // feature string. This is important for setting features that are implied
176  // based on the architecture version.
177  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
178  if (!FS.empty()) {
179  if (!ArchFS.empty())
180  ArchFS = (Twine(ArchFS) + "," + FS).str();
181  else
182  ArchFS = FS;
183  }
185 
186  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
187  // Assert this for now to make the change obvious.
188  assert(hasV6T2Ops() || !hasThumb2());
189 
190  // Execute only support requires movt support
191  if (genExecuteOnly()) {
192  NoMovt = false;
193  assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
194  }
195 
196  // Keep a pointer to static instruction cost data for the specified CPU.
197  SchedModel = getSchedModelForCPU(CPUString);
198 
199  // Initialize scheduling itinerary for the specified CPU.
200  InstrItins = getInstrItineraryForCPU(CPUString);
201 
202  // FIXME: this is invalid for WindowsCE
203  if (isTargetWindows())
204  NoARM = true;
205 
206  if (isAAPCS_ABI())
207  stackAlignment = 8;
208  if (isTargetNaCl() || isAAPCS16_ABI())
209  stackAlignment = 16;
210 
211  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
212  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
213  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
214  // support in the assembler and linker to be used. This would need to be
215  // fixed to fully support tail calls in Thumb1.
216  //
217  // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
218  // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
219  // means if we need to reload LR, it takes extra instructions, which outweighs
220  // the value of the tail call; but here we don't know yet whether LR is going
221  // to be used. We take the optimistic approach of generating the tail call and
222  // perhaps taking a hit if we need to restore the LR.
223 
224  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
225  // but we need to make sure there are enough registers; the only valid
226  // registers are the 4 used for parameters. We don't currently do this
227  // case.
228 
230 
231  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
232  SupportsTailCall = false;
233 
234  switch (IT) {
235  case DefaultIT:
236  RestrictIT = hasV8Ops();
237  break;
238  case RestrictedIT:
239  RestrictIT = true;
240  break;
241  case NoRestrictedIT:
242  RestrictIT = false;
243  break;
244  }
245 
246  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
247  const FeatureBitset &Bits = getFeatureBits();
248  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
251 
252  if (isRWPI())
253  ReserveR9 = true;
254 
255  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
256  switch (ARMProcFamily) {
257  case Others:
258  case CortexA5:
259  break;
260  case CortexA7:
262  break;
263  case CortexA8:
265  break;
266  case CortexA9:
269  break;
270  case CortexA12:
271  break;
272  case CortexA15:
276  break;
277  case CortexA17:
278  case CortexA32:
279  case CortexA35:
280  case CortexA53:
281  case CortexA55:
282  case CortexA57:
283  case CortexA72:
284  case CortexA73:
285  case CortexA75:
286  case CortexR4:
287  case CortexR4F:
288  case CortexR5:
289  case CortexR7:
290  case CortexM3:
291  case CortexR52:
292  break;
293  case Exynos:
296  if (!isThumb())
297  PrefLoopAlignment = 3;
298  break;
299  case Kryo:
300  break;
301  case Krait:
303  break;
304  case Swift:
309  break;
310  }
311 }
312 
314 
318 }
323 }
327 }
328 
329 bool ARMSubtarget::isROPI() const {
330  return TM.getRelocationModel() == Reloc::ROPI ||
332 }
333 bool ARMSubtarget::isRWPI() const {
334  return TM.getRelocationModel() == Reloc::RWPI ||
336 }
337 
339  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
340  return true;
341 
342  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
343  // the section that is being relocated. This means we have to use o load even
344  // for GVs that are known to be local to the dso.
346  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
347  return true;
348 
349  return false;
350 }
351 
352 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
353  return isTargetELF() && TM.isPositionIndependent() &&
354  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
355 }
356 
359 }
360 
362  // Enable the MachineScheduler before register allocation for subtargets
363  // with the use-misched feature.
364  return useMachineScheduler();
365 }
366 
367 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
370  return false;
371  // Don't reschedule potential IT blocks.
372  return !isThumb1Only();
373 }
374 
376 
378  // For general targets, the prologue can grow when VFPs are allocated with
379  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
380  // format which it's more important to get right.
381  return isTargetWatchABI() ||
383 }
384 
385 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
386  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
387  // immediates as it is inherently position independent, and may be out of
388  // range otherwise.
389  return !NoMovt && hasV8MBaselineOps() &&
391 }
392 
394  // Enable fast-isel for any target, for testing only.
395  if (ForceFastISel)
396  return true;
397 
398  // Limit fast-isel to the targets that are or have been tested.
399  if (!hasV6Ops())
400  return false;
401 
402  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
403  return TM.Options.EnableFastISel &&
404  ((isTargetMachO() && !isThumb1Only()) ||
405  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
406 }
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:219
bool isDeclarationForLinker() const
Definition: GlobalValue.h:524
unsigned MispredictPenalty
Definition: MCSchedule.h:297
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:428
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:453
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isThumb() const
Definition: ARMSubtarget.h:712
This class represents lattice values for constants.
Definition: AllocatorList.h:24
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool useFastISel() const
True if fast-isel is used.
DWARF-like instruction based exceptions.
bool isTargetNaCl() const
Definition: ARMSubtarget.h:652
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:495
This class provides the information for the target register banks.
bool hasV6Ops() const
Definition: ARMSubtarget.h:536
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
bool isThumb1Only() const
Definition: ARMSubtarget.h:713
const LegalizerInfo * getLegalizerInfo() const override
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:464
bool isTargetHardFloat() const
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:224
bool genExecuteOnly() const
Definition: ARMSubtarget.h:633
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:179
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:547
bool isTargetELF() const
Definition: ARMSubtarget.h:657
Holds all the information related to register banks.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool hasARMOps() const
Definition: ARMSubtarget.h:565
bool hasV8Ops() const
Definition: ARMSubtarget.h:541
ExceptionHandling ExceptionModel
What exception model to use.
bool useStride4VFPs(const MachineFunction &MF) const
bool hasCommonLinkage() const
Definition: GlobalValue.h:440
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:450
bool useMovt(const MachineFunction &MF) const
bool enableAtomicExpand() const override
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:123
bool isXRaySupported() const override
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:212
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:539
This class provides the information for the target register banks.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:647
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:444
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:650
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:419
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Container class for subtarget features.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:133
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:398
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:639
This file declares the targeting of the Machinelegalizer class for ARM.
bool useMachineScheduler() const
Definition: ARMSubtarget.h:709
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
unsigned getMispredictionPenalty() const
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:614
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:971
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
ArchKind parseArch(StringRef Arch)
bool isTargetLinux() const
Definition: ARMSubtarget.h:651
const InstructionSelector * getInstructionSelector() const override
const Function & getFunction() const
Return the LLVM function that this machine code represents.
unsigned PrefLoopAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:447
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:456
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:710
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:462
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isROPI() const
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:614
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
Provides the logic to select generic machine instructions.
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:645
bool isTargetIOS() const
Definition: ARMSubtarget.h:648
bool isPositionIndependent() const
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:215
TargetOptions Options
Definition: TargetMachine.h:97
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:459
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:175
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:503
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:595
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:436
bool isTargetMachO() const
Definition: ARMSubtarget.h:658
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:440
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:128
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:570
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isRWPI() const
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:120
bool isTargetWindows() const
Definition: ARMSubtarget.h:654
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:431
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This file describes how to lower LLVM calls to machine code calls.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:591
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
ITMode
bool isAAPCS_ABI() const
bool hasThumb2() const
Definition: ARMSubtarget.h:715
const RegisterBankInfo * getRegBankInfo() const override
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:417
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:433