LLVM  6.0.0svn
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/Support/CodeGen.h"
44 #include <cassert>
45 #include <string>
46 
47 using namespace llvm;
48 
49 #define DEBUG_TYPE "arm-subtarget"
50 
51 #define GET_SUBTARGETINFO_TARGET_DESC
52 #define GET_SUBTARGETINFO_CTOR
53 #include "ARMGenSubtargetInfo.inc"
54 
55 static cl::opt<bool>
56 UseFusedMulOps("arm-use-mulops",
57  cl::init(true), cl::Hidden);
58 
59 enum ITMode {
63 };
64 
65 static cl::opt<ITMode>
66 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
68  cl::values(clEnumValN(DefaultIT, "arm-default-it",
69  "Generate IT block based on arch"),
70  clEnumValN(RestrictedIT, "arm-restrict-it",
71  "Disallow deprecated IT based on ARMv8"),
72  clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
73  "Allow IT blocks based on ARMv7")));
74 
75 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
76 /// currently supported (for testing only).
77 static cl::opt<bool>
78 ForceFastISel("arm-force-fast-isel",
79  cl::init(false), cl::Hidden);
80 
81 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
82 /// so that we can use initializer lists for subtarget initialization.
84  StringRef FS) {
85  initializeEnvironment();
86  initSubtargetFeatures(CPU, FS);
87  return *this;
88 }
89 
90 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
91  StringRef FS) {
93  if (STI.isThumb1Only())
94  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
95 
96  return new ARMFrameLowering(STI);
97 }
98 
99 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
100  const std::string &FS,
101  const ARMBaseTargetMachine &TM, bool IsLittle)
103  CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
104  TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
105  // At this point initializeSubtargetDependencies has been called so
106  // we can query directly.
107  InstrInfo(isThumb1Only()
108  ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
109  : !isThumb()
110  ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
111  : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
112  TLInfo(TM, *this) {
113 
114  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
115  Legalizer.reset(new ARMLegalizerInfo(*this));
116 
117  auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
118 
119  // FIXME: At this point, we can't rely on Subtarget having RBI.
120  // It's awkward to mix passing RBI and the Subtarget; should we pass
121  // TII/TRI as well?
122  InstSelector.reset(createARMInstructionSelector(
123  *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
124 
125  RegBankInfo.reset(RBI);
126 }
127 
129  return CallLoweringInfo.get();
130 }
131 
133  return InstSelector.get();
134 }
135 
137  return Legalizer.get();
138 }
139 
141  return RegBankInfo.get();
142 }
143 
145  // We don't currently suppport Thumb, but Windows requires Thumb.
146  return hasV6Ops() && hasARMOps() && !isTargetWindows();
147 }
148 
149 void ARMSubtarget::initializeEnvironment() {
150  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
151  // directly from it, but we can try to make sure they're consistent when both
152  // available.
156  assert((!TM.getMCAsmInfo() ||
159  "inconsistent sjlj choice between CodeGen and MC");
160 }
161 
162 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
163  if (CPUString.empty()) {
164  CPUString = "generic";
165 
166  if (isTargetDarwin()) {
167  StringRef ArchName = TargetTriple.getArchName();
168  ARM::ArchKind AK = ARM::parseArch(ArchName);
169  if (AK == ARM::ArchKind::ARMV7S)
170  // Default to the Swift CPU when targeting armv7s/thumbv7s.
171  CPUString = "swift";
172  else if (AK == ARM::ArchKind::ARMV7K)
173  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
174  // ARMv7k does not use SjLj exception handling.
175  CPUString = "cortex-a7";
176  }
177  }
178 
179  // Insert the architecture feature derived from the target triple into the
180  // feature string. This is important for setting features that are implied
181  // based on the architecture version.
182  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
183  if (!FS.empty()) {
184  if (!ArchFS.empty())
185  ArchFS = (Twine(ArchFS) + "," + FS).str();
186  else
187  ArchFS = FS;
188  }
190 
191  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
192  // Assert this for now to make the change obvious.
193  assert(hasV6T2Ops() || !hasThumb2());
194 
195  // Execute only support requires movt support
196  if (genExecuteOnly())
197  assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
198 
199  // Keep a pointer to static instruction cost data for the specified CPU.
200  SchedModel = getSchedModelForCPU(CPUString);
201 
202  // Initialize scheduling itinerary for the specified CPU.
203  InstrItins = getInstrItineraryForCPU(CPUString);
204 
205  // FIXME: this is invalid for WindowsCE
206  if (isTargetWindows())
207  NoARM = true;
208 
209  if (isAAPCS_ABI())
210  stackAlignment = 8;
211  if (isTargetNaCl() || isAAPCS16_ABI())
212  stackAlignment = 16;
213 
214  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
215  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
216  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
217  // support in the assembler and linker to be used. This would need to be
218  // fixed to fully support tail calls in Thumb1.
219  //
220  // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
221  // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
222  // means if we need to reload LR, it takes extra instructions, which outweighs
223  // the value of the tail call; but here we don't know yet whether LR is going
224  // to be used. We take the optimistic approach of generating the tail call and
225  // perhaps taking a hit if we need to restore the LR.
226 
227  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
228  // but we need to make sure there are enough registers; the only valid
229  // registers are the 4 used for parameters. We don't currently do this
230  // case.
231 
233 
234  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
235  SupportsTailCall = false;
236 
237  switch (IT) {
238  case DefaultIT:
239  RestrictIT = hasV8Ops();
240  break;
241  case RestrictedIT:
242  RestrictIT = true;
243  break;
244  case NoRestrictedIT:
245  RestrictIT = false;
246  break;
247  }
248 
249  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
250  const FeatureBitset &Bits = getFeatureBits();
251  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
254 
255  if (isRWPI())
256  ReserveR9 = true;
257 
258  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
259  switch (ARMProcFamily) {
260  case Others:
261  case CortexA5:
262  break;
263  case CortexA7:
265  break;
266  case CortexA8:
268  break;
269  case CortexA9:
272  break;
273  case CortexA12:
274  break;
275  case CortexA15:
279  break;
280  case CortexA17:
281  case CortexA32:
282  case CortexA35:
283  case CortexA53:
284  case CortexA55:
285  case CortexA57:
286  case CortexA72:
287  case CortexA73:
288  case CortexA75:
289  case CortexR4:
290  case CortexR4F:
291  case CortexR5:
292  case CortexR7:
293  case CortexM3:
294  case CortexR52:
295  case ExynosM1:
296  case Kryo:
297  break;
298  case Krait:
300  break;
301  case Swift:
306  break;
307  }
308 }
309 
313 }
318 }
322 }
323 
324 bool ARMSubtarget::isROPI() const {
325  return TM.getRelocationModel() == Reloc::ROPI ||
327 }
328 bool ARMSubtarget::isRWPI() const {
329  return TM.getRelocationModel() == Reloc::RWPI ||
331 }
332 
334  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
335  return true;
336 
337  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
338  // the section that is being relocated. This means we have to use o load even
339  // for GVs that are known to be local to the dso.
341  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
342  return true;
343 
344  return false;
345 }
346 
347 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
348  return isTargetELF() && TM.isPositionIndependent() &&
349  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
350 }
351 
354 }
355 
357  return isTargetWatchOS() ||
358  (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
359 }
360 
362  // Enable the MachineScheduler before register allocation for subtargets
363  // with the use-misched feature.
364  return useMachineScheduler();
365 }
366 
367 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
370  return false;
371  // Don't reschedule potential IT blocks.
372  return !isThumb1Only();
373 }
374 
376 
378  // For general targets, the prologue can grow when VFPs are allocated with
379  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
380  // format which it's more important to get right.
381  return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
382 }
383 
384 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
385  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
386  // immediates as it is inherently position independent, and may be out of
387  // range otherwise.
388  return !NoMovt && hasV8MBaselineOps() &&
390 }
391 
393  // Enable fast-isel for any target, for testing only.
394  if (ForceFastISel)
395  return true;
396 
397  // Limit fast-isel to the targets that are or have been tested.
398  if (!hasV6Ops())
399  return false;
400 
401  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
402  return TM.Options.EnableFastISel &&
403  ((isTargetMachO() && !isThumb1Only()) ||
404  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
405 }
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:212
bool isDeclarationForLinker() const
Definition: GlobalValue.h:514
unsigned MispredictPenalty
Definition: MCSchedule.h:180
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:395
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:417
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isThumb() const
Definition: ARMSubtarget.h:672
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool useFastISel() const
True if fast-isel is used.
DWARF-like instruction based exceptions.
bool isTargetNaCl() const
Definition: ARMSubtarget.h:606
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:459
This class provides the information for the target register banks.
bool hasV6Ops() const
Definition: ARMSubtarget.h:500
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
bool isThumb1Only() const
Definition: ARMSubtarget.h:673
const LegalizerInfo * getLegalizerInfo() const override
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:428
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:217
bool genExecuteOnly() const
Definition: ARMSubtarget.h:589
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:175
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:509
bool isTargetELF() const
Definition: ARMSubtarget.h:611
Holds all the information related to register banks.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool hasARMOps() const
Definition: ARMSubtarget.h:527
bool hasV8Ops() const
Definition: ARMSubtarget.h:505
ExceptionHandling ExceptionModel
What exception model to use.
bool useStride4VFPs(const MachineFunction &MF) const
bool hasCommonLinkage() const
Definition: GlobalValue.h:431
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:414
bool useMovt(const MachineFunction &MF) const
bool enableAtomicExpand() const override
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:121
bool isXRaySupported() const override
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:205
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:503
This class provides the information for the target register banks.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:601
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:411
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:604
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Container class for subtarget features.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:131
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:368
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:626
This file declares the targeting of the Machinelegalizer class for ARM.
bool useMachineScheduler() const
Definition: ARMSubtarget.h:669
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:603
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
unsigned getMispredictionPenalty() const
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:940
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isTargetLinux() const
Definition: ARMSubtarget.h:605
const InstructionSelector * getInstructionSelector() const override
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:420
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:670
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:426
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isROPI() const
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:601
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
Provides the logic to select generic machine instructions.
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:599
bool isTargetIOS() const
Definition: ARMSubtarget.h:602
bool isPositionIndependent() const
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:208
TargetOptions Options
Definition: TargetMachine.h:96
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:423
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:171
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:467
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:527
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:403
ArchKind parseArch(StringRef Arch)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isTargetMachO() const
Definition: ARMSubtarget.h:612
This file declares the IRTranslator pass.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:407
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSwift() const
Definition: ARMSubtarget.h:520
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:556
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:126
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:554
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isRWPI() const
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:118
bool isTargetWindows() const
Definition: ARMSubtarget.h:608
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:398
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:403
This file describes how to lower LLVM calls to machine code calls.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:550
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
ITMode
bool isAAPCS_ABI() const
bool hasThumb2() const
Definition: ARMSubtarget.h:675
const RegisterBankInfo * getRegBankInfo() const override
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:387
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:400