LLVM  7.0.0svn
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/Support/CodeGen.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "arm-subtarget"
45 
46 #define GET_SUBTARGETINFO_TARGET_DESC
47 #define GET_SUBTARGETINFO_CTOR
48 #include "ARMGenSubtargetInfo.inc"
49 
50 static cl::opt<bool>
51 UseFusedMulOps("arm-use-mulops",
52  cl::init(true), cl::Hidden);
53 
54 enum ITMode {
58 };
59 
60 static cl::opt<ITMode>
61 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
63  cl::values(clEnumValN(DefaultIT, "arm-default-it",
64  "Generate IT block based on arch"),
65  clEnumValN(RestrictedIT, "arm-restrict-it",
66  "Disallow deprecated IT based on ARMv8"),
67  clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
68  "Allow IT blocks based on ARMv7")));
69 
70 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
71 /// currently supported (for testing only).
72 static cl::opt<bool>
73 ForceFastISel("arm-force-fast-isel",
74  cl::init(false), cl::Hidden);
75 
76 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
77 /// so that we can use initializer lists for subtarget initialization.
79  StringRef FS) {
80  initializeEnvironment();
81  initSubtargetFeatures(CPU, FS);
82  return *this;
83 }
84 
85 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
86  StringRef FS) {
88  if (STI.isThumb1Only())
89  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
90 
91  return new ARMFrameLowering(STI);
92 }
93 
94 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
95  const std::string &FS,
96  const ARMBaseTargetMachine &TM, bool IsLittle)
98  CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
99  TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
100  // At this point initializeSubtargetDependencies has been called so
101  // we can query directly.
102  InstrInfo(isThumb1Only()
103  ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
104  : !isThumb()
105  ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106  : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
107  TLInfo(TM, *this) {
108 
109  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
110  Legalizer.reset(new ARMLegalizerInfo(*this));
111 
112  auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
113 
114  // FIXME: At this point, we can't rely on Subtarget having RBI.
115  // It's awkward to mix passing RBI and the Subtarget; should we pass
116  // TII/TRI as well?
117  InstSelector.reset(createARMInstructionSelector(
118  *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
119 
120  RegBankInfo.reset(RBI);
121 }
122 
124  return CallLoweringInfo.get();
125 }
126 
128  return InstSelector.get();
129 }
130 
132  return Legalizer.get();
133 }
134 
136  return RegBankInfo.get();
137 }
138 
140  // We don't currently suppport Thumb, but Windows requires Thumb.
141  return hasV6Ops() && hasARMOps() && !isTargetWindows();
142 }
143 
144 void ARMSubtarget::initializeEnvironment() {
145  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
146  // directly from it, but we can try to make sure they're consistent when both
147  // available.
151  assert((!TM.getMCAsmInfo() ||
154  "inconsistent sjlj choice between CodeGen and MC");
155 }
156 
157 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
158  if (CPUString.empty()) {
159  CPUString = "generic";
160 
161  if (isTargetDarwin()) {
162  StringRef ArchName = TargetTriple.getArchName();
163  ARM::ArchKind AK = ARM::parseArch(ArchName);
164  if (AK == ARM::ArchKind::ARMV7S)
165  // Default to the Swift CPU when targeting armv7s/thumbv7s.
166  CPUString = "swift";
167  else if (AK == ARM::ArchKind::ARMV7K)
168  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
169  // ARMv7k does not use SjLj exception handling.
170  CPUString = "cortex-a7";
171  }
172  }
173 
174  // Insert the architecture feature derived from the target triple into the
175  // feature string. This is important for setting features that are implied
176  // based on the architecture version.
177  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
178  if (!FS.empty()) {
179  if (!ArchFS.empty())
180  ArchFS = (Twine(ArchFS) + "," + FS).str();
181  else
182  ArchFS = FS;
183  }
185 
186  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
187  // Assert this for now to make the change obvious.
188  assert(hasV6T2Ops() || !hasThumb2());
189 
190  // Execute only support requires movt support
191  if (genExecuteOnly())
192  assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
193 
194  // Keep a pointer to static instruction cost data for the specified CPU.
195  SchedModel = getSchedModelForCPU(CPUString);
196 
197  // Initialize scheduling itinerary for the specified CPU.
198  InstrItins = getInstrItineraryForCPU(CPUString);
199 
200  // FIXME: this is invalid for WindowsCE
201  if (isTargetWindows())
202  NoARM = true;
203 
204  if (isAAPCS_ABI())
205  stackAlignment = 8;
206  if (isTargetNaCl() || isAAPCS16_ABI())
207  stackAlignment = 16;
208 
209  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
210  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
211  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
212  // support in the assembler and linker to be used. This would need to be
213  // fixed to fully support tail calls in Thumb1.
214  //
215  // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
216  // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
217  // means if we need to reload LR, it takes extra instructions, which outweighs
218  // the value of the tail call; but here we don't know yet whether LR is going
219  // to be used. We take the optimistic approach of generating the tail call and
220  // perhaps taking a hit if we need to restore the LR.
221 
222  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
223  // but we need to make sure there are enough registers; the only valid
224  // registers are the 4 used for parameters. We don't currently do this
225  // case.
226 
228 
229  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
230  SupportsTailCall = false;
231 
232  switch (IT) {
233  case DefaultIT:
234  RestrictIT = hasV8Ops();
235  break;
236  case RestrictedIT:
237  RestrictIT = true;
238  break;
239  case NoRestrictedIT:
240  RestrictIT = false;
241  break;
242  }
243 
244  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
245  const FeatureBitset &Bits = getFeatureBits();
246  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
249 
250  if (isRWPI())
251  ReserveR9 = true;
252 
253  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
254  switch (ARMProcFamily) {
255  case Others:
256  case CortexA5:
257  break;
258  case CortexA7:
260  break;
261  case CortexA8:
263  break;
264  case CortexA9:
267  break;
268  case CortexA12:
269  break;
270  case CortexA15:
274  break;
275  case CortexA17:
276  case CortexA32:
277  case CortexA35:
278  case CortexA53:
279  case CortexA55:
280  case CortexA57:
281  case CortexA72:
282  case CortexA73:
283  case CortexA75:
284  case CortexR4:
285  case CortexR4F:
286  case CortexR5:
287  case CortexR7:
288  case CortexM3:
289  case CortexR52:
290  case ExynosM1:
291  case Kryo:
292  break;
293  case Krait:
295  break;
296  case Swift:
301  break;
302  }
303 }
304 
308 }
313 }
317 }
318 
319 bool ARMSubtarget::isROPI() const {
320  return TM.getRelocationModel() == Reloc::ROPI ||
322 }
323 bool ARMSubtarget::isRWPI() const {
324  return TM.getRelocationModel() == Reloc::RWPI ||
326 }
327 
329  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
330  return true;
331 
332  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
333  // the section that is being relocated. This means we have to use o load even
334  // for GVs that are known to be local to the dso.
336  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
337  return true;
338 
339  return false;
340 }
341 
342 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
343  return isTargetELF() && TM.isPositionIndependent() &&
344  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
345 }
346 
349 }
350 
352  // Enable the MachineScheduler before register allocation for subtargets
353  // with the use-misched feature.
354  return useMachineScheduler();
355 }
356 
357 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
360  return false;
361  // Don't reschedule potential IT blocks.
362  return !isThumb1Only();
363 }
364 
366 
368  // For general targets, the prologue can grow when VFPs are allocated with
369  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
370  // format which it's more important to get right.
371  return isTargetWatchABI() || (isSwift() && !MF.getFunction().optForMinSize());
372 }
373 
374 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
375  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
376  // immediates as it is inherently position independent, and may be out of
377  // range otherwise.
378  return !NoMovt && hasV8MBaselineOps() &&
380 }
381 
383  // Enable fast-isel for any target, for testing only.
384  if (ForceFastISel)
385  return true;
386 
387  // Limit fast-isel to the targets that are or have been tested.
388  if (!hasV6Ops())
389  return false;
390 
391  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
392  return TM.Options.EnableFastISel &&
393  ((isTargetMachO() && !isThumb1Only()) ||
394  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
395 }
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:212
bool isDeclarationForLinker() const
Definition: GlobalValue.h:523
unsigned MispredictPenalty
Definition: MCSchedule.h:300
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:399
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:421
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isThumb() const
Definition: ARMSubtarget.h:677
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool useFastISel() const
True if fast-isel is used.
DWARF-like instruction based exceptions.
bool isTargetNaCl() const
Definition: ARMSubtarget.h:611
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:463
This class provides the information for the target register banks.
bool hasV6Ops() const
Definition: ARMSubtarget.h:504
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
bool isThumb1Only() const
Definition: ARMSubtarget.h:678
const LegalizerInfo * getLegalizerInfo() const override
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:432
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:217
bool genExecuteOnly() const
Definition: ARMSubtarget.h:594
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:175
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:513
bool isTargetELF() const
Definition: ARMSubtarget.h:616
Holds all the information related to register banks.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool hasARMOps() const
Definition: ARMSubtarget.h:531
bool hasV8Ops() const
Definition: ARMSubtarget.h:509
ExceptionHandling ExceptionModel
What exception model to use.
bool useStride4VFPs(const MachineFunction &MF) const
bool hasCommonLinkage() const
Definition: GlobalValue.h:439
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:418
bool useMovt(const MachineFunction &MF) const
bool enableAtomicExpand() const override
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:121
bool isXRaySupported() const override
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:205
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:507
This class provides the information for the target register banks.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:606
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:415
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:609
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Container class for subtarget features.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:131
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:372
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:630
This file declares the targeting of the Machinelegalizer class for ARM.
bool useMachineScheduler() const
Definition: ARMSubtarget.h:674
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
unsigned getMispredictionPenalty() const
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:938
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isTargetLinux() const
Definition: ARMSubtarget.h:610
const InstructionSelector * getInstructionSelector() const override
const Function & getFunction() const
Return the LLVM function that this machine code represents.
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:424
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:675
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:430
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isROPI() const
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:605
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
Provides the logic to select generic machine instructions.
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:604
bool isTargetIOS() const
Definition: ARMSubtarget.h:607
bool isPositionIndependent() const
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:208
TargetOptions Options
Definition: TargetMachine.h:98
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:427
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:171
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:471
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:581
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:407
ArchKind parseArch(StringRef Arch)
bool isTargetMachO() const
Definition: ARMSubtarget.h:617
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:411
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSwift() const
Definition: ARMSubtarget.h:524
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:126
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:559
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isRWPI() const
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:118
bool isTargetWindows() const
Definition: ARMSubtarget.h:613
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:402
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This file describes how to lower LLVM calls to machine code calls.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:555
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
ITMode
bool isAAPCS_ABI() const
bool hasThumb2() const
Definition: ARMSubtarget.h:680
const RegisterBankInfo * getRegBankInfo() const override
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:391
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:404