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Thumb2InstrInfo.h
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1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
16 
17 #include "ARMBaseInstrInfo.h"
18 #include "ThumbRegisterInfo.h"
19 
20 namespace llvm {
21 class ARMSubtarget;
22 class ScheduleHazardRecognizer;
23 
26 public:
27  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
28 
29  /// Return the noop instruction to use for a noop.
30  void getNoop(MCInst &NopInst) const override;
31 
32  // Return the non-pre/post incrementing version of 'Opc'. Return 0
33  // if there is not such an opcode.
34  unsigned getUnindexedOpcode(unsigned Opc) const override;
35 
37  MachineBasicBlock *NewDest) const override;
38 
40  MachineBasicBlock::iterator MBBI) const override;
41 
43  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
44  bool KillSrc) const override;
45 
48  unsigned SrcReg, bool isKill, int FrameIndex,
49  const TargetRegisterClass *RC,
50  const TargetRegisterInfo *TRI) const override;
51 
54  unsigned DestReg, int FrameIndex,
55  const TargetRegisterClass *RC,
56  const TargetRegisterInfo *TRI) const override;
57 
58  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
59  /// such, whenever a client has an instance of instruction info, it should
60  /// always be able to get register info as well (through this method).
61  ///
62  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
63 
64 private:
65  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
66 };
67 
68 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
69 /// to llvm::getInstrPredicate except it returns AL for conditional branch
70 /// instructions which are "predicated", but are not in IT blocks.
71 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
72 }
73 
74 #endif
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A debug info location.
Definition: DebugLoc.h:34
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getUnindexedOpcode(unsigned Opc) const override
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
Thumb2InstrInfo(const ARMSubtarget &STI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
Representation of each machine instruction.
Definition: MachineInstr.h:59
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
#define I(x, y, z)
Definition: MD5.cpp:58
IRTranslator LLVM IR MI