LLVM 19.0.0git
Thumb2InstrInfo.h
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1//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ThumbRegisterInfo.h"
18
19namespace llvm {
20class ARMSubtarget;
21
24public:
25 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
26
27 /// Return the noop instruction to use for a noop.
28 MCInst getNop() const override;
29
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const override;
33
35 MachineBasicBlock *NewDest) const override;
36
38 MachineBasicBlock::iterator MBBI) const override;
39
41 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
42 bool KillSrc) const override;
43
46 bool isKill, int FrameIndex,
47 const TargetRegisterClass *RC,
49 Register VReg) const override;
50
53 int FrameIndex, const TargetRegisterClass *RC,
55 Register VReg) const override;
56
57 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
58 /// such, whenever a client has an instance of instruction info, it should
59 /// always be able to get register info as well (through this method).
60 ///
61 const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
62
65 bool) const override;
66
68 unsigned OpIdx1,
69 unsigned OpIdx2) const override;
70
71private:
72 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
73};
74
75/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
76/// to llvm::getInstrPredicate except it returns AL for conditional branch
77/// instructions which are "predicated", but are not in IT blocks.
78ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
79
80// getVPTInstrPredicate: VPT analogue of that, plus a helper function
81// corresponding to MachineInstr::findFirstPredOperandIdx.
82int findFirstVPTPredOperandIdx(const MachineInstr &MI);
83ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
84 Register &PredReg);
86 Register PredReg;
87 return getVPTInstrPredicate(MI, PredReg);
88}
89
90// Recomputes the Block Mask of Instr, a VPT or VPST instruction.
91// This rebuilds the block mask of the instruction depending on the predicates
92// of the instructions following it. This should only be used after the
93// MVEVPTBlockInsertion pass has run, and should be used whenever a predicated
94// instruction is added to/removed from the block.
95void recomputeVPTBlockMask(MachineInstr &Instr);
96} // namespace llvm
97
98#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
unsigned getUnindexedOpcode(unsigned Opc) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
void recomputeVPTBlockMask(MachineInstr &Instr)