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llvm::ARMBaseInstrInfo Class Referenceabstract

#include "Target/ARM/ARMBaseInstrInfo.h"

Inheritance diagram for llvm::ARMBaseInstrInfo:
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Collaboration diagram for llvm::ARMBaseInstrInfo:
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Public Member Functions

bool hasNOP () const
 
virtual unsigned getUnindexedOpcode (unsigned Opc) const =0
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
 
virtual const ARMBaseRegisterInfogetRegisterInfo () const =0
 
const ARMSubtargetgetSubtarget () const
 
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
ARMCC::CondCodes getPredicate (const MachineInstr &MI) const
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
 
bool isPredicable (const MachineInstr &MI) const override
 isPredicable - Return true if the specified instruction can be predicated. More...
 
bool isAddrMode3OpImm (const MachineInstr &MI, unsigned Op) const
 
bool isAddrMode3OpMinusReg (const MachineInstr &MI, unsigned Op) const
 
bool isLdstScaledReg (const MachineInstr &MI, unsigned Op) const
 
bool isLdstScaledRegNotPlusLsl2 (const MachineInstr &MI, unsigned Op) const
 
bool isLdstSoMinusReg (const MachineInstr &MI, unsigned Op) const
 
bool isAm2ScaledReg (const MachineInstr &MI, unsigned Op) const
 
bool isLDMBaseRegInList (const MachineInstr &MI) const
 
unsigned getLDMVariableDefsSize (const MachineInstr &MI) const
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Returns the size of the specified MachineInstr. More...
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
 
void copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
 
void copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
 
MachineInstrduplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
 
const MachineInstrBuilderAddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
 
bool produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More...
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More...
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB. More...
 
bool analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
 
MachineInstroptimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool) const override
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
 FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. More...
 
unsigned getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
 
std::pair< uint16_t, uint16_t > getExecutionDomain (const MachineInstr &MI) const override
 VFP/NEON execution domains. More...
 
void setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
 
unsigned getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
 
void breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
 
unsigned getNumLDMAddresses (const MachineInstr &MI) const
 Get the number of addresses by LDM or VLDM or zero for unknown. More...
 
bool isFpMLxInstruction (unsigned Opcode) const
 isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction. More...
 
bool isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
 isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to. More...
 
bool canCauseFpMLxStall (unsigned Opcode) const
 canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction. More...
 
bool isSwiftFastImmShift (const MachineInstr *MI) const
 Returns true if the instruction has a shift by immediate that can be executed in one cycle less. More...
 
unsigned getFramePred (const MachineInstr &MI) const
 Returns predicate register associated with the given frame instruction. More...
 

Static Public Member Functions

static bool isCPSRDefined (const MachineInstr &MI)
 

Protected Member Functions

 ARMBaseInstrInfo (const ARMSubtarget &STI)
 
void expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
 
bool getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
 Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More...
 
bool getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
 Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More...
 
bool getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
 Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More...
 
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction. More...
 

Detailed Description

Definition at line 36 of file ARMBaseInstrInfo.h.

Constructor & Destructor Documentation

◆ ARMBaseInstrInfo()

ARMBaseInstrInfo::ARMBaseInstrInfo ( const ARMSubtarget STI)
explicitprotected

Member Function Documentation

◆ AddDReg()

const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg ( MachineInstrBuilder MIB,
unsigned  Reg,
unsigned  SubIdx,
unsigned  State,
const TargetRegisterInfo TRI 
) const

◆ analyzeBranch()

bool ARMBaseInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

◆ analyzeCompare()

bool ARMBaseInstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  CmpMask,
int &  CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 2458 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by isProfitableToDupForIfCvt().

◆ analyzeSelect()

bool ARMBaseInstrInfo::analyzeSelect ( const MachineInstr MI,
SmallVectorImpl< MachineOperand > &  Cond,
unsigned TrueOp,
unsigned FalseOp,
bool Optimizable 
) const
override

◆ areLoadsFromSameBasePtr()

bool ARMBaseInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1673 of file ARMBaseInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), and llvm::SDNode::isMachineOpcode().

Referenced by getPredicate().

◆ breakPartialRegDependency()

void ARMBaseInstrInfo::breakPartialRegDependency ( MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override

◆ canCauseFpMLxStall()

bool llvm::ARMBaseInstrInfo::canCauseFpMLxStall ( unsigned  Opcode) const
inline

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.

Definition at line 415 of file ARMBaseInstrInfo.h.

References llvm::SmallSet< T, N, C >::count(), and isSwiftFastImmShift().

Referenced by llvm::ARMHazardRecognizer::getHazardType().

◆ commuteInstructionImpl()

MachineInstr * ARMBaseInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 1951 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::ARMCC::getOppositeCondition().

◆ convertToThreeAddress()

MachineInstr * ARMBaseInstrInfo::convertToThreeAddress ( MachineFunction::iterator MFI,
MachineInstr MI,
LiveVariables LV 
) const
override

Definition at line 142 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::BuildMI(), llvm::condCodeOp(), EnableARM3Addr, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), isLoad(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, llvm::MachineInstr::mayStore(), llvm::predOps(), llvm::MachineInstr::readsRegister(), llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, llvm::MCInstrDesc::TSFlags, and VI.

◆ copyFromCPSR()

void ARMBaseInstrInfo::copyFromCPSR ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DestReg,
bool  KillSrc,
const ARMSubtarget Subtarget 
) const

◆ copyPhysReg()

void ARMBaseInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ copyToCPSR()

void ARMBaseInstrInfo::copyToCPSR ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  SrcReg,
bool  KillSrc,
const ARMSubtarget Subtarget 
) const

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo STI,
const ScheduleDAG DAG 
) const
override

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

◆ DefinesPredicate()

bool ARMBaseInstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override

◆ duplicate()

MachineInstr & ARMBaseInstrInfo::duplicate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsertBefore,
const MachineInstr Orig 
) const
override

◆ expandLoadStackGuardBase()

void ARMBaseInstrInfo::expandLoadStackGuardBase ( MachineBasicBlock::iterator  MI,
unsigned  LoadImmOpc,
unsigned  LoadOpc 
) const
protected

◆ expandPostRAPseudo()

bool ARMBaseInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ FoldImmediate()

bool ARMBaseInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
unsigned  Reg,
MachineRegisterInfo MRI 
) const
override

◆ getExecutionDomain()

std::pair< uint16_t, uint16_t > ARMBaseInstrInfo::getExecutionDomain ( const MachineInstr MI) const
override

◆ getExtractSubregLikeInputs()

bool ARMBaseInstrInfo::getExtractSubregLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPairAndIdx &  InputReg 
) const
overrideprotected

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:

  • vreg1:sub1, sub0
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isExtractSubregLike().

Definition at line 4869 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isExtractSubregLike(), llvm_unreachable, llvm::MachineOperand::Reg, and llvm::ARMISD::VMOVRRD.

◆ getFramePred()

unsigned llvm::ARMBaseInstrInfo::getFramePred ( const MachineInstr MI) const
inline

Returns predicate register associated with the given frame instruction.

Definition at line 424 of file ARMBaseInstrInfo.h.

References assert(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves().

◆ getInsertSubregLikeInputs()

bool ARMBaseInstrInfo::getInsertSubregLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPair &  BaseReg,
RegSubRegPairAndIdx &  InsertedReg 
) const
overrideprotected

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:

  • BaseReg: vreg0:sub0
  • InsertedReg: vreg1:sub1, sub3
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isInsertSubregLike().

Definition at line 4890 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isInsertSubregLike(), llvm_unreachable, and llvm::MachineOperand::Reg.

◆ getInstSizeInBytes()

unsigned ARMBaseInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getLDMVariableDefsSize()

unsigned ARMBaseInstrInfo::getLDMVariableDefsSize ( const MachineInstr MI) const

◆ getNumLDMAddresses()

unsigned ARMBaseInstrInfo::getNumLDMAddresses ( const MachineInstr MI) const

Get the number of addresses by LDM or VLDM or zero for unknown.

Definition at line 3247 of file ARMBaseInstrInfo.cpp.

References E, I, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), and llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size.

Referenced by isProfitableToDupForIfCvt().

◆ getNumMicroOps()

unsigned ARMBaseInstrInfo::getNumMicroOps ( const InstrItineraryData ItinData,
const MachineInstr MI 
) const
override

◆ getOperandLatency() [1/2]

int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

◆ getOperandLatency() [2/2]

int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
override

Definition at line 4012 of file ARMBaseInstrInfo.cpp.

References adjustDefLatency(), llvm::TargetSchedModel::computeOperandLatency(), llvm::convertAddSubFlagsOpcode(), llvm::ARMII::DomainGeneral, llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainVFP, llvm::dyn_cast(), E, getAlignment(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::MachineInstr::getDesc(), llvm::TargetSchedModel::getInstrItineraries(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::SDNode::getMachineOpcode(), llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOps(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::SDNode::getOperand(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::MachineInstr::getParent(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::getStageLatency(), llvm::MCInstrDesc::hasImplicitDefOfPhysReg(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundle(), llvm::MCInstrDesc::isCall(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::SDNode::isMachineOpcode(), llvm::MachineInstr::isRegSequence(), llvm::Latency, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::memoperands_begin(), llvm::MachineSDNode::memoperands_begin(), llvm::MachineSDNode::memoperands_empty(), MRI, llvm::MCInstrDesc::Opcode, Threshold, and llvm::MCInstrDesc::TSFlags.

◆ getPartialRegUpdateClearance()

unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override

◆ getPredicate()

ARMCC::CondCodes llvm::ARMBaseInstrInfo::getPredicate ( const MachineInstr MI) const
inline

◆ getRegisterInfo()

virtual const ARMBaseRegisterInfo& llvm::ARMBaseInstrInfo::getRegisterInfo ( ) const
pure virtual

◆ getRegSequenceLikeInputs()

bool ARMBaseInstrInfo::getRegSequenceLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
SmallVectorImpl< RegSubRegPairAndIdx > &  InputRegs 
) const
overrideprotected

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce two elements:

  • vreg1:sub1, sub0
  • vreg2<:0>, sub1
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isRegSequenceLike().

Definition at line 4844 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isRegSequenceLike(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ARMISD::VMOVDRR.

◆ getSubtarget()

const ARMSubtarget& llvm::ARMBaseInstrInfo::getSubtarget ( ) const
inline

◆ getUnindexedOpcode()

virtual unsigned llvm::ARMBaseInstrInfo::getUnindexedOpcode ( unsigned  Opc) const
pure virtual

◆ hasNOP()

bool ARMBaseInstrInfo::hasNOP ( ) const

Definition at line 4826 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMInstrInfo::getNoop().

◆ insertBranch()

unsigned ARMBaseInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ isAddrMode3OpImm()

bool ARMBaseInstrInfo::isAddrMode3OpImm ( const MachineInstr MI,
unsigned  Op 
) const

Definition at line 568 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by getPredicate().

◆ isAddrMode3OpMinusReg()

bool ARMBaseInstrInfo::isAddrMode3OpMinusReg ( const MachineInstr MI,
unsigned  Op 
) const

◆ isAm2ScaledReg()

bool ARMBaseInstrInfo::isAm2ScaledReg ( const MachineInstr MI,
unsigned  Op 
) const

◆ isCPSRDefined()

bool ARMBaseInstrInfo::isCPSRDefined ( const MachineInstr MI)
static

Definition at line 561 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstr::operands().

Referenced by getPredicate(), and isEligibleForITBlock().

◆ isFpMLxInstruction() [1/2]

bool llvm::ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode) const
inline

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition at line 401 of file ARMBaseInstrInfo.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::count().

Referenced by llvm::ARMHazardRecognizer::getHazardType(), and isScaledConstantInRange().

◆ isFpMLxInstruction() [2/2]

bool ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode,
unsigned MulOpc,
unsigned AddSubOpc,
bool NegAcc,
bool HasLane 
) const

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.

Return true for 'HasLane' for the MLX instructions with an extra lane operand.

Definition at line 4397 of file ARMBaseInstrInfo.cpp.

References ARM_MLxEntry::AddSubOpc, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), ARM_MLxEntry::HasLane, I, ARM_MLxEntry::MulOpc, and ARM_MLxEntry::NegAcc.

◆ isLDMBaseRegInList()

bool ARMBaseInstrInfo::isLDMBaseRegInList ( const MachineInstr MI) const

◆ isLdstScaledReg()

bool ARMBaseInstrInfo::isLdstScaledReg ( const MachineInstr MI,
unsigned  Op 
) const

◆ isLdstScaledRegNotPlusLsl2()

bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2 ( const MachineInstr MI,
unsigned  Op 
) const

◆ isLdstSoMinusReg()

bool ARMBaseInstrInfo::isLdstSoMinusReg ( const MachineInstr MI,
unsigned  Op 
) const

◆ isLoadFromStackSlot()

unsigned ARMBaseInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isLoadFromStackSlotPostFE()

unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isPredicable()

bool ARMBaseInstrInfo::isPredicable ( const MachineInstr MI) const
override

◆ isPredicated()

bool ARMBaseInstrInfo::isPredicated ( const MachineInstr MI) const
override

◆ isProfitableToDupForIfCvt()

bool llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlineoverride

◆ isProfitableToIfCvt() [1/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
override

◆ isProfitableToIfCvt() [2/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock FMBB,
unsigned  NumF,
unsigned  ExtraF,
BranchProbability  Probability 
) const
override

◆ isProfitableToUnpredicate()

bool ARMBaseInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
override

Definition at line 1918 of file ARMBaseInstrInfo.cpp.

Referenced by isProfitableToDupForIfCvt().

◆ isSchedulingBoundary()

bool ARMBaseInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

◆ isStoreToStackSlot()

unsigned ARMBaseInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isStoreToStackSlotPostFE()

unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isSwiftFastImmShift()

bool ARMBaseInstrInfo::isSwiftFastImmShift ( const MachineInstr MI) const

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 4830 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, and llvm::ARM_AM::lsr.

Referenced by canCauseFpMLxStall().

◆ loadRegFromStackSlot()

void ARMBaseInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ optimizeCompareInstr()

bool ARMBaseInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.

E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.

Definition at line 2620 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, assert(), B, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), E, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), first, llvm::ARMCC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, I, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDef(), isOptimizeCompareCandidate(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, MI, llvm::MachineInstr::modifiesRegister(), llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::removeFromParent(), llvm::MachineOperand::setIsDef(), llvm::MachineOperand::setReg(), SI, llvm::SmallVectorTemplateCommon< T >::size(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.

Referenced by isProfitableToDupForIfCvt().

◆ optimizeSelect()

MachineInstr * ARMBaseInstrInfo::optimizeSelect ( MachineInstr MI,
SmallPtrSetImpl< MachineInstr *> &  SeenMIs,
bool  PreferFalse 
) const
override

◆ PredicateInstruction()

bool ARMBaseInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ produceSameValue()

bool ARMBaseInstrInfo::produceSameValue ( const MachineInstr MI0,
const MachineInstr MI1,
const MachineRegisterInfo MRI 
) const
override

◆ reMaterialize()

void ARMBaseInstrInfo::reMaterialize ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
unsigned  SubIdx,
const MachineInstr Orig,
const TargetRegisterInfo TRI 
) const
override

◆ removeBranch()

unsigned ARMBaseInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool ARMBaseInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 477 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::getOppositeCondition().

Referenced by getSubtarget(), and insertBranch().

◆ setExecutionDomain()

void ARMBaseInstrInfo::setExecutionDomain ( MachineInstr MI,
unsigned  Domain 
) const
override

◆ shouldScheduleLoadsNear()

bool ARMBaseInstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1754 of file ARMBaseInstrInfo.cpp.

References assert(), and llvm::SDNode::getMachineOpcode().

Referenced by getPredicate().

◆ storeRegToStackSlot()

void ARMBaseInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ SubsumesPredicate()

bool ARMBaseInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

The documentation for this class was generated from the following files: