LLVM  6.0.0svn
llvm::ARMBaseInstrInfo Member List

This is the complete list of members for llvm::ARMBaseInstrInfo, including all inherited members.

AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) constllvm::ARMBaseInstrInfo
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const overridellvm::ARMBaseInstrInfo
analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const overridellvm::ARMBaseInstrInfo
analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const overridellvm::ARMBaseInstrInfo
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::ARMBaseInstrInfo
ARMBaseInstrInfo(const ARMSubtarget &STI)llvm::ARMBaseInstrInfoexplicitprotected
breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const overridellvm::ARMBaseInstrInfo
canCauseFpMLxStall(unsigned Opcode) constllvm::ARMBaseInstrInfoinline
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const overridellvm::ARMBaseInstrInfoprotected
convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const overridellvm::ARMBaseInstrInfo
copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) constllvm::ARMBaseInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::ARMBaseInstrInfo
copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) constllvm::ARMBaseInstrInfo
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const overridellvm::ARMBaseInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const overridellvm::ARMBaseInstrInfo
DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const overridellvm::ARMBaseInstrInfo
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const overridellvm::ARMBaseInstrInfo
expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) constllvm::ARMBaseInstrInfoprotected
expandPostRAPseudo(MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const overridellvm::ARMBaseInstrInfo
getExecutionDomain(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const overridellvm::ARMBaseInstrInfoprotected
getFramePred(const MachineInstr &MI) constllvm::ARMBaseInstrInfoinline
getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const overridellvm::ARMBaseInstrInfoprotected
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
getLDMVariableDefsSize(const MachineInstr &MI) constllvm::ARMBaseInstrInfo
getNumLDMAddresses(const MachineInstr &MI) constllvm::ARMBaseInstrInfo
getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::ARMBaseInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const overridellvm::ARMBaseInstrInfo
getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const overridellvm::ARMBaseInstrInfo
getPredicate(const MachineInstr &MI) constllvm::ARMBaseInstrInfoinline
getRegisterInfo() const =0llvm::ARMBaseInstrInfopure virtual
getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const overridellvm::ARMBaseInstrInfoprotected
getSubtarget() constllvm::ARMBaseInstrInfoinline
getUnindexedOpcode(unsigned Opc) const =0llvm::ARMBaseInstrInfopure virtual
hasNOP() constllvm::ARMBaseInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::ARMBaseInstrInfo
isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) constllvm::ARMBaseInstrInfo
isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) constllvm::ARMBaseInstrInfo
isAm2ScaledReg(const MachineInstr &MI, unsigned Op) constllvm::ARMBaseInstrInfo
isCPSRDefined(const MachineInstr &MI)llvm::ARMBaseInstrInfostatic
isFpMLxInstruction(unsigned Opcode) constllvm::ARMBaseInstrInfoinline
isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) constllvm::ARMBaseInstrInfo
isLDMBaseRegInList(const MachineInstr &MI) constllvm::ARMBaseInstrInfo
isLdstScaledReg(const MachineInstr &MI, unsigned Op) constllvm::ARMBaseInstrInfo
isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) constllvm::ARMBaseInstrInfo
isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) constllvm::ARMBaseInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isPredicable(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
isPredicated(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::ARMBaseInstrInfoinline
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::ARMBaseInstrInfo
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const overridellvm::ARMBaseInstrInfo
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const overridellvm::ARMBaseInstrInfo
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const overridellvm::ARMBaseInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isSwiftFastImmShift(const MachineInstr *MI) constllvm::ARMBaseInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::ARMBaseInstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const overridellvm::ARMBaseInstrInfo
optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool) const overridellvm::ARMBaseInstrInfo
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const overridellvm::ARMBaseInstrInfo
produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const overridellvm::ARMBaseInstrInfo
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const overridellvm::ARMBaseInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::ARMBaseInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::ARMBaseInstrInfo
setExecutionDomain(MachineInstr &MI, unsigned Domain) const overridellvm::ARMBaseInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::ARMBaseInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::ARMBaseInstrInfo
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const overridellvm::ARMBaseInstrInfo