LLVM  6.0.0svn
LiveVariables.cpp
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1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
15 // killed).
16 //
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
26 //
27 //===----------------------------------------------------------------------===//
28 
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Support/Debug.h"
41 #include <algorithm>
42 using namespace llvm;
43 
44 char LiveVariables::ID = 0;
47  "Live Variable Analysis", false, false)
48 INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
50  "Live Variable Analysis", false, false)
51 
52 
53 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
54  AU.addRequiredID(UnreachableMachineBlockElimID);
55  AU.setPreservesAll();
57 }
58 
61  for (unsigned i = 0, e = Kills.size(); i != e; ++i)
62  if (Kills[i]->getParent() == MBB)
63  return Kills[i];
64  return nullptr;
65 }
66 
67 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
69  dbgs() << " Alive in blocks: ";
71  E = AliveBlocks.end(); I != E; ++I)
72  dbgs() << *I << ", ";
73  dbgs() << "\n Killed by:";
74  if (Kills.empty())
75  dbgs() << " No instructions.\n";
76  else {
77  for (unsigned i = 0, e = Kills.size(); i != e; ++i)
78  dbgs() << "\n #" << i << ": " << *Kills[i];
79  dbgs() << "\n";
80  }
81 }
82 #endif
83 
84 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
87  "getVarInfo: not a virtual register!");
88  VirtRegInfo.grow(RegIdx);
89  return VirtRegInfo[RegIdx];
90 }
91 
93  MachineBasicBlock *DefBlock,
94  MachineBasicBlock *MBB,
95  std::vector<MachineBasicBlock*> &WorkList) {
96  unsigned BBNum = MBB->getNumber();
97 
98  // Check to see if this basic block is one of the killing blocks. If so,
99  // remove it.
100  for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
101  if (VRInfo.Kills[i]->getParent() == MBB) {
102  VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
103  break;
104  }
105 
106  if (MBB == DefBlock) return; // Terminate recursion
107 
108  if (VRInfo.AliveBlocks.test(BBNum))
109  return; // We already know the block is live
110 
111  // Mark the variable known alive in this bb
112  VRInfo.AliveBlocks.set(BBNum);
113 
114  assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
115  WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
116 }
117 
119  MachineBasicBlock *DefBlock,
120  MachineBasicBlock *MBB) {
121  std::vector<MachineBasicBlock*> WorkList;
122  MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
123 
124  while (!WorkList.empty()) {
125  MachineBasicBlock *Pred = WorkList.back();
126  WorkList.pop_back();
127  MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
128  }
129 }
130 
132  MachineInstr &MI) {
133  assert(MRI->getVRegDef(reg) && "Register use before def!");
134 
135  unsigned BBNum = MBB->getNumber();
136 
137  VarInfo& VRInfo = getVarInfo(reg);
138 
139  // Check to see if this basic block is already a kill block.
140  if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
141  // Yes, this register is killed in this basic block already. Increase the
142  // live range by updating the kill instruction.
143  VRInfo.Kills.back() = &MI;
144  return;
145  }
146 
147 #ifndef NDEBUG
148  for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
149  assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
150 #endif
151 
152  // This situation can occur:
153  //
154  // ,------.
155  // | |
156  // | v
157  // | t2 = phi ... t1 ...
158  // | |
159  // | v
160  // | t1 = ...
161  // | ... = ... t1 ...
162  // | |
163  // `------'
164  //
165  // where there is a use in a PHI node that's a predecessor to the defining
166  // block. We don't want to mark all predecessors as having the value "alive"
167  // in this case.
168  if (MBB == MRI->getVRegDef(reg)->getParent()) return;
169 
170  // Add a new kill entry for this basic block. If this virtual register is
171  // already marked as alive in this basic block, that means it is alive in at
172  // least one of the successor blocks, it's not a kill.
173  if (!VRInfo.AliveBlocks.test(BBNum))
174  VRInfo.Kills.push_back(&MI);
175 
176  // Update all dominating blocks to mark them as "known live".
178  E = MBB->pred_end(); PI != E; ++PI)
179  MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
180 }
181 
183  VarInfo &VRInfo = getVarInfo(Reg);
184 
185  if (VRInfo.AliveBlocks.empty())
186  // If vr is not alive in any block, then defaults to dead.
187  VRInfo.Kills.push_back(&MI);
188 }
189 
190 /// FindLastPartialDef - Return the last partial def of the specified register.
191 /// Also returns the sub-registers that're defined by the instruction.
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
193  SmallSet<unsigned,4> &PartDefRegs) {
194  unsigned LastDefReg = 0;
195  unsigned LastDefDist = 0;
196  MachineInstr *LastDef = nullptr;
197  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
198  unsigned SubReg = *SubRegs;
199  MachineInstr *Def = PhysRegDef[SubReg];
200  if (!Def)
201  continue;
202  unsigned Dist = DistanceMap[Def];
203  if (Dist > LastDefDist) {
204  LastDefReg = SubReg;
205  LastDef = Def;
206  LastDefDist = Dist;
207  }
208  }
209 
210  if (!LastDef)
211  return nullptr;
212 
213  PartDefRegs.insert(LastDefReg);
214  for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
215  MachineOperand &MO = LastDef->getOperand(i);
216  if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
217  continue;
218  unsigned DefReg = MO.getReg();
219  if (TRI->isSubRegister(Reg, DefReg)) {
220  for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
221  SubRegs.isValid(); ++SubRegs)
222  PartDefRegs.insert(*SubRegs);
223  }
224  }
225  return LastDef;
226 }
227 
228 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
229 /// implicit defs to a machine instruction if there was an earlier def of its
230 /// super-register.
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
232  MachineInstr *LastDef = PhysRegDef[Reg];
233  // If there was a previous use or a "full" def all is well.
234  if (!LastDef && !PhysRegUse[Reg]) {
235  // Otherwise, the last sub-register def implicitly defines this register.
236  // e.g.
237  // AH =
238  // AL = ... <imp-def EAX>, <imp-kill AH>
239  // = AH
240  // ...
241  // = EAX
242  // All of the sub-registers must have been defined before the use of Reg!
243  SmallSet<unsigned, 4> PartDefRegs;
244  MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
245  // If LastPartialDef is NULL, it must be using a livein register.
246  if (LastPartialDef) {
247  LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
248  true/*IsImp*/));
249  PhysRegDef[Reg] = LastPartialDef;
250  SmallSet<unsigned, 8> Processed;
251  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
252  unsigned SubReg = *SubRegs;
253  if (Processed.count(SubReg))
254  continue;
255  if (PartDefRegs.count(SubReg))
256  continue;
257  // This part of Reg was defined before the last partial def. It's killed
258  // here.
259  LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
260  false/*IsDef*/,
261  true/*IsImp*/));
262  PhysRegDef[SubReg] = LastPartialDef;
263  for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
264  Processed.insert(*SS);
265  }
266  }
267  } else if (LastDef && !PhysRegUse[Reg] &&
268  !LastDef->findRegisterDefOperand(Reg))
269  // Last def defines the super register, add an implicit def of reg.
270  LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
271  true/*IsImp*/));
272 
273  // Remember this use.
274  for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
275  SubRegs.isValid(); ++SubRegs)
276  PhysRegUse[*SubRegs] = &MI;
277 }
278 
279 /// FindLastRefOrPartRef - Return the last reference or partial reference of
280 /// the specified register.
281 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
282  MachineInstr *LastDef = PhysRegDef[Reg];
283  MachineInstr *LastUse = PhysRegUse[Reg];
284  if (!LastDef && !LastUse)
285  return nullptr;
286 
287  MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
288  unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
289  unsigned LastPartDefDist = 0;
290  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
291  unsigned SubReg = *SubRegs;
292  MachineInstr *Def = PhysRegDef[SubReg];
293  if (Def && Def != LastDef) {
294  // There was a def of this sub-register in between. This is a partial
295  // def, keep track of the last one.
296  unsigned Dist = DistanceMap[Def];
297  if (Dist > LastPartDefDist)
298  LastPartDefDist = Dist;
299  } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
300  unsigned Dist = DistanceMap[Use];
301  if (Dist > LastRefOrPartRefDist) {
302  LastRefOrPartRefDist = Dist;
303  LastRefOrPartRef = Use;
304  }
305  }
306  }
307 
308  return LastRefOrPartRef;
309 }
310 
311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
312  MachineInstr *LastDef = PhysRegDef[Reg];
313  MachineInstr *LastUse = PhysRegUse[Reg];
314  if (!LastDef && !LastUse)
315  return false;
316 
317  MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
318  unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
319  // The whole register is used.
320  // AL =
321  // AH =
322  //
323  // = AX
324  // = AL, AX<imp-use, kill>
325  // AX =
326  //
327  // Or whole register is defined, but not used at all.
328  // AX<dead> =
329  // ...
330  // AX =
331  //
332  // Or whole register is defined, but only partly used.
333  // AX<dead> = AL<imp-def>
334  // = AL<kill>
335  // AX =
336  MachineInstr *LastPartDef = nullptr;
337  unsigned LastPartDefDist = 0;
338  SmallSet<unsigned, 8> PartUses;
339  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
340  unsigned SubReg = *SubRegs;
341  MachineInstr *Def = PhysRegDef[SubReg];
342  if (Def && Def != LastDef) {
343  // There was a def of this sub-register in between. This is a partial
344  // def, keep track of the last one.
345  unsigned Dist = DistanceMap[Def];
346  if (Dist > LastPartDefDist) {
347  LastPartDefDist = Dist;
348  LastPartDef = Def;
349  }
350  continue;
351  }
352  if (MachineInstr *Use = PhysRegUse[SubReg]) {
353  for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid();
354  ++SS)
355  PartUses.insert(*SS);
356  unsigned Dist = DistanceMap[Use];
357  if (Dist > LastRefOrPartRefDist) {
358  LastRefOrPartRefDist = Dist;
359  LastRefOrPartRef = Use;
360  }
361  }
362  }
363 
364  if (!PhysRegUse[Reg]) {
365  // Partial uses. Mark register def dead and add implicit def of
366  // sub-registers which are used.
367  // EAX<dead> = op AL<imp-def>
368  // That is, EAX def is dead but AL def extends pass it.
369  PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
370  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
371  unsigned SubReg = *SubRegs;
372  if (!PartUses.count(SubReg))
373  continue;
374  bool NeedDef = true;
375  if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
376  MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
377  if (MO) {
378  NeedDef = false;
379  assert(!MO->isDead());
380  }
381  }
382  if (NeedDef)
383  PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
384  true/*IsDef*/, true/*IsImp*/));
385  MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
386  if (LastSubRef)
387  LastSubRef->addRegisterKilled(SubReg, TRI, true);
388  else {
389  LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
390  for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
391  SS.isValid(); ++SS)
392  PhysRegUse[*SS] = LastRefOrPartRef;
393  }
394  for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
395  PartUses.erase(*SS);
396  }
397  } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
398  if (LastPartDef)
399  // The last partial def kills the register.
400  LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
401  true/*IsImp*/, true/*IsKill*/));
402  else {
403  MachineOperand *MO =
404  LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
405  bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
406  // If the last reference is the last def, then it's not used at all.
407  // That is, unless we are currently processing the last reference itself.
408  LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
409  if (NeedEC) {
410  // If we are adding a subreg def and the superreg def is marked early
411  // clobber, add an early clobber marker to the subreg def.
412  MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
413  if (MO)
414  MO->setIsEarlyClobber();
415  }
416  }
417  } else
418  LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
419  return true;
420 }
421 
422 void LiveVariables::HandleRegMask(const MachineOperand &MO) {
423  // Call HandlePhysRegKill() for all live registers clobbered by Mask.
424  // Clobbered registers are always dead, sp there is no need to use
425  // HandlePhysRegDef().
426  for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
427  // Skip dead regs.
428  if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
429  continue;
430  // Skip mask-preserved regs.
431  if (!MO.clobbersPhysReg(Reg))
432  continue;
433  // Kill the largest clobbered super-register.
434  // This avoids needless implicit operands.
435  unsigned Super = Reg;
436  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
437  if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
438  Super = *SR;
439  HandlePhysRegKill(Super, nullptr);
440  }
441 }
442 
443 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
445  // What parts of the register are previously defined?
447  if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
448  for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
449  SubRegs.isValid(); ++SubRegs)
450  Live.insert(*SubRegs);
451  } else {
452  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
453  unsigned SubReg = *SubRegs;
454  // If a register isn't itself defined, but all parts that make up of it
455  // are defined, then consider it also defined.
456  // e.g.
457  // AL =
458  // AH =
459  // = AX
460  if (Live.count(SubReg))
461  continue;
462  if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
463  for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
464  SS.isValid(); ++SS)
465  Live.insert(*SS);
466  }
467  }
468  }
469 
470  // Start from the largest piece, find the last time any part of the register
471  // is referenced.
472  HandlePhysRegKill(Reg, MI);
473  // Only some of the sub-registers are used.
474  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
475  unsigned SubReg = *SubRegs;
476  if (!Live.count(SubReg))
477  // Skip if this sub-register isn't defined.
478  continue;
479  HandlePhysRegKill(SubReg, MI);
480  }
481 
482  if (MI)
483  Defs.push_back(Reg); // Remember this def.
484 }
485 
486 void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
488  while (!Defs.empty()) {
489  unsigned Reg = Defs.back();
490  Defs.pop_back();
491  for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
492  SubRegs.isValid(); ++SubRegs) {
493  unsigned SubReg = *SubRegs;
494  PhysRegDef[SubReg] = &MI;
495  PhysRegUse[SubReg] = nullptr;
496  }
497  }
498 }
499 
500 void LiveVariables::runOnInstr(MachineInstr &MI,
502  assert(!MI.isDebugValue());
503  // Process all of the operands of the instruction...
504  unsigned NumOperandsToProcess = MI.getNumOperands();
505 
506  // Unless it is a PHI node. In this case, ONLY process the DEF, not any
507  // of the uses. They will be handled in other basic blocks.
508  if (MI.isPHI())
509  NumOperandsToProcess = 1;
510 
511  // Clear kill and dead markers. LV will recompute them.
512  SmallVector<unsigned, 4> UseRegs;
513  SmallVector<unsigned, 4> DefRegs;
514  SmallVector<unsigned, 1> RegMasks;
515  for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
516  MachineOperand &MO = MI.getOperand(i);
517  if (MO.isRegMask()) {
518  RegMasks.push_back(i);
519  continue;
520  }
521  if (!MO.isReg() || MO.getReg() == 0)
522  continue;
523  unsigned MOReg = MO.getReg();
524  if (MO.isUse()) {
526  MRI->isReserved(MOReg)))
527  MO.setIsKill(false);
528  if (MO.readsReg())
529  UseRegs.push_back(MOReg);
530  } else {
531  assert(MO.isDef());
532  // FIXME: We should not remove any dead flags. However the MIPS RDDSP
533  // instruction needs it at the moment: http://llvm.org/PR27116.
535  !MRI->isReserved(MOReg))
536  MO.setIsDead(false);
537  DefRegs.push_back(MOReg);
538  }
539  }
540 
541  MachineBasicBlock *MBB = MI.getParent();
542  // Process all uses.
543  for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
544  unsigned MOReg = UseRegs[i];
546  HandleVirtRegUse(MOReg, MBB, MI);
547  else if (!MRI->isReserved(MOReg))
548  HandlePhysRegUse(MOReg, MI);
549  }
550 
551  // Process all masked registers. (Call clobbers).
552  for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
553  HandleRegMask(MI.getOperand(RegMasks[i]));
554 
555  // Process all defs.
556  for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
557  unsigned MOReg = DefRegs[i];
559  HandleVirtRegDef(MOReg, MI);
560  else if (!MRI->isReserved(MOReg))
561  HandlePhysRegDef(MOReg, &MI, Defs);
562  }
563  UpdatePhysRegDefs(MI, Defs);
564 }
565 
566 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
567  // Mark live-in registers as live-in.
569  for (const auto &LI : MBB->liveins()) {
571  "Cannot have a live-in virtual register!");
572  HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
573  }
574 
575  // Loop over all of the instructions, processing them.
576  DistanceMap.clear();
577  unsigned Dist = 0;
578  for (MachineInstr &MI : *MBB) {
579  if (MI.isDebugValue())
580  continue;
581  DistanceMap.insert(std::make_pair(&MI, Dist++));
582 
583  runOnInstr(MI, Defs);
584  }
585 
586  // Handle any virtual assignments from PHI nodes which might be at the
587  // bottom of this basic block. We check all of our successor blocks to see
588  // if they have PHI nodes, and if so, we simulate an assignment at the end
589  // of the current block.
590  if (!PHIVarInfo[MBB->getNumber()].empty()) {
591  SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
592 
593  for (SmallVectorImpl<unsigned>::iterator I = VarInfoVec.begin(),
594  E = VarInfoVec.end(); I != E; ++I)
595  // Mark it alive only in the block we are representing.
596  MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
597  MBB);
598  }
599 
600  // MachineCSE may CSE instructions which write to non-allocatable physical
601  // registers across MBBs. Remember if any reserved register is liveout.
602  SmallSet<unsigned, 4> LiveOuts;
603  for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
604  SE = MBB->succ_end(); SI != SE; ++SI) {
605  MachineBasicBlock *SuccMBB = *SI;
606  if (SuccMBB->isEHPad())
607  continue;
608  for (const auto &LI : SuccMBB->liveins()) {
609  if (!TRI->isInAllocatableClass(LI.PhysReg))
610  // Ignore other live-ins, e.g. those that are live into landing pads.
611  LiveOuts.insert(LI.PhysReg);
612  }
613  }
614 
615  // Loop over PhysRegDef / PhysRegUse, killing any registers that are
616  // available at the end of the basic block.
617  for (unsigned i = 0; i != NumRegs; ++i)
618  if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
619  HandlePhysRegDef(i, nullptr, Defs);
620 }
621 
623  MF = &mf;
624  MRI = &mf.getRegInfo();
625  TRI = MF->getSubtarget().getRegisterInfo();
626 
627  const unsigned NumRegs = TRI->getNumRegs();
628  PhysRegDef.assign(NumRegs, nullptr);
629  PhysRegUse.assign(NumRegs, nullptr);
630  PHIVarInfo.resize(MF->getNumBlockIDs());
631  PHIJoins.clear();
632 
633  // FIXME: LiveIntervals will be updated to remove its dependence on
634  // LiveVariables to improve compilation time and eliminate bizarre pass
635  // dependencies. Until then, we can't change much in -O0.
636  if (!MRI->isSSA())
637  report_fatal_error("regalloc=... not currently supported with -O0");
638 
639  analyzePHINodes(mf);
640 
641  // Calculate live variable information in depth first order on the CFG of the
642  // function. This guarantees that we will see the definition of a virtual
643  // register before its uses due to dominance properties of SSA (except for PHI
644  // nodes, which are treated as a special case).
645  MachineBasicBlock *Entry = &MF->front();
647 
648  for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
649  runOnBlock(MBB, NumRegs);
650 
651  PhysRegDef.assign(NumRegs, nullptr);
652  PhysRegUse.assign(NumRegs, nullptr);
653  }
654 
655  // Convert and transfer the dead / killed information we have gathered into
656  // VirtRegInfo onto MI's.
657  for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
658  const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
659  for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
660  if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
661  VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
662  else
663  VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
664  }
665 
666  // Check to make sure there are no unreachable blocks in the MC CFG for the
667  // function. If so, it is due to a bug in the instruction selector or some
668  // other part of the code generator if this happens.
669 #ifndef NDEBUG
670  for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
671  assert(Visited.count(&*i) != 0 && "unreachable basic block found");
672 #endif
673 
674  PhysRegDef.clear();
675  PhysRegUse.clear();
676  PHIVarInfo.clear();
677 
678  return false;
679 }
680 
681 /// replaceKillInstruction - Update register kill info by replacing a kill
682 /// instruction with a new one.
684  MachineInstr &NewMI) {
685  VarInfo &VI = getVarInfo(Reg);
686  std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);
687 }
688 
689 /// removeVirtualRegistersKilled - Remove all killed info for the specified
690 /// instruction.
692  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
693  MachineOperand &MO = MI.getOperand(i);
694  if (MO.isReg() && MO.isKill()) {
695  MO.setIsKill(false);
696  unsigned Reg = MO.getReg();
698  bool removed = getVarInfo(Reg).removeKill(MI);
699  assert(removed && "kill not in register's VarInfo?");
700  (void)removed;
701  }
702  }
703  }
704 }
705 
706 /// analyzePHINodes - Gather information about the PHI nodes in here. In
707 /// particular, we want to map the variable information of a virtual register
708 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
709 ///
710 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
711  for (const auto &MBB : Fn)
712  for (const auto &BBI : MBB) {
713  if (!BBI.isPHI())
714  break;
715  for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
716  if (BBI.getOperand(i).readsReg())
717  PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
718  .push_back(BBI.getOperand(i).getReg());
719  }
720 }
721 
723  unsigned Reg,
724  MachineRegisterInfo &MRI) {
725  unsigned Num = MBB.getNumber();
726 
727  // Reg is live-through.
728  if (AliveBlocks.test(Num))
729  return true;
730 
731  // Registers defined in MBB cannot be live in.
732  const MachineInstr *Def = MRI.getVRegDef(Reg);
733  if (Def && Def->getParent() == &MBB)
734  return false;
735 
736  // Reg was not defined in MBB, was it killed here?
737  return findKill(&MBB);
738 }
739 
740 bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
742 
744  for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
745  Kills.insert(VI.Kills[i]->getParent());
746 
747  // Loop over all of the successors of the basic block, checking to see if
748  // the value is either live in the block, or if it is killed in the block.
749  for (const MachineBasicBlock *SuccMBB : MBB.successors()) {
750  // Is it alive in this successor?
751  unsigned SuccIdx = SuccMBB->getNumber();
752  if (VI.AliveBlocks.test(SuccIdx))
753  return true;
754  // Or is it live because there is a use in a successor that kills it?
755  if (Kills.count(SuccMBB))
756  return true;
757  }
758 
759  return false;
760 }
761 
762 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
763 /// variables that are live out of DomBB will be marked as passing live through
764 /// BB.
766  MachineBasicBlock *DomBB,
767  MachineBasicBlock *SuccBB) {
768  const unsigned NumNew = BB->getNumber();
769 
771 
772  MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
773  for (; BBI != BBE && BBI->isPHI(); ++BBI) {
774  // Record the def of the PHI node.
775  Defs.insert(BBI->getOperand(0).getReg());
776 
777  // All registers used by PHI nodes in SuccBB must be live through BB.
778  for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
779  if (BBI->getOperand(i+1).getMBB() == BB)
780  getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
781  }
782 
783  // Record all vreg defs and kills of all instructions in SuccBB.
784  for (; BBI != BBE; ++BBI) {
785  for (MachineInstr::mop_iterator I = BBI->operands_begin(),
786  E = BBI->operands_end(); I != E; ++I) {
787  if (I->isReg() && TargetRegisterInfo::isVirtualRegister(I->getReg())) {
788  if (I->isDef())
789  Defs.insert(I->getReg());
790  else if (I->isKill())
791  Kills.insert(I->getReg());
792  }
793  }
794  }
795 
796  // Update info for all live variables
797  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
798  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
799 
800  // If the Defs is defined in the successor it can't be live in BB.
801  if (Defs.count(Reg))
802  continue;
803 
804  // If the register is either killed in or live through SuccBB it's also live
805  // through BB.
806  VarInfo &VI = getVarInfo(Reg);
807  if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
808  VI.AliveBlocks.set(NumNew);
809  }
810 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
iterator end() const
pred_reverse_iterator pred_rbegin()
void push_back(const T &Elt)
Definition: SmallVector.h:212
pred_reverse_iterator pred_rend()
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
void set(unsigned Idx)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB)
isLiveOut - Determine if Reg is live out from MBB, when not considering PHI nodes.
void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI)
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
void setIsDead(bool Val=true)
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
bool isPHI() const
Definition: MachineInstr.h:826
bool erase(const T &V)
Definition: SmallSet.h:108
iterator_range< succ_iterator > successors()
iterator begin() const
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
bool isEarlyClobber() const
bool test(unsigned Idx)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MCSuperRegIterator enumerates all super-registers of Reg.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:84
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
void setIsEarlyClobber(bool Val=true)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:187
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:371
iterator_range< df_ext_iterator< T, SetTy > > depth_first_ext(const T &G, SetTy &S)
Represent the analysis usage information of a pass.
livevars
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:382
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
MCSubRegIterator enumerates all sub-registers of Reg.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *BB)
void setIsKill(bool Val=true)
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
addNewBlock - Add a new basic block BB between DomBB and SuccBB.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction&#39;s which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
Iterator for intrusive lists based on ilist_node.
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void HandleVirtRegDef(unsigned reg, MachineInstr &MI)
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI)
isLiveIn - Is Reg live in to MBB? This means that Reg is live through MBB, or it is killed in MBB...
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void removeVirtualRegistersKilled(MachineInstr &MI)
removeVirtualRegistersKilled - Remove all killed info for the specified instruction.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isEHPad() const
Returns true if the block is a landing pad.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
#define I(x, y, z)
Definition: MD5.cpp:58
Live Variable Analysis
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Definition: DenseSet.h:91
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SparseBitVectorIterator iterator
static const Function * getParent(const Value *V)
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
static Expected< std::string > replace(StringRef S, StringRef From, StringRef To)
INITIALIZE_PASS_BEGIN(LiveVariables, "livevars", "Live Variable Analysis", false, false) INITIALIZE_PASS_END(LiveVariables
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65