224 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H 225 #define LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H 237 #include <unordered_map> 244 static_assert(
sizeof(
uint32_t) ==
sizeof(
unsigned),
"Those should be equal");
248 class MachineBasicBlock;
249 class MachineDominanceFrontier;
250 class MachineDominatorTree;
251 class MachineFunction;
253 class MachineOperand;
255 class TargetInstrInfo;
256 class TargetRegisterInfo;
313 uint16_t KB =
kind(B);
318 return KB ==
Phi || KB ==
Stmt;
341 : Addr(static_cast<
T>(NA.Addr)),
Id(NA.
Id) {}
345 return Addr == NA.
Addr;
375 enum { NodeMemSize = 32 };
378 : NodesPerBlock(NPB), BitsPerIndex(
Log2_32(NPB)),
379 IndexMask((1 << BitsPerIndex)-1) {
385 uint32_t BlockN = N1 >> BitsPerIndex;
395 void startNewBlock();
400 return ((Block << BitsPerIndex) | Index) + 1;
406 char *ActiveEnd =
nullptr;
407 std::vector<char*> Blocks;
418 virtual bool isPreserving(
const MachineInstr &
In,
unsigned OpNum)
const;
419 virtual bool isClobbering(
const MachineInstr &In,
unsigned OpNum)
const;
420 virtual bool isFixedReg(
const MachineInstr &In,
unsigned OpNum)
const;
440 return LM.
all() ? 0 : insert(LM);
445 return LM.
all() ? 0 :
find(LM);
467 void init() { memset(
this, 0,
sizeof *
this); }
510 "NodeBase must be at most NodeAllocator::NodeMemSize bytes");
552 template <
typename Predicate>
582 return Ref.PhiU.PredB;
592 return static_cast<T>(
Code.CP);
606 template <
typename Predicate>
622 return CodeNode::getCode<MachineInstr*>();
628 return CodeNode::getCode<MachineBasicBlock*>();
636 return CodeNode::getCode<MachineFunction*>();
651 return static_cast<T>(ptr(N));
657 return { ptr<T>(
N), N };
672 bool empty()
const {
return Stack.empty() || top() == bottom(); }
679 Iterator &up() { Pos =
DS.nextUp(Pos);
return *
this; }
680 Iterator &down() { Pos =
DS.nextDown(Pos);
return *
this; }
684 return DS.Stack[Pos-1];
688 return &
DS.Stack[Pos-1];
690 bool operator==(
const Iterator &It)
const {
return Pos == It.Pos; }
691 bool operator!=(
const Iterator &It)
const {
return Pos != It.Pos; }
696 Iterator(
const DefStack &S,
bool Top);
709 unsigned size()
const;
713 void start_block(
NodeId N);
714 void clear_block(
NodeId N);
717 friend struct Iterator;
719 using StorageType = std::vector<value_type>;
721 bool isDelimiter(
const StorageType::value_type &P,
NodeId N = 0)
const {
722 return (P.Addr ==
nullptr) && (N == 0 || P.Id ==
N);
725 unsigned nextUp(
unsigned P)
const;
726 unsigned nextDown(
unsigned P)
const;
741 return { RR.
Reg, LMI.getIndexForLaneMask(RR.
Mask) };
744 return { RR.
Reg, LMI.getIndexForLaneMask(RR.
Mask) };
769 return BlockNodes.at(BB);
785 template <u
int16_t Kind>
791 template <u
int16_t Kind>
813 uint16_t Flags = DA.
Addr->getFlags();
840 template <
typename Predicate>
845 using BlockRefsMap = std::map<NodeId, RegisterSet>;
849 void buildPhis(BlockRefsMap &PhiM,
RegisterSet &AllRefs,
851 void removeUnusedPhis();
857 template <
typename Predicate>
void linkStmtRefs(
DefStackMap &DefM,
866 IA.
Addr->removeMember(RA, *
this);
881 std::map<MachineBasicBlock*,NodeAddr<BlockNode*>> BlockNodes;
886 template <
typename Predicate>
893 while (NA.Addr !=
this) {
896 if (RA.
Addr->getRegRef(G) == RR &&
P(NA))
905 NA = CA.
Addr->getFirstMember(G);
912 template <
typename Predicate>
915 auto M = getFirstMember(G);
919 while (M.Addr !=
this) {
927 template <
typename T>
935 template <
typename T>
941 raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterRef> &
P);
942 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeId> &
P);
943 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<DefNode *>> &
P);
944 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<UseNode *>> &
P);
947 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<RefNode *>> &
P);
948 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeList> &
P);
949 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeSet> &
P);
950 raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<PhiNode *>> &
P);
959 raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterSet> &
P);
960 raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterAggr> &
P);
968 #endif // LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H NodeAddr< BlockNode * > findBlock(MachineBasicBlock *BB) const
raw_ostream & operator<<(raw_ostream &OS, const PrintLaneMaskOpt &P)
void setReachingDef(NodeId RD)
NodeId getReachedUse() const
A common definition of LaneBitmask for use in TableGen and CodeGen.
MachineFunction & getMF() const
uint16_t getFlags() const
static uint16_t kind(uint16_t T)
This class represents lattice values for constants.
static uint16_t type(uint16_t T)
void unlinkDef(NodeAddr< DefNode *> DA, bool RemoveFromOwner)
This class provides various memory handling functions that manipulate MemoryBlock instances...
static bool IsPreservingDef(const NodeAddr< DefNode *> DA)
void push_back(const T &Elt)
uint32_t getIndexForLaneMask(LaneBitmask LM) const
unsigned const TargetRegisterInfo * TRI
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
const TargetInstrInfo & TII
const TargetInstrInfo & getTII() const
SI optimize exec mask operations pre RA
NodeAddr< FuncNode * > getFunc() const
void append(SmallVectorImpl< char > &path, const Twine &a, const Twine &b="", const Twine &c="", const Twine &d="")
Append to path.
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
std::set< RegisterRef > RegisterSet
static constexpr LaneBitmask getAll()
void unlinkUse(NodeAddr< UseNode *> UA, bool RemoveFromOwner)
APInt operator*(APInt a, uint64_t RHS)
uint16_t getAttrs() const
static uint16_t set_flags(uint16_t A, uint16_t F)
const MachineDominatorTree & getDT() const
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
TargetInstrInfo - Interface to description of machine instruction set.
NodeAllocator(uint32_t NPB=4096)
void setFlags(uint16_t F)
void setReachedDef(NodeId D)
Error build(ArrayRef< Module *> Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)
Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.
static bool IsUse(const NodeAddr< NodeBase *> BA)
Control flow instructions. These all have token chains.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
PrintNode(const NodeAddr< T > &x, const DataFlowGraph &g)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
NodeAddr< T > addr(NodeId N) const
const TargetRegisterInfo & getTRI() const
LaneBitmask getLaneMaskForIndex(uint32_t K) const
MachineInstr * getCode() const
static bool IsPhi(const NodeAddr< NodeBase *> BA)
static uint16_t flags(uint16_t T)
TargetOperandInfo(const TargetInstrInfo &tii)
NodeId getPredecessor() const
constexpr bool all() const
static bool contains(uint16_t A, uint16_t B)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static wasm::ValType getType(const TargetRegisterClass *RC)
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
RegisterRef unpack(PackedRegisterRef PR) const
const PhysicalRegisterInfo & getPRI() const
void setPredecessor(NodeId B)
MachineFunction * getCode() const
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
NodeAddr(const NodeAddr< S > &NA)
MachineInstr * getCode() const
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
static uint32_t getFlags(const Symbol *Sym)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
void setAttrs(uint16_t A)
static uint16_t set_type(uint16_t A, uint16_t T)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
const MachineDominanceFrontier & getDF() const
NodeId getReachedDef() const
static void clear(coro::Shape &Shape)
const RegisterAggr & getLiveIns() const
std::set< NodeId > NodeSet
bool operator!=(uint64_t V1, const APInt &V2)
Representation of each machine instruction.
NodeId getReachingDef() const
static uint16_t set_kind(uint16_t A, uint16_t K)
PackedRegisterRef pack(RegisterRef RR)
constexpr bool any() const
static bool IsCode(const NodeAddr< NodeBase *> BA)
NodeBase * ptr(NodeId N) const
void push(NodeAddr< DefNode *> DA)
PackedRegisterRef pack(RegisterRef RR) const
Print(const T &x, const DataFlowGraph &g)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBasicBlock * getCode() const
This class implements an extremely fast bulk output stream that can only output to a stream...
static bool IsDef(const NodeAddr< NodeBase *> BA)
bool operator==(uint64_t V1, const APInt &V2)
NodeId getSibling() const
static bool IsRef(const NodeAddr< NodeBase *> BA)
NodeAddr< RefNode * > getNextRef(RegisterRef RR, Predicate P, bool NextOnly, const DataFlowGraph &G)
std::unordered_map< RegisterId, DefStack > DefStackMap
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void setReachedUse(NodeId U)
uint32_t getIndexForLaneMask(LaneBitmask LM)
void setSibling(NodeId Sib)